1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77990 processor support - PFC hardware block.
5 * Copyright (C) 2018 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 * R-Car Gen3 processor support - PFC hardware block.
11 * Copyright (C) 2015 Renesas Electronics Corporation
17 #include <dm/pinctrl.h>
18 #include <linux/kernel.h>
22 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
23 SH_PFC_PIN_CFG_PULL_DOWN)
25 #define CPU_ALL_PORT(fn, sfx) \
26 PORT_GP_18(0, fn, sfx), \
27 PORT_GP_23(1, fn, sfx), \
28 PORT_GP_26(2, fn, sfx), \
29 PORT_GP_12(3, fn, sfx), \
30 PORT_GP_1(3, 12, fn, sfx), \
31 PORT_GP_1(3, 13, fn, sfx), \
32 PORT_GP_1(3, 14, fn, sfx), \
33 PORT_GP_1(3, 15, fn, sfx), \
34 PORT_GP_11(4, fn, sfx), \
35 PORT_GP_20(5, fn, sfx), \
36 PORT_GP_18(6, fn, sfx)
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
43 #define GPSR0_17 F_(SDA4, IP7_27_24)
44 #define GPSR0_16 F_(SCL4, IP7_23_20)
45 #define GPSR0_15 F_(D15, IP7_19_16)
46 #define GPSR0_14 F_(D14, IP7_15_12)
47 #define GPSR0_13 F_(D13, IP7_11_8)
48 #define GPSR0_12 F_(D12, IP7_7_4)
49 #define GPSR0_11 F_(D11, IP7_3_0)
50 #define GPSR0_10 F_(D10, IP6_31_28)
51 #define GPSR0_9 F_(D9, IP6_27_24)
52 #define GPSR0_8 F_(D8, IP6_23_20)
53 #define GPSR0_7 F_(D7, IP6_19_16)
54 #define GPSR0_6 F_(D6, IP6_15_12)
55 #define GPSR0_5 F_(D5, IP6_11_8)
56 #define GPSR0_4 F_(D4, IP6_7_4)
57 #define GPSR0_3 F_(D3, IP6_3_0)
58 #define GPSR0_2 F_(D2, IP5_31_28)
59 #define GPSR0_1 F_(D1, IP5_27_24)
60 #define GPSR0_0 F_(D0, IP5_23_20)
63 #define GPSR1_22 F_(WE0_N, IP5_19_16)
64 #define GPSR1_21 F_(CS0_N, IP5_15_12)
65 #define GPSR1_20 FM(CLKOUT)
66 #define GPSR1_19 F_(A19, IP5_11_8)
67 #define GPSR1_18 F_(A18, IP5_7_4)
68 #define GPSR1_17 F_(A17, IP5_3_0)
69 #define GPSR1_16 F_(A16, IP4_31_28)
70 #define GPSR1_15 F_(A15, IP4_27_24)
71 #define GPSR1_14 F_(A14, IP4_23_20)
72 #define GPSR1_13 F_(A13, IP4_19_16)
73 #define GPSR1_12 F_(A12, IP4_15_12)
74 #define GPSR1_11 F_(A11, IP4_11_8)
75 #define GPSR1_10 F_(A10, IP4_7_4)
76 #define GPSR1_9 F_(A9, IP4_3_0)
77 #define GPSR1_8 F_(A8, IP3_31_28)
78 #define GPSR1_7 F_(A7, IP3_27_24)
79 #define GPSR1_6 F_(A6, IP3_23_20)
80 #define GPSR1_5 F_(A5, IP3_19_16)
81 #define GPSR1_4 F_(A4, IP3_15_12)
82 #define GPSR1_3 F_(A3, IP3_11_8)
83 #define GPSR1_2 F_(A2, IP3_7_4)
84 #define GPSR1_1 F_(A1, IP3_3_0)
85 #define GPSR1_0 F_(A0, IP2_31_28)
88 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
89 #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
90 #define GPSR2_23 F_(RD_N, IP2_19_16)
91 #define GPSR2_22 F_(BS_N, IP2_15_12)
92 #define GPSR2_21 FM(AVB_PHY_INT)
93 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
94 #define GPSR2_19 FM(AVB_RD3)
95 #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
96 #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
97 #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
98 #define GPSR2_15 FM(AVB_RXC)
99 #define GPSR2_14 FM(AVB_RX_CTL)
100 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
101 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
102 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
103 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
104 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
105 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
106 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
107 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
108 #define GPSR2_5 FM(QSPI0_SSL)
109 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
110 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
111 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
112 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
113 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
116 #define GPSR3_15 F_(SD1_WP, IP11_7_4)
117 #define GPSR3_14 F_(SD1_CD, IP11_3_0)
118 #define GPSR3_13 F_(SD0_WP, IP10_31_28)
119 #define GPSR3_12 F_(SD0_CD, IP10_27_24)
120 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
121 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
122 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
123 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
124 #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
125 #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
126 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
127 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
128 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
129 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
130 #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
131 #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
134 #define GPSR4_10 F_(SD3_DS, IP10_23_20)
135 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
136 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
137 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
138 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
139 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
140 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
141 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
142 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
143 #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
144 #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
147 #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
148 #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
149 #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
150 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
151 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
152 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
153 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
154 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
155 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
156 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
157 #define GPSR5_9 F_(RX2_A, IP12_15_12)
158 #define GPSR5_8 F_(TX2_A, IP12_11_8)
159 #define GPSR5_7 F_(SCK2_A, IP12_7_4)
160 #define GPSR5_6 F_(TX1, IP12_3_0)
161 #define GPSR5_5 F_(RX1, IP11_31_28)
162 #define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
163 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
164 #define GPSR5_2 F_(TX0_A, IP11_15_12)
165 #define GPSR5_1 F_(RX0_A, IP11_11_8)
166 #define GPSR5_0 F_(SCK0_A, IP11_27_24)
169 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
170 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
171 #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
172 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
173 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
174 #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
175 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
176 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
177 #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
178 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
179 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
180 #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
181 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
182 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
183 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
184 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
185 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
186 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
188 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
189 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
223 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
257 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB1_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
291 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define PINMUX_GPSR \
338 GPSR1_19 GPSR2_19 GPSR5_19 \
339 GPSR1_18 GPSR2_18 GPSR5_18 \
340 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
341 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
342 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
343 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
344 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
345 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
346 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
347 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
348 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
349 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
350 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
351 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
352 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
353 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
354 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
355 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
356 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
357 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
359 #define PINMUX_IPSR \
361 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
362 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
363 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
364 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
365 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
366 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
367 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
368 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
370 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
371 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
372 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
373 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
374 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
375 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
376 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
377 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
379 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
380 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
381 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
382 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
383 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
384 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
385 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
386 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
388 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
389 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
390 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
391 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
392 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
393 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
394 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
395 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
397 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
398 #define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0)
399 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
400 #define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0)
401 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
402 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
403 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
404 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
405 #define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3) FM(SEL_I2C1_4) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
408 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
409 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
410 #define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0)
411 #define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0)
412 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
413 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
414 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
415 #define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0)
416 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
417 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
418 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
419 #define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0)
421 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
422 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
423 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
424 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
425 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
426 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
427 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
428 #define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
431 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
432 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
433 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
434 #define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0)
435 #define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
436 #define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0)
437 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
438 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
439 #define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0)
440 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
442 #define PINMUX_MOD_SELS \
445 MOD_SEL0_30_29 MOD_SEL1_30 \
447 MOD_SEL0_28 MOD_SEL1_28 \
450 MOD_SEL0_25 MOD_SEL1_25 \
451 MOD_SEL0_24 MOD_SEL1_24_23_22 \
454 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
455 MOD_SEL0_19_18_17 MOD_SEL1_18 \
457 MOD_SEL0_16 MOD_SEL1_16 \
458 MOD_SEL0_15 MOD_SEL1_15 \
459 MOD_SEL0_14 MOD_SEL1_14_13 \
465 MOD_SEL0_8 MOD_SEL1_8 \
466 MOD_SEL0_7 MOD_SEL1_7 \
467 MOD_SEL0_6_5 MOD_SEL1_6_5 \
468 MOD_SEL0_4 MOD_SEL1_4 \
474 * These pins are not able to be muxed but have other properties
475 * that can be set, such as pull-up/pull-down enable.
477 #define PINMUX_STATIC \
478 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
480 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
492 #define FM(x) FN_##x,
493 PINMUX_FUNCTION_BEGIN,
503 #define FM(x) x##_MARK,
514 static const u16 pinmux_data[] = {
515 PINMUX_DATA_GP_ALL(),
517 PINMUX_SINGLE(CLKOUT),
518 PINMUX_SINGLE(AVB_PHY_INT),
519 PINMUX_SINGLE(AVB_RD3),
520 PINMUX_SINGLE(AVB_RXC),
521 PINMUX_SINGLE(AVB_RX_CTL),
522 PINMUX_SINGLE(QSPI0_SSL),
525 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
526 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
528 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
529 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
531 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
532 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
534 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
535 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
537 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
538 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
540 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
541 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
542 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
543 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
545 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
546 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
547 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
548 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
550 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
551 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
552 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
553 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
556 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
557 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
558 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
559 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
561 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
562 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
563 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
564 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
566 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
567 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
568 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
569 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
571 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
572 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
573 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
574 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
576 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
577 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
578 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
579 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
581 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
583 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
585 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
588 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
590 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
592 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
594 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
595 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
596 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
597 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
598 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
599 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
601 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
602 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
603 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
604 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
605 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
606 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
607 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
609 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
610 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
611 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
612 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
613 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
614 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
615 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
617 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
618 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
619 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
620 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
621 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
622 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
624 PINMUX_IPSR_GPSR(IP2_31_28, A0),
625 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
626 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
627 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
628 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
629 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
630 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
631 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
632 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
635 PINMUX_IPSR_GPSR(IP3_3_0, A1),
636 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
637 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
638 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
639 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
640 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
641 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
642 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
643 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
645 PINMUX_IPSR_GPSR(IP3_7_4, A2),
646 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
647 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
648 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
649 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
650 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
651 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
652 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
654 PINMUX_IPSR_GPSR(IP3_11_8, A3),
655 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
656 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
657 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
658 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
659 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
660 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
661 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
663 PINMUX_IPSR_GPSR(IP3_15_12, A4),
664 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
665 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
666 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
667 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
668 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
669 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
671 PINMUX_IPSR_GPSR(IP3_19_16, A5),
672 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
673 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
674 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
675 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
676 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
677 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
679 PINMUX_IPSR_GPSR(IP3_23_20, A6),
680 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
681 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
682 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
683 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
685 PINMUX_IPSR_GPSR(IP3_27_24, A7),
686 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
687 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
688 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
689 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
691 PINMUX_IPSR_GPSR(IP3_31_28, A8),
692 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
693 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
694 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
695 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
696 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
697 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
698 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
701 PINMUX_IPSR_GPSR(IP4_3_0, A9),
702 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
703 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
704 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
705 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
706 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
707 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
709 PINMUX_IPSR_GPSR(IP4_7_4, A10),
710 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
711 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
712 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
713 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
714 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
715 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
716 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
718 PINMUX_IPSR_GPSR(IP4_11_8, A11),
719 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
720 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
721 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
722 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
723 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
724 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
726 PINMUX_IPSR_GPSR(IP4_15_12, A12),
727 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
728 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
729 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
730 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
731 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
732 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
734 PINMUX_IPSR_GPSR(IP4_19_16, A13),
735 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
736 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
737 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
738 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
739 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
740 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
742 PINMUX_IPSR_GPSR(IP4_23_20, A14),
743 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
744 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
745 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
746 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
747 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
748 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
750 PINMUX_IPSR_GPSR(IP4_27_24, A15),
751 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
752 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
753 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
754 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
755 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
756 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
758 PINMUX_IPSR_GPSR(IP4_31_28, A16),
759 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
760 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
761 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
762 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
763 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
764 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
767 PINMUX_IPSR_GPSR(IP5_3_0, A17),
768 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
769 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
770 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
771 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
772 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
774 PINMUX_IPSR_GPSR(IP5_7_4, A18),
775 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
776 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
777 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
778 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
779 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
780 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
782 PINMUX_IPSR_GPSR(IP5_11_8, A19),
783 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
784 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
785 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
786 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
787 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
788 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
790 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
791 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
792 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
793 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
794 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
796 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
797 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
798 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
799 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
800 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
802 PINMUX_IPSR_GPSR(IP5_23_20, D0),
803 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
804 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
805 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
806 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
808 PINMUX_IPSR_GPSR(IP5_27_24, D1),
809 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
810 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
811 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
812 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
813 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
814 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
815 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
817 PINMUX_IPSR_GPSR(IP5_31_28, D2),
818 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
819 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
820 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
821 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
822 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
823 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
826 PINMUX_IPSR_GPSR(IP6_3_0, D3),
827 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
828 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
829 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
830 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
831 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
832 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
834 PINMUX_IPSR_GPSR(IP6_7_4, D4),
835 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
836 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
837 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
838 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
839 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
840 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
842 PINMUX_IPSR_GPSR(IP6_11_8, D5),
843 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
844 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
845 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
846 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
847 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
849 PINMUX_IPSR_GPSR(IP6_15_12, D6),
850 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
851 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
852 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
853 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
854 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
856 PINMUX_IPSR_GPSR(IP6_19_16, D7),
857 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
858 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
859 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
860 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
861 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
863 PINMUX_IPSR_GPSR(IP6_23_20, D8),
864 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
865 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
866 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
867 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
868 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
869 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
870 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
872 PINMUX_IPSR_GPSR(IP6_27_24, D9),
873 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
874 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
875 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
876 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
877 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
878 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
880 PINMUX_IPSR_GPSR(IP6_31_28, D10),
881 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
882 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
883 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
884 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
885 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
886 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
889 PINMUX_IPSR_GPSR(IP7_3_0, D11),
890 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
891 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
892 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
893 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
894 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
895 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
897 PINMUX_IPSR_GPSR(IP7_7_4, D12),
898 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
899 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
900 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
901 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
902 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
904 PINMUX_IPSR_GPSR(IP7_11_8, D13),
905 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
906 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
907 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
908 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
909 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
910 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
912 PINMUX_IPSR_GPSR(IP7_15_12, D14),
913 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
914 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
915 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
916 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
917 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
919 PINMUX_IPSR_GPSR(IP7_19_16, D15),
920 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
921 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
922 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
923 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
924 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
926 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
927 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
928 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
929 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
930 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
931 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
933 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
934 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
935 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
936 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
937 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
939 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
940 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
941 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
942 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
943 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
944 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
947 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
948 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
949 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
950 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
952 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
953 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
954 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
955 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
957 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
958 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
959 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
960 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
961 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
963 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
964 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
965 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
966 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
967 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
969 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
970 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
971 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
972 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
973 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
974 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
976 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
977 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
979 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
980 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
982 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
983 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
986 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
987 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
989 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
990 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
992 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
993 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
995 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
996 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
998 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
999 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
1001 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
1002 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
1004 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
1005 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
1007 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1008 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1011 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1012 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1014 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1015 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1017 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1018 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1020 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1021 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1023 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1024 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1026 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1027 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1029 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1030 PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
1031 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1032 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1033 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1034 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1035 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1036 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1038 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1039 PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
1040 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1041 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1042 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1043 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1044 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1045 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1048 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1049 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
1050 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1051 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1052 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1054 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1055 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
1056 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1057 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1058 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1060 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1061 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1062 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1063 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1064 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1066 PINMUX_IPSR_GPSR(IP11_15_12, TX0_A),
1067 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1068 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1069 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1070 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1072 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1073 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
1074 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1075 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1076 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1077 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1079 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
1080 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
1081 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1082 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1083 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1084 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1086 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1087 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1088 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1089 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1090 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1091 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1092 PINMUX_IPSR_GPSR(IP11_27_24, USB1_ID),
1094 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1095 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1096 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1097 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1100 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1101 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1102 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1103 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1105 PINMUX_IPSR_GPSR(IP12_7_4, SCK2_A),
1106 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1107 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1108 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1109 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1110 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1111 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1113 PINMUX_IPSR_GPSR(IP12_11_8, TX2_A),
1114 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1115 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1116 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1117 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1118 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1120 PINMUX_IPSR_GPSR(IP12_15_12, RX2_A),
1121 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1122 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1123 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1124 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1125 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1127 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1128 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1130 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1131 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1132 PINMUX_IPSR_GPSR(IP12_23_20, TX2_B),
1134 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1135 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1136 PINMUX_IPSR_GPSR(IP12_27_24, RX2_B),
1138 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1139 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1140 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1143 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1144 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1145 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1146 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1147 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1148 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1150 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1151 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1152 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1153 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1154 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1155 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1157 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1158 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1159 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1161 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1162 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1163 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1164 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1165 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1166 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1168 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1169 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1170 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1171 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1172 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1173 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1175 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1176 PINMUX_IPSR_GPSR(IP13_23_20, TX0_B),
1177 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1178 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1180 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1182 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1185 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1187 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1188 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1189 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1191 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1192 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1193 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1194 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1196 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1197 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1199 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1200 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1202 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1203 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1204 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1205 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1207 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1208 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1209 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1211 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1212 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1213 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1214 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1215 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1218 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1219 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1220 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1221 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1223 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1224 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1225 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1226 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1228 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1229 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1230 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1231 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1232 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1233 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1235 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1236 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1237 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1238 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1239 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1240 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1241 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1243 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1244 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1245 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1246 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1247 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1248 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1249 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1251 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1253 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1254 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1256 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1257 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1260 * Static pins can not be muxed between different functions but
1261 * still needs a mark entry in the pinmux list. Add each static
1262 * pin to the list without an associated function. The sh-pfc
1263 * core will do the right thing and skip trying to mux then pin
1264 * while still applying configuration to it
1266 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1272 * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
1273 * Physical layout rows: A - AE, cols: 1 - 25.
1275 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1276 #define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
1277 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1278 #define PIN_NONE U16_MAX
1280 static const struct sh_pfc_pin pinmux_pins[] = {
1281 PINMUX_GPIO_GP_ALL(),
1284 * Pins not associated with a GPIO port.
1286 * The pin positions are different between different R8A77990
1287 * packages, all that is needed for the pfc driver is a unique
1288 * number for each pin. To this end use the pin layout from
1289 * R8A77990 to calculate a unique number for each pin.
1291 SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
1292 SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
1293 SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
1294 SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
1295 SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
1296 SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
1297 SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
1298 SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
1299 SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
1300 SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
1301 SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
1302 SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
1303 SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
1304 SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
1305 SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
1306 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
1309 /* - AUDIO CLOCK ------------------------------------------------------------ */
1310 static const unsigned int audio_clk_a_pins[] = {
1315 static const unsigned int audio_clk_a_mux[] = {
1319 static const unsigned int audio_clk_b_a_pins[] = {
1324 static const unsigned int audio_clk_b_a_mux[] = {
1328 static const unsigned int audio_clk_b_b_pins[] = {
1333 static const unsigned int audio_clk_b_b_mux[] = {
1337 static const unsigned int audio_clk_b_c_pins[] = {
1342 static const unsigned int audio_clk_b_c_mux[] = {
1346 static const unsigned int audio_clk_c_a_pins[] = {
1351 static const unsigned int audio_clk_c_a_mux[] = {
1355 static const unsigned int audio_clk_c_b_pins[] = {
1360 static const unsigned int audio_clk_c_b_mux[] = {
1364 static const unsigned int audio_clk_c_c_pins[] = {
1369 static const unsigned int audio_clk_c_c_mux[] = {
1373 static const unsigned int audio_clkout_a_pins[] = {
1378 static const unsigned int audio_clkout_a_mux[] = {
1379 AUDIO_CLKOUT_A_MARK,
1382 static const unsigned int audio_clkout_b_pins[] = {
1387 static const unsigned int audio_clkout_b_mux[] = {
1388 AUDIO_CLKOUT_B_MARK,
1391 static const unsigned int audio_clkout1_a_pins[] = {
1396 static const unsigned int audio_clkout1_a_mux[] = {
1397 AUDIO_CLKOUT1_A_MARK,
1400 static const unsigned int audio_clkout1_b_pins[] = {
1405 static const unsigned int audio_clkout1_b_mux[] = {
1406 AUDIO_CLKOUT1_B_MARK,
1409 static const unsigned int audio_clkout1_c_pins[] = {
1414 static const unsigned int audio_clkout1_c_mux[] = {
1415 AUDIO_CLKOUT1_C_MARK,
1418 static const unsigned int audio_clkout2_a_pins[] = {
1423 static const unsigned int audio_clkout2_a_mux[] = {
1424 AUDIO_CLKOUT2_A_MARK,
1427 static const unsigned int audio_clkout2_b_pins[] = {
1432 static const unsigned int audio_clkout2_b_mux[] = {
1433 AUDIO_CLKOUT2_B_MARK,
1436 static const unsigned int audio_clkout2_c_pins[] = {
1441 static const unsigned int audio_clkout2_c_mux[] = {
1442 AUDIO_CLKOUT2_C_MARK,
1445 static const unsigned int audio_clkout3_a_pins[] = {
1450 static const unsigned int audio_clkout3_a_mux[] = {
1451 AUDIO_CLKOUT3_A_MARK,
1454 static const unsigned int audio_clkout3_b_pins[] = {
1459 static const unsigned int audio_clkout3_b_mux[] = {
1460 AUDIO_CLKOUT3_B_MARK,
1463 static const unsigned int audio_clkout3_c_pins[] = {
1468 static const unsigned int audio_clkout3_c_mux[] = {
1469 AUDIO_CLKOUT3_C_MARK,
1472 /* - EtherAVB --------------------------------------------------------------- */
1473 static const unsigned int avb_link_pins[] = {
1478 static const unsigned int avb_link_mux[] = {
1482 static const unsigned int avb_magic_pins[] = {
1487 static const unsigned int avb_magic_mux[] = {
1491 static const unsigned int avb_phy_int_pins[] = {
1496 static const unsigned int avb_phy_int_mux[] = {
1500 static const unsigned int avb_mii_pins[] = {
1502 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1503 * AVB_RD1, AVB_RD2, AVB_RD3,
1506 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1507 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1511 static const unsigned int avb_mii_mux[] = {
1512 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1513 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1517 static const unsigned int avb_avtp_pps_pins[] = {
1522 static const unsigned int avb_avtp_pps_mux[] = {
1526 static const unsigned int avb_avtp_match_a_pins[] = {
1527 /* AVB_AVTP_MATCH_A */
1531 static const unsigned int avb_avtp_match_a_mux[] = {
1532 AVB_AVTP_MATCH_A_MARK,
1535 static const unsigned int avb_avtp_capture_a_pins[] = {
1536 /* AVB_AVTP_CAPTURE_A */
1540 static const unsigned int avb_avtp_capture_a_mux[] = {
1541 AVB_AVTP_CAPTURE_A_MARK,
1544 /* - CAN ------------------------------------------------------------------ */
1545 static const unsigned int can0_data_pins[] = {
1547 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1550 static const unsigned int can0_data_mux[] = {
1551 CAN0_TX_MARK, CAN0_RX_MARK,
1554 static const unsigned int can1_data_pins[] = {
1556 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1559 static const unsigned int can1_data_mux[] = {
1560 CAN1_TX_MARK, CAN1_RX_MARK,
1563 /* - CAN Clock -------------------------------------------------------------- */
1564 static const unsigned int can_clk_pins[] = {
1569 static const unsigned int can_clk_mux[] = {
1573 /* - CAN FD --------------------------------------------------------------- */
1574 static const unsigned int canfd0_data_pins[] = {
1576 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1579 static const unsigned int canfd0_data_mux[] = {
1580 CANFD0_TX_MARK, CANFD0_RX_MARK,
1583 static const unsigned int canfd1_data_pins[] = {
1585 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1588 static const unsigned int canfd1_data_mux[] = {
1589 CANFD1_TX_MARK, CANFD1_RX_MARK,
1592 /* - DRIF0 --------------------------------------------------------------- */
1593 static const unsigned int drif0_ctrl_a_pins[] = {
1595 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1598 static const unsigned int drif0_ctrl_a_mux[] = {
1599 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1602 static const unsigned int drif0_data0_a_pins[] = {
1607 static const unsigned int drif0_data0_a_mux[] = {
1611 static const unsigned int drif0_data1_a_pins[] = {
1616 static const unsigned int drif0_data1_a_mux[] = {
1620 static const unsigned int drif0_ctrl_b_pins[] = {
1622 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1625 static const unsigned int drif0_ctrl_b_mux[] = {
1626 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1629 static const unsigned int drif0_data0_b_pins[] = {
1634 static const unsigned int drif0_data0_b_mux[] = {
1638 static const unsigned int drif0_data1_b_pins[] = {
1643 static const unsigned int drif0_data1_b_mux[] = {
1647 /* - DRIF1 --------------------------------------------------------------- */
1648 static const unsigned int drif1_ctrl_pins[] = {
1650 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1653 static const unsigned int drif1_ctrl_mux[] = {
1654 RIF1_CLK_MARK, RIF1_SYNC_MARK,
1657 static const unsigned int drif1_data0_pins[] = {
1662 static const unsigned int drif1_data0_mux[] = {
1666 static const unsigned int drif1_data1_pins[] = {
1671 static const unsigned int drif1_data1_mux[] = {
1675 /* - DRIF2 --------------------------------------------------------------- */
1676 static const unsigned int drif2_ctrl_a_pins[] = {
1678 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1681 static const unsigned int drif2_ctrl_a_mux[] = {
1682 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1685 static const unsigned int drif2_data0_a_pins[] = {
1690 static const unsigned int drif2_data0_a_mux[] = {
1694 static const unsigned int drif2_data1_a_pins[] = {
1699 static const unsigned int drif2_data1_a_mux[] = {
1703 static const unsigned int drif2_ctrl_b_pins[] = {
1705 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1708 static const unsigned int drif2_ctrl_b_mux[] = {
1709 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1712 static const unsigned int drif2_data0_b_pins[] = {
1717 static const unsigned int drif2_data0_b_mux[] = {
1721 static const unsigned int drif2_data1_b_pins[] = {
1726 static const unsigned int drif2_data1_b_mux[] = {
1730 /* - DRIF3 --------------------------------------------------------------- */
1731 static const unsigned int drif3_ctrl_a_pins[] = {
1733 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1736 static const unsigned int drif3_ctrl_a_mux[] = {
1737 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1740 static const unsigned int drif3_data0_a_pins[] = {
1745 static const unsigned int drif3_data0_a_mux[] = {
1749 static const unsigned int drif3_data1_a_pins[] = {
1754 static const unsigned int drif3_data1_a_mux[] = {
1758 static const unsigned int drif3_ctrl_b_pins[] = {
1760 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1763 static const unsigned int drif3_ctrl_b_mux[] = {
1764 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1767 static const unsigned int drif3_data0_b_pins[] = {
1772 static const unsigned int drif3_data0_b_mux[] = {
1776 static const unsigned int drif3_data1_b_pins[] = {
1781 static const unsigned int drif3_data1_b_mux[] = {
1785 /* - DU --------------------------------------------------------------------- */
1786 static const unsigned int du_rgb666_pins[] = {
1787 /* R[7:2], G[7:2], B[7:2] */
1788 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1789 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1790 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1791 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1792 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1793 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1796 static const unsigned int du_rgb666_mux[] = {
1797 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1798 DU_DR3_MARK, DU_DR2_MARK,
1799 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1800 DU_DG3_MARK, DU_DG2_MARK,
1801 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1802 DU_DB3_MARK, DU_DB2_MARK,
1805 static const unsigned int du_rgb888_pins[] = {
1806 /* R[7:0], G[7:0], B[7:0] */
1807 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1808 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1809 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1810 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1811 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1812 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1813 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1814 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1815 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1818 static const unsigned int du_rgb888_mux[] = {
1819 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1820 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1821 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1822 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1823 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1824 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1827 static const unsigned int du_clk_out_0_pins[] = {
1832 static const unsigned int du_clk_out_0_mux[] = {
1836 static const unsigned int du_sync_pins[] = {
1838 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1841 static const unsigned int du_sync_mux[] = {
1842 DU_VSYNC_MARK, DU_HSYNC_MARK
1845 static const unsigned int du_cde_pins[] = {
1850 static const unsigned int du_cde_mux[] = {
1854 static const unsigned int du_disp_pins[] = {
1859 static const unsigned int du_disp_mux[] = {
1863 static const unsigned int du_disp_cde_pins[] = {
1868 static const unsigned int du_disp_cde_mux[] = {
1872 static const unsigned int du_clk_in_0_pins[] = {
1877 static const unsigned int du_clk_in_0_mux[] = {
1881 static const unsigned int du_clk_in_1_pins[] = {
1886 static const unsigned int du_clk_in_1_mux[] = {
1890 /* - HSCIF0 --------------------------------------------------*/
1891 static const unsigned int hscif0_data_a_pins[] = {
1893 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1896 static const unsigned int hscif0_data_a_mux[] = {
1897 HRX0_A_MARK, HTX0_A_MARK,
1900 static const unsigned int hscif0_clk_a_pins[] = {
1905 static const unsigned int hscif0_clk_a_mux[] = {
1909 static const unsigned int hscif0_ctrl_a_pins[] = {
1911 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1914 static const unsigned int hscif0_ctrl_a_mux[] = {
1915 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1918 static const unsigned int hscif0_data_b_pins[] = {
1920 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1923 static const unsigned int hscif0_data_b_mux[] = {
1924 HRX0_B_MARK, HTX0_B_MARK,
1927 static const unsigned int hscif0_clk_b_pins[] = {
1932 static const unsigned int hscif0_clk_b_mux[] = {
1936 /* - HSCIF1 ------------------------------------------------- */
1937 static const unsigned int hscif1_data_a_pins[] = {
1939 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1942 static const unsigned int hscif1_data_a_mux[] = {
1943 HRX1_A_MARK, HTX1_A_MARK,
1946 static const unsigned int hscif1_clk_a_pins[] = {
1951 static const unsigned int hscif1_clk_a_mux[] = {
1955 static const unsigned int hscif1_data_b_pins[] = {
1957 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1960 static const unsigned int hscif1_data_b_mux[] = {
1961 HRX1_B_MARK, HTX1_B_MARK,
1964 static const unsigned int hscif1_clk_b_pins[] = {
1969 static const unsigned int hscif1_clk_b_mux[] = {
1973 static const unsigned int hscif1_ctrl_b_pins[] = {
1975 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1978 static const unsigned int hscif1_ctrl_b_mux[] = {
1979 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1982 /* - HSCIF2 ------------------------------------------------- */
1983 static const unsigned int hscif2_data_a_pins[] = {
1985 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1988 static const unsigned int hscif2_data_a_mux[] = {
1989 HRX2_A_MARK, HTX2_A_MARK,
1992 static const unsigned int hscif2_clk_a_pins[] = {
1997 static const unsigned int hscif2_clk_a_mux[] = {
2001 static const unsigned int hscif2_ctrl_a_pins[] = {
2003 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2006 static const unsigned int hscif2_ctrl_a_mux[] = {
2007 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2010 static const unsigned int hscif2_data_b_pins[] = {
2012 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2015 static const unsigned int hscif2_data_b_mux[] = {
2016 HRX2_B_MARK, HTX2_B_MARK,
2019 /* - HSCIF3 ------------------------------------------------*/
2020 static const unsigned int hscif3_data_a_pins[] = {
2022 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2025 static const unsigned int hscif3_data_a_mux[] = {
2026 HRX3_A_MARK, HTX3_A_MARK,
2029 static const unsigned int hscif3_data_b_pins[] = {
2031 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2034 static const unsigned int hscif3_data_b_mux[] = {
2035 HRX3_B_MARK, HTX3_B_MARK,
2038 static const unsigned int hscif3_clk_b_pins[] = {
2043 static const unsigned int hscif3_clk_b_mux[] = {
2047 static const unsigned int hscif3_data_c_pins[] = {
2049 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2052 static const unsigned int hscif3_data_c_mux[] = {
2053 HRX3_C_MARK, HTX3_C_MARK,
2056 static const unsigned int hscif3_clk_c_pins[] = {
2061 static const unsigned int hscif3_clk_c_mux[] = {
2065 static const unsigned int hscif3_ctrl_c_pins[] = {
2067 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2070 static const unsigned int hscif3_ctrl_c_mux[] = {
2071 HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2074 static const unsigned int hscif3_data_d_pins[] = {
2076 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0),
2079 static const unsigned int hscif3_data_d_mux[] = {
2080 HRX3_D_MARK, HTX3_D_MARK,
2083 static const unsigned int hscif3_data_e_pins[] = {
2085 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2088 static const unsigned int hscif3_data_e_mux[] = {
2089 HRX3_E_MARK, HTX3_E_MARK,
2092 static const unsigned int hscif3_ctrl_e_pins[] = {
2094 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2097 static const unsigned int hscif3_ctrl_e_mux[] = {
2098 HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2101 /* - HSCIF4 -------------------------------------------------- */
2102 static const unsigned int hscif4_data_a_pins[] = {
2104 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2107 static const unsigned int hscif4_data_a_mux[] = {
2108 HRX4_A_MARK, HTX4_A_MARK,
2111 static const unsigned int hscif4_clk_a_pins[] = {
2116 static const unsigned int hscif4_clk_a_mux[] = {
2120 static const unsigned int hscif4_ctrl_a_pins[] = {
2122 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2125 static const unsigned int hscif4_ctrl_a_mux[] = {
2126 HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2129 static const unsigned int hscif4_data_b_pins[] = {
2131 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2134 static const unsigned int hscif4_data_b_mux[] = {
2135 HRX4_B_MARK, HTX4_B_MARK,
2138 static const unsigned int hscif4_clk_b_pins[] = {
2143 static const unsigned int hscif4_clk_b_mux[] = {
2147 static const unsigned int hscif4_data_c_pins[] = {
2149 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2152 static const unsigned int hscif4_data_c_mux[] = {
2153 HRX4_C_MARK, HTX4_C_MARK,
2156 static const unsigned int hscif4_data_d_pins[] = {
2158 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2161 static const unsigned int hscif4_data_d_mux[] = {
2162 HRX4_D_MARK, HTX4_D_MARK,
2165 static const unsigned int hscif4_data_e_pins[] = {
2167 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2170 static const unsigned int hscif4_data_e_mux[] = {
2171 HRX4_E_MARK, HTX4_E_MARK,
2174 /* - I2C -------------------------------------------------------------------- */
2175 static const unsigned int i2c1_a_pins[] = {
2177 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2180 static const unsigned int i2c1_a_mux[] = {
2181 SCL1_A_MARK, SDA1_A_MARK,
2184 static const unsigned int i2c1_b_pins[] = {
2186 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2189 static const unsigned int i2c1_b_mux[] = {
2190 SCL1_B_MARK, SDA1_B_MARK,
2193 static const unsigned int i2c1_c_pins[] = {
2195 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2198 static const unsigned int i2c1_c_mux[] = {
2199 SCL1_C_MARK, SDA1_C_MARK,
2202 static const unsigned int i2c1_d_pins[] = {
2204 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2207 static const unsigned int i2c1_d_mux[] = {
2208 SCL1_D_MARK, SDA1_D_MARK,
2211 static const unsigned int i2c2_a_pins[] = {
2213 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2216 static const unsigned int i2c2_a_mux[] = {
2217 SCL2_A_MARK, SDA2_A_MARK,
2220 static const unsigned int i2c2_b_pins[] = {
2222 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2225 static const unsigned int i2c2_b_mux[] = {
2226 SCL2_B_MARK, SDA2_B_MARK,
2229 static const unsigned int i2c2_c_pins[] = {
2231 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2234 static const unsigned int i2c2_c_mux[] = {
2235 SCL2_C_MARK, SDA2_C_MARK,
2238 static const unsigned int i2c2_d_pins[] = {
2240 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2243 static const unsigned int i2c2_d_mux[] = {
2244 SCL2_D_MARK, SDA2_D_MARK,
2247 static const unsigned int i2c2_e_pins[] = {
2249 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2252 static const unsigned int i2c2_e_mux[] = {
2253 SCL2_E_MARK, SDA2_E_MARK,
2256 static const unsigned int i2c4_pins[] = {
2258 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2261 static const unsigned int i2c4_mux[] = {
2262 SCL4_MARK, SDA4_MARK,
2265 static const unsigned int i2c5_pins[] = {
2267 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2270 static const unsigned int i2c5_mux[] = {
2271 SCL5_MARK, SDA5_MARK,
2274 static const unsigned int i2c6_a_pins[] = {
2276 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2279 static const unsigned int i2c6_a_mux[] = {
2280 SCL6_A_MARK, SDA6_A_MARK,
2283 static const unsigned int i2c6_b_pins[] = {
2285 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2288 static const unsigned int i2c6_b_mux[] = {
2289 SCL6_B_MARK, SDA6_B_MARK,
2292 static const unsigned int i2c7_a_pins[] = {
2294 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2297 static const unsigned int i2c7_a_mux[] = {
2298 SCL7_A_MARK, SDA7_A_MARK,
2301 static const unsigned int i2c7_b_pins[] = {
2303 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2306 static const unsigned int i2c7_b_mux[] = {
2307 SCL7_B_MARK, SDA7_B_MARK,
2310 /* - INTC-EX ---------------------------------------------------------------- */
2311 static const unsigned int intc_ex_irq0_pins[] = {
2316 static const unsigned int intc_ex_irq0_mux[] = {
2320 /* - MSIOF0 ----------------------------------------------------------------- */
2321 static const unsigned int msiof0_clk_pins[] = {
2326 static const unsigned int msiof0_clk_mux[] = {
2330 static const unsigned int msiof0_sync_pins[] = {
2335 static const unsigned int msiof0_sync_mux[] = {
2339 static const unsigned int msiof0_ss1_pins[] = {
2344 static const unsigned int msiof0_ss1_mux[] = {
2348 static const unsigned int msiof0_ss2_pins[] = {
2353 static const unsigned int msiof0_ss2_mux[] = {
2357 static const unsigned int msiof0_txd_pins[] = {
2362 static const unsigned int msiof0_txd_mux[] = {
2366 static const unsigned int msiof0_rxd_pins[] = {
2371 static const unsigned int msiof0_rxd_mux[] = {
2375 /* - MSIOF1 ----------------------------------------------------------------- */
2376 static const unsigned int msiof1_clk_pins[] = {
2381 static const unsigned int msiof1_clk_mux[] = {
2385 static const unsigned int msiof1_sync_pins[] = {
2390 static const unsigned int msiof1_sync_mux[] = {
2394 static const unsigned int msiof1_ss1_pins[] = {
2399 static const unsigned int msiof1_ss1_mux[] = {
2403 static const unsigned int msiof1_ss2_pins[] = {
2408 static const unsigned int msiof1_ss2_mux[] = {
2412 static const unsigned int msiof1_txd_pins[] = {
2417 static const unsigned int msiof1_txd_mux[] = {
2421 static const unsigned int msiof1_rxd_pins[] = {
2426 static const unsigned int msiof1_rxd_mux[] = {
2430 /* - MSIOF2 ----------------------------------------------------------------- */
2431 static const unsigned int msiof2_clk_a_pins[] = {
2436 static const unsigned int msiof2_clk_a_mux[] = {
2440 static const unsigned int msiof2_sync_a_pins[] = {
2445 static const unsigned int msiof2_sync_a_mux[] = {
2449 static const unsigned int msiof2_ss1_a_pins[] = {
2454 static const unsigned int msiof2_ss1_a_mux[] = {
2458 static const unsigned int msiof2_ss2_a_pins[] = {
2463 static const unsigned int msiof2_ss2_a_mux[] = {
2467 static const unsigned int msiof2_txd_a_pins[] = {
2472 static const unsigned int msiof2_txd_a_mux[] = {
2476 static const unsigned int msiof2_rxd_a_pins[] = {
2481 static const unsigned int msiof2_rxd_a_mux[] = {
2485 static const unsigned int msiof2_clk_b_pins[] = {
2490 static const unsigned int msiof2_clk_b_mux[] = {
2494 static const unsigned int msiof2_sync_b_pins[] = {
2499 static const unsigned int msiof2_sync_b_mux[] = {
2503 static const unsigned int msiof2_ss1_b_pins[] = {
2508 static const unsigned int msiof2_ss1_b_mux[] = {
2512 static const unsigned int msiof2_ss2_b_pins[] = {
2517 static const unsigned int msiof2_ss2_b_mux[] = {
2521 static const unsigned int msiof2_txd_b_pins[] = {
2526 static const unsigned int msiof2_txd_b_mux[] = {
2530 static const unsigned int msiof2_rxd_b_pins[] = {
2535 static const unsigned int msiof2_rxd_b_mux[] = {
2539 /* - MSIOF3 ----------------------------------------------------------------- */
2540 static const unsigned int msiof3_clk_a_pins[] = {
2545 static const unsigned int msiof3_clk_a_mux[] = {
2549 static const unsigned int msiof3_sync_a_pins[] = {
2554 static const unsigned int msiof3_sync_a_mux[] = {
2558 static const unsigned int msiof3_ss1_a_pins[] = {
2563 static const unsigned int msiof3_ss1_a_mux[] = {
2567 static const unsigned int msiof3_ss2_a_pins[] = {
2572 static const unsigned int msiof3_ss2_a_mux[] = {
2576 static const unsigned int msiof3_txd_a_pins[] = {
2581 static const unsigned int msiof3_txd_a_mux[] = {
2585 static const unsigned int msiof3_rxd_a_pins[] = {
2590 static const unsigned int msiof3_rxd_a_mux[] = {
2594 static const unsigned int msiof3_clk_b_pins[] = {
2599 static const unsigned int msiof3_clk_b_mux[] = {
2603 static const unsigned int msiof3_sync_b_pins[] = {
2608 static const unsigned int msiof3_sync_b_mux[] = {
2612 static const unsigned int msiof3_ss1_b_pins[] = {
2617 static const unsigned int msiof3_ss1_b_mux[] = {
2621 static const unsigned int msiof3_txd_b_pins[] = {
2626 static const unsigned int msiof3_txd_b_mux[] = {
2630 static const unsigned int msiof3_rxd_b_pins[] = {
2635 static const unsigned int msiof3_rxd_b_mux[] = {
2639 /* - PWM0 --------------------------------------------------------------------*/
2640 static const unsigned int pwm0_a_pins[] = {
2645 static const unsigned int pwm0_a_mux[] = {
2649 static const unsigned int pwm0_b_pins[] = {
2654 static const unsigned int pwm0_b_mux[] = {
2658 /* - PWM1 --------------------------------------------------------------------*/
2659 static const unsigned int pwm1_a_pins[] = {
2664 static const unsigned int pwm1_a_mux[] = {
2668 static const unsigned int pwm1_b_pins[] = {
2673 static const unsigned int pwm1_b_mux[] = {
2677 /* - PWM2 --------------------------------------------------------------------*/
2678 static const unsigned int pwm2_a_pins[] = {
2683 static const unsigned int pwm2_a_mux[] = {
2687 static const unsigned int pwm2_b_pins[] = {
2692 static const unsigned int pwm2_b_mux[] = {
2696 static const unsigned int pwm2_c_pins[] = {
2701 static const unsigned int pwm2_c_mux[] = {
2705 /* - PWM3 --------------------------------------------------------------------*/
2706 static const unsigned int pwm3_a_pins[] = {
2711 static const unsigned int pwm3_a_mux[] = {
2715 static const unsigned int pwm3_b_pins[] = {
2720 static const unsigned int pwm3_b_mux[] = {
2724 static const unsigned int pwm3_c_pins[] = {
2729 static const unsigned int pwm3_c_mux[] = {
2733 /* - PWM4 --------------------------------------------------------------------*/
2734 static const unsigned int pwm4_a_pins[] = {
2739 static const unsigned int pwm4_a_mux[] = {
2743 static const unsigned int pwm4_b_pins[] = {
2748 static const unsigned int pwm4_b_mux[] = {
2752 /* - PWM5 --------------------------------------------------------------------*/
2753 static const unsigned int pwm5_a_pins[] = {
2758 static const unsigned int pwm5_a_mux[] = {
2762 static const unsigned int pwm5_b_pins[] = {
2767 static const unsigned int pwm5_b_mux[] = {
2771 /* - PWM6 --------------------------------------------------------------------*/
2772 static const unsigned int pwm6_a_pins[] = {
2777 static const unsigned int pwm6_a_mux[] = {
2781 static const unsigned int pwm6_b_pins[] = {
2786 static const unsigned int pwm6_b_mux[] = {
2790 /* - SCIF0 ------------------------------------------------------------------ */
2791 static const unsigned int scif0_data_a_pins[] = {
2793 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2796 static const unsigned int scif0_data_a_mux[] = {
2797 RX0_A_MARK, TX0_A_MARK,
2800 static const unsigned int scif0_clk_a_pins[] = {
2805 static const unsigned int scif0_clk_a_mux[] = {
2809 static const unsigned int scif0_ctrl_a_pins[] = {
2811 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2814 static const unsigned int scif0_ctrl_a_mux[] = {
2815 RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
2818 static const unsigned int scif0_data_b_pins[] = {
2820 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2823 static const unsigned int scif0_data_b_mux[] = {
2824 RX0_B_MARK, TX0_B_MARK,
2827 static const unsigned int scif0_clk_b_pins[] = {
2832 static const unsigned int scif0_clk_b_mux[] = {
2836 /* - SCIF1 ------------------------------------------------------------------ */
2837 static const unsigned int scif1_data_pins[] = {
2839 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2842 static const unsigned int scif1_data_mux[] = {
2846 static const unsigned int scif1_clk_pins[] = {
2851 static const unsigned int scif1_clk_mux[] = {
2855 static const unsigned int scif1_ctrl_pins[] = {
2857 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2860 static const unsigned int scif1_ctrl_mux[] = {
2861 RTS1_N_TANS_MARK, CTS1_N_MARK,
2864 /* - SCIF2 ------------------------------------------------------------------ */
2865 static const unsigned int scif2_data_a_pins[] = {
2867 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2870 static const unsigned int scif2_data_a_mux[] = {
2871 RX2_A_MARK, TX2_A_MARK,
2874 static const unsigned int scif2_clk_a_pins[] = {
2879 static const unsigned int scif2_clk_a_mux[] = {
2883 static const unsigned int scif2_data_b_pins[] = {
2885 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2888 static const unsigned int scif2_data_b_mux[] = {
2889 RX2_B_MARK, TX2_B_MARK,
2892 /* - SCIF3 ------------------------------------------------------------------ */
2893 static const unsigned int scif3_data_a_pins[] = {
2895 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2898 static const unsigned int scif3_data_a_mux[] = {
2899 RX3_A_MARK, TX3_A_MARK,
2902 static const unsigned int scif3_clk_a_pins[] = {
2907 static const unsigned int scif3_clk_a_mux[] = {
2911 static const unsigned int scif3_ctrl_a_pins[] = {
2913 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
2916 static const unsigned int scif3_ctrl_a_mux[] = {
2917 RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
2920 static const unsigned int scif3_data_b_pins[] = {
2922 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2925 static const unsigned int scif3_data_b_mux[] = {
2926 RX3_B_MARK, TX3_B_MARK,
2929 static const unsigned int scif3_data_c_pins[] = {
2931 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2934 static const unsigned int scif3_data_c_mux[] = {
2935 RX3_C_MARK, TX3_C_MARK,
2938 static const unsigned int scif3_clk_c_pins[] = {
2943 static const unsigned int scif3_clk_c_mux[] = {
2947 /* - SCIF4 ------------------------------------------------------------------ */
2948 static const unsigned int scif4_data_a_pins[] = {
2950 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2953 static const unsigned int scif4_data_a_mux[] = {
2954 RX4_A_MARK, TX4_A_MARK,
2957 static const unsigned int scif4_clk_a_pins[] = {
2962 static const unsigned int scif4_clk_a_mux[] = {
2966 static const unsigned int scif4_ctrl_a_pins[] = {
2968 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
2971 static const unsigned int scif4_ctrl_a_mux[] = {
2972 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2975 static const unsigned int scif4_data_b_pins[] = {
2977 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
2980 static const unsigned int scif4_data_b_mux[] = {
2981 RX4_B_MARK, TX4_B_MARK,
2984 static const unsigned int scif4_clk_b_pins[] = {
2989 static const unsigned int scif4_clk_b_mux[] = {
2993 static const unsigned int scif4_data_c_pins[] = {
2995 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
2998 static const unsigned int scif4_data_c_mux[] = {
2999 RX4_C_MARK, TX4_C_MARK,
3002 static const unsigned int scif4_ctrl_c_pins[] = {
3004 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3007 static const unsigned int scif4_ctrl_c_mux[] = {
3008 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3011 /* - SCIF5 ------------------------------------------------------------------ */
3012 static const unsigned int scif5_data_a_pins[] = {
3014 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3017 static const unsigned int scif5_data_a_mux[] = {
3018 RX5_A_MARK, TX5_A_MARK,
3021 static const unsigned int scif5_clk_a_pins[] = {
3026 static const unsigned int scif5_clk_a_mux[] = {
3030 static const unsigned int scif5_data_b_pins[] = {
3032 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3035 static const unsigned int scif5_data_b_mux[] = {
3036 RX5_B_MARK, TX5_B_MARK,
3039 static const unsigned int scif5_data_c_pins[] = {
3041 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3044 static const unsigned int scif5_data_c_mux[] = {
3045 RX5_C_MARK, TX5_C_MARK,
3048 /* - SCIF Clock ------------------------------------------------------------- */
3049 static const unsigned int scif_clk_a_pins[] = {
3054 static const unsigned int scif_clk_a_mux[] = {
3058 static const unsigned int scif_clk_b_pins[] = {
3063 static const unsigned int scif_clk_b_mux[] = {
3067 /* - SDHI0 ------------------------------------------------------------------ */
3068 static const unsigned int sdhi0_data1_pins[] = {
3073 static const unsigned int sdhi0_data1_mux[] = {
3077 static const unsigned int sdhi0_data4_pins[] = {
3079 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3080 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3083 static const unsigned int sdhi0_data4_mux[] = {
3084 SD0_DAT0_MARK, SD0_DAT1_MARK,
3085 SD0_DAT2_MARK, SD0_DAT3_MARK,
3088 static const unsigned int sdhi0_ctrl_pins[] = {
3090 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3093 static const unsigned int sdhi0_ctrl_mux[] = {
3094 SD0_CLK_MARK, SD0_CMD_MARK,
3097 static const unsigned int sdhi0_cd_pins[] = {
3102 static const unsigned int sdhi0_cd_mux[] = {
3106 static const unsigned int sdhi0_wp_pins[] = {
3111 static const unsigned int sdhi0_wp_mux[] = {
3115 /* - SDHI1 ------------------------------------------------------------------ */
3116 static const unsigned int sdhi1_data1_pins[] = {
3121 static const unsigned int sdhi1_data1_mux[] = {
3125 static const unsigned int sdhi1_data4_pins[] = {
3127 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3128 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3131 static const unsigned int sdhi1_data4_mux[] = {
3132 SD1_DAT0_MARK, SD1_DAT1_MARK,
3133 SD1_DAT2_MARK, SD1_DAT3_MARK,
3136 static const unsigned int sdhi1_ctrl_pins[] = {
3138 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3141 static const unsigned int sdhi1_ctrl_mux[] = {
3142 SD1_CLK_MARK, SD1_CMD_MARK,
3145 static const unsigned int sdhi1_cd_pins[] = {
3150 static const unsigned int sdhi1_cd_mux[] = {
3154 static const unsigned int sdhi1_wp_pins[] = {
3159 static const unsigned int sdhi1_wp_mux[] = {
3163 /* - SDHI3 ------------------------------------------------------------------ */
3164 static const unsigned int sdhi3_data1_pins[] = {
3169 static const unsigned int sdhi3_data1_mux[] = {
3173 static const unsigned int sdhi3_data4_pins[] = {
3175 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3176 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3179 static const unsigned int sdhi3_data4_mux[] = {
3180 SD3_DAT0_MARK, SD3_DAT1_MARK,
3181 SD3_DAT2_MARK, SD3_DAT3_MARK,
3184 static const unsigned int sdhi3_data8_pins[] = {
3186 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3187 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3188 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3189 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3192 static const unsigned int sdhi3_data8_mux[] = {
3193 SD3_DAT0_MARK, SD3_DAT1_MARK,
3194 SD3_DAT2_MARK, SD3_DAT3_MARK,
3195 SD3_DAT4_MARK, SD3_DAT5_MARK,
3196 SD3_DAT6_MARK, SD3_DAT7_MARK,
3199 static const unsigned int sdhi3_ctrl_pins[] = {
3201 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3204 static const unsigned int sdhi3_ctrl_mux[] = {
3205 SD3_CLK_MARK, SD3_CMD_MARK,
3208 static const unsigned int sdhi3_cd_pins[] = {
3213 static const unsigned int sdhi3_cd_mux[] = {
3217 static const unsigned int sdhi3_wp_pins[] = {
3222 static const unsigned int sdhi3_wp_mux[] = {
3226 static const unsigned int sdhi3_ds_pins[] = {
3231 static const unsigned int sdhi3_ds_mux[] = {
3235 /* - SSI -------------------------------------------------------------------- */
3236 static const unsigned int ssi0_data_pins[] = {
3241 static const unsigned int ssi0_data_mux[] = {
3245 static const unsigned int ssi01239_ctrl_pins[] = {
3247 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3250 static const unsigned int ssi01239_ctrl_mux[] = {
3251 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3254 static const unsigned int ssi1_data_pins[] = {
3259 static const unsigned int ssi1_data_mux[] = {
3263 static const unsigned int ssi1_ctrl_pins[] = {
3265 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3268 static const unsigned int ssi1_ctrl_mux[] = {
3269 SSI_SCK1_MARK, SSI_WS1_MARK,
3272 static const unsigned int ssi2_data_pins[] = {
3277 static const unsigned int ssi2_data_mux[] = {
3281 static const unsigned int ssi2_ctrl_a_pins[] = {
3283 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3286 static const unsigned int ssi2_ctrl_a_mux[] = {
3287 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3290 static const unsigned int ssi2_ctrl_b_pins[] = {
3292 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3295 static const unsigned int ssi2_ctrl_b_mux[] = {
3296 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3299 static const unsigned int ssi3_data_pins[] = {
3304 static const unsigned int ssi3_data_mux[] = {
3308 static const unsigned int ssi349_ctrl_pins[] = {
3310 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3313 static const unsigned int ssi349_ctrl_mux[] = {
3314 SSI_SCK349_MARK, SSI_WS349_MARK,
3317 static const unsigned int ssi4_data_pins[] = {
3322 static const unsigned int ssi4_data_mux[] = {
3326 static const unsigned int ssi4_ctrl_pins[] = {
3328 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3331 static const unsigned int ssi4_ctrl_mux[] = {
3332 SSI_SCK4_MARK, SSI_WS4_MARK,
3335 static const unsigned int ssi5_data_pins[] = {
3340 static const unsigned int ssi5_data_mux[] = {
3344 static const unsigned int ssi5_ctrl_pins[] = {
3346 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3349 static const unsigned int ssi5_ctrl_mux[] = {
3350 SSI_SCK5_MARK, SSI_WS5_MARK,
3353 static const unsigned int ssi6_data_pins[] = {
3358 static const unsigned int ssi6_data_mux[] = {
3362 static const unsigned int ssi6_ctrl_pins[] = {
3364 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3367 static const unsigned int ssi6_ctrl_mux[] = {
3368 SSI_SCK6_MARK, SSI_WS6_MARK,
3371 static const unsigned int ssi7_data_pins[] = {
3376 static const unsigned int ssi7_data_mux[] = {
3380 static const unsigned int ssi78_ctrl_pins[] = {
3382 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3385 static const unsigned int ssi78_ctrl_mux[] = {
3386 SSI_SCK78_MARK, SSI_WS78_MARK,
3389 static const unsigned int ssi8_data_pins[] = {
3394 static const unsigned int ssi8_data_mux[] = {
3398 static const unsigned int ssi9_data_pins[] = {
3403 static const unsigned int ssi9_data_mux[] = {
3407 static const unsigned int ssi9_ctrl_a_pins[] = {
3409 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3412 static const unsigned int ssi9_ctrl_a_mux[] = {
3413 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3416 static const unsigned int ssi9_ctrl_b_pins[] = {
3418 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3421 static const unsigned int ssi9_ctrl_b_mux[] = {
3422 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3425 /* - TMU -------------------------------------------------------------------- */
3426 static const unsigned int tmu_tclk1_a_pins[] = {
3431 static const unsigned int tmu_tclk1_a_mux[] = {
3435 static const unsigned int tmu_tclk1_b_pins[] = {
3440 static const unsigned int tmu_tclk1_b_mux[] = {
3444 static const unsigned int tmu_tclk2_a_pins[] = {
3449 static const unsigned int tmu_tclk2_a_mux[] = {
3453 static const unsigned int tmu_tclk2_b_pins[] = {
3458 static const unsigned int tmu_tclk2_b_mux[] = {
3462 /* - USB0 ------------------------------------------------------------------- */
3463 static const unsigned int usb0_a_pins[] = {
3465 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3468 static const unsigned int usb0_a_mux[] = {
3469 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3472 static const unsigned int usb0_b_pins[] = {
3474 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3477 static const unsigned int usb0_b_mux[] = {
3478 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3481 static const unsigned int usb0_id_pins[] = {
3486 static const unsigned int usb0_id_mux[] = {
3490 /* - USB30 ------------------------------------------------------------------ */
3491 static const unsigned int usb30_pins[] = {
3493 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3496 static const unsigned int usb30_mux[] = {
3497 USB30_PWEN_MARK, USB30_OVC_MARK,
3500 static const unsigned int usb30_id_pins[] = {
3505 static const unsigned int usb30_id_mux[] = {
3509 /* - VIN4 ------------------------------------------------------------------- */
3510 static const unsigned int vin4_data8_a_pins[] = {
3511 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3512 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3513 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3514 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3517 static const unsigned int vin4_data8_a_mux[] = {
3518 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3519 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3520 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3521 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3524 static const unsigned int vin4_data10_a_pins[] = {
3525 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3526 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3527 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3528 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3529 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3532 static const unsigned int vin4_data10_a_mux[] = {
3533 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3534 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3535 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3536 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3537 VI4_DATA8_MARK, VI4_DATA9_MARK,
3540 static const unsigned int vin4_data12_a_pins[] = {
3541 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3542 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3543 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3544 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3545 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3546 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3549 static const unsigned int vin4_data12_a_mux[] = {
3550 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3551 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3552 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3553 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3554 VI4_DATA8_MARK, VI4_DATA9_MARK,
3555 VI4_DATA10_MARK, VI4_DATA11_MARK,
3558 static const unsigned int vin4_data16_a_pins[] = {
3559 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3560 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3561 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3562 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3563 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3564 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3565 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3566 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3569 static const unsigned int vin4_data16_a_mux[] = {
3570 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3571 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3572 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3573 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3574 VI4_DATA8_MARK, VI4_DATA9_MARK,
3575 VI4_DATA10_MARK, VI4_DATA11_MARK,
3576 VI4_DATA12_MARK, VI4_DATA13_MARK,
3577 VI4_DATA14_MARK, VI4_DATA15_MARK,
3580 static const unsigned int vin4_data20_a_pins[] = {
3581 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3582 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3583 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3584 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3585 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3586 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3587 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3588 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3589 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3590 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3593 static const unsigned int vin4_data20_a_mux[] = {
3594 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3595 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3596 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3597 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3598 VI4_DATA8_MARK, VI4_DATA9_MARK,
3599 VI4_DATA10_MARK, VI4_DATA11_MARK,
3600 VI4_DATA12_MARK, VI4_DATA13_MARK,
3601 VI4_DATA14_MARK, VI4_DATA15_MARK,
3602 VI4_DATA16_MARK, VI4_DATA17_MARK,
3603 VI4_DATA18_MARK, VI4_DATA19_MARK,
3606 static const unsigned int vin4_data24_a_pins[] = {
3607 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3608 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3609 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3610 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3611 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3612 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3613 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3614 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3615 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3616 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3617 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3618 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3621 static const unsigned int vin4_data24_a_mux[] = {
3622 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3623 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3624 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3625 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3626 VI4_DATA8_MARK, VI4_DATA9_MARK,
3627 VI4_DATA10_MARK, VI4_DATA11_MARK,
3628 VI4_DATA12_MARK, VI4_DATA13_MARK,
3629 VI4_DATA14_MARK, VI4_DATA15_MARK,
3630 VI4_DATA16_MARK, VI4_DATA17_MARK,
3631 VI4_DATA18_MARK, VI4_DATA19_MARK,
3632 VI4_DATA20_MARK, VI4_DATA21_MARK,
3633 VI4_DATA22_MARK, VI4_DATA23_MARK,
3636 static const unsigned int vin4_data8_b_pins[] = {
3637 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3638 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3639 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3640 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3643 static const unsigned int vin4_data8_b_mux[] = {
3644 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3645 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3646 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3647 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3650 static const unsigned int vin4_data10_b_pins[] = {
3651 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3652 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3653 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3654 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3655 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3658 static const unsigned int vin4_data10_b_mux[] = {
3659 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3660 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3661 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3662 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3663 VI4_DATA8_MARK, VI4_DATA9_MARK,
3666 static const unsigned int vin4_data12_b_pins[] = {
3667 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3668 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3669 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3670 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3671 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3672 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3675 static const unsigned int vin4_data12_b_mux[] = {
3676 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3677 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3678 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3679 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3680 VI4_DATA8_MARK, VI4_DATA9_MARK,
3681 VI4_DATA10_MARK, VI4_DATA11_MARK,
3684 static const unsigned int vin4_data16_b_pins[] = {
3685 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3686 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3687 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3688 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3689 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3690 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3691 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3692 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3695 static const unsigned int vin4_data16_b_mux[] = {
3696 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3697 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3698 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3699 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3700 VI4_DATA8_MARK, VI4_DATA9_MARK,
3701 VI4_DATA10_MARK, VI4_DATA11_MARK,
3702 VI4_DATA12_MARK, VI4_DATA13_MARK,
3703 VI4_DATA14_MARK, VI4_DATA15_MARK,
3706 static const unsigned int vin4_data20_b_pins[] = {
3707 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3708 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3709 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3710 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3711 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3712 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3713 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3714 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3715 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3716 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3719 static const unsigned int vin4_data20_b_mux[] = {
3720 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3721 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3722 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3723 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3724 VI4_DATA8_MARK, VI4_DATA9_MARK,
3725 VI4_DATA10_MARK, VI4_DATA11_MARK,
3726 VI4_DATA12_MARK, VI4_DATA13_MARK,
3727 VI4_DATA14_MARK, VI4_DATA15_MARK,
3728 VI4_DATA16_MARK, VI4_DATA17_MARK,
3729 VI4_DATA18_MARK, VI4_DATA19_MARK,
3732 static const unsigned int vin4_data24_b_pins[] = {
3733 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3734 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3735 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3736 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3737 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3738 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3739 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3740 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3741 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3742 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 15),
3743 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3744 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3747 static const unsigned int vin4_data24_b_mux[] = {
3748 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3749 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3750 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3751 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3752 VI4_DATA8_MARK, VI4_DATA9_MARK,
3753 VI4_DATA10_MARK, VI4_DATA11_MARK,
3754 VI4_DATA12_MARK, VI4_DATA13_MARK,
3755 VI4_DATA14_MARK, VI4_DATA15_MARK,
3756 VI4_DATA16_MARK, VI4_DATA17_MARK,
3757 VI4_DATA18_MARK, VI4_DATA19_MARK,
3758 VI4_DATA20_MARK, VI4_DATA21_MARK,
3759 VI4_DATA22_MARK, VI4_DATA23_MARK,
3762 static const unsigned int vin4_data8_sft8_pins[] = {
3763 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3764 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3765 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3766 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3769 static const unsigned int vin4_data8_sft8_mux[] = {
3770 VI4_DATA8_MARK, VI4_DATA9_MARK,
3771 VI4_DATA10_MARK, VI4_DATA11_MARK,
3772 VI4_DATA12_MARK, VI4_DATA13_MARK,
3773 VI4_DATA14_MARK, VI4_DATA15_MARK,
3776 static const unsigned int vin4_sync_pins[] = {
3778 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3781 static const unsigned int vin4_sync_mux[] = {
3782 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3785 static const unsigned int vin4_field_pins[] = {
3789 static const unsigned int vin4_field_mux[] = {
3793 static const unsigned int vin4_clkenb_pins[] = {
3797 static const unsigned int vin4_clkenb_mux[] = {
3801 static const unsigned int vin4_clk_pins[] = {
3805 static const unsigned int vin4_clk_mux[] = {
3809 /* - VIN5 ------------------------------------------------------------------- */
3810 static const unsigned int vin5_data8_a_pins[] = {
3811 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3812 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3813 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3814 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3817 static const unsigned int vin5_data8_a_mux[] = {
3818 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3819 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3820 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3821 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3824 static const unsigned int vin5_data8_sft8_a_pins[] = {
3825 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3826 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3827 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3828 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3831 static const unsigned int vin5_data8_sft8_a_mux[] = {
3832 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3833 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3834 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3835 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3838 static const unsigned int vin5_data10_a_pins[] = {
3839 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3840 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3841 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3842 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3843 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3846 static const unsigned int vin5_data10_a_mux[] = {
3847 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3848 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3849 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3850 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3851 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3854 static const unsigned int vin5_data12_a_pins[] = {
3855 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3856 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3857 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3858 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3859 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3860 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3863 static const unsigned int vin5_data12_a_mux[] = {
3864 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3865 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3866 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3867 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3868 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3869 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3872 static const unsigned int vin5_data16_a_pins[] = {
3873 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3874 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3875 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3876 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3877 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3878 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3879 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3880 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3883 static const unsigned int vin5_data16_a_mux[] = {
3884 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3885 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3886 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3887 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3888 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3889 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3890 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3891 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3894 static const unsigned int vin5_data8_b_pins[] = {
3895 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3896 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
3897 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3898 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3901 static const unsigned int vin5_data8_b_mux[] = {
3902 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
3903 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
3904 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
3905 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
3908 static const unsigned int vin5_sync_a_pins[] = {
3909 /* HSYNC_N, VSYNC_N */
3910 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3913 static const unsigned int vin5_sync_a_mux[] = {
3914 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3917 static const unsigned int vin5_field_a_pins[] = {
3921 static const unsigned int vin5_field_a_mux[] = {
3925 static const unsigned int vin5_clkenb_a_pins[] = {
3929 static const unsigned int vin5_clkenb_a_mux[] = {
3933 static const unsigned int vin5_clk_a_pins[] = {
3937 static const unsigned int vin5_clk_a_mux[] = {
3941 static const unsigned int vin5_clk_b_pins[] = {
3945 static const unsigned int vin5_clk_b_mux[] = {
3949 static const struct sh_pfc_pin_group pinmux_groups[] = {
3950 SH_PFC_PIN_GROUP(audio_clk_a),
3951 SH_PFC_PIN_GROUP(audio_clk_b_a),
3952 SH_PFC_PIN_GROUP(audio_clk_b_b),
3953 SH_PFC_PIN_GROUP(audio_clk_b_c),
3954 SH_PFC_PIN_GROUP(audio_clk_c_a),
3955 SH_PFC_PIN_GROUP(audio_clk_c_b),
3956 SH_PFC_PIN_GROUP(audio_clk_c_c),
3957 SH_PFC_PIN_GROUP(audio_clkout_a),
3958 SH_PFC_PIN_GROUP(audio_clkout_b),
3959 SH_PFC_PIN_GROUP(audio_clkout1_a),
3960 SH_PFC_PIN_GROUP(audio_clkout1_b),
3961 SH_PFC_PIN_GROUP(audio_clkout1_c),
3962 SH_PFC_PIN_GROUP(audio_clkout2_a),
3963 SH_PFC_PIN_GROUP(audio_clkout2_b),
3964 SH_PFC_PIN_GROUP(audio_clkout2_c),
3965 SH_PFC_PIN_GROUP(audio_clkout3_a),
3966 SH_PFC_PIN_GROUP(audio_clkout3_b),
3967 SH_PFC_PIN_GROUP(audio_clkout3_c),
3968 SH_PFC_PIN_GROUP(avb_link),
3969 SH_PFC_PIN_GROUP(avb_magic),
3970 SH_PFC_PIN_GROUP(avb_phy_int),
3971 SH_PFC_PIN_GROUP(avb_mii),
3972 SH_PFC_PIN_GROUP(avb_avtp_pps),
3973 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3974 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3975 SH_PFC_PIN_GROUP(can0_data),
3976 SH_PFC_PIN_GROUP(can1_data),
3977 SH_PFC_PIN_GROUP(can_clk),
3978 SH_PFC_PIN_GROUP(canfd0_data),
3979 SH_PFC_PIN_GROUP(canfd1_data),
3980 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3981 SH_PFC_PIN_GROUP(drif0_data0_a),
3982 SH_PFC_PIN_GROUP(drif0_data1_a),
3983 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3984 SH_PFC_PIN_GROUP(drif0_data0_b),
3985 SH_PFC_PIN_GROUP(drif0_data1_b),
3986 SH_PFC_PIN_GROUP(drif1_ctrl),
3987 SH_PFC_PIN_GROUP(drif1_data0),
3988 SH_PFC_PIN_GROUP(drif1_data1),
3989 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3990 SH_PFC_PIN_GROUP(drif2_data0_a),
3991 SH_PFC_PIN_GROUP(drif2_data1_a),
3992 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3993 SH_PFC_PIN_GROUP(drif2_data0_b),
3994 SH_PFC_PIN_GROUP(drif2_data1_b),
3995 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3996 SH_PFC_PIN_GROUP(drif3_data0_a),
3997 SH_PFC_PIN_GROUP(drif3_data1_a),
3998 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3999 SH_PFC_PIN_GROUP(drif3_data0_b),
4000 SH_PFC_PIN_GROUP(drif3_data1_b),
4001 SH_PFC_PIN_GROUP(du_rgb666),
4002 SH_PFC_PIN_GROUP(du_rgb888),
4003 SH_PFC_PIN_GROUP(du_clk_out_0),
4004 SH_PFC_PIN_GROUP(du_sync),
4005 SH_PFC_PIN_GROUP(du_cde),
4006 SH_PFC_PIN_GROUP(du_disp),
4007 SH_PFC_PIN_GROUP(du_disp_cde),
4008 SH_PFC_PIN_GROUP(du_clk_in_0),
4009 SH_PFC_PIN_GROUP(du_clk_in_1),
4010 SH_PFC_PIN_GROUP(hscif0_data_a),
4011 SH_PFC_PIN_GROUP(hscif0_clk_a),
4012 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
4013 SH_PFC_PIN_GROUP(hscif0_data_b),
4014 SH_PFC_PIN_GROUP(hscif0_clk_b),
4015 SH_PFC_PIN_GROUP(hscif1_data_a),
4016 SH_PFC_PIN_GROUP(hscif1_clk_a),
4017 SH_PFC_PIN_GROUP(hscif1_data_b),
4018 SH_PFC_PIN_GROUP(hscif1_clk_b),
4019 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4020 SH_PFC_PIN_GROUP(hscif2_data_a),
4021 SH_PFC_PIN_GROUP(hscif2_clk_a),
4022 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4023 SH_PFC_PIN_GROUP(hscif2_data_b),
4024 SH_PFC_PIN_GROUP(hscif3_data_a),
4025 SH_PFC_PIN_GROUP(hscif3_data_b),
4026 SH_PFC_PIN_GROUP(hscif3_clk_b),
4027 SH_PFC_PIN_GROUP(hscif3_data_c),
4028 SH_PFC_PIN_GROUP(hscif3_clk_c),
4029 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
4030 SH_PFC_PIN_GROUP(hscif3_data_d),
4031 SH_PFC_PIN_GROUP(hscif3_data_e),
4032 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
4033 SH_PFC_PIN_GROUP(hscif4_data_a),
4034 SH_PFC_PIN_GROUP(hscif4_clk_a),
4035 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
4036 SH_PFC_PIN_GROUP(hscif4_data_b),
4037 SH_PFC_PIN_GROUP(hscif4_clk_b),
4038 SH_PFC_PIN_GROUP(hscif4_data_c),
4039 SH_PFC_PIN_GROUP(hscif4_data_d),
4040 SH_PFC_PIN_GROUP(hscif4_data_e),
4041 SH_PFC_PIN_GROUP(i2c1_a),
4042 SH_PFC_PIN_GROUP(i2c1_b),
4043 SH_PFC_PIN_GROUP(i2c1_c),
4044 SH_PFC_PIN_GROUP(i2c1_d),
4045 SH_PFC_PIN_GROUP(i2c2_a),
4046 SH_PFC_PIN_GROUP(i2c2_b),
4047 SH_PFC_PIN_GROUP(i2c2_c),
4048 SH_PFC_PIN_GROUP(i2c2_d),
4049 SH_PFC_PIN_GROUP(i2c2_e),
4050 SH_PFC_PIN_GROUP(i2c4),
4051 SH_PFC_PIN_GROUP(i2c5),
4052 SH_PFC_PIN_GROUP(i2c6_a),
4053 SH_PFC_PIN_GROUP(i2c6_b),
4054 SH_PFC_PIN_GROUP(i2c7_a),
4055 SH_PFC_PIN_GROUP(i2c7_b),
4056 SH_PFC_PIN_GROUP(intc_ex_irq0),
4057 SH_PFC_PIN_GROUP(msiof0_clk),
4058 SH_PFC_PIN_GROUP(msiof0_sync),
4059 SH_PFC_PIN_GROUP(msiof0_ss1),
4060 SH_PFC_PIN_GROUP(msiof0_ss2),
4061 SH_PFC_PIN_GROUP(msiof0_txd),
4062 SH_PFC_PIN_GROUP(msiof0_rxd),
4063 SH_PFC_PIN_GROUP(msiof1_clk),
4064 SH_PFC_PIN_GROUP(msiof1_sync),
4065 SH_PFC_PIN_GROUP(msiof1_ss1),
4066 SH_PFC_PIN_GROUP(msiof1_ss2),
4067 SH_PFC_PIN_GROUP(msiof1_txd),
4068 SH_PFC_PIN_GROUP(msiof1_rxd),
4069 SH_PFC_PIN_GROUP(msiof2_clk_a),
4070 SH_PFC_PIN_GROUP(msiof2_sync_a),
4071 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4072 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4073 SH_PFC_PIN_GROUP(msiof2_txd_a),
4074 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4075 SH_PFC_PIN_GROUP(msiof2_clk_b),
4076 SH_PFC_PIN_GROUP(msiof2_sync_b),
4077 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4078 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4079 SH_PFC_PIN_GROUP(msiof2_txd_b),
4080 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4081 SH_PFC_PIN_GROUP(msiof3_clk_a),
4082 SH_PFC_PIN_GROUP(msiof3_sync_a),
4083 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4084 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4085 SH_PFC_PIN_GROUP(msiof3_txd_a),
4086 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4087 SH_PFC_PIN_GROUP(msiof3_clk_b),
4088 SH_PFC_PIN_GROUP(msiof3_sync_b),
4089 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4090 SH_PFC_PIN_GROUP(msiof3_txd_b),
4091 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4092 SH_PFC_PIN_GROUP(pwm0_a),
4093 SH_PFC_PIN_GROUP(pwm0_b),
4094 SH_PFC_PIN_GROUP(pwm1_a),
4095 SH_PFC_PIN_GROUP(pwm1_b),
4096 SH_PFC_PIN_GROUP(pwm2_a),
4097 SH_PFC_PIN_GROUP(pwm2_b),
4098 SH_PFC_PIN_GROUP(pwm2_c),
4099 SH_PFC_PIN_GROUP(pwm3_a),
4100 SH_PFC_PIN_GROUP(pwm3_b),
4101 SH_PFC_PIN_GROUP(pwm3_c),
4102 SH_PFC_PIN_GROUP(pwm4_a),
4103 SH_PFC_PIN_GROUP(pwm4_b),
4104 SH_PFC_PIN_GROUP(pwm5_a),
4105 SH_PFC_PIN_GROUP(pwm5_b),
4106 SH_PFC_PIN_GROUP(pwm6_a),
4107 SH_PFC_PIN_GROUP(pwm6_b),
4108 SH_PFC_PIN_GROUP(scif0_data_a),
4109 SH_PFC_PIN_GROUP(scif0_clk_a),
4110 SH_PFC_PIN_GROUP(scif0_ctrl_a),
4111 SH_PFC_PIN_GROUP(scif0_data_b),
4112 SH_PFC_PIN_GROUP(scif0_clk_b),
4113 SH_PFC_PIN_GROUP(scif1_data),
4114 SH_PFC_PIN_GROUP(scif1_clk),
4115 SH_PFC_PIN_GROUP(scif1_ctrl),
4116 SH_PFC_PIN_GROUP(scif2_data_a),
4117 SH_PFC_PIN_GROUP(scif2_clk_a),
4118 SH_PFC_PIN_GROUP(scif2_data_b),
4119 SH_PFC_PIN_GROUP(scif3_data_a),
4120 SH_PFC_PIN_GROUP(scif3_clk_a),
4121 SH_PFC_PIN_GROUP(scif3_ctrl_a),
4122 SH_PFC_PIN_GROUP(scif3_data_b),
4123 SH_PFC_PIN_GROUP(scif3_data_c),
4124 SH_PFC_PIN_GROUP(scif3_clk_c),
4125 SH_PFC_PIN_GROUP(scif4_data_a),
4126 SH_PFC_PIN_GROUP(scif4_clk_a),
4127 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4128 SH_PFC_PIN_GROUP(scif4_data_b),
4129 SH_PFC_PIN_GROUP(scif4_clk_b),
4130 SH_PFC_PIN_GROUP(scif4_data_c),
4131 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4132 SH_PFC_PIN_GROUP(scif5_data_a),
4133 SH_PFC_PIN_GROUP(scif5_clk_a),
4134 SH_PFC_PIN_GROUP(scif5_data_b),
4135 SH_PFC_PIN_GROUP(scif5_data_c),
4136 SH_PFC_PIN_GROUP(scif_clk_a),
4137 SH_PFC_PIN_GROUP(scif_clk_b),
4138 SH_PFC_PIN_GROUP(sdhi0_data1),
4139 SH_PFC_PIN_GROUP(sdhi0_data4),
4140 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4141 SH_PFC_PIN_GROUP(sdhi0_cd),
4142 SH_PFC_PIN_GROUP(sdhi0_wp),
4143 SH_PFC_PIN_GROUP(sdhi1_data1),
4144 SH_PFC_PIN_GROUP(sdhi1_data4),
4145 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4146 SH_PFC_PIN_GROUP(sdhi1_cd),
4147 SH_PFC_PIN_GROUP(sdhi1_wp),
4148 SH_PFC_PIN_GROUP(sdhi3_data1),
4149 SH_PFC_PIN_GROUP(sdhi3_data4),
4150 SH_PFC_PIN_GROUP(sdhi3_data8),
4151 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4152 SH_PFC_PIN_GROUP(sdhi3_cd),
4153 SH_PFC_PIN_GROUP(sdhi3_wp),
4154 SH_PFC_PIN_GROUP(sdhi3_ds),
4155 SH_PFC_PIN_GROUP(ssi0_data),
4156 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4157 SH_PFC_PIN_GROUP(ssi1_data),
4158 SH_PFC_PIN_GROUP(ssi1_ctrl),
4159 SH_PFC_PIN_GROUP(ssi2_data),
4160 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4161 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4162 SH_PFC_PIN_GROUP(ssi3_data),
4163 SH_PFC_PIN_GROUP(ssi349_ctrl),
4164 SH_PFC_PIN_GROUP(ssi4_data),
4165 SH_PFC_PIN_GROUP(ssi4_ctrl),
4166 SH_PFC_PIN_GROUP(ssi5_data),
4167 SH_PFC_PIN_GROUP(ssi5_ctrl),
4168 SH_PFC_PIN_GROUP(ssi6_data),
4169 SH_PFC_PIN_GROUP(ssi6_ctrl),
4170 SH_PFC_PIN_GROUP(ssi7_data),
4171 SH_PFC_PIN_GROUP(ssi78_ctrl),
4172 SH_PFC_PIN_GROUP(ssi8_data),
4173 SH_PFC_PIN_GROUP(ssi9_data),
4174 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4175 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4176 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4177 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4178 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4179 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4180 SH_PFC_PIN_GROUP(usb0_a),
4181 SH_PFC_PIN_GROUP(usb0_b),
4182 SH_PFC_PIN_GROUP(usb0_id),
4183 SH_PFC_PIN_GROUP(usb30),
4184 SH_PFC_PIN_GROUP(usb30_id),
4185 SH_PFC_PIN_GROUP(vin4_data8_a),
4186 SH_PFC_PIN_GROUP(vin4_data10_a),
4187 SH_PFC_PIN_GROUP(vin4_data12_a),
4188 SH_PFC_PIN_GROUP(vin4_data16_a),
4189 SH_PFC_PIN_GROUP(vin4_data20_a),
4190 SH_PFC_PIN_GROUP(vin4_data24_a),
4191 SH_PFC_PIN_GROUP(vin4_data8_b),
4192 SH_PFC_PIN_GROUP(vin4_data10_b),
4193 SH_PFC_PIN_GROUP(vin4_data12_b),
4194 SH_PFC_PIN_GROUP(vin4_data16_b),
4195 SH_PFC_PIN_GROUP(vin4_data20_b),
4196 SH_PFC_PIN_GROUP(vin4_data24_b),
4197 SH_PFC_PIN_GROUP(vin4_data8_sft8),
4198 SH_PFC_PIN_GROUP(vin4_sync),
4199 SH_PFC_PIN_GROUP(vin4_field),
4200 SH_PFC_PIN_GROUP(vin4_clkenb),
4201 SH_PFC_PIN_GROUP(vin4_clk),
4202 SH_PFC_PIN_GROUP(vin5_data8_a),
4203 SH_PFC_PIN_GROUP(vin5_data8_sft8_a),
4204 SH_PFC_PIN_GROUP(vin5_data10_a),
4205 SH_PFC_PIN_GROUP(vin5_data12_a),
4206 SH_PFC_PIN_GROUP(vin5_data16_a),
4207 SH_PFC_PIN_GROUP(vin5_data8_b),
4208 SH_PFC_PIN_GROUP(vin5_sync_a),
4209 SH_PFC_PIN_GROUP(vin5_field_a),
4210 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4211 SH_PFC_PIN_GROUP(vin5_clk_a),
4212 SH_PFC_PIN_GROUP(vin5_clk_b),
4215 static const char * const audio_clk_groups[] = {
4236 static const char * const avb_groups[] = {
4243 "avb_avtp_capture_a",
4246 static const char * const can0_groups[] = {
4250 static const char * const can1_groups[] = {
4254 static const char * const can_clk_groups[] = {
4258 static const char * const canfd0_groups[] = {
4262 static const char * const canfd1_groups[] = {
4266 static const char * const drif0_groups[] = {
4275 static const char * const drif1_groups[] = {
4281 static const char * const drif2_groups[] = {
4290 static const char * const drif3_groups[] = {
4299 static const char * const du_groups[] = {
4311 static const char * const hscif0_groups[] = {
4319 static const char * const hscif1_groups[] = {
4327 static const char * const hscif2_groups[] = {
4334 static const char * const hscif3_groups[] = {
4346 static const char * const hscif4_groups[] = {
4357 static const char * const i2c1_groups[] = {
4364 static const char * const i2c2_groups[] = {
4372 static const char * const i2c4_groups[] = {
4376 static const char * const i2c5_groups[] = {
4380 static const char * const i2c6_groups[] = {
4385 static const char * const i2c7_groups[] = {
4390 static const char * const intc_ex_groups[] = {
4394 static const char * const msiof0_groups[] = {
4403 static const char * const msiof1_groups[] = {
4412 static const char * const msiof2_groups[] = {
4427 static const char * const msiof3_groups[] = {
4441 static const char * const pwm0_groups[] = {
4446 static const char * const pwm1_groups[] = {
4451 static const char * const pwm2_groups[] = {
4457 static const char * const pwm3_groups[] = {
4463 static const char * const pwm4_groups[] = {
4468 static const char * const pwm5_groups[] = {
4473 static const char * const pwm6_groups[] = {
4478 static const char * const scif0_groups[] = {
4486 static const char * const scif1_groups[] = {
4492 static const char * const scif2_groups[] = {
4498 static const char * const scif3_groups[] = {
4507 static const char * const scif4_groups[] = {
4517 static const char * const scif5_groups[] = {
4524 static const char * const scif_clk_groups[] = {
4529 static const char * const sdhi0_groups[] = {
4537 static const char * const sdhi1_groups[] = {
4545 static const char * const sdhi3_groups[] = {
4555 static const char * const ssi_groups[] = {
4579 static const char * const tmu_groups[] = {
4586 static const char * const usb0_groups[] = {
4592 static const char * const usb30_groups[] = {
4597 static const char * const vin4_groups[] = {
4617 static const char * const vin5_groups[] = {
4619 "vin5_data8_sft8_a",
4631 static const struct sh_pfc_function pinmux_functions[] = {
4632 SH_PFC_FUNCTION(audio_clk),
4633 SH_PFC_FUNCTION(avb),
4634 SH_PFC_FUNCTION(can0),
4635 SH_PFC_FUNCTION(can1),
4636 SH_PFC_FUNCTION(can_clk),
4637 SH_PFC_FUNCTION(canfd0),
4638 SH_PFC_FUNCTION(canfd1),
4639 SH_PFC_FUNCTION(drif0),
4640 SH_PFC_FUNCTION(drif1),
4641 SH_PFC_FUNCTION(drif2),
4642 SH_PFC_FUNCTION(drif3),
4643 SH_PFC_FUNCTION(du),
4644 SH_PFC_FUNCTION(hscif0),
4645 SH_PFC_FUNCTION(hscif1),
4646 SH_PFC_FUNCTION(hscif2),
4647 SH_PFC_FUNCTION(hscif3),
4648 SH_PFC_FUNCTION(hscif4),
4649 SH_PFC_FUNCTION(i2c1),
4650 SH_PFC_FUNCTION(i2c2),
4651 SH_PFC_FUNCTION(i2c4),
4652 SH_PFC_FUNCTION(i2c5),
4653 SH_PFC_FUNCTION(i2c6),
4654 SH_PFC_FUNCTION(i2c7),
4655 SH_PFC_FUNCTION(intc_ex),
4656 SH_PFC_FUNCTION(msiof0),
4657 SH_PFC_FUNCTION(msiof1),
4658 SH_PFC_FUNCTION(msiof2),
4659 SH_PFC_FUNCTION(msiof3),
4660 SH_PFC_FUNCTION(pwm0),
4661 SH_PFC_FUNCTION(pwm1),
4662 SH_PFC_FUNCTION(pwm2),
4663 SH_PFC_FUNCTION(pwm3),
4664 SH_PFC_FUNCTION(pwm4),
4665 SH_PFC_FUNCTION(pwm5),
4666 SH_PFC_FUNCTION(pwm6),
4667 SH_PFC_FUNCTION(scif0),
4668 SH_PFC_FUNCTION(scif1),
4669 SH_PFC_FUNCTION(scif2),
4670 SH_PFC_FUNCTION(scif3),
4671 SH_PFC_FUNCTION(scif4),
4672 SH_PFC_FUNCTION(scif5),
4673 SH_PFC_FUNCTION(scif_clk),
4674 SH_PFC_FUNCTION(sdhi0),
4675 SH_PFC_FUNCTION(sdhi1),
4676 SH_PFC_FUNCTION(sdhi3),
4677 SH_PFC_FUNCTION(ssi),
4678 SH_PFC_FUNCTION(tmu),
4679 SH_PFC_FUNCTION(usb0),
4680 SH_PFC_FUNCTION(usb30),
4681 SH_PFC_FUNCTION(vin4),
4682 SH_PFC_FUNCTION(vin5),
4685 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4686 #define F_(x, y) FN_##y
4687 #define FM(x) FN_##x
4688 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4703 GP_0_17_FN, GPSR0_17,
4704 GP_0_16_FN, GPSR0_16,
4705 GP_0_15_FN, GPSR0_15,
4706 GP_0_14_FN, GPSR0_14,
4707 GP_0_13_FN, GPSR0_13,
4708 GP_0_12_FN, GPSR0_12,
4709 GP_0_11_FN, GPSR0_11,
4710 GP_0_10_FN, GPSR0_10,
4720 GP_0_0_FN, GPSR0_0, }
4722 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4732 GP_1_22_FN, GPSR1_22,
4733 GP_1_21_FN, GPSR1_21,
4734 GP_1_20_FN, GPSR1_20,
4735 GP_1_19_FN, GPSR1_19,
4736 GP_1_18_FN, GPSR1_18,
4737 GP_1_17_FN, GPSR1_17,
4738 GP_1_16_FN, GPSR1_16,
4739 GP_1_15_FN, GPSR1_15,
4740 GP_1_14_FN, GPSR1_14,
4741 GP_1_13_FN, GPSR1_13,
4742 GP_1_12_FN, GPSR1_12,
4743 GP_1_11_FN, GPSR1_11,
4744 GP_1_10_FN, GPSR1_10,
4754 GP_1_0_FN, GPSR1_0, }
4756 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4763 GP_2_25_FN, GPSR2_25,
4764 GP_2_24_FN, GPSR2_24,
4765 GP_2_23_FN, GPSR2_23,
4766 GP_2_22_FN, GPSR2_22,
4767 GP_2_21_FN, GPSR2_21,
4768 GP_2_20_FN, GPSR2_20,
4769 GP_2_19_FN, GPSR2_19,
4770 GP_2_18_FN, GPSR2_18,
4771 GP_2_17_FN, GPSR2_17,
4772 GP_2_16_FN, GPSR2_16,
4773 GP_2_15_FN, GPSR2_15,
4774 GP_2_14_FN, GPSR2_14,
4775 GP_2_13_FN, GPSR2_13,
4776 GP_2_12_FN, GPSR2_12,
4777 GP_2_11_FN, GPSR2_11,
4778 GP_2_10_FN, GPSR2_10,
4788 GP_2_0_FN, GPSR2_0, }
4790 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4807 GP_3_15_FN, GPSR3_15,
4808 GP_3_14_FN, GPSR3_14,
4809 GP_3_13_FN, GPSR3_13,
4810 GP_3_12_FN, GPSR3_12,
4811 GP_3_11_FN, GPSR3_11,
4812 GP_3_10_FN, GPSR3_10,
4822 GP_3_0_FN, GPSR3_0, }
4824 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4846 GP_4_10_FN, GPSR4_10,
4856 GP_4_0_FN, GPSR4_0, }
4858 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4871 GP_5_19_FN, GPSR5_19,
4872 GP_5_18_FN, GPSR5_18,
4873 GP_5_17_FN, GPSR5_17,
4874 GP_5_16_FN, GPSR5_16,
4875 GP_5_15_FN, GPSR5_15,
4876 GP_5_14_FN, GPSR5_14,
4877 GP_5_13_FN, GPSR5_13,
4878 GP_5_12_FN, GPSR5_12,
4879 GP_5_11_FN, GPSR5_11,
4880 GP_5_10_FN, GPSR5_10,
4890 GP_5_0_FN, GPSR5_0, }
4892 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4907 GP_6_17_FN, GPSR6_17,
4908 GP_6_16_FN, GPSR6_16,
4909 GP_6_15_FN, GPSR6_15,
4910 GP_6_14_FN, GPSR6_14,
4911 GP_6_13_FN, GPSR6_13,
4912 GP_6_12_FN, GPSR6_12,
4913 GP_6_11_FN, GPSR6_11,
4914 GP_6_10_FN, GPSR6_10,
4924 GP_6_0_FN, GPSR6_0, }
4930 #define FM(x) FN_##x,
4931 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4941 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4951 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4961 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4971 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4981 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4991 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5001 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5011 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5021 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5031 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5041 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5051 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5061 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5071 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5081 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5095 #define FM(x) FN_##x,
5096 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5097 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
5098 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
5124 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5125 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
5126 1, 2, 2, 2, 1, 1, 2, 1, 4) {
5148 /* RESERVED 3, 2, 1, 0 */
5149 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
5154 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5155 .name = "r8a77990_pfc",
5156 .unlock_reg = 0xe6060000, /* PMMR */
5158 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5160 .pins = pinmux_pins,
5161 .nr_pins = ARRAY_SIZE(pinmux_pins),
5162 .groups = pinmux_groups,
5163 .nr_groups = ARRAY_SIZE(pinmux_groups),
5164 .functions = pinmux_functions,
5165 .nr_functions = ARRAY_SIZE(pinmux_functions),
5167 .cfg_regs = pinmux_config_regs,
5169 .pinmux_data = pinmux_data,
5170 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / u-boot / blob