git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc.c

   1 /*
   2  * Pin Control driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  * Copyright (C) 2017 Marek Vasut
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #define DRV_NAME "sh-pfc"
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sh_pfc.h"
  23
  24 enum sh_pfc_model {
  25         SH_PFC_R8A7790 = 0,
  26         SH_PFC_R8A7791,
  27         SH_PFC_R8A7792,
  28         SH_PFC_R8A7793,
  29         SH_PFC_R8A7794,
  30         SH_PFC_R8A7795,
  31         SH_PFC_R8A7796,
  32         SH_PFC_R8A77970,
  33         SH_PFC_R8A77995,
  34 };
  35
  36 struct sh_pfc_pin_config {
  37         u32 type;
  38 };
  39
  40 struct sh_pfc_pinctrl {
  41         struct sh_pfc *pfc;
  42
  43         struct sh_pfc_pin_config *configs;
  44
  45         const char *func_prop_name;
  46         const char *groups_prop_name;
  47         const char *pins_prop_name;
  48 };
  49
  50 struct sh_pfc_pin_range {
  51         u16 start;
  52         u16 end;
  53 };
  54
  55 struct sh_pfc_pinctrl_priv {
  56         struct sh_pfc                   pfc;
  57         struct sh_pfc_pinctrl           pmx;
  58 };
  59
  60 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  61 {
  62         unsigned int offset;
  63         unsigned int i;
  64
  65         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  66                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  67
  68                 if (pin <= range->end)
  69                         return pin >= range->start
  70                              ? offset + pin - range->start : -1;
  71
  72                 offset += range->end - range->start + 1;
  73         }
  74
  75         return -EINVAL;
  76 }
  77
  78 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  79 {
  80         if (enum_id < r->begin)
  81                 return 0;
  82
  83         if (enum_id > r->end)
  84                 return 0;
  85
  86         return 1;
  87 }
  88
  89 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  90 {
  91         switch (reg_width) {
  92         case 8:
  93                 return readb(mapped_reg);
  94         case 16:
  95                 return readw(mapped_reg);
  96         case 32:
  97                 return readl(mapped_reg);
  98         }
  99
 100         BUG();
 101         return 0;
 102 }
 103
 104 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 105                           u32 data)
 106 {
 107         switch (reg_width) {
 108         case 8:
 109                 writeb(data, mapped_reg);
 110                 return;
 111         case 16:
 112                 writew(data, mapped_reg);
 113                 return;
 114         case 32:
 115                 writel(data, mapped_reg);
 116                 return;
 117         }
 118
 119         BUG();
 120 }
 121
 122 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 123 {
 124         return sh_pfc_read_raw_reg(pfc->regs + reg, width);
 125 }
 126
 127 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 128 {
 129         void __iomem *unlock_reg =
 130                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 131
 132         if (pfc->info->unlock_reg)
 133                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 134
 135         sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
 136 }
 137
 138 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 139                                      const struct pinmux_cfg_reg *crp,
 140                                      unsigned int in_pos,
 141                                      void __iomem **mapped_regp, u32 *maskp,
 142                                      unsigned int *posp)
 143 {
 144         unsigned int k;
 145
 146         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 147
 148         if (crp->field_width) {
 149                 *maskp = (1 << crp->field_width) - 1;
 150                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 151         } else {
 152                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 153                 *posp = crp->reg_width;
 154                 for (k = 0; k <= in_pos; k++)
 155                         *posp -= crp->var_field_width[k];
 156         }
 157 }
 158
 159 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 160                                     const struct pinmux_cfg_reg *crp,
 161                                     unsigned int field, u32 value)
 162 {
 163         void __iomem *mapped_reg;
 164         void __iomem *unlock_reg =
 165                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 166         unsigned int pos;
 167         u32 mask, data;
 168
 169         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 170
 171         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 172                 "r_width = %u, f_width = %u\n",
 173                 crp->reg, value, field, crp->reg_width, crp->field_width);
 174
 175         mask = ~(mask << pos);
 176         value = value << pos;
 177
 178         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 179         data &= mask;
 180         data |= value;
 181
 182         if (pfc->info->unlock_reg)
 183                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 184
 185         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 186 }
 187
 188 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 189                                  const struct pinmux_cfg_reg **crp,
 190                                  unsigned int *fieldp, u32 *valuep)
 191 {
 192         unsigned int k = 0;
 193
 194         while (1) {
 195                 const struct pinmux_cfg_reg *config_reg =
 196                         pfc->info->cfg_regs + k;
 197                 unsigned int r_width = config_reg->reg_width;
 198                 unsigned int f_width = config_reg->field_width;
 199                 unsigned int curr_width;
 200                 unsigned int bit_pos;
 201                 unsigned int pos = 0;
 202                 unsigned int m = 0;
 203
 204                 if (!r_width)
 205                         break;
 206
 207                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 208                         u32 ncomb;
 209                         u32 n;
 210
 211                         if (f_width)
 212                                 curr_width = f_width;
 213                         else
 214                                 curr_width = config_reg->var_field_width[m];
 215
 216                         ncomb = 1 << curr_width;
 217                         for (n = 0; n < ncomb; n++) {
 218                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 219                                         *crp = config_reg;
 220                                         *fieldp = m;
 221                                         *valuep = n;
 222                                         return 0;
 223                                 }
 224                         }
 225                         pos += ncomb;
 226                         m++;
 227                 }
 228                 k++;
 229         }
 230
 231         return -EINVAL;
 232 }
 233
 234 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 235                               u16 *enum_idp)
 236 {
 237         const u16 *data = pfc->info->pinmux_data;
 238         unsigned int k;
 239
 240         if (pos) {
 241                 *enum_idp = data[pos + 1];
 242                 return pos + 1;
 243         }
 244
 245         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 246                 if (data[k] == mark) {
 247                         *enum_idp = data[k + 1];
 248                         return k + 1;
 249                 }
 250         }
 251
 252         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 253                 mark);
 254         return -EINVAL;
 255 }
 256
 257 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 258 {
 259         const struct pinmux_range *range;
 260         int pos = 0;
 261
 262         switch (pinmux_type) {
 263         case PINMUX_TYPE_GPIO:
 264         case PINMUX_TYPE_FUNCTION:
 265                 range = NULL;
 266                 break;
 267
 268         case PINMUX_TYPE_OUTPUT:
 269                 range = &pfc->info->output;
 270                 break;
 271
 272         case PINMUX_TYPE_INPUT:
 273                 range = &pfc->info->input;
 274                 break;
 275
 276         default:
 277                 return -EINVAL;
 278         }
 279
 280         /* Iterate over all the configuration fields we need to update. */
 281         while (1) {
 282                 const struct pinmux_cfg_reg *cr;
 283                 unsigned int field;
 284                 u16 enum_id;
 285                 u32 value;
 286                 int in_range;
 287                 int ret;
 288
 289                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 290                 if (pos < 0)
 291                         return pos;
 292
 293                 if (!enum_id)
 294                         break;
 295
 296                 /* Check if the configuration field selects a function. If it
 297                  * doesn't, skip the field if it's not applicable to the
 298                  * requested pinmux type.
 299                  */
 300                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 301                 if (!in_range) {
 302                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 303                                 /* Functions are allowed to modify all
 304                                  * fields.
 305                                  */
 306                                 in_range = 1;
 307                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 308                                 /* Input/output types can only modify fields
 309                                  * that correspond to their respective ranges.
 310                                  */
 311                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 312
 313                                 /*
 314                                  * special case pass through for fixed
 315                                  * input-only or output-only pins without
 316                                  * function enum register association.
 317                                  */
 318                                 if (in_range && enum_id == range->force)
 319                                         continue;
 320                         }
 321                         /* GPIOs are only allowed to modify function fields. */
 322                 }
 323
 324                 if (!in_range)
 325                         continue;
 326
 327                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 328                 if (ret < 0)
 329                         return ret;
 330
 331                 sh_pfc_write_config_reg(pfc, cr, field, value);
 332         }
 333
 334         return 0;
 335 }
 336
 337 const struct sh_pfc_bias_info *
 338 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 339                         unsigned int num, unsigned int pin)
 340 {
 341         unsigned int i;
 342
 343         for (i = 0; i < num; i++)
 344                 if (info[i].pin == pin)
 345                         return &info[i];
 346
 347         printf("Pin %u is not in bias info list\n", pin);
 348
 349         return NULL;
 350 }
 351
 352 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 353 {
 354         struct sh_pfc_pin_range *range;
 355         unsigned int nr_ranges;
 356         unsigned int i;
 357
 358         if (pfc->info->pins[0].pin == (u16)-1) {
 359                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 360                  * in its pin arrays yet. Consider the pin numbers range as
 361                  * continuous and allocate a single range.
 362                  */
 363                 pfc->nr_ranges = 1;
 364                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 365                 if (pfc->ranges == NULL)
 366                         return -ENOMEM;
 367
 368                 pfc->ranges->start = 0;
 369                 pfc->ranges->end = pfc->info->nr_pins - 1;
 370                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 371
 372                 return 0;
 373         }
 374
 375         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 376          * be sorted by pin numbers, and pins without a GPIO port must come
 377          * last.
 378          */
 379         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 380                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 381                         nr_ranges++;
 382         }
 383
 384         pfc->nr_ranges = nr_ranges;
 385         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 386         if (pfc->ranges == NULL)
 387                 return -ENOMEM;
 388
 389         range = pfc->ranges;
 390         range->start = pfc->info->pins[0].pin;
 391
 392         for (i = 1; i < pfc->info->nr_pins; ++i) {
 393                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 394                         continue;
 395
 396                 range->end = pfc->info->pins[i-1].pin;
 397                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 398                         pfc->nr_gpio_pins = range->end + 1;
 399
 400                 range++;
 401                 range->start = pfc->info->pins[i].pin;
 402         }
 403
 404         range->end = pfc->info->pins[i-1].pin;
 405         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 406                 pfc->nr_gpio_pins = range->end + 1;
 407
 408         return 0;
 409 }
 410
 411 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 412 {
 413         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 414
 415         return priv->pfc.info->nr_pins;
 416 }
 417
 418 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 419                                                   unsigned selector)
 420 {
 421         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 422
 423         return priv->pfc.info->pins[selector].name;
 424 }
 425
 426 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 427 {
 428         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 429
 430         return priv->pfc.info->nr_groups;
 431 }
 432
 433 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 434                                                   unsigned selector)
 435 {
 436         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 437
 438         return priv->pfc.info->groups[selector].name;
 439 }
 440
 441 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 442 {
 443         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 444
 445         return priv->pfc.info->nr_functions;
 446 }
 447
 448 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 449                                                   unsigned selector)
 450 {
 451         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 452
 453         return priv->pfc.info->functions[selector].name;
 454 }
 455
 456 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 457 {
 458         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 459         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 460         struct sh_pfc *pfc = &priv->pfc;
 461         struct sh_pfc_pin_config *cfg;
 462         const struct sh_pfc_pin *pin = NULL;
 463         int i, idx;
 464
 465         for (i = 1; i < pfc->info->nr_pins; i++) {
 466                 if (priv->pfc.info->pins[i].pin != pin_selector)
 467                         continue;
 468
 469                 pin = &priv->pfc.info->pins[i];
 470                 break;
 471         }
 472
 473         if (!pin)
 474                 return -EINVAL;
 475
 476         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 477         cfg = &pmx->configs[idx];
 478
 479         if (cfg->type != PINMUX_TYPE_NONE)
 480                 return -EBUSY;
 481
 482         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 483 }
 484
 485 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 486                                   unsigned func_selector)
 487 {
 488         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 489         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 490         struct sh_pfc *pfc = &priv->pfc;
 491         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 492         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 493         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 494
 495         if (cfg->type != PINMUX_TYPE_NONE)
 496                 return -EBUSY;
 497
 498         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 499 }
 500
 501 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 502                                      unsigned func_selector)
 503 {
 504         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 505         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 506         struct sh_pfc *pfc = &priv->pfc;
 507         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 508         unsigned int i;
 509         int ret = 0;
 510
 511         for (i = 0; i < grp->nr_pins; ++i) {
 512                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 513                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 514
 515                 if (cfg->type != PINMUX_TYPE_NONE) {
 516                         ret = -EBUSY;
 517                         goto done;
 518                 }
 519         }
 520
 521         for (i = 0; i < grp->nr_pins; ++i) {
 522                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 523                 if (ret < 0)
 524                         break;
 525         }
 526
 527 done:
 528         return ret;
 529 }
 530 #if CONFIG_IS_ENABLED(PINCONF)
 531 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 532         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 533         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 534         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 535         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 536         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 537 };
 538
 539 static void __iomem *
 540 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 541                                        unsigned int *offset, unsigned int *size)
 542 {
 543         const struct pinmux_drive_reg_field *field;
 544         const struct pinmux_drive_reg *reg;
 545         unsigned int i;
 546
 547         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 548                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 549                         field = &reg->fields[i];
 550
 551                         if (field->size && field->pin == pin) {
 552                                 *offset = field->offset;
 553                                 *size = field->size;
 554
 555                                 return (void __iomem *)(uintptr_t)reg->reg;
 556                         }
 557                 }
 558         }
 559
 560         return NULL;
 561 }
 562
 563 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 564                                              unsigned int pin, u16 strength)
 565 {
 566         unsigned int offset;
 567         unsigned int size;
 568         unsigned int step;
 569         void __iomem *reg;
 570         void __iomem *unlock_reg =
 571                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 572         u32 val;
 573
 574         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 575         if (!reg)
 576                 return -EINVAL;
 577
 578         step = size == 2 ? 6 : 3;
 579
 580         if (strength < step || strength > 24)
 581                 return -EINVAL;
 582
 583         /* Convert the value from mA based on a full drive strength value of
 584          * 24mA. We can make the full value configurable later if needed.
 585          */
 586         strength = strength / step - 1;
 587
 588         val = sh_pfc_read_raw_reg(reg, 32);
 589         val &= ~GENMASK(offset + size - 1, offset);
 590         val |= strength << offset;
 591
 592         if (unlock_reg)
 593                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 594
 595         sh_pfc_write_raw_reg(reg, 32, val);
 596
 597         return 0;
 598 }
 599
 600 /* Check whether the requested parameter is supported for a pin. */
 601 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 602                                     unsigned int param)
 603 {
 604         int idx = sh_pfc_get_pin_index(pfc, _pin);
 605         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 606
 607         switch (param) {
 608         case PIN_CONFIG_BIAS_DISABLE:
 609                 return pin->configs &
 610                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 611
 612         case PIN_CONFIG_BIAS_PULL_UP:
 613                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 614
 615         case PIN_CONFIG_BIAS_PULL_DOWN:
 616                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 617
 618         case PIN_CONFIG_DRIVE_STRENGTH:
 619                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 620
 621         case PIN_CONFIG_POWER_SOURCE:
 622                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 623
 624         default:
 625                 return false;
 626         }
 627 }
 628
 629 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 630                               unsigned int param, unsigned int arg)
 631 {
 632         struct sh_pfc *pfc = pmx->pfc;
 633         void __iomem *pocctrl;
 634         void __iomem *unlock_reg =
 635                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 636         u32 addr, val;
 637         int bit, ret;
 638
 639         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 640                 return -ENOTSUPP;
 641
 642         switch (param) {
 643         case PIN_CONFIG_BIAS_PULL_UP:
 644         case PIN_CONFIG_BIAS_PULL_DOWN:
 645         case PIN_CONFIG_BIAS_DISABLE:
 646                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 647                         return -ENOTSUPP;
 648
 649                 pfc->info->ops->set_bias(pfc, _pin, param);
 650
 651                 break;
 652
 653         case PIN_CONFIG_DRIVE_STRENGTH:
 654                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 655                 if (ret < 0)
 656                         return ret;
 657
 658                 break;
 659
 660         case PIN_CONFIG_POWER_SOURCE:
 661                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 662                         return -ENOTSUPP;
 663
 664                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 665                 if (bit < 0) {
 666                         printf("invalid pin %#x", _pin);
 667                         return bit;
 668                 }
 669
 670                 if (arg != 1800 && arg != 3300)
 671                         return -EINVAL;
 672
 673                 pocctrl = (void __iomem *)(uintptr_t)addr;
 674
 675                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 676                 if (arg == 3300)
 677                         val |= BIT(bit);
 678                 else
 679                         val &= ~BIT(bit);
 680
 681                 if (unlock_reg)
 682                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 683
 684                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 685
 686                 break;
 687
 688         default:
 689                 return -ENOTSUPP;
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 696                                   unsigned int pin_selector,
 697                                   unsigned int param, unsigned int arg)
 698 {
 699         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 700         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 701         struct sh_pfc *pfc = &priv->pfc;
 702         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 703
 704         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 705
 706         return 0;
 707 }
 708
 709 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 710                                       unsigned int group_selector,
 711                                       unsigned int param, unsigned int arg)
 712 {
 713         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 714         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 715         struct sh_pfc *pfc = &priv->pfc;
 716         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 717         unsigned int i;
 718
 719         for (i = 0; i < grp->nr_pins; i++)
 720                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 721
 722         return 0;
 723 }
 724 #endif
 725
 726 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 727         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 728         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 729         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 730         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 731         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 732         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 733
 734 #if CONFIG_IS_ENABLED(PINCONF)
 735         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 736         .pinconf_params         = sh_pfc_pinconf_params,
 737         .pinconf_set            = sh_pfc_pinconf_pin_set,
 738         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 739 #endif
 740         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 741         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 742         .set_state              = pinctrl_generic_set_state,
 743 };
 744
 745 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 746 {
 747         unsigned int i;
 748
 749         /* Allocate and initialize the pins and configs arrays. */
 750         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 751                                     GFP_KERNEL);
 752         if (unlikely(!pmx->configs))
 753                 return -ENOMEM;
 754
 755         for (i = 0; i < pfc->info->nr_pins; ++i) {
 756                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 757                 cfg->type = PINMUX_TYPE_NONE;
 758         }
 759
 760         return 0;
 761 }
 762
 763
 764 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 765 {
 766         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 767         enum sh_pfc_model model = dev_get_driver_data(dev);
 768         fdt_addr_t base;
 769
 770         base = devfdt_get_addr(dev);
 771         if (base == FDT_ADDR_T_NONE)
 772                 return -EINVAL;
 773
 774         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 775         if (!priv->pfc.regs)
 776                 return -ENOMEM;
 777
 778 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 779         if (model == SH_PFC_R8A7790)
 780                 priv->pfc.info = &r8a7790_pinmux_info;
 781 #endif
 782 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 783         if (model == SH_PFC_R8A7791)
 784                 priv->pfc.info = &r8a7791_pinmux_info;
 785 #endif
 786 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 787         if (model == SH_PFC_R8A7792)
 788                 priv->pfc.info = &r8a7792_pinmux_info;
 789 #endif
 790 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 791         if (model == SH_PFC_R8A7793)
 792                 priv->pfc.info = &r8a7793_pinmux_info;
 793 #endif
 794 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 795         if (model == SH_PFC_R8A7794)
 796                 priv->pfc.info = &r8a7794_pinmux_info;
 797 #endif
 798 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 799         if (model == SH_PFC_R8A7795)
 800                 priv->pfc.info = &r8a7795_pinmux_info;
 801 #endif
 802 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 803         if (model == SH_PFC_R8A7796)
 804                 priv->pfc.info = &r8a7796_pinmux_info;
 805 #endif
 806 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 807         if (model == SH_PFC_R8A77970)
 808                 priv->pfc.info = &r8a77970_pinmux_info;
 809 #endif
 810 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 811         if (model == SH_PFC_R8A77995)
 812                 priv->pfc.info = &r8a77995_pinmux_info;
 813 #endif
 814
 815         priv->pmx.pfc = &priv->pfc;
 816         sh_pfc_init_ranges(&priv->pfc);
 817         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 818
 819         return 0;
 820 }
 821
 822 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 823 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 824         {
 825                 .compatible = "renesas,pfc-r8a7790",
 826                 .data = SH_PFC_R8A7790,
 827         },
 828 #endif
 829 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 830         {
 831                 .compatible = "renesas,pfc-r8a7791",
 832                 .data = SH_PFC_R8A7791,
 833         },
 834 #endif
 835 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 836         {
 837                 .compatible = "renesas,pfc-r8a7792",
 838                 .data = SH_PFC_R8A7792,
 839         },
 840 #endif
 841 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 842         {
 843                 .compatible = "renesas,pfc-r8a7793",
 844                 .data = SH_PFC_R8A7793,
 845         },
 846 #endif
 847 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 848         {
 849                 .compatible = "renesas,pfc-r8a7794",
 850                 .data = SH_PFC_R8A7794,
 851         },
 852 #endif
 853 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 854         {
 855                 .compatible = "renesas,pfc-r8a7795",
 856                 .data = SH_PFC_R8A7795,
 857         },
 858 #endif
 859 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 860         {
 861                 .compatible = "renesas,pfc-r8a7796",
 862                 .data = SH_PFC_R8A7796,
 863         }, {
 864                 .compatible = "renesas,pfc-r8a77965",
 865                 .data = SH_PFC_R8A7796,
 866         },
 867 #endif
 868 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 869         {
 870                 .compatible = "renesas,pfc-r8a77970",
 871                 .data = SH_PFC_R8A77970,
 872         },
 873 #endif
 874 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 875         {
 876                 .compatible = "renesas,pfc-r8a77995",
 877                 .data = SH_PFC_R8A77995,
 878         },
 879 #endif
 880         { },
 881 };
 882
 883 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 884         .name           = "sh_pfc_pinctrl",
 885         .id             = UCLASS_PINCTRL,
 886         .of_match       = sh_pfc_pinctrl_ids,
 887         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 888         .ops            = &sh_pfc_pinctrl_ops,
 889         .probe          = sh_pfc_pinctrl_probe,
 890 };