git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk322x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <errno.h>
   9 #include <syscon.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/grf_rk322x.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <dm/pinctrl.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /* GRF_GPIO0A_IOMUX */
  20 enum {
  21         GPIO0A7_SHIFT           = 14,
  22         GPIO0A7_MASK            = 3 << GPIO0A7_SHIFT,
  23         GPIO0A7_GPIO            = 0,
  24         GPIO0A7_I2C3_SDA,
  25         GPIO0A7_HDMI_DDCSDA,
  26
  27         GPIO0A6_SHIFT           = 12,
  28         GPIO0A6_MASK            = 3 << GPIO0A6_SHIFT,
  29         GPIO0A6_GPIO            = 0,
  30         GPIO0A6_I2C3_SCL,
  31         GPIO0A6_HDMI_DDCSCL,
  32
  33         GPIO0A3_SHIFT           = 6,
  34         GPIO0A3_MASK            = 3 << GPIO0A3_SHIFT,
  35         GPIO0A3_GPIO            = 0,
  36         GPIO0A3_I2C1_SDA,
  37         GPIO0A3_SDIO_CMD,
  38
  39         GPIO0A2_SHIFT           = 4,
  40         GPIO0A2_MASK            = 3 << GPIO0A2_SHIFT,
  41         GPIO0A2_GPIO            = 0,
  42         GPIO0A2_I2C1_SCL,
  43
  44         GPIO0A1_SHIFT           = 2,
  45         GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
  46         GPIO0A1_GPIO            = 0,
  47         GPIO0A1_I2C0_SDA,
  48
  49         GPIO0A0_SHIFT           = 0,
  50         GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
  51         GPIO0A0_GPIO            = 0,
  52         GPIO0A0_I2C0_SCL,
  53 };
  54
  55 /* GRF_GPIO0B_IOMUX */
  56 enum {
  57         GPIO0B7_SHIFT           = 14,
  58         GPIO0B7_MASK            = 3 << GPIO0B7_SHIFT,
  59         GPIO0B7_GPIO            = 0,
  60         GPIO0B7_HDMI_HDP,
  61
  62         GPIO0B6_SHIFT           = 12,
  63         GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
  64         GPIO0B6_GPIO            = 0,
  65         GPIO0B6_I2S_SDI,
  66         GPIO0B6_SPI_CSN0,
  67
  68         GPIO0B5_SHIFT           = 10,
  69         GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
  70         GPIO0B5_GPIO            = 0,
  71         GPIO0B5_I2S_SDO,
  72         GPIO0B5_SPI_RXD,
  73
  74         GPIO0B3_SHIFT           = 6,
  75         GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
  76         GPIO0B3_GPIO            = 0,
  77         GPIO0B3_I2S1_LRCKRX,
  78         GPIO0B3_SPI_TXD,
  79
  80         GPIO0B1_SHIFT           = 2,
  81         GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
  82         GPIO0B1_GPIO            = 0,
  83         GPIO0B1_I2S_SCLK,
  84         GPIO0B1_SPI_CLK,
  85
  86         GPIO0B0_SHIFT           = 0,
  87         GPIO0B0_MASK            = 3,
  88         GPIO0B0_GPIO            = 0,
  89         GPIO0B0_I2S_MCLK,
  90 };
  91
  92 /* GRF_GPIO0C_IOMUX */
  93 enum {
  94         GPIO0C4_SHIFT           = 8,
  95         GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
  96         GPIO0C4_GPIO            = 0,
  97         GPIO0C4_HDMI_CECSDA,
  98
  99         GPIO0C1_SHIFT           = 2,
 100         GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
 101         GPIO0C1_GPIO            = 0,
 102         GPIO0C1_UART0_RSTN,
 103         GPIO0C1_CLK_OUT1,
 104 };
 105
 106 /* GRF_GPIO0D_IOMUX */
 107 enum {
 108         GPIO0D6_SHIFT           = 12,
 109         GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
 110         GPIO0D6_GPIO            = 0,
 111         GPIO0D6_SDIO_PWREN,
 112         GPIO0D6_PWM11,
 113
 114         GPIO0D4_SHIFT           = 8,
 115         GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
 116         GPIO0D4_GPIO            = 0,
 117         GPIO0D4_PWM2,
 118
 119         GPIO0D3_SHIFT           = 6,
 120         GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
 121         GPIO0D3_GPIO            = 0,
 122         GPIO0D3_PWM1,
 123
 124         GPIO0D2_SHIFT           = 4,
 125         GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
 126         GPIO0D2_GPIO            = 0,
 127         GPIO0D2_PWM0,
 128 };
 129
 130 /* GRF_GPIO1A_IOMUX */
 131 enum {
 132         GPIO1A7_SHIFT           = 14,
 133         GPIO1A7_MASK            = 1,
 134         GPIO1A7_GPIO            = 0,
 135         GPIO1A7_SDMMC_WRPRT,
 136 };
 137
 138 /* GRF_GPIO1B_IOMUX */
 139 enum {
 140         GPIO1B7_SHIFT           = 14,
 141         GPIO1B7_MASK            = 3 << GPIO1B7_SHIFT,
 142         GPIO1B7_GPIO            = 0,
 143         GPIO1B7_SDMMC_CMD,
 144
 145         GPIO1B6_SHIFT           = 12,
 146         GPIO1B6_MASK            = 3 << GPIO1B6_SHIFT,
 147         GPIO1B6_GPIO            = 0,
 148         GPIO1B6_SDMMC_PWREN,
 149
 150         GPIO1B4_SHIFT           = 8,
 151         GPIO1B4_MASK            = 3 << GPIO1B4_SHIFT,
 152         GPIO1B4_GPIO            = 0,
 153         GPIO1B4_SPI_CSN1,
 154         GPIO1B4_PWM12,
 155
 156         GPIO1B3_SHIFT           = 6,
 157         GPIO1B3_MASK            = 3 << GPIO1B3_SHIFT,
 158         GPIO1B3_GPIO            = 0,
 159         GPIO1B3_UART1_RSTN,
 160         GPIO1B3_PWM13,
 161
 162         GPIO1B2_SHIFT           = 4,
 163         GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
 164         GPIO1B2_GPIO            = 0,
 165         GPIO1B2_UART1_SIN,
 166         GPIO1B2_UART21_SIN,
 167
 168         GPIO1B1_SHIFT           = 2,
 169         GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
 170         GPIO1B1_GPIO            = 0,
 171         GPIO1B1_UART1_SOUT,
 172         GPIO1B1_UART21_SOUT,
 173 };
 174
 175 /* GRF_GPIO1C_IOMUX */
 176 enum {
 177         GPIO1C7_SHIFT           = 14,
 178         GPIO1C7_MASK            = 3 << GPIO1C7_SHIFT,
 179         GPIO1C7_GPIO            = 0,
 180         GPIO1C7_NAND_CS3,
 181         GPIO1C7_EMMC_RSTNOUT,
 182
 183         GPIO1C6_SHIFT           = 12,
 184         GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
 185         GPIO1C6_GPIO            = 0,
 186         GPIO1C6_NAND_CS2,
 187         GPIO1C6_EMMC_CMD,
 188
 189         GPIO1C5_SHIFT           = 10,
 190         GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
 191         GPIO1C5_GPIO            = 0,
 192         GPIO1C5_SDMMC_D3,
 193         GPIO1C5_JTAG_TMS,
 194
 195         GPIO1C4_SHIFT           = 8,
 196         GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
 197         GPIO1C4_GPIO            = 0,
 198         GPIO1C4_SDMMC_D2,
 199         GPIO1C4_JTAG_TCK,
 200
 201         GPIO1C3_SHIFT           = 6,
 202         GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
 203         GPIO1C3_GPIO            = 0,
 204         GPIO1C3_SDMMC_D1,
 205         GPIO1C3_UART2_SIN,
 206
 207         GPIO1C2_SHIFT           = 4,
 208         GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT,
 209         GPIO1C2_GPIO            = 0,
 210         GPIO1C2_SDMMC_D0,
 211         GPIO1C2_UART2_SOUT,
 212
 213         GPIO1C1_SHIFT           = 2,
 214         GPIO1C1_MASK            = 3 << GPIO1C1_SHIFT,
 215         GPIO1C1_GPIO            = 0,
 216         GPIO1C1_SDMMC_DETN,
 217
 218         GPIO1C0_SHIFT           = 0,
 219         GPIO1C0_MASK            = 3 << GPIO1C0_SHIFT,
 220         GPIO1C0_GPIO            = 0,
 221         GPIO1C0_SDMMC_CLKOUT,
 222 };
 223
 224 /* GRF_GPIO1D_IOMUX */
 225 enum {
 226         GPIO1D7_SHIFT           = 14,
 227         GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
 228         GPIO1D7_GPIO            = 0,
 229         GPIO1D7_NAND_D7,
 230         GPIO1D7_EMMC_D7,
 231
 232         GPIO1D6_SHIFT           = 12,
 233         GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
 234         GPIO1D6_GPIO            = 0,
 235         GPIO1D6_NAND_D6,
 236         GPIO1D6_EMMC_D6,
 237
 238         GPIO1D5_SHIFT           = 10,
 239         GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
 240         GPIO1D5_GPIO            = 0,
 241         GPIO1D5_NAND_D5,
 242         GPIO1D5_EMMC_D5,
 243
 244         GPIO1D4_SHIFT           = 8,
 245         GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
 246         GPIO1D4_GPIO            = 0,
 247         GPIO1D4_NAND_D4,
 248         GPIO1D4_EMMC_D4,
 249
 250         GPIO1D3_SHIFT           = 6,
 251         GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
 252         GPIO1D3_GPIO            = 0,
 253         GPIO1D3_NAND_D3,
 254         GPIO1D3_EMMC_D3,
 255
 256         GPIO1D2_SHIFT           = 4,
 257         GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
 258         GPIO1D2_GPIO            = 0,
 259         GPIO1D2_NAND_D2,
 260         GPIO1D2_EMMC_D2,
 261
 262         GPIO1D1_SHIFT           = 2,
 263         GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
 264         GPIO1D1_GPIO            = 0,
 265         GPIO1D1_NAND_D1,
 266         GPIO1D1_EMMC_D1,
 267
 268         GPIO1D0_SHIFT           = 0,
 269         GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
 270         GPIO1D0_GPIO            = 0,
 271         GPIO1D0_NAND_D0,
 272         GPIO1D0_EMMC_D0,
 273 };
 274
 275 /* GRF_GPIO2A_IOMUX */
 276 enum {
 277         GPIO2A7_SHIFT           = 14,
 278         GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
 279         GPIO2A7_GPIO            = 0,
 280         GPIO2A7_NAND_DQS,
 281         GPIO2A7_EMMC_CLKOUT,
 282
 283         GPIO2A5_SHIFT           = 10,
 284         GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
 285         GPIO2A5_GPIO            = 0,
 286         GPIO2A5_NAND_WP,
 287         GPIO2A5_EMMC_PWREN,
 288
 289         GPIO2A4_SHIFT           = 8,
 290         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 291         GPIO2A4_GPIO            = 0,
 292         GPIO2A4_NAND_RDY,
 293         GPIO2A4_EMMC_CMD,
 294
 295         GPIO2A3_SHIFT           = 6,
 296         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 297         GPIO2A3_GPIO            = 0,
 298         GPIO2A3_NAND_RDN,
 299         GPIO2A4_SPI1_CSN1,
 300
 301         GPIO2A2_SHIFT           = 4,
 302         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 303         GPIO2A2_GPIO            = 0,
 304         GPIO2A2_NAND_WRN,
 305         GPIO2A4_SPI1_CSN0,
 306
 307         GPIO2A1_SHIFT           = 2,
 308         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 309         GPIO2A1_GPIO            = 0,
 310         GPIO2A1_NAND_CLE,
 311         GPIO2A1_SPI1_TXD,
 312
 313         GPIO2A0_SHIFT           = 0,
 314         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 315         GPIO2A0_GPIO            = 0,
 316         GPIO2A0_NAND_ALE,
 317         GPIO2A0_SPI1_RXD,
 318 };
 319
 320 /* GRF_GPIO2B_IOMUX */
 321 enum {
 322         GPIO2B7_SHIFT           = 14,
 323         GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
 324         GPIO2B7_GPIO            = 0,
 325         GPIO2B7_GMAC_RXER,
 326
 327         GPIO2B6_SHIFT           = 12,
 328         GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
 329         GPIO2B6_GPIO            = 0,
 330         GPIO2B6_GMAC_CLK,
 331         GPIO2B6_MAC_LINK,
 332
 333         GPIO2B5_SHIFT           = 10,
 334         GPIO2B5_MASK            = 3 << GPIO2B5_SHIFT,
 335         GPIO2B5_GPIO            = 0,
 336         GPIO2B5_GMAC_TXEN,
 337
 338         GPIO2B4_SHIFT           = 8,
 339         GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
 340         GPIO2B4_GPIO            = 0,
 341         GPIO2B4_GMAC_MDIO,
 342
 343         GPIO2B3_SHIFT           = 6,
 344         GPIO2B3_MASK            = 3 << GPIO2B3_SHIFT,
 345         GPIO2B3_GPIO            = 0,
 346         GPIO2B3_GMAC_RXCLK,
 347
 348         GPIO2B2_SHIFT           = 4,
 349         GPIO2B2_MASK            = 3 << GPIO2B2_SHIFT,
 350         GPIO2B2_GPIO            = 0,
 351         GPIO2B2_GMAC_CRS,
 352
 353         GPIO2B1_SHIFT           = 2,
 354         GPIO2B1_MASK            = 3 << GPIO2B1_SHIFT,
 355         GPIO2B1_GPIO            = 0,
 356         GPIO2B1_GMAC_TXCLK,
 357
 358         GPIO2B0_SHIFT           = 0,
 359         GPIO2B0_MASK            = 3 << GPIO2B0_SHIFT,
 360         GPIO2B0_GPIO            = 0,
 361         GPIO2B0_GMAC_RXDV,
 362         GPIO2B0_MAC_SPEED_IOUT,
 363 };
 364
 365 /* GRF_GPIO2C_IOMUX */
 366 enum {
 367         GPIO2C7_SHIFT           = 14,
 368         GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
 369         GPIO2C7_GPIO            = 0,
 370         GPIO2C7_GMAC_TXD3,
 371
 372         GPIO2C6_SHIFT           = 12,
 373         GPIO2C6_MASK            = 3 << GPIO2C6_SHIFT,
 374         GPIO2C6_GPIO            = 0,
 375         GPIO2C6_GMAC_TXD2,
 376
 377         GPIO2C5_SHIFT           = 10,
 378         GPIO2C5_MASK            = 3 << GPIO2C5_SHIFT,
 379         GPIO2C5_GPIO            = 0,
 380         GPIO2C5_I2C2_SCL,
 381         GPIO2C5_GMAC_RXD2,
 382
 383         GPIO2C4_SHIFT           = 8,
 384         GPIO2C4_MASK            = 3 << GPIO2C4_SHIFT,
 385         GPIO2C4_GPIO            = 0,
 386         GPIO2C4_I2C2_SDA,
 387         GPIO2C4_GMAC_RXD3,
 388
 389         GPIO2C3_SHIFT           = 6,
 390         GPIO2C3_MASK            = 3 << GPIO2C3_SHIFT,
 391         GPIO2C3_GPIO            = 0,
 392         GPIO2C3_GMAC_TXD0,
 393
 394         GPIO2C2_SHIFT           = 4,
 395         GPIO2C2_MASK            = 3 << GPIO2C2_SHIFT,
 396         GPIO2C2_GPIO            = 0,
 397         GPIO2C2_GMAC_TXD1,
 398
 399         GPIO2C1_SHIFT           = 2,
 400         GPIO2C1_MASK            = 3 << GPIO2C1_SHIFT,
 401         GPIO2C1_GPIO            = 0,
 402         GPIO2C1_GMAC_RXD0,
 403
 404         GPIO2C0_SHIFT           = 0,
 405         GPIO2C0_MASK            = 3 << GPIO2C0_SHIFT,
 406         GPIO2C0_GPIO            = 0,
 407         GPIO2C0_GMAC_RXD1,
 408 };
 409
 410 /* GRF_GPIO2D_IOMUX */
 411 enum {
 412         GPIO2D1_SHIFT           = 2,
 413         GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
 414         GPIO2D1_GPIO            = 0,
 415         GPIO2D1_GMAC_MDC,
 416
 417         GPIO2D0_SHIFT           = 0,
 418         GPIO2D0_MASK            = 3,
 419         GPIO2D0_GPIO            = 0,
 420         GPIO2D0_GMAC_COL,
 421 };
 422
 423 /* GRF_GPIO3C_IOMUX */
 424 enum {
 425         GPIO3C6_SHIFT           = 12,
 426         GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
 427         GPIO3C6_GPIO            = 0,
 428         GPIO3C6_DRV_VBUS1,
 429
 430         GPIO3C5_SHIFT           = 10,
 431         GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
 432         GPIO3C5_GPIO            = 0,
 433         GPIO3C5_PWM10,
 434
 435         GPIO3C1_SHIFT           = 2,
 436         GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
 437         GPIO3C1_GPIO            = 0,
 438         GPIO3C1_DRV_VBUS,
 439 };
 440
 441 /* GRF_GPIO3D_IOMUX */
 442 enum {
 443         GPIO3D2_SHIFT   = 4,
 444         GPIO3D2_MASK    = 3 << GPIO3D2_SHIFT,
 445         GPIO3D2_GPIO    = 0,
 446         GPIO3D2_PWM3,
 447 };
 448
 449 /* GRF_CON_IOMUX */
 450 enum {
 451         CON_IOMUX_GMACSEL_SHIFT = 15,
 452         CON_IOMUX_GMACSEL_MASK  = 1 << CON_IOMUX_GMACSEL_SHIFT,
 453         CON_IOMUX_GMACSEL_1     = 1,
 454         CON_IOMUX_UART1SEL_SHIFT        = 11,
 455         CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
 456         CON_IOMUX_UART2SEL_SHIFT        = 8,
 457         CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
 458         CON_IOMUX_UART2SEL_2    = 0,
 459         CON_IOMUX_UART2SEL_21,
 460         CON_IOMUX_EMMCSEL_SHIFT = 7,
 461         CON_IOMUX_EMMCSEL_MASK  = 1 << CON_IOMUX_EMMCSEL_SHIFT,
 462         CON_IOMUX_PWM3SEL_SHIFT = 3,
 463         CON_IOMUX_PWM3SEL_MASK  = 1 << CON_IOMUX_PWM3SEL_SHIFT,
 464         CON_IOMUX_PWM2SEL_SHIFT = 2,
 465         CON_IOMUX_PWM2SEL_MASK  = 1 << CON_IOMUX_PWM2SEL_SHIFT,
 466         CON_IOMUX_PWM1SEL_SHIFT = 1,
 467         CON_IOMUX_PWM1SEL_MASK  = 1 << CON_IOMUX_PWM1SEL_SHIFT,
 468         CON_IOMUX_PWM0SEL_SHIFT = 0,
 469         CON_IOMUX_PWM0SEL_MASK  = 1 << CON_IOMUX_PWM0SEL_SHIFT,
 470 };
 471
 472 /* GRF_GPIO2B_E */
 473 enum {
 474         GRF_GPIO2B0_E_SHIFT = 0,
 475         GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
 476         GRF_GPIO2B1_E_SHIFT = 2,
 477         GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
 478         GRF_GPIO2B3_E_SHIFT = 6,
 479         GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
 480         GRF_GPIO2B4_E_SHIFT = 8,
 481         GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
 482         GRF_GPIO2B5_E_SHIFT = 10,
 483         GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
 484         GRF_GPIO2B6_E_SHIFT = 12,
 485         GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
 486 };
 487
 488 /* GRF_GPIO2C_E */
 489 enum {
 490         GRF_GPIO2C0_E_SHIFT = 0,
 491         GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
 492         GRF_GPIO2C1_E_SHIFT = 2,
 493         GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
 494         GRF_GPIO2C2_E_SHIFT = 4,
 495         GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
 496         GRF_GPIO2C3_E_SHIFT = 6,
 497         GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
 498         GRF_GPIO2C4_E_SHIFT = 8,
 499         GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
 500         GRF_GPIO2C5_E_SHIFT = 10,
 501         GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
 502         GRF_GPIO2C6_E_SHIFT = 12,
 503         GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
 504         GRF_GPIO2C7_E_SHIFT = 14,
 505         GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
 506 };
 507
 508 /* GRF_GPIO2D_E */
 509 enum {
 510         GRF_GPIO2D1_E_SHIFT = 2,
 511         GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
 512 };
 513
 514 /* GPIO Bias drive strength settings */
 515 enum GPIO_BIAS {
 516         GPIO_BIAS_2MA = 0,
 517         GPIO_BIAS_4MA,
 518         GPIO_BIAS_8MA,
 519         GPIO_BIAS_12MA,
 520 };
 521
 522 struct rk322x_pinctrl_priv {
 523         struct rk322x_grf *grf;
 524 };
 525
 526 static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
 527 {
 528         u32 mux_con = readl(&grf->con_iomux);
 529
 530         switch (pwm_id) {
 531         case PERIPH_ID_PWM0:
 532                 if (mux_con & CON_IOMUX_PWM0SEL_MASK)
 533                         rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
 534                                      GPIO3C5_PWM10 << GPIO3C5_SHIFT);
 535                 else
 536                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
 537                                      GPIO0D2_PWM0 << GPIO0D2_SHIFT);
 538                 break;
 539         case PERIPH_ID_PWM1:
 540                 if (mux_con & CON_IOMUX_PWM1SEL_MASK)
 541                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
 542                                      GPIO0D6_PWM11 << GPIO0D6_SHIFT);
 543                 else
 544                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
 545                                      GPIO0D3_PWM1 << GPIO0D3_SHIFT);
 546                 break;
 547         case PERIPH_ID_PWM2:
 548                 if (mux_con & CON_IOMUX_PWM2SEL_MASK)
 549                         rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
 550                                      GPIO1B4_PWM12 << GPIO1B4_SHIFT);
 551                 else
 552                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
 553                                      GPIO0D4_PWM2 << GPIO0D4_SHIFT);
 554                 break;
 555         case PERIPH_ID_PWM3:
 556                 if (mux_con & CON_IOMUX_PWM3SEL_MASK)
 557                         rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
 558                                      GPIO1B3_PWM13 << GPIO1B3_SHIFT);
 559                 else
 560                         rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
 561                                      GPIO3D2_PWM3 << GPIO3D2_SHIFT);
 562                 break;
 563         default:
 564                 debug("pwm id = %d iomux error!\n", pwm_id);
 565                 break;
 566         }
 567 }
 568
 569 static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
 570 {
 571         switch (i2c_id) {
 572         case PERIPH_ID_I2C0:
 573                 rk_clrsetreg(&grf->gpio0a_iomux,
 574                              GPIO0A1_MASK | GPIO0A0_MASK,
 575                              GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
 576                              GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
 577
 578                 break;
 579         case PERIPH_ID_I2C1:
 580                 rk_clrsetreg(&grf->gpio0a_iomux,
 581                              GPIO0A3_MASK | GPIO0A2_MASK,
 582                              GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
 583                              GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
 584                 break;
 585         case PERIPH_ID_I2C2:
 586                 rk_clrsetreg(&grf->gpio2c_iomux,
 587                              GPIO2C5_MASK | GPIO2C4_MASK,
 588                              GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
 589                              GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
 590                 break;
 591         case PERIPH_ID_I2C3:
 592                 rk_clrsetreg(&grf->gpio0a_iomux,
 593                              GPIO0A7_MASK | GPIO0A6_MASK,
 594                              GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
 595                              GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
 596
 597                 break;
 598         }
 599 }
 600
 601 static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
 602 {
 603         switch (cs) {
 604         case 0:
 605                 rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
 606                              GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
 607                 break;
 608         case 1:
 609                 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
 610                              GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
 611                 break;
 612         }
 613         rk_clrsetreg(&grf->gpio0b_iomux,
 614                      GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
 615                      GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
 616                      GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
 617                      GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
 618 }
 619
 620 static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
 621 {
 622         u32 mux_con = readl(&grf->con_iomux);
 623
 624         switch (uart_id) {
 625         case PERIPH_ID_UART1:
 626                 if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
 627                         rk_clrsetreg(&grf->gpio1b_iomux,
 628                                      GPIO1B1_MASK | GPIO1B2_MASK,
 629                                      GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
 630                                      GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
 631                 break;
 632         case PERIPH_ID_UART2:
 633                 if (mux_con & CON_IOMUX_UART2SEL_MASK)
 634                         rk_clrsetreg(&grf->gpio1b_iomux,
 635                                      GPIO1B1_MASK | GPIO1B2_MASK,
 636                                      GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
 637                                      GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
 638                 else
 639                         rk_clrsetreg(&grf->gpio1c_iomux,
 640                                      GPIO1C3_MASK | GPIO1C2_MASK,
 641                                      GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
 642                                      GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
 643                 break;
 644         }
 645 }
 646
 647 static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
 648 {
 649         switch (mmc_id) {
 650         case PERIPH_ID_EMMC:
 651                 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
 652                              GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
 653                              GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
 654                              GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
 655                              GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
 656                              GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
 657                              GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
 658                              GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
 659                              GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
 660                 rk_clrsetreg(&grf->gpio2a_iomux,
 661                              GPIO2A5_MASK | GPIO2A7_MASK,
 662                              GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
 663                              GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
 664                 rk_clrsetreg(&grf->gpio1c_iomux,
 665                              GPIO1C6_MASK | GPIO1C7_MASK,
 666                              GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
 667                              GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
 668                 break;
 669         case PERIPH_ID_SDCARD:
 670                 rk_clrsetreg(&grf->gpio1b_iomux,
 671                              GPIO1B6_MASK | GPIO1B7_MASK,
 672                              GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
 673                              GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
 674                 rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
 675                              GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
 676                              GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
 677                              GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
 678                              GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
 679                              GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
 680                              GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
 681                 break;
 682         }
 683 }
 684
 685 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 686 static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
 687 {
 688         switch (gmac_id) {
 689         case PERIPH_ID_GMAC:
 690                 /* set rgmii pins mux */
 691                 rk_clrsetreg(&grf->gpio2b_iomux,
 692                              GPIO2B0_MASK |
 693                              GPIO2B1_MASK |
 694                              GPIO2B3_MASK |
 695                              GPIO2B4_MASK |
 696                              GPIO2B5_MASK |
 697                              GPIO2B6_MASK,
 698                              GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
 699                              GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
 700                              GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
 701                              GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
 702                              GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
 703                              GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
 704
 705                 rk_clrsetreg(&grf->gpio2c_iomux,
 706                              GPIO2C0_MASK |
 707                              GPIO2C1_MASK |
 708                              GPIO2C2_MASK |
 709                              GPIO2C3_MASK |
 710                              GPIO2C4_MASK |
 711                              GPIO2C5_MASK |
 712                              GPIO2C6_MASK |
 713                              GPIO2C7_MASK,
 714                              GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
 715                              GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
 716                              GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
 717                              GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
 718                              GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
 719                              GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
 720                              GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
 721                              GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
 722
 723                 rk_clrsetreg(&grf->gpio2d_iomux,
 724                              GPIO2D1_MASK,
 725                              GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
 726
 727                 /*
 728                  * set rgmii tx pins to 12ma drive-strength,
 729                  * clean others with 2ma.
 730                  */
 731                 rk_clrsetreg(&grf->gpio2_e[1],
 732                              GRF_GPIO2B0_E_MASK |
 733                              GRF_GPIO2B1_E_MASK |
 734                              GRF_GPIO2B3_E_MASK |
 735                              GRF_GPIO2B4_E_MASK |
 736                              GRF_GPIO2B5_E_MASK |
 737                              GRF_GPIO2B6_E_MASK,
 738                              GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
 739                              GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
 740                              GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
 741                              GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
 742                              GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
 743                              GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
 744
 745                 rk_clrsetreg(&grf->gpio2_e[2],
 746                              GRF_GPIO2C0_E_MASK |
 747                              GRF_GPIO2C1_E_MASK |
 748                              GRF_GPIO2C2_E_MASK |
 749                              GRF_GPIO2C3_E_MASK |
 750                              GRF_GPIO2C4_E_MASK |
 751                              GRF_GPIO2C5_E_MASK |
 752                              GRF_GPIO2C6_E_MASK |
 753                              GRF_GPIO2C7_E_MASK,
 754                              GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
 755                              GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
 756                              GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
 757                              GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
 758                              GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
 759                              GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
 760                              GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
 761                              GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
 762
 763                 rk_clrsetreg(&grf->gpio2_e[3],
 764                              GRF_GPIO2D1_E_MASK,
 765                              GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
 766                 break;
 767         default:
 768                 debug("gmac id = %d iomux error!\n", gmac_id);
 769                 break;
 770         }
 771 }
 772 #endif
 773
 774 static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
 775 {
 776         struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
 777
 778         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 779         switch (func) {
 780         case PERIPH_ID_PWM0:
 781         case PERIPH_ID_PWM1:
 782         case PERIPH_ID_PWM2:
 783         case PERIPH_ID_PWM3:
 784                 pinctrl_rk322x_pwm_config(priv->grf, func);
 785                 break;
 786         case PERIPH_ID_I2C0:
 787         case PERIPH_ID_I2C1:
 788         case PERIPH_ID_I2C2:
 789                 pinctrl_rk322x_i2c_config(priv->grf, func);
 790                 break;
 791         case PERIPH_ID_SPI0:
 792                 pinctrl_rk322x_spi_config(priv->grf, flags);
 793                 break;
 794         case PERIPH_ID_UART0:
 795         case PERIPH_ID_UART1:
 796         case PERIPH_ID_UART2:
 797                 pinctrl_rk322x_uart_config(priv->grf, func);
 798                 break;
 799         case PERIPH_ID_SDMMC0:
 800         case PERIPH_ID_SDMMC1:
 801                 pinctrl_rk322x_sdmmc_config(priv->grf, func);
 802                 break;
 803 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 804         case PERIPH_ID_GMAC:
 805                 pinctrl_rk322x_gmac_config(priv->grf, func);
 806                 break;
 807 #endif
 808         default:
 809                 return -EINVAL;
 810         }
 811
 812         return 0;
 813 }
 814
 815 static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
 816                                         struct udevice *periph)
 817 {
 818         u32 cell[3];
 819         int ret;
 820
 821         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 822                                    "interrupts", cell, ARRAY_SIZE(cell));
 823         if (ret < 0)
 824                 return -EINVAL;
 825
 826         switch (cell[1]) {
 827         case 12:
 828                 return PERIPH_ID_SDCARD;
 829         case 14:
 830                 return PERIPH_ID_EMMC;
 831         case 36:
 832                 return PERIPH_ID_I2C0;
 833         case 37:
 834                 return PERIPH_ID_I2C1;
 835         case 38:
 836                 return PERIPH_ID_I2C2;
 837         case 49:
 838                 return PERIPH_ID_SPI0;
 839         case 50:
 840                 return PERIPH_ID_PWM0;
 841         case 55:
 842                 return PERIPH_ID_UART0;
 843         case 56:
 844                 return PERIPH_ID_UART1;
 845         case 57:
 846                 return PERIPH_ID_UART2;
 847 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 848         case 24:
 849                 return PERIPH_ID_GMAC;
 850 #endif
 851         }
 852         return -ENOENT;
 853 }
 854
 855 static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
 856                                            struct udevice *periph)
 857 {
 858         int func;
 859
 860         func = rk322x_pinctrl_get_periph_id(dev, periph);
 861         if (func < 0)
 862                 return func;
 863         return rk322x_pinctrl_request(dev, func, 0);
 864 }
 865
 866 static struct pinctrl_ops rk322x_pinctrl_ops = {
 867         .set_state_simple       = rk322x_pinctrl_set_state_simple,
 868         .request        = rk322x_pinctrl_request,
 869         .get_periph_id  = rk322x_pinctrl_get_periph_id,
 870 };
 871
 872 static int rk322x_pinctrl_probe(struct udevice *dev)
 873 {
 874         struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
 875
 876         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 877         debug("%s: grf=%p\n", __func__, priv->grf);
 878         return 0;
 879 }
 880
 881 static const struct udevice_id rk322x_pinctrl_ids[] = {
 882         { .compatible = "rockchip,rk3228-pinctrl" },
 883         { }
 884 };
 885
 886 U_BOOT_DRIVER(pinctrl_rk3228) = {
 887         .name           = "pinctrl_rk3228",
 888         .id             = UCLASS_PINCTRL,
 889         .of_match       = rk322x_pinctrl_ids,
 890         .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
 891         .ops            = &rk322x_pinctrl_ops,
 892         .bind           = dm_scan_fdt_dev,
 893         .probe          = rk322x_pinctrl_probe,
 894 };