1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
7 * Author: Tor Krill tor@excito.com
14 #include <usb/ehci-ci.h>
17 #include <fdt_support.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
29 struct ehci_fsl_priv {
30 struct ehci_ctrl ehci;
36 static void set_txfifothresh(struct usb_ehci *, u32);
38 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
39 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
41 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
42 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
45 /* Check USB PHY clock valid */
46 static int usb_phy_clk_valid(struct usb_ehci *ehci)
48 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
49 in_be32(&ehci->prictrl))) {
50 printf("USB PHY clock invalid!\n");
58 static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
60 struct ehci_fsl_priv *priv = dev_get_priv(dev);
63 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
66 priv->phy_type = (char *)prop;
67 debug("phy_type %s\n", priv->phy_type);
73 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
75 struct usb_ehci *ehci = NULL;
76 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
79 ehci = (struct usb_ehci *)priv->hcd_base;
80 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
86 static const struct ehci_ops fsl_ehci_ops = {
87 .init_after_reset = ehci_fsl_init_after_reset,
90 static int ehci_fsl_probe(struct udevice *dev)
92 struct ehci_fsl_priv *priv = dev_get_priv(dev);
93 struct usb_ehci *ehci = NULL;
94 struct ehci_hccr *hccr;
95 struct ehci_hcor *hcor;
98 * Get the base address for EHCI controller from the device node
100 priv->hcd_base = devfdt_get_addr(dev);
101 if (priv->hcd_base == FDT_ADDR_T_NONE) {
102 debug("Can't get the EHCI register base address\n");
105 ehci = (struct usb_ehci *)priv->hcd_base;
106 hccr = (struct ehci_hccr *)(&ehci->caplength);
107 hcor = (struct ehci_hcor *)
108 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
110 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
113 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
114 (void *)hccr, (void *)hcor,
115 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
117 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
120 static const struct udevice_id ehci_usb_ids[] = {
121 { .compatible = "fsl-usb2-mph", },
122 { .compatible = "fsl-usb2-dr", },
126 U_BOOT_DRIVER(ehci_fsl) = {
129 .of_match = ehci_usb_ids,
130 .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
131 .probe = ehci_fsl_probe,
132 .remove = ehci_deregister,
133 .ops = &ehci_usb_ops,
134 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
135 .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
136 .flags = DM_FLAG_ALLOC_PRIV_DMA,
140 * Create the appropriate control structures to manage
141 * a new EHCI host controller.
143 * Excerpts from linux ehci fsl driver.
145 int ehci_hcd_init(int index, enum usb_init_type init,
146 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
148 struct usb_ehci *ehci = NULL;
152 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
155 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
158 printf("ERROR: wrong controller index!!\n");
162 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
163 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
164 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
166 return ehci_fsl_init(index, ehci, *hccr, *hcor);
170 * Destroy the appropriate control structures corresponding
171 * the the EHCI host controller.
173 int ehci_hcd_stop(int index)
180 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
181 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
183 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
184 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
187 const char *phy_type = NULL;
188 #ifndef CONFIG_DM_USB
190 char current_usb_controller[5];
192 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
197 if (has_erratum_a007075()) {
199 * A 5ms delay is needed after applying soft-reset to the
200 * controller to let external ULPI phy come out of reset.
201 * This delay needs to be added before re-initializing
202 * the controller after soft-resetting completes
207 /* Set to Host mode */
208 setbits_le32(&ehci->usbmode, CM_HOST);
210 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
211 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
216 phy_type = priv->phy_type;
218 memset(current_usb_controller, '\0', 5);
219 snprintf(current_usb_controller, sizeof(current_usb_controller),
222 if (hwconfig_sub(current_usb_controller, "phy_type"))
223 phy_type = hwconfig_subarg(current_usb_controller,
227 phy_type = env_get("usb_phy_type");
230 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
231 /* if none specified assume internal UTMI */
232 strcpy(usb_phy, "utmi");
235 printf("WARNING: USB phy type not defined !!\n");
240 if (!strncmp(phy_type, "utmi", 4)) {
241 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
242 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
244 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
246 udelay(1000); /* delay required for PHY Clk to appear */
248 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
249 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
252 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
254 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
255 CONTROL_REGISTER_W1C_MASK, USB_EN);
256 udelay(1000); /* delay required for PHY Clk to appear */
257 if (!usb_phy_clk_valid(ehci))
259 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
262 out_be32(&ehci->prictrl, 0x0000000c);
263 out_be32(&ehci->age_cnt_limit, 0x00000040);
264 out_be32(&ehci->sictrl, 0x00000001);
266 in_le32(&ehci->usbmode);
268 if (has_erratum_a007798())
269 set_txfifothresh(ehci, TXFIFOTHRESH);
271 if (has_erratum_a004477()) {
273 * When reset is issued while any ULPI transaction is ongoing
274 * then it may result to corruption of ULPI Function Control
275 * Register which eventually causes phy clock to enter low
276 * power mode which stops the clock. Thus delay is required
277 * before reset to let ongoing ULPI transaction complete.
285 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
286 * to counter DDR latencies in writing data into Tx buffer.
287 * This prevents Tx buffer from getting underrun
289 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
292 cmd = ehci_readl(&ehci->txfilltuning);
293 cmd &= ~TXFIFO_THRESH_MASK;
294 cmd |= TXFIFO_THRESH(txfifo_thresh);
295 ehci_writel(&ehci->txfilltuning, cmd);