git.sur5r.net Git - u-boot/blob - include/configs/MPC837XERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Kevin Lam <kevin.lam@freescale.com>
   4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
  17 #define CONFIG_MPC837XERDB      1
  18
  19 #define CONFIG_MISC_INIT_R
  20 #define CONFIG_HWCONFIG
  21
  22 /*
  23  * On-board devices
  24  */
  25 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  26 #define CONFIG_VSC7385_ENET
  27
  28 /*
  29  * System Clock Setup
  30  */
  31 #ifdef CONFIG_PCISLAVE
  32 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
  33 #else
  34 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  35 #define CONFIG_PCIE
  36 #endif
  37
  38 #ifndef CONFIG_SYS_CLK_FREQ
  39 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  40 #endif
  41
  42 /*
  43  * Hardware Reset Configuration Word
  44  */
  45 #define CONFIG_SYS_HRCW_LOW (\
  46         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  47         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  48         HRCWL_SVCOD_DIV_2 |\
  49         HRCWL_CSB_TO_CLKIN_5X1 |\
  50         HRCWL_CORE_TO_CSB_2X1)
  51
  52 #ifdef CONFIG_PCISLAVE
  53 #define CONFIG_SYS_HRCW_HIGH (\
  54         HRCWH_PCI_AGENT |\
  55         HRCWH_PCI1_ARBITER_DISABLE |\
  56         HRCWH_CORE_ENABLE |\
  57         HRCWH_FROM_0XFFF00100 |\
  58         HRCWH_BOOTSEQ_DISABLE |\
  59         HRCWH_SW_WATCHDOG_DISABLE |\
  60         HRCWH_ROM_LOC_LOCAL_16BIT |\
  61         HRCWH_RL_EXT_LEGACY |\
  62         HRCWH_TSEC1M_IN_RGMII |\
  63         HRCWH_TSEC2M_IN_RGMII |\
  64         HRCWH_BIG_ENDIAN |\
  65         HRCWH_LDP_CLEAR)
  66 #else
  67 #define CONFIG_SYS_HRCW_HIGH (\
  68         HRCWH_PCI_HOST |\
  69         HRCWH_PCI1_ARBITER_ENABLE |\
  70         HRCWH_CORE_ENABLE |\
  71         HRCWH_FROM_0X00000100 |\
  72         HRCWH_BOOTSEQ_DISABLE |\
  73         HRCWH_SW_WATCHDOG_DISABLE |\
  74         HRCWH_ROM_LOC_LOCAL_16BIT |\
  75         HRCWH_RL_EXT_LEGACY |\
  76         HRCWH_TSEC1M_IN_RGMII |\
  77         HRCWH_TSEC2M_IN_RGMII |\
  78         HRCWH_BIG_ENDIAN |\
  79         HRCWH_LDP_CLEAR)
  80 #endif
  81
  82 /* System performance - define the value i.e. CONFIG_SYS_XXX
  83 */
  84
  85 /* Arbiter Configuration Register */
  86 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  87 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  88
  89 /* System Priority Control Regsiter */
  90 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  91
  92 /* System Clock Configuration Register */
  93 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  94 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  95 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  96
  97 /*
  98  * System IO Config
  99  */
 100 #define CONFIG_SYS_SICRH                0x08200000
 101 #define CONFIG_SYS_SICRL                0x00000000
 102
 103 /*
 104  * Output Buffer Impedance
 105  */
 106 #define CONFIG_SYS_OBIR         0x30100000
 107
 108 /*
 109  * IMMR new address
 110  */
 111 #define CONFIG_SYS_IMMR         0xE0000000
 112
 113 /*
 114  * Device configurations
 115  */
 116
 117 /* Vitesse 7385 */
 118
 119 #ifdef CONFIG_VSC7385_ENET
 120
 121 #define CONFIG_TSEC2
 122
 123 /* The flash address and size of the VSC7385 firmware image */
 124 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 125 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 126
 127 #endif
 128
 129 /*
 130  * DDR Setup
 131  */
 132 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 133 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 134 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 135 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
 136 #define CONFIG_SYS_83XX_DDR_USES_CS0
 137
 138 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 139
 140 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 141 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 142
 143 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 144
 145 /*
 146  * Manually set up DDR parameters
 147  */
 148 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 149 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 150 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 151                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 152                                         | CSCONFIG_ROW_BIT_13 \
 153                                         | CSCONFIG_COL_BIT_10)
 154
 155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 156 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 157                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 158                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 159                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 160                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 161                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 162                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 163                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 164                                 /* 0x00260802 */ /* DDR400 */
 165 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 166                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 167                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 168                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 169                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 170                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 171                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 172                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 173                                 /* 0x3937d322 */
 174 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 175                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 176                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 177                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 178                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 179                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 180                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 181                                 /* 0x02984cc8 */
 182
 183 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 184                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 185                                 /* 0x06090100 */
 186
 187 #if defined(CONFIG_DDR_2T_TIMING)
 188 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 189                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 190                                         | SDRAM_CFG_32_BE \
 191                                         | SDRAM_CFG_2T_EN)
 192                                         /* 0x43088000 */
 193 #else
 194 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 195                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 196                                         /* 0x43000000 */
 197 #endif
 198 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 199 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 200                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 201                                         /* 0x04400442 */ /* DDR400 */
 202 #define CONFIG_SYS_DDR_MODE2            0x00000000
 203
 204 /*
 205  * Memory test
 206  */
 207 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 208 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 209 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 210
 211 /*
 212  * The reserved memory
 213  */
 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 215
 216 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 217 #define CONFIG_SYS_RAMBOOT
 218 #else
 219 #undef  CONFIG_SYS_RAMBOOT
 220 #endif
 221
 222 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 223 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 224
 225 /*
 226  * Initial RAM Base Address Setup
 227  */
 228 #define CONFIG_SYS_INIT_RAM_LOCK        1
 229 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 230 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 232                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 233
 234 /*
 235  * Local Bus Configuration & Clock Setup
 236  */
 237 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 238 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 239 #define CONFIG_SYS_LBC_LBCR             0x00000000
 240 #define CONFIG_FSL_ELBC         1
 241
 242 /*
 243  * FLASH on the Local Bus
 244  */
 245 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 246 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 247 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 248 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 249
 250 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 251 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 252 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 253
 254                                         /* Window base at flash base */
 255 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 256 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 257
 258 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 259                                 | BR_PS_16      /* 16 bit port */ \
 260                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 261                                 | BR_V)         /* valid */
 262 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 263                                 | OR_GPCM_XACS \
 264                                 | OR_GPCM_SCY_9 \
 265                                 | OR_GPCM_EHTR_SET \
 266                                 | OR_GPCM_EAD)
 267                                 /* 0xFF800191 */
 268
 269 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 270 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 271
 272 #undef  CONFIG_SYS_FLASH_CHECKSUM
 273 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 274 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 275
 276 /*
 277  * NAND Flash on the Local Bus
 278  */
 279 #define CONFIG_SYS_NAND_BASE    0xE0600000
 280 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 281                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 282                                 | BR_PS_8               /* 8 bit port */ \
 283                                 | BR_MS_FCM             /* MSEL = FCM */ \
 284                                 | BR_V)                 /* valid */
 285 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 286                                 | OR_FCM_CSCT \
 287                                 | OR_FCM_CST \
 288                                 | OR_FCM_CHT \
 289                                 | OR_FCM_SCY_1 \
 290                                 | OR_FCM_TRLX \
 291                                 | OR_FCM_EHTR)
 292 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 293 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 294
 295 /* Vitesse 7385 */
 296
 297 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 298
 299 #ifdef CONFIG_VSC7385_ENET
 300
 301 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 302                                         | BR_PS_8 \
 303                                         | BR_MS_GPCM \
 304                                         | BR_V)
 305                                         /* 0xF0000801 */
 306 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
 307                                         | OR_GPCM_CSNT \
 308                                         | OR_GPCM_XACS \
 309                                         | OR_GPCM_SCY_15 \
 310                                         | OR_GPCM_SETA \
 311                                         | OR_GPCM_TRLX_SET \
 312                                         | OR_GPCM_EHTR_SET \
 313                                         | OR_GPCM_EAD)
 314                                         /* 0xfffe09ff */
 315
 316                                         /* Access Base */
 317 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 318 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 319
 320 #endif
 321
 322 /*
 323  * Serial Port
 324  */
 325 #define CONFIG_CONS_INDEX       1
 326 #define CONFIG_SYS_NS16550_SERIAL
 327 #define CONFIG_SYS_NS16550_REG_SIZE     1
 328 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 329
 330 #define CONFIG_SYS_BAUDRATE_TABLE \
 331                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 332
 333 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 334 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 335
 336 /* SERDES */
 337 #define CONFIG_FSL_SERDES
 338 #define CONFIG_FSL_SERDES1      0xe3000
 339 #define CONFIG_FSL_SERDES2      0xe3100
 340
 341 /* I2C */
 342 #define CONFIG_SYS_I2C
 343 #define CONFIG_SYS_I2C_FSL
 344 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 345 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 346 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 347 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 348
 349 /*
 350  * Config on-board RTC
 351  */
 352 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 353 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 354
 355 /*
 356  * General PCI
 357  * Addresses are mapped 1-1.
 358  */
 359 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 360 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 361 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 362 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 363 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 364 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 365 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 366 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 367 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 368
 369 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 370 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 371 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 372
 373 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 374 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 375 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 376 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 377 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 378 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 379 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 380 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 381 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 382
 383 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 384 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 385 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 386 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 387 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 388 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 389 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 390 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 391 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 392
 393 #ifdef CONFIG_PCI
 394 #define CONFIG_PCI_INDIRECT_BRIDGE
 395
 396 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 397 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 398 #endif  /* CONFIG_PCI */
 399
 400 /*
 401  * TSEC
 402  */
 403 #ifdef CONFIG_TSEC_ENET
 404
 405 #define CONFIG_GMII                     /* MII PHY management */
 406
 407 #define CONFIG_TSEC1
 408
 409 #ifdef CONFIG_TSEC1
 410 #define CONFIG_HAS_ETH0
 411 #define CONFIG_TSEC1_NAME               "TSEC0"
 412 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 413 #define TSEC1_PHY_ADDR                  2
 414 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 415 #define TSEC1_PHYIDX                    0
 416 #endif
 417
 418 #ifdef CONFIG_TSEC2
 419 #define CONFIG_HAS_ETH1
 420 #define CONFIG_TSEC2_NAME               "TSEC1"
 421 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 422 #define TSEC2_PHY_ADDR                  0x1c
 423 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 424 #define TSEC2_PHYIDX                    0
 425 #endif
 426
 427 /* Options are: TSEC[0-1] */
 428 #define CONFIG_ETHPRIME                 "TSEC0"
 429
 430 #endif
 431
 432 /*
 433  * SATA
 434  */
 435 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 436 #define CONFIG_SATA1
 437 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 438 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 439 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 440 #define CONFIG_SATA2
 441 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 442 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 443 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 444
 445 #ifdef CONFIG_FSL_SATA
 446 #define CONFIG_LBA48
 447 #endif
 448
 449 /*
 450  * Environment
 451  */
 452 #ifndef CONFIG_SYS_RAMBOOT
 453         #define CONFIG_ENV_ADDR         \
 454                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 455         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 456         #define CONFIG_ENV_SIZE         0x4000
 457 #else
 458         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 459         #define CONFIG_ENV_SIZE         0x2000
 460 #endif
 461
 462 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 463 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 464
 465 /*
 466  * BOOTP options
 467  */
 468 #define CONFIG_BOOTP_BOOTFILESIZE
 469 #define CONFIG_BOOTP_BOOTPATH
 470 #define CONFIG_BOOTP_GATEWAY
 471 #define CONFIG_BOOTP_HOSTNAME
 472
 473 /*
 474  * Command line configuration.
 475  */
 476
 477 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 478 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 479
 480 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 481
 482 #ifdef CONFIG_MMC
 483 #define CONFIG_FSL_ESDHC
 484 #define CONFIG_FSL_ESDHC_PIN_MUX
 485 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 486 #endif
 487
 488 /*
 489  * Miscellaneous configurable options
 490  */
 491 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 492 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 493
 494 /*
 495  * For booting Linux, the board info and command line data
 496  * have to be in the first 256 MB of memory, since this is
 497  * the maximum mapped by the Linux kernel during initialization.
 498  */
 499 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 500 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 501
 502 /*
 503  * Core HID Setup
 504  */
 505 #define CONFIG_SYS_HID0_INIT    0x000000000
 506 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 507                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 508 #define CONFIG_SYS_HID2         HID2_HBE
 509
 510 /*
 511  * MMU Setup
 512  */
 513
 514 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 515
 516 /* DDR: cache cacheable */
 517 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 518 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 519
 520 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 521                                 | BATL_PP_RW \
 522                                 | BATL_MEMCOHERENCE)
 523 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 524                                 | BATU_BL_256M \
 525                                 | BATU_VS \
 526                                 | BATU_VP)
 527 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 528 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 529
 530 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 531                                 | BATL_PP_RW \
 532                                 | BATL_MEMCOHERENCE)
 533 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 534                                 | BATU_BL_256M \
 535                                 | BATU_VS \
 536                                 | BATU_VP)
 537 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 538 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 539
 540 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 541 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 542                                 | BATL_PP_RW \
 543                                 | BATL_CACHEINHIBIT \
 544                                 | BATL_GUARDEDSTORAGE)
 545 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 546                                 | BATU_BL_8M \
 547                                 | BATU_VS \
 548                                 | BATU_VP)
 549 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 550 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 551
 552 /* L2 Switch: cache-inhibit and guarded */
 553 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
 554                                 | BATL_PP_RW \
 555                                 | BATL_CACHEINHIBIT \
 556                                 | BATL_GUARDEDSTORAGE)
 557 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
 558                                 | BATU_BL_128K \
 559                                 | BATU_VS \
 560                                 | BATU_VP)
 561 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 562 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 563
 564 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 565 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 566                                 | BATL_PP_RW \
 567                                 | BATL_MEMCOHERENCE)
 568 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 569                                 | BATU_BL_32M \
 570                                 | BATU_VS \
 571                                 | BATU_VP)
 572 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 573                                 | BATL_PP_RW \
 574                                 | BATL_CACHEINHIBIT \
 575                                 | BATL_GUARDEDSTORAGE)
 576 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 577
 578 /* Stack in dcache: cacheable, no memory coherence */
 579 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 580 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 581                                 | BATU_BL_128K \
 582                                 | BATU_VS \
 583                                 | BATU_VP)
 584 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 585 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 586
 587 #ifdef CONFIG_PCI
 588 /* PCI MEM space: cacheable */
 589 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 590                                 | BATL_PP_RW \
 591                                 | BATL_MEMCOHERENCE)
 592 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 593                                 | BATU_BL_256M \
 594                                 | BATU_VS \
 595                                 | BATU_VP)
 596 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 597 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 598 /* PCI MMIO space: cache-inhibit and guarded */
 599 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 600                                 | BATL_PP_RW \
 601                                 | BATL_CACHEINHIBIT \
 602                                 | BATL_GUARDEDSTORAGE)
 603 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 604                                 | BATU_BL_256M \
 605                                 | BATU_VS \
 606                                 | BATU_VP)
 607 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 608 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 609 #else
 610 #define CONFIG_SYS_IBAT6L       (0)
 611 #define CONFIG_SYS_IBAT6U       (0)
 612 #define CONFIG_SYS_IBAT7L       (0)
 613 #define CONFIG_SYS_IBAT7U       (0)
 614 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 615 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 616 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 617 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 618 #endif
 619
 620 #if defined(CONFIG_CMD_KGDB)
 621 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 622 #endif
 623
 624 /*
 625  * Environment Configuration
 626  */
 627 #define CONFIG_ENV_OVERWRITE
 628
 629 #define CONFIG_HAS_FSL_DR_USB
 630 #define CONFIG_USB_EHCI_FSL
 631 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 632
 633 #define CONFIG_NETDEV           "eth1"
 634
 635 #define CONFIG_HOSTNAME         mpc837x_rdb
 636 #define CONFIG_ROOTPATH         "/nfsroot"
 637 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 638 #define CONFIG_BOOTFILE         "uImage"
 639                                 /* U-Boot image on TFTP server */
 640 #define CONFIG_UBOOTPATH        "u-boot.bin"
 641 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 642
 643                                 /* default location for tftp and bootm */
 644 #define CONFIG_LOADADDR         800000
 645
 646 #define CONFIG_EXTRA_ENV_SETTINGS \
 647         "netdev=" CONFIG_NETDEV "\0"                            \
 648         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 649         "tftpflash=tftp $loadaddr $uboot;"                              \
 650                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 651                         " +$filesize; " \
 652                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 653                         " +$filesize; " \
 654                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 655                         " $filesize; "  \
 656                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 657                         " +$filesize; " \
 658                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 659                         " $filesize\0"  \
 660         "fdtaddr=780000\0"                                              \
 661         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 662         "ramdiskaddr=1000000\0"                                         \
 663         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 664         "console=ttyS0\0"                                               \
 665         "setbootargs=setenv bootargs "                                  \
 666                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 667         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 668                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 669                                                         "$netdev:off "  \
 670                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 671
 672 #define CONFIG_NFSBOOTCOMMAND                                           \
 673         "setenv rootdev /dev/nfs;"                                      \
 674         "run setbootargs;"                                              \
 675         "run setipargs;"                                                \
 676         "tftp $loadaddr $bootfile;"                                     \
 677         "tftp $fdtaddr $fdtfile;"                                       \
 678         "bootm $loadaddr - $fdtaddr"
 679
 680 #define CONFIG_RAMBOOTCOMMAND                                           \
 681         "setenv rootdev /dev/ram;"                                      \
 682         "run setbootargs;"                                              \
 683         "tftp $ramdiskaddr $ramdiskfile;"                               \
 684         "tftp $loadaddr $bootfile;"                                     \
 685         "tftp $fdtaddr $fdtfile;"                                       \
 686         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 687
 688 #endif  /* __CONFIG_H */