git.sur5r.net Git - u-boot/blob - include/configs/MPC8641HPCN.h

   1 /*
   2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   3  *
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * MPC8641HPCN board configuration file
  11  *
  12  * Make sure you change the MAC address and other network params first,
  13  * search for CONFIG_SERVERIP, etc. in this file.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_MP               1       /* support multiple processors */
  21 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  22 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  23
  24 /*
  25  * default CCSRBAR is at 0xff700000
  26  * assume U-Boot is less than 0.5MB
  27  */
  28
  29 #ifdef RUN_DIAG
  30 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  31 #endif
  32
  33 /*
  34  * virtual address to be used for temporary mappings.  There
  35  * should be 128k free at this VA.
  36  */
  37 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  38
  39 #define CONFIG_SYS_SRIO
  40 #define CONFIG_SRIO1                    /* SRIO port 1 */
  41
  42 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  43 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  44 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  45 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  46
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49
  50 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  51 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  52 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  53
  54 #define CONFIG_ALTIVEC          1
  55
  56 /*
  57  * L2CR setup -- make sure this is right for your board!
  58  */
  59 #define CONFIG_SYS_L2
  60 #define L2_INIT         0
  61 #define L2_ENABLE       (L2CR_L2E)
  62
  63 #ifndef CONFIG_SYS_CLK_FREQ
  64 #ifndef __ASSEMBLY__
  65 extern unsigned long get_board_sys_clk(unsigned long dummy);
  66 #endif
  67 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  68 #endif
  69
  70 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  71 #define CONFIG_SYS_MEMTEST_END          0x00400000
  72
  73 /*
  74  * With the exception of PCI Memory and Rapid IO, most devices will simply
  75  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  76  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  77  */
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  80 #else
  81 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  82 #endif
  83
  84 /*
  85  * Base addresses -- Note these are effective addresses where the
  86  * actual resources get mapped (not physical addresses)
  87  */
  88 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  89 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  90
  91 /* Physical addresses */
  92 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  93 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  94 #define CONFIG_SYS_CCSRBAR_PHYS \
  95         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  96                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  97
  98 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  99
 100 /*
 101  * DDR Setup
 102  */
 103 #define CONFIG_FSL_DDR_INTERACTIVE
 104 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 105 #define CONFIG_DDR_SPD
 106
 107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 108 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 109
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 112 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 113 #define CONFIG_VERY_BIG_RAM
 114
 115 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 116 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 117
 118 /*
 119  * I2C addresses of SPD EEPROMs
 120  */
 121 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 122 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 123 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 124 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 125
 126 /*
 127  * These are used when DDR doesn't use SPD.
 128  */
 129 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 131 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 132 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 133 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 134 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 135 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 136 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 137 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 138 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 139 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 140 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 141 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 142 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 143 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 144 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 145
 146 #define CONFIG_ID_EEPROM
 147 #define CONFIG_SYS_I2C_EEPROM_NXID
 148 #define CONFIG_ID_EEPROM
 149 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 151
 152 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 153 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 154 #define CONFIG_SYS_FLASH_BASE_PHYS \
 155         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 156                             CONFIG_SYS_PHYS_ADDR_HIGH)
 157
 158 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 159
 160 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 161                                  | 0x00001001)  /* port size 16bit */
 162 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 163
 164 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 165                                  | 0x00001001)  /* port size 16bit */
 166 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 167
 168 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 169                                  | 0x00000801) /* port size 8bit */
 170 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 171
 172 /*
 173  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 174  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 175  * required for the smallest BAT mapping, so there's a 64k hole.
 176  */
 177 #define CONFIG_SYS_LBC_BASE             0xffde0000
 178 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 179
 180 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 181 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 182 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 183 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 184                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 185 #define PIXIS_SIZE              0x00008000      /* 32k */
 186 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 187 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 188 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 189 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 190 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 191 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 192 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 193 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 194 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 195 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 196 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 197 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 198 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 199 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 200 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 201 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 202 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 203
 204 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 205 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 206 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 207
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 210
 211 #undef  CONFIG_SYS_FLASH_CHECKSUM
 212 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 213 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 214 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 215 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 216
 217 #define CONFIG_FLASH_CFI_DRIVER
 218 #define CONFIG_SYS_FLASH_CFI
 219 #define CONFIG_SYS_FLASH_EMPTY_INFO
 220
 221 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 222 #define CONFIG_SYS_RAMBOOT
 223 #else
 224 #undef  CONFIG_SYS_RAMBOOT
 225 #endif
 226
 227 #if defined(CONFIG_SYS_RAMBOOT)
 228 #undef CONFIG_SPD_EEPROM
 229 #define CONFIG_SYS_SDRAM_SIZE   256
 230 #endif
 231
 232 #undef CONFIG_CLOCKS_IN_MHZ
 233
 234 #define CONFIG_SYS_INIT_RAM_LOCK        1
 235 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 236 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 237 #else
 238 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 239 #endif
 240 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 241
 242 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 243 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 244
 245 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 246 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 247
 248 /* Serial Port */
 249 #define CONFIG_CONS_INDEX     1
 250 #define CONFIG_SYS_NS16550_SERIAL
 251 #define CONFIG_SYS_NS16550_REG_SIZE     1
 252 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 253
 254 #define CONFIG_SYS_BAUDRATE_TABLE  \
 255         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 256
 257 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 258 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 259
 260 /*
 261  * I2C
 262  */
 263 #define CONFIG_SYS_I2C
 264 #define CONFIG_SYS_I2C_FSL
 265 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 266 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 267 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 268 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 269
 270 /*
 271  * RapidIO MMU
 272  */
 273 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 274 #ifdef CONFIG_PHYS_64BIT
 275 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 276 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 277 #else
 278 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 279 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 280 #endif
 281 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 282         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 283                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 284 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 285
 286 /*
 287  * General PCI
 288  * Addresses are mapped 1-1.
 289  */
 290
 291 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 292 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 293 #ifdef CONFIG_PHYS_64BIT
 294 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 295 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 296 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 297 #else
 298 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 299 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 300 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 301 #endif
 302 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 303         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 304                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 305 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 306 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 307 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 308 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 309 #define CONFIG_SYS_PCIE1_IO_PHYS \
 310         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 311                             CONFIG_SYS_PHYS_ADDR_HIGH)
 312 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 313
 314 #ifdef CONFIG_PHYS_64BIT
 315 /*
 316  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 317  * This will increase the amount of PCI address space available for
 318  * for mapping RAM.
 319  */
 320 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 321 #else
 322 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 323                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 324 #endif
 325 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 326                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 327 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 328                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 329 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 330 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 331                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 332 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 333 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 334 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 335                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 336 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 337                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 338 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 339                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 340 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 341
 342 #if defined(CONFIG_PCI)
 343
 344 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 345
 346 #undef CONFIG_EEPRO100
 347 #undef CONFIG_TULIP
 348
 349 /************************************************************
 350  * USB support
 351  ************************************************************/
 352 #define CONFIG_PCI_OHCI                 1
 353 #define CONFIG_USB_OHCI_NEW             1
 354 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 355 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 356 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 357
 358 /*PCIE video card used*/
 359 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 360
 361 /*PCI video card used*/
 362 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 363
 364 /* video */
 365
 366 #if defined(CONFIG_VIDEO)
 367 #define CONFIG_BIOSEMU
 368 #define CONFIG_ATI_RADEON_FB
 369 #define CONFIG_VIDEO_LOGO
 370 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 371 #endif
 372
 373 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 374
 375 #ifdef CONFIG_SCSI_AHCI
 376 #define CONFIG_SATA_ULI5288
 377 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 378 #define CONFIG_SYS_SCSI_MAX_LUN 1
 379 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 380 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 381 #endif
 382
 383 #endif  /* CONFIG_PCI */
 384
 385 #if defined(CONFIG_TSEC_ENET)
 386
 387 #define CONFIG_MII              1       /* MII PHY management */
 388
 389 #define CONFIG_TSEC1            1
 390 #define CONFIG_TSEC1_NAME       "eTSEC1"
 391 #define CONFIG_TSEC2            1
 392 #define CONFIG_TSEC2_NAME       "eTSEC2"
 393 #define CONFIG_TSEC3            1
 394 #define CONFIG_TSEC3_NAME       "eTSEC3"
 395 #define CONFIG_TSEC4            1
 396 #define CONFIG_TSEC4_NAME       "eTSEC4"
 397
 398 #define TSEC1_PHY_ADDR          0
 399 #define TSEC2_PHY_ADDR          1
 400 #define TSEC3_PHY_ADDR          2
 401 #define TSEC4_PHY_ADDR          3
 402 #define TSEC1_PHYIDX            0
 403 #define TSEC2_PHYIDX            0
 404 #define TSEC3_PHYIDX            0
 405 #define TSEC4_PHYIDX            0
 406 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 407 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 408 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 409 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 410
 411 #define CONFIG_ETHPRIME         "eTSEC1"
 412
 413 #endif  /* CONFIG_TSEC_ENET */
 414
 415 #ifdef CONFIG_PHYS_64BIT
 416 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 417 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 418
 419 /* Put physical address into the BAT format */
 420 #define BAT_PHYS_ADDR(low, high) \
 421         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 422 /* Convert high/low pairs to actual 64-bit value */
 423 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 424 #else
 425 /* 32-bit systems just ignore the "high" bits */
 426 #define BAT_PHYS_ADDR(low, high)        (low)
 427 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 428 #endif
 429
 430 /*
 431  * BAT0         DDR
 432  */
 433 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 434 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 435
 436 /*
 437  * BAT1         LBC (PIXIS/CF)
 438  */
 439 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 440                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 441                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 442                                  BATL_GUARDEDSTORAGE)
 443 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 444                                  | BATU_VS | BATU_VP)
 445 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 446                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 447                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 448 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 449
 450 /* if CONFIG_PCI:
 451  * BAT2         PCIE1 and PCIE1 MEM
 452  * if CONFIG_RIO
 453  * BAT2         Rapidio Memory
 454  */
 455 #ifdef CONFIG_PCI
 456 #define CONFIG_PCI_INDIRECT_BRIDGE
 457 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 458                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 459                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 460                                  | BATL_GUARDEDSTORAGE)
 461 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 462                                  | BATU_VS | BATU_VP)
 463 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 464                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 465                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 466 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 467 #else /* CONFIG_RIO */
 468 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 469                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 470                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 471                                  BATL_GUARDEDSTORAGE)
 472 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 473                                  | BATU_VS | BATU_VP)
 474 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 475                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 476                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 477 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 478 #endif
 479
 480 /*
 481  * BAT3         CCSR Space
 482  */
 483 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 484                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 485                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 486                                  | BATL_GUARDEDSTORAGE)
 487 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 488                                  | BATU_VP)
 489 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 490                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 491                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 492 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 493
 494 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 495 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 496                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 497                                        | BATL_GUARDEDSTORAGE)
 498 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 499                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 500 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 501                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 502 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 503 #endif
 504
 505 /*
 506  * BAT4         PCIE1_IO and PCIE2_IO
 507  */
 508 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 509                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 510                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 511                                  | BATL_GUARDEDSTORAGE)
 512 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 513                                  | BATU_VS | BATU_VP)
 514 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 515                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 516                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 517 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 518
 519 /*
 520  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 521  */
 522 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 523 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 524 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 525 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 526
 527 /*
 528  * BAT6         FLASH
 529  */
 530 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 531                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 532                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 533                                  | BATL_GUARDEDSTORAGE)
 534 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 535                                  | BATU_VP)
 536 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 537                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 538                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 539 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 540
 541 /* Map the last 1M of flash where we're running from reset */
 542 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 543                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 544 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 545 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 546                                  | BATL_MEMCOHERENCE)
 547 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 548
 549 /*
 550  * BAT7         FREE - used later for tmp mappings
 551  */
 552 #define CONFIG_SYS_DBAT7L 0x00000000
 553 #define CONFIG_SYS_DBAT7U 0x00000000
 554 #define CONFIG_SYS_IBAT7L 0x00000000
 555 #define CONFIG_SYS_IBAT7U 0x00000000
 556
 557 /*
 558  * Environment
 559  */
 560 #ifndef CONFIG_SYS_RAMBOOT
 561     #define CONFIG_ENV_ADDR             \
 562                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 563     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 564 #else
 565     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 566 #endif
 567 #define CONFIG_ENV_SIZE         0x2000
 568
 569 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 570 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 571
 572 /*
 573  * BOOTP options
 574  */
 575 #define CONFIG_BOOTP_BOOTFILESIZE
 576
 577 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 578
 579 /*
 580  * Miscellaneous configurable options
 581  */
 582 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 583
 584 /*
 585  * For booting Linux, the board info and command line data
 586  * have to be in the first 8 MB of memory, since this is
 587  * the maximum mapped by the Linux kernel during initialization.
 588  */
 589 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 590 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 591
 592 #if defined(CONFIG_CMD_KGDB)
 593     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 594 #endif
 595
 596 /*
 597  * Environment Configuration
 598  */
 599
 600 #define CONFIG_HAS_ETH0         1
 601 #define CONFIG_HAS_ETH1         1
 602 #define CONFIG_HAS_ETH2         1
 603 #define CONFIG_HAS_ETH3         1
 604
 605 #define CONFIG_IPADDR           192.168.1.100
 606
 607 #define CONFIG_HOSTNAME         unknown
 608 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 609 #define CONFIG_BOOTFILE         "uImage"
 610 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 611
 612 #define CONFIG_SERVERIP         192.168.1.1
 613 #define CONFIG_GATEWAYIP        192.168.1.1
 614 #define CONFIG_NETMASK          255.255.255.0
 615
 616 /* default location for tftp and bootm */
 617 #define CONFIG_LOADADDR         0x10000000
 618
 619 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 620         "netdev=eth0\0"                                                 \
 621         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 622         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 623                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 624                         " +$filesize; " \
 625                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 626                         " +$filesize; " \
 627                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 628                         " $filesize; "  \
 629                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 630                         " +$filesize; " \
 631                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 632                         " $filesize\0"  \
 633         "consoledev=ttyS0\0"                                            \
 634         "ramdiskaddr=0x18000000\0"                                              \
 635         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 636         "fdtaddr=0x17c00000\0"                                          \
 637         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 638         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 639         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 640         "maxcpus=2"
 641
 642 #define CONFIG_NFSBOOTCOMMAND                                           \
 643         "setenv bootargs root=/dev/nfs rw "                             \
 644               "nfsroot=$serverip:$rootpath "                            \
 645               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 646               "console=$consoledev,$baudrate $othbootargs;"             \
 647         "tftp $loadaddr $bootfile;"                                     \
 648         "tftp $fdtaddr $fdtfile;"                                       \
 649         "bootm $loadaddr - $fdtaddr"
 650
 651 #define CONFIG_RAMBOOTCOMMAND                                           \
 652         "setenv bootargs root=/dev/ram rw "                             \
 653               "console=$consoledev,$baudrate $othbootargs;"             \
 654         "tftp $ramdiskaddr $ramdiskfile;"                               \
 655         "tftp $loadaddr $bootfile;"                                     \
 656         "tftp $fdtaddr $fdtfile;"                                       \
 657         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 658
 659 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 660
 661 #endif  /* __CONFIG_H */