git.sur5r.net Git - u-boot/blob - include/configs/MPC8641HPCN.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2006, 2010-2011 Freescale Semiconductor.
   4  *
   5  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   6  */
   7
   8 /*
   9  * MPC8641HPCN board configuration file
  10  *
  11  * Make sure you change the MAC address and other network params first,
  12  * search for CONFIG_SERVERIP, etc. in this file.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_MP               1       /* support multiple processors */
  20 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  21 #define CONFIG_ADDR_MAP         1       /* Use addr map */
  22
  23 /*
  24  * default CCSRBAR is at 0xff700000
  25  * assume U-Boot is less than 0.5MB
  26  */
  27
  28 #ifdef RUN_DIAG
  29 #define CONFIG_SYS_DIAG_ADDR         CONFIG_SYS_FLASH_BASE
  30 #endif
  31
  32 /*
  33  * virtual address to be used for temporary mappings.  There
  34  * should be 128k free at this VA.
  35  */
  36 #define CONFIG_SYS_SCRATCH_VA   0xe0000000
  37
  38 #define CONFIG_SYS_SRIO
  39 #define CONFIG_SRIO1                    /* SRIO port 1 */
  40
  41 #define CONFIG_PCIE1            1       /* PCIE controller 1 (ULI bridge) */
  42 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot) */
  43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  44 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  45
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  49 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  50 #define CONFIG_SYS_NUM_ADDR_MAP 8       /* Number of addr map slots = 8 dbats */
  51
  52 #define CONFIG_ALTIVEC          1
  53
  54 /*
  55  * L2CR setup -- make sure this is right for your board!
  56  */
  57 #define CONFIG_SYS_L2
  58 #define L2_INIT         0
  59 #define L2_ENABLE       (L2CR_L2E)
  60
  61 #ifndef CONFIG_SYS_CLK_FREQ
  62 #ifndef __ASSEMBLY__
  63 extern unsigned long get_board_sys_clk(unsigned long dummy);
  64 #endif
  65 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  66 #endif
  67
  68 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  69 #define CONFIG_SYS_MEMTEST_END          0x00400000
  70
  71 /*
  72  * With the exception of PCI Memory and Rapid IO, most devices will simply
  73  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
  74  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
  75  */
  76 #ifdef CONFIG_PHYS_64BIT
  77 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
  78 #else
  79 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
  80 #endif
  81
  82 /*
  83  * Base addresses -- Note these are effective addresses where the
  84  * actual resources get mapped (not physical addresses)
  85  */
  86 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
  87 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  88
  89 /* Physical addresses */
  90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  91 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    CONFIG_SYS_PHYS_ADDR_HIGH
  92 #define CONFIG_SYS_CCSRBAR_PHYS \
  93         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
  94                             CONFIG_SYS_CCSRBAR_PHYS_HIGH)
  95
  96 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
  97
  98 /*
  99  * DDR Setup
 100  */
 101 #define CONFIG_FSL_DDR_INTERACTIVE
 102 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 103 #define CONFIG_DDR_SPD
 104
 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 106 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 107
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 109 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 110 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 111 #define CONFIG_VERY_BIG_RAM
 112
 113 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 114 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 115
 116 /*
 117  * I2C addresses of SPD EEPROMs
 118  */
 119 #define SPD_EEPROM_ADDRESS1     0x51    /* CTLR 0 DIMM 0 */
 120 #define SPD_EEPROM_ADDRESS2     0x52    /* CTLR 0 DIMM 1 */
 121 #define SPD_EEPROM_ADDRESS3     0x53    /* CTLR 1 DIMM 0 */
 122 #define SPD_EEPROM_ADDRESS4     0x54    /* CTLR 1 DIMM 1 */
 123
 124 /*
 125  * These are used when DDR doesn't use SPD.
 126  */
 127 #define CONFIG_SYS_SDRAM_SIZE           256             /* DDR is 256MB */
 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
 129 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102      /* Enable, no interleaving */
 130 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 131 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 132 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
 133 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 134 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 135 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 136 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
 137 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 138 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 139 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 140 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 141 #define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 142 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
 143
 144 #define CONFIG_ID_EEPROM
 145 #define CONFIG_SYS_I2C_EEPROM_NXID
 146 #define CONFIG_ID_EEPROM
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 148 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 149
 150 #define CONFIG_SYS_FLASH_BASE           0xef800000     /* start of FLASH 8M */
 151 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW  CONFIG_SYS_FLASH_BASE
 152 #define CONFIG_SYS_FLASH_BASE_PHYS \
 153         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 154                             CONFIG_SYS_PHYS_ADDR_HIGH)
 155
 156 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
 157
 158 #define CONFIG_SYS_BR0_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 159                                  | 0x00001001)  /* port size 16bit */
 160 #define CONFIG_SYS_OR0_PRELIM   0xff806ff7      /* 8MB Boot Flash area*/
 161
 162 #define CONFIG_SYS_BR2_PRELIM   (BR_PHYS_ADDR(CF_BASE_PHYS)             \
 163                                  | 0x00001001)  /* port size 16bit */
 164 #define CONFIG_SYS_OR2_PRELIM   0xffffeff7      /* 32k Compact Flash */
 165
 166 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS)  \
 167                                  | 0x00000801) /* port size 8bit */
 168 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32k PIXIS area*/
 169
 170 /*
 171  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
 172  * The PIXIS and CF by themselves aren't large enough to take up the 128k
 173  * required for the smallest BAT mapping, so there's a 64k hole.
 174  */
 175 #define CONFIG_SYS_LBC_BASE             0xffde0000
 176 #define CONFIG_SYS_LBC_BASE_PHYS_LOW    CONFIG_SYS_LBC_BASE
 177
 178 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 179 #define PIXIS_BASE              (CONFIG_SYS_LBC_BASE + 0x00010000)
 180 #define PIXIS_BASE_PHYS_LOW     (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
 181 #define PIXIS_BASE_PHYS         PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
 182                                                     CONFIG_SYS_PHYS_ADDR_HIGH)
 183 #define PIXIS_SIZE              0x00008000      /* 32k */
 184 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 185 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 186 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 187 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 188 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch register */
 189 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 190 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 191 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 192 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 193 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 194 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 195 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 196 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 197 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 198 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 199 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 200 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 201
 202 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
 203 #define CF_BASE                 (PIXIS_BASE + PIXIS_SIZE)
 204 #define CF_BASE_PHYS            (PIXIS_BASE_PHYS + PIXIS_SIZE)
 205
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 207 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 208
 209 #undef  CONFIG_SYS_FLASH_CHECKSUM
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 212 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 213 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 214
 215 #define CONFIG_FLASH_CFI_DRIVER
 216 #define CONFIG_SYS_FLASH_CFI
 217 #define CONFIG_SYS_FLASH_EMPTY_INFO
 218
 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 220 #define CONFIG_SYS_RAMBOOT
 221 #else
 222 #undef  CONFIG_SYS_RAMBOOT
 223 #endif
 224
 225 #if defined(CONFIG_SYS_RAMBOOT)
 226 #undef CONFIG_SPD_EEPROM
 227 #define CONFIG_SYS_SDRAM_SIZE   256
 228 #endif
 229
 230 #undef CONFIG_CLOCKS_IN_MHZ
 231
 232 #define CONFIG_SYS_INIT_RAM_LOCK        1
 233 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 234 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 235 #else
 236 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 237 #endif
 238 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 239
 240 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 241 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 242
 243 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 244 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)    /* Reserved for malloc */
 245
 246 /* Serial Port */
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #define CONFIG_SYS_NS16550_REG_SIZE     1
 249 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 250
 251 #define CONFIG_SYS_BAUDRATE_TABLE  \
 252         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 253
 254 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 255 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 256
 257 /*
 258  * I2C
 259  */
 260 #define CONFIG_SYS_I2C
 261 #define CONFIG_SYS_I2C_FSL
 262 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 263 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 264 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 265 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 266
 267 /*
 268  * RapidIO MMU
 269  */
 270 #define CONFIG_SYS_SRIO1_MEM_BASE       0x80000000      /* base address */
 271 #ifdef CONFIG_PHYS_64BIT
 272 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   0x00000000
 273 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
 274 #else
 275 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW   CONFIG_SYS_SRIO1_MEM_BASE
 276 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
 277 #endif
 278 #define CONFIG_SYS_SRIO1_MEM_PHYS \
 279         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 280                             CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
 281 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 282
 283 /*
 284  * General PCI
 285  * Addresses are mapped 1-1.
 286  */
 287
 288 #define CONFIG_SYS_PCIE1_NAME           "ULI"
 289 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 290 #ifdef CONFIG_PHYS_64BIT
 291 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 292 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   0x00000000
 293 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x0000000c
 294 #else
 295 #define CONFIG_SYS_PCIE1_MEM_BUS        CONFIG_SYS_PCIE1_MEM_VIRT
 296 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW   CONFIG_SYS_PCIE1_MEM_VIRT
 297 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH  0x00000000
 298 #endif
 299 #define CONFIG_SYS_PCIE1_MEM_PHYS \
 300         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 301                             CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
 302 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 303 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 304 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 305 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW    CONFIG_SYS_PCIE1_IO_VIRT
 306 #define CONFIG_SYS_PCIE1_IO_PHYS \
 307         PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 308                             CONFIG_SYS_PHYS_ADDR_HIGH)
 309 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64K */
 310
 311 #ifdef CONFIG_PHYS_64BIT
 312 /*
 313  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
 314  * This will increase the amount of PCI address space available for
 315  * for mapping RAM.
 316  */
 317 #define CONFIG_SYS_PCIE2_MEM_BUS        CONFIG_SYS_PCIE1_MEM_BUS
 318 #else
 319 #define CONFIG_SYS_PCIE2_MEM_BUS        (CONFIG_SYS_PCIE1_MEM_BUS \
 320                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 321 #endif
 322 #define CONFIG_SYS_PCIE2_MEM_VIRT       (CONFIG_SYS_PCIE1_MEM_VIRT \
 323                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 324 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW   (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
 325                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 326 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH  CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
 327 #define CONFIG_SYS_PCIE2_MEM_PHYS       (CONFIG_SYS_PCIE1_MEM_PHYS \
 328                                          + CONFIG_SYS_PCIE1_MEM_SIZE)
 329 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 330 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 331 #define CONFIG_SYS_PCIE2_IO_VIRT        (CONFIG_SYS_PCIE1_IO_VIRT \
 332                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 333 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW    (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
 334                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 335 #define CONFIG_SYS_PCIE2_IO_PHYS        (CONFIG_SYS_PCIE1_IO_PHYS \
 336                                          + CONFIG_SYS_PCIE1_IO_SIZE)
 337 #define CONFIG_SYS_PCIE2_IO_SIZE        CONFIG_SYS_PCIE1_IO_SIZE
 338
 339 #if defined(CONFIG_PCI)
 340
 341 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 342
 343 #undef CONFIG_EEPRO100
 344 #undef CONFIG_TULIP
 345
 346 /************************************************************
 347  * USB support
 348  ************************************************************/
 349 #define CONFIG_PCI_OHCI                 1
 350 #define CONFIG_USB_OHCI_NEW             1
 351 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "ohci_pci"
 352 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 353 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 354
 355 /*PCIE video card used*/
 356 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 357
 358 /*PCI video card used*/
 359 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCIE1_IO_VIRT*/
 360
 361 /* video */
 362
 363 #if defined(CONFIG_VIDEO)
 364 #define CONFIG_BIOSEMU
 365 #define CONFIG_ATI_RADEON_FB
 366 #define CONFIG_VIDEO_LOGO
 367 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 368 #endif
 369
 370 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 371
 372 #ifdef CONFIG_SCSI_AHCI
 373 #define CONFIG_SATA_ULI5288
 374 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 375 #define CONFIG_SYS_SCSI_MAX_LUN 1
 376 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 377 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 378 #endif
 379
 380 #endif  /* CONFIG_PCI */
 381
 382 #if defined(CONFIG_TSEC_ENET)
 383
 384 #define CONFIG_MII              1       /* MII PHY management */
 385
 386 #define CONFIG_TSEC1            1
 387 #define CONFIG_TSEC1_NAME       "eTSEC1"
 388 #define CONFIG_TSEC2            1
 389 #define CONFIG_TSEC2_NAME       "eTSEC2"
 390 #define CONFIG_TSEC3            1
 391 #define CONFIG_TSEC3_NAME       "eTSEC3"
 392 #define CONFIG_TSEC4            1
 393 #define CONFIG_TSEC4_NAME       "eTSEC4"
 394
 395 #define TSEC1_PHY_ADDR          0
 396 #define TSEC2_PHY_ADDR          1
 397 #define TSEC3_PHY_ADDR          2
 398 #define TSEC4_PHY_ADDR          3
 399 #define TSEC1_PHYIDX            0
 400 #define TSEC2_PHYIDX            0
 401 #define TSEC3_PHYIDX            0
 402 #define TSEC4_PHYIDX            0
 403 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 404 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 405 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 406 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 407
 408 #define CONFIG_ETHPRIME         "eTSEC1"
 409
 410 #endif  /* CONFIG_TSEC_ENET */
 411
 412 #ifdef CONFIG_PHYS_64BIT
 413 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
 414 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
 415
 416 /* Put physical address into the BAT format */
 417 #define BAT_PHYS_ADDR(low, high) \
 418         (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
 419 /* Convert high/low pairs to actual 64-bit value */
 420 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
 421 #else
 422 /* 32-bit systems just ignore the "high" bits */
 423 #define BAT_PHYS_ADDR(low, high)        (low)
 424 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
 425 #endif
 426
 427 /*
 428  * BAT0         DDR
 429  */
 430 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 431 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 432
 433 /*
 434  * BAT1         LBC (PIXIS/CF)
 435  */
 436 #define CONFIG_SYS_DBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 437                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 438                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 439                                  BATL_GUARDEDSTORAGE)
 440 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
 441                                  | BATU_VS | BATU_VP)
 442 #define CONFIG_SYS_IBAT1L       (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
 443                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 444                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 445 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 446
 447 /* if CONFIG_PCI:
 448  * BAT2         PCIE1 and PCIE1 MEM
 449  * if CONFIG_RIO
 450  * BAT2         Rapidio Memory
 451  */
 452 #ifdef CONFIG_PCI
 453 #define CONFIG_PCI_INDIRECT_BRIDGE
 454 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 455                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 456                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 457                                  | BATL_GUARDEDSTORAGE)
 458 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
 459                                  | BATU_VS | BATU_VP)
 460 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
 461                                                CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
 462                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 463 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 464 #else /* CONFIG_RIO */
 465 #define CONFIG_SYS_DBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 466                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 467                                  | BATL_PP_RW | BATL_CACHEINHIBIT | \
 468                                  BATL_GUARDEDSTORAGE)
 469 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
 470                                  | BATU_VS | BATU_VP)
 471 #define CONFIG_SYS_IBAT2L       (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
 472                                                CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
 473                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 474 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 475 #endif
 476
 477 /*
 478  * BAT3         CCSR Space
 479  */
 480 #define CONFIG_SYS_DBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 481                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 482                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 483                                  | BATL_GUARDEDSTORAGE)
 484 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
 485                                  | BATU_VP)
 486 #define CONFIG_SYS_IBAT3L       (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
 487                                                CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
 488                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 489 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 490
 491 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 492 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 493                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 494                                        | BATL_GUARDEDSTORAGE)
 495 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 496                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 497 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 498                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 499 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 500 #endif
 501
 502 /*
 503  * BAT4         PCIE1_IO and PCIE2_IO
 504  */
 505 #define CONFIG_SYS_DBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 506                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 507                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 508                                  | BATL_GUARDEDSTORAGE)
 509 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
 510                                  | BATU_VS | BATU_VP)
 511 #define CONFIG_SYS_IBAT4L       (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
 512                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 513                                  | BATL_PP_RW | BATL_CACHEINHIBIT)
 514 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 515
 516 /*
 517  * BAT5         Init RAM for stack in the CPU DCache (no backing memory)
 518  */
 519 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 520 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 521 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 522 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 523
 524 /*
 525  * BAT6         FLASH
 526  */
 527 #define CONFIG_SYS_DBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 528                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 529                                  | BATL_PP_RW | BATL_CACHEINHIBIT \
 530                                  | BATL_GUARDEDSTORAGE)
 531 #define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
 532                                  | BATU_VP)
 533 #define CONFIG_SYS_IBAT6L       (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
 534                                                CONFIG_SYS_PHYS_ADDR_HIGH) \
 535                                  | BATL_PP_RW | BATL_MEMCOHERENCE)
 536 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 537
 538 /* Map the last 1M of flash where we're running from reset */
 539 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 540                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 541 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 542 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 543                                  | BATL_MEMCOHERENCE)
 544 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 545
 546 /*
 547  * BAT7         FREE - used later for tmp mappings
 548  */
 549 #define CONFIG_SYS_DBAT7L 0x00000000
 550 #define CONFIG_SYS_DBAT7U 0x00000000
 551 #define CONFIG_SYS_IBAT7L 0x00000000
 552 #define CONFIG_SYS_IBAT7U 0x00000000
 553
 554 /*
 555  * Environment
 556  */
 557 #ifndef CONFIG_SYS_RAMBOOT
 558     #define CONFIG_ENV_ADDR             \
 559                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 560     #define CONFIG_ENV_SECT_SIZE                0x10000 /* 64K(one sector) for env */
 561 #else
 562     #define CONFIG_ENV_ADDR             (CONFIG_SYS_MONITOR_BASE - 0x1000)
 563 #endif
 564 #define CONFIG_ENV_SIZE         0x2000
 565
 566 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 568
 569 /*
 570  * BOOTP options
 571  */
 572 #define CONFIG_BOOTP_BOOTFILESIZE
 573
 574 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 575
 576 /*
 577  * Miscellaneous configurable options
 578  */
 579 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 580
 581 /*
 582  * For booting Linux, the board info and command line data
 583  * have to be in the first 8 MB of memory, since this is
 584  * the maximum mapped by the Linux kernel during initialization.
 585  */
 586 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 587 #define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 588
 589 #if defined(CONFIG_CMD_KGDB)
 590     #define CONFIG_KGDB_BAUDRATE        230400  /* speed to run kgdb serial port */
 591 #endif
 592
 593 /*
 594  * Environment Configuration
 595  */
 596
 597 #define CONFIG_HAS_ETH0         1
 598 #define CONFIG_HAS_ETH1         1
 599 #define CONFIG_HAS_ETH2         1
 600 #define CONFIG_HAS_ETH3         1
 601
 602 #define CONFIG_IPADDR           192.168.1.100
 603
 604 #define CONFIG_HOSTNAME         "unknown"
 605 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 606 #define CONFIG_BOOTFILE         "uImage"
 607 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 608
 609 #define CONFIG_SERVERIP         192.168.1.1
 610 #define CONFIG_GATEWAYIP        192.168.1.1
 611 #define CONFIG_NETMASK          255.255.255.0
 612
 613 /* default location for tftp and bootm */
 614 #define CONFIG_LOADADDR         0x10000000
 615
 616 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 617         "netdev=eth0\0"                                                 \
 618         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 619         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 620                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 621                         " +$filesize; " \
 622                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 623                         " +$filesize; " \
 624                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 625                         " $filesize; "  \
 626                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 627                         " +$filesize; " \
 628                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 629                         " $filesize\0"  \
 630         "consoledev=ttyS0\0"                                            \
 631         "ramdiskaddr=0x18000000\0"                                              \
 632         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 633         "fdtaddr=0x17c00000\0"                                          \
 634         "fdtfile=mpc8641_hpcn.dtb\0"                                    \
 635         "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"                        \
 636         "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
 637         "maxcpus=2"
 638
 639 #define CONFIG_NFSBOOTCOMMAND                                           \
 640         "setenv bootargs root=/dev/nfs rw "                             \
 641               "nfsroot=$serverip:$rootpath "                            \
 642               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 643               "console=$consoledev,$baudrate $othbootargs;"             \
 644         "tftp $loadaddr $bootfile;"                                     \
 645         "tftp $fdtaddr $fdtfile;"                                       \
 646         "bootm $loadaddr - $fdtaddr"
 647
 648 #define CONFIG_RAMBOOTCOMMAND                                           \
 649         "setenv bootargs root=/dev/ram rw "                             \
 650               "console=$consoledev,$baudrate $othbootargs;"             \
 651         "tftp $ramdiskaddr $ramdiskfile;"                               \
 652         "tftp $loadaddr $bootfile;"                                     \
 653         "tftp $fdtaddr $fdtfile;"                                       \
 654         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 655
 656 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 657
 658 #endif  /* __CONFIG_H */