git.sur5r.net Git - u-boot/blob - include/configs/P1023RDB.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
   5  *           Chunhe Lan <Chunhe.Lan@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifndef CONFIG_SYS_TEXT_BASE
  14 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  15 #endif
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  23 #endif
  24
  25 /* High Level Configuration Options */
  26 #define CONFIG_MP               /* support multiple processors */
  27
  28 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
  29 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  30 #define CONFIG_PCIE2            /* PCIE controller 2 (slot 2) */
  31 #define CONFIG_PCIE3            /* PCIE controller 3 (slot 3) */
  32 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  33 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  34 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  35
  36 #ifndef __ASSEMBLY__
  37 extern unsigned long get_clock_freq(void);
  38 #endif
  39
  40 #define CONFIG_SYS_CLK_FREQ     66666666
  41 #define CONFIG_DDR_CLK_FREQ     CONFIG_SYS_CLK_FREQ
  42
  43 /*
  44  * These can be toggled for performance analysis, otherwise use default.
  45  */
  46 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  47 #define CONFIG_BTB                      /* toggle branch predition */
  48 #define CONFIG_HWCONFIG
  49
  50 #define CONFIG_ENABLE_36BIT_PHYS
  51
  52 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
  53 #define CONFIG_SYS_MEMTEST_END          0x02000000
  54
  55 /* Implement conversion of addresses in the LBC */
  56 #define CONFIG_SYS_LBC_LBCR             0x00000000
  57 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  58
  59 /* DDR Setup */
  60 #define CONFIG_VERY_BIG_RAM
  61 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  63
  64 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  65 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  66
  67 #define CONFIG_DDR_SPD
  68 #define CONFIG_FSL_DDR_INTERACTIVE
  69 #define CONFIG_SYS_SDRAM_SIZE           512u    /* DDR is 512M */
  70 #define CONFIG_SYS_SPD_BUS_NUM          0
  71 #define SPD_EEPROM_ADDRESS              0x50
  72 #define CONFIG_SYS_DDR_RAW_TIMING
  73
  74 /*
  75  * Memory map
  76  *
  77  * 0x0000_0000  0x1fff_ffff     DDR                     512M cacheable
  78  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  79  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  80  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  81  * 0xff00_0000  0xff3f_ffff     DPAA_QBMAN              4M cacheable
  82  * 0xff60_0000  0xff7f_ffff     CCSR                    2M non-cacheable
  83  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K cacheable TLB0
  84  *
  85  * Localbus non-cacheable
  86  *
  87  * 0xec00_0000  0xefff_ffff     NOR flash               64M non-cacheable
  88  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
  89  */
  90
  91 /*
  92  * Local Bus Definitions
  93  */
  94 #define CONFIG_SYS_FLASH_BASE           0xec000000 /* start of FLASH 64M */
  95 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  96
  97 #define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  98                                 | BR_PS_16 | BR_V)
  99 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 100
 101 #define CONFIG_FLASH_CFI_DRIVER
 102 #define CONFIG_SYS_FLASH_CFI
 103 #define CONFIG_SYS_FLASH_EMPTY_INFO
 104 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 105 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device */
 106 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 107 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 108
 109 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 110
 111 #define CONFIG_SYS_INIT_RAM_LOCK
 112 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 113 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* Size of used area in RAM */
 114 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 115                                         GENERATED_GBL_DATA_SIZE)
 116 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 117
 118 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)      /* Reserve 512 kB for Mon */
 119 #define CONFIG_SYS_MALLOC_LEN   (6 * 1024 * 1024) /* Reserved for malloc */
 120
 121 #define CONFIG_SYS_NAND_BASE            0xffa00000
 122 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 123
 124 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 125 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 126 #define CONFIG_NAND_FSL_ELBC
 127 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 128
 129 /* NAND flash config */
 130 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 131                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 132                                 | BR_PS_8               /* Port Size = 8bit */ \
 133                                 | BR_MS_FCM             /* MSEL = FCM */ \
 134                                 | BR_V)                 /* valid */
 135 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB         /* length 256K */ \
 136                                 | OR_FCM_PGS \
 137                                 | OR_FCM_CSCT \
 138                                 | OR_FCM_CST \
 139                                 | OR_FCM_CHT \
 140                                 | OR_FCM_SCY_1 \
 141                                 | OR_FCM_TRLX \
 142                                 | OR_FCM_EHTR)
 143
 144 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 145 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 146 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM
 147 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 148
 149 /* Serial Port */
 150 #define CONFIG_CONS_INDEX               1
 151 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 152 #define CONFIG_SYS_NS16550_SERIAL
 153 #define CONFIG_SYS_NS16550_REG_SIZE     1
 154 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 155
 156 #define CONFIG_SYS_BAUDRATE_TABLE       \
 157         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 158
 159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 161
 162 /* I2C */
 163 #define CONFIG_SYS_I2C
 164 #define CONFIG_SYS_I2C_FSL
 165 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 166 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 167 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 168 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 169 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 170 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 171
 172 /*
 173  * I2C2 EEPROM
 174  */
 175 #define CONFIG_ID_EEPROM
 176 #ifdef CONFIG_ID_EEPROM
 177 #define CONFIG_SYS_I2C_EEPROM_NXID
 178 #endif
 179 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 181 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 182
 183 /*
 184  * General PCI
 185  * Memory space is mapped 1-1, but I/O space must start from 0.
 186  */
 187
 188 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 189 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 190 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 191 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
 192 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
 193 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 194 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 195 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 196 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
 197 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 198
 199 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 200 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 201 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 202 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 203 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 204 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 205 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 206 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 207 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 208 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 209
 210 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 211 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 212 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 213 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 214 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 215 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 216 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 217 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 218 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 219 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 220
 221 #if defined(CONFIG_PCI)
 222 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 223 #endif  /* CONFIG_PCI */
 224
 225 /*
 226  * Environment
 227  */
 228 #define CONFIG_ENV_OVERWRITE
 229
 230 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 231 #define CONFIG_ENV_SIZE         0x2000
 232 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 233
 234 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 235 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 236
 237 /*
 238  * USB
 239  */
 240 #define CONFIG_HAS_FSL_DR_USB
 241 #ifdef CONFIG_HAS_FSL_DR_USB
 242 #ifdef CONFIG_USB_EHCI_HCD
 243 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 244 #define CONFIG_USB_EHCI_FSL
 245 #endif
 246 #endif
 247
 248 /*
 249  * Miscellaneous configurable options
 250  */
 251 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 252 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 253 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 254
 255 /*
 256  * For booting Linux, the board info and command line data
 257  * have to be in the first 64 MB of memory, since this is
 258  * the maximum mapped by the Linux kernel during initialization.
 259  */
 260 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)   /* Initial Memory map for Linux*/
 261 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)   /* Increase max gunzip size */
 262
 263 /*
 264  * Environment Configuration
 265  */
 266 #define CONFIG_BOOTFILE         "uImage"
 267 #define CONFIG_UBOOTPATH        (u-boot.bin) /* U-Boot image on TFTP server */
 268
 269 /* default location for tftp and bootm */
 270 #define CONFIG_LOADADDR         1000000
 271
 272 /* Qman/Bman */
 273 #define CONFIG_SYS_DPAA_QBMAN           /* support Q/Bman */
 274 #define CONFIG_SYS_QMAN_MEM_BASE        0xff000000
 275 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 276 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 277 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 278 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 279 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 280 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 281 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 282                                         CONFIG_SYS_QMAN_CENA_SIZE)
 283 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 284 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 285 #define CONFIG_SYS_BMAN_MEM_BASE        0xff200000
 286 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 287 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 288 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 289 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 290 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 291 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 292 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 293                                         CONFIG_SYS_BMAN_CENA_SIZE)
 294 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 295 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 296
 297 /* For FM */
 298 #define CONFIG_SYS_DPAA_FMAN
 299
 300 #ifdef CONFIG_SYS_DPAA_FMAN
 301 #define CONFIG_FMAN_ENET
 302 #define CONFIG_PHY_ATHEROS
 303 #endif
 304
 305 /* Default address of microcode for the Linux Fman driver */
 306 /* QE microcode/firmware address */
 307 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 308 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 309 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 310 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 311
 312 #ifdef CONFIG_FMAN_ENET
 313 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1
 314 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x2
 315
 316 #define CONFIG_SYS_TBIPA_VALUE  8
 317 #define CONFIG_MII              /* MII PHY management */
 318 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 319 #endif
 320
 321 #define CONFIG_EXTRA_ENV_SETTINGS       \
 322         "netdev=eth0\0"                                         \
 323         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 324         "loadaddr=1000000\0"                                    \
 325         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 326         "tftpflash=tftpboot $loadaddr $uboot; "                 \
 327                 "protect off $ubootaddr +$filesize; "           \
 328                 "erase $ubootaddr +$filesize; "                 \
 329                 "cp.b $loadaddr $ubootaddr $filesize; "         \
 330                 "protect on $ubootaddr +$filesize; "            \
 331                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 332         "consoledev=ttyS0\0"                                    \
 333         "ramdiskaddr=2000000\0"                                 \
 334         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 335         "fdtaddr=1e00000\0"                                     \
 336         "fdtfile=p1023rdb.dtb\0"                                \
 337         "othbootargs=ramdisk_size=600000\0"                     \
 338         "bdev=sda1\0"                                           \
 339         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 340
 341 #define CONFIG_HDBOOT                                   \
 342         "setenv bootargs root=/dev/$bdev rw "           \
 343         "console=$consoledev,$baudrate $othbootargs;"   \
 344         "tftp $loadaddr $bootfile;"                     \
 345         "tftp $fdtaddr $fdtfile;"                       \
 346         "bootm $loadaddr - $fdtaddr"
 347
 348 #define CONFIG_NFSBOOTCOMMAND                                           \
 349         "setenv bootargs root=/dev/nfs rw "                             \
 350         "nfsroot=$serverip:$rootpath "                                  \
 351         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 352         "console=$consoledev,$baudrate $othbootargs;"                   \
 353         "tftp $loadaddr $bootfile;"                                     \
 354         "tftp $fdtaddr $fdtfile;"                                       \
 355         "bootm $loadaddr - $fdtaddr"
 356
 357 #define CONFIG_RAMBOOTCOMMAND                                           \
 358         "setenv bootargs root=/dev/ram rw "                             \
 359         "console=$consoledev,$baudrate $othbootargs;"                   \
 360         "tftp $ramdiskaddr $ramdiskfile;"                               \
 361         "tftp $loadaddr $bootfile;"                                     \
 362         "tftp $fdtaddr $fdtfile;"                                       \
 363         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 364
 365 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 366
 367 #endif  /* __CONFIG_H */