git.sur5r.net Git - u-boot/blob - include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * P2041 RDB board configuration file
   8  * Also supports P2040 RDB
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifdef CONFIG_RAMBOOT_PBL
  14 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  15 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  16 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  17 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  18 #endif
  19
  20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  21 /* Set 1M boot space */
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  24                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  26 #endif
  27
  28 /* High Level Configuration Options */
  29 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  30
  31 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  32 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  33 #endif
  34
  35 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  36 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  37 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  38 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  39 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  40 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  41 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  42
  43 #define CONFIG_SYS_SRIO
  44 #define CONFIG_SRIO1                    /* SRIO port 1 */
  45 #define CONFIG_SRIO2                    /* SRIO port 2 */
  46 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 #define CONFIG_ENV_OVERWRITE
  50
  51 #ifndef CONFIG_MTD_NOR_FLASH
  52 #else
  53 #define CONFIG_FLASH_CFI_DRIVER
  54 #define CONFIG_SYS_FLASH_CFI
  55 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  56 #endif
  57
  58 #if defined(CONFIG_SPIFLASH)
  59         #define CONFIG_SYS_EXTRA_ENV_RELOC
  60         #define CONFIG_ENV_SPI_BUS              0
  61         #define CONFIG_ENV_SPI_CS               0
  62         #define CONFIG_ENV_SPI_MAX_HZ           10000000
  63         #define CONFIG_ENV_SPI_MODE             0
  64         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  65         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  66         #define CONFIG_ENV_SECT_SIZE            0x10000
  67 #elif defined(CONFIG_SDCARD)
  68         #define CONFIG_SYS_EXTRA_ENV_RELOC
  69         #define CONFIG_FSL_FIXED_MMC_LOCATION
  70         #define CONFIG_SYS_MMC_ENV_DEV          0
  71         #define CONFIG_ENV_SIZE                 0x2000
  72         #define CONFIG_ENV_OFFSET               (512 * 1658)
  73 #elif defined(CONFIG_NAND)
  74 #define CONFIG_SYS_EXTRA_ENV_RELOC
  75 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  76 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  77 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  78 #define CONFIG_ENV_ADDR         0xffe20000
  79 #define CONFIG_ENV_SIZE         0x2000
  80 #elif defined(CONFIG_ENV_IS_NOWHERE)
  81 #define CONFIG_ENV_SIZE         0x2000
  82 #else
  83         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
  84                         - CONFIG_ENV_SECT_SIZE)
  85         #define CONFIG_ENV_SIZE         0x2000
  86         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  87 #endif
  88
  89 #ifndef __ASSEMBLY__
  90 unsigned long get_board_sys_clk(unsigned long dummy);
  91 #endif
  92 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  93
  94 /*
  95  * These can be toggled for performance analysis, otherwise use default.
  96  */
  97 #define CONFIG_SYS_CACHE_STASHING
  98 #define CONFIG_BACKSIDE_L2_CACHE
  99 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 100 #define CONFIG_BTB                      /* toggle branch predition */
 101
 102 #define CONFIG_ENABLE_36BIT_PHYS
 103
 104 #ifdef CONFIG_PHYS_64BIT
 105 #define CONFIG_ADDR_MAP
 106 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 107 #endif
 108
 109 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 110 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 111 #define CONFIG_SYS_MEMTEST_END          0x00400000
 112
 113 /*
 114  *  Config the L3 Cache as L3 SRAM
 115  */
 116 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 117 #ifdef CONFIG_PHYS_64BIT
 118 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 119                 CONFIG_RAMBOOT_TEXT_BASE)
 120 #else
 121 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 122 #endif
 123 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 124 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 125
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_SYS_DCSRBAR              0xf0000000
 128 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 129 #endif
 130
 131 /* EEPROM */
 132 #define CONFIG_ID_EEPROM
 133 #define CONFIG_SYS_I2C_EEPROM_NXID
 134 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 135 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 137
 138 /*
 139  * DDR Setup
 140  */
 141 #define CONFIG_VERY_BIG_RAM
 142 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 143 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 144
 145 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 146 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 147
 148 #define CONFIG_DDR_SPD
 149
 150 #define CONFIG_SYS_SPD_BUS_NUM  0
 151 #define SPD_EEPROM_ADDRESS      0x52
 152 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 153
 154 /*
 155  * Local Bus Definitions
 156  */
 157
 158 /* Set the local bus clock 1/8 of platform clock */
 159 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 160
 161 /*
 162  * This board doesn't have a promjet connector.
 163  * However, it uses commone corenet board LAW and TLB.
 164  * It is necessary to use the same start address with proper offset.
 165  */
 166 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 167 #ifdef CONFIG_PHYS_64BIT
 168 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 169 #else
 170 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 171 #endif
 172
 173 #define CONFIG_SYS_FLASH_BR_PRELIM \
 174                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 175                 BR_PS_16 | BR_V)
 176 #define CONFIG_SYS_FLASH_OR_PRELIM \
 177                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 178                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 179
 180 #define CONFIG_FSL_CPLD
 181 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CPLD_BASE_PHYS          0xfffdf0000ull
 184 #else
 185 #define CPLD_BASE_PHYS          CPLD_BASE
 186 #endif
 187
 188 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 189 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 190
 191 #define PIXIS_LBMAP_SWITCH      7
 192 #define PIXIS_LBMAP_MASK        0xf0
 193 #define PIXIS_LBMAP_SHIFT       4
 194 #define PIXIS_LBMAP_ALTBANK     0x40
 195
 196 #define CONFIG_SYS_FLASH_QUIET_TEST
 197 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 203
 204 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 205
 206 #if defined(CONFIG_RAMBOOT_PBL)
 207 #define CONFIG_SYS_RAMBOOT
 208 #endif
 209
 210 #define CONFIG_NAND_FSL_ELBC
 211 /* Nand Flash */
 212 #ifdef CONFIG_NAND_FSL_ELBC
 213 #define CONFIG_SYS_NAND_BASE            0xffa00000
 214 #ifdef CONFIG_PHYS_64BIT
 215 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 216 #else
 217 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 218 #endif
 219
 220 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 221 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 222 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 223
 224 /* NAND flash config */
 225 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 226                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 227                                | BR_PS_8               /* Port Size = 8 bit */ \
 228                                | BR_MS_FCM             /* MSEL = FCM */ \
 229                                | BR_V)                 /* valid */
 230 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 231                                | OR_FCM_PGS            /* Large Page*/ \
 232                                | OR_FCM_CSCT \
 233                                | OR_FCM_CST \
 234                                | OR_FCM_CHT \
 235                                | OR_FCM_SCY_1 \
 236                                | OR_FCM_TRLX \
 237                                | OR_FCM_EHTR)
 238
 239 #ifdef CONFIG_NAND
 240 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 241 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 242 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 243 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 244 #else
 245 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 246 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 247 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 248 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 249 #endif
 250 #else
 251 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 252 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 253 #endif /* CONFIG_NAND_FSL_ELBC */
 254
 255 #define CONFIG_SYS_FLASH_EMPTY_INFO
 256 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 257 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 258
 259 #define CONFIG_MISC_INIT_R
 260
 261 #define CONFIG_HWCONFIG
 262
 263 /* define to use L1 as initial stack */
 264 #define CONFIG_L1_INIT_RAM
 265 #define CONFIG_SYS_INIT_RAM_LOCK
 266 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 267 #ifdef CONFIG_PHYS_64BIT
 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 270 /* The assembler doesn't like typecast */
 271 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 272         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 273           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 274 #else
 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 276 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 278 #endif
 279 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 280
 281 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 282                                         GENERATED_GBL_DATA_SIZE)
 283 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 284
 285 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 286 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 287
 288 /* Serial Port - controlled on board with jumper J8
 289  * open - index 2
 290  * shorted - index 1
 291  */
 292 #define CONFIG_SYS_NS16550_SERIAL
 293 #define CONFIG_SYS_NS16550_REG_SIZE     1
 294 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 295
 296 #define CONFIG_SYS_BAUDRATE_TABLE       \
 297         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 298
 299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 301 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 302 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 303
 304 /* I2C */
 305 #define CONFIG_SYS_I2C
 306 #define CONFIG_SYS_I2C_FSL
 307 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 308 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 309 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 310 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 311 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 312 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 313
 314 /*
 315  * RapidIO
 316  */
 317 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 318 #ifdef CONFIG_PHYS_64BIT
 319 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 320 #else
 321 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 322 #endif
 323 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 324
 325 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 326 #ifdef CONFIG_PHYS_64BIT
 327 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 328 #else
 329 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 330 #endif
 331 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 332
 333 /*
 334  * for slave u-boot IMAGE instored in master memory space,
 335  * PHYS must be aligned based on the SIZE
 336  */
 337 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 338 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 339 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 340 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 341 /*
 342  * for slave UCODE and ENV instored in master memory space,
 343  * PHYS must be aligned based on the SIZE
 344  */
 345 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 346 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 347 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 348
 349 /* slave core release by master*/
 350 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 351 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 352
 353 /*
 354  * SRIO_PCIE_BOOT - SLAVE
 355  */
 356 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 357 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 358 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 359                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 360 #endif
 361
 362 /*
 363  * eSPI - Enhanced SPI
 364  */
 365 #define CONFIG_SF_DEFAULT_SPEED         10000000
 366 #define CONFIG_SF_DEFAULT_MODE          0
 367
 368 /*
 369  * General PCI
 370  * Memory space is mapped 1-1, but I/O space must start from 0.
 371  */
 372
 373 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 374 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 375 #ifdef CONFIG_PHYS_64BIT
 376 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 377 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 378 #else
 379 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 380 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 381 #endif
 382 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 383 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 384 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 385 #ifdef CONFIG_PHYS_64BIT
 386 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 387 #else
 388 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 389 #endif
 390 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 391
 392 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 393 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 394 #ifdef CONFIG_PHYS_64BIT
 395 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 396 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 397 #else
 398 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 399 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 400 #endif
 401 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 402 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 403 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 404 #ifdef CONFIG_PHYS_64BIT
 405 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 406 #else
 407 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 408 #endif
 409 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 410
 411 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 412 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 413 #ifdef CONFIG_PHYS_64BIT
 414 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 415 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 416 #else
 417 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 418 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 419 #endif
 420 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 421 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 422 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 423 #ifdef CONFIG_PHYS_64BIT
 424 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 425 #else
 426 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 427 #endif
 428 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 429
 430 /* Qman/Bman */
 431 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 432 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 433 #ifdef CONFIG_PHYS_64BIT
 434 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 435 #else
 436 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 437 #endif
 438 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 439 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 440 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 441 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 442 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 443 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 444                                         CONFIG_SYS_BMAN_CENA_SIZE)
 445 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 446 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 447 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 448 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 449 #ifdef CONFIG_PHYS_64BIT
 450 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 451 #else
 452 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 453 #endif
 454 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 455 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 456 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 457 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 458 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 459 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 460                                         CONFIG_SYS_QMAN_CENA_SIZE)
 461 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 462 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 463
 464 #define CONFIG_SYS_DPAA_FMAN
 465 #define CONFIG_SYS_DPAA_PME
 466 /* Default address of microcode for the Linux Fman driver */
 467 #if defined(CONFIG_SPIFLASH)
 468 /*
 469  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 470  * env, so we got 0x110000.
 471  */
 472 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 473 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 474 #elif defined(CONFIG_SDCARD)
 475 /*
 476  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 477  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 478  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 479  */
 480 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 481 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 482 #elif defined(CONFIG_NAND)
 483 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 484 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 485 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 486 /*
 487  * Slave has no ucode locally, it can fetch this from remote. When implementing
 488  * in two corenet boards, slave's ucode could be stored in master's memory
 489  * space, the address can be mapped from slave TLB->slave LAW->
 490  * slave SRIO or PCIE outbound window->master inbound window->
 491  * master LAW->the ucode address in master's memory space.
 492  */
 493 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 494 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 495 #else
 496 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 497 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 498 #endif
 499 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 500 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 501
 502 #ifdef CONFIG_SYS_DPAA_FMAN
 503 #define CONFIG_FMAN_ENET
 504 #define CONFIG_PHYLIB_10G
 505 #define CONFIG_PHY_VITESSE
 506 #define CONFIG_PHY_TERANETICS
 507 #endif
 508
 509 #ifdef CONFIG_PCI
 510 #define CONFIG_PCI_INDIRECT_BRIDGE
 511
 512 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 513 #endif  /* CONFIG_PCI */
 514
 515 /* SATA */
 516 #define CONFIG_FSL_SATA_V2
 517
 518 #ifdef CONFIG_FSL_SATA_V2
 519 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 520 #define CONFIG_SATA1
 521 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 522 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 523 #define CONFIG_SATA2
 524 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 525 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 526
 527 #define CONFIG_LBA48
 528 #endif
 529
 530 #ifdef CONFIG_FMAN_ENET
 531 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 532 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 533 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 534 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 535 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 536
 537 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 538 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 539 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 540 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 541
 542 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 543
 544 #define CONFIG_SYS_TBIPA_VALUE  8
 545 #define CONFIG_MII              /* MII PHY management */
 546 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 547 #endif
 548
 549 /*
 550  * Environment
 551  */
 552 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 553 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 554
 555 /*
 556  * Command line configuration.
 557  */
 558
 559 /*
 560 * USB
 561 */
 562 #define CONFIG_HAS_FSL_DR_USB
 563 #define CONFIG_HAS_FSL_MPH_USB
 564
 565 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 566 #define CONFIG_USB_EHCI_FSL
 567 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 568 #endif
 569
 570 #ifdef CONFIG_MMC
 571 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 572 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 573 #endif
 574
 575 /*
 576  * Miscellaneous configurable options
 577  */
 578 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 579
 580 /*
 581  * For booting Linux, the board info and command line data
 582  * have to be in the first 64 MB of memory, since this is
 583  * the maximum mapped by the Linux kernel during initialization.
 584  */
 585 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 586 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 587
 588 #ifdef CONFIG_CMD_KGDB
 589 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 590 #endif
 591
 592 /*
 593  * Environment Configuration
 594  */
 595 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 596 #define CONFIG_BOOTFILE         "uImage"
 597 #define CONFIG_UBOOTPATH        u-boot.bin
 598
 599 /* default location for tftp and bootm */
 600 #define CONFIG_LOADADDR         1000000
 601
 602 #define __USB_PHY_TYPE  utmi
 603
 604 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 605         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 606         "bank_intlv=cs0_cs1\0"                                  \
 607         "netdev=eth0\0"                                         \
 608         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 609         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 610         "tftpflash=tftpboot $loadaddr $uboot && "               \
 611         "protect off $ubootaddr +$filesize && "                 \
 612         "erase $ubootaddr +$filesize && "                       \
 613         "cp.b $loadaddr $ubootaddr $filesize && "               \
 614         "protect on $ubootaddr +$filesize && "                  \
 615         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 616         "consoledev=ttyS0\0"                                    \
 617         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 618         "usb_dr_mode=host\0"                                    \
 619         "ramdiskaddr=2000000\0"                                 \
 620         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 621         "fdtaddr=1e00000\0"                                     \
 622         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 623         "bdev=sda3\0"
 624
 625 #define CONFIG_HDBOOT                                   \
 626         "setenv bootargs root=/dev/$bdev rw "           \
 627         "console=$consoledev,$baudrate $othbootargs;"   \
 628         "tftp $loadaddr $bootfile;"                     \
 629         "tftp $fdtaddr $fdtfile;"                       \
 630         "bootm $loadaddr - $fdtaddr"
 631
 632 #define CONFIG_NFSBOOTCOMMAND                   \
 633         "setenv bootargs root=/dev/nfs rw "     \
 634         "nfsroot=$serverip:$rootpath "          \
 635         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 636         "console=$consoledev,$baudrate $othbootargs;"   \
 637         "tftp $loadaddr $bootfile;"             \
 638         "tftp $fdtaddr $fdtfile;"               \
 639         "bootm $loadaddr - $fdtaddr"
 640
 641 #define CONFIG_RAMBOOTCOMMAND                           \
 642         "setenv bootargs root=/dev/ram rw "             \
 643         "console=$consoledev,$baudrate $othbootargs;"   \
 644         "tftp $ramdiskaddr $ramdiskfile;"               \
 645         "tftp $loadaddr $bootfile;"                     \
 646         "tftp $fdtaddr $fdtfile;"                       \
 647         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 648
 649 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 650
 651 #include <asm/fsl_secure_boot.h>
 652
 653 #endif  /* __CONFIG_H */