git.sur5r.net Git - u-boot/blob - include/configs/T102xQDS.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_MP                       /* support multiple processors */
  17 #define CONFIG_ENABLE_36BIT_PHYS
  18
  19 #ifdef CONFIG_PHYS_64BIT
  20 #define CONFIG_ADDR_MAP         1
  21 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  22 #endif
  23
  24 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  25 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  26
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 #define CONFIG_DEEP_SLEEP
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  33 #define CONFIG_SPL_FLUSH_IMAGE
  34 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  35 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  36 #define CONFIG_SPL_PAD_TO               0x40000
  37 #define CONFIG_SPL_MAX_SIZE             0x28000
  38 #define RESET_VECTOR_OFFSET             0x27FFC
  39 #define BOOT_PAGE_OFFSET                0x27000
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #endif
  45
  46 #ifdef CONFIG_NAND
  47 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  48 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  49 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  50 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  51 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  53 #define CONFIG_SPL_NAND_BOOT
  54 #endif
  55
  56 #ifdef CONFIG_SPIFLASH
  57 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  58 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  63 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  64 #ifndef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  66 #endif
  67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  68 #define CONFIG_SPL_SPI_BOOT
  69 #endif
  70
  71 #ifdef CONFIG_SDCARD
  72 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  73 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  74 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  75 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  76 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  77 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  78 #ifndef CONFIG_SPL_BUILD
  79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  80 #endif
  81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  82 #define CONFIG_SPL_MMC_BOOT
  83 #endif
  84
  85 #endif /* CONFIG_RAMBOOT_PBL */
  86
  87 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  88 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  89 #endif
  90
  91 #ifdef CONFIG_MTD_NOR_FLASH
  92 #define CONFIG_FLASH_CFI_DRIVER
  93 #define CONFIG_SYS_FLASH_CFI
  94 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  95 #endif
  96
  97 /* PCIe Boot - Master */
  98 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  99 /*
 100  * for slave u-boot IMAGE instored in master memory space,
 101  * PHYS must be aligned based on the SIZE
 102  */
 103 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 105 #ifdef CONFIG_PHYS_64BIT
 106 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 108 #else
 109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 111 #endif
 112 /*
 113  * for slave UCODE and ENV instored in master memory space,
 114  * PHYS must be aligned based on the SIZE
 115  */
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 119 #else
 120 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 122 #endif
 123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 124 /* slave core release by master*/
 125 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 126 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 127
 128 /* PCIe Boot - Slave */
 129 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 130 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 131 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 132                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 133 /* Set 1M boot space for PCIe boot */
 134 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 135 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 136                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 137 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 138 #endif
 139
 140 #if defined(CONFIG_SPIFLASH)
 141 #define CONFIG_SYS_EXTRA_ENV_RELOC
 142 #define CONFIG_ENV_SPI_BUS              0
 143 #define CONFIG_ENV_SPI_CS               0
 144 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 145 #define CONFIG_ENV_SPI_MODE             0
 146 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 147 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 148 #define CONFIG_ENV_SECT_SIZE            0x10000
 149 #elif defined(CONFIG_SDCARD)
 150 #define CONFIG_SYS_EXTRA_ENV_RELOC
 151 #define CONFIG_SYS_MMC_ENV_DEV          0
 152 #define CONFIG_ENV_SIZE                 0x2000
 153 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 154 #elif defined(CONFIG_NAND)
 155 #define CONFIG_SYS_EXTRA_ENV_RELOC
 156 #define CONFIG_ENV_SIZE                 0x2000
 157 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 158 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 159 #define CONFIG_ENV_ADDR         0xffe20000
 160 #define CONFIG_ENV_SIZE         0x2000
 161 #elif defined(CONFIG_ENV_IS_NOWHERE)
 162 #define CONFIG_ENV_SIZE         0x2000
 163 #else
 164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 167 #endif
 168
 169 #ifndef __ASSEMBLY__
 170 unsigned long get_board_sys_clk(void);
 171 unsigned long get_board_ddr_clk(void);
 172 #endif
 173
 174 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 175 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 176
 177 /*
 178  * These can be toggled for performance analysis, otherwise use default.
 179  */
 180 #define CONFIG_SYS_CACHE_STASHING
 181 #define CONFIG_BACKSIDE_L2_CACHE
 182 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 183 #define CONFIG_BTB                      /* toggle branch predition */
 184 #define CONFIG_DDR_ECC
 185 #ifdef CONFIG_DDR_ECC
 186 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 187 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 188 #endif
 189
 190 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 191 #define CONFIG_SYS_MEMTEST_END          0x00400000
 192 #define CONFIG_SYS_ALT_MEMTEST
 193
 194 /*
 195  *  Config the L3 Cache as L3 SRAM
 196  */
 197 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 198 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 199 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 200 #ifdef CONFIG_RAMBOOT_PBL
 201 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 202 #endif
 203 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 204 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 205 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 206 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 207
 208 #ifdef CONFIG_PHYS_64BIT
 209 #define CONFIG_SYS_DCSRBAR              0xf0000000
 210 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 211 #endif
 212
 213 /* EEPROM */
 214 #define CONFIG_ID_EEPROM
 215 #define CONFIG_SYS_I2C_EEPROM_NXID
 216 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 217 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 221
 222 /*
 223  * DDR Setup
 224  */
 225 #define CONFIG_VERY_BIG_RAM
 226 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 227 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 228 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 229 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 230 #define CONFIG_DDR_SPD
 231
 232 #define CONFIG_SYS_SPD_BUS_NUM  0
 233 #define SPD_EEPROM_ADDRESS      0x51
 234
 235 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 236
 237 /*
 238  * IFC Definitions
 239  */
 240 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 243 #else
 244 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 245 #endif
 246
 247 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 248 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 249                                 + 0x8000000) | \
 250                                 CSPR_PORT_SIZE_16 | \
 251                                 CSPR_MSEL_NOR | \
 252                                 CSPR_V)
 253 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 254 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 255                                 CSPR_PORT_SIZE_16 | \
 256                                 CSPR_MSEL_NOR | \
 257                                 CSPR_V)
 258 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 259 /* NOR Flash Timing Params */
 260 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 261 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 262                                 FTIM0_NOR_TEADC(0x5) | \
 263                                 FTIM0_NOR_TEAHC(0x5))
 264 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 265                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 266                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 267 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 268                                 FTIM2_NOR_TCH(0x4) | \
 269                                 FTIM2_NOR_TWPH(0x0E) | \
 270                                 FTIM2_NOR_TWP(0x1c))
 271 #define CONFIG_SYS_NOR_FTIM3    0x0
 272
 273 #define CONFIG_SYS_FLASH_QUIET_TEST
 274 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 275
 276 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 277 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 278 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 279 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 280
 281 #define CONFIG_SYS_FLASH_EMPTY_INFO
 282 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 283                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 284 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 285 #define QIXIS_BASE              0xffdf0000
 286 #ifdef CONFIG_PHYS_64BIT
 287 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 288 #else
 289 #define QIXIS_BASE_PHYS         QIXIS_BASE
 290 #endif
 291 #define QIXIS_LBMAP_SWITCH              0x06
 292 #define QIXIS_LBMAP_MASK                0x0f
 293 #define QIXIS_LBMAP_SHIFT               0
 294 #define QIXIS_LBMAP_DFLTBANK            0x00
 295 #define QIXIS_LBMAP_ALTBANK             0x04
 296 #define QIXIS_RST_CTL_RESET             0x31
 297 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 298 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 299 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 300 #define QIXIS_RST_FORCE_MEM             0x01
 301
 302 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 303 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 304                                 | CSPR_PORT_SIZE_8 \
 305                                 | CSPR_MSEL_GPCM \
 306                                 | CSPR_V)
 307 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 308 #define CONFIG_SYS_CSOR3        0x0
 309 /* QIXIS Timing parameters for IFC CS3 */
 310 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 311                                         FTIM0_GPCM_TEADC(0x0e) | \
 312                                         FTIM0_GPCM_TEAHC(0x0e))
 313 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 314                                         FTIM1_GPCM_TRAD(0x3f))
 315 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 316                                         FTIM2_GPCM_TCH(0x8) | \
 317                                         FTIM2_GPCM_TWP(0x1f))
 318 #define CONFIG_SYS_CS3_FTIM3            0x0
 319
 320 #define CONFIG_NAND_FSL_IFC
 321 #define CONFIG_SYS_NAND_BASE            0xff800000
 322 #ifdef CONFIG_PHYS_64BIT
 323 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 324 #else
 325 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 326 #endif
 327 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 328 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 329                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 330                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 331                                 | CSPR_V)
 332 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 333
 334 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 335                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 336                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 337                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 338                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 339                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 340                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 341
 342 #define CONFIG_SYS_NAND_ONFI_DETECTION
 343
 344 /* ONFI NAND Flash mode0 Timing Params */
 345 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 346                                         FTIM0_NAND_TWP(0x18)   | \
 347                                         FTIM0_NAND_TWCHT(0x07) | \
 348                                         FTIM0_NAND_TWH(0x0a))
 349 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 350                                         FTIM1_NAND_TWBE(0x39)  | \
 351                                         FTIM1_NAND_TRR(0x0e)   | \
 352                                         FTIM1_NAND_TRP(0x18))
 353 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 354                                         FTIM2_NAND_TREH(0x0a) | \
 355                                         FTIM2_NAND_TWHRE(0x1e))
 356 #define CONFIG_SYS_NAND_FTIM3           0x0
 357
 358 #define CONFIG_SYS_NAND_DDR_LAW         11
 359 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 360 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 361
 362 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 363
 364 #if defined(CONFIG_NAND)
 365 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 366 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 367 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 368 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 369 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 370 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 371 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 372 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 373 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 374 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 375 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 376 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 377 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 378 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 379 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 380 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 381 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 382 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 383 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 384 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 385 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 386 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 387 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 388 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 389 #else
 390 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 391 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 392 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 393 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 394 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 395 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 396 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 397 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 398 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 399 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 400 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 401 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 402 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 403 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 404 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 405 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 406 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 407 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 408 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 409 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 410 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 411 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 412 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 413 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 414 #endif
 415
 416 #ifdef CONFIG_SPL_BUILD
 417 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 418 #else
 419 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 420 #endif
 421
 422 #if defined(CONFIG_RAMBOOT_PBL)
 423 #define CONFIG_SYS_RAMBOOT
 424 #endif
 425
 426 #define CONFIG_BOARD_EARLY_INIT_R
 427 #define CONFIG_MISC_INIT_R
 428
 429 #define CONFIG_HWCONFIG
 430
 431 /* define to use L1 as initial stack */
 432 #define CONFIG_L1_INIT_RAM
 433 #define CONFIG_SYS_INIT_RAM_LOCK
 434 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 435 #ifdef CONFIG_PHYS_64BIT
 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 438 /* The assembler doesn't like typecast */
 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 440         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 441           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 442 #else
 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 445 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 446 #endif
 447 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 448
 449 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 450                                         GENERATED_GBL_DATA_SIZE)
 451 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 452
 453 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 454 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 455
 456 /* Serial Port */
 457 #define CONFIG_CONS_INDEX       1
 458 #define CONFIG_SYS_NS16550_SERIAL
 459 #define CONFIG_SYS_NS16550_REG_SIZE     1
 460 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 461
 462 #define CONFIG_SYS_BAUDRATE_TABLE       \
 463         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 464
 465 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 466 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 467 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 468 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 469
 470 /* Video */
 471 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 472 #define CONFIG_FSL_DIU_FB
 473 #ifdef CONFIG_FSL_DIU_FB
 474 #define CONFIG_FSL_DIU_CH7301
 475 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 476 #define CONFIG_VIDEO_LOGO
 477 #define CONFIG_VIDEO_BMP_LOGO
 478 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 479 /*
 480  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 481  * disable empty flash sector detection, which is I/O-intensive.
 482  */
 483 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 484 #endif
 485 #endif
 486
 487 /* I2C */
 488 #define CONFIG_SYS_I2C
 489 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 490 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 491 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 492 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 493 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 494 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 495 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 496
 497 #define I2C_MUX_PCA_ADDR                0x77
 498 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 499 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 500 #define I2C_RETIMER_ADDR                0x18
 501
 502 /* I2C bus multiplexer */
 503 #define I2C_MUX_CH_DEFAULT      0x8
 504 #define I2C_MUX_CH_DIU          0xC
 505 #define I2C_MUX_CH5             0xD
 506 #define I2C_MUX_CH7             0xF
 507
 508 /* LDI/DVI Encoder for display */
 509 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 510 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 511
 512 /*
 513  * RTC configuration
 514  */
 515 #define RTC
 516 #define CONFIG_RTC_DS3231       1
 517 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 518
 519 /*
 520  * eSPI - Enhanced SPI
 521  */
 522 #ifndef CONFIG_SPL_BUILD
 523 #endif
 524 #define CONFIG_SPI_FLASH_BAR
 525 #define CONFIG_SF_DEFAULT_SPEED  10000000
 526 #define CONFIG_SF_DEFAULT_MODE    0
 527
 528 /*
 529  * General PCIe
 530  * Memory space is mapped 1-1, but I/O space must start from 0.
 531  */
 532 #define CONFIG_PCIE1            /* PCIE controller 1 */
 533 #define CONFIG_PCIE2            /* PCIE controller 2 */
 534 #define CONFIG_PCIE3            /* PCIE controller 3 */
 535 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 536 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 537 #define CONFIG_PCI_INDIRECT_BRIDGE
 538
 539 #ifdef CONFIG_PCI
 540 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 541 #ifdef CONFIG_PCIE1
 542 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 543 #ifdef CONFIG_PHYS_64BIT
 544 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 545 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 546 #else
 547 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 548 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 549 #endif
 550 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 551 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 552 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 553 #ifdef CONFIG_PHYS_64BIT
 554 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 555 #else
 556 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 557 #endif
 558 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 559 #endif
 560
 561 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 562 #ifdef CONFIG_PCIE2
 563 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 564 #ifdef CONFIG_PHYS_64BIT
 565 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 566 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 567 #else
 568 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 569 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 570 #endif
 571 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 572 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 573 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 574 #ifdef CONFIG_PHYS_64BIT
 575 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 576 #else
 577 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 578 #endif
 579 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 580 #endif
 581
 582 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 583 #ifdef CONFIG_PCIE3
 584 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 585 #ifdef CONFIG_PHYS_64BIT
 586 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 587 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 588 #else
 589 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 590 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 591 #endif
 592 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 593 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 594 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 595 #ifdef CONFIG_PHYS_64BIT
 596 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 597 #else
 598 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 599 #endif
 600 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 601 #endif
 602
 603 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 604 #endif  /* CONFIG_PCI */
 605
 606 /*
 607  *SATA
 608  */
 609 #define CONFIG_FSL_SATA_V2
 610 #ifdef CONFIG_FSL_SATA_V2
 611 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 612 #define CONFIG_SATA1
 613 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 614 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 615 #define CONFIG_LBA48
 616 #endif
 617
 618 /*
 619  * USB
 620  */
 621 #define CONFIG_HAS_FSL_DR_USB
 622
 623 #ifdef CONFIG_HAS_FSL_DR_USB
 624 #define CONFIG_USB_EHCI_FSL
 625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 626 #endif
 627
 628 /*
 629  * SDHC
 630  */
 631 #ifdef CONFIG_MMC
 632 #define CONFIG_FSL_ESDHC
 633 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 634 #endif
 635
 636 /* Qman/Bman */
 637 #ifndef CONFIG_NOBQFMAN
 638 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 639 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 640 #ifdef CONFIG_PHYS_64BIT
 641 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 642 #else
 643 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 644 #endif
 645 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 646 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 647 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 648 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 649 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 650 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 651                                         CONFIG_SYS_BMAN_CENA_SIZE)
 652 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 653 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 654 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 655 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 656 #ifdef CONFIG_PHYS_64BIT
 657 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 658 #else
 659 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 660 #endif
 661 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 662 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 663 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 664 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 665 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 666 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 667                                         CONFIG_SYS_QMAN_CENA_SIZE)
 668 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 669 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 670
 671 #define CONFIG_SYS_DPAA_FMAN
 672
 673 #define CONFIG_QE
 674 #define CONFIG_U_QE
 675 /* Default address of microcode for the Linux FMan driver */
 676 #if defined(CONFIG_SPIFLASH)
 677 /*
 678  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 679  * env, so we got 0x110000.
 680  */
 681 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 682 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 683 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 684 #elif defined(CONFIG_SDCARD)
 685 /*
 686  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 687  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 688  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 689  */
 690 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 691 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 692 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 693 #elif defined(CONFIG_NAND)
 694 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 695 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 696 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 697 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 698 /*
 699  * Slave has no ucode locally, it can fetch this from remote. When implementing
 700  * in two corenet boards, slave's ucode could be stored in master's memory
 701  * space, the address can be mapped from slave TLB->slave LAW->
 702  * slave SRIO or PCIE outbound window->master inbound window->
 703  * master LAW->the ucode address in master's memory space.
 704  */
 705 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 706 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 707 #else
 708 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 709 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 710 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 711 #endif
 712 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 713 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 714 #endif /* CONFIG_NOBQFMAN */
 715
 716 #ifdef CONFIG_SYS_DPAA_FMAN
 717 #define CONFIG_FMAN_ENET
 718 #define CONFIG_PHYLIB_10G
 719 #define CONFIG_PHY_VITESSE
 720 #define CONFIG_PHY_REALTEK
 721 #define CONFIG_PHY_TERANETICS
 722 #define RGMII_PHY1_ADDR         0x1
 723 #define RGMII_PHY2_ADDR         0x2
 724 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 725 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 726 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 727 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 728 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 729 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 730 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 731 #endif
 732
 733 #ifdef CONFIG_FMAN_ENET
 734 #define CONFIG_MII              /* MII PHY management */
 735 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 736 #endif
 737
 738 /*
 739  * Dynamic MTD Partition support with mtdparts
 740  */
 741 #ifdef CONFIG_MTD_NOR_FLASH
 742 #define CONFIG_MTD_DEVICE
 743 #define CONFIG_MTD_PARTITIONS
 744 #define CONFIG_FLASH_CFI_MTD
 745 #endif
 746
 747 /*
 748  * Environment
 749  */
 750 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 751 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 752
 753 /*
 754  * Miscellaneous configurable options
 755  */
 756 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 757
 758 /*
 759  * For booting Linux, the board info and command line data
 760  * have to be in the first 64 MB of memory, since this is
 761  * the maximum mapped by the Linux kernel during initialization.
 762  */
 763 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 764 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 765
 766 #ifdef CONFIG_CMD_KGDB
 767 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 768 #endif
 769
 770 /*
 771  * Environment Configuration
 772  */
 773 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 774 #define CONFIG_BOOTFILE         "uImage"
 775 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 776 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 777 #define __USB_PHY_TYPE          utmi
 778
 779 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 780         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 781         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 782         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 783         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 784         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 785         "netdev=eth0\0"                                         \
 786         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 787         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 788         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 789         "tftpflash=tftpboot $loadaddr $uboot && "               \
 790         "protect off $ubootaddr +$filesize && "                 \
 791         "erase $ubootaddr +$filesize && "                       \
 792         "cp.b $loadaddr $ubootaddr $filesize && "               \
 793         "protect on $ubootaddr +$filesize && "                  \
 794         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 795         "consoledev=ttyS0\0"                                    \
 796         "ramdiskaddr=2000000\0"                                 \
 797         "fdtaddr=d00000\0"                                      \
 798         "bdev=sda3\0"
 799
 800 #define CONFIG_LINUX                                    \
 801         "setenv bootargs root=/dev/ram rw "             \
 802         "console=$consoledev,$baudrate $othbootargs;"   \
 803         "setenv ramdiskaddr 0x02000000;"                \
 804         "setenv fdtaddr 0x00c00000;"                    \
 805         "setenv loadaddr 0x1000000;"                    \
 806         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 807
 808 #define CONFIG_NFSBOOTCOMMAND                   \
 809         "setenv bootargs root=/dev/nfs rw "     \
 810         "nfsroot=$serverip:$rootpath "          \
 811         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 812         "console=$consoledev,$baudrate $othbootargs;"   \
 813         "tftp $loadaddr $bootfile;"             \
 814         "tftp $fdtaddr $fdtfile;"               \
 815         "bootm $loadaddr - $fdtaddr"
 816
 817 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 818
 819 #include <asm/fsl_secure_boot.h>
 820
 821 #endif  /* __T1024QDS_H */