git.sur5r.net Git - u-boot/blob - include/configs/T102xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 RDB board configuration file
   8  */
   9
  10 #ifndef __T1024RDB_H
  11 #define __T1024RDB_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 /* support deep sleep */
  28 #ifdef CONFIG_ARCH_T1024
  29 #define CONFIG_DEEP_SLEEP
  30 #endif
  31
  32 #ifdef CONFIG_RAMBOOT_PBL
  33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  34 #define CONFIG_SPL_FLUSH_IMAGE
  35 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  36 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  37 #define CONFIG_SPL_PAD_TO               0x40000
  38 #define CONFIG_SPL_MAX_SIZE             0x28000
  39 #define RESET_VECTOR_OFFSET             0x27FFC
  40 #define BOOT_PAGE_OFFSET                0x27000
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_SKIP_RELOCATE
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  45 #endif
  46
  47 #ifdef CONFIG_NAND
  48 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  49 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
  50 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
  51 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  52 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  53 #if defined(CONFIG_TARGET_T1024RDB)
  54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
  55 #elif defined(CONFIG_TARGET_T1023RDB)
  56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
  57 #endif
  58 #define CONFIG_SPL_NAND_BOOT
  59 #endif
  60
  61 #ifdef CONFIG_SPIFLASH
  62 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
  63 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
  66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
  67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  68 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  69 #ifndef CONFIG_SPL_BUILD
  70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  71 #endif
  72 #if defined(CONFIG_TARGET_T1024RDB)
  73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
  74 #elif defined(CONFIG_TARGET_T1023RDB)
  75 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
  76 #endif
  77 #define CONFIG_SPL_SPI_BOOT
  78 #endif
  79
  80 #ifdef CONFIG_SDCARD
  81 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
  82 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  83 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
  84 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
  85 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  86 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  87 #ifndef CONFIG_SPL_BUILD
  88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  89 #endif
  90 #if defined(CONFIG_TARGET_T1024RDB)
  91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
  92 #elif defined(CONFIG_TARGET_T1023RDB)
  93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
  94 #endif
  95 #define CONFIG_SPL_MMC_BOOT
  96 #endif
  97
  98 #endif /* CONFIG_RAMBOOT_PBL */
  99
 100 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 101 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 102 #endif
 103
 104 #ifdef CONFIG_MTD_NOR_FLASH
 105 #define CONFIG_FLASH_CFI_DRIVER
 106 #define CONFIG_SYS_FLASH_CFI
 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 108 #endif
 109
 110 /* PCIe Boot - Master */
 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 112 /*
 113  * for slave u-boot IMAGE instored in master memory space,
 114  * PHYS must be aligned based on the SIZE
 115  */
 116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 117 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 121 #else
 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 124 #endif
 125 /*
 126  * for slave UCODE and ENV instored in master memory space,
 127  * PHYS must be aligned based on the SIZE
 128  */
 129 #ifdef CONFIG_PHYS_64BIT
 130 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 131 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 132 #else
 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 135 #endif
 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 137 /* slave core release by master*/
 138 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
 139 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
 140
 141 /* PCIe Boot - Slave */
 142 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 143 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 144 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 145                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 146 /* Set 1M boot space for PCIe boot */
 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 148 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 149                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 151 #endif
 152
 153 #if defined(CONFIG_SPIFLASH)
 154 #define CONFIG_SYS_EXTRA_ENV_RELOC
 155 #define CONFIG_ENV_SPI_BUS              0
 156 #define CONFIG_ENV_SPI_CS               0
 157 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 158 #define CONFIG_ENV_SPI_MODE             0
 159 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 160 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 161 #if defined(CONFIG_TARGET_T1024RDB)
 162 #define CONFIG_ENV_SECT_SIZE            0x10000
 163 #elif defined(CONFIG_TARGET_T1023RDB)
 164 #define CONFIG_ENV_SECT_SIZE            0x40000
 165 #endif
 166 #elif defined(CONFIG_SDCARD)
 167 #define CONFIG_SYS_EXTRA_ENV_RELOC
 168 #define CONFIG_SYS_MMC_ENV_DEV          0
 169 #define CONFIG_ENV_SIZE                 0x2000
 170 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 171 #elif defined(CONFIG_NAND)
 172 #define CONFIG_SYS_EXTRA_ENV_RELOC
 173 #define CONFIG_ENV_SIZE                 0x2000
 174 #if defined(CONFIG_TARGET_T1024RDB)
 175 #define CONFIG_ENV_OFFSET               (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 176 #elif defined(CONFIG_TARGET_T1023RDB)
 177 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 178 #endif
 179 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 180 #define CONFIG_ENV_ADDR         0xffe20000
 181 #define CONFIG_ENV_SIZE         0x2000
 182 #elif defined(CONFIG_ENV_IS_NOWHERE)
 183 #define CONFIG_ENV_SIZE         0x2000
 184 #else
 185 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 186 #define CONFIG_ENV_SIZE         0x2000
 187 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 188 #endif
 189
 190 #ifndef __ASSEMBLY__
 191 unsigned long get_board_sys_clk(void);
 192 unsigned long get_board_ddr_clk(void);
 193 #endif
 194
 195 #define CONFIG_SYS_CLK_FREQ     100000000
 196 #define CONFIG_DDR_CLK_FREQ     100000000
 197
 198 /*
 199  * These can be toggled for performance analysis, otherwise use default.
 200  */
 201 #define CONFIG_SYS_CACHE_STASHING
 202 #define CONFIG_BACKSIDE_L2_CACHE
 203 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 204 #define CONFIG_BTB                      /* toggle branch predition */
 205 #define CONFIG_DDR_ECC
 206 #ifdef CONFIG_DDR_ECC
 207 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 208 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 209 #endif
 210
 211 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 212 #define CONFIG_SYS_MEMTEST_END          0x00400000
 213
 214 /*
 215  *  Config the L3 Cache as L3 SRAM
 216  */
 217 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 218 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 219 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 220 #ifdef CONFIG_RAMBOOT_PBL
 221 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 222 #endif
 223 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 224 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 225 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 226 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 227
 228 #ifdef CONFIG_PHYS_64BIT
 229 #define CONFIG_SYS_DCSRBAR              0xf0000000
 230 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 231 #endif
 232
 233 /* EEPROM */
 234 #define CONFIG_ID_EEPROM
 235 #define CONFIG_SYS_I2C_EEPROM_NXID
 236 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 237 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 241
 242 /*
 243  * DDR Setup
 244  */
 245 #define CONFIG_VERY_BIG_RAM
 246 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 247 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 248 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 249 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 250 #define CONFIG_FSL_DDR_INTERACTIVE
 251 #if defined(CONFIG_TARGET_T1024RDB)
 252 #define CONFIG_DDR_SPD
 253 #define CONFIG_SYS_SPD_BUS_NUM  0
 254 #define SPD_EEPROM_ADDRESS      0x51
 255 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 256 #elif defined(CONFIG_TARGET_T1023RDB)
 257 #define CONFIG_SYS_DDR_RAW_TIMING
 258 #define CONFIG_SYS_SDRAM_SIZE   2048
 259 #endif
 260
 261 /*
 262  * IFC Definitions
 263  */
 264 #define CONFIG_SYS_FLASH_BASE   0xe8000000
 265 #ifdef CONFIG_PHYS_64BIT
 266 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 267 #else
 268 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 269 #endif
 270
 271 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 272 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 273                                 CSPR_PORT_SIZE_16 | \
 274                                 CSPR_MSEL_NOR | \
 275                                 CSPR_V)
 276 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 277
 278 /* NOR Flash Timing Params */
 279 #if defined(CONFIG_TARGET_T1024RDB)
 280 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 281 #elif defined(CONFIG_TARGET_T1023RDB)
 282 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
 283                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
 284 #endif
 285 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 286                                 FTIM0_NOR_TEADC(0x5) | \
 287                                 FTIM0_NOR_TEAHC(0x5))
 288 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 289                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 290                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 291 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 292                                 FTIM2_NOR_TCH(0x4) | \
 293                                 FTIM2_NOR_TWPH(0x0E) | \
 294                                 FTIM2_NOR_TWP(0x1c))
 295 #define CONFIG_SYS_NOR_FTIM3    0x0
 296
 297 #define CONFIG_SYS_FLASH_QUIET_TEST
 298 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 299
 300 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 301 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 302 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 303 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 304
 305 #define CONFIG_SYS_FLASH_EMPTY_INFO
 306 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 307
 308 #ifdef CONFIG_TARGET_T1024RDB
 309 /* CPLD on IFC */
 310 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 311 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 312 #define CONFIG_SYS_CSPR2_EXT            (0xf)
 313 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 314                                                 | CSPR_PORT_SIZE_8 \
 315                                                 | CSPR_MSEL_GPCM \
 316                                                 | CSPR_V)
 317 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 318 #define CONFIG_SYS_CSOR2                0x0
 319
 320 /* CPLD Timing parameters for IFC CS2 */
 321 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 322                                                 FTIM0_GPCM_TEADC(0x0e) | \
 323                                                 FTIM0_GPCM_TEAHC(0x0e))
 324 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 325                                                 FTIM1_GPCM_TRAD(0x1f))
 326 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 327                                                 FTIM2_GPCM_TCH(0x8) | \
 328                                                 FTIM2_GPCM_TWP(0x1f))
 329 #define CONFIG_SYS_CS2_FTIM3            0x0
 330 #endif
 331
 332 /* NAND Flash on IFC */
 333 #define CONFIG_NAND_FSL_IFC
 334 #define CONFIG_SYS_NAND_BASE            0xff800000
 335 #ifdef CONFIG_PHYS_64BIT
 336 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 337 #else
 338 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 339 #endif
 340 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 341 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 342                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 343                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 344                                 | CSPR_V)
 345 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 346
 347 #if defined(CONFIG_TARGET_T1024RDB)
 348 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 349                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 350                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 351                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 352                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 353                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 354                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 355 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 356 #elif defined(CONFIG_TARGET_T1023RDB)
 357 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 358                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 359                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 360                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
 361                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 362                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
 363                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 364 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 365 #endif
 366
 367 #define CONFIG_SYS_NAND_ONFI_DETECTION
 368 /* ONFI NAND Flash mode0 Timing Params */
 369 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 370                                         FTIM0_NAND_TWP(0x18)   | \
 371                                         FTIM0_NAND_TWCHT(0x07) | \
 372                                         FTIM0_NAND_TWH(0x0a))
 373 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 374                                         FTIM1_NAND_TWBE(0x39)  | \
 375                                         FTIM1_NAND_TRR(0x0e)   | \
 376                                         FTIM1_NAND_TRP(0x18))
 377 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 378                                         FTIM2_NAND_TREH(0x0a) | \
 379                                         FTIM2_NAND_TWHRE(0x1e))
 380 #define CONFIG_SYS_NAND_FTIM3           0x0
 381
 382 #define CONFIG_SYS_NAND_DDR_LAW         11
 383 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 384 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 385
 386 #if defined(CONFIG_NAND)
 387 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 388 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 389 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 390 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 391 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 392 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 393 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 394 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 395 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 396 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 397 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 398 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 399 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 400 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 401 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 402 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 403 #else
 404 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 405 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 406 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 407 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 408 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 409 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 410 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 411 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 412 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 413 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 414 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 415 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 416 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 417 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 418 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 419 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 420 #endif
 421
 422 #ifdef CONFIG_SPL_BUILD
 423 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 424 #else
 425 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 426 #endif
 427
 428 #if defined(CONFIG_RAMBOOT_PBL)
 429 #define CONFIG_SYS_RAMBOOT
 430 #endif
 431
 432 #define CONFIG_MISC_INIT_R
 433
 434 #define CONFIG_HWCONFIG
 435
 436 /* define to use L1 as initial stack */
 437 #define CONFIG_L1_INIT_RAM
 438 #define CONFIG_SYS_INIT_RAM_LOCK
 439 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 440 #ifdef CONFIG_PHYS_64BIT
 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 443 /* The assembler doesn't like typecast */
 444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 445         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 446           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 447 #else
 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 451 #endif
 452 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 453
 454 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 455                                         GENERATED_GBL_DATA_SIZE)
 456 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 457
 458 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 459 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 460
 461 /* Serial Port */
 462 #define CONFIG_SYS_NS16550_SERIAL
 463 #define CONFIG_SYS_NS16550_REG_SIZE     1
 464 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 465
 466 #define CONFIG_SYS_BAUDRATE_TABLE       \
 467         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 468
 469 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 470 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 471 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 472 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 473
 474 /* Video */
 475 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
 476 #ifdef CONFIG_FSL_DIU_FB
 477 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 478 #define CONFIG_VIDEO_LOGO
 479 #define CONFIG_VIDEO_BMP_LOGO
 480 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 481 /*
 482  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 483  * disable empty flash sector detection, which is I/O-intensive.
 484  */
 485 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 486 #endif
 487
 488 /* I2C */
 489 #define CONFIG_SYS_I2C
 490 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 491 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 492 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 493 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 494 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 495 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 496 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 497
 498 #define I2C_PCA6408_BUS_NUM             1
 499 #define I2C_PCA6408_ADDR                0x20
 500
 501 /* I2C bus multiplexer */
 502 #define I2C_MUX_CH_DEFAULT      0x8
 503
 504 /*
 505  * RTC configuration
 506  */
 507 #define RTC
 508 #define CONFIG_RTC_DS1337       1
 509 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 510
 511 /*
 512  * eSPI - Enhanced SPI
 513  */
 514 #define CONFIG_SPI_FLASH_BAR
 515 #define CONFIG_SF_DEFAULT_SPEED 10000000
 516 #define CONFIG_SF_DEFAULT_MODE  0
 517
 518 /*
 519  * General PCIe
 520  * Memory space is mapped 1-1, but I/O space must start from 0.
 521  */
 522 #define CONFIG_PCIE1            /* PCIE controller 1 */
 523 #define CONFIG_PCIE2            /* PCIE controller 2 */
 524 #define CONFIG_PCIE3            /* PCIE controller 3 */
 525 #ifdef CONFIG_ARCH_T1040
 526 #define CONFIG_PCIE4            /* PCIE controller 4 */
 527 #endif
 528 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 529 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 530 #define CONFIG_PCI_INDIRECT_BRIDGE
 531
 532 #ifdef CONFIG_PCI
 533 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 534 #ifdef CONFIG_PCIE1
 535 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 536 #ifdef CONFIG_PHYS_64BIT
 537 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 538 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 539 #else
 540 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 541 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 542 #endif
 543 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 544 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 545 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 546 #ifdef CONFIG_PHYS_64BIT
 547 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 548 #else
 549 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 550 #endif
 551 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 552 #endif
 553
 554 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 555 #ifdef CONFIG_PCIE2
 556 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 557 #ifdef CONFIG_PHYS_64BIT
 558 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 559 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 560 #else
 561 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 562 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 563 #endif
 564 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 565 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 566 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 567 #ifdef CONFIG_PHYS_64BIT
 568 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 569 #else
 570 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 571 #endif
 572 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 573 #endif
 574
 575 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 576 #ifdef CONFIG_PCIE3
 577 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 578 #ifdef CONFIG_PHYS_64BIT
 579 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 580 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 581 #else
 582 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 583 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 584 #endif
 585 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 586 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 587 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 588 #ifdef CONFIG_PHYS_64BIT
 589 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 590 #else
 591 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 592 #endif
 593 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 594 #endif
 595
 596 /* controller 4, Base address 203000, to be removed */
 597 #ifdef CONFIG_PCIE4
 598 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xb0000000
 599 #ifdef CONFIG_PHYS_64BIT
 600 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 601 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc30000000ull
 602 #else
 603 #define CONFIG_SYS_PCIE4_MEM_BUS        0xb0000000
 604 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xb0000000
 605 #endif
 606 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 607 #define CONFIG_SYS_PCIE4_IO_VIRT        0xf8030000
 608 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 609 #ifdef CONFIG_PHYS_64BIT
 610 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 611 #else
 612 #define CONFIG_SYS_PCIE4_IO_PHYS        0xf8030000
 613 #endif
 614 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 615 #endif
 616
 617 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 618 #endif  /* CONFIG_PCI */
 619
 620 /*
 621  * USB
 622  */
 623 #define CONFIG_HAS_FSL_DR_USB
 624
 625 #ifdef CONFIG_HAS_FSL_DR_USB
 626 #define CONFIG_USB_EHCI_FSL
 627 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 628 #endif
 629
 630 /*
 631  * SDHC
 632  */
 633 #ifdef CONFIG_MMC
 634 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 635 #endif
 636
 637 /* Qman/Bman */
 638 #ifndef CONFIG_NOBQFMAN
 639 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 640 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 641 #ifdef CONFIG_PHYS_64BIT
 642 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 643 #else
 644 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 645 #endif
 646 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 647 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 648 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 649 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 650 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 651 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 652                                         CONFIG_SYS_BMAN_CENA_SIZE)
 653 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 654 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 655 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 656 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 657 #ifdef CONFIG_PHYS_64BIT
 658 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 659 #else
 660 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 661 #endif
 662 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 663 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 664 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 665 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 666 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 667 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 668                                         CONFIG_SYS_QMAN_CENA_SIZE)
 669 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 670 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 671
 672 #define CONFIG_SYS_DPAA_FMAN
 673
 674 #ifdef CONFIG_TARGET_T1024RDB
 675 #define CONFIG_QE
 676 #define CONFIG_U_QE
 677 #endif
 678 /* Default address of microcode for the Linux FMan driver */
 679 #if defined(CONFIG_SPIFLASH)
 680 /*
 681  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 682  * env, so we got 0x110000.
 683  */
 684 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 685 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 686 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 687 #elif defined(CONFIG_SDCARD)
 688 /*
 689  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 690  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 691  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 692  */
 693 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 694 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 695 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 696 #elif defined(CONFIG_NAND)
 697 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 698 #if defined(CONFIG_TARGET_T1024RDB)
 699 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 700 #define CONFIG_SYS_QE_FW_ADDR           (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 701 #elif defined(CONFIG_TARGET_T1023RDB)
 702 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 703 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 704 #endif
 705 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 706 /*
 707  * Slave has no ucode locally, it can fetch this from remote. When implementing
 708  * in two corenet boards, slave's ucode could be stored in master's memory
 709  * space, the address can be mapped from slave TLB->slave LAW->
 710  * slave SRIO or PCIE outbound window->master inbound window->
 711  * master LAW->the ucode address in master's memory space.
 712  */
 713 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 714 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 715 #else
 716 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 717 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 718 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 719 #endif
 720 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 721 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 722 #endif /* CONFIG_NOBQFMAN */
 723
 724 #ifdef CONFIG_SYS_DPAA_FMAN
 725 #define CONFIG_FMAN_ENET
 726 #define CONFIG_PHYLIB_10G
 727 #define CONFIG_PHY_REALTEK
 728 #define CONFIG_PHY_AQUANTIA
 729 #if defined(CONFIG_TARGET_T1024RDB)
 730 #define RGMII_PHY1_ADDR         0x2
 731 #define RGMII_PHY2_ADDR         0x6
 732 #define SGMII_AQR_PHY_ADDR      0x2
 733 #define FM1_10GEC1_PHY_ADDR     0x1
 734 #elif defined(CONFIG_TARGET_T1023RDB)
 735 #define RGMII_PHY1_ADDR         0x1
 736 #define SGMII_RTK_PHY_ADDR      0x3
 737 #define SGMII_AQR_PHY_ADDR      0x2
 738 #endif
 739 #endif
 740
 741 #ifdef CONFIG_FMAN_ENET
 742 #define CONFIG_MII              /* MII PHY management */
 743 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 744 #endif
 745
 746 /*
 747  * Dynamic MTD Partition support with mtdparts
 748  */
 749 #ifdef CONFIG_MTD_NOR_FLASH
 750 #define CONFIG_MTD_DEVICE
 751 #define CONFIG_MTD_PARTITIONS
 752 #define CONFIG_FLASH_CFI_MTD
 753 #endif
 754
 755 /*
 756  * Environment
 757  */
 758 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 759 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 760
 761 /*
 762  * Miscellaneous configurable options
 763  */
 764 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 765
 766 /*
 767  * For booting Linux, the board info and command line data
 768  * have to be in the first 64 MB of memory, since this is
 769  * the maximum mapped by the Linux kernel during initialization.
 770  */
 771 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 772 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 773
 774 #ifdef CONFIG_CMD_KGDB
 775 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 776 #endif
 777
 778 /*
 779  * Environment Configuration
 780  */
 781 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 782 #define CONFIG_BOOTFILE         "uImage"
 783 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 784 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 785 #define __USB_PHY_TYPE          utmi
 786
 787 #ifdef CONFIG_ARCH_T1024
 788 #define CONFIG_BOARDNAME t1024rdb
 789 #define BANK_INTLV cs0_cs1
 790 #else
 791 #define CONFIG_BOARDNAME t1023rdb
 792 #define BANK_INTLV  null
 793 #endif
 794
 795 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 796         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 797         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
 798         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
 799         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
 800         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
 801         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
 802         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 803         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 804         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 805         "netdev=eth0\0"                                         \
 806         "tftpflash=tftpboot $loadaddr $uboot && "               \
 807         "protect off $ubootaddr +$filesize && "                 \
 808         "erase $ubootaddr +$filesize && "                       \
 809         "cp.b $loadaddr $ubootaddr $filesize && "               \
 810         "protect on $ubootaddr +$filesize && "                  \
 811         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 812         "consoledev=ttyS0\0"                                    \
 813         "ramdiskaddr=2000000\0"                                 \
 814         "fdtaddr=1e00000\0"                                     \
 815         "bdev=sda3\0"
 816
 817 #define CONFIG_LINUX                                    \
 818         "setenv bootargs root=/dev/ram rw "             \
 819         "console=$consoledev,$baudrate $othbootargs;"   \
 820         "setenv ramdiskaddr 0x02000000;"                \
 821         "setenv fdtaddr 0x00c00000;"                    \
 822         "setenv loadaddr 0x1000000;"                    \
 823         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 824
 825 #define CONFIG_NFSBOOTCOMMAND                   \
 826         "setenv bootargs root=/dev/nfs rw "     \
 827         "nfsroot=$serverip:$rootpath "          \
 828         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 829         "console=$consoledev,$baudrate $othbootargs;"   \
 830         "tftp $loadaddr $bootfile;"             \
 831         "tftp $fdtaddr $fdtfile;"               \
 832         "bootm $loadaddr - $fdtaddr"
 833
 834 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 835
 836 #include <asm/fsl_secure_boot.h>
 837
 838 #endif  /* __T1024RDB_H */