1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
11 * QorIQ uCP1020-xx boards configuration file
16 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
17 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
18 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
19 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
20 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
21 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
23 #if defined(CONFIG_TARTGET_UCP1020T1)
25 #define CONFIG_UCP1020_REV_1_3
27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
31 #define CONFIG_HAS_ETH0
32 #define CONFIG_HAS_ETH1
33 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
34 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
35 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
36 #define CONFIG_IPADDR 10.80.41.229
37 #define CONFIG_SERVERIP 10.80.41.227
38 #define CONFIG_NETMASK 255.255.252.0
39 #define CONFIG_ETHPRIME "eTSEC3"
41 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
43 #define CONFIG_SYS_L2_SIZE (256 << 10)
47 #if defined(CONFIG_TARGET_UCP1020)
49 #define CONFIG_UCP1020
50 #define CONFIG_UCP1020_REV_1_3
52 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
57 #define CONFIG_HAS_ETH0
58 #define CONFIG_HAS_ETH1
59 #define CONFIG_HAS_ETH2
60 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
61 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
62 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
63 #define CONFIG_IPADDR 192.168.1.81
64 #define CONFIG_IPADDR1 192.168.1.82
65 #define CONFIG_IPADDR2 192.168.1.83
66 #define CONFIG_SERVERIP 192.168.1.80
67 #define CONFIG_GATEWAYIP 102.168.1.1
68 #define CONFIG_NETMASK 255.255.255.0
69 #define CONFIG_ETHPRIME "eTSEC1"
71 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
73 #define CONFIG_SYS_L2_SIZE (256 << 10)
78 #define CONFIG_RAMBOOT_SDCARD
79 #define CONFIG_SYS_RAMBOOT
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
84 #ifdef CONFIG_SPIFLASH
85 #define CONFIG_RAMBOOT_SPIFLASH
86 #define CONFIG_SYS_RAMBOOT
87 #define CONFIG_SYS_EXTRA_ENV_RELOC
88 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
91 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
97 #ifndef CONFIG_SYS_MONITOR_BASE
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
103 #define CONFIG_ENV_OVERWRITE
105 #define CONFIG_SYS_SATA_MAX_DEVICE 2
108 #define CONFIG_SYS_CLK_FREQ 66666666
109 #define CONFIG_DDR_CLK_FREQ 66666666
111 #define CONFIG_HWCONFIG
114 * These can be toggled for performance analysis, otherwise use default.
116 #define CONFIG_L2_CACHE
119 #define CONFIG_ENABLE_36BIT_PHYS
121 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
122 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
124 #define CONFIG_SYS_CCSRBAR 0xffe00000
125 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
127 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
129 #ifdef CONFIG_SPL_BUILD
130 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
134 #define CONFIG_DDR_ECC_ENABLE
135 #ifndef CONFIG_DDR_ECC_ENABLE
136 #define CONFIG_SYS_DDR_RAW_TIMING
137 #define CONFIG_DDR_SPD
139 #define CONFIG_SYS_SPD_BUS_NUM 1
140 #undef CONFIG_FSL_DDR_INTERACTIVE
142 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
143 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
144 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150 /* Default settings for DDR3 */
151 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
152 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
153 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
154 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
155 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
156 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
158 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
159 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
160 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
161 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
163 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
164 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
165 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
166 #define CONFIG_SYS_DDR_RCW_1 0x00000000
167 #define CONFIG_SYS_DDR_RCW_2 0x00000000
168 #ifdef CONFIG_DDR_ECC_ENABLE
169 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
171 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
173 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
174 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
175 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
177 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
178 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
179 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
180 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
181 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
182 #define CONFIG_SYS_DDR_MODE_1 0x40461520
183 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
184 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
186 #undef CONFIG_CLOCKS_IN_MHZ
191 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
192 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
193 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
194 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
196 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
197 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
198 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
202 * Local Bus Definitions
204 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
205 #define CONFIG_SYS_FLASH_BASE 0xec000000
207 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
209 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
212 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
215 #define CONFIG_SYS_FLASH_QUIET_TEST
216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
220 #undef CONFIG_SYS_FLASH_CHECKSUM
221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
224 #define CONFIG_FLASH_CFI_DRIVER
225 #define CONFIG_SYS_FLASH_CFI
226 #define CONFIG_SYS_FLASH_EMPTY_INFO
227 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
229 #define CONFIG_SYS_INIT_RAM_LOCK
230 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
231 /* Initial L1 address */
232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
235 /* Size of used area in RAM */
236 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
239 GENERATED_GBL_DATA_SIZE)
240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
242 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
243 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
245 #define CONFIG_SYS_PMC_BASE 0xff980000
246 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
247 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
249 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
250 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
253 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
254 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
255 #ifdef CONFIG_NAND_FSL_ELBC
256 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
257 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
260 /* Serial Port - controlled on board with jumper J8
264 #undef CONFIG_SERIAL_SOFTWARE_FIFO
265 #define CONFIG_SYS_NS16550_SERIAL
266 #define CONFIG_SYS_NS16550_REG_SIZE 1
267 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
268 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
269 #define CONFIG_NS16550_MIN_FUNCTIONS
272 #define CONFIG_SYS_BAUDRATE_TABLE \
273 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
275 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
276 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
279 #define CONFIG_SYS_I2C
280 #define CONFIG_SYS_I2C_FSL
281 #define CONFIG_SYS_FSL_I2C_SPEED 400000
282 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
283 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
284 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
285 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
286 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
287 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
288 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
290 #define CONFIG_RTC_DS1337
291 #define CONFIG_RTC_DS1337_NOOSC
292 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
293 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
294 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
295 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
298 * eSPI - Enhanced SPI
300 #define CONFIG_HARD_SPI
302 #define CONFIG_SF_DEFAULT_SPEED 10000000
303 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
305 #if defined(CONFIG_PCI)
308 * Memory space is mapped 1-1, but I/O space must start from 0.
311 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
312 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
313 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
314 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
315 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
316 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
317 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
318 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
319 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
320 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
322 /* controller 1, Slot 2, tgtid 1, Base address a000 */
323 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
324 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
325 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
326 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
327 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
328 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
329 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
330 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
331 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
333 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
334 #endif /* CONFIG_PCI */
339 #ifdef CONFIG_ENV_FIT_UCBOOT
341 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
342 #define CONFIG_ENV_SIZE 0x20000
343 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
347 #define CONFIG_ENV_SPI_BUS 0
348 #define CONFIG_ENV_SPI_CS 0
349 #define CONFIG_ENV_SPI_MAX_HZ 10000000
350 #define CONFIG_ENV_SPI_MODE 0
352 #ifdef CONFIG_RAMBOOT_SPIFLASH
354 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
355 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
356 #define CONFIG_ENV_SECT_SIZE 0x1000
358 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
359 /* Address and size of Redundant Environment Sector */
360 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
361 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
364 #elif defined(CONFIG_RAMBOOT_SDCARD)
365 #define CONFIG_FSL_FIXED_MMC_LOCATION
366 #define CONFIG_ENV_SIZE 0x2000
367 #define CONFIG_SYS_MMC_ENV_DEV 0
369 #elif defined(CONFIG_SYS_RAMBOOT)
370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
371 #define CONFIG_ENV_SIZE 0x2000
374 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
375 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
376 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
377 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
378 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
379 /* Address and size of Redundant Environment Sector */
380 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
381 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
386 #endif /* CONFIG_ENV_FIT_UCBOOT */
388 #define CONFIG_LOADS_ECHO /* echo on for serial download */
389 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
394 #define CONFIG_HAS_FSL_DR_USB
396 #if defined(CONFIG_HAS_FSL_DR_USB)
397 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
399 #ifdef CONFIG_USB_EHCI_HCD
400 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
401 #define CONFIG_USB_EHCI_FSL
405 #undef CONFIG_WATCHDOG /* watchdog disabled */
408 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
409 #define CONFIG_MMC_SPI
412 /* Misc Extra Settings */
413 #undef CONFIG_WATCHDOG /* watchdog disabled */
416 * Miscellaneous configurable options
418 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
419 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
422 * For booting Linux, the board info and command line data
423 * have to be in the first 64 MB of memory, since this is
424 * the maximum mapped by the Linux kernel during initialization.
426 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
427 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
429 #if defined(CONFIG_CMD_KGDB)
430 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
431 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
435 * Environment Configuration
438 #if defined(CONFIG_TSEC_ENET)
440 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
442 #error "UCP1020 module revision is not defined !!!"
445 #define CONFIG_BOOTP_SERVERIP
447 #define CONFIG_MII /* MII PHY management */
448 #define CONFIG_TSEC1_NAME "eTSEC1"
449 #define CONFIG_TSEC2_NAME "eTSEC2"
450 #define CONFIG_TSEC3_NAME "eTSEC3"
452 #define TSEC1_PHY_ADDR 4
453 #define TSEC2_PHY_ADDR 0
454 #define TSEC2_PHY_ADDR_SGMII 0x00
455 #define TSEC3_PHY_ADDR 6
457 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
458 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
459 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
461 #define TSEC1_PHYIDX 0
462 #define TSEC2_PHYIDX 0
463 #define TSEC3_PHYIDX 0
467 #define CONFIG_HOSTNAME "UCP1020"
468 #define CONFIG_ROOTPATH "/opt/nfsroot"
469 #define CONFIG_BOOTFILE "uImage"
470 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
472 /* default location for tftp and bootm */
473 #define CONFIG_LOADADDR 1000000
475 #if defined(CONFIG_DONGLE)
477 #define CONFIG_EXTRA_ENV_SETTINGS \
478 "bootcmd=run prog_spi_mbrbootcramfs\0" \
479 "bootfile=uImage\0" \
480 "consoledev=ttyS0\0" \
481 "cramfsfile=image.cramfs\0" \
482 "dtbaddr=0x00c00000\0" \
483 "dtbfile=image.dtb\0" \
484 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
485 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
486 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
487 "fileaddr=0x01000000\0" \
488 "filesize=0x00080000\0" \
489 "flashmbr=sf probe 0; " \
490 "tftp $loadaddr $mbr; " \
491 "sf erase $mbr_offset +$filesize; " \
492 "sf write $loadaddr $mbr_offset $filesize\0" \
493 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
494 "protect off $nor_recoveryaddr +$filesize; " \
495 "erase $nor_recoveryaddr +$filesize; " \
496 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
497 "protect on $nor_recoveryaddr +$filesize\0 " \
498 "flashuboot=tftp $ubootaddr $ubootfile; " \
499 "protect off $nor_ubootaddr +$filesize; " \
500 "erase $nor_ubootaddr +$filesize; " \
501 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
502 "protect on $nor_ubootaddr +$filesize\0 " \
503 "flashworking=tftp $workingaddr $cramfsfile; " \
504 "protect off $nor_workingaddr +$filesize; " \
505 "erase $nor_workingaddr +$filesize; " \
506 "cp.b $workingaddr $nor_workingaddr $filesize; " \
507 "protect on $nor_workingaddr +$filesize\0 " \
508 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
509 "kerneladdr=0x01100000\0" \
510 "kernelfile=uImage\0" \
511 "loadaddr=0x01000000\0" \
512 "mbr=uCP1020d.mbr\0" \
513 "mbr_offset=0x00000000\0" \
514 "mmbr=uCP1020Quiet.mbr\0" \
516 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
518 "mmc write $loadaddr 1 1\0" \
519 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
520 "mmc erase 0x40 0x400; " \
521 "mmc write $loadaddr 0x40 0x400\0" \
523 "nor_recoveryaddr=0xEC0A0000\0" \
524 "nor_ubootaddr=0xEFF80000\0" \
525 "nor_workingaddr=0xECFA0000\0" \
526 "norbootrecovery=setenv bootargs $recoverybootargs" \
527 " console=$consoledev,$baudrate $othbootargs; " \
528 "run norloadrecovery; " \
529 "bootm $kerneladdr - $dtbaddr\0" \
530 "norbootworking=setenv bootargs $workingbootargs" \
531 " console=$consoledev,$baudrate $othbootargs; " \
532 "run norloadworking; " \
533 "bootm $kerneladdr - $dtbaddr\0" \
534 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
535 "setenv cramfsaddr $nor_recoveryaddr; " \
536 "cramfsload $dtbaddr $dtbfile; " \
537 "cramfsload $kerneladdr $kernelfile\0" \
538 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
539 "setenv cramfsaddr $nor_workingaddr; " \
540 "cramfsload $dtbaddr $dtbfile; " \
541 "cramfsload $kerneladdr $kernelfile\0" \
542 "prog_spi_mbr=run spi__mbr\0" \
543 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
544 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
545 "run spi__cramfs\0" \
546 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
547 " console=$consoledev,$baudrate $othbootargs; " \
548 "tftp $rootfsaddr $rootfsfile; " \
549 "tftp $loadaddr $kernelfile; " \
550 "tftp $dtbaddr $dtbfile; " \
551 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
552 "ramdisk_size=120000\0" \
553 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
554 "recoveryaddr=0x02F00000\0" \
555 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
556 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
557 "mw.l 0xffe0f008 0x00400000\0" \
558 "rootfsaddr=0x02F00000\0" \
559 "rootfsfile=rootfs.ext2.gz.uboot\0" \
560 "rootpath=/opt/nfsroot\0" \
561 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
562 "protect off 0xeC000000 +$filesize; " \
563 "erase 0xEC000000 +$filesize; " \
564 "cp.b $loadaddr 0xEC000000 $filesize; " \
565 "cmp.b $loadaddr 0xEC000000 $filesize; " \
566 "protect on 0xeC000000 +$filesize\0" \
567 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
568 "protect off 0xeFF80000 +$filesize; " \
569 "erase 0xEFF80000 +$filesize; " \
570 "cp.b $loadaddr 0xEFF80000 $filesize; " \
571 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
572 "protect on 0xeFF80000 +$filesize\0" \
573 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
574 "sf probe 0; sf erase 0x8000 +$filesize; " \
575 "sf write $loadaddr 0x8000 $filesize\0" \
576 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
577 "protect off 0xec0a0000 +$filesize; " \
578 "erase 0xeC0A0000 +$filesize; " \
579 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
580 "protect on 0xec0a0000 +$filesize\0" \
581 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
582 "sf probe 1; sf erase 0 +$filesize; " \
583 "sf write $loadaddr 0 $filesize\0" \
584 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
585 "sf probe 0; sf erase 0 +$filesize; " \
586 "sf write $loadaddr 0 $filesize\0" \
587 "tftpflash=tftpboot $loadaddr $uboot; " \
588 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
589 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
590 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
591 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
592 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
593 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
594 "ubootaddr=0x01000000\0" \
595 "ubootfile=u-boot.bin\0" \
596 "ubootd=u-boot4dongle.bin\0" \
597 "upgrade=run flashworking\0" \
598 "usb_phy_type=ulpi\0 " \
599 "workingaddr=0x02F00000\0" \
600 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
604 #if defined(CONFIG_UCP1020T1)
606 #define CONFIG_EXTRA_ENV_SETTINGS \
607 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
608 "bootfile=uImage\0" \
609 "consoledev=ttyS0\0" \
610 "cramfsfile=image.cramfs\0" \
611 "dtbaddr=0x00c00000\0" \
612 "dtbfile=image.dtb\0" \
613 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
614 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
615 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
616 "fileaddr=0x01000000\0" \
617 "filesize=0x00080000\0" \
618 "flashmbr=sf probe 0; " \
619 "tftp $loadaddr $mbr; " \
620 "sf erase $mbr_offset +$filesize; " \
621 "sf write $loadaddr $mbr_offset $filesize\0" \
622 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
623 "protect off $nor_recoveryaddr +$filesize; " \
624 "erase $nor_recoveryaddr +$filesize; " \
625 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
626 "protect on $nor_recoveryaddr +$filesize\0 " \
627 "flashuboot=tftp $ubootaddr $ubootfile; " \
628 "protect off $nor_ubootaddr +$filesize; " \
629 "erase $nor_ubootaddr +$filesize; " \
630 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
631 "protect on $nor_ubootaddr +$filesize\0 " \
632 "flashworking=tftp $workingaddr $cramfsfile; " \
633 "protect off $nor_workingaddr +$filesize; " \
634 "erase $nor_workingaddr +$filesize; " \
635 "cp.b $workingaddr $nor_workingaddr $filesize; " \
636 "protect on $nor_workingaddr +$filesize\0 " \
637 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
638 "kerneladdr=0x01100000\0" \
639 "kernelfile=uImage\0" \
640 "loadaddr=0x01000000\0" \
641 "mbr=uCP1020.mbr\0" \
642 "mbr_offset=0x00000000\0" \
644 "nor_recoveryaddr=0xEC0A0000\0" \
645 "nor_ubootaddr=0xEFF80000\0" \
646 "nor_workingaddr=0xECFA0000\0" \
647 "norbootrecovery=setenv bootargs $recoverybootargs" \
648 " console=$consoledev,$baudrate $othbootargs; " \
649 "run norloadrecovery; " \
650 "bootm $kerneladdr - $dtbaddr\0" \
651 "norbootworking=setenv bootargs $workingbootargs" \
652 " console=$consoledev,$baudrate $othbootargs; " \
653 "run norloadworking; " \
654 "bootm $kerneladdr - $dtbaddr\0" \
655 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
656 "setenv cramfsaddr $nor_recoveryaddr; " \
657 "cramfsload $dtbaddr $dtbfile; " \
658 "cramfsload $kerneladdr $kernelfile\0" \
659 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
660 "setenv cramfsaddr $nor_workingaddr; " \
661 "cramfsload $dtbaddr $dtbfile; " \
662 "cramfsload $kerneladdr $kernelfile\0" \
663 "othbootargs=quiet\0" \
664 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
665 " console=$consoledev,$baudrate $othbootargs; " \
666 "tftp $rootfsaddr $rootfsfile; " \
667 "tftp $loadaddr $kernelfile; " \
668 "tftp $dtbaddr $dtbfile; " \
669 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
670 "ramdisk_size=120000\0" \
671 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
672 "recoveryaddr=0x02F00000\0" \
673 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
674 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
675 "mw.l 0xffe0f008 0x00400000\0" \
676 "rootfsaddr=0x02F00000\0" \
677 "rootfsfile=rootfs.ext2.gz.uboot\0" \
678 "rootpath=/opt/nfsroot\0" \
680 "tftpflash=tftpboot $loadaddr $uboot; " \
681 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
682 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
683 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
684 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
685 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
686 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
687 "ubootaddr=0x01000000\0" \
688 "ubootfile=u-boot.bin\0" \
689 "upgrade=run flashworking\0" \
690 "workingaddr=0x02F00000\0" \
691 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
693 #else /* For Arcturus Modules */
695 #define CONFIG_EXTRA_ENV_SETTINGS \
696 "bootcmd=run norkernel\0" \
697 "bootfile=uImage\0" \
698 "consoledev=ttyS0\0" \
699 "dtbaddr=0x00c00000\0" \
700 "dtbfile=image.dtb\0" \
701 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
702 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
703 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
704 "fileaddr=0x01000000\0" \
705 "filesize=0x00080000\0" \
706 "flashmbr=sf probe 0; " \
707 "tftp $loadaddr $mbr; " \
708 "sf erase $mbr_offset +$filesize; " \
709 "sf write $loadaddr $mbr_offset $filesize\0" \
710 "flashuboot=tftp $loadaddr $ubootfile; " \
711 "protect off $nor_ubootaddr0 +$filesize; " \
712 "erase $nor_ubootaddr0 +$filesize; " \
713 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
714 "protect on $nor_ubootaddr0 +$filesize; " \
715 "protect off $nor_ubootaddr1 +$filesize; " \
716 "erase $nor_ubootaddr1 +$filesize; " \
717 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
718 "protect on $nor_ubootaddr1 +$filesize\0 " \
719 "format0=protect off $part0base +$part0size; " \
720 "erase $part0base +$part0size\0" \
721 "format1=protect off $part1base +$part1size; " \
722 "erase $part1base +$part1size\0" \
723 "format2=protect off $part2base +$part2size; " \
724 "erase $part2base +$part2size\0" \
725 "format3=protect off $part3base +$part3size; " \
726 "erase $part3base +$part3size\0" \
727 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
728 "kerneladdr=0x01100000\0" \
729 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
730 "kernelfile=uImage\0" \
731 "loadaddr=0x01000000\0" \
732 "mbr=uCP1020.mbr\0" \
733 "mbr_offset=0x00000000\0" \
735 "nor_ubootaddr0=0xEC000000\0" \
736 "nor_ubootaddr1=0xEFF80000\0" \
737 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
738 "run norkernelload; " \
739 "bootm $kerneladdr - $dtbaddr\0" \
740 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
741 "setenv cramfsaddr $part0base; " \
742 "cramfsload $dtbaddr $dtbfile; " \
743 "cramfsload $kerneladdr $kernelfile\0" \
744 "part0base=0xEC100000\0" \
745 "part0size=0x00700000\0" \
746 "part1base=0xEC800000\0" \
747 "part1size=0x02000000\0" \
748 "part2base=0xEE800000\0" \
749 "part2size=0x00800000\0" \
750 "part3base=0xEF000000\0" \
751 "part3size=0x00F80000\0" \
752 "partENVbase=0xEC080000\0" \
753 "partENVsize=0x00080000\0" \
754 "program0=tftp part0-000000.bin; " \
755 "protect off $part0base +$filesize; " \
756 "erase $part0base +$filesize; " \
757 "cp.b $loadaddr $part0base $filesize; " \
758 "echo Verifying...; " \
759 "cmp.b $loadaddr $part0base $filesize\0" \
760 "program1=tftp part1-000000.bin; " \
761 "protect off $part1base +$filesize; " \
762 "erase $part1base +$filesize; " \
763 "cp.b $loadaddr $part1base $filesize; " \
764 "echo Verifying...; " \
765 "cmp.b $loadaddr $part1base $filesize\0" \
766 "program2=tftp part2-000000.bin; " \
767 "protect off $part2base +$filesize; " \
768 "erase $part2base +$filesize; " \
769 "cp.b $loadaddr $part2base $filesize; " \
770 "echo Verifying...; " \
771 "cmp.b $loadaddr $part2base $filesize\0" \
772 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
773 " console=$consoledev,$baudrate $othbootargs; " \
774 "tftp $rootfsaddr $rootfsfile; " \
775 "tftp $loadaddr $kernelfile; " \
776 "tftp $dtbaddr $dtbfile; " \
777 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
778 "ramdisk_size=120000\0" \
779 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
780 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
781 "mw.l 0xffe0f008 0x00400000\0" \
782 "rootfsaddr=0x02F00000\0" \
783 "rootfsfile=rootfs.ext2.gz.uboot\0" \
784 "rootpath=/opt/nfsroot\0" \
785 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
786 "sf probe 0; sf erase 0 +$filesize; " \
787 "sf write $loadaddr 0 $filesize\0" \
788 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
789 "protect off 0xeC000000 +$filesize; " \
790 "erase 0xEC000000 +$filesize; " \
791 "cp.b $loadaddr 0xEC000000 $filesize; " \
792 "cmp.b $loadaddr 0xEC000000 $filesize; " \
793 "protect on 0xeC000000 +$filesize\0" \
794 "tftpflash=tftpboot $loadaddr $uboot; " \
795 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
796 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
797 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
798 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
799 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
800 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
801 "ubootfile=u-boot.bin\0" \
802 "upgrade=run flashuboot\0" \
803 "usb_phy_type=ulpi\0 " \
805 "setenv bootargs root=/dev/nfs rw " \
806 "nfsroot=$serverip:$rootpath " \
807 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
808 "console=$consoledev,$baudrate $othbootargs;" \
809 "tftp $loadaddr $bootfile;" \
810 "tftp $fdtaddr $fdtfile;" \
811 "bootm $loadaddr - $fdtaddr\0" \
813 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
814 "console=$consoledev,$baudrate $othbootargs;" \
816 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
817 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
818 "bootm $loadaddr - $fdtaddr\0" \
820 "setenv bootargs root=/dev/ram rw " \
821 "console=$consoledev,$baudrate $othbootargs " \
822 "ramdisk_size=$ramdisk_size;" \
824 "fatload usb 0:2 $loadaddr $bootfile;" \
825 "fatload usb 0:2 $fdtaddr $fdtfile;" \
826 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
827 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
829 "setenv bootargs root=/dev/ram rw " \
830 "console=$consoledev,$baudrate $othbootargs " \
831 "ramdisk_size=$ramdisk_size;" \
833 "ext2load usb 0:4 $loadaddr $bootfile;" \
834 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
835 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
836 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
838 "setenv bootargs root=/dev/$jffs2nor rw " \
839 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
840 "bootm $norbootaddr - $norfdtaddr\0 " \
842 "setenv bootargs root=/dev/ram rw " \
843 "console=$consoledev,$baudrate $othbootargs " \
844 "ramdisk_size=$ramdisk_size;" \
845 "tftp $ramdiskaddr $ramdiskfile;" \
846 "tftp $loadaddr $bootfile;" \
847 "tftp $fdtaddr $fdtfile;" \
848 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
853 #endif /* __CONFIG_H */