git.sur5r.net Git - u-boot/blob - include/configs/UCP1020.h

   1 /*
   2  * Copyright 2013-2015 Arcturus Networks, Inc.
   3  *           http://www.arcturusnetworks.com/products/ucp1020/
   4  * based on include/configs/p1_p2_rdb_pc.h
   5  * original copyright follows:
   6  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * QorIQ uCP1020-xx boards configuration file
  13  */
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
  18 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
  19 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  20 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  21 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  22 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  23
  24 #if defined(CONFIG_TARTGET_UCP1020T1)
  25
  26 #define CONFIG_UCP1020_REV_1_3
  27
  28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
  29
  30 #define CONFIG_TSEC_ENET
  31 #define CONFIG_TSEC1
  32 #define CONFIG_TSEC3
  33 #define CONFIG_HAS_ETH0
  34 #define CONFIG_HAS_ETH1
  35 #define CONFIG_ETHADDR          00:19:D3:FF:FF:FF
  36 #define CONFIG_ETH1ADDR         00:19:D3:FF:FF:FE
  37 #define CONFIG_ETH2ADDR         00:19:D3:FF:FF:FD
  38 #define CONFIG_IPADDR           10.80.41.229
  39 #define CONFIG_SERVERIP         10.80.41.227
  40 #define CONFIG_NETMASK          255.255.252.0
  41 #define CONFIG_ETHPRIME         "eTSEC3"
  42
  43 #ifndef CONFIG_SPI_FLASH
  44 #endif
  45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  46
  47 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  48
  49 #define CONFIG_LAST_STAGE_INIT
  50
  51 #endif
  52
  53 #if defined(CONFIG_TARGET_UCP1020)
  54
  55 #define CONFIG_UCP1020
  56 #define CONFIG_UCP1020_REV_1_3
  57
  58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
  59
  60 #define CONFIG_TSEC_ENET
  61 #define CONFIG_TSEC1
  62 #define CONFIG_TSEC2
  63 #define CONFIG_TSEC3
  64 #define CONFIG_HAS_ETH0
  65 #define CONFIG_HAS_ETH1
  66 #define CONFIG_HAS_ETH2
  67 #define CONFIG_ETHADDR          00:06:3B:FF:FF:FF
  68 #define CONFIG_ETH1ADDR         00:06:3B:FF:FF:FE
  69 #define CONFIG_ETH2ADDR         00:06:3B:FF:FF:FD
  70 #define CONFIG_IPADDR           192.168.1.81
  71 #define CONFIG_IPADDR1          192.168.1.82
  72 #define CONFIG_IPADDR2          192.168.1.83
  73 #define CONFIG_SERVERIP         192.168.1.80
  74 #define CONFIG_GATEWAYIP        102.168.1.1
  75 #define CONFIG_NETMASK          255.255.255.0
  76 #define CONFIG_ETHPRIME         "eTSEC1"
  77
  78 #ifndef CONFIG_SPI_FLASH
  79 #endif
  80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  81
  82 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  83
  84 #define CONFIG_LAST_STAGE_INIT
  85
  86 #endif
  87
  88 #ifdef CONFIG_SDCARD
  89 #define CONFIG_RAMBOOT_SDCARD
  90 #define CONFIG_SYS_RAMBOOT
  91 #define CONFIG_SYS_EXTRA_ENV_RELOC
  92 #define CONFIG_SYS_TEXT_BASE            0x11000000
  93 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  94 #endif
  95
  96 #ifdef CONFIG_SPIFLASH
  97 #define CONFIG_RAMBOOT_SPIFLASH
  98 #define CONFIG_SYS_RAMBOOT
  99 #define CONFIG_SYS_EXTRA_ENV_RELOC
 100 #define CONFIG_SYS_TEXT_BASE            0x11000000
 101 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
 102 #endif
 103
 104 #ifndef CONFIG_SYS_TEXT_BASE
 105 #define CONFIG_SYS_TEXT_BASE            0xeff80000
 106 #endif
 107 #define CONFIG_SYS_TEXT_BASE_NOR        0xeff80000
 108
 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 110 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 111 #endif
 112
 113 #ifndef CONFIG_SYS_MONITOR_BASE
 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 115 #endif
 116
 117 #define CONFIG_MP
 118
 119 #define CONFIG_ENV_OVERWRITE
 120
 121 #define CONFIG_CMD_SATA
 122 #define CONFIG_SATA_SIL
 123 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 124 #define CONFIG_LIBATA
 125 #define CONFIG_LBA48
 126
 127 #define CONFIG_SYS_CLK_FREQ     66666666
 128 #define CONFIG_DDR_CLK_FREQ     66666666
 129
 130 #define CONFIG_HWCONFIG
 131
 132 /*
 133  * These can be toggled for performance analysis, otherwise use default.
 134  */
 135 #define CONFIG_L2_CACHE
 136 #define CONFIG_BTB
 137
 138 #define CONFIG_ENABLE_36BIT_PHYS
 139
 140 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 141 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 142 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 143
 144 #define CONFIG_SYS_CCSRBAR              0xffe00000
 145 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 146
 147 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 148        SPL code*/
 149 #ifdef CONFIG_SPL_BUILD
 150 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 151 #endif
 152
 153 /* DDR Setup */
 154 #define CONFIG_DDR_ECC_ENABLE
 155 #ifndef CONFIG_DDR_ECC_ENABLE
 156 #define CONFIG_SYS_DDR_RAW_TIMING
 157 #define CONFIG_DDR_SPD
 158 #endif
 159 #define CONFIG_SYS_SPD_BUS_NUM 1
 160 #undef CONFIG_FSL_DDR_INTERACTIVE
 161
 162 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
 163 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 164 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 165 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 166 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 167
 168 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 169
 170 /* Default settings for DDR3 */
 171 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 172 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 173 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 174 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 175 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 176 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 177
 178 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 179 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 180 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 181 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 182
 183 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 184 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 185 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 186 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 187 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 188 #ifdef CONFIG_DDR_ECC_ENABLE
 189 #define CONFIG_SYS_DDR_CONTROL          0xE70C0000      /* Type = DDR3 & ECC */
 190 #else
 191 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3 */
 192 #endif
 193 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 194 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 195 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 196
 197 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 198 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 199 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 200 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 201 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 202 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 203 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 204 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 205
 206 #undef CONFIG_CLOCKS_IN_MHZ
 207
 208 /*
 209  * Memory map
 210  *
 211  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 212  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1G non-cacheable(PCIe * 2)
 213  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 214  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 256K cacheable
 215  *   (early boot only)
 216  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 217  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 218  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 219  */
 220
 221 /*
 222  * Local Bus Definitions
 223  */
 224 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 225 #define CONFIG_SYS_FLASH_BASE           0xec000000
 226
 227 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 228
 229 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 230         | BR_PS_16 | BR_V)
 231
 232 #define CONFIG_FLASH_OR_PRELIM          0xfc000ff7
 233
 234 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 235 #define CONFIG_SYS_FLASH_QUIET_TEST
 236 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 237
 238 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 239
 240 #undef CONFIG_SYS_FLASH_CHECKSUM
 241 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 242 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 243
 244 #define CONFIG_FLASH_CFI_DRIVER
 245 #define CONFIG_SYS_FLASH_CFI
 246 #define CONFIG_SYS_FLASH_EMPTY_INFO
 247 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 248
 249 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 250
 251 #define CONFIG_SYS_INIT_RAM_LOCK
 252 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 253 /* Initial L1 address */
 254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 255 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 256 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 257 /* Size of used area in RAM */
 258 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 259
 260 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 261                                         GENERATED_GBL_DATA_SIZE)
 262 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 263
 264 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)/* Reserve 256 kB for Mon */
 265 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 266
 267 #define CONFIG_SYS_PMC_BASE     0xff980000
 268 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 269 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 270                                         BR_PS_8 | BR_V)
 271 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 272                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 273                                  OR_GPCM_EAD)
 274
 275 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 276 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 277 #ifdef CONFIG_NAND_FSL_ELBC
 278 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 279 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 280 #endif
 281
 282 /* Serial Port - controlled on board with jumper J8
 283  * open - index 2
 284  * shorted - index 1
 285  */
 286 #define CONFIG_CONS_INDEX               1
 287 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 288 #define CONFIG_SYS_NS16550_SERIAL
 289 #define CONFIG_SYS_NS16550_REG_SIZE     1
 290 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 291 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 292 #define CONFIG_NS16550_MIN_FUNCTIONS
 293 #endif
 294
 295 #define CONFIG_SYS_BAUDRATE_TABLE       \
 296         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 297
 298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 300
 301 /* I2C */
 302 #define CONFIG_SYS_I2C
 303 #define CONFIG_SYS_I2C_FSL
 304 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 305 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 306 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 307 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 308 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 309 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 310 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 311 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 312
 313 #define CONFIG_RTC_DS1337
 314 #define CONFIG_RTC_DS1337_NOOSC
 315 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 316 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 317 #define CONFIG_SYS_I2C_NCT72_ADDR       0x4C
 318 #define CONFIG_SYS_I2C_IDT6V49205B      0x69
 319
 320 /*
 321  * eSPI - Enhanced SPI
 322  */
 323 #define CONFIG_HARD_SPI
 324
 325 #define CONFIG_SF_DEFAULT_SPEED         10000000
 326 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 327
 328 #if defined(CONFIG_PCI)
 329 /*
 330  * General PCI
 331  * Memory space is mapped 1-1, but I/O space must start from 0.
 332  */
 333
 334 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 335 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT CON9"
 336 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 337 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 338 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 339 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 340 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 341 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 342 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 343 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 344
 345 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 346 #define CONFIG_SYS_PCIE1_NAME           "PCIe SLOT CON10"
 347 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 348 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 349 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 350 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 351 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 352 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 353 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 354 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 355
 356 #define CONFIG_CMD_PCI
 357
 358 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 359 #endif /* CONFIG_PCI */
 360
 361 /*
 362  * Environment
 363  */
 364 #ifdef CONFIG_ENV_FIT_UCBOOT
 365
 366 #define CONFIG_ENV_IS_IN_FLASH
 367 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x20000)
 368 #define CONFIG_ENV_SIZE         0x20000
 369 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 370
 371 #else
 372
 373 #define CONFIG_ENV_SPI_BUS      0
 374 #define CONFIG_ENV_SPI_CS       0
 375 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 376 #define CONFIG_ENV_SPI_MODE     0
 377
 378 #ifdef CONFIG_RAMBOOT_SPIFLASH
 379
 380 #define CONFIG_ENV_IS_IN_SPI_FLASH
 381 #define CONFIG_ENV_SIZE         0x3000          /* 12KB */
 382 #define CONFIG_ENV_OFFSET       0x2000          /* 8KB */
 383 #define CONFIG_ENV_SECT_SIZE    0x1000
 384
 385 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
 386 /* Address and size of Redundant Environment Sector     */
 387 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 388 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 389 #endif
 390
 391 #elif defined(CONFIG_RAMBOOT_SDCARD)
 392 #define CONFIG_ENV_IS_IN_MMC
 393 #define CONFIG_FSL_FIXED_MMC_LOCATION
 394 #define CONFIG_ENV_SIZE         0x2000
 395 #define CONFIG_SYS_MMC_ENV_DEV  0
 396
 397 #elif defined(CONFIG_SYS_RAMBOOT)
 398 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 399 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 400 #define CONFIG_ENV_SIZE         0x2000
 401
 402 #else
 403 #define CONFIG_ENV_IS_IN_FLASH
 404 #define CONFIG_ENV_BASE         (CONFIG_SYS_FLASH_BASE)
 405 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 406 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 407 #define CONFIG_ENV_ADDR         (CONFIG_ENV_BASE + 0xC0000)
 408 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
 409 /* Address and size of Redundant Environment Sector     */
 410 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 411 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 412 #endif
 413
 414 #endif
 415
 416 #endif  /* CONFIG_ENV_FIT_UCBOOT */
 417
 418 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 419 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 420
 421 /*
 422  * Command line configuration.
 423  */
 424 #define CONFIG_CMD_REGINFO
 425
 426 /*
 427  * USB
 428  */
 429 #define CONFIG_HAS_FSL_DR_USB
 430
 431 #if defined(CONFIG_HAS_FSL_DR_USB)
 432 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 433
 434 #ifdef CONFIG_USB_EHCI_HCD
 435 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 436 #define CONFIG_USB_EHCI_FSL
 437 #endif
 438 #endif
 439
 440 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 441
 442 #ifdef CONFIG_MMC
 443 #define CONFIG_FSL_ESDHC
 444 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 445 #define CONFIG_MMC_SPI
 446 #define CONFIG_CMD_MMC_SPI
 447 #endif
 448
 449 /* Misc Extra Settings */
 450 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 451
 452 /*
 453  * Miscellaneous configurable options
 454  */
 455 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 456 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 457 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 458 #if defined(CONFIG_CMD_KGDB)
 459 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 460 #else
 461 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 462 #endif
 463 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 464         /* Print Buffer Size */
 465 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 466 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 467 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms tick */
 468
 469 /*
 470  * For booting Linux, the board info and command line data
 471  * have to be in the first 64 MB of memory, since this is
 472  * the maximum mapped by the Linux kernel during initialization.
 473  */
 474 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 475 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 476
 477 #if defined(CONFIG_CMD_KGDB)
 478 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 479 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 480 #endif
 481
 482 /*
 483  * Environment Configuration
 484  */
 485
 486 #if defined(CONFIG_TSEC_ENET)
 487
 488 #if defined(CONFIG_UCP1020_REV_1_2)
 489 #define CONFIG_PHY_MICREL_KSZ9021
 490 #elif defined(CONFIG_UCP1020_REV_1_3)
 491 #define CONFIG_PHY_MICREL_KSZ9031
 492 #else
 493 #error "UCP1020 module revision is not defined !!!"
 494 #endif
 495
 496 #define CONFIG_BOOTP_SERVERIP
 497
 498 #define CONFIG_MII              /* MII PHY management */
 499 #define CONFIG_TSEC1_NAME       "eTSEC1"
 500 #define CONFIG_TSEC2_NAME       "eTSEC2"
 501 #define CONFIG_TSEC3_NAME       "eTSEC3"
 502
 503 #define TSEC1_PHY_ADDR  4
 504 #define TSEC2_PHY_ADDR  0
 505 #define TSEC2_PHY_ADDR_SGMII    0x00
 506 #define TSEC3_PHY_ADDR  6
 507
 508 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 509 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 510 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 511
 512 #define TSEC1_PHYIDX    0
 513 #define TSEC2_PHYIDX    0
 514 #define TSEC3_PHYIDX    0
 515
 516 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 517
 518 #endif
 519
 520 #define CONFIG_HOSTNAME         UCP1020
 521 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 522 #define CONFIG_BOOTFILE         "uImage"
 523 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 524
 525 /* default location for tftp and bootm */
 526 #define CONFIG_LOADADDR         1000000
 527
 528 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 529
 530 #if defined(CONFIG_DONGLE)
 531
 532 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 533 "bootcmd=run prog_spi_mbrbootcramfs\0"                                  \
 534 "bootfile=uImage\0"                                                     \
 535 "consoledev=ttyS0\0"                                                    \
 536 "cramfsfile=image.cramfs\0"                                             \
 537 "dtbaddr=0x00c00000\0"                                                  \
 538 "dtbfile=image.dtb\0"                                                   \
 539 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
 540 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
 541 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
 542 "fileaddr=0x01000000\0"                                                 \
 543 "filesize=0x00080000\0"                                                 \
 544 "flashmbr=sf probe 0; "                                                 \
 545         "tftp $loadaddr $mbr; "                                         \
 546         "sf erase $mbr_offset +$filesize; "                             \
 547         "sf write $loadaddr $mbr_offset $filesize\0"                    \
 548 "flashrecovery=tftp $recoveryaddr $cramfsfile; "                        \
 549         "protect off $nor_recoveryaddr +$filesize; "                    \
 550         "erase $nor_recoveryaddr +$filesize; "                          \
 551         "cp.b $recoveryaddr $nor_recoveryaddr $filesize; "              \
 552         "protect on $nor_recoveryaddr +$filesize\0 "                    \
 553 "flashuboot=tftp $ubootaddr $ubootfile; "                               \
 554         "protect off $nor_ubootaddr +$filesize; "                       \
 555         "erase $nor_ubootaddr +$filesize; "                             \
 556         "cp.b $ubootaddr $nor_ubootaddr $filesize; "                    \
 557         "protect on $nor_ubootaddr +$filesize\0 "                       \
 558 "flashworking=tftp $workingaddr $cramfsfile; "                          \
 559         "protect off $nor_workingaddr +$filesize; "                     \
 560         "erase $nor_workingaddr +$filesize; "                           \
 561         "cp.b $workingaddr $nor_workingaddr $filesize; "                \
 562         "protect on $nor_workingaddr +$filesize\0 "                     \
 563 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
 564 "kerneladdr=0x01100000\0"                                               \
 565 "kernelfile=uImage\0"                                                   \
 566 "loadaddr=0x01000000\0"                                                 \
 567 "mbr=uCP1020d.mbr\0"                                                    \
 568 "mbr_offset=0x00000000\0"                                               \
 569 "mmbr=uCP1020Quiet.mbr\0"                                               \
 570 "mmcpart=0:2\0"                                                         \
 571 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "                       \
 572         "mmc erase 1 1; "                                               \
 573         "mmc write $loadaddr 1 1\0"                                     \
 574 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; "                \
 575         "mmc erase 0x40 0x400; "                                        \
 576         "mmc write $loadaddr 0x40 0x400\0"                              \
 577 "netdev=eth0\0"                                                         \
 578 "nor_recoveryaddr=0xEC0A0000\0"                                         \
 579 "nor_ubootaddr=0xEFF80000\0"                                            \
 580 "nor_workingaddr=0xECFA0000\0"                                          \
 581 "norbootrecovery=setenv bootargs $recoverybootargs"                     \
 582         " console=$consoledev,$baudrate $othbootargs; "                 \
 583         "run norloadrecovery; "                                         \
 584         "bootm $kerneladdr - $dtbaddr\0"                                \
 585 "norbootworking=setenv bootargs $workingbootargs"                       \
 586         " console=$consoledev,$baudrate $othbootargs; "                 \
 587         "run norloadworking; "                                          \
 588         "bootm $kerneladdr - $dtbaddr\0"                                \
 589 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "                     \
 590         "setenv cramfsaddr $nor_recoveryaddr; "                         \
 591         "cramfsload $dtbaddr $dtbfile; "                                \
 592         "cramfsload $kerneladdr $kernelfile\0"                          \
 593 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "                      \
 594         "setenv cramfsaddr $nor_workingaddr; "                          \
 595         "cramfsload $dtbaddr $dtbfile; "                                \
 596         "cramfsload $kerneladdr $kernelfile\0"                          \
 597 "prog_spi_mbr=run spi__mbr\0"                                           \
 598 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0"       \
 599 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
 600         "run spi__cramfs\0"                                             \
 601 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
 602         " console=$consoledev,$baudrate $othbootargs; "                 \
 603         "tftp $rootfsaddr $rootfsfile; "                                \
 604         "tftp $loadaddr $kernelfile; "                                  \
 605         "tftp $dtbaddr $dtbfile; "                                      \
 606         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
 607 "ramdisk_size=120000\0"                                                 \
 608 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
 609 "recoveryaddr=0x02F00000\0"                                             \
 610 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"           \
 611 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
 612         "mw.l 0xffe0f008 0x00400000\0"                                  \
 613 "rootfsaddr=0x02F00000\0"                                               \
 614 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
 615 "rootpath=/opt/nfsroot\0"                                               \
 616 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; "                \
 617         "protect off 0xeC000000 +$filesize; "                           \
 618         "erase 0xEC000000 +$filesize; "                                 \
 619         "cp.b $loadaddr 0xEC000000 $filesize; "                         \
 620         "cmp.b $loadaddr 0xEC000000 $filesize; "                        \
 621         "protect on 0xeC000000 +$filesize\0"                            \
 622 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; "                \
 623         "protect off 0xeFF80000 +$filesize; "                           \
 624         "erase 0xEFF80000 +$filesize; "                                 \
 625         "cp.b $loadaddr 0xEFF80000 $filesize; "                         \
 626         "cmp.b $loadaddr 0xEFF80000 $filesize; "                        \
 627         "protect on 0xeFF80000 +$filesize\0"                            \
 628 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; "                   \
 629         "sf probe 0; sf erase 0x8000 +$filesize; "                      \
 630         "sf write $loadaddr 0x8000 $filesize\0"                         \
 631 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; "             \
 632         "protect off 0xec0a0000 +$filesize; "                           \
 633         "erase 0xeC0A0000 +$filesize; "                                 \
 634         "cp.b $loadaddr 0xeC0A0000 $filesize; "                         \
 635         "protect on 0xec0a0000 +$filesize\0"                            \
 636 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "                       \
 637         "sf probe 1; sf erase 0 +$filesize; "                           \
 638         "sf write $loadaddr 0 $filesize\0"                              \
 639 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "                       \
 640         "sf probe 0; sf erase 0 +$filesize; "                           \
 641         "sf write $loadaddr 0 $filesize\0"                              \
 642 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
 643         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 644         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
 645         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
 646         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 647         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
 648 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
 649 "ubootaddr=0x01000000\0"                                                \
 650 "ubootfile=u-boot.bin\0"                                                \
 651 "ubootd=u-boot4dongle.bin\0"                                            \
 652 "upgrade=run flashworking\0"                                            \
 653 "usb_phy_type=ulpi\0 "                                                  \
 654 "workingaddr=0x02F00000\0"                                              \
 655 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
 656
 657 #else
 658
 659 #if defined(CONFIG_UCP1020T1)
 660
 661 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 662 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0"  \
 663 "bootfile=uImage\0"                                                     \
 664 "consoledev=ttyS0\0"                                                    \
 665 "cramfsfile=image.cramfs\0"                                             \
 666 "dtbaddr=0x00c00000\0"                                                  \
 667 "dtbfile=image.dtb\0"                                                   \
 668 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
 669 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
 670 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
 671 "fileaddr=0x01000000\0"                                                 \
 672 "filesize=0x00080000\0"                                                 \
 673 "flashmbr=sf probe 0; "                                                 \
 674         "tftp $loadaddr $mbr; "                                         \
 675         "sf erase $mbr_offset +$filesize; "                             \
 676         "sf write $loadaddr $mbr_offset $filesize\0"                    \
 677 "flashrecovery=tftp $recoveryaddr $cramfsfile; "                        \
 678         "protect off $nor_recoveryaddr +$filesize; "                    \
 679         "erase $nor_recoveryaddr +$filesize; "                          \
 680         "cp.b $recoveryaddr $nor_recoveryaddr $filesize; "              \
 681         "protect on $nor_recoveryaddr +$filesize\0 "                    \
 682 "flashuboot=tftp $ubootaddr $ubootfile; "                               \
 683         "protect off $nor_ubootaddr +$filesize; "                       \
 684         "erase $nor_ubootaddr +$filesize; "                             \
 685         "cp.b $ubootaddr $nor_ubootaddr $filesize; "                    \
 686         "protect on $nor_ubootaddr +$filesize\0 "                       \
 687 "flashworking=tftp $workingaddr $cramfsfile; "                          \
 688         "protect off $nor_workingaddr +$filesize; "                     \
 689         "erase $nor_workingaddr +$filesize; "                           \
 690         "cp.b $workingaddr $nor_workingaddr $filesize; "                \
 691         "protect on $nor_workingaddr +$filesize\0 "                     \
 692 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
 693 "kerneladdr=0x01100000\0"                                               \
 694 "kernelfile=uImage\0"                                                   \
 695 "loadaddr=0x01000000\0"                                                 \
 696 "mbr=uCP1020.mbr\0"                                                     \
 697 "mbr_offset=0x00000000\0"                                               \
 698 "netdev=eth0\0"                                                         \
 699 "nor_recoveryaddr=0xEC0A0000\0"                                         \
 700 "nor_ubootaddr=0xEFF80000\0"                                            \
 701 "nor_workingaddr=0xECFA0000\0"                                          \
 702 "norbootrecovery=setenv bootargs $recoverybootargs"                     \
 703         " console=$consoledev,$baudrate $othbootargs; "                 \
 704         "run norloadrecovery; "                                         \
 705         "bootm $kerneladdr - $dtbaddr\0"                                \
 706 "norbootworking=setenv bootargs $workingbootargs"                       \
 707         " console=$consoledev,$baudrate $othbootargs; "                 \
 708         "run norloadworking; "                                          \
 709         "bootm $kerneladdr - $dtbaddr\0"                                \
 710 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "                     \
 711         "setenv cramfsaddr $nor_recoveryaddr; "                         \
 712         "cramfsload $dtbaddr $dtbfile; "                                \
 713         "cramfsload $kerneladdr $kernelfile\0"                          \
 714 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "                      \
 715         "setenv cramfsaddr $nor_workingaddr; "                          \
 716         "cramfsload $dtbaddr $dtbfile; "                                \
 717         "cramfsload $kerneladdr $kernelfile\0"                          \
 718 "othbootargs=quiet\0"                                                   \
 719 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
 720         " console=$consoledev,$baudrate $othbootargs; "                 \
 721         "tftp $rootfsaddr $rootfsfile; "                                \
 722         "tftp $loadaddr $kernelfile; "                                  \
 723         "tftp $dtbaddr $dtbfile; "                                      \
 724         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
 725 "ramdisk_size=120000\0"                                                 \
 726 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
 727 "recoveryaddr=0x02F00000\0"                                             \
 728 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"           \
 729 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
 730         "mw.l 0xffe0f008 0x00400000\0"                                  \
 731 "rootfsaddr=0x02F00000\0"                                               \
 732 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
 733 "rootpath=/opt/nfsroot\0"                                               \
 734 "silent=1\0"                                                            \
 735 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
 736         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 737         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
 738         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
 739         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 740         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
 741 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
 742 "ubootaddr=0x01000000\0"                                                \
 743 "ubootfile=u-boot.bin\0"                                                \
 744 "upgrade=run flashworking\0"                                            \
 745 "workingaddr=0x02F00000\0"                                              \
 746 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
 747
 748 #else /* For Arcturus Modules */
 749
 750 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 751 "bootcmd=run norkernel\0"                                               \
 752 "bootfile=uImage\0"                                                     \
 753 "consoledev=ttyS0\0"                                                    \
 754 "dtbaddr=0x00c00000\0"                                                  \
 755 "dtbfile=image.dtb\0"                                                   \
 756 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
 757 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
 758 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
 759 "fileaddr=0x01000000\0"                                                 \
 760 "filesize=0x00080000\0"                                                 \
 761 "flashmbr=sf probe 0; "                                                 \
 762         "tftp $loadaddr $mbr; "                                         \
 763         "sf erase $mbr_offset +$filesize; "                             \
 764         "sf write $loadaddr $mbr_offset $filesize\0"                    \
 765 "flashuboot=tftp $loadaddr $ubootfile; "                                \
 766         "protect off $nor_ubootaddr0 +$filesize; "                      \
 767         "erase $nor_ubootaddr0 +$filesize; "                            \
 768         "cp.b $loadaddr $nor_ubootaddr0 $filesize; "                    \
 769         "protect on $nor_ubootaddr0 +$filesize; "                       \
 770         "protect off $nor_ubootaddr1 +$filesize; "                      \
 771         "erase $nor_ubootaddr1 +$filesize; "                            \
 772         "cp.b $loadaddr $nor_ubootaddr1 $filesize; "                    \
 773         "protect on $nor_ubootaddr1 +$filesize\0 "                      \
 774 "format0=protect off $part0base +$part0size; "                          \
 775         "erase $part0base +$part0size\0"                                \
 776 "format1=protect off $part1base +$part1size; "                          \
 777         "erase $part1base +$part1size\0"                                \
 778 "format2=protect off $part2base +$part2size; "                          \
 779         "erase $part2base +$part2size\0"                                \
 780 "format3=protect off $part3base +$part3size; "                          \
 781         "erase $part3base +$part3size\0"                                \
 782 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
 783 "kerneladdr=0x01100000\0"                                               \
 784 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"                 \
 785 "kernelfile=uImage\0"                                                   \
 786 "loadaddr=0x01000000\0"                                                 \
 787 "mbr=uCP1020.mbr\0"                                                     \
 788 "mbr_offset=0x00000000\0"                                               \
 789 "netdev=eth0\0"                                                         \
 790 "nor_ubootaddr0=0xEC000000\0"                                           \
 791 "nor_ubootaddr1=0xEFF80000\0"                                           \
 792 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
 793         "run norkernelload; "                                           \
 794         "bootm $kerneladdr - $dtbaddr\0"                                \
 795 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; "                       \
 796         "setenv cramfsaddr $part0base; "                                \
 797         "cramfsload $dtbaddr $dtbfile; "                                \
 798         "cramfsload $kerneladdr $kernelfile\0"                          \
 799 "part0base=0xEC100000\0"                                                \
 800 "part0size=0x00700000\0"                                                \
 801 "part1base=0xEC800000\0"                                                \
 802 "part1size=0x02000000\0"                                                \
 803 "part2base=0xEE800000\0"                                                \
 804 "part2size=0x00800000\0"                                                \
 805 "part3base=0xEF000000\0"                                                \
 806 "part3size=0x00F80000\0"                                                \
 807 "partENVbase=0xEC080000\0"                                              \
 808 "partENVsize=0x00080000\0"                                              \
 809 "program0=tftp part0-000000.bin; "                                      \
 810         "protect off $part0base +$filesize; "                           \
 811         "erase $part0base +$filesize; "                                 \
 812         "cp.b $loadaddr $part0base $filesize; "                         \
 813         "echo Verifying...; "                                           \
 814         "cmp.b $loadaddr $part0base $filesize\0"                        \
 815 "program1=tftp part1-000000.bin; "                                      \
 816         "protect off $part1base +$filesize; "                           \
 817         "erase $part1base +$filesize; "                                 \
 818         "cp.b $loadaddr $part1base $filesize; "                         \
 819         "echo Verifying...; "                                           \
 820         "cmp.b $loadaddr $part1base $filesize\0"                        \
 821 "program2=tftp part2-000000.bin; "                                      \
 822         "protect off $part2base +$filesize; "                           \
 823         "erase $part2base +$filesize; "                                 \
 824         "cp.b $loadaddr $part2base $filesize; "                         \
 825         "echo Verifying...; "                                           \
 826         "cmp.b $loadaddr $part2base $filesize\0"                        \
 827 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
 828         "  console=$consoledev,$baudrate $othbootargs; "                \
 829         "tftp $rootfsaddr $rootfsfile; "                                \
 830         "tftp $loadaddr $kernelfile; "                                  \
 831         "tftp $dtbaddr $dtbfile; "                                      \
 832         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
 833 "ramdisk_size=120000\0"                                                 \
 834 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
 835 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
 836         "mw.l 0xffe0f008 0x00400000\0"                                  \
 837 "rootfsaddr=0x02F00000\0"                                               \
 838 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
 839 "rootpath=/opt/nfsroot\0"                                               \
 840 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "                       \
 841         "sf probe 0; sf erase 0 +$filesize; "                           \
 842         "sf write $loadaddr 0 $filesize\0"                              \
 843 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; "                 \
 844         "protect off 0xeC000000 +$filesize; "                           \
 845         "erase 0xEC000000 +$filesize; "                                 \
 846         "cp.b $loadaddr 0xEC000000 $filesize; "                         \
 847         "cmp.b $loadaddr 0xEC000000 $filesize; "                        \
 848         "protect on 0xeC000000 +$filesize\0"                            \
 849 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
 850         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 851         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
 852         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
 853         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 854         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
 855 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
 856 "ubootfile=u-boot.bin\0"                                                \
 857 "upgrade=run flashuboot\0"                                              \
 858 "usb_phy_type=ulpi\0 "                                                  \
 859 "boot_nfs= "                                                            \
 860         "setenv bootargs root=/dev/nfs rw "                             \
 861         "nfsroot=$serverip:$rootpath "                                  \
 862         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 863         "console=$consoledev,$baudrate $othbootargs;"                   \
 864         "tftp $loadaddr $bootfile;"                                     \
 865         "tftp $fdtaddr $fdtfile;"                                       \
 866         "bootm $loadaddr - $fdtaddr\0"                                  \
 867 "boot_hd = "                                                            \
 868         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "              \
 869         "console=$consoledev,$baudrate $othbootargs;"                   \
 870         "usb start;"                                                    \
 871         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"                   \
 872         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"                     \
 873         "bootm $loadaddr - $fdtaddr\0"                                  \
 874 "boot_usb_fat = "                                                       \
 875         "setenv bootargs root=/dev/ram rw "                             \
 876         "console=$consoledev,$baudrate $othbootargs "                   \
 877         "ramdisk_size=$ramdisk_size;"                                   \
 878         "usb start;"                                                    \
 879         "fatload usb 0:2 $loadaddr $bootfile;"                          \
 880         "fatload usb 0:2 $fdtaddr $fdtfile;"                            \
 881         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"                    \
 882         "bootm $loadaddr $ramdiskaddr $fdtaddr\0 "                      \
 883 "boot_usb_ext2 = "                                                      \
 884         "setenv bootargs root=/dev/ram rw "                             \
 885         "console=$consoledev,$baudrate $othbootargs "                   \
 886         "ramdisk_size=$ramdisk_size;"                                   \
 887         "usb start;"                                                    \
 888         "ext2load usb 0:4 $loadaddr $bootfile;"                         \
 889         "ext2load usb 0:4 $fdtaddr $fdtfile;"                           \
 890         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"                   \
 891         "bootm $loadaddr $ramdiskaddr $fdtaddr\0 "                      \
 892 "boot_nor = "                                                           \
 893         "setenv bootargs root=/dev/$jffs2nor rw "                       \
 894         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 895         "bootm $norbootaddr - $norfdtaddr\0 "                           \
 896 "boot_ram = "                                                           \
 897         "setenv bootargs root=/dev/ram rw "                             \
 898         "console=$consoledev,$baudrate $othbootargs "                   \
 899         "ramdisk_size=$ramdisk_size;"                                   \
 900         "tftp $ramdiskaddr $ramdiskfile;"                               \
 901         "tftp $loadaddr $bootfile;"                                     \
 902         "tftp $fdtaddr $fdtfile;"                                       \
 903         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
 904
 905 #endif
 906 #endif
 907
 908 #endif /* __CONFIG_H */