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   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19
  20 #include <asm/arch/cpu.h>               /* get chip and board defs */
  21 #include <asm/arch/omap.h>
  22
  23 /* Clock Defines */
  24 #define V_OSCK                  26000000        /* Clock output from T2 */
  25 #define V_SCLK                  (V_OSCK >> 1)
  26
  27 #define CONFIG_MISC_INIT_R
  28
  29 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  30 #define CONFIG_SETUP_MEMORY_TAGS        1
  31 #define CONFIG_INITRD_TAG               1
  32 #define CONFIG_REVISION_TAG             1
  33
  34 /*
  35  * Size of malloc() pool
  36  */
  37 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  38 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  39                                                 /* initial data */
  40 /*
  41  * DDR related
  42  */
  43 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  44
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * NS16550 Configuration
  51  */
  52 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  53
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  56 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_CONS_INDEX               3
  62 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  63 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  64
  65 /* allow to overwrite serial and ethaddr */
  66 #define CONFIG_ENV_OVERWRITE
  67 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  68                                         115200}
  69
  70 /*
  71  * USB configuration
  72  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  73  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  74  */
  75 #define CONFIG_USB_AM35X                1
  76 #define CONFIG_USB_MUSB_HCD                     1
  77
  78 #ifdef CONFIG_USB_AM35X
  79
  80 #ifdef CONFIG_USB_MUSB_HCD
  81
  82 #ifdef CONFIG_USB_KEYBOARD
  83 #define CONFIG_PREBOOT "usb start"
  84 #endif /* CONFIG_USB_KEYBOARD */
  85
  86 #endif /* CONFIG_USB_MUSB_HCD */
  87
  88 #ifdef CONFIG_USB_MUSB_UDC
  89 /* USB device configuration */
  90 #define CONFIG_USB_DEVICE               1
  91 #define CONFIG_USB_TTY                  1
  92 /* Change these to suit your needs */
  93 #define CONFIG_USBD_VENDORID            0x0451
  94 #define CONFIG_USBD_PRODUCTID           0x5678
  95 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
  96 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
  97 #endif /* CONFIG_USB_MUSB_UDC */
  98
  99 #endif /* CONFIG_USB_AM35X */
 100
 101 #define CONFIG_SYS_I2C
 102 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 103 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 104
 105 /*
 106  * Board NAND Info.
 107  */
 108 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 109                                                         /* to access nand */
 110 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 111                                                         /* to access */
 112                                                         /* nand at CS0 */
 113
 114 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 115                                                         /* NAND devices */
 116
 117 #define CONFIG_JFFS2_NAND
 118 /* nand device jffs2 lives on */
 119 #define CONFIG_JFFS2_DEV                "nand0"
 120 /* start of jffs2 partition */
 121 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 122 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 123
 124 /* Environment information */
 125
 126 #define CONFIG_BOOTFILE         "uImage"
 127
 128 #define CONFIG_EXTRA_ENV_SETTINGS \
 129         "loadaddr=0x82000000\0" \
 130         "console=ttyS2,115200n8\0" \
 131         "mmcdev=0\0" \
 132         "mmcargs=setenv bootargs console=${console} " \
 133                 "root=/dev/mmcblk0p2 rw " \
 134                 "rootfstype=ext3 rootwait\0" \
 135         "nandargs=setenv bootargs console=${console} " \
 136                 "root=/dev/mtdblock4 rw " \
 137                 "rootfstype=jffs2\0" \
 138         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 139         "bootscript=echo Running bootscript from mmc ...; " \
 140                 "source ${loadaddr}\0" \
 141         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 142         "mmcboot=echo Booting from mmc ...; " \
 143                 "run mmcargs; " \
 144                 "bootm ${loadaddr}\0" \
 145         "nandboot=echo Booting from nand ...; " \
 146                 "run nandargs; " \
 147                 "nand read ${loadaddr} 280000 400000; " \
 148                 "bootm ${loadaddr}\0" \
 149
 150 #define CONFIG_BOOTCOMMAND \
 151         "mmc dev ${mmcdev}; if mmc rescan; then " \
 152                 "if run loadbootscript; then " \
 153                         "run bootscript; " \
 154                 "else " \
 155                         "if run loaduimage; then " \
 156                                 "run mmcboot; " \
 157                         "else run nandboot; " \
 158                         "fi; " \
 159                 "fi; " \
 160         "else run nandboot; fi"
 161
 162 #define CONFIG_AUTO_COMPLETE    1
 163 /*
 164  * Miscellaneous configurable options
 165  */
 166 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 167 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 168 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 169                                                 /* args */
 170 /* memtest works on */
 171 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 172 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 173                                         0x01F00000) /* 31MB */
 174
 175 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 176                                                                 /* address */
 177
 178 /*
 179  * AM3517 has 12 GP timers, they can be driven by the system clock
 180  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 181  * This rate is divided by a local divisor.
 182  */
 183 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 184 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 185
 186 /*-----------------------------------------------------------------------
 187  * Physical Memory Map
 188  */
 189 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 190 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 191 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 192
 193 /*-----------------------------------------------------------------------
 194  * FLASH and environment organization
 195  */
 196
 197 /* **** PISMO SUPPORT *** */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 199                                                 /* on one chip */
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 201 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 202
 203 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 204
 205 /* Monitor at start of flash */
 206 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 207
 208 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 209 #define CONFIG_ENV_OFFSET               0x260000
 210 #define CONFIG_ENV_ADDR                 0x260000
 211
 212 /*-----------------------------------------------------------------------
 213  * CFI FLASH driver setup
 214  */
 215 /* timeout values are in ticks */
 216 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 217 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 218
 219 /* Flash banks JFFS2 should use */
 220 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 221                                         CONFIG_SYS_MAX_NAND_DEVICE)
 222 #define CONFIG_SYS_JFFS2_MEM_NAND
 223 /* use flash_info[2] */
 224 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 225 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 226
 227 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 228 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 229 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 230 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 231                                          CONFIG_SYS_INIT_RAM_SIZE - \
 232                                          GENERATED_GBL_DATA_SIZE)
 233
 234 /* Defines for SPL */
 235 #define CONFIG_SPL_FRAMEWORK
 236 #define CONFIG_SPL_TEXT_BASE            0x40200800
 237 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 238                                          CONFIG_SPL_TEXT_BASE)
 239
 240 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 241 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 242
 243 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 244 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 245
 246 #define CONFIG_SPL_NAND_BASE
 247 #define CONFIG_SPL_NAND_DRIVERS
 248 #define CONFIG_SPL_NAND_ECC
 249
 250 /* NAND boot config */
 251 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 252 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 253 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 254 #define CONFIG_SYS_NAND_OOBSIZE         64
 255 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 256 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 257 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 258                                                 10, 11, 12, 13}
 259 #define CONFIG_SYS_NAND_ECCSIZE         512
 260 #define CONFIG_SYS_NAND_ECCBYTES        3
 261 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 262 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 263 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 264
 265 /*
 266  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 267  * 64 bytes before this address should be set aside for u-boot.img's
 268  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 269  * other needs.
 270  */
 271 #define CONFIG_SYS_TEXT_BASE            0x80100000
 272 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 273 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 274
 275 #endif /* __CONFIG_H */