git.sur5r.net Git - u-boot/blob - include/configs/at91sam9m10g45ek.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  15
  16 /* ARM asynchronous clock */
  17 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  18 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  19
  20 #define CONFIG_AT91SAM9M10G45EK
  21
  22 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs      */
  23 #define CONFIG_SETUP_MEMORY_TAGS
  24 #define CONFIG_INITRD_TAG
  25 #define CONFIG_SKIP_LOWLEVEL_INIT
  26
  27 /* general purpose I/O */
  28 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  29
  30 /* LCD */
  31 #define LCD_BPP                         LCD_COLOR8
  32 #define CONFIG_LCD_LOGO
  33 #undef LCD_TEST_PATTERN
  34 #define CONFIG_LCD_INFO
  35 #define CONFIG_LCD_INFO_BELOW_LOGO
  36 #define CONFIG_ATMEL_LCD
  37 #define CONFIG_ATMEL_LCD_RGB565
  38 /* board specific(not enough SRAM) */
  39 #define CONFIG_AT91SAM9G45_LCD_BASE             0x73E00000
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #define CONFIG_BOOTP_BOOTFILESIZE
  45 #define CONFIG_BOOTP_BOOTPATH
  46 #define CONFIG_BOOTP_GATEWAY
  47 #define CONFIG_BOOTP_HOSTNAME
  48
  49 /* SDRAM */
  50 #define CONFIG_NR_DRAM_BANKS            1
  51 #define CONFIG_SYS_SDRAM_BASE           0x70000000
  52 #define CONFIG_SYS_SDRAM_SIZE           0x08000000
  53
  54 #define CONFIG_SYS_INIT_SP_ADDR \
  55         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  56
  57 /* NAND flash */
  58 #ifdef CONFIG_CMD_NAND
  59 #define CONFIG_NAND_ATMEL
  60 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  61 #define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
  62 #define CONFIG_SYS_NAND_DBW_8
  63 /* our ALE is AD21 */
  64 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
  65 /* our CLE is AD22 */
  66 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
  67 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
  68 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PC8
  69
  70 #endif
  71
  72 /* Ethernet */
  73 #define CONFIG_RESET_PHY_R
  74 #define CONFIG_AT91_WANTS_COMMON_PHY
  75
  76 #define CONFIG_SYS_LOAD_ADDR            0x22000000      /* load address */
  77
  78 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  79 #define CONFIG_SYS_MEMTEST_END          0x23e00000
  80
  81 #ifdef CONFIG_NAND_BOOT
  82 /* bootstrap + u-boot + env in nandflash */
  83 #define CONFIG_ENV_OFFSET               0x120000
  84 #define CONFIG_ENV_OFFSET_REDUND        0x100000
  85 #define CONFIG_ENV_SIZE                 0x20000
  86
  87 #define CONFIG_BOOTCOMMAND                                              \
  88         "nand read 0x70000000 0x200000 0x300000;"                       \
  89         "bootm 0x70000000"
  90 #elif CONFIG_SD_BOOT
  91 /* bootstrap + u-boot + env + linux in mmc */
  92 #define CONFIG_ENV_SIZE         0x4000
  93
  94 #define CONFIG_BOOTCOMMAND      "fatload mmc 0:1 0x71000000 dtb; " \
  95                                 "fatload mmc 0:1 0x72000000 zImage; " \
  96                                 "bootz 0x72000000 - 0x71000000"
  97 #endif
  98
  99 #define CONFIG_SYS_LONGHELP
 100 #define CONFIG_CMDLINE_EDITING
 101 #define CONFIG_AUTO_COMPLETE
 102
 103 /*
 104  * Size of malloc() pool
 105  */
 106 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 107
 108 /* Defines for SPL */
 109 #define CONFIG_SPL_FRAMEWORK
 110 #define CONFIG_SPL_TEXT_BASE            0x300000
 111 #define CONFIG_SPL_MAX_SIZE             0x010000
 112 #define CONFIG_SPL_STACK                0x310000
 113
 114 #define CONFIG_SYS_MONITOR_LEN          0x80000
 115
 116 #ifdef CONFIG_SD_BOOT
 117
 118 #define CONFIG_SPL_BSS_START_ADDR       0x70000000
 119 #define CONFIG_SPL_BSS_MAX_SIZE         0x00080000
 120 #define CONFIG_SYS_SPL_MALLOC_START     0x70080000
 121 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00080000
 122
 123 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 124 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 125
 126 #elif CONFIG_NAND_BOOT
 127 #define CONFIG_SPL_NAND_DRIVERS
 128 #define CONFIG_SPL_NAND_BASE
 129 #define CONFIG_SPL_NAND_ECC
 130 #define CONFIG_SPL_NAND_SOFTECC
 131 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 132 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x80000
 133 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 134
 135 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 136 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 137 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 138 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 139 #define CONFIG_SYS_NAND_ECCSIZE         256
 140 #define CONFIG_SYS_NAND_ECCBYTES        3
 141 #define CONFIG_SYS_NAND_OOBSIZE         64
 142 #define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
 143                                           48, 49, 50, 51, 52, 53, 54, 55, \
 144                                           56, 57, 58, 59, 60, 61, 62, 63, }
 145 #endif
 146
 147 #define CONFIG_SPL_ATMEL_SIZE
 148 #define CONFIG_SYS_MASTER_CLOCK         132096000
 149 #define CONFIG_SYS_AT91_PLLA            0x20c73f03
 150 #define CONFIG_SYS_MCKR                 0x1301
 151 #define CONFIG_SYS_MCKR_CSS             0x1302
 152
 153 #endif