git.sur5r.net Git - u-boot/blob - include/configs/calimain.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011-2014 OMICRON electronics GmbH
   4  *
   5  * Based on da850evm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   8  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Board
  16  */
  17 #define CONFIG_DRIVER_TI_EMAC
  18 #define CONFIG_MACH_TYPE        MACH_TYPE_CALIMAIN
  19
  20 /*
  21  * SoC Configuration
  22  */
  23 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  24 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  25 #define CONFIG_SYS_OSCIN_FREQ           calimain_get_osc_freq()
  26 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  27 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  28 #define CONFIG_ARCH_CPU_INIT
  29 #define CONFIG_DA8XX_GPIO
  30 #define CONFIG_HW_WATCHDOG
  31 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
  32 #define CONFIG_SYS_WDT_PERIOD_LOW \
  33         (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
  34 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
  35 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  36
  37 /*
  38  * PLL configuration
  39  */
  40
  41 #define CONFIG_SYS_DA850_PLL0_PLLM \
  42         ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
  43 #define CONFIG_SYS_DA850_PLL1_PLLM \
  44         ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
  45
  46 /*
  47  * DDR2 memory configuration
  48  */
  49 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  50                                         DV_DDR_PHY_EXT_STRBEN | \
  51                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  52
  53 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  54         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
  55         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
  56         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  57         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  58         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  59         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  60         (0x3 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  61         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  62
  63 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  64 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0
  65
  66 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  67         (16 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  68         (1 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  69         (1 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  70         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  71         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  72         (7 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  73         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  74         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  75
  76 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  77         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  78         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  79         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  80         (18 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  81         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  82         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  83         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  84
  85 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x000003FF
  86 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
  87
  88 /*
  89  * Flash memory timing
  90  */
  91
  92 #define CONFIG_SYS_DA850_CS2CFG (       \
  93         DAVINCI_ABCR_WSETUP(2) |        \
  94         DAVINCI_ABCR_WSTROBE(5) |       \
  95         DAVINCI_ABCR_WHOLD(3) |         \
  96         DAVINCI_ABCR_RSETUP(1) |        \
  97         DAVINCI_ABCR_RSTROBE(14) |      \
  98         DAVINCI_ABCR_RHOLD(0) |         \
  99         DAVINCI_ABCR_TA(3) |            \
 100         DAVINCI_ABCR_ASIZE_16BIT)
 101
 102 /* single 64 MB NOR flash device connected to CS2 and CS3 */
 103 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
 104
 105 /*
 106  * Memory Info
 107  */
 108 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
 109 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 110 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
 111 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 112
 113 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
 114         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
 115         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
 116         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
 117         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
 118         DAVINCI_SYSCFG_SUSPSRC_I2C)
 119
 120 /* memtest start addr */
 121 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
 122
 123 /* memtest will be run on 16MB */
 124 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (16 << 20))
 125
 126 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
 127
 128 /*
 129  * Serial Driver info
 130  */
 131 #define CONFIG_SYS_NS16550_SERIAL
 132 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 133 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 134 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 135
 136 #define CONFIG_FLASH_CFI_DRIVER
 137 #define CONFIG_SYS_FLASH_CFI
 138 #define CONFIG_SYS_FLASH_PROTECTION
 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 140 #define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
 141 #define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
 142 #define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 143 #define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
 144 #define CONFIG_ENV_ADDR \
 145         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
 146 #define CONFIG_ENV_SIZE             (128 << 10)
 147 #define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 148 #define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
 149 #define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
 150 #define CONFIG_SYS_MAX_FLASH_SECT \
 151         ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
 152
 153 /*
 154  * Network & Ethernet Configuration
 155  */
 156 #ifdef CONFIG_DRIVER_TI_EMAC
 157 #define CONFIG_MII
 158 #define CONFIG_BOOTP_DNS2
 159 #define CONFIG_BOOTP_SEND_HOSTNAME
 160 #define CONFIG_NET_RETRY_COUNT  10
 161 #endif
 162
 163 /*
 164  * U-Boot general configuration
 165  */
 166 #define CONFIG_BOOTFILE        "uImage" /* Boot file name */
 167 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size  */
 168 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 169 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
 170 #define CONFIG_LOADADDR        0xc0700000
 171 #define CONFIG_MX_CYCLIC
 172
 173 /*
 174  * Linux Information
 175  */
 176 #define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
 177 #define CONFIG_CMDLINE_TAG
 178 #define CONFIG_REVISION_TAG
 179 #define CONFIG_SETUP_MEMORY_TAGS
 180 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
 181 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 182 #define CONFIG_RESET_TO_RETRY
 183
 184 /*
 185  * Default environment settings
 186  * gpio0 = button, gpio1 = led green, gpio2 = led red
 187  * verify = n ... disable kernel checksum verification for faster booting
 188  */
 189 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 190         "tftpdir=calimero\0"                                            \
 191         "flashkernel=tftpboot $loadaddr $tftpdir/uImage; "              \
 192                 "erase 0x60800000 +0x400000; "                          \
 193                 "cp.b $loadaddr 0x60800000 $filesize\0"                 \
 194         "flashrootfs="                                                  \
 195                 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; "            \
 196                 "erase 0x60c00000 +0x2e00000; "                         \
 197                 "cp.b $loadaddr 0x60c00000 $filesize\0"                 \
 198         "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "           \
 199                 "protect off all; "                                     \
 200                 "erase 0x60000000 +0x80000; "                           \
 201                 "cp.b $loadaddr 0x60000000 $filesize\0"                 \
 202         "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "             \
 203                 "erase 0x60080000 +0x780000; "                          \
 204                 "cp.b $loadaddr 0x60080000 $filesize\0"                 \
 205         "erase_persistent=erase 0x63a00000 +0x600000;\0"                \
 206         "bootnor=setenv bootargs console=ttyS2,115200n8 "               \
 207                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 208                 "rootwait ethaddr=$ethaddr; "                           \
 209                 "gpio c 1; gpio s 2; bootm 0x60800000\0"                \
 210         "bootrlk=gpio s 1; gpio s 2;"                                   \
 211                 "setenv bootargs console=ttyS2,115200n8 "               \
 212                 "ethaddr=$ethaddr; bootm 0x60080000\0"                  \
 213         "boottftp=setenv bootargs console=ttyS2,115200n8 "              \
 214                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 215                 "rootwait ethaddr=$ethaddr; "                           \
 216                 "tftpboot $loadaddr $tftpdir/uImage;"                   \
 217                 "gpio c 1; gpio s 2; bootm $loadaddr\0"                 \
 218         "checkupdate=if test -n $update_flag; then "                    \
 219                 "echo Previous update failed - starting RLK; "          \
 220                 "run bootrlk; fi; "                                     \
 221                 "if test -n $initial_setup; then "                      \
 222                 "echo Running initial setup procedure; "                \
 223                 "sleep 1; run flashall; fi\0"                           \
 224         "product=accessory\0"                                           \
 225         "serial=XX12345\0"                                              \
 226         "checknor="                                                     \
 227                 "if gpio i 0; then run bootnor; fi;\0"                  \
 228         "checkrlk="                                                     \
 229                 "if gpio i 0; then run bootrlk; fi;\0"                  \
 230         "checkbutton="                                                  \
 231                 "run checknor; sleep 1;"                                \
 232                 "run checknor; sleep 1;"                                \
 233                 "run checknor; sleep 1;"                                \
 234                 "run checknor; sleep 1;"                                \
 235                 "run checknor;"                                         \
 236                 "gpio s 1; gpio s 2;"                                   \
 237                 "echo ---- Release button to boot RLK ----;"            \
 238                 "run checkrlk; sleep 1;"                                \
 239                 "run checkrlk; sleep 1;"                                \
 240                 "run checkrlk; sleep 1;"                                \
 241                 "run checkrlk; sleep 1;"                                \
 242                 "run checkrlk; sleep 1;"                                \
 243                 "run checkrlk;"                                         \
 244                 "echo ---- Factory reset requested ----;"               \
 245                 "gpio c 1;"                                             \
 246                 "setenv factory_reset true;"                            \
 247                 "saveenv;"                                              \
 248                 "run bootnor;\0"                                        \
 249         "flashall=run flashrlk;"                                        \
 250                 "run flashkernel;"                                      \
 251                 "run flashrootfs;"                                      \
 252                 "setenv erase_datafs true;"                             \
 253                 "setenv initial_setup;"                                 \
 254                 "saveenv;"                                              \
 255                 "run bootnor;\0"                                        \
 256         "verify=n\0"                                                    \
 257         "clearenv=protect off all;"                                     \
 258                 "erase 0x60040000 +0x40000;\0"                          \
 259         "bootlimit=3\0"                                                 \
 260         "altbootcmd=run bootrlk\0"
 261
 262 #define CONFIG_PREBOOT                  \
 263         "echo Version: $ver; "          \
 264         "echo Serial: $serial; "        \
 265         "echo MAC: $ethaddr; "          \
 266         "echo Product: $product; "      \
 267         "gpio c 1; gpio c 2;"
 268
 269 /* additions for new relocation code, must added to all boards */
 270 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 271 /* initial stack pointer in internal SRAM */
 272 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
 273
 274 #define CONFIG_SYS_BOOTCOUNT_LE         /* Use little-endian accessors */
 275
 276 #ifndef __ASSEMBLY__
 277 int calimain_get_osc_freq(void);
 278 #endif
 279
 280 #include <asm/arch/hardware.h>
 281
 282 #endif /* __CONFIG_H */