git.sur5r.net Git - u-boot/blob - include/configs/controlcenterd.h

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  * based on P1022DS.h
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #ifdef CONFIG_SDCARD
  30 #define CONFIG_RAMBOOT_SDCARD
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #define CONFIG_RAMBOOT_SPIFLASH
  35 #endif
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_CONTROLCENTERD
  39 #define CONFIG_MP                       /* support multiple processors */
  40
  41 #define CONFIG_ENABLE_36BIT_PHYS
  42
  43 #ifdef CONFIG_PHYS_64BIT
  44 #define CONFIG_ADDR_MAP
  45 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  46 #endif
  47
  48 #define CONFIG_L2_CACHE
  49 #define CONFIG_BTB
  50
  51 #define CONFIG_SYS_CLK_FREQ     66666600
  52 #define CONFIG_DDR_CLK_FREQ     66666600
  53
  54 #define CONFIG_SYS_RAMBOOT
  55
  56 #ifdef CONFIG_TRAILBLAZER
  57
  58 #define CONFIG_SYS_TEXT_BASE            0xf8fc0000
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  60 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
  61
  62 /*
  63  * Config the L2 Cache
  64  */
  65 #define CONFIG_SYS_INIT_L2_ADDR         0xf8fc0000
  66 #ifdef CONFIG_PHYS_64BIT
  67 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8fc0000ull
  68 #else
  69 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  70 #endif
  71 #define CONFIG_SYS_L2_SIZE              (256 << 10)
  72 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  73
  74 #else /* CONFIG_TRAILBLAZER */
  75
  76 #define CONFIG_SYS_TEXT_BASE            0x11000000
  77 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  78 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  79
  80 #endif /* CONFIG_TRAILBLAZER */
  81
  82 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  83 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
  84
  85 /*
  86  * Memory map
  87  *
  88  * 0x0000_0000  0x3fff_ffff     DDR                     1G Cacheable
  89  * 0xc000_0000  0xdfff_ffff     PCI Express Mem         512M non-cacheable
  90  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
  91  *
  92  * Localbus non-cacheable
  93  * 0xe000_0000  0xe00f_ffff     eLBC                    1M non-cacheable
  94  * 0xf8fc0000   0xf8ff_ffff     L2 SRAM                 256k Cacheable
  95  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
  96  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
  97  */
  98
  99 #define CONFIG_SYS_INIT_RAM_LOCK
 100 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 101 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* used area in RAM */
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 103         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 104 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 105
 106 #ifdef CONFIG_TRAILBLAZER
 107 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
 108 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_CCSRBAR_DEFAULT
 109 #else
 110 #define CONFIG_SYS_CCSRBAR              0xffe00000
 111 #endif
 112 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 113 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR   (CONFIG_SYS_CCSRBAR+0xf200)
 114
 115 /*
 116  * DDR Setup
 117  */
 118
 119 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 120 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 121 #define CONFIG_SYS_SDRAM_SIZE 1024
 122 #define CONFIG_VERY_BIG_RAM
 123
 124 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 125 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 126
 127 #define CONFIG_SYS_MEMTEST_START        0x00000000
 128 #define CONFIG_SYS_MEMTEST_END          0x3fffffff
 129
 130 #ifdef CONFIG_TRAILBLAZER
 131 #define CONFIG_SPD_EEPROM
 132 #define SPD_EEPROM_ADDRESS 0x52
 133 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
 134 #endif
 135
 136 /*
 137  * Local Bus Definitions
 138  */
 139
 140 #define CONFIG_SYS_ELBC_BASE            0xe0000000
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_SYS_ELBC_BASE_PHYS       0xfe0000000ull
 143 #else
 144 #define CONFIG_SYS_ELBC_BASE_PHYS       CONFIG_SYS_ELBC_BASE
 145 #endif
 146
 147 #define CONFIG_UART_BR_PRELIM  \
 148         (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
 149 #define CONFIG_UART_OR_PRELIM   (OR_AM_32KB | 0xff7)
 150
 151 #define CONFIG_SYS_BR0_PRELIM   0 /* CS0 was originally intended for FPGA */
 152 #define CONFIG_SYS_OR0_PRELIM   0 /* debugging, was never used */
 153
 154 #define CONFIG_SYS_BR1_PRELIM   CONFIG_UART_BR_PRELIM
 155 #define CONFIG_SYS_OR1_PRELIM   CONFIG_UART_OR_PRELIM
 156
 157 /*
 158  * Serial Port
 159  */
 160 #define CONFIG_CONS_INDEX               2
 161 #define CONFIG_SYS_NS16550_SERIAL
 162 #define CONFIG_SYS_NS16550_REG_SIZE     1
 163 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 164
 165 #define CONFIG_SYS_BAUDRATE_TABLE       \
 166         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 167
 168 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 169 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 170
 171 /*
 172  * I2C
 173  */
 174 #define CONFIG_SYS_I2C
 175 #define CONFIG_SYS_I2C_FSL
 176 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 177 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 178 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 179 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 180 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 181 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 182
 183 #ifndef CONFIG_TRAILBLAZER
 184 #endif
 185
 186 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 187
 188 #define CONFIG_CMD_EEPROM
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
 190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 191
 192 #ifndef CONFIG_TRAILBLAZER
 193 /*
 194  * eSPI - Enhanced SPI
 195  */
 196 #define CONFIG_HARD_SPI
 197
 198 #define CONFIG_SF_DEFAULT_SPEED         10000000
 199 #define CONFIG_SF_DEFAULT_MODE          0
 200 #endif
 201
 202 #define CONFIG_SHA1
 203
 204 /*
 205  * MMC
 206  */
 207 #define CONFIG_FSL_ESDHC
 208 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 209
 210 #ifndef CONFIG_TRAILBLAZER
 211
 212 /*
 213  * Video
 214  */
 215 #define CONFIG_FSL_DIU_FB
 216 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 217
 218 /*
 219  * General PCI
 220  * Memory space is mapped 1-1, but I/O space must start from 0.
 221  */
 222 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 223 #define CONFIG_PCI_INDIRECT_BRIDGE
 224 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 225 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 226 #define CONFIG_CMD_PCI
 227
 228 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 229 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 230
 231 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 232 #ifdef CONFIG_PHYS_64BIT
 233 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 234 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 235 #else
 236 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 237 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 238 #endif
 239 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 240 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 241 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 242 #ifdef CONFIG_PHYS_64BIT
 243 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 244 #else
 245 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 246 #endif
 247 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 248
 249 /*
 250  * SATA
 251  */
 252 #define CONFIG_LIBATA
 253 #define CONFIG_LBA48
 254 #define CONFIG_CMD_SATA
 255
 256 #define CONFIG_FSL_SATA
 257 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 258 #define CONFIG_SATA1
 259 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 260 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 261 #define CONFIG_SATA2
 262 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 263 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 264
 265 /*
 266  * Ethernet
 267  */
 268 #define CONFIG_TSEC_ENET
 269
 270 #define CONFIG_TSECV2
 271
 272 #define CONFIG_MII                      /* MII PHY management */
 273 #define CONFIG_TSEC1            1
 274 #define CONFIG_TSEC1_NAME       "eTSEC1"
 275 #define CONFIG_TSEC2            1
 276 #define CONFIG_TSEC2_NAME       "eTSEC2"
 277
 278 #define TSEC1_PHY_ADDR          0
 279 #define TSEC2_PHY_ADDR          1
 280
 281 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 282 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 283
 284 #define TSEC1_PHYIDX            0
 285 #define TSEC2_PHYIDX            0
 286
 287 #define CONFIG_ETHPRIME         "eTSEC1"
 288
 289 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 290
 291 /*
 292  * USB
 293  */
 294
 295 #define CONFIG_HAS_FSL_DR_USB
 296 #define CONFIG_USB_EHCI_FSL
 297 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 298
 299 #endif /* CONFIG_TRAILBLAZER */
 300
 301 /*
 302  * Environment
 303  */
 304 #if defined(CONFIG_TRAILBLAZER)
 305 #define CONFIG_ENV_IS_NOWHERE
 306 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 307 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 308 #define CONFIG_ENV_IS_IN_SPI_FLASH
 309 #define CONFIG_ENV_SPI_BUS      0
 310 #define CONFIG_ENV_SPI_CS       0
 311 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 312 #define CONFIG_ENV_SPI_MODE     0
 313 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 314 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 315 #define CONFIG_ENV_SECT_SIZE    0x10000
 316 #elif defined(CONFIG_RAMBOOT_SDCARD)
 317 #define CONFIG_ENV_IS_IN_MMC
 318 #define CONFIG_FSL_FIXED_MMC_LOCATION
 319 #define CONFIG_ENV_SIZE         0x2000
 320 #define CONFIG_SYS_MMC_ENV_DEV  0
 321 #endif
 322
 323 #define CONFIG_SYS_EXTRA_ENV_RELOC
 324
 325 /*
 326  * Command line configuration.
 327  */
 328 #ifndef CONFIG_TRAILBLAZER
 329 #define CONFIG_SYS_LONGHELP
 330 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 331 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 332 #endif /* CONFIG_TRAILBLAZER */
 333
 334 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 335 #ifdef CONFIG_CMD_KGDB
 336 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 337 #else
 338 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 339 #endif
 340 /* Print Buffer Size */
 341 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 342 #define CONFIG_SYS_MAXARGS      16
 343 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 344
 345 #ifndef CONFIG_TRAILBLAZER
 346
 347 #define CONFIG_CMD_ERRATA
 348 #define CONFIG_CMD_IRQ
 349 #define CONFIG_CMD_REGINFO
 350
 351 /*
 352  * Board initialisation callbacks
 353  */
 354 #define CONFIG_BOARD_EARLY_INIT_R
 355 #define CONFIG_MISC_INIT_R
 356 #define CONFIG_LAST_STAGE_INIT
 357
 358 #else /* CONFIG_TRAILBLAZER */
 359
 360 #define CONFIG_BOARD_EARLY_INIT_R
 361 #define CONFIG_LAST_STAGE_INIT
 362
 363 #endif /* CONFIG_TRAILBLAZER */
 364
 365 /*
 366  * Miscellaneous configurable options
 367  */
 368 #define CONFIG_HW_WATCHDOG
 369 #define CONFIG_LOADS_ECHO
 370 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 371
 372 /*
 373  * For booting Linux, the board info and command line data
 374  * have to be in the first 64 MB of memory, since this is
 375  * the maximum mapped by the Linux kernel during initialization.
 376  */
 377 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Linux Memory map */
 378 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 379
 380 /*
 381  * Environment Configuration
 382  */
 383
 384 #ifdef CONFIG_TRAILBLAZER
 385 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 386         "mp_holdoff=1\0"
 387
 388 #else
 389
 390 #define CONFIG_HOSTNAME         controlcenterd
 391 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 392 #define CONFIG_BOOTFILE         "uImage"
 393 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP */
 394
 395 #define CONFIG_LOADADDR         1000000
 396
 397 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 398         "netdev=eth0\0"                                         \
 399         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 400         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 401         "tftpflash=tftpboot $loadaddr $uboot && "               \
 402                 "protect off $ubootaddr +$filesize && "         \
 403                 "erase $ubootaddr +$filesize && "               \
 404                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 405                 "protect on $ubootaddr +$filesize && "          \
 406                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 407         "consoledev=ttyS1\0"                                    \
 408         "ramdiskaddr=2000000\0"                                 \
 409         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 410         "fdtaddr=1e00000\0"                                     \
 411         "fdtfile=controlcenterd.dtb\0"                          \
 412         "bdev=sda3\0"
 413
 414 /* these are used and NUL-terminated in env_default.h */
 415 #define CONFIG_NFSBOOTCOMMAND                                           \
 416         "setenv bootargs root=/dev/nfs rw "                             \
 417         "nfsroot=$serverip:$rootpath "                                  \
 418         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 419         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 420         "tftp $loadaddr $bootfile;"                                     \
 421         "tftp $fdtaddr $fdtfile;"                                       \
 422         "bootm $loadaddr - $fdtaddr"
 423
 424 #define CONFIG_RAMBOOTCOMMAND                                           \
 425         "setenv bootargs root=/dev/ram rw "                             \
 426         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 427         "tftp $ramdiskaddr $ramdiskfile;"                               \
 428         "tftp $loadaddr $bootfile;"                                     \
 429         "tftp $fdtaddr $fdtfile;"                                       \
 430         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 431
 432 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 433
 434 #endif /* CONFIG_TRAILBLAZER */
 435
 436 #endif