git.sur5r.net Git - u-boot/blob - include/configs/ge_bx50v3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015 Timesys Corporation
   4  * Copyright (C) 2015 General Electric Company
   5  * Copyright (C) 2014 Advantech
   6  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   7  *
   8  * Configuration settings for the GE MX6Q Bx50v3 boards.
   9  */
  10
  11 #ifndef __GE_BX50V3_CONFIG_H
  12 #define __GE_BX50V3_CONFIG_H
  13
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/mach-imx/gpio.h>
  16
  17 #define CONFIG_BOARD_NAME       "General Electric Bx50v3"
  18
  19 #define CONFIG_MXC_UART_BASE    UART3_BASE
  20 #define CONSOLE_DEV     "ttymxc2"
  21
  22 #define CONFIG_SUPPORT_EMMC_BOOT
  23
  24
  25 #include "mx6_common.h"
  26 #include <linux/sizes.h>
  27
  28 #define CONFIG_CMDLINE_TAG
  29 #define CONFIG_SETUP_MEMORY_TAGS
  30 #define CONFIG_INITRD_TAG
  31 #define CONFIG_REVISION_TAG
  32 #define CONFIG_SYS_MALLOC_LEN           (10 * SZ_1M)
  33
  34 #define CONFIG_HW_WATCHDOG
  35 #define CONFIG_IMX_WATCHDOG
  36 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
  37
  38 #define CONFIG_MXC_UART
  39
  40 #define CONFIG_MXC_OCOTP
  41
  42 /* SATA Configs */
  43 #ifdef CONFIG_CMD_SATA
  44 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  45 #define CONFIG_DWC_AHSATA_PORT_ID       0
  46 #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
  47 #define CONFIG_LBA48
  48 #endif
  49
  50 /* MMC Configs */
  51 #define CONFIG_FSL_USDHC
  52 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
  53 #define CONFIG_BOUNCE_BUFFER
  54
  55 /* USB Configs */
  56 #ifdef CONFIG_USB
  57 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  58 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  59 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
  60 #define CONFIG_MXC_USB_FLAGS    0
  61
  62 #define CONFIG_USBD_HS
  63 #define CONFIG_USB_GADGET_MASS_STORAGE
  64 #endif
  65
  66 /* Networking Configs */
  67 #ifdef CONFIG_NET
  68 #define CONFIG_FEC_MXC
  69 #define CONFIG_MII
  70 #define IMX_FEC_BASE                    ENET_BASE_ADDR
  71 #define CONFIG_FEC_XCV_TYPE             RGMII
  72 #define CONFIG_ETHPRIME         "FEC"
  73 #define CONFIG_FEC_MXC_PHYADDR          4
  74 #define CONFIG_PHY_ATHEROS
  75 #endif
  76
  77 /* Serial Flash */
  78 #ifdef CONFIG_CMD_SF
  79 #define CONFIG_SF_DEFAULT_BUS           0
  80 #define CONFIG_SF_DEFAULT_CS            0
  81 #define CONFIG_SF_DEFAULT_SPEED 20000000
  82 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
  83 #endif
  84
  85 /* allow to overwrite serial and ethaddr */
  86 #define CONFIG_ENV_OVERWRITE
  87
  88 #define CONFIG_LOADADDR 0x12000000
  89
  90 #define CONFIG_EXTRA_ENV_SETTINGS \
  91         "bootcause=POR\0" \
  92         "bootlimit=10\0" \
  93         "image=/boot/fitImage\0" \
  94         "fdt_high=0xffffffff\0" \
  95         "dev=mmc\0" \
  96         "devnum=1\0" \
  97         "rootdev=mmcblk0p\0" \
  98         "quiet=quiet loglevel=0\0" \
  99         "console=" CONSOLE_DEV "\0" \
 100         "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
 101                 "ro rootwait cma=128M " \
 102                 "bootcause=${bootcause} " \
 103                 "${quiet} console=${console} ${rtc_status} " \
 104                 "${videoargs}" "\0" \
 105         "doquiet=" \
 106                 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
 107                         "then setenv quiet; fi\0" \
 108         "hasfirstboot=" \
 109                 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
 110                 "/boot/bootcause/firstboot\0" \
 111         "swappartitions=" \
 112                 "setexpr partnum 3 - ${partnum}\0" \
 113         "failbootcmd=" \
 114                 "bx50_backlight_enable; " \
 115                 "msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
 116                 "echo $msg; " \
 117                 "setenv stdout vga; " \
 118                 "echo \"\n\n\n\n    \" $msg; " \
 119                 "setenv stdout serial; " \
 120                 "mw.b 0x7000A000 0xbc; " \
 121                 "mw.b 0x7000A001 0x00; " \
 122                 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
 123         "altbootcmd=" \
 124                 "run doquiet; " \
 125                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 126                 "run hasfirstboot || setenv partnum 0; " \
 127                 "if test ${partnum} != 0; then " \
 128                         "setenv bootcause REVERT; " \
 129                         "run swappartitions loadimage doboot; " \
 130                 "fi; " \
 131                 "run failbootcmd\0" \
 132         "loadimage=" \
 133                 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 134         "doboot=" \
 135                 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
 136                 "run setargs; " \
 137                 "bootm ${loadaddr}#conf@${confidx}\0" \
 138         "tryboot=" \
 139                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 140                 "run loadimage || run swappartitions && run loadimage || " \
 141                 "setenv partnum 0 && echo MISSING IMAGE;" \
 142                 "run doboot; " \
 143                 "run failbootcmd\0" \
 144
 145 #define CONFIG_MMCBOOTCOMMAND \
 146         "if mmc dev ${devnum}; then " \
 147                 "run doquiet; " \
 148                 "run tryboot; " \
 149         "fi; " \
 150
 151 #define CONFIG_USBBOOTCOMMAND \
 152         "echo Unsupported; " \
 153
 154 #ifdef CONFIG_CMD_USB
 155 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
 156 #else
 157 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
 158 #endif
 159
 160 #define CONFIG_ARP_TIMEOUT     200UL
 161
 162 /* Miscellaneous configurable options */
 163
 164 #define CONFIG_SYS_MEMTEST_START       0x10000000
 165 #define CONFIG_SYS_MEMTEST_END         0x10010000
 166 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 167
 168 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 169
 170 /* Physical Memory Map */
 171 #define CONFIG_NR_DRAM_BANKS           1
 172 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 173
 174 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 175 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
 176 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 177
 178 #define CONFIG_SYS_INIT_SP_OFFSET \
 179         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 180 #define CONFIG_SYS_INIT_SP_ADDR \
 181         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 182
 183 /* environment organization */
 184 #define CONFIG_ENV_SIZE         (8 * 1024)
 185 #define CONFIG_ENV_OFFSET               (768 * 1024)
 186 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 187 #define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
 188 #define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
 189 #define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
 190 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 191
 192 #ifndef CONFIG_SYS_DCACHE_OFF
 193 #endif
 194
 195 #define CONFIG_SYS_FSL_USDHC_NUM        3
 196
 197 /* Framebuffer */
 198 #define CONFIG_VIDEO
 199 #ifdef CONFIG_VIDEO
 200 #define CONFIG_VIDEO_IPUV3
 201 #define CONFIG_CFB_CONSOLE
 202 #define CONFIG_VGA_AS_SINGLE_DEVICE
 203 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
 204 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
 205 #define CONFIG_HIDE_LOGO_VERSION
 206 #define CONFIG_IMX_HDMI
 207 #define CONFIG_IMX_VIDEO_SKIP
 208 #define CONFIG_CMD_BMP
 209 #endif
 210
 211 #define CONFIG_PWM_IMX
 212 #define CONFIG_IMX6_PWM_PER_CLK 66000000
 213
 214 #define CONFIG_PCI
 215 #define CONFIG_PCI_PNP
 216 #define CONFIG_PCI_SCAN_SHOW
 217 #define CONFIG_PCIE_IMX
 218 #define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
 219 #define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
 220
 221 #define CONFIG_RTC_RX8010SJ
 222 #define CONFIG_SYS_RTC_BUS_NUM 2
 223 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 224
 225 /* I2C Configs */
 226 #define CONFIG_SYS_I2C
 227 #define CONFIG_SYS_I2C_MXC
 228 #define CONFIG_SYS_I2C_SPEED              100000
 229 #define CONFIG_SYS_I2C_MXC_I2C1
 230 #define CONFIG_SYS_I2C_MXC_I2C2
 231 #define CONFIG_SYS_I2C_MXC_I2C3
 232
 233 #define CONFIG_SYS_NUM_I2C_BUSES        11
 234 #define CONFIG_SYS_I2C_MAX_HOPS         1
 235 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 236                                         {1, {I2C_NULL_HOP} }, \
 237                                         {2, {I2C_NULL_HOP} }, \
 238                                         {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
 239                                         {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 240                                         {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 241                                         {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
 242                                         {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
 243                                         {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
 244                                         {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
 245                                         {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
 246                                 }
 247
 248 #define CONFIG_BCH
 249
 250 #endif  /* __GE_BX50V3_CONFIG_H */