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Convert CONFIG_SPL_GPIO_SUPPORT to Kconfig
[u-boot] / include / configs / ipam390.h
1 /*
2  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
3  * Based on:
4  * U-Boot:include/configs/da850evm.h
5  *
6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * Based on davinci_dvevm.h. Original Copyrights follow:
9  *
10  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11  *
12  * SPDX-License-Identifier:     GPL-2.0+
13  */
14
15 #ifndef __CONFIG_H
16 #define __CONFIG_H
17
18 /*
19  * Board
20  */
21 #define CONFIG_DRIVER_TI_EMAC
22 #define CONFIG_BARIX_IPAM390
23
24 /*
25  * SoC Configuration
26  */
27 #define CONFIG_MACH_DAVINCI_DA850_EVM
28 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
29 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
31 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
32 #define CONFIG_SYS_OSCIN_FREQ           24000000
33 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
34 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
35 #define CONFIG_SYS_DA850_PLL_INIT
36 #define CONFIG_SYS_DA850_DDR_INIT
37 #define CONFIG_SYS_TEXT_BASE            0xc1080000
38
39 /*
40  * Memory Info
41  */
42 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
43 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
44 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
45 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
46
47 /* memtest start addr */
48 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
49
50 /* memtest will be run on 16MB */
51 #define CONFIG_SYS_MEMTEST_END  (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
52
53 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
54
55 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
56         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
57         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
58         DAVINCI_SYSCFG_SUSPSRC_UART0 |          \
59         DAVINCI_SYSCFG_SUSPSRC_EMAC)
60
61 /*
62  * PLL configuration
63  */
64 #define CONFIG_SYS_DV_CLKMODE          0
65 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
66 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
67 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
68 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
69 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
70 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
71 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
72 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
73
74 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
75 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
76 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
77 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
78
79 #define CONFIG_SYS_DA850_PLL0_PLLM     24
80 #define CONFIG_SYS_DA850_PLL1_PLLM     24
81
82 /*
83  * DDR2 memory configuration
84  */
85 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
86                                         DV_DDR_PHY_EXT_STRBEN | \
87                                         (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
88 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x00000498
89
90 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0x00000004
91 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x00000020
92
93 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
94         (13 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
95         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
96         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
97         (2 << DV_DDR_SDTMR1_WR_SHIFT) |         \
98         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
99         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
100         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
101         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
102
103 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
104         (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
105         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
106         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
107         (14 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
108         (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) |    \
109         (1 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
110         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
111
112 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
113         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
114         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
115         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
116         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
117         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
118         (2 << DV_DDR_SDCR_CL_SHIFT) |   \
119         (3 << DV_DDR_SDCR_IBANK_SHIFT) |        \
120         (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
121
122 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
123                                 DAVINCI_ABCR_WSTROBE(2) | \
124                                 DAVINCI_ABCR_WHOLD(0)   | \
125                                 DAVINCI_ABCR_RSETUP(1)  | \
126                                 DAVINCI_ABCR_RSTROBE(2) | \
127                                 DAVINCI_ABCR_RHOLD(1)   | \
128                                 DAVINCI_ABCR_TA(0)      | \
129                                 DAVINCI_ABCR_ASIZE_8BIT)
130
131 /*
132  * Serial Driver info
133  */
134 #define CONFIG_SYS_NS16550_SERIAL
135 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
136 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
137 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
138 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
139 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
140
141 /*
142  * Flash & Environment
143  */
144 #define CONFIG_NAND_DAVINCI
145 #define CONFIG_SYS_NO_FLASH
146 #define CONFIG_ENV_IS_IN_NAND           /* U-Boot env in NAND Flash  */
147 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
148 #define CONFIG_ENV_SIZE                 (128 << 10)
149 #define CONFIG_SYS_NAND_USE_FLASH_BBT
150 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
151 #define CONFIG_SYS_NAND_PAGE_2K
152 #define CONFIG_SYS_NAND_CS              3
153 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
154 #define CONFIG_SYS_NAND_MASK_CLE                0x10
155 #define CONFIG_SYS_NAND_MASK_ALE                0x8
156 #undef CONFIG_SYS_NAND_HW_ECC
157 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
158 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
159 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
160 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
161 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
162 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
163 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
164 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x120000
165 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
166 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
167 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
168                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
169                                         CONFIG_SYS_MALLOC_LEN -       \
170                                         GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_NAND_ECCPOS          {                               \
172                         6,   7,  8,  9, 10,     11, 12, 13, 14, 15,     \
173                         22, 23, 24, 25, 26,     27, 28, 29, 30, 31,     \
174                         38, 39, 40, 41, 42,     43, 44, 45, 46, 47,     \
175                         54, 55, 56, 57, 58,     59, 60, 61, 62, 63}
176 #define CONFIG_SYS_NAND_PAGE_COUNT      64
177 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
178 #define CONFIG_SYS_NAND_ECCSIZE         512
179 #define CONFIG_SYS_NAND_ECCBYTES        10
180 #define CONFIG_SYS_NAND_OOBSIZE         64
181 #define CONFIG_SPL_NAND_SUPPORT
182 #define CONFIG_SPL_NAND_BASE
183 #define CONFIG_SPL_NAND_DRIVERS
184 #define CONFIG_SPL_NAND_ECC
185 #define CONFIG_SPL_NAND_SIMPLE
186 #define CONFIG_SPL_NAND_LOAD
187
188 /*
189  * Network & Ethernet Configuration
190  */
191 #ifdef CONFIG_DRIVER_TI_EMAC
192 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
193 #define CONFIG_BOOTP_DEFAULT
194 #define CONFIG_BOOTP_DNS
195 #define CONFIG_BOOTP_DNS2
196 #define CONFIG_BOOTP_SEND_HOSTNAME
197 #define CONFIG_NET_RETRY_COUNT  10
198 #endif
199
200 /*
201  * U-Boot general configuration
202  */
203 #define CONFIG_MISC_INIT_R
204 #define CONFIG_BOARD_EARLY_INIT_F
205 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
206 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
207 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
208 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
209 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
210 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
211 #define CONFIG_AUTO_COMPLETE
212 #define CONFIG_CMDLINE_EDITING
213 #define CONFIG_SYS_LONGHELP
214 #define CONFIG_CRC32_VERIFY
215 #define CONFIG_MX_CYCLIC
216
217 /*
218  * Linux Information
219  */
220 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
221 #define CONFIG_HWCONFIG         /* enable hwconfig */
222 #define CONFIG_CMDLINE_TAG
223 #define CONFIG_REVISION_TAG
224 #define CONFIG_SETUP_MEMORY_TAGS
225 #define CONFIG_EXTRA_ENV_SETTINGS \
226         "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
227                 "root=/dev/mtdblock5 rw noinitrd " \
228                 "rootfstype=jffs2 noinitrd\0" \
229         "hwconfig=dsp:wake=yes\0" \
230         "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
231         "bootfile=uImage\0" \
232         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"      \
233         "mtddevname=uboot-env\0" \
234         "mtddevnum=0\0" \
235         "mtdids=" MTDIDS_DEFAULT "\0"                           \
236         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
237         "u-boot=/tftpboot/ipam390/u-boot.ais\0"                 \
238         "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
239                 "nand write c0000000 20000 ${filesize}\0"       \
240         "setbootparms=nand read c0100000 200000 400000;"        \
241                 "run defbootargs addmtd;"                       \
242                 "spl export atags c0100000;"                    \
243                 "nand erase.part bootparms;"                    \
244                 "nand write c0000100 180000 20000\0"            \
245         "\0"
246
247 /*
248  * U-Boot commands
249  */
250 #define CONFIG_CMD_ENV
251 #define CONFIG_CMD_DIAG
252 #define CONFIG_CMD_SAVES
253
254 #ifdef CONFIG_CMD_BDI
255 #define CONFIG_CLOCKS
256 #endif
257
258 #ifndef CONFIG_DRIVER_TI_EMAC
259 #endif
260
261 #define CONFIG_CMD_NAND
262 #define CONFIG_CMD_NAND_TRIMFFS
263
264 #define CONFIG_CMD_MTDPARTS
265 #define CONFIG_MTD_DEVICE
266 #define CONFIG_MTD_PARTITIONS
267 #define CONFIG_LZO
268 #define CONFIG_RBTREE
269 #define CONFIG_CMD_UBI
270 #define CONFIG_CMD_UBIFS
271
272 #define MTDIDS_NAME_STR         "davinci_nand.0"
273 #define MTDIDS_DEFAULT          "nand0=" MTDIDS_NAME_STR
274 #define MTDPARTS_DEFAULT        "mtdparts=" MTDIDS_NAME_STR ":" \
275                                         "128k(u-boot-env),"     \
276                                         "1408k(u-boot),"        \
277                                         "128k(bootparms),"      \
278                                         "384k(factory-info),"   \
279                                         "4M(kernel),"   \
280                                         "-(rootfs)"
281
282 /* defines for SPL */
283 #define CONFIG_SPL_FRAMEWORK
284 #define CONFIG_SPL_BOARD_INIT
285 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
286                                                 CONFIG_SYS_MALLOC_LEN)
287 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
288 #define CONFIG_SPL_SERIAL_SUPPORT
289 #define CONFIG_SPL_LIBCOMMON_SUPPORT
290 #define CONFIG_SPL_LIBGENERIC_SUPPORT
291 #define CONFIG_SPL_LDSCRIPT     "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
292 #define CONFIG_SPL_STACK        0x8001ff00
293 #define CONFIG_SPL_TEXT_BASE    0x80000000
294 #define CONFIG_SPL_MAX_SIZE     0x20000
295 #define CONFIG_SPL_MAX_FOOTPRINT        32768
296
297 /* additions for new relocation code, must added to all boards */
298 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
299
300 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
301                                         GENERATED_GBL_DATA_SIZE)
302
303 /* add FALCON boot mode */
304 #define CONFIG_CMD_SPL
305 #define CONFIG_SPL_OS_BOOT
306 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
307 #define CONFIG_SYS_SPL_ARGS_ADDR        LINUX_BOOT_PARAM_ADDR
308 #define CONFIG_CMD_SPL_NAND_OFS         0x00180000
309 #define CONFIG_CMD_SPL_WRITE_SIZE       0x400
310
311 /* GPIO support */
312 #define CONFIG_DA8XX_GPIO
313 #define CONFIG_IPAM390_GPIO_BOOTMODE    ((16 * 7) + 14)
314
315 #define CONFIG_SHOW_BOOT_PROGRESS
316 #define CONFIG_IPAM390_GPIO_LED_RED     ((16 * 7) + 11)
317 #define CONFIG_IPAM390_GPIO_LED_GREEN   ((16 * 7) + 12)
318
319 #endif /* __CONFIG_H */