git.sur5r.net Git - u-boot/blob - include/configs/km/km8321-common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2008
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  *
  15  * (C) Copyright 2010
  16  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
  17  *
  18  * (C) Copyright 2010-2011
  19  * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
  20  */
  21
  22 #ifndef __CONFIG_KM8321_COMMON_H
  23 #define __CONFIG_KM8321_COMMON_H
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_QE       /* Has QE */
  29 #define CONFIG_MPC832x  /* MPC832x CPU specific */
  30 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  31
  32 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  33
  34 /* include common defines/options for all 83xx Keymile boards */
  35 #include "km83xx-common.h"
  36
  37 /*
  38  * System IO Config
  39  */
  40 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
  41
  42 /*
  43  * Hardware Reset Configuration Word
  44  */
  45 #define CONFIG_SYS_HRCW_LOW (\
  46         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
  47         HRCWL_DDR_TO_SCB_CLK_2X1 | \
  48         HRCWL_CSB_TO_CLKIN_2X1 | \
  49         HRCWL_CORE_TO_CSB_2_5X1 | \
  50         HRCWL_CE_PLL_VCO_DIV_2 | \
  51         HRCWL_CE_TO_PLL_1X3)
  52
  53 #define CONFIG_SYS_HRCW_HIGH (\
  54         HRCWH_PCI_AGENT | \
  55         HRCWH_PCI_ARBITER_DISABLE | \
  56         HRCWH_CORE_ENABLE | \
  57         HRCWH_FROM_0X00000100 | \
  58         HRCWH_BOOTSEQ_DISABLE | \
  59         HRCWH_SW_WATCHDOG_DISABLE | \
  60         HRCWH_ROM_LOC_LOCAL_16BIT | \
  61         HRCWH_BIG_ENDIAN | \
  62         HRCWH_LALE_NORMAL)
  63
  64 #define CONFIG_SYS_DDRCDR (\
  65         DDRCDR_EN | \
  66         DDRCDR_PZ_MAXZ | \
  67         DDRCDR_NZ_MAXZ | \
  68         DDRCDR_M_ODR)
  69
  70 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  71 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  72                                          SDRAM_CFG_32_BE | \
  73                                          SDRAM_CFG_SREN | \
  74                                          SDRAM_CFG_HSE)
  75
  76 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  77 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  78 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  79                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  80
  81 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  82                                          CSCONFIG_ODT_WR_CFG | \
  83                                          CSCONFIG_ROW_BIT_13 | \
  84                                          CSCONFIG_COL_BIT_10)
  85
  86 #define CONFIG_SYS_DDR_MODE     0x47860242
  87 #define CONFIG_SYS_DDR_MODE2    0x8080c000
  88
  89 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  90                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  91                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  92                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  93                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  94                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  95                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  96                                  (0 << TIMING_CFG0_RWT_SHIFT))
  97
  98 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
  99                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 100                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 101                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 102                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 103                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 104                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 105                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 106
 107 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 108                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 109                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 110                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 111                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 112                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 113                                  (5 << TIMING_CFG2_CPO_SHIFT))
 114
 115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 116
 117 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 118 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 119
 120 /* EEprom support */
 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 122
 123 /*
 124  * Local Bus Configuration & Clock Setup
 125  */
 126 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 127 #define CONFIG_SYS_LCRR_EADC    0x00010000
 128 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 129
 130 #define CONFIG_SYS_LBC_LBCR     0x00000000
 131
 132 /*
 133  * MMU Setup
 134  */
 135 #define CONFIG_SYS_IBAT7L       (0)
 136 #define CONFIG_SYS_IBAT7U       (0)
 137 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 138 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 139
 140 #endif /* __CONFIG_KM8321_COMMON_H */