git.sur5r.net Git - u-boot/blob - include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_PSCI_1_0
  11
  12 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17
  18 #define CONFIG_DEEP_SLEEP
  19
  20 /*
  21  * Size of malloc() pool
  22  */
  23 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  24
  25 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  26 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  27
  28 #ifndef __ASSEMBLY__
  29 unsigned long get_board_sys_clk(void);
  30 unsigned long get_board_ddr_clk(void);
  31 #endif
  32
  33 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  34 #define CONFIG_SYS_CLK_FREQ             100000000
  35 #define CONFIG_DDR_CLK_FREQ             100000000
  36 #define CONFIG_QIXIS_I2C_ACCESS
  37 #else
  38 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  39 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  40 #endif
  41
  42 #ifdef CONFIG_RAMBOOT_PBL
  43 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  44 #endif
  45
  46 #ifdef CONFIG_SD_BOOT
  47 #ifdef CONFIG_SD_BOOT_QSPI
  48 #define CONFIG_SYS_FSL_PBL_RCW  \
  49         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  50 #else
  51 #define CONFIG_SYS_FSL_PBL_RCW  \
  52         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  53 #endif
  54 #define CONFIG_SPL_FRAMEWORK
  55
  56 #define CONFIG_SPL_TEXT_BASE            0x10000000
  57 #define CONFIG_SPL_MAX_SIZE             0x1a000
  58 #define CONFIG_SPL_STACK                0x1001d000
  59 #define CONFIG_SPL_PAD_TO               0x1c000
  60
  61 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  62                 CONFIG_SYS_MONITOR_LEN)
  63 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  64 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  65 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  66 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  67 #endif
  68
  69 #ifdef CONFIG_NAND_BOOT
  70 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  71 #define CONFIG_SPL_FRAMEWORK
  72
  73 #define CONFIG_SPL_TEXT_BASE            0x10000000
  74 #define CONFIG_SPL_MAX_SIZE             0x1a000
  75 #define CONFIG_SPL_STACK                0x1001d000
  76 #define CONFIG_SPL_PAD_TO               0x1c000
  77
  78 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  79 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  80 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  81 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  82 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  83
  84 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  85 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  86 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  87 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  88 #define CONFIG_SYS_MONITOR_LEN          0x80000
  89 #endif
  90
  91 #define CONFIG_NR_DRAM_BANKS            1
  92
  93 #define CONFIG_DDR_SPD
  94 #define SPD_EEPROM_ADDRESS              0x51
  95 #define CONFIG_SYS_SPD_BUS_NUM          0
  96
  97 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  98 #ifndef CONFIG_SYS_FSL_DDR4
  99 #define CONFIG_SYS_DDR_RAW_TIMING
 100 #endif
 101 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 102 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 103
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 106
 107 #define CONFIG_DDR_ECC
 108 #ifdef CONFIG_DDR_ECC
 109 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 110 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 111 #endif
 112
 113 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 114         !defined(CONFIG_QSPI_BOOT)
 115 #define CONFIG_U_QE
 116 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 117 #endif
 118
 119 /*
 120  * IFC Definitions
 121  */
 122 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 123 #define CONFIG_FSL_IFC
 124 #define CONFIG_SYS_FLASH_BASE           0x60000000
 125 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 126
 127 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 128 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 129                                 CSPR_PORT_SIZE_16 | \
 130                                 CSPR_MSEL_NOR | \
 131                                 CSPR_V)
 132 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 133 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 134                                 + 0x8000000) | \
 135                                 CSPR_PORT_SIZE_16 | \
 136                                 CSPR_MSEL_NOR | \
 137                                 CSPR_V)
 138 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 139
 140 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 141                                         CSOR_NOR_TRHZ_80)
 142 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 143                                         FTIM0_NOR_TEADC(0x5) | \
 144                                         FTIM0_NOR_TEAHC(0x5))
 145 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 146                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 147                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 148 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 149                                         FTIM2_NOR_TCH(0x4) | \
 150                                         FTIM2_NOR_TWPH(0xe) | \
 151                                         FTIM2_NOR_TWP(0x1c))
 152 #define CONFIG_SYS_NOR_FTIM3            0
 153
 154 #define CONFIG_FLASH_CFI_DRIVER
 155 #define CONFIG_SYS_FLASH_CFI
 156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 157 #define CONFIG_SYS_FLASH_QUIET_TEST
 158 #define CONFIG_FLASH_SHOW_PROGRESS      45
 159 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 160 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 161
 162 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 163 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 164 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 165 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 166
 167 #define CONFIG_SYS_FLASH_EMPTY_INFO
 168 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 169                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 170
 171 /*
 172  * NAND Flash Definitions
 173  */
 174 #define CONFIG_NAND_FSL_IFC
 175
 176 #define CONFIG_SYS_NAND_BASE            0x7e800000
 177 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 178
 179 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 180
 181 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 182                                 | CSPR_PORT_SIZE_8      \
 183                                 | CSPR_MSEL_NAND        \
 184                                 | CSPR_V)
 185 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 186 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 187                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 188                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 189                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 190                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 191                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 192                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 193
 194 #define CONFIG_SYS_NAND_ONFI_DETECTION
 195
 196 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 197                                         FTIM0_NAND_TWP(0x18)   | \
 198                                         FTIM0_NAND_TWCHT(0x7) | \
 199                                         FTIM0_NAND_TWH(0xa))
 200 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 201                                         FTIM1_NAND_TWBE(0x39)  | \
 202                                         FTIM1_NAND_TRR(0xe)   | \
 203                                         FTIM1_NAND_TRP(0x18))
 204 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 205                                         FTIM2_NAND_TREH(0xa) | \
 206                                         FTIM2_NAND_TWHRE(0x1e))
 207 #define CONFIG_SYS_NAND_FTIM3           0x0
 208
 209 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 210 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 211
 212 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 213 #endif
 214
 215 /*
 216  * QIXIS Definitions
 217  */
 218 #define CONFIG_FSL_QIXIS
 219
 220 #ifdef CONFIG_FSL_QIXIS
 221 #define QIXIS_BASE                      0x7fb00000
 222 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 223 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 224 #define QIXIS_LBMAP_SWITCH              6
 225 #define QIXIS_LBMAP_MASK                0x0f
 226 #define QIXIS_LBMAP_SHIFT               0
 227 #define QIXIS_LBMAP_DFLTBANK            0x00
 228 #define QIXIS_LBMAP_ALTBANK             0x04
 229 #define QIXIS_PWR_CTL                   0x21
 230 #define QIXIS_PWR_CTL_POWEROFF          0x80
 231 #define QIXIS_RST_CTL_RESET             0x44
 232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 233 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 235 #define QIXIS_CTL_SYS                   0x5
 236 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 237 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 238 #define QIXIS_RST_FORCE_3               0x45
 239 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 240 #define QIXIS_PWR_CTL2                  0x21
 241 #define QIXIS_PWR_CTL2_PCTL             0x2
 242
 243 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 244 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 245                                         CSPR_PORT_SIZE_8 | \
 246                                         CSPR_MSEL_GPCM | \
 247                                         CSPR_V)
 248 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 249 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 250                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 251                                         CSOR_NOR_TRHZ_80)
 252
 253 /*
 254  * QIXIS Timing parameters for IFC GPCM
 255  */
 256 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 257                                         FTIM0_GPCM_TEADC(0xe) | \
 258                                         FTIM0_GPCM_TEAHC(0xe))
 259 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 260                                         FTIM1_GPCM_TRAD(0x1f))
 261 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 262                                         FTIM2_GPCM_TCH(0xe) | \
 263                                         FTIM2_GPCM_TWP(0xf0))
 264 #define CONFIG_SYS_FPGA_FTIM3           0x0
 265 #endif
 266
 267 #if defined(CONFIG_NAND_BOOT)
 268 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 269 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 270 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 271 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 272 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 273 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 274 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 275 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 276 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 277 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 278 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 279 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 280 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 281 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 282 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 283 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 284 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 285 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 286 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 287 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 288 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 289 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 290 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 291 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 292 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 293 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 294 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 295 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 296 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 297 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 298 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 299 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 300 #else
 301 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 302 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 303 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 304 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 305 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 306 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 307 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 308 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 309 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 310 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 311 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 312 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 313 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 314 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 315 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 316 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 317 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 318 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 319 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 320 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 321 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 322 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 323 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 324 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 325 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 326 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 327 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 328 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 329 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 330 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 331 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 332 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 333 #endif
 334
 335 /*
 336  * Serial Port
 337  */
 338 #ifdef CONFIG_LPUART
 339 #define CONFIG_LPUART_32B_REG
 340 #else
 341 #define CONFIG_CONS_INDEX               1
 342 #define CONFIG_SYS_NS16550_SERIAL
 343 #ifndef CONFIG_DM_SERIAL
 344 #define CONFIG_SYS_NS16550_REG_SIZE     1
 345 #endif
 346 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 347 #endif
 348
 349 /*
 350  * I2C
 351  */
 352 #define CONFIG_SYS_I2C
 353 #define CONFIG_SYS_I2C_MXC
 354 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 355 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 356 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 357
 358 /*
 359  * I2C bus multiplexer
 360  */
 361 #define I2C_MUX_PCA_ADDR_PRI            0x77
 362 #define I2C_MUX_CH_DEFAULT              0x8
 363 #define I2C_MUX_CH_CH7301               0xC
 364
 365 /*
 366  * MMC
 367  */
 368 #define CONFIG_FSL_ESDHC
 369
 370 /* SPI */
 371 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 372 /* QSPI */
 373 #define QSPI0_AMBA_BASE                 0x40000000
 374 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 375 #define FSL_QSPI_FLASH_NUM              2
 376
 377 /* DSPI */
 378
 379 /* DM SPI */
 380 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 381 #define CONFIG_DM_SPI_FLASH
 382 #define CONFIG_SPI_FLASH_DATAFLASH
 383 #endif
 384 #endif
 385
 386 /*
 387  * Video
 388  */
 389 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 390 #define CONFIG_VIDEO_LOGO
 391 #define CONFIG_VIDEO_BMP_LOGO
 392
 393 #define CONFIG_FSL_DIU_CH7301
 394 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 395 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 396 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 397 #endif
 398
 399 /*
 400  * eTSEC
 401  */
 402 #define CONFIG_TSEC_ENET
 403
 404 #ifdef CONFIG_TSEC_ENET
 405 #define CONFIG_MII
 406 #define CONFIG_MII_DEFAULT_TSEC         3
 407 #define CONFIG_TSEC1                    1
 408 #define CONFIG_TSEC1_NAME               "eTSEC1"
 409 #define CONFIG_TSEC2                    1
 410 #define CONFIG_TSEC2_NAME               "eTSEC2"
 411 #define CONFIG_TSEC3                    1
 412 #define CONFIG_TSEC3_NAME               "eTSEC3"
 413
 414 #define TSEC1_PHY_ADDR                  1
 415 #define TSEC2_PHY_ADDR                  2
 416 #define TSEC3_PHY_ADDR                  3
 417
 418 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 419 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 420 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 421
 422 #define TSEC1_PHYIDX                    0
 423 #define TSEC2_PHYIDX                    0
 424 #define TSEC3_PHYIDX                    0
 425
 426 #define CONFIG_ETHPRIME                 "eTSEC1"
 427
 428 #define CONFIG_PHY_REALTEK
 429
 430 #define CONFIG_HAS_ETH0
 431 #define CONFIG_HAS_ETH1
 432 #define CONFIG_HAS_ETH2
 433
 434 #define CONFIG_FSL_SGMII_RISER          1
 435 #define SGMII_RISER_PHY_OFFSET          0x1b
 436
 437 #ifdef CONFIG_FSL_SGMII_RISER
 438 #define CONFIG_SYS_TBIPA_VALUE          8
 439 #endif
 440
 441 #endif
 442
 443 /* PCIe */
 444 #define CONFIG_PCIE1            /* PCIE controller 1 */
 445 #define CONFIG_PCIE2            /* PCIE controller 2 */
 446
 447 #ifdef CONFIG_PCI
 448 #define CONFIG_PCI_SCAN_SHOW
 449 #endif
 450
 451 #define CONFIG_CMDLINE_TAG
 452 #define CONFIG_CMDLINE_EDITING
 453
 454 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 455 #define CONFIG_LAYERSCAPE_NS_ACCESS
 456 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 457 #define COUNTER_FREQUENCY               12500000
 458
 459 #define CONFIG_HWCONFIG
 460 #define HWCONFIG_BUFFER_SIZE            256
 461
 462 #define CONFIG_FSL_DEVICE_DISABLE
 463
 464
 465 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 466
 467 #ifdef CONFIG_LPUART
 468 #define CONFIG_EXTRA_ENV_SETTINGS       \
 469         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 470         "fdt_high=0xffffffff\0"         \
 471         "initrd_high=0xffffffff\0"      \
 472         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 473 #else
 474 #define CONFIG_EXTRA_ENV_SETTINGS       \
 475         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 476         "fdt_high=0xffffffff\0"         \
 477         "initrd_high=0xffffffff\0"      \
 478         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 479 #endif
 480
 481 /*
 482  * Miscellaneous configurable options
 483  */
 484 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 485 #define CONFIG_AUTO_COMPLETE
 486
 487 #define CONFIG_SYS_MEMTEST_START        0x80000000
 488 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 489
 490 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 491
 492 #define CONFIG_LS102XA_STREAM_ID
 493
 494 #define CONFIG_SYS_INIT_SP_OFFSET \
 495         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 496 #define CONFIG_SYS_INIT_SP_ADDR \
 497         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 498
 499 #ifdef CONFIG_SPL_BUILD
 500 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 501 #else
 502 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 503 #endif
 504
 505 /*
 506  * Environment
 507  */
 508 #define CONFIG_ENV_OVERWRITE
 509
 510 #if defined(CONFIG_SD_BOOT)
 511 #define CONFIG_ENV_OFFSET               0x300000
 512 #define CONFIG_SYS_MMC_ENV_DEV          0
 513 #define CONFIG_ENV_SIZE                 0x2000
 514 #elif defined(CONFIG_QSPI_BOOT)
 515 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 516 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 517 #define CONFIG_ENV_SECT_SIZE            0x10000
 518 #elif defined(CONFIG_NAND_BOOT)
 519 #define CONFIG_ENV_SIZE                 0x2000
 520 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 521 #else
 522 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 523 #define CONFIG_ENV_SIZE                 0x2000
 524 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 525 #endif
 526
 527 #define CONFIG_MISC_INIT_R
 528
 529 #include <asm/fsl_secure_boot.h>
 530 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 531
 532 #endif