git.sur5r.net Git - u-boot/blob - include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_PSCI_1_0
  11
  12 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17 #define CONFIG_DEEP_SLEEP
  18
  19 /*
  20  * Size of malloc() pool
  21  */
  22 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  23
  24 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  25 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  26
  27 /*
  28  * USB
  29  */
  30
  31 /*
  32  * EHCI Support - disbaled by default as
  33  * there is no signal coming out of soc on
  34  * this board for this controller. However,
  35  * the silicon still has this controller,
  36  * and anyone can use this controller by
  37  * taking signals out on their board.
  38  */
  39
  40 /*#define CONFIG_HAS_FSL_DR_USB*/
  41
  42 #ifdef CONFIG_HAS_FSL_DR_USB
  43 #define CONFIG_USB_EHCI_FSL
  44 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  45 #endif
  46
  47 /* XHCI Support - enabled by default */
  48 #define CONFIG_HAS_FSL_XHCI_USB
  49
  50 #ifdef CONFIG_HAS_FSL_XHCI_USB
  51 #define CONFIG_USB_XHCI_FSL
  52 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
  53 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
  54 #endif
  55
  56 #define CONFIG_SYS_CLK_FREQ             100000000
  57 #define CONFIG_DDR_CLK_FREQ             100000000
  58
  59 #define DDR_SDRAM_CFG                   0x470c0008
  60 #define DDR_CS0_BNDS                    0x008000bf
  61 #define DDR_CS0_CONFIG                  0x80014302
  62 #define DDR_TIMING_CFG_0                0x50550004
  63 #define DDR_TIMING_CFG_1                0xbcb38c56
  64 #define DDR_TIMING_CFG_2                0x0040d120
  65 #define DDR_TIMING_CFG_3                0x010e1000
  66 #define DDR_TIMING_CFG_4                0x00000001
  67 #define DDR_TIMING_CFG_5                0x03401400
  68 #define DDR_SDRAM_CFG_2                 0x00401010
  69 #define DDR_SDRAM_MODE                  0x00061c60
  70 #define DDR_SDRAM_MODE_2                0x00180000
  71 #define DDR_SDRAM_INTERVAL              0x18600618
  72 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  73 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  74 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  75 #define DDR_DDR_CDR1                    0x80040000
  76 #define DDR_DDR_CDR2                    0x00000001
  77 #define DDR_SDRAM_CLK_CNTL              0x02000000
  78 #define DDR_DDR_ZQ_CNTL                 0x89080600
  79 #define DDR_CS0_CONFIG_2                0
  80 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  81 #define SDRAM_CFG2_D_INIT               0x00000010
  82 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  83 #define SDRAM_CFG2_FRC_SR               0x80000000
  84 #define SDRAM_CFG_BI                    0x00000001
  85
  86 #ifdef CONFIG_RAMBOOT_PBL
  87 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  88 #endif
  89
  90 #ifdef CONFIG_SD_BOOT
  91 #ifdef CONFIG_SD_BOOT_QSPI
  92 #define CONFIG_SYS_FSL_PBL_RCW  \
  93         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  94 #else
  95 #define CONFIG_SYS_FSL_PBL_RCW  \
  96         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  97 #endif
  98 #define CONFIG_SPL_FRAMEWORK
  99 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
 100
 101 #ifdef CONFIG_SECURE_BOOT
 102 /*
 103  * HDR would be appended at end of image and copied to DDR along
 104  * with U-Boot image.
 105  */
 106 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
 107 #endif /* ifdef CONFIG_SECURE_BOOT */
 108
 109 #define CONFIG_SPL_TEXT_BASE            0x10000000
 110 #define CONFIG_SPL_MAX_SIZE             0x1a000
 111 #define CONFIG_SPL_STACK                0x1001d000
 112 #define CONFIG_SPL_PAD_TO               0x1c000
 113 #define CONFIG_SYS_TEXT_BASE            0x82000000
 114
 115 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 116                 CONFIG_SYS_MONITOR_LEN)
 117 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 118 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 119 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 120
 121 #ifdef CONFIG_U_BOOT_HDR_SIZE
 122 /*
 123  * HDR would be appended at end of image and copied to DDR along
 124  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 125  * size increases then increase this size in case of secure boot as
 126  * it uses raw u-boot image instead of fit image.
 127  */
 128 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 129 #else
 130 #define CONFIG_SYS_MONITOR_LEN          0x100000
 131 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 132 #endif
 133
 134 #ifdef CONFIG_QSPI_BOOT
 135 #define CONFIG_SYS_TEXT_BASE            0x40010000
 136 #endif
 137
 138 #ifndef CONFIG_SYS_TEXT_BASE
 139 #define CONFIG_SYS_TEXT_BASE            0x60100000
 140 #endif
 141
 142 #define CONFIG_NR_DRAM_BANKS            1
 143 #define PHYS_SDRAM                      0x80000000
 144 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 145
 146 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 147 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 148
 149 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 150         !defined(CONFIG_QSPI_BOOT)
 151 #define CONFIG_U_QE
 152 #endif
 153
 154 /*
 155  * IFC Definitions
 156  */
 157 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 158 #define CONFIG_FSL_IFC
 159 #define CONFIG_SYS_FLASH_BASE           0x60000000
 160 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 161
 162 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 163 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 164                                 CSPR_PORT_SIZE_16 | \
 165                                 CSPR_MSEL_NOR | \
 166                                 CSPR_V)
 167 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 168
 169 /* NOR Flash Timing Params */
 170 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 171                                         CSOR_NOR_TRHZ_80)
 172 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 173                                         FTIM0_NOR_TEADC(0x5) | \
 174                                         FTIM0_NOR_TAVDS(0x0) | \
 175                                         FTIM0_NOR_TEAHC(0x5))
 176 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 177                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 178                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 179 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 180                                         FTIM2_NOR_TCH(0x4) | \
 181                                         FTIM2_NOR_TWP(0x1c) | \
 182                                         FTIM2_NOR_TWPH(0x0e))
 183 #define CONFIG_SYS_NOR_FTIM3            0
 184
 185 #define CONFIG_FLASH_CFI_DRIVER
 186 #define CONFIG_SYS_FLASH_CFI
 187 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 188 #define CONFIG_SYS_FLASH_QUIET_TEST
 189 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 190
 191 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 192 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 193 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 194 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 195
 196 #define CONFIG_SYS_FLASH_EMPTY_INFO
 197 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 198
 199 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 200 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 201 #endif
 202
 203 /* CPLD */
 204
 205 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 206 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 207
 208 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 209 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 210                                         CSPR_PORT_SIZE_8 | \
 211                                         CSPR_MSEL_GPCM | \
 212                                         CSPR_V)
 213 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 214 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 215                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 216                                         CSOR_NOR_TRHZ_80)
 217
 218 /* CPLD Timing parameters for IFC GPCM */
 219 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 220                                         FTIM0_GPCM_TEADC(0xf) | \
 221                                         FTIM0_GPCM_TEAHC(0xf))
 222 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 223                                         FTIM1_GPCM_TRAD(0x3f))
 224 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 225                                         FTIM2_GPCM_TCH(0xf) | \
 226                                         FTIM2_GPCM_TWP(0xff))
 227 #define CONFIG_SYS_FPGA_FTIM3           0x0
 228 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 229 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 230 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 231 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 232 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 233 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 234 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 235 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 236 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 237 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 238 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 239 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 240 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 241 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 242 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 243 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 244
 245 /*
 246  * Serial Port
 247  */
 248 #ifdef CONFIG_LPUART
 249 #define CONFIG_LPUART_32B_REG
 250 #else
 251 #define CONFIG_CONS_INDEX               1
 252 #define CONFIG_SYS_NS16550_SERIAL
 253 #ifndef CONFIG_DM_SERIAL
 254 #define CONFIG_SYS_NS16550_REG_SIZE     1
 255 #endif
 256 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 257 #endif
 258
 259 /*
 260  * I2C
 261  */
 262 #define CONFIG_SYS_I2C
 263 #define CONFIG_SYS_I2C_MXC
 264 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 265 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 266 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 267
 268 /* EEPROM */
 269 #define CONFIG_ID_EEPROM
 270 #define CONFIG_SYS_I2C_EEPROM_NXID
 271 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 272 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 273 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 274 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 275 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 276
 277 /*
 278  * MMC
 279  */
 280 #define CONFIG_FSL_ESDHC
 281
 282 /* SPI */
 283 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 284 /* QSPI */
 285 #define QSPI0_AMBA_BASE                 0x40000000
 286 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 287 #define FSL_QSPI_FLASH_NUM              2
 288
 289 /* DSPI */
 290 #endif
 291
 292 /* DM SPI */
 293 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 294 #define CONFIG_DM_SPI_FLASH
 295 #endif
 296
 297 /*
 298  * Video
 299  */
 300 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 301 #define CONFIG_VIDEO_LOGO
 302 #define CONFIG_VIDEO_BMP_LOGO
 303
 304 #define CONFIG_FSL_DCU_SII9022A
 305 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 306 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 307 #endif
 308
 309 /*
 310  * eTSEC
 311  */
 312 #define CONFIG_TSEC_ENET
 313
 314 #ifdef CONFIG_TSEC_ENET
 315 #define CONFIG_MII
 316 #define CONFIG_MII_DEFAULT_TSEC         1
 317 #define CONFIG_TSEC1                    1
 318 #define CONFIG_TSEC1_NAME               "eTSEC1"
 319 #define CONFIG_TSEC2                    1
 320 #define CONFIG_TSEC2_NAME               "eTSEC2"
 321 #define CONFIG_TSEC3                    1
 322 #define CONFIG_TSEC3_NAME               "eTSEC3"
 323
 324 #define TSEC1_PHY_ADDR                  2
 325 #define TSEC2_PHY_ADDR                  0
 326 #define TSEC3_PHY_ADDR                  1
 327
 328 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 329 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 330 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 331
 332 #define TSEC1_PHYIDX                    0
 333 #define TSEC2_PHYIDX                    0
 334 #define TSEC3_PHYIDX                    0
 335
 336 #define CONFIG_ETHPRIME                 "eTSEC1"
 337
 338 #define CONFIG_PHY_GIGE
 339 #define CONFIG_PHYLIB
 340 #define CONFIG_PHY_ATHEROS
 341
 342 #define CONFIG_HAS_ETH0
 343 #define CONFIG_HAS_ETH1
 344 #define CONFIG_HAS_ETH2
 345 #endif
 346
 347 /* PCIe */
 348 #define CONFIG_PCIE1            /* PCIE controller 1 */
 349 #define CONFIG_PCIE2            /* PCIE controller 2 */
 350
 351 #ifdef CONFIG_PCI
 352 #define CONFIG_PCI_SCAN_SHOW
 353 #define CONFIG_CMD_PCI
 354 #endif
 355
 356 #define CONFIG_CMDLINE_TAG
 357 #define CONFIG_CMDLINE_EDITING
 358
 359 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 360 #define CONFIG_LAYERSCAPE_NS_ACCESS
 361 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 362 #define COUNTER_FREQUENCY               12500000
 363
 364 #define CONFIG_HWCONFIG
 365 #define HWCONFIG_BUFFER_SIZE            256
 366
 367 #define CONFIG_FSL_DEVICE_DISABLE
 368
 369
 370 #ifdef CONFIG_LPUART
 371 #define CONFIG_EXTRA_ENV_SETTINGS       \
 372         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 373         "initrd_high=0xffffffff\0"      \
 374         "fdt_high=0xffffffff\0"
 375 #else
 376 #define CONFIG_EXTRA_ENV_SETTINGS       \
 377         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 378         "initrd_high=0xffffffff\0"      \
 379         "fdt_high=0xffffffff\0"
 380 #endif
 381
 382 /*
 383  * Miscellaneous configurable options
 384  */
 385 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 386 #define CONFIG_AUTO_COMPLETE
 387 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 388 #define CONFIG_SYS_PBSIZE               \
 389                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 390 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 391 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 392
 393 #define CONFIG_SYS_MEMTEST_START        0x80000000
 394 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 395
 396 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 397
 398 #define CONFIG_LS102XA_STREAM_ID
 399
 400 #define CONFIG_SYS_INIT_SP_OFFSET \
 401         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 402 #define CONFIG_SYS_INIT_SP_ADDR \
 403         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 404
 405 #ifdef CONFIG_SPL_BUILD
 406 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 407 #else
 408 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 409 #endif
 410
 411 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 412
 413 /*
 414  * Environment
 415  */
 416 #define CONFIG_ENV_OVERWRITE
 417
 418 #if defined(CONFIG_SD_BOOT)
 419 #define CONFIG_ENV_OFFSET               0x100000
 420 #define CONFIG_ENV_IS_IN_MMC
 421 #define CONFIG_SYS_MMC_ENV_DEV          0
 422 #define CONFIG_ENV_SIZE                 0x20000
 423 #elif defined(CONFIG_QSPI_BOOT)
 424 #define CONFIG_ENV_IS_IN_SPI_FLASH
 425 #define CONFIG_ENV_SIZE                 0x2000
 426 #define CONFIG_ENV_OFFSET               0x100000
 427 #define CONFIG_ENV_SECT_SIZE            0x10000
 428 #else
 429 #define CONFIG_ENV_IS_IN_FLASH
 430 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 431 #define CONFIG_ENV_SIZE                 0x20000
 432 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 433 #endif
 434
 435 #define CONFIG_MISC_INIT_R
 436
 437 /* Hash command with SHA acceleration supported in hardware */
 438 #ifdef CONFIG_FSL_CAAM
 439 #define CONFIG_CMD_HASH
 440 #endif
 441
 442 #include <asm/fsl_secure_boot.h>
 443 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 444
 445 #endif