git.sur5r.net Git - u-boot/blob - include/configs/ve8313.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * (C) Copyright 2010
   5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /*
  10  * ve8313 board configuration file
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 #define CONFIG_E300             1
  22 #define CONFIG_MPC831x          1
  23 #define CONFIG_MPC8313          1
  24 #define CONFIG_VE8313           1
  25
  26 #ifndef CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_SYS_TEXT_BASE    0xfe000000
  28 #endif
  29
  30 #define CONFIG_PCI              1
  31 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  32 #define CONFIG_FSL_ELBC         1
  33
  34 #define CONFIG_BOARD_EARLY_INIT_F       1
  35
  36 /*
  37  * On-board devices
  38  *
  39  */
  40 #define CONFIG_83XX_CLKIN       32000000        /* in Hz */
  41
  42 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  43
  44 #define CONFIG_SYS_IMMR         0xE0000000
  45
  46 #define CONFIG_SYS_MEMTEST_START        0x00001000
  47 #define CONFIG_SYS_MEMTEST_END          0x07000000
  48
  49 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth */
  50 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count */
  51
  52 /*
  53  * Device configurations
  54  */
  55
  56 /*
  57  * DDR Setup
  58  */
  59 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  60 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  61 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  62
  63 /*
  64  * Manually set up DDR parameters, as this board does not
  65  * have the SPD connected to I2C.
  66  */
  67 #define CONFIG_SYS_DDR_SIZE     128     /* MB */
  68 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  69                                 | CSCONFIG_AP \
  70                                 | CSCONFIG_ODT_RD_NEVER \
  71                                 | CSCONFIG_ODT_WR_ALL \
  72                                 | CSCONFIG_ROW_BIT_13 \
  73                                 | CSCONFIG_COL_BIT_10)
  74                                 /* 0x80840102 */
  75
  76 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  77 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  78                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  79                                 | (3 << TIMING_CFG0_RRT_SHIFT) \
  80                                 | (2 << TIMING_CFG0_WWT_SHIFT) \
  81                                 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  82                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  83                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  84                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  85                                 /* 0x0e720802 */
  86 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  87                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  88                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  89                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  90                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  91                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  92                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  93                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  94                                 /* 0x26256222 */
  95 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  96                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
  97                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  98                                 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  99                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 100                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 101                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 102                                 /* 0x029028c7 */
 103 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
 104                                 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 105                                 /* 0x03202000 */
 106 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 107                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 108                                 | SDRAM_CFG_DBW_32)
 109                                 /* 0x43080000 */
 110 #define CONFIG_SYS_SDRAM_CFG2   0x00401000
 111 #define CONFIG_SYS_DDR_MODE     ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
 112                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 113                                 /* 0x44400232 */
 114 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 115
 116 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 117                                 /*0x02000000*/
 118 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 119                                 | DDRCDR_PZ_NOMZ \
 120                                 | DDRCDR_NZ_NOMZ \
 121                                 | DDRCDR_M_ODR)
 122                                 /* 0x73000002 */
 123
 124 /*
 125  * FLASH on the Local Bus
 126  */
 127 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 128 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 129 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 130 #define CONFIG_SYS_FLASH_SIZE           32      /* size in MB */
 131 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 132 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 133
 134 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 135                                         | BR_PS_16      /* 16 bit */ \
 136                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 137                                         | BR_V)         /* valid */
 138 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 139                                         | OR_GPCM_CSNT \
 140                                         | OR_GPCM_ACS_DIV4 \
 141                                         | OR_GPCM_SCY_5 \
 142                                         | OR_GPCM_TRLX_SET \
 143                                         | OR_GPCM_EAD)
 144                                         /* 0xfe000c55 */
 145
 146 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 147 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 148
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per dev */
 151
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 154
 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 156
 157 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 158 #define CONFIG_SYS_RAMBOOT
 159 #endif
 160
 161 #define CONFIG_SYS_INIT_RAM_LOCK        1
 162 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
 163 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 164
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 166                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 167 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 168
 169 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 170 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
 171 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 172
 173 /*
 174  * Local Bus LCRR and LBCR regs
 175  */
 176 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_3
 177 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 178
 179 #define CONFIG_SYS_LBC_LBCR     0x00040000
 180
 181 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 182
 183 /*
 184  * NAND settings
 185  */
 186 #define CONFIG_SYS_NAND_BASE            0x61000000
 187 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 188 #define CONFIG_CMD_NAND 1
 189 #define CONFIG_NAND_FSL_ELBC 1
 190 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 191
 192 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 193                                         | BR_PS_8               \
 194                                         | BR_DECC_CHK_GEN       \
 195                                         | BR_MS_FCM             \
 196                                         | BR_V) /* valid */
 197                                         /* 0x61000c21 */
 198 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 199                                         | OR_FCM_BCTLD \
 200                                         | OR_FCM_CHT \
 201                                         | OR_FCM_SCY_2 \
 202                                         | OR_FCM_RST \
 203                                         | OR_FCM_TRLX)
 204                                         /* 0xffff90ac */
 205
 206 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 207 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 208 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 209 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 210
 211 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 212 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 213
 214 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 215 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 216
 217 /* CS2 NvRAM */
 218 #define CONFIG_SYS_BR2_PRELIM   (0x60000000 \
 219                                 | BR_PS_8 \
 220                                 | BR_V)
 221                                 /* 0x60000801 */
 222 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_128KB \
 223                                 | OR_GPCM_CSNT \
 224                                 | OR_GPCM_XACS \
 225                                 | OR_GPCM_SCY_3 \
 226                                 | OR_GPCM_TRLX_SET \
 227                                 | OR_GPCM_EHTR_SET \
 228                                 | OR_GPCM_EAD)
 229                                 /* 0xfffe0937 */
 230 /* local bus read write buffer mapping SRAM@0x64000000 */
 231 #define CONFIG_SYS_BR3_PRELIM   (0x62000000 \
 232                                 | BR_PS_16 \
 233                                 | BR_V)
 234                                 /* 0x62001001 */
 235
 236 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32MB \
 237                                 | OR_GPCM_CSNT \
 238                                 | OR_GPCM_XACS \
 239                                 | OR_GPCM_SCY_15 \
 240                                 | OR_GPCM_TRLX_SET \
 241                                 | OR_GPCM_EHTR_SET \
 242                                 | OR_GPCM_EAD)
 243                                 /* 0xfe0009f7 */
 244
 245 /*
 246  * Serial Port
 247  */
 248 #define CONFIG_CONS_INDEX       1
 249 #define CONFIG_SYS_NS16550_SERIAL
 250 #define CONFIG_SYS_NS16550_REG_SIZE     1
 251 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 252
 253 #define CONFIG_SYS_BAUDRATE_TABLE       \
 254         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 255
 256 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 257 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 258
 259 #if defined(CONFIG_PCI)
 260 /*
 261  * General PCI
 262  * Addresses are mapped 1-1.
 263  */
 264 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 265 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 266 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 267 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 268 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 269 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 270 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 271 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 272 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 273
 274 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 275 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 276 #endif
 277
 278 /*
 279  * TSEC
 280  */
 281 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 282
 283
 284 #define CONFIG_TSEC1
 285 #ifdef CONFIG_TSEC1
 286 #define CONFIG_HAS_ETH0
 287 #define CONFIG_TSEC1_NAME       "TSEC1"
 288 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 289 #define TSEC1_PHY_ADDR          0x01
 290 #define TSEC1_FLAGS             0
 291 #define TSEC1_PHYIDX            0
 292 #endif
 293
 294 /* Options are: TSEC[0-1] */
 295 #define CONFIG_ETHPRIME                 "TSEC1"
 296
 297 /*
 298  * Environment
 299  */
 300 #define CONFIG_ENV_IS_IN_FLASH  1
 301 #define CONFIG_ENV_ADDR         \
 302                         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 303 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 304 #define CONFIG_ENV_SIZE         0x4000
 305 /* Address and size of Redundant Environment Sector */
 306 #define CONFIG_ENV_OFFSET_REDUND        \
 307                         (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 308 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 309
 310 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 311 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 312
 313 /*
 314  * BOOTP options
 315  */
 316 #define CONFIG_BOOTP_BOOTFILESIZE
 317 #define CONFIG_BOOTP_BOOTPATH
 318 #define CONFIG_BOOTP_GATEWAY
 319 #define CONFIG_BOOTP_HOSTNAME
 320
 321 /*
 322  * Command line configuration.
 323  */
 324 #define CONFIG_CMD_DHCP
 325 #define CONFIG_CMD_MII
 326 #define CONFIG_CMD_PING
 327 #define CONFIG_CMD_PCI
 328
 329 #define CONFIG_CMDLINE_EDITING 1
 330 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
 331
 332 /*
 333  * Miscellaneous configurable options
 334  */
 335 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 336 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 337 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 338
 339 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 340 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 341 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
 342
 343 /*
 344  * For booting Linux, the board info and command line data
 345  * have to be in the first 256 MB of memory, since this is
 346  * the maximum mapped by the Linux kernel during initialization.
 347  */
 348                                 /* Initial Memory map for Linux*/
 349 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 350
 351 /* 0x64050000 */
 352 #define CONFIG_SYS_HRCW_LOW (\
 353         0x20000000 /* reserved, must be set */ |\
 354         HRCWL_DDRCM |\
 355         HRCWL_CSB_TO_CLKIN_4X1 | \
 356         HRCWL_CORE_TO_CSB_2_5X1)
 357
 358 /* 0xa0600004 */
 359 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
 360         HRCWH_PCI_ARBITER_ENABLE | \
 361         HRCWH_CORE_ENABLE | \
 362         HRCWH_FROM_0X00000100 | \
 363         HRCWH_BOOTSEQ_DISABLE |\
 364         HRCWH_SW_WATCHDOG_DISABLE |\
 365         HRCWH_ROM_LOC_LOCAL_16BIT | \
 366         HRCWH_TSEC1M_IN_MII | \
 367         HRCWH_BIG_ENDIAN | \
 368         HRCWH_LALE_EARLY)
 369
 370 /* System IO Config */
 371 #define CONFIG_SYS_SICRH        (0x01000000 | \
 372                                 SICRH_ETSEC2_B | \
 373                                 SICRH_ETSEC2_C | \
 374                                 SICRH_ETSEC2_D | \
 375                                 SICRH_ETSEC2_E | \
 376                                 SICRH_ETSEC2_F | \
 377                                 SICRH_ETSEC2_G | \
 378                                 SICRH_TSOBI1 | \
 379                                 SICRH_TSOBI2)
 380                                 /* 0x010fff03 */
 381 #define CONFIG_SYS_SICRL        (SICRL_LBC | \
 382                                 SICRL_SPI_A | \
 383                                 SICRL_SPI_B | \
 384                                 SICRL_SPI_C | \
 385                                 SICRL_SPI_D | \
 386                                 SICRL_ETSEC2_A)
 387                                 /* 0x33fc0003) */
 388
 389 #define CONFIG_SYS_HID0_INIT    0x000000000
 390 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 391                                  HID0_ENABLE_INSTRUCTION_CACHE)
 392
 393 #define CONFIG_SYS_HID2 HID2_HBE
 394
 395 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 396
 397 /* DDR @ 0x00000000 */
 398 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
 399 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 400                                 | BATU_BL_256M \
 401                                 | BATU_VS \
 402                                 | BATU_VP)
 403
 404 #if defined(CONFIG_PCI)
 405 /* PCI @ 0x80000000 */
 406 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
 407 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 408                                 | BATU_BL_256M \
 409                                 | BATU_VS \
 410                                 | BATU_VP)
 411 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 412                                 | BATL_PP_RW \
 413                                 | BATL_CACHEINHIBIT \
 414                                 | BATL_GUARDEDSTORAGE)
 415 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 416                                 | BATU_BL_256M \
 417                                 | BATU_VS \
 418                                 | BATU_VP)
 419 #else
 420 #define CONFIG_SYS_IBAT1L       (0)
 421 #define CONFIG_SYS_IBAT1U       (0)
 422 #define CONFIG_SYS_IBAT2L       (0)
 423 #define CONFIG_SYS_IBAT2U       (0)
 424 #endif
 425
 426 /* PCI2 not supported on 8313 */
 427 #define CONFIG_SYS_IBAT3L       (0)
 428 #define CONFIG_SYS_IBAT3U       (0)
 429 #define CONFIG_SYS_IBAT4L       (0)
 430 #define CONFIG_SYS_IBAT4U       (0)
 431
 432 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 433 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 434                                 | BATL_PP_RW \
 435                                 | BATL_CACHEINHIBIT \
 436                                 | BATL_GUARDEDSTORAGE)
 437 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 438                                 | BATU_BL_256M \
 439                                 | BATU_VS \
 440                                 | BATU_VP)
 441
 442 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 443 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 444 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 445
 446 /*  FPGA, SRAM, NAND @ 0x60000000 */
 447 #define CONFIG_SYS_IBAT7L       (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_IBAT7U       (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 449
 450 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 451 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 452 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 453 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 454 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 455 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 456 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 457 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 458 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 459 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 460 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 461 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 462 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 463 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 464 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 465 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 466
 467 #define CONFIG_NETDEV           eth0
 468
 469 #define CONFIG_HOSTNAME         ve8313
 470 #define CONFIG_UBOOTPATH        ve8313/u-boot.bin
 471
 472 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 473 #define CONFIG_BAUDRATE         115200
 474
 475 #define CONFIG_EXTRA_ENV_SETTINGS \
 476         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 477         "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"                 \
 478         "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"                    \
 479         "u-boot_addr_r=100000\0"                                        \
 480         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 481         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)        \
 482                 " +${filesize};"        \
 483         "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 484         "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 485         " ${filesize};"                                                 \
 486         "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
 487
 488 #endif  /* __CONFIG_H */