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   1 /*
   2  * Copyright (C) 2016 NXP Semiconductors
   3  *
   4  * Configuration settings for the i.MX7S Warp board.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __WARP7_CONFIG_H
  10 #define __WARP7_CONFIG_H
  11
  12 #include "mx7_common.h"
  13 #include <imximage.h>
  14
  15 #define PHYS_SDRAM_SIZE                 SZ_512M
  16
  17 #define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
  18
  19 /* Size of malloc() pool */
  20 #define CONFIG_SYS_MALLOC_LEN           (35 * SZ_1M)
  21
  22 /* MMC Config*/
  23 #define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
  24 #define CONFIG_SUPPORT_EMMC_BOOT
  25 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  26 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
  27
  28 /* Switch on SERIAL_TAG */
  29 #define CONFIG_SERIAL_TAG
  30
  31 #define CONFIG_DFU_ENV_SETTINGS \
  32         "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
  33
  34 #define CONFIG_EXTRA_ENV_SETTINGS \
  35         CONFIG_DFU_ENV_SETTINGS \
  36         "script=boot.scr\0" \
  37         "script_signed=boot.scr.imx-signed\0" \
  38         "image=zImage\0" \
  39         "console=ttymxc0\0" \
  40         "ethact=usb_ether\0" \
  41         "fdt_high=0xffffffff\0" \
  42         "initrd_high=0xffffffff\0" \
  43         "fdt_file=imx7s-warp.dtb\0" \
  44         "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \
  45         "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \
  46         "boot_fdt=try\0" \
  47         "ip_dyn=yes\0" \
  48         "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  49         "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  50         "rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \
  51         "finduuid=part uuid mmc 0:${rootpart} uuid\0" \
  52         "mmcargs=setenv bootargs console=${console},${baudrate} " \
  53                 "root=PARTUUID=${uuid} rootwait rw\0" \
  54         "ivt_offset=" __stringify(BOOTROM_IVT_HDR_OFFSET)"\0"\
  55         "warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \
  56         "loadbootscript=" \
  57                 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  58         "bootscript=echo Running bootscript from mmc ...; " \
  59                 "source\0" \
  60         "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  61         "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  62         "mmcboot=echo Booting from mmc ...; " \
  63                 "run finduuid; " \
  64                 "run mmcargs; " \
  65                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  66                         "if run loadfdt; then " \
  67                                 "bootz ${loadaddr} - ${fdt_addr}; " \
  68                         "else " \
  69                                 "if test ${boot_fdt} = try; then " \
  70                                         "bootz; " \
  71                                 "else " \
  72                                         "echo WARN: Cannot load the DT; " \
  73                                 "fi; " \
  74                         "fi; " \
  75                 "else " \
  76                         "bootz; " \
  77                 "fi;\0" \
  78
  79 #define CONFIG_BOOTCOMMAND \
  80            "mmc dev ${mmcdev};" \
  81            "mmc dev ${mmcdev}; if mmc rescan; then " \
  82                    "if run loadbootscript; then " \
  83                            "run bootscript; " \
  84                    "else " \
  85                            "if run loadimage; then " \
  86                                    "run mmcboot; " \
  87                            "fi; " \
  88                    "fi; " \
  89            "fi"
  90
  91 #define CONFIG_SYS_MEMTEST_START        0x80000000
  92 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + 0x20000000)
  93
  94 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
  95 #define CONFIG_SYS_HZ                   1000
  96
  97 /* Physical Memory Map */
  98 #define CONFIG_NR_DRAM_BANKS            1
  99 #define PHYS_SDRAM                      MMDC0_ARB_BASE_ADDR
 100
 101 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM
 102 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
 103 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
 104
 105 #define CONFIG_SYS_INIT_SP_OFFSET \
 106         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 107 #define CONFIG_SYS_INIT_SP_ADDR \
 108         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 109
 110 /* I2C configs */
 111 #define CONFIG_SYS_I2C
 112 #define CONFIG_SYS_I2C_MXC
 113 #define CONFIG_SYS_I2C_MXC_I2C1
 114 #define CONFIG_SYS_I2C_SPEED            100000
 115
 116 /* PMIC */
 117 #define CONFIG_POWER
 118 #define CONFIG_POWER_I2C
 119 #define CONFIG_POWER_PFUZE3000
 120 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
 121
 122 /* environment organization */
 123 #define CONFIG_ENV_SIZE                 SZ_8K
 124
 125 #define CONFIG_ENV_OFFSET               (8 * SZ_64K)
 126 #define CONFIG_SYS_FSL_USDHC_NUM        1
 127
 128 #define CONFIG_SYS_MMC_ENV_DEV          0
 129 #define CONFIG_SYS_MMC_ENV_PART         0
 130
 131 /* USB Configs */
 132 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 133
 134 #define CONFIG_MXC_USB_PORTSC           (PORT_PTS_UTMI | PORT_PTS_PTW)
 135 #define CONFIG_MXC_USB_FLAGS            0
 136 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
 137
 138 #define CONFIG_IMX_THERMAL
 139
 140 #define CONFIG_USBD_HS
 141
 142 /* USB Device Firmware Update support */
 143 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    SZ_16M
 144 #define DFU_DEFAULT_POLL_TIMEOUT        300
 145
 146 #define CONFIG_USBNET_DEV_ADDR          "de:ad:be:af:00:01"
 147
 148 /* Environment variable name to represent HAB enable state */
 149 #define HAB_ENABLED_ENVNAME             "hab_enabled"
 150
 151 #endif