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   1 /*
   2  * Configuration for Xilinx ZynqMP zcu111
   3  *
   4  * (C) Copyright 2017 Xilinx, Inc.
   5  * Michal Simek <michal.simek@xilinx.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_ZYNQMP_ZCU111_H
  11 #define __CONFIG_ZYNQMP_ZCU111_H
  12
  13 #define CONFIG_ZYNQ_SDHCI1
  14 #define CONFIG_SYS_I2C_MAX_HOPS         1
  15 #define CONFIG_SYS_NUM_I2C_BUSES        21
  16 #define CONFIG_SYS_I2C_BUSES    { \
  17                                 {0, {I2C_NULL_HOP} }, \
  18                                 {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
  19                                 {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
  20                                 {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
  21                                 {0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \
  22                                 {1, {I2C_NULL_HOP} }, \
  23                                 {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
  24                                 {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
  25                                 {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
  26                                 {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
  27                                 {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
  28                                 {1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \
  29                                 {1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \
  30                                 {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
  31                                 {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
  32                                 {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
  33                                 {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
  34                                 {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
  35                                 {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
  36                                 {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
  37                                 {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
  38                                 }
  39
  40 #define CONFIG_PCA953X
  41
  42 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
  43
  44 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  45 #define CONFIG_ZYNQ_EEPROM_BUS          5
  46 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x54
  47
  48 #include <configs/xilinx_zynqmp.h>
  49
  50 #endif /* __CONFIG_ZYNQMP_ZCU111_H */