git.sur5r.net Git - u-boot/blob - include/gdsys_fpga.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2010
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  */
   6
   7 #ifndef __GDSYS_FPGA_H
   8 #define __GDSYS_FPGA_H
   9
  10 int init_func_fpga(void);
  11
  12 enum {
  13         FPGA_STATE_DONE_FAILED = 1 << 0,
  14         FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  15         FPGA_STATE_PLATFORM = 1 << 2,
  16 };
  17
  18 int get_fpga_state(unsigned dev);
  19
  20 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
  21 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
  22
  23 extern struct ihs_fpga *fpga_ptr[];
  24
  25 #define FPGA_SET_REG(ix, fld, val) \
  26         fpga_set_reg((ix), \
  27                      &fpga_ptr[ix]->fld, \
  28                      offsetof(struct ihs_fpga, fld), \
  29                      val)
  30
  31 #define FPGA_GET_REG(ix, fld, val) \
  32         fpga_get_reg((ix), \
  33                      &fpga_ptr[ix]->fld, \
  34                      offsetof(struct ihs_fpga, fld), \
  35                      val)
  36
  37 struct ihs_gpio {
  38         u16 read;
  39         u16 clear;
  40         u16 set;
  41 };
  42
  43 struct ihs_i2c {
  44         u16 interrupt_status;
  45         u16 interrupt_enable;
  46         u16 write_mailbox_ext;
  47         u16 write_mailbox;
  48         u16 read_mailbox_ext;
  49         u16 read_mailbox;
  50 };
  51
  52 struct ihs_osd {
  53         u16 version;
  54         u16 features;
  55         u16 control;
  56         u16 xy_size;
  57         u16 xy_scale;
  58         u16 x_pos;
  59         u16 y_pos;
  60 };
  61
  62 struct ihs_mdio {
  63         u16 control;
  64         u16 address_data;
  65         u16 rx_data;
  66 };
  67
  68 struct ihs_io_ep {
  69         u16 transmit_data;
  70         u16 rx_tx_control;
  71         u16 receive_data;
  72         u16 rx_tx_status;
  73         u16 reserved;
  74         u16 device_address;
  75         u16 target_address;
  76 };
  77
  78 #ifdef CONFIG_NEO
  79 struct ihs_fpga {
  80         u16 reflection_low;     /* 0x0000 */
  81         u16 versions;           /* 0x0002 */
  82         u16 fpga_features;      /* 0x0004 */
  83         u16 fpga_version;       /* 0x0006 */
  84         u16 reserved_0[8187];   /* 0x0008 */
  85         u16 reflection_high;    /* 0x3ffe */
  86 };
  87 #endif
  88
  89 #ifdef CONFIG_IO
  90 struct ihs_fpga {
  91         u16 reflection_low;     /* 0x0000 */
  92         u16 versions;           /* 0x0002 */
  93         u16 fpga_features;      /* 0x0004 */
  94         u16 fpga_version;       /* 0x0006 */
  95         u16 reserved_0[5];      /* 0x0008 */
  96         u16 quad_serdes_reset;  /* 0x0012 */
  97         u16 reserved_1[8181];   /* 0x0014 */
  98         u16 reflection_high;    /* 0x3ffe */
  99 };
 100 #endif
 101
 102 #ifdef CONFIG_IO64
 103 struct ihs_fpga_channel {
 104         u16 status_int;
 105         u16 config_int;
 106         u16 switch_connect_config;
 107         u16 tx_destination;
 108 };
 109
 110 struct ihs_fpga_hicb {
 111         u16 status_int;
 112         u16 config_int;
 113 };
 114
 115 struct ihs_fpga {
 116         u16 reflection_low;     /* 0x0000 */
 117         u16 versions;           /* 0x0002 */
 118         u16 fpga_features;      /* 0x0004 */
 119         u16 fpga_version;       /* 0x0006 */
 120         u16 reserved_0[5];      /* 0x0008 */
 121         u16 quad_serdes_reset;  /* 0x0012 */
 122         u16 reserved_1[502];    /* 0x0014 */
 123         struct ihs_fpga_channel ch[32];         /* 0x0400 */
 124         struct ihs_fpga_channel hicb_ch[32];    /* 0x0500 */
 125         u16 reserved_2[7487];   /* 0x0580 */
 126         u16 reflection_high;    /* 0x3ffe */
 127 };
 128 #endif
 129
 130 #ifdef CONFIG_IOCON
 131 struct ihs_fpga {
 132         u16 reflection_low;     /* 0x0000 */
 133         u16 versions;           /* 0x0002 */
 134         u16 fpga_version;       /* 0x0004 */
 135         u16 fpga_features;      /* 0x0006 */
 136         u16 reserved_0[1];      /* 0x0008 */
 137         u16 top_interrupt;      /* 0x000a */
 138         u16 reserved_1[4];      /* 0x000c */
 139         struct ihs_gpio gpio;   /* 0x0014 */
 140         u16 mpc3w_control;      /* 0x001a */
 141         u16 reserved_2[2];      /* 0x001c */
 142         struct ihs_io_ep ep;    /* 0x0020 */
 143         u16 reserved_3[9];      /* 0x002e */
 144         struct ihs_i2c i2c0;    /* 0x0040 */
 145         u16 reserved_4[10];     /* 0x004c */
 146         u16 mc_int;             /* 0x0060 */
 147         u16 mc_int_en;          /* 0x0062 */
 148         u16 mc_status;          /* 0x0064 */
 149         u16 mc_control;         /* 0x0066 */
 150         u16 mc_tx_data;         /* 0x0068 */
 151         u16 mc_tx_address;      /* 0x006a */
 152         u16 mc_tx_cmd;          /* 0x006c */
 153         u16 mc_res;             /* 0x006e */
 154         u16 mc_rx_cmd_status;   /* 0x0070 */
 155         u16 mc_rx_data;         /* 0x0072 */
 156         u16 reserved_5[69];     /* 0x0074 */
 157         u16 reflection_high;    /* 0x00fe */
 158         struct ihs_osd osd0;    /* 0x0100 */
 159         u16 reserved_6[889];    /* 0x010e */
 160         u16 videomem0[2048];    /* 0x0800 */
 161 };
 162 #endif
 163
 164 #if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
 165 struct ihs_fpga {
 166         u16 reflection_low;     /* 0x0000 */
 167         u16 versions;           /* 0x0002 */
 168         u16 fpga_version;       /* 0x0004 */
 169         u16 fpga_features;      /* 0x0006 */
 170         u16 reserved_0[1];      /* 0x0008 */
 171         u16 top_interrupt;      /* 0x000a */
 172         u16 reserved_1[2];      /* 0x000c */
 173         u16 control;            /* 0x0010 */
 174         u16 extended_control;   /* 0x0012 */
 175         struct ihs_gpio gpio;   /* 0x0014 */
 176         u16 mpc3w_control;      /* 0x001a */
 177         u16 reserved_2[2];      /* 0x001c */
 178         struct ihs_io_ep ep;    /* 0x0020 */
 179         u16 reserved_3[9];      /* 0x002e */
 180         struct ihs_i2c i2c0;    /* 0x0040 */
 181         u16 reserved_4[10];     /* 0x004c */
 182         u16 mc_int;             /* 0x0060 */
 183         u16 mc_int_en;          /* 0x0062 */
 184         u16 mc_status;          /* 0x0064 */
 185         u16 mc_control;         /* 0x0066 */
 186         u16 mc_tx_data;         /* 0x0068 */
 187         u16 mc_tx_address;      /* 0x006a */
 188         u16 mc_tx_cmd;          /* 0x006c */
 189         u16 mc_res;             /* 0x006e */
 190         u16 mc_rx_cmd_status;   /* 0x0070 */
 191         u16 mc_rx_data;         /* 0x0072 */
 192         u16 reserved_5[69];     /* 0x0074 */
 193         u16 reflection_high;    /* 0x00fe */
 194         struct ihs_osd osd0;    /* 0x0100 */
 195 #ifdef CONFIG_SYS_OSD_DH
 196         u16 reserved_6[57];     /* 0x010e */
 197         struct ihs_osd osd1;    /* 0x0180 */
 198         u16 reserved_7[9];      /* 0x018e */
 199         struct ihs_i2c i2c1;    /* 0x01a0 */
 200         u16 reserved_8[1834];   /* 0x01ac */
 201         u16 videomem0[2048];    /* 0x1000 */
 202         u16 videomem1[2048];    /* 0x2000 */
 203 #else
 204         u16 reserved_6[889];    /* 0x010e */
 205         u16 videomem0[2048];    /* 0x0800 */
 206 #endif
 207 };
 208 #endif
 209
 210 #ifdef CONFIG_STRIDER_CPU
 211 struct ihs_fpga {
 212         u16 reflection_low;     /* 0x0000 */
 213         u16 versions;           /* 0x0002 */
 214         u16 fpga_version;       /* 0x0004 */
 215         u16 fpga_features;      /* 0x0006 */
 216         u16 reserved_0[1];      /* 0x0008 */
 217         u16 top_interrupt;      /* 0x000a */
 218         u16 reserved_1[3];      /* 0x000c */
 219         u16 extended_control;   /* 0x0012 */
 220         struct ihs_gpio gpio;   /* 0x0014 */
 221         u16 mpc3w_control;      /* 0x001a */
 222         u16 reserved_2[2];      /* 0x001c */
 223         struct ihs_io_ep ep;    /* 0x0020 */
 224         u16 reserved_3[9];      /* 0x002e */
 225         u16 mc_int;             /* 0x0040 */
 226         u16 mc_int_en;          /* 0x0042 */
 227         u16 mc_status;          /* 0x0044 */
 228         u16 mc_control;         /* 0x0046 */
 229         u16 mc_tx_data;         /* 0x0048 */
 230         u16 mc_tx_address;      /* 0x004a */
 231         u16 mc_tx_cmd;          /* 0x004c */
 232         u16 mc_res;             /* 0x004e */
 233         u16 mc_rx_cmd_status;   /* 0x0050 */
 234         u16 mc_rx_data;         /* 0x0052 */
 235         u16 reserved_4[62];     /* 0x0054 */
 236         struct ihs_i2c i2c0;    /* 0x00d0 */
 237 };
 238 #endif
 239
 240 #ifdef CONFIG_STRIDER_CON
 241 struct ihs_fpga {
 242         u16 reflection_low;     /* 0x0000 */
 243         u16 versions;           /* 0x0002 */
 244         u16 fpga_version;       /* 0x0004 */
 245         u16 fpga_features;      /* 0x0006 */
 246         u16 reserved_0[1];      /* 0x0008 */
 247         u16 top_interrupt;      /* 0x000a */
 248         u16 reserved_1[4];      /* 0x000c */
 249         struct ihs_gpio gpio;   /* 0x0014 */
 250         u16 mpc3w_control;      /* 0x001a */
 251         u16 reserved_2[2];      /* 0x001c */
 252         struct ihs_io_ep ep;    /* 0x0020 */
 253         u16 reserved_3[9];      /* 0x002e */
 254         struct ihs_i2c i2c0;    /* 0x0040 */
 255         u16 reserved_4[10];     /* 0x004c */
 256         u16 mc_int;             /* 0x0060 */
 257         u16 mc_int_en;          /* 0x0062 */
 258         u16 mc_status;          /* 0x0064 */
 259         u16 mc_control;         /* 0x0066 */
 260         u16 mc_tx_data;         /* 0x0068 */
 261         u16 mc_tx_address;      /* 0x006a */
 262         u16 mc_tx_cmd;          /* 0x006c */
 263         u16 mc_res;             /* 0x006e */
 264         u16 mc_rx_cmd_status;   /* 0x0070 */
 265         u16 mc_rx_data;         /* 0x0072 */
 266         u16 reserved_5[70];     /* 0x0074 */
 267         struct ihs_osd osd0;    /* 0x0100 */
 268         u16 reserved_6[889];    /* 0x010e */
 269         u16 videomem0[2048];    /* 0x0800 */
 270 };
 271 #endif
 272
 273 #ifdef CONFIG_DLVISION_10G
 274 struct ihs_fpga {
 275         u16 reflection_low;     /* 0x0000 */
 276         u16 versions;           /* 0x0002 */
 277         u16 fpga_version;       /* 0x0004 */
 278         u16 fpga_features;      /* 0x0006 */
 279         u16 reserved_0[10];     /* 0x0008 */
 280         u16 extended_interrupt; /* 0x001c */
 281         u16 reserved_1[29];     /* 0x001e */
 282         u16 mpc3w_control;      /* 0x0058 */
 283         u16 reserved_2[3];      /* 0x005a */
 284         struct ihs_i2c i2c0;    /* 0x0060 */
 285         u16 reserved_3[2];      /* 0x006c */
 286         struct ihs_i2c i2c1;    /* 0x0070 */
 287         u16 reserved_4[194];    /* 0x007c */
 288         struct ihs_osd osd0;    /* 0x0200 */
 289         u16 reserved_5[761];    /* 0x020e */
 290         u16 videomem0[2048];    /* 0x0800 */
 291 };
 292 #endif
 293
 294 #endif