clk: clk_stm32h7: Fix prescaler for Domain 3

d1cfgr register was used to calculate the domain 3
prescaler value instead of d3cfgr.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 92db71431e45791cac86f83c1c43f7a0d9c10d2d..9ee2e2e999a295950c89f8ba89c193f8494fdd2c 100644 (file)
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -635,7 +635,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
        struct stm32_rcc_regs *regs = priv->rcc_base;
        ulong sysclk = 0;
        u32 gate_offset;
-       u32 d1cfgr;
+       u32 d1cfgr, d3cfgr;
        /* prescaler table lookups for clock computation */
        u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
        u8 source, idx;
@@ -712,9 +712,10 @@ static ulong stm32_clk_get_rate(struct clk *clk)
                break;
 
        case RCC_APB4ENR:
-               if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
+               d3cfgr = readl(&regs->d3cfgr);
+               if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
                        /* get D3 domain APB4 prescaler */
-                       idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
+                       idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
                              RCC_D3CFGR_D3PPRE_SHIFT;
                        sysclk = sysclk / prescaler_table[idx];
                }