Flattened Image Tree. FIT is formally a FDT, which can include
images of various types (kernel, FDT blob, ramdisk, etc.)
in a single blob. To boot this new uImage structure,
- pass the the address of the blob to the "bootm" command.
+ pass the address of the blob to the "bootm" command.
config FIT_VERBOSE
bool "Display verbose messages on FIT boot"
VERSION = 2015
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
CONFIG_ARM_ERRATA_742230
CONFIG_ARM_ERRATA_743622
CONFIG_ARM_ERRATA_751472
- CONFIG_ARM_ERRATA_794072
CONFIG_ARM_ERRATA_761320
+ CONFIG_ARM_ERRATA_773022
+ CONFIG_ARM_ERRATA_774769
+ CONFIG_ARM_ERRATA_794072
If set, the workarounds for these ARM errata are applied early
during U-Boot startup. Note that these options force the
define this to a list of base addresses for each (supported)
port. See e.g. include/configs/versatile.h
- CONFIG_PL011_SERIAL_RLCR
-
- Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
- have separate receive and transmit line control registers. Set
- this variable to initialize the extra register.
-
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-
- On some platforms (e.g. U8500) U-Boot is loaded by a second stage
- boot loader that has already initialized the UART. Define this
- variable to flush the UART at init time.
-
CONFIG_SERIAL_HW_FLOW_CONTROL
Define this variable to enable hw flow control in serial driver.
- drivers/i2c/i2c_mxc.c
- activate this driver with CONFIG_SYS_I2C_MXC
+ - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1
+ - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2
+ - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
+ - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
- define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
- define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
- define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
- define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
- define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
+ - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED
+ - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE
If those defines are not set, default value is 100000
for speed, and 0 for slave.
- - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3
- - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4
- drivers/i2c/rcar_i2c.c:
- activate this driver with CONFIG_SYS_I2C_RCAR
else
found = 1;
+ /* provide hint if there are more devices in
+ * this group to enumerate */
+ if (1 < specs[type].max_dev)
+ *more = 1;
+
} else {
for (i = 0; i < specs[type].max_dev; i++)
if (di->cookie == (void *)get_dev(specs[type].name, i)) {
choice
prompt "Target select"
- default ARCH_VERSATILE
+ default TARGET_HIKEY
config ARCH_AT91
bool "Atmel AT91"
bool "Support edb93xx"
select CPU_ARM920T
-config TARGET_SCB9328
- bool "Support scb9328"
- select CPU_ARM920T
-
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
bool "Support mx25pdk"
select CPU_ARM926EJS
-config TARGET_TX25
- bool "Support tx25"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
config TARGET_ZMX25
bool "Support zmx25"
select CPU_ARM926EJS
select CPU_ARM926EJS
select SUPPORT_SPL
-config TARGET_IMX27LITE
- bool "Support imx27lite"
- select CPU_ARM926EJS
-
-config TARGET_MAGNESIUM
- bool "Support magnesium"
- select CPU_ARM926EJS
-
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
select CPU_ARM926EJS
select CPU_ARM926EJS
select SUPPORT_SPL
-config ARCH_NOMADIK
- bool "ST-Ericsson Nomadik"
- select CPU_ARM926EJS
-
config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
select CPU_ARM926EJS
select SUPPORT_SPL
-config ARCH_VERSATILE
- bool "ARM Ltd. Versatile family"
- select CPU_ARM926EJS
-
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
select CPU_ARM1136
-config TARGET_QONG
- bool "Support qong"
- select CPU_ARM1136
-
config TARGET_MX31ADS
bool "Support mx31ads"
select CPU_ARM1136
select CPU_ARM1136
select SUPPORT_SPL
-config TARGET_TT01
- bool "Support tt01"
- select CPU_ARM1136
-
-config TARGET_IMX31_LITEKIT
- bool "Support imx31_litekit"
- select CPU_ARM1136
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
select DM_SERIAL
select DM_GPIO
+config TARGET_AM335X_SL50
+ bool "Support am335x_sl50"
+ select CPU_V7
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select CPU_V7
select CPU_V7
select SUPPORT_SPL
+config ARCH_MX7
+ bool "Freescale MX7"
+ select CPU_V7
+
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
select CPU_V7
select SUPPORT_SPL
-config TARGET_IMA3_MX53
- bool "Support ima3-mx53"
- select CPU_V7
-
config TARGET_MX51EVK
bool "Support mx51evk"
select CPU_V7
bool "Support mx53smd"
select CPU_V7
-config TARGET_MX51_EFIKAMX
- bool "Support mx51_efikamx"
- select CPU_V7
-
-config TARGET_VISION2
- bool "Support vision2"
- select CPU_V7
-
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
select USB_STORAGE
select USB_KEYBOARD
-config TARGET_SNOWBALL
- bool "Support snowball"
- select CPU_V7
-
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
-config TARGET_U8500_HREF
- bool "Support u8500_href"
- select CPU_V7
-
config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
bool "Support Colibri VF50/61"
select CPU_V7
+config TARGET_PCM052
+ bool "Support pcm-052"
+ select CPU_V7
+
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7
select ARM64
select SEMIHOSTING
+config TARGET_VEXPRESS64_BASE_FVP_DRAM
+ bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
+ select ARM64
+ help
+ This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
+ the default config to allow the user to load the images directly into
+ DRAM using model parameters rather than by using semi-hosting to load
+ the files from the host filesystem.
+
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
bool "Support ls1021aqds"
select CPU_V7
select SUPPORT_SPL
-
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
select SUPPORT_SPL
-config TARGET_BALLOON3
- bool "Support balloon3"
- select CPU_PXA
-
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
-config TARGET_PALMLD
- bool "Support palmld"
- select CPU_PXA
-
-config TARGET_PALMTC
- bool "Support palmtc"
- select CPU_PXA
-
-config TARGET_PALMTREO680
- bool "Support palmtreo680"
- select CPU_PXA
- select SUPPORT_SPL
-
-config TARGET_PXA255_IDP
- bool "Support pxa255_idp"
- select CPU_PXA
-
-config TARGET_TRIZEPSIV
- bool "Support trizepsiv"
- select CPU_PXA
-
-config TARGET_VPAC270
- bool "Support vpac270"
- select CPU_PXA
- select SUPPORT_SPL
-
-config TARGET_XAENIAX
- bool "Support xaeniax"
- select CPU_PXA
-
-config TARGET_ZIPITZ2
- bool "Support zipitz2"
- select CPU_PXA
-
-config TARGET_LP8X4X
- bool "Support lp8x4x"
- select CPU_PXA
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
-config TARGET_JORNADA
- bool "Support jornada"
- select CPU_SA1100
-
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CPU_V7
source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/cpu/armv7/mx7/Kconfig"
+
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
-source "arch/arm/mach-nomadik/Kconfig"
-
source "arch/arm/cpu/armv7/omap3/Kconfig"
source "arch/arm/cpu/armv7/omap4/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
-source "arch/arm/mach-versatile/Kconfig"
-
source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
-source "board/balloon3/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/creative/xfi3/Kconfig"
-source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
-source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/vf610twr/Kconfig"
-source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
-source "board/hale/tt01/Kconfig"
source "board/hisilicon/hikey/Kconfig"
-source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/jornada/Kconfig"
-source "board/karo/tx25/Kconfig"
-source "board/logicpd/imx27lite/Kconfig"
-source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/palmld/Kconfig"
-source "board/palmtc/Kconfig"
-source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
+source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
-source "board/pxa255_idp/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
-source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
-source "board/st-ericsson/snowball/Kconfig"
-source "board/st-ericsson/u8500/Kconfig"
source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
+source "board/tcl/sl50/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
-source "board/trizepsiv/Kconfig"
source "board/technologic/ts4800/Kconfig"
-source "board/ttcontrol/vision2/Kconfig"
-source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
-source "board/xaeniax/Kconfig"
-source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"
machine-$(CONFIG_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARMADA_XP) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
-machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
-machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
libs-y += arch/arm/imx-common/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
libs-y += arch/arm/imx-common/
endif
endif
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
- fout = fref * m_div;
- if (val & CLK_HCLK_PLL_FEEDBACK) {
- fcco = fout;
+ fcco = fref * m_div;
+ fout = fcco;
+ if (val & CLK_HCLK_PLL_FEEDBACK)
+ fcco *= p_div;
+ else
do_div(fout, p_div);
- } else
- fcco = fout * p_div;
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;
void lpc32xx_dma_init(void)
{
/* Enable DMA interface */
- writel(DMA_CLK_ENABLE, &clk->dmaclk_ctrl);
-
+ writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
}
void lpc32xx_mac_init(void)
return 0;
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ /* 1-bit HW ECC */
+ printf("Switching to 1-bit HW ECC\n");
+ fsmc_nand_switch_ecc(1);
+ } else if (strncmp(argv[1], "bch4", 2) == 0) {
+ /* 4-bit SW ECC BCH4 */
+ printf("Switching to 4-bit SW ECC (BCH4)\n");
+ fsmc_nand_switch_ecc(4);
+ } else {
+ goto usage;
+ }
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 0, do_switch_ecc,
+ "switch NAND ECC calculation algorithm",
+ "hw|bch4 - Switch between NAND hardware 1-bit HW and"
+ " 4-bit SW BCH\n"
+);
+#endif
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_VF610) += vf610/
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
+#include <config.h>
+#include <fsl_wdog.h>
#include "fsl_epu.h"
asm volatile("sev");
}
#endif
+
+void reset_cpu(ulong addr)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ clrbits_be16(&wdog->wcr, WCR_SRS);
+
+ while (1) {
+ /*
+ * Let the watchdog trigger
+ */
+ }
+}
config TARGET_ARISTAINETOS
bool "aristainetos"
- select CPU_V7
config TARGET_ARISTAINETOS2
bool "aristainetos2"
- select CPU_V7
config TARGET_ARISTAINETOS2B
bool "Support aristainetos2-revB"
- select CPU_V7
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
- select CPU_V7
config TARGET_CM_FX6
bool "CM-FX6"
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
- select CPU_V7
config TARGET_GW_VENTANA
bool "gw_ventana"
- select CPU_V7
select SUPPORT_SPL
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
- select CPU_V7
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
- select CPU_V7
select SUPPORT_SPL
config TARGET_MX6QARM2
bool "mx6qarm2"
- select CPU_V7
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
- select CPU_V7
select DM
select DM_THERMAL
config TARGET_MX6SABRESD
bool "mx6sabresd"
- select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6SLEVK
bool "mx6slevk"
- select CPU_V7
select SUPPORT_SPL
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
- select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
+config TARGET_MX6UL_9X9_EVK
+ bool "mx6ul_9x9_evk"
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
select MX6UL
- select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_NITROGEN6X
bool "nitrogen6x"
- select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
- select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_PICON
bool "platinum-picon"
- select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
- select CPU_V7
select SUPPORT_SPL
config TARGET_SECOMX6
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
- select CPU_V7
config TARGET_TITANIUM
bool "titanium"
- select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
config TARGET_UDOO
bool "udoo"
- select CPU_V7
select SUPPORT_SPL
config TARGET_WANDBOARD
bool "wandboard"
- select CPU_V7
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
- select CPU_V7
endchoice
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
+ reg = readl(&anatop->pll_enet);
+
if (fec_id == 0) {
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
- trfc = DIV_ROUND_UP(300000, clkper) - 1;
- txs = DIV_ROUND_UP(310000, clkper) - 1;
+ trfc = DIV_ROUND_UP(260000, clkper) - 1;
+ txs = DIV_ROUND_UP(270000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;
*/
#include <common.h>
-#include <asm/armv7.h>
-#include <asm/bootm.h>
-#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
u32 fpga_rev;
};
-#if defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 1,
}
#endif
-void init_aips(void)
-{
- struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
- struct aipstz_regs *aips3;
-#endif
-
- aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
- aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_MX6SX
- aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
-#endif
-
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips1->mprot0);
- writel(0x77777777, &aips1->mprot1);
- writel(0x77777777, &aips2->mprot0);
- writel(0x77777777, &aips2->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips1->opacr0);
- writel(0x00000000, &aips1->opacr1);
- writel(0x00000000, &aips1->opacr2);
- writel(0x00000000, &aips1->opacr3);
- writel(0x00000000, &aips1->opacr4);
- writel(0x00000000, &aips2->opacr0);
- writel(0x00000000, &aips2->opacr1);
- writel(0x00000000, &aips2->opacr2);
- writel(0x00000000, &aips2->opacr3);
- writel(0x00000000, &aips2->opacr4);
-
-#ifdef CONFIG_MX6SX
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips3->mprot0);
- writel(0x77777777, &aips3->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips3->opacr0);
- writel(0x00000000, &aips3->opacr1);
- writel(0x00000000, &aips3->opacr2);
- writel(0x00000000, &aips3->opacr3);
- writel(0x00000000, &aips3->opacr4);
-#endif
-}
-
static void clear_ldo_ramp(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
return 0;
}
-static void imx_set_wdog_powerdown(bool enable)
-{
- struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
- struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
- struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
-
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
- writew(enable, &wdog3->wmcr);
-
- /* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
-}
-
static void set_ahb_rate(u32 val)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
}
#endif
-#define SRC_SCR_WARM_RESET_ENABLE 0
-
-static void init_src(void)
-{
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 val;
-
- /*
- * force warm reset sources to generate cold reset
- * for a more reliable restart
- */
- val = readl(&src_regs->scr);
- val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
- writel(val, &src_regs->scr);
-}
-
int arch_cpu_init(void)
{
init_aips();
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
- enum dcache_option option = DCACHE_WRITEBACK;
-#endif
-
- /* Avoid random hang when download by usb */
- invalidate_dcache_all();
-
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-
- /* Enable caching on OCRAM and ROM */
- mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
- ROMCP_ARB_END_ADDR,
- option);
- mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
- IRAM_SIZE,
- option);
-}
-#endif
-
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
}
#endif
-void boot_mode_apply(unsigned cfg_val)
-{
- unsigned reg;
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- writel(cfg_val, &psrc->gpr9);
- reg = readl(&psrc->gpr10);
- if (cfg_val)
- reg |= 1 << 28;
- else
- reg &= ~(1 << 28);
- writel(reg, &psrc->gpr10);
-}
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
writel(reg, &mxc_ccm->chsccdr);
}
#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
-void v7_outer_cache_enable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- unsigned int val;
-
-
- /*
- * Set bit 22 in the auxiliary control register. If this bit
- * is cleared, PL310 treats Normal Shared Non-cacheable
- * accesses as Cacheable no-allocate.
- */
- setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
- }
-#endif
-
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x132, &pl310->pl310_tag_latency_ctrl);
- writel(0x132, &pl310->pl310_data_latency_ctrl);
-
- val = readl(&pl310->pl310_prefetch_ctrl);
-
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
-
- /*
- * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
- * But according to ARM PL310 errata: 752271
- * ID: 752271: Double linefill feature can cause data corruption
- * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
- * Workaround: The only workaround to this erratum is to disable the
- * double linefill feature. This is the default behavior.
- */
-
-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
- writel(val, &pl310->pl310_prefetch_ctrl);
-
- val = readl(&pl310->pl310_power_ctrl);
- val |= L2X0_DYNAMIC_CLK_GATING_EN;
- val |= L2X0_STNDBY_MODE_EN;
- writel(val, &pl310->pl310_power_ctrl);
-
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
-void v7_outer_cache_disable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
-
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
--- /dev/null
+if ARCH_MX7
+
+config MX7
+ bool
+ default y
+
+config MX7D
+ bool
+
+choice
+ prompt "MX7 board select"
+ optional
+
+config TARGET_MX7DSABRESD
+ bool "mx7dsabresd"
+ select DM
+ select DM_THERMAL
+
+endchoice
+
+config SYS_SOC
+ default "mx7"
+
+source "board/freescale/mx7dsabresd/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y := soc.o clock.o clock_slice.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+ return 0;
+}
+
+u32 get_ahb_clk(void)
+{
+ return get_root_clk(AHB_CLK_ROOT);
+}
+
+static u32 get_ipg_clk(void)
+{
+ /*
+ * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
+ * each other.
+ */
+ return get_ahb_clk() / 2;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_root_clk(UART1_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, enable);
+}
+
+void enable_thermal_clk(void)
+{
+ enable_ocotp_clk(1);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 target;
+
+ if (enable) {
+ /* disable the clock gate first */
+ clock_enable(CCGR_USB_HSIC, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON |
+ USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(USB_HSIC_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USB_CTRL, 1);
+ clock_enable(CCGR_USB_HSIC, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ } else {
+ clock_enable(CCGR_USB_CTRL, 0);
+ clock_enable(CCGR_USB_HSIC, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ }
+}
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 reg, div_sel;
+ u32 num, denom;
+
+ /*
+ * Alought there are four choices for the bypass src,
+ * we choose OSC_24M which is the default set in ROM.
+ */
+ switch (pll) {
+ case PLL_CORE:
+ reg = readl(&ccm_anatop->pll_arm);
+
+ if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
+
+ return (infreq * div_sel) / 2;
+
+ case PLL_SYS:
+ reg = readl(&ccm_anatop->pll_480);
+
+ if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
+ return MXC_HCLK;
+
+ if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
+ return 480000000u;
+ else
+ return 528000000u;
+
+ case PLL_ENET:
+ reg = readl(&ccm_anatop->pll_enet);
+
+ if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
+ return MXC_HCLK;
+
+ return 1000000000u;
+
+ case PLL_DDR:
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
+ return 0;
+
+ num = ccm_anatop->pll_ddr_num;
+ denom = ccm_anatop->pll_ddr_denom;
+
+ if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
+
+ return infreq * (div_sel + num / denom);
+
+ case PLL_USB:
+ return 480000000u;
+
+ default:
+ printf("Unsupported pll clocks %d\n", pll);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_sys_derive(int derive)
+{
+ u32 freq, div, frac;
+ u32 reg;
+
+ div = 1;
+ reg = readl(&ccm_anatop->pll_480);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+ switch (derive) {
+ case PLL_SYS_MAIN_480M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
+ return 0;
+ else
+ return freq;
+ case PLL_SYS_MAIN_240M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 2;
+ case PLL_SYS_MAIN_120M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 4;
+ case PLL_SYS_PFD0_392M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD0_196M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD1_332M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD1_166M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD2_270M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD2_135M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD3_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD4_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD5_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD6_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD7_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
+ break;
+ default:
+ printf("Error derived pll_sys clock %d\n", derive);
+ return 0;
+ }
+
+ return ((freq / frac) * 18) / div;
+}
+
+static u32 mxc_get_pll_enet_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_enet);
+
+ switch (derive) {
+ case PLL_ENET_MAIN_500M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
+ return freq / 2;
+ break;
+ case PLL_ENET_MAIN_250M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
+ return freq / 4;
+ break;
+ case PLL_ENET_MAIN_125M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
+ return freq / 8;
+ break;
+ case PLL_ENET_MAIN_100M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
+ return freq / 10;
+ break;
+ case PLL_ENET_MAIN_50M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
+ return freq / 20;
+ break;
+ case PLL_ENET_MAIN_40M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
+ return freq / 25;
+ break;
+ case PLL_ENET_MAIN_25M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
+ return freq / 40;
+ break;
+ default:
+ printf("Error derived pll_enet clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_ddr_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_DDR, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ switch (derive) {
+ case PLL_DRAM_MAIN_1066M_CLK:
+ return freq;
+ case PLL_DRAM_MAIN_533M_CLK:
+ if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
+ return freq / 2;
+ break;
+ default:
+ printf("Error derived pll_ddr clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
+{
+ switch (pll) {
+ case PLL_SYS:
+ return mxc_get_pll_sys_derive(derive);
+ case PLL_ENET:
+ return mxc_get_pll_enet_derive(derive);
+ case PLL_DDR:
+ return mxc_get_pll_ddr_derive(derive);
+ default:
+ printf("Error pll.\n");
+ return 0;
+ }
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_24M_CLK:
+ return 24000000u;
+ case PLL_ARM_MAIN_800M_CLK:
+ return decode_pll(PLL_CORE, MXC_HCLK);
+
+ case PLL_SYS_MAIN_480M_CLK:
+ case PLL_SYS_MAIN_240M_CLK:
+ case PLL_SYS_MAIN_120M_CLK:
+ case PLL_SYS_PFD0_392M_CLK:
+ case PLL_SYS_PFD0_196M_CLK:
+ case PLL_SYS_PFD1_332M_CLK:
+ case PLL_SYS_PFD1_166M_CLK:
+ case PLL_SYS_PFD2_270M_CLK:
+ case PLL_SYS_PFD2_135M_CLK:
+ case PLL_SYS_PFD3_CLK:
+ case PLL_SYS_PFD4_CLK:
+ case PLL_SYS_PFD5_CLK:
+ case PLL_SYS_PFD6_CLK:
+ case PLL_SYS_PFD7_CLK:
+ return mxc_get_pll_derive(PLL_SYS, root_src);
+
+ case PLL_ENET_MAIN_500M_CLK:
+ case PLL_ENET_MAIN_250M_CLK:
+ case PLL_ENET_MAIN_125M_CLK:
+ case PLL_ENET_MAIN_100M_CLK:
+ case PLL_ENET_MAIN_50M_CLK:
+ case PLL_ENET_MAIN_40M_CLK:
+ case PLL_ENET_MAIN_25M_CLK:
+ return mxc_get_pll_derive(PLL_ENET, root_src);
+
+ case PLL_DRAM_MAIN_1066M_CLK:
+ case PLL_DRAM_MAIN_533M_CLK:
+ return mxc_get_pll_derive(PLL_DDR, root_src);
+
+ case PLL_AUDIO_MAIN_CLK:
+ return decode_pll(PLL_AUDIO, MXC_HCLK);
+ case PLL_VIDEO_MAIN_CLK:
+ return decode_pll(PLL_VIDEO, MXC_HCLK);
+
+ case PLL_USB_MAIN_480M_CLK:
+ return decode_pll(PLL_USB, MXC_HCLK);
+
+ case REF_1M_CLK:
+ return 1000000;
+ case OSC_32K_CLK:
+ return MXC_CLK32;
+
+ case EXT_CLK_1:
+ case EXT_CLK_2:
+ case EXT_CLK_3:
+ case EXT_CLK_4:
+ printf("No EXT CLK supported??\n");
+ break;
+ };
+
+ return 0;
+}
+
+u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, auto_podf, root_src_clk;
+ int auto_en;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
+ return 0;
+
+ if (auto_en == 0)
+ auto_podf = 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ /*
+ * bypass clk is ignored.
+ */
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
+ (auto_podf + 1);
+}
+
+static u32 get_ddrc_clk(void)
+{
+ u32 reg, freq;
+ enum root_post_div post_div;
+
+ reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
+ if (reg & CLK_ROOT_MUX_MASK)
+ /* DRAM_ALT_CLK_ROOT */
+ freq = get_root_clk(DRAM_ALT_CLK_ROOT);
+ else
+ /* PLL_DRAM_MAIN_1066M_CLK */
+ freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
+
+ post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
+
+ return freq / (post_div + 1) / 2;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_root_clk(ARM_A7_CLK_ROOT);
+ case MXC_AXI_CLK:
+ return get_root_clk(MAIN_AXI_CLK_ROOT);
+ case MXC_AHB_CLK:
+ return get_root_clk(AHB_CLK_ROOT);
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
+ case MXC_DDR_CLK:
+ return get_ddrc_clk();
+ case MXC_ESDHC_CLK:
+ return get_root_clk(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return get_root_clk(USDHC3_CLK_ROOT);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 target;
+
+ if (i2c_num >= 4)
+ return -EINVAL;
+
+ if (enable) {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+
+ /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
+
+ target = CLK_ROOT_ON |
+ I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
+
+ clock_enable(CCGR_I2C1 + i2c_num, 1);
+ } else {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+ }
+
+ return 0;
+}
+#endif
+
+static void init_clk_esdhc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_USDHC1, 0);
+ clock_enable(CCGR_USDHC2, 0);
+ clock_enable(CCGR_USDHC3, 0);
+
+ /* 196: 392/2 */
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC3_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USDHC1, 1);
+ clock_enable(CCGR_USDHC2, 1);
+ clock_enable(CCGR_USDHC3, 1);
+}
+
+static void init_clk_uart(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_UART1, 0);
+ clock_enable(CCGR_UART2, 0);
+ clock_enable(CCGR_UART3, 0);
+ clock_enable(CCGR_UART4, 0);
+ clock_enable(CCGR_UART5, 0);
+ clock_enable(CCGR_UART6, 0);
+ clock_enable(CCGR_UART7, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART4_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART5_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART6_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART7_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_UART1, 1);
+ clock_enable(CCGR_UART2, 1);
+ clock_enable(CCGR_UART3, 1);
+ clock_enable(CCGR_UART4, 1);
+ clock_enable(CCGR_UART5, 1);
+ clock_enable(CCGR_UART6, 1);
+ clock_enable(CCGR_UART7, 1);
+}
+
+static void init_clk_weim(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WEIM, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(EIM_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WEIM, 1);
+}
+
+static void init_clk_ecspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_ECSPI1, 0);
+ clock_enable(CCGR_ECSPI2, 0);
+ clock_enable(CCGR_ECSPI3, 0);
+ clock_enable(CCGR_ECSPI4, 0);
+
+ /* 60Mhz: 240/4 */
+ target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI4_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_ECSPI1, 1);
+ clock_enable(CCGR_ECSPI2, 1);
+ clock_enable(CCGR_ECSPI3, 1);
+ clock_enable(CCGR_ECSPI4, 1);
+}
+
+static void init_clk_wdog(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_enable(CCGR_WDOG4, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(WDOG_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+ clock_enable(CCGR_WDOG4, 1);
+}
+
+#ifdef CONFIG_MXC_EPDC
+static void init_clk_epdc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_EPDC, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
+ clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_EPDC, 1);
+}
+#endif
+
+static int enable_pll_enet(void)
+{
+ u32 reg;
+ s32 timeout = 100000;
+
+ reg = readl(&ccm_anatop->pll_enet);
+ /* If pll_enet powered up, no need to set it again */
+ if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
+ reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
+ writel(reg, &ccm_anatop->pll_enet);
+
+ while (timeout--) {
+ if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
+ break;
+ }
+
+ if (timeout <= 0) {
+ /* If timeout, we set pwdn for pll_enet. */
+ reg |= ANADIG_PLL_ENET_PWDN_MASK;
+ return -ETIME;
+ }
+ }
+
+ /* Clear bypass */
+ writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
+
+ writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
+ &ccm_anatop->pll_enet_set);
+
+ return 0;
+}
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+ u32 post_div)
+{
+ u32 reg = 0;
+ ulong start;
+
+ debug("pll5 div = %d, num = %d, denom = %d\n",
+ pll_div, pll_num, pll_denom);
+
+ /* Power up PLL5 video and disable its output */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
+ &ccm_anatop->pll_video_clr);
+
+ /* Set div, num and denom */
+ switch (post_div) {
+ case 1:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 2:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 3:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 4:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 0:
+ default:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ }
+
+ writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
+ &ccm_anatop->pll_video_num);
+
+ writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
+ &ccm_anatop->pll_video_denom);
+
+ /* Wait PLL5 lock */
+ start = get_timer(0); /* Get current timestamp */
+
+ do {
+ reg = readl(&ccm_anatop->pll_video);
+ if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
+ /* Enable PLL out */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
+ &ccm_anatop->pll_video_set);
+ return 0;
+ }
+ } while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+ printf("Lock PLL5 timeout\n");
+
+ return 1;
+}
+
+int set_clk_qspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_QSPI, 0);
+
+ /* 49M: 392/2/4 */
+ target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(QSPI_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+int set_clk_nand(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_RAWNAND, 0);
+
+ enable_pll_enet();
+ /* 100: 500/5 */
+ target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
+ clock_set_target_val(NAND_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_RAWNAND, 1);
+
+ return 0;
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
+{
+ u32 hck = MXC_HCLK/1000;
+ u32 min = hck * 27;
+ u32 max = hck * 54;
+ u32 temp, best = 0;
+ u32 i, j, pred = 1, postd = 1;
+ u32 pll_div, pll_num, pll_denom, post_div = 0;
+ u32 target;
+
+ debug("mxs_set_lcdclk, freq = %d\n", freq);
+
+ clock_enable(CCGR_LCDIF, 0);
+
+ temp = (freq * 8 * 8);
+ if (temp < min) {
+ for (i = 1; i <= 4; i++) {
+ if ((temp * (1 << i)) > min) {
+ post_div = i;
+ freq = (freq * (1 << i));
+ break;
+ }
+ }
+
+ if (5 == i) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+ }
+
+ for (i = 1; i <= 8; i++) {
+ for (j = 1; j <= 8; j++) {
+ temp = freq * i * j;
+ if (temp > max || temp < min)
+ continue;
+
+ if (best == 0 || temp < best) {
+ best = temp;
+ pred = i;
+ postd = j;
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+
+ debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+ pll_div = best / hck;
+ pll_denom = 1000000;
+ pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
+ CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
+ clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
+
+ clock_enable(CCGR_LCDIF, 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ int ret;
+ u32 enet1_ref, enet2_ref;
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_ENET2, 0);
+
+ switch (type) {
+ case ENET_125MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = enable_pll_enet();
+ if (ret != 0)
+ return ret;
+
+ /* set enet axi clock 196M: 392/2 */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET1_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet2_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET2_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ target = CLK_ROOT_ON |
+ ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
+#endif
+ /* enable clock */
+ clock_enable(CCGR_ENET1, 1);
+ clock_enable(CCGR_ENET2, 1);
+
+ return 0;
+}
+#endif
+
+/* Configure PLL/PFD freq */
+void clock_init(void)
+{
+/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
+ * In u-boot, we have to:
+ * 1. Configure PFD3- PFD7 for freq we needed in u-boot
+ * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
+ * interface. The clocks for these peripherals are enabled after this intialization.
+ * 3. Other peripherals with set clock rate interface does not be set in this function.
+ */
+ u32 reg;
+
+ /*
+ * Configure PFD4 to 392M
+ * 480M * 18 / 0x16 = 392M
+ */
+ reg = readl(&ccm_anatop->pfd_480b);
+
+ reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
+ CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
+ reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
+
+ writel(reg, &ccm_anatop->pfd_480b);
+
+ init_clk_esdhc();
+ init_clk_uart();
+ init_clk_weim();
+ init_clk_ecspi();
+ init_clk_wdog();
+#ifdef CONFIG_MXC_EPDC
+ init_clk_epdc();
+#endif
+
+ enable_usboh3_clk(1);
+
+ clock_enable(CCGR_SNVS, 1);
+
+#ifdef CONFIG_NAND_MXS
+ clock_enable(CCGR_RAWNAND, 1);
+#endif
+}
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ if (enable)
+ clock_enable(CCGR_CAAM, 1);
+ else
+ clock_enable(CCGR_CAAM, 0);
+}
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+void epdc_clock_enable(void)
+{
+ clock_enable(CCGR_EPDC, 1);
+}
+void epdc_clock_disable(void)
+{
+ clock_enable(CCGR_EPDC, 0);
+}
+#endif
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+ freq = decode_pll(PLL_CORE, MXC_HCLK);
+ printf("PLL_CORE %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+ printf("PLL_SYS %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ printf("PLL_NET %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+
+ printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+ printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
+ "display clocks",
+ ""
+);
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+static struct clk_root_map root_array[] = {
+ {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
+ {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
+ PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
+ },
+ {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
+ },
+ {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
+ },
+ {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
+ },
+ {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
+ },
+ {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
+ PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
+ EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
+ },
+ {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
+ },
+ {EIM_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {NAND_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {UART1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART5_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART6_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART7_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
+ },
+ {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
+ },
+ {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {IPP_DO_CLKO1, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
+ },
+ {IPP_DO_CLKO2, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
+ },
+};
+
+/* select which entry of root_array */
+static int select(enum clk_root_index clock_id)
+{
+ int i, size;
+ struct clk_root_map *p = root_array;
+
+ size = ARRAY_SIZE(root_array);
+
+ for (i = 0; i < size; i++, p++) {
+ if (clock_id == p->entry)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int src_supported(int entry, enum clk_root_src clock_src)
+{
+ int i, size;
+ struct clk_root_map *p = &root_array[entry];
+
+ if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
+ size = 2;
+ else
+ size = 8;
+
+ for (i = 0; i < size; i++) {
+ if (p->src_mux[i] == clock_src)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+/* Set src for clock root slice. */
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
+{
+ int root_entry, src_entry;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_MUX_MASK;
+ reg |= src_entry << CLK_ROOT_MUX_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Get src of a clock root slice. */
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_MUX_MASK;
+ val >>= CLK_ROOT_MUX_SHIFT;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+ *p_clock_src = p->src_mux[val];
+
+ return 0;
+}
+
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
+{
+ int root_entry;
+ struct clk_root_map *p;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_PRE_DIV_MASK;
+ reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ *pre_div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_PRE_DIV_MASK;
+ val >>= CLK_ROOT_PRE_DIV_SHIFT;
+
+ *pre_div = val;
+
+ return 0;
+}
+
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
+{
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ if (div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_POST_DIV_MASK;
+ reg |= div << CLK_ROOT_POST_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if (clock_id == DRAM_CLK_ROOT)
+ val &= DRAM_CLK_ROOT_POST_DIV_MASK;
+ else
+ val &= CLK_ROOT_POST_DIV_MASK;
+ val >>= CLK_ROOT_POST_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+ int auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ printf("Auto postdiv not supported.!\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Each time only one filed can be changed, no use target_root_set.
+ */
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= ~CLK_ROOT_AUTO_DIV_MASK;
+ val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
+
+ if (auto_en)
+ val |= CLK_ROOT_AUTO_EN;
+ else
+ val &= ~CLK_ROOT_AUTO_EN;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+ int *auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ /*
+ * Only bus/ahb channel supports auto div.
+ * If unsupported, just set auto_en and div with 0.
+ */
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ *auto_en = 0;
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
+ *auto_en = 0;
+ else
+ *auto_en = 1;
+
+ val &= CLK_ROOT_AUTO_DIV_MASK;
+ val >>= CLK_ROOT_AUTO_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_set_target_val(enum clk_root_index clock_id, u32 val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Auto_div and auto_en is ignored, they are rarely used. */
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src)
+{
+ u32 val;
+ int root_entry, src_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if (p->type == CCM_DRAM_CHANNEL) {
+ if (post_div > CLK_ROOT_POST_DIV7) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ if (p->type == CCM_DRAM_PHYM_CHANNEL) {
+ if (post_div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
+ post_div << CLK_ROOT_POST_DIV_SHIFT |
+ src_entry << CLK_ROOT_MUX_SHIFT;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_root_enabled(enum clk_root_index clock_id)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ /*
+ * No enable bit for DRAM controller and PHY. Just return enabled.
+ */
+ if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
+ return 1;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
+}
+
+/* CCGR gate operation */
+int clock_enable(enum clk_ccgr_index index, bool enable)
+{
+ if (index >= CCGR_MAX)
+ return -EINVAL;
+
+ if (enable)
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_set);
+ else
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_clr);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
+
+#if defined(CONFIG_IMX_THERMAL)
+static const struct imx_thermal_plat imx7_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 3,
+ .fuse_word = 3,
+};
+
+U_BOOT_DEVICE(imx7_thermal) = {
+ .name = "imx_thermal",
+ .platdata = &imx7_thermal_plat,
+};
+#endif
+
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT 8
+#define OCOTP_TESTER3_SPEED_800MHZ 0
+#define OCOTP_TESTER3_SPEED_850MHZ 1
+#define OCOTP_TESTER3_SPEED_1GHZ 2
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_SPEED_SHIFT;
+ val &= 0x3;
+
+ switch(val) {
+ case OCOTP_TESTER3_SPEED_800MHZ:
+ return 792000000;
+ case OCOTP_TESTER3_SPEED_850MHZ:
+ return 852000000;
+ case OCOTP_TESTER3_SPEED_1GHZ:
+ return 996000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
+u32 get_cpu_rev(void)
+{
+ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+ u32 reg = readl(&ccm_anatop->digprog);
+ u32 type = (reg >> 16) & 0xff;
+
+ reg &= 0xff;
+ return (type << 12) | reg;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
+int arch_cpu_init(void)
+{
+ init_aips();
+
+ /* Disable PDE bit of WMCR register */
+ imx_set_wdog_powerdown(false);
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ serialnr->low = fuse->tester0;
+ serialnr->high = fuse->tester1;
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[9];
+ struct fuse_bank9_regs *fuse =
+ (struct fuse_bank9_regs *)bank->fuse_regs;
+
+ if (0 == dev_id) {
+ u32 value = readl(&fuse->mac_addr1);
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+ } else {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24;
+ mac[1] = value >> 16;
+ mac[2] = value >> 8;
+ mac[3] = value;
+
+ value = readl(&fuse->mac_addr1);
+ mac[4] = value >> 24;
+ mac[5] = value >> 16;
+ }
+}
+#endif
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+ u32 reg = readw(&wdog->wcr);
+ /*
+ * Output WDOG_B signal to reset external pmic or POR_B decided by
+ * the board desgin. Without external reset, the peripherals/DDR/
+ * PMIC are not reset, that may cause system working abnormal.
+ */
+ reg = readw(&wdog->wcr);
+ reg |= 1 << 3;
+ /*
+ * WDZST bit is write-once only bit. Align this bit in kernel,
+ * otherwise kernel code will have no chance to set this bit.
+ */
+ reg |= 1 << 0;
+ writew(reg, &wdog->wcr);
+}
+
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
+ * to SBMR1, which will determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
+ {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
+ {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
+ {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
+
+ {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
+ /* 4 bit bus width */
+ {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
+ {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
+ {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
+ {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
+ {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
+ {NULL, 0},
+};
+
+enum boot_device get_boot_device(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+ enum boot_device boot_dev = SD1_BOOT;
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 boot_instance = (*p)->boot_dev_instance;
+
+ switch (boot_type) {
+ case BOOT_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BOOT_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BOOT_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BOOT_TYPE_QSPI:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BOOT_TYPE_WEIM:
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case BOOT_TYPE_SPINOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+
+void s_init(void)
+{
+#if !defined CONFIG_SPL_BUILD
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+ /* clock configuration. */
+ clock_init();
+
+ return;
+}
bl psci_arch_init
#endif
+#ifdef CONFIG_ARM_ERRATA_773022
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 1)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_774769
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 25)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
/* Disable refreshed before leveling */
- clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
- EMIF_REG_INITREF_DIS_SHIFT);
+ clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
+ EMIF_REG_INITREF_DIS_MASK);
/* Start Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
}
/* Enable refreshes after leveling */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
debug("HW leveling success\n");
/*
bool "TeeJet Mt.Ventoux"
select SUPPORT_SPL
-config TARGET_OMAP3_SDP3430
- bool "TI OMAP3430 SDP"
-
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select SUPPORT_SPL
bool "ECO5PK"
select SUPPORT_SPL
-config TARGET_DIG297
- bool "DIG297"
-
config TARGET_TRICORDER
bool "Tricorder"
select SUPPORT_SPL
select DM_SERIAL
select DM_GPIO
-config TARGET_OMAP3_MVBLX
- bool "OMAP3 MVBLX"
-
config TARGET_NOKIA_RX51
bool "Nokia RX51"
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
-source "board/comelit/dig297/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
select DM
select DM_SERIAL
+config TARGET_STOUT
+ bool "Stout board"
+ select DM
+ select DM_SERIAL
+
endchoice
config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
default n
choice
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
source "board/renesas/porter/Kconfig"
+source "board/renesas/stout/Kconfig"
endif
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
* binary over USB. If it is found, it determines where SPL was
* read from.
*/
- if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */
+ if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
return BOOT_DEVICE_BOARD;
/* The BROM will try to boot from mmc0 first, so try that first. */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- board_init_r(NULL, 0);
}
#endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := timer.o clock.o prcmu.o cpu.o
-obj-y += lowlevel.o
+++ /dev/null
-/*
- * (C) Copyright 2009 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct clkrst {
- unsigned int pcken;
- unsigned int pckdis;
- unsigned int kcken;
- unsigned int kckdis;
-};
-
-static unsigned int clkrst_base[] = {
- U8500_CLKRST1_BASE,
- U8500_CLKRST2_BASE,
- U8500_CLKRST3_BASE,
- 0,
- U8500_CLKRST5_BASE,
- U8500_CLKRST6_BASE,
- U8500_CLKRST7_BASE, /* ED only */
-};
-
-/* Turn on peripheral clock at PRCC level */
-void u8500_clock_enable(int periph, int cluster, int kern)
-{
- struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
-
- if (kern != -1)
- writel(1 << kern, &clkrst->kcken);
-
- if (cluster != -1)
- writel(1 << cluster, &clkrst->pcken);
-}
-
-void db8500_clocks_init(void)
-{
- /*
- * Enable all clocks. This is u-boot, we can enable it all. There is no
- * powersave in u-boot.
- */
-
- u8500_clock_enable(1, 9, -1); /* GPIO0 */
- u8500_clock_enable(2, 11, -1);/* GPIO1 */
- u8500_clock_enable(3, 8, -1); /* GPIO2 */
- u8500_clock_enable(5, 1, -1); /* GPIO3 */
- u8500_clock_enable(3, 6, 6); /* UART2 */
- u8500_clock_enable(3, 3, 3); /* I2C0 */
- u8500_clock_enable(1, 5, 5); /* SDI0 */
- u8500_clock_enable(2, 4, 2); /* SDI4 */
- u8500_clock_enable(6, 6, -1); /* MTU0 */
- u8500_clock_enable(3, 4, 4); /* SDI2 */
-
- /*
- * Enabling clocks for all devices which are AMBA devices in the
- * kernel. Otherwise they will not get probe()'d because the
- * peripheral ID register will not be powered.
- */
-
- /* XXX: some of these differ between ED/V1 */
-
- u8500_clock_enable(1, 1, 1); /* UART1 */
- u8500_clock_enable(1, 0, 0); /* UART0 */
- u8500_clock_enable(3, 2, 2); /* SSP1 */
- u8500_clock_enable(3, 1, 1); /* SSP0 */
- u8500_clock_enable(2, 8, -1); /* SPI0 */
- u8500_clock_enable(2, 5, 3); /* MSP2 */
-}
+++ /dev/null
-/*
- * Copyright (C) 2012 Linaro Limited
- * Mathieu Poirier <mathieu.poirier@linaro.org>
- *
- * Based on original code from Joakim Axelsson at ST-Ericsson
- * (C) Copyright 2010 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/prcmu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-
-#include <asm/arch/hardware.h>
-
-#define CPUID_DB8500V1 0x411fc091
-#define CPUID_DB8500V2 0x412fc091
-#define ASICID_DB8500V11 0x008500A1
-
-#define CACHE_CONTR_BASE 0xA0412000
-/* Cache controller register offsets
- * as found in ARM's technical reference manual
- */
-#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
-#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
-#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
-
-static unsigned int read_asicid(void);
-
-static inline unsigned int read_cpuid(void)
-{
- unsigned int val;
-
- /* Main ID register (MIDR) */
- asm("mrc p15, 0, %0, c0, c0, 0"
- : "=r" (val)
- :
- : "cc");
-
- return val;
-}
-
-static int cpu_is_u8500v11(void)
-{
- return read_asicid() == ASICID_DB8500V11;
-}
-
-static int cpu_is_u8500v2(void)
-{
- return read_cpuid() == CPUID_DB8500V2;
-}
-
-static unsigned int read_asicid(void)
-{
- unsigned int *address;
-
- if (cpu_is_u8500v2())
- address = (void *) U8500_ASIC_ID_LOC_V2;
- else
- address = (void *) U8500_ASIC_ID_LOC_ED_V1;
-
- return readl(address);
-}
-
-void cpu_cache_initialization(void)
-{
- unsigned int value;
- /* invalidate all cache entries */
- writel(0xFFFF, CACHE_INVAL_BY_WAY);
-
- /* ways are set to '0' when they are totally
- * cleaned and invalidated
- */
- do {
- value = readl(CACHE_INVAL_BY_WAY);
- } while (value & 0xFF);
-
- /* Invalidate register 9 D and I lockdown */
- writel(0xFF, CACHE_LOCKDOWN_BY_D);
- writel(0xFF, CACHE_LOCKDOWN_BY_I);
-}
-
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * SOC specific cpu init
- */
-int arch_cpu_init(void)
-{
- db8500_prcmu_init();
- db8500_clocks_init();
-
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-#ifdef CONFIG_MMC
-
-int u8500_mmc_power_init(void)
-{
- int ret;
- int enable, voltage;
- int ab8500_revision;
-
- if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
- return 0;
-
- /* Get AB8500 revision */
- ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
- if (ret < 0)
- goto out;
-
- ab8500_revision = ret;
-
- /*
- * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
- * card to work. This is done by enabling the regulators in the AB8500
- * via PRCMU I2C transactions.
- *
- * This code is derived from the handling of AB8500_LDO_VAUX3 in
- * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
- *
- * Turn off and delay is required to have it work across soft reboots.
- */
-
- /* Turn off (read-modify-write) */
- ret = ab8500_read(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG);
- if (ret < 0)
- goto out;
-
- enable = ret;
-
- /* Turn off */
- ret = ab8500_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG,
- enable & ~LDO_VAUX3_ENABLE_MASK);
- if (ret < 0)
- goto out;
-
- udelay(10 * 1000);
-
- /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
- ret = ab8500_read(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_SEL_REG);
- if (ret < 0)
- goto out;
-
- voltage = ret;
-
- if (ab8500_revision < 0x20) {
- voltage &= ~LDO_VAUX3_SEL_MASK;
- voltage |= LDO_VAUX3_SEL_2V9;
- } else {
- voltage &= ~LDO_VAUX3_V2_SEL_MASK;
- voltage |= LDO_VAUX3_V2_SEL_2V91;
- }
-
- ret = ab8500_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
- if (ret < 0)
- goto out;
-
- /* Turn on the supply */
- enable &= ~LDO_VAUX3_ENABLE_MASK;
- enable |= LDO_VAUX3_ENABLE_VAL;
-
- ret = ab8500_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
-
-out:
- return ret;
-}
-#endif /* CONFIG_MMC */
+++ /dev/null
-/*
- * (C) Copyright 2011 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
- mov pc, lr
-ENDPROC(lowlevel_init)
-
- .align 5
-ENTRY(reset_cpu)
- ldr r0, =CFG_PRCMU_BASE
- ldr r1, =0x1
- str r1, [r0, #0x228]
-_loop_forever:
- b _loop_forever
-ENDPROC(reset_cpu)
+++ /dev/null
-/*
- * Copyright (C) 2009 ST-Ericsson SA
- *
- * Adapted from the Linux version:
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * NOTE: This currently does not support the I2C workaround access method.
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/prcmu.h>
-
-/* CPU mailbox registers */
-#define PRCMU_I2C_WRITE(slave) \
- (((slave) << 1) | I2CWRITE | (1 << 6))
-#define PRCMU_I2C_READ(slave) \
- (((slave) << 1) | I2CREAD | (1 << 6))
-
-#define I2C_MBOX_BIT (1 << 5)
-
-static int prcmu_is_ready(void)
-{
- int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
- if (!ready)
- printf("PRCMU firmware not ready\n");
- return ready;
-}
-
-static int wait_for_i2c_mbx_rdy(void)
-{
- int timeout = 10000;
-
- if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
- printf("prcmu: warning i2c mailbox was not acked\n");
- /* clear mailbox 5 ack irq */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
- }
-
- /* check any already on-going transaction */
- while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
- timeout--;
-
- if (timeout == 0)
- return -1;
-
- return 0;
-}
-
-static int wait_for_i2c_req_done(void)
-{
- int timeout = 10000;
-
- /* Set an interrupt to XP70 */
- writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
-
- /* wait for mailbox 5 (i2c) ack */
- while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
- timeout--;
-
- if (timeout == 0)
- return -1;
-
- return 0;
-}
-
-/**
- * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
- * @reg: - db8500 register bank to be accessed
- * @slave: - db8500 register to be accessed
- * Returns: ACK_MB5 value containing the status
- */
-int prcmu_i2c_read(u8 reg, u16 slave)
-{
- uint8_t i2c_status;
- uint8_t i2c_val;
- int ret;
-
- if (!prcmu_is_ready())
- return -1;
-
- debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
- reg, slave);
-
- ret = wait_for_i2c_mbx_rdy();
- if (ret) {
- printf("prcmu_i2c_read: mailbox became not ready\n");
- return ret;
- }
-
- /* prepare the data for mailbox 5 */
- writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
- writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
- writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
- writeb(0, PRCM_REQ_MB5_I2CVAL);
-
- ret = wait_for_i2c_req_done();
- if (ret) {
- printf("prcmu_i2c_read: mailbox request timed out\n");
- return ret;
- }
-
- /* retrieve values */
- debug("ack-mb5:transfer status = %x\n",
- readb(PRCM_ACK_MB5_STATUS));
- debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
- debug("ack-mb5:slave_add = %x\n",
- readb(PRCM_ACK_MB5_SLAVE));
- debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
-
- i2c_status = readb(PRCM_ACK_MB5_STATUS);
- i2c_val = readb(PRCM_ACK_MB5_VAL);
- /* clear mailbox 5 ack irq */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
-
- if (i2c_status == I2C_RD_OK)
- return i2c_val;
-
- printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
- return -1;
-}
-
-/**
- * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
- * @reg: - db8500 register bank to be accessed
- * @slave: - db800 register to be written to
- * @reg_data: - the data to write
- * Returns: ACK_MB5 value containing the status
- */
-int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
-{
- uint8_t i2c_status;
- int ret;
-
- if (!prcmu_is_ready())
- return -1;
-
- debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
- reg, slave);
-
- ret = wait_for_i2c_mbx_rdy();
- if (ret) {
- printf("prcmu_i2c_write: mailbox became not ready\n");
- return ret;
- }
-
- /* prepare the data for mailbox 5 */
- writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
- writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
- writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
- writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
-
- ret = wait_for_i2c_req_done();
- if (ret) {
- printf("prcmu_i2c_write: mailbox request timed out\n");
- return ret;
- }
-
- /* retrieve values */
- debug("ack-mb5:transfer status = %x\n",
- readb(PRCM_ACK_MB5_STATUS));
- debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
- debug("ack-mb5:slave_add = %x\n",
- readb(PRCM_ACK_MB5_SLAVE));
- debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
-
- i2c_status = readb(PRCM_ACK_MB5_STATUS);
- debug("\ni2c_status = %x\n", i2c_status);
- /* clear mailbox 5 ack irq */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
-
- if (i2c_status == I2C_WR_OK)
- return 0;
-
- printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
- return -1;
-}
-
-void u8500_prcmu_enable(u32 *reg)
-{
- writel(readl(reg) | (1 << 8), reg);
-}
-
-void db8500_prcmu_init(void)
-{
- /* Enable timers */
- writel(1 << 17, PRCM_TCR);
-
- u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
- /* PER4CLK does not exist */
- u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
- /* Only exists in ED but is always ok to write to */
- u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
-
- u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
-
- u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
-
- /* Clean up the mailbox interrupts after pre-u-boot code. */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Linaro Limited
- * John Rigby <john.rigby@linaro.org>
- *
- * Based on original from Linux kernel source and
- * internal ST-Ericsson U-Boot source.
- * (C) Copyright 2009 Alessandro Rubini
- * (C) Copyright 2010 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The MTU device has some interrupt control registers
- * followed by 4 timers.
- */
-
-/* The timers */
-struct u8500_mtu_timer {
- u32 lr; /* Load value */
- u32 cv; /* Current value */
- u32 cr; /* Control reg */
- u32 bglr; /* ??? */
-};
-
-/* The MTU that contains the timers */
-struct u8500_mtu {
- u32 imsc; /* Interrupt mask set/clear */
- u32 ris; /* Raw interrupt status */
- u32 mis; /* Masked interrupt status */
- u32 icr; /* Interrupt clear register */
- struct u8500_mtu_timer pt[4];
-};
-
-/* bits for the control register */
-#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
-#define MTU_CR_32BITS 0x02
-
-#define MTU_CR_PRESCALE_1 0x00
-#define MTU_CR_PRESCALE_16 0x04
-#define MTU_CR_PRESCALE_256 0x08
-#define MTU_CR_PRESCALE_MASK 0x0c
-
-#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CR_ENA 0x80
-
-/*
- * The MTU is clocked at 133 MHz by default. (V1 and later)
- */
-#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
-#define COUNT_TO_USEC(x) ((x) * 16 / 133)
-#define USEC_TO_COUNT(x) ((x) * 133 / 16)
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-#define TIMER_LOAD_VAL 0xffffffff
-
-/*
- * MTU timer to use (from 0 to 3).
- */
-#define MTU_TIMER 2
-
-static struct u8500_mtu_timer *timer_base =
- &((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
-
-/* macro to read the 32 bit timer: since it decrements, we invert read value */
-#define READ_TIMER() (~readl(&timer_base->cv))
-
-/* Configure a free-running, auto-wrap counter with /16 prescaler */
-int timer_init(void)
-{
- writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
- &timer_base->cr);
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* current tick value */
- ulong now = TICKS_TO_HZ(READ_TIMER());
-
- if (now >= gd->arch.lastinc) { /* normal (non rollover) */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else { /* rollover */
- gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
- gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
-}
-
-/* Delay x useconds */
-void __udelay(ulong usec)
-{
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- ulong now, last = READ_TIMER();
-
- while (tmo > 0) {
- now = READ_TIMER();
- if (now > last) /* normal (non rollover) */
- tmo -= now - last;
- else /* rollover */
- tmo -= TIMER_LOAD_VAL - last + now;
- last = now;
- }
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * Emulation of Power architecture long long timebase.
- *
- * TODO: Support gd->arch.tbu for real long long timebase.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * Emulation of Power architecture timebase.
- * NB: Low resolution compared to Power tbclk.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
+#ifdef COUNTER_FREQUENCY
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
+#endif
b 0f
2: msr vbar_el2, x0
mov x0, #0x33ff
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
+ tegra210-p2371-2180.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
+ uniphier-ph1-pro5-4kbox.dtb \
uniphier-ph1-sld3-ref.dtb \
- uniphier-ph1-sld8-ref.dtb
+ uniphier-ph1-sld8-ref.dtb \
+ uniphier-proxstream2-gentil.dtb \
+ uniphier-proxstream2-vodka.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
+ sun4i-a10-inet1.dtb \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb \
sun4i-a10-inet97fv2.dtb \
+ sun4i-a10-inet9f-rev03.dtb \
sun4i-a10-itead-iteaduino-plus.dtb \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
- sun4i-a10-pcduino.dtb
+ sun4i-a10-pcduino.dtb \
+ sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
+ sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
sun5i-a13-forfun-q88db.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
+ sun5i-a13-q8-tablet.dtb \
sun5i-a13-tzx-q8-713b7.dtb \
sun5i-a13-utoo-p66.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
- sun8i-a23-ippo-q8h-v1.2.dtb
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a23-q8-tablet.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
+ sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sdhci@12540000 {
status = "disabled";
};
+
+ dwmmc@12550000 {
+ status = "disabled";
+ };
};
enet0_sgmii_phy = &sgmii_phy2;
enet1_sgmii_phy = &sgmii_phy0;
spi0 = &qspi;
+ spi1 = &dspi1;
};
};
};
};
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: at26df081a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
&i2c0 {
status = "okay";
};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "iNet-1";
+ compatible = "inet-tek,inet1", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@1000 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+
+ button@1200 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <1200000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "iNet-9F Rev 03";
+ compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@600 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button@800 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button@1000 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+
+ button@1200 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1200000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Point of View Protab2-IPS9";
+ compatible = "pov,protab2-ips9", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@400 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+
+ button@800 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ /*
+ * We need to always power the camera sensor, otherwhise all access
+ * to i2c1 is blocked.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vdd-csi";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a10s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "A10s-Wobo i5";
+ compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_wobo_i5>;
+
+ blue {
+ label = "a10s-wobo-i5:blue:usr";
+ gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_power_pin_wobo>;
+ regulator-name = "emac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_b>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&emac_sram {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&mdio {
+ phy-supply = <®_emac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ led_pins_wobo_i5: led_pins@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
+ allwinner,pins = "PB3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ emac_power_pin_wobo: emac_power_pin@0 {
+ allwinner,pins = "PA02";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_usb1_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG12";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ emac_pins_b: emac0@1 {
+ allwinner,pins = "PD6", "PD7", "PD10",
+ "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD18", "PD19", "PD20",
+ "PD21", "PD22", "PD23", "PD24",
+ "PD25", "PD26", "PD27";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc1_pins_a: mmc1@0 {
allwinner,pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sun5i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A13 Tablet";
+ compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_ldo3>;
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sunxi-q8-common.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+&i2c1 {
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_q8: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_pin_a: usb0_vbus_pin@0 {
+ allwinner,pins = "PG12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A23 Tablet";
+ compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp223 pmic on the board.
+ *
+ * Once we have axp223 support we should switch to fully supporting otg.
+ */
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A33 Tablet";
+ compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp223 pmic on the board.
+ *
+ * Once we have axp223 support we should switch to fully supporting otg.
+ */
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sunxi-q8-common.dtsi"
+
+/ {
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ bl_en_pin_q8: bl_en_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_q8: mmc0_cd_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sunxi-common-regulators.dtsi"
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
clocks = <&tegra_car 47>, <&tegra_car 124>;
};
+ spi@7000d400 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+ resets = <&tegra_car 41>;
+ reset-names = "spi";
+ dmas = <&apbdma 15>, <&apbdma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+ resets = <&tegra_car 44>;
+ reset-names = "spi";
+ dmas = <&apbdma 16>, <&apbdma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d800 0x200>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+ resets = <&tegra_car 46>;
+ reset-names = "spi";
+ dmas = <&apbdma 17>, <&apbdma 17>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+ resets = <&tegra_car 68>;
+ reset-names = "spi";
+ dmas = <&apbdma 18>, <&apbdma 18>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+
kbc@7000e200 {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;
--- /dev/null
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA P2371-2180";
+ compatible = "nvidia,p2371-2180", "nvidia,tegra210";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = "/i2c@0,7000d000";
+ sdhci0 = "/sdhci@0,700b0600";
+ sdhci1 = "/sdhci@0,700b0000";
+ usb0 = "/usb@0,7d000000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
+ };
+
+ sdhci@0,700b0000 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ };
+
+ sdhci@0,700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ i2c@0,7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ usb@0,7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro5.dtsi"
+
+/ {
+ model = "UniPhier PH1-Pro5 4KBOX Board";
+ compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS1,115200";
+ stdout-path = &serial1;
+ };
+
+ aliases {
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial1 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {
--- /dev/null
+/*
+ * Device Tree Source for UniPhier ProXstream2 Gentil Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-proxstream2.dtsi"
+
+/ {
+ model = "UniPhier ProXstream2 Gentil Board";
+ compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &serial2;
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for UniPhier ProXstream2 Vodka Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-proxstream2.dtsi"
+
+/ {
+ model = "UniPhier ProXstream2 Vodka Board";
+ compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &serial2;
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
obj-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx6))
+ifeq ($(SOC),$(filter $(SOC),mx7))
+obj-y += cpu.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
+obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ /* Avoid random hang when download by usb */
+ invalidate_dcache_all();
+
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+
+ /* Enable caching on OCRAM and ROM */
+ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+ ROMCP_ARB_END_ADDR,
+ option);
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+ IRAM_SIZE,
+ option);
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#ifdef CONFIG_SYS_L2_PL310
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ unsigned int val;
+
+
+ /*
+ * Set bit 22 in the auxiliary control register. If this bit
+ * is cleared, PL310 treats Normal Shared Non-cacheable
+ * accesses as Cacheable no-allocate.
+ */
+ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+#if defined CONFIG_MX6SL
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
+#endif
+
+ /* Must disable the L2 before changing the latency parameters */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x132, &pl310->pl310_tag_latency_ctrl);
+ writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+ val = readl(&pl310->pl310_prefetch_ctrl);
+
+ /* Turn on the L2 I/D prefetch */
+ val |= 0x30000000;
+
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * But according to ARM PL310 errata: 752271
+ * ID: 752271: Double linefill feature can cause data corruption
+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+ * Workaround: The only workaround to this erratum is to disable the
+ * double linefill feature. This is the default behavior.
+ */
+
+#ifndef CONFIG_MX6Q
+ val |= 0x40800000;
+#endif
+ writel(val, &pl310->pl310_prefetch_ctrl);
+
+ val = readl(&pl310->pl310_power_ctrl);
+ val |= L2X0_DYNAMIC_CLK_GATING_EN;
+ val |= L2X0_STNDBY_MODE_EN;
+ writel(val, &pl310->pl310_power_ctrl);
+
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2_PL310 */
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
case 0x00008:
return "IPP USER";
case 0x00010:
+#ifdef CONFIG_MX7
+ return "WDOG1";
+#else
return "WDOG";
+#endif
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
+ case 0x00080:
+ return "WDOG3";
+#ifdef CONFIG_MX7
+ case 0x00100:
+ return "WDOG4";
+ case 0x00200:
+ return "TEMPSENSE";
+#else
+ case 0x00100:
+ return "TEMPSENSE";
case 0x10000:
return "WARM BOOT";
+#endif
default:
return "unknown reset";
}
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_MX7D:
+ return "7D"; /* Dual-core version of the mx7 */
case MXC_CPU_MX6QP:
return "6QP"; /* Quad-Plus version of the mx6 */
case MXC_CPU_MX6DP:
u32 cpurev;
__maybe_unused u32 max_freq;
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+ cpurev = get_cpu_rev();
+
+#if defined(CONFIG_IMX_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
-#endif
-
- cpurev = get_cpu_rev();
-#if defined(CONFIG_MX6)
printf("CPU: Freescale i.MX%s rev%d.%d",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
puts("CPU: ");
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
if (!ret)
printf(" at %dC\n", cpu_tmp);
else
- puts(" - invalid sensor data\n");
+ debug(" - invalid sensor data\n");
} else {
- puts(" - invalid sensor device\n");
+ debug(" - invalid sensor device\n");
}
#endif
}
#endif
+#ifndef CONFIG_MX7
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
return get_periph_clk() / (ahb_podf + 1);
}
+#endif
void arch_preboot_os(void)
{
#include <asm/arch/iomux-vf610.h>
#include <asm/arch/ddrmc-vf610.h>
-void ddrmc_setup_iomux(void)
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
- static const iomux_v3_cfg_t ddr_pads[] = {
+ static const iomux_v3_cfg_t default_pads[] = {
VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A14__DDR_A_14,
VF610_PAD_DDR_A13__DDR_A_13,
VF610_PAD_DDR_RESETB,
};
- imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
+ if ((pads == NULL) || (pads_count == 0)) {
+ pads = default_pads;
+ pads_count = ARRAY_SIZE(default_pads);
+ }
-void ddrmc_phy_init(void)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+static struct ddrmc_phy_setting default_phy_settings[] = {
+ { DDRMC_PHY_DQ_TIMING, 0 },
+ { DDRMC_PHY_DQ_TIMING, 16 },
+ { DDRMC_PHY_DQ_TIMING, 32 },
- writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
- writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+ { DDRMC_PHY_DQS_TIMING, 1 },
+ { DDRMC_PHY_DQS_TIMING, 17 },
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+ { DDRMC_PHY_CTRL, 2 },
+ { DDRMC_PHY_CTRL, 18 },
+ { DDRMC_PHY_CTRL, 34 },
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+ { DDRMC_PHY_MASTER_CTRL, 3 },
+ { DDRMC_PHY_MASTER_CTRL, 19 },
+ { DDRMC_PHY_MASTER_CTRL, 35 },
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+ { DDRMC_PHY_SLAVE_CTRL, 4 },
+ { DDRMC_PHY_SLAVE_CTRL, 20 },
+ { DDRMC_PHY_SLAVE_CTRL, 36 },
/* LPDDR2 only parameter */
- writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+ { DDRMC_PHY_OFF, 49 },
- writel(DDRMC_PHY50_DDR3_MODE |
- DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
+ { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
/* Processor Pad ODT settings */
- writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
-}
-
-static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
- u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+ { DDRMC_PHY_PROC_PAD_ODT, 52 },
- if (lvl->wrlvl_reg_en) {
- writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
- writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
- writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
- }
-
- if (lvl->rdlvl_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_REG_EN;
- cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
- }
-
- if (lvl->rdlvl_gt_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
- cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
- }
-
- writel(cr102, &ddrmr->cr[102]);
- writel(cr105, &ddrmr->cr[105]);
- writel(cr106, &ddrmr->cr[106]);
- writel(cr110, &ddrmr->cr[110]);
-}
+ /* end marker */
+ { 0, -1 }
+};
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_lvl_info *lvl,
- int col_diff, int row_diff)
+ struct ddrmc_cr_setting *board_cr_settings,
+ struct ddrmc_phy_setting *board_phy_settings,
+ int col_diff, int row_diff)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ struct ddrmc_cr_setting *cr_setting;
+ struct ddrmc_phy_setting *phy_setting;
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
writel(DDRMC_CR12_WRLAT(timings->wrlat) |
DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
- DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
+ DDRMC_CR13_TCCD(timings->tccd) |
+ DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
+ &ddrmr->cr[13]);
writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
DDRMC_CR14_TWTR(timings->twtr) |
DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
- writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
- DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+ writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
+ DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
+ &ddrmr->cr[21]);
writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
- writel(DDRMC_CR23_BSTLEN(3) |
+ writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
writel(DDRMC_CR26_TREF(timings->tref) |
DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
- writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+ writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
writel(DDRMC_CR34_CKSRX(timings->cksrx) |
DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
- writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+ writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
- writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+ writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(timings->aprebit) |
DDRMC_CR73_COL_DIFF(col_diff) |
DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
- DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+ DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
+ DDRMC_CR74_AGE_CNT(timings->age_cnt),
&ddrmr->cr[74]);
writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
DDRMC_CR75_PLEN, &ddrmr->cr[75]);
DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
- writel(DDRMC_CR78_Q_FULLNESS(7) |
+ writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+ writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
+ DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
+ &ddrmr->cr[87]);
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
- if (lvl != NULL)
- ddrmc_ctrl_lvl_init(lvl);
-
- writel(DDRMC_CR117_AXI0_W_PRI(0) |
- DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
- writel(DDRMC_CR118_AXI1_W_PRI(1) |
- DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
-
- writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
- DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
- writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
- DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
- writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
- DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
- writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
- DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
- writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
-
- writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
- writel(DDRMC_CR132_WRLAT_ADJ(5) |
- DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
- writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
- writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
- DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
- writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
- DDRMC_CR139_PHY_WRLV_DLL(3) |
- DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
- writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
- writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
- DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
- writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
- DDRMC_CR144_PHY_RDLV_DLL(3) |
- DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
- writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
- writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
- writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
- writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
- writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
- DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
-
- writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
- DDRMC_CR154_PAD_ZQ_MODE(1) |
- DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
- DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
- writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
- DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
- writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
- writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
- DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
-
- ddrmc_phy_init();
+ /* execute custom CR setting sequence (may be NULL) */
+ cr_setting = board_cr_settings;
+ if (cr_setting != NULL)
+ while (cr_setting->cr_rnum >= 0) {
+ writel(cr_setting->setting,
+ &ddrmr->cr[cr_setting->cr_rnum]);
+ cr_setting++;
+ }
+
+ /* perform default PHY settings (may be overriden by custom settings */
+ phy_setting = default_phy_settings;
+ while (phy_setting->phy_rnum >= 0) {
+ writel(phy_setting->setting,
+ &ddrmr->phy[phy_setting->phy_rnum]);
+ phy_setting++;
+ }
+
+ /* execute custom PHY setting sequence (may be NULL) */
+ phy_setting = board_phy_settings;
+ if (phy_setting != NULL)
+ while (phy_setting->phy_rnum >= 0) {
+ writel(phy_setting->setting,
+ &ddrmr->phy[phy_setting->phy_rnum]);
+ phy_setting++;
+ }
+ /* all inits done, start the DDR controller */
writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
while (!(readl(&ddrmr->cr[80]) && 0x100))
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+
+void init_aips(void)
+{
+ struct aipstz_regs *aips1, *aips2, *aips3;
+
+ aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+ aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+ aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips1->mprot0);
+ writel(0x77777777, &aips1->mprot1);
+ writel(0x77777777, &aips2->mprot0);
+ writel(0x77777777, &aips2->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips1->opacr0);
+ writel(0x00000000, &aips1->opacr1);
+ writel(0x00000000, &aips1->opacr2);
+ writel(0x00000000, &aips1->opacr3);
+ writel(0x00000000, &aips1->opacr4);
+ writel(0x00000000, &aips2->opacr0);
+ writel(0x00000000, &aips2->opacr1);
+ writel(0x00000000, &aips2->opacr2);
+ writel(0x00000000, &aips2->opacr3);
+ writel(0x00000000, &aips2->opacr4);
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips3->mprot0);
+ writel(0x77777777, &aips3->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips3->opacr0);
+ writel(0x00000000, &aips3->opacr1);
+ writel(0x00000000, &aips3->opacr2);
+ writel(0x00000000, &aips3->opacr3);
+ writel(0x00000000, &aips3->opacr4);
+ }
+}
+
+void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+ struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_soc_type(MXC_SOC_MX7))
+ writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+ writew(enable, &wdog4->wmcr);
+#endif
+}
+
+#define SRC_SCR_WARM_RESET_ENABLE 0
+
+void init_src(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+
+ /*
+ * force warm reset sources to generate cold reset
+ * for a more reliable restart
+ */
+ val = readl(&src_regs->scr);
+ val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
+ writel(val, &src_regs->scr);
+}
+
+#ifdef CONFIG_CMD_BMODE
+void boot_mode_apply(unsigned cfg_val)
+{
+ unsigned reg;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+ reg |= 1 << 28;
+ else
+ reg &= ~(1 << 28);
+ writel(reg, &psrc->gpr10);
+}
+#endif
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
-#include <asm/arch/sys_proto.h>
-#endif
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sys_proto.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
}
#endif
- if (mux_ctrl_ofs)
+ if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+ return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, freq);
+
+ return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ usec = usec * freq + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+int timer_init(void)
+{
+ struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+ unsigned long val, freq;
+
+ freq = CONFIG_SC_TIMER_CLK;
+ asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+ writel(freq, &sctr->cntfid0);
+
+ /* Enable system counter */
+ val = readl(&sctr->cntcr);
+ val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+ val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+ writel(val, &sctr->cntcr);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ unsigned long long now;
+
+ asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+ gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+ gd->arch.tbu = (unsigned long)(now >> 32);
+
+ return now;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ return freq;
+}
#include <asm/arch/hardware.h>
-#define BIT(x) (1 << x)
#define CL_BIT(x) (0 << x)
/* Timer register bits */
#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
0xf7020000 - 0x4000) + (0x1000 * bank))
-#define BIT(x) (1 << (x))
-
#define HI6220_GPIO_PER_BANK 8
#define HI6220_GPIO_DIR 0x400
#define HI6220_MMC0_BASE 0xF723D000
#define HI6220_MMC1_BASE 0xF723E000
+#define HI6220_UART0_BASE 0xF8015000
+#define HI6220_UART3_BASE 0xF7113000
+
#define HI6220_PMUSSI_BASE 0xF8000000
#define HI6220_PERI_BASE 0xF7030000
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
+#define MXC_CPU_MX7D 0x72
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_SOC_MX6 0x60
+#define MXC_SOC_MX7 0x70
+
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CLK_NAND_SLC_SELECT (1 << 2)
#define CLK_NAND_MLC_INT (1 << 5)
-/* DMA Clock Control Register bits */
-#define DMA_CLK_ENABLE (1 << 0)
-
/* SSP Clock Control Register bits */
#define CLK_SSP0_ENABLE_CLOCK (1 << 0)
/* Static Memory Delay Registers */
#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
-#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
+#define EMC_STAT_WAITOEN(n) ((n) & 0x0F)
#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
/*
* Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear, from 0 to 127;
+ * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPI_P3_GRP 96
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
+#define LPC32XX_GPI_P3_GRP 128
/*
* A specific GPIO can be selected with this macro
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
+#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+#include <common.h>
+#include <asm/arch/crm_regs.h>
+
+#ifdef CONFIG_SYS_MX7_HCLK
+#define MXC_HCLK CONFIG_SYS_MX7_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX7_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX7_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+};
+
+/* PLL supported by i.mx7d */
+enum pll_clocks {
+ PLL_CORE, /* Core PLL */
+ PLL_SYS, /* System PLL*/
+ PLL_ENET, /* Enet PLL */
+ PLL_AUDIO, /* Audio PLL */
+ PLL_VIDEO, /* Video PLL*/
+ PLL_DDR, /* Dram PLL */
+ PLL_USB, /* USB PLL, fixed at 480MHZ */
+};
+
+/* clk src for clock root gen */
+enum clk_root_src {
+ OSC_24M_CLK,
+
+ PLL_ARM_MAIN_800M_CLK,
+
+ PLL_SYS_MAIN_480M_CLK,
+ PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_MAIN_120M_CLK,
+ PLL_SYS_PFD0_392M_CLK,
+ PLL_SYS_PFD0_196M_CLK,
+ PLL_SYS_PFD1_332M_CLK,
+ PLL_SYS_PFD1_166M_CLK,
+ PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD2_135M_CLK,
+ PLL_SYS_PFD3_CLK,
+ PLL_SYS_PFD4_CLK,
+ PLL_SYS_PFD5_CLK,
+ PLL_SYS_PFD6_CLK,
+ PLL_SYS_PFD7_CLK,
+
+ PLL_ENET_MAIN_500M_CLK,
+ PLL_ENET_MAIN_250M_CLK,
+ PLL_ENET_MAIN_125M_CLK,
+ PLL_ENET_MAIN_100M_CLK,
+ PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_25M_CLK,
+
+ PLL_DRAM_MAIN_1066M_CLK,
+ PLL_DRAM_MAIN_533M_CLK,
+
+ PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK,
+
+ PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
+
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+
+ REF_1M_CLK,
+ OSC_32K_CLK,
+};
+
+/*
+ * Clock root index
+ */
+enum clk_root_index {
+ ARM_A7_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ ARM_M0_CLK_ROOT = 2,
+ MAIN_AXI_CLK_ROOT = 16,
+ DISP_AXI_CLK_ROOT = 17,
+ ENET_AXI_CLK_ROOT = 18,
+ NAND_USDHC_BUS_CLK_ROOT = 19,
+ AHB_CLK_ROOT = 32,
+ DRAM_PHYM_CLK_ROOT = 48,
+ DRAM_CLK_ROOT = 49,
+ DRAM_PHYM_ALT_CLK_ROOT = 64,
+ DRAM_ALT_CLK_ROOT = 65,
+ USB_HSIC_CLK_ROOT = 66,
+ PCIE_CTRL_CLK_ROOT = 67,
+ PCIE_PHY_CLK_ROOT = 68,
+ EPDC_PIXEL_CLK_ROOT = 69,
+ LCDIF_PIXEL_CLK_ROOT = 70,
+ MIPI_DSI_EXTSER_CLK_ROOT = 71,
+ MIPI_CSI_WARP_CLK_ROOT = 72,
+ MIPI_DPHY_REF_CLK_ROOT = 73,
+ SAI1_CLK_ROOT = 74,
+ SAI2_CLK_ROOT = 75,
+ SAI3_CLK_ROOT = 76,
+ SPDIF_CLK_ROOT = 77,
+ ENET1_REF_CLK_ROOT = 78,
+ ENET1_TIME_CLK_ROOT = 79,
+ ENET2_REF_CLK_ROOT = 80,
+ ENET2_TIME_CLK_ROOT = 81,
+ ENET_PHY_REF_CLK_ROOT = 82,
+ EIM_CLK_ROOT = 83,
+ NAND_CLK_ROOT = 84,
+ QSPI_CLK_ROOT = 85,
+ USDHC1_CLK_ROOT = 86,
+ USDHC2_CLK_ROOT = 87,
+ USDHC3_CLK_ROOT = 88,
+ CAN1_CLK_ROOT = 89,
+ CAN2_CLK_ROOT = 90,
+ I2C1_CLK_ROOT = 91,
+ I2C2_CLK_ROOT = 92,
+ I2C3_CLK_ROOT = 93,
+ I2C4_CLK_ROOT = 94,
+ UART1_CLK_ROOT = 95,
+ UART2_CLK_ROOT = 96,
+ UART3_CLK_ROOT = 97,
+ UART4_CLK_ROOT = 98,
+ UART5_CLK_ROOT = 99,
+ UART6_CLK_ROOT = 100,
+ UART7_CLK_ROOT = 101,
+ ECSPI1_CLK_ROOT = 102,
+ ECSPI2_CLK_ROOT = 103,
+ ECSPI3_CLK_ROOT = 104,
+ ECSPI4_CLK_ROOT = 105,
+ PWM1_CLK_ROOT = 106,
+ PWM2_CLK_ROOT = 107,
+ PWM3_CLK_ROOT = 108,
+ PWM4_CLK_ROOT = 109,
+ FLEXTIMER1_CLK_ROOT = 110,
+ FLEXTIMER2_CLK_ROOT = 111,
+ SIM1_CLK_ROOT = 112,
+ SIM2_CLK_ROOT = 113,
+ GPT1_CLK_ROOT = 114,
+ GPT2_CLK_ROOT = 115,
+ GPT3_CLK_ROOT = 116,
+ GPT4_CLK_ROOT = 117,
+ TRACE_CLK_ROOT = 118,
+ WDOG_CLK_ROOT = 119,
+ CSI_MCLK_CLK_ROOT = 120,
+ AUDIO_MCLK_CLK_ROOT = 121,
+ WRCLK_CLK_ROOT = 122,
+ IPP_DO_CLKO1 = 123,
+ IPP_DO_CLKO2 = 124,
+
+ CLK_ROOT_MAX,
+};
+
+struct clk_root_setting {
+ enum clk_root_index root;
+ u32 setting;
+};
+
+/*
+ * CCGR mapping
+ */
+enum clk_ccgr_index {
+ CCGR_CPU = 0,
+ CCGR_M4 = 1,
+ CCGR_SIM_MAIN = 4,
+ CCGR_SIM_DISPLAY = 5,
+ CCGR_SIM_ENET = 6,
+ CCGR_SIM_M = 7,
+ CCGR_SIM_S = 8,
+ CCGR_SIM_WAKEUP = 9,
+ CCGR_IPMUX1 = 10,
+ CCGR_IPMUX2 = 11,
+ CCGR_IPMUX3 = 12,
+ CCGR_ROM = 16,
+ CCGR_OCRAM = 17,
+ CCGR_OCRAM_S = 18,
+ CCGR_DRAM = 19,
+ CCGR_RAWNAND = 20,
+ CCGR_QSPI = 21,
+ CCGR_WEIM = 22,
+ CCGR_ADC = 32,
+ CCGR_ANATOP = 33,
+ CCGR_SCTR = 34,
+ CCGR_OCOTP = 35,
+ CCGR_CAAM = 36,
+ CCGR_SNVS = 37,
+ CCGR_RDC = 38,
+ CCGR_MU = 39,
+ CCGR_HS = 40,
+ CCGR_DVFS = 41,
+ CCGR_QOS = 42,
+ CCGR_QOS_DISPMIX = 43,
+ CCGR_QOS_MEGAMIX = 44,
+ CCGR_CSU = 45,
+ CCGR_DBGMON = 46,
+ CCGR_DEBUG = 47,
+ CCGR_TRACE = 48,
+ CCGR_SEC_DEBUG = 49,
+ CCGR_SEMA1 = 64,
+ CCGR_SEMA2 = 65,
+ CCGR_PERFMON1 = 68,
+ CCGR_PERFMON2 = 69,
+ CCGR_SDMA = 72,
+ CCGR_CSI = 73,
+ CCGR_EPDC = 74,
+ CCGR_LCDIF = 75,
+ CCGR_PXP = 76,
+ CCGR_PCIE = 96,
+ CCGR_MIPI_CSI = 100,
+ CCGR_MIPI_DSI = 101,
+ CCGR_MIPI_MEM_PHY = 102,
+ CCGR_USB_CTRL = 104,
+ CCGR_USB_HSIC = 105,
+ CCGR_USB_PHY1 = 106,
+ CCGR_USB_PHY2 = 107,
+ CCGR_USDHC1 = 108,
+ CCGR_USDHC2 = 109,
+ CCGR_USDHC3 = 110,
+ CCGR_ENET1 = 112,
+ CCGR_ENET2 = 113,
+ CCGR_CAN1 = 116,
+ CCGR_CAN2 = 117,
+ CCGR_ECSPI1 = 120,
+ CCGR_ECSPI2 = 121,
+ CCGR_ECSPI3 = 122,
+ CCGR_ECSPI4 = 123,
+ CCGR_GPT1 = 124,
+ CCGR_GPT2 = 125,
+ CCGR_GPT3 = 126,
+ CCGR_GPT4 = 127,
+ CCGR_FTM1 = 128,
+ CCGR_FTM2 = 129,
+ CCGR_PWM1 = 132,
+ CCGR_PWM2 = 133,
+ CCGR_PWM3 = 134,
+ CCGR_PWM4 = 135,
+ CCGR_I2C1 = 136,
+ CCGR_I2C2 = 137,
+ CCGR_I2C3 = 138,
+ CCGR_I2C4 = 139,
+ CCGR_SAI1 = 140,
+ CCGR_SAI2 = 141,
+ CCGR_SAI3 = 142,
+ CCGR_SIM1 = 144,
+ CCGR_SIM2 = 145,
+ CCGR_UART1 = 148,
+ CCGR_UART2 = 149,
+ CCGR_UART3 = 150,
+ CCGR_UART4 = 151,
+ CCGR_UART5 = 152,
+ CCGR_UART6 = 153,
+ CCGR_UART7 = 154,
+ CCGR_WDOG1 = 156,
+ CCGR_WDOG2 = 157,
+ CCGR_WDOG3 = 158,
+ CCGR_WDOG4 = 159,
+ CCGR_GPIO1 = 160,
+ CCGR_GPIO2 = 161,
+ CCGR_GPIO3 = 162,
+ CCGR_GPIO4 = 163,
+ CCGR_GPIO5 = 164,
+ CCGR_GPIO6 = 165,
+ CCGR_GPIO7 = 166,
+ CCGR_IOMUX = 168,
+ CCGR_IOMUX_LPSR = 169,
+ CCGR_KPP = 170,
+
+ CCGR_SKIP,
+ CCGR_MAX,
+};
+
+/* Clock root channel */
+enum clk_root_type {
+ CCM_CORE_CHANNEL,
+ CCM_BUS_CHANNEL,
+ CCM_AHB_CHANNEL,
+ CCM_DRAM_PHYM_CHANNEL,
+ CCM_DRAM_CHANNEL,
+ CCM_IP_CHANNEL,
+};
+
+#include <asm/arch/clock_slice.h>
+
+/*
+ * entry: the clock root index
+ * type: ccm channel
+ * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
+ */
+struct clk_root_map {
+ enum clk_root_index entry;
+ enum clk_root_type type;
+ uint8_t src_mux[8];
+};
+
+enum enet_freq {
+ ENET_25MHz,
+ ENET_50MHz,
+ ENET_125MHz,
+};
+
+u32 get_root_clk(enum clk_root_index clock_id);
+u32 mxc_get_clock(enum mxc_clock clk);
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+void clock_init(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+#endif
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type);
+#endif
+int set_clk_qspi(void);
+int set_clk_nand(void);
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable);
+#endif
+void enable_usboh3_clk(unsigned char enable);
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable);
+#endif
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
+void enable_thermal_clk(void);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CLOCK_SLICE_H
+#define _ASM_ARCH_CLOCK_SLICE_H
+
+enum root_pre_div {
+ CLK_ROOT_PRE_DIV1 = 0,
+ CLK_ROOT_PRE_DIV2,
+ CLK_ROOT_PRE_DIV3,
+ CLK_ROOT_PRE_DIV4,
+ CLK_ROOT_PRE_DIV5,
+ CLK_ROOT_PRE_DIV6,
+ CLK_ROOT_PRE_DIV7,
+ CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+ CLK_ROOT_POST_DIV1 = 0,
+ CLK_ROOT_POST_DIV2,
+ CLK_ROOT_POST_DIV3,
+ CLK_ROOT_POST_DIV4,
+ CLK_ROOT_POST_DIV5,
+ CLK_ROOT_POST_DIV6,
+ CLK_ROOT_POST_DIV7,
+ CLK_ROOT_POST_DIV8,
+ CLK_ROOT_POST_DIV9,
+ CLK_ROOT_POST_DIV10,
+ CLK_ROOT_POST_DIV11,
+ CLK_ROOT_POST_DIV12,
+ CLK_ROOT_POST_DIV13,
+ CLK_ROOT_POST_DIV14,
+ CLK_ROOT_POST_DIV15,
+ CLK_ROOT_POST_DIV16,
+ CLK_ROOT_POST_DIV17,
+ CLK_ROOT_POST_DIV18,
+ CLK_ROOT_POST_DIV19,
+ CLK_ROOT_POST_DIV20,
+ CLK_ROOT_POST_DIV21,
+ CLK_ROOT_POST_DIV22,
+ CLK_ROOT_POST_DIV23,
+ CLK_ROOT_POST_DIV24,
+ CLK_ROOT_POST_DIV25,
+ CLK_ROOT_POST_DIV26,
+ CLK_ROOT_POST_DIV27,
+ CLK_ROOT_POST_DIV28,
+ CLK_ROOT_POST_DIV29,
+ CLK_ROOT_POST_DIV30,
+ CLK_ROOT_POST_DIV31,
+ CLK_ROOT_POST_DIV32,
+ CLK_ROOT_POST_DIV33,
+ CLK_ROOT_POST_DIV34,
+ CLK_ROOT_POST_DIV35,
+ CLK_ROOT_POST_DIV36,
+ CLK_ROOT_POST_DIV37,
+ CLK_ROOT_POST_DIV38,
+ CLK_ROOT_POST_DIV39,
+ CLK_ROOT_POST_DIV40,
+ CLK_ROOT_POST_DIV41,
+ CLK_ROOT_POST_DIV42,
+ CLK_ROOT_POST_DIV43,
+ CLK_ROOT_POST_DIV44,
+ CLK_ROOT_POST_DIV45,
+ CLK_ROOT_POST_DIV46,
+ CLK_ROOT_POST_DIV47,
+ CLK_ROOT_POST_DIV48,
+ CLK_ROOT_POST_DIV49,
+ CLK_ROOT_POST_DIV50,
+ CLK_ROOT_POST_DIV51,
+ CLK_ROOT_POST_DIV52,
+ CLK_ROOT_POST_DIV53,
+ CLK_ROOT_POST_DIV54,
+ CLK_ROOT_POST_DIV55,
+ CLK_ROOT_POST_DIV56,
+ CLK_ROOT_POST_DIV57,
+ CLK_ROOT_POST_DIV58,
+ CLK_ROOT_POST_DIV59,
+ CLK_ROOT_POST_DIV60,
+ CLK_ROOT_POST_DIV61,
+ CLK_ROOT_POST_DIV62,
+ CLK_ROOT_POST_DIV63,
+ CLK_ROOT_POST_DIV64,
+};
+
+enum root_auto_div {
+ CLK_ROOT_AUTO_DIV1 = 0,
+ CLK_ROOT_AUTO_DIV2,
+ CLK_ROOT_AUTO_DIV4,
+ CLK_ROOT_AUTO_DIV8,
+ CLK_ROOT_AUTO_DIV16,
+};
+
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+ int auto_en);
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+ int *auto_en);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_root_enabled(enum clk_root_index clock_id);
+
+int clock_enable(enum clk_ccgr_index index, bool enable);
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__
+
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+
+#define CCM_GPR0_OFFSET 0x0
+#define CCM_OBSERVE0_OFFSET 0x0400
+#define CCM_SCTRL0_OFFSET 0x0800
+#define CCM_CCGR0_OFFSET 0x4000
+#define CCM_ROOT0_TARGET_OFFSET 0x8000
+
+#ifndef __ASSEMBLY__
+
+struct mxc_ccm_ccgr {
+ uint32_t ccgr;
+ uint32_t ccgr_set;
+ uint32_t ccgr_clr;
+ uint32_t ccgr_tog;
+};
+
+struct mxc_ccm_root_slice {
+ uint32_t target_root;
+ uint32_t target_root_set;
+ uint32_t target_root_clr;
+ uint32_t target_root_tog;
+ uint32_t reserved_0[4];
+ uint32_t post;
+ uint32_t post_root_set;
+ uint32_t post_root_clr;
+ uint32_t post_root_tog;
+ uint32_t pre;
+ uint32_t pre_root_set;
+ uint32_t pre_root_clr;
+ uint32_t pre_root_tog;
+ uint32_t reserved_1[12];
+ uint32_t access_ctrl;
+ uint32_t access_ctrl_root_set;
+ uint32_t access_ctrl_root_clr;
+ uint32_t access_ctrl_root_tog;
+};
+
+/** CCM - Peripheral register structure */
+struct mxc_ccm_reg {
+ uint32_t gpr0;
+ uint32_t gpr0_set;
+ uint32_t gpr0_clr;
+ uint32_t gpr0_tog;
+ uint32_t reserved_0[4092];
+ struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
+ uint32_t reserved_1[3332];
+ struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
+
+};
+
+struct mxc_ccm_anatop_reg {
+ uint32_t ctrl_24m; /* offset 0x0000 */
+ uint32_t ctrl_24m_set;
+ uint32_t ctrl_24m_clr;
+ uint32_t ctrl_24m_tog;
+ uint32_t rcosc_config0; /* offset 0x0010 */
+ uint32_t rcosc_config0_set;
+ uint32_t rcosc_config0_clr;
+ uint32_t rcosc_config0_tog;
+ uint32_t rcosc_config1; /* offset 0x0020 */
+ uint32_t rcosc_config1_set;
+ uint32_t rcosc_config1_clr;
+ uint32_t rcosc_config1_tog;
+ uint32_t rcosc_config2; /* offset 0x0030 */
+ uint32_t rcosc_config2_set;
+ uint32_t rcosc_config2_clr;
+ uint32_t rcosc_config2_tog;
+ uint8_t reserved_0[16];
+ uint32_t osc_32k; /* offset 0x0050 */
+ uint32_t osc_32k_set;
+ uint32_t osc_32k_clr;
+ uint32_t osc_32k_tog;
+ uint32_t pll_arm; /* offset 0x0060 */
+ uint32_t pll_arm_set;
+ uint32_t pll_arm_clr;
+ uint32_t pll_arm_tog;
+ uint32_t pll_ddr; /* offset 0x0070 */
+ uint32_t pll_ddr_set;
+ uint32_t pll_ddr_clr;
+ uint32_t pll_ddr_tog;
+ uint32_t pll_ddr_ss; /* offset 0x0080 */
+ uint8_t reserved_1[12];
+ uint32_t pll_ddr_num; /* offset 0x0090 */
+ uint8_t reserved_2[12];
+ uint32_t pll_ddr_denom; /* offset 0x00a0 */
+ uint8_t reserved_3[12];
+ uint32_t pll_480; /* offset 0x00b0 */
+ uint32_t pll_480_set;
+ uint32_t pll_480_clr;
+ uint32_t pll_480_tog;
+ uint32_t pfd_480a; /* offset 0x00c0 */
+ uint32_t pfd_480a_set;
+ uint32_t pfd_480a_clr;
+ uint32_t pfd_480a_tog;
+ uint32_t pfd_480b; /* offset 0x00d0 */
+ uint32_t pfd_480b_set;
+ uint32_t pfd_480b_clr;
+ uint32_t pfd_480b_tog;
+ uint32_t pll_enet; /* offset 0x00e0 */
+ uint32_t pll_enet_set;
+ uint32_t pll_enet_clr;
+ uint32_t pll_enet_tog;
+ uint32_t pll_audio; /* offset 0x00f0 */
+ uint32_t pll_audio_set;
+ uint32_t pll_audio_clr;
+ uint32_t pll_audio_tog;
+ uint32_t pll_audio_ss; /* offset 0x0100 */
+ uint8_t reserved_4[12];
+ uint32_t pll_audio_num; /* offset 0x0110 */
+ uint8_t reserved_5[12];
+ uint32_t pll_audio_denom; /* offset 0x0120 */
+ uint8_t reserved_6[12];
+ uint32_t pll_video; /* offset 0x0130 */
+ uint32_t pll_video_set;
+ uint32_t pll_video_clr;
+ uint32_t pll_video_tog;
+ uint32_t pll_video_ss; /* offset 0x0140 */
+ uint8_t reserved_7[12];
+ uint32_t pll_video_num; /* offset 0x0150 */
+ uint8_t reserved_8[12];
+ uint32_t pll_video_denom; /* offset 0x0160 */
+ uint8_t reserved_9[12];
+ uint32_t clk_misc0; /* offset 0x0170 */
+ uint32_t clk_misc0_set;
+ uint32_t clk_misc0_clr;
+ uint32_t clk_misc0_tog;
+ uint32_t clk_rsvd; /* offset 0x0180 */
+ uint8_t reserved_10[124];
+ uint32_t reg_1p0a; /* offset 0x0200 */
+ uint32_t reg_1p0a_set;
+ uint32_t reg_1p0a_clr;
+ uint32_t reg_1p0a_tog;
+ uint32_t reg_1p0d; /* offsest 0x0210 */
+ uint32_t reg_1p0d_set;
+ uint32_t reg_1p0d_clr;
+ uint32_t reg_1p0d_tog;
+ uint32_t reg_hsic_1p2; /* offset 0x0220 */
+ uint32_t reg_hsic_1p2_set;
+ uint32_t reg_hsic_1p2_clr;
+ uint32_t reg_hsic_1p2_tog;
+ uint32_t reg_lpsr_1p0; /* offset 0x0230 */
+ uint32_t reg_lpsr_1p0_set;
+ uint32_t reg_lpsr_1p0_clr;
+ uint32_t reg_lpsr_1p0_tog;
+ uint32_t reg_3p0; /* offset 0x0240 */
+ uint32_t reg_3p0_set;
+ uint32_t reg_3p0_clr;
+ uint32_t reg_3p0_tog;
+ uint32_t reg_snvs; /* offset 0x0250 */
+ uint32_t reg_snvs_set;
+ uint32_t reg_snvs_clr;
+ uint32_t reg_snvs_tog;
+ uint32_t analog_debug_misc0; /* offset 0x0260 */
+ uint32_t analog_debug_misc0_set;
+ uint32_t analog_debug_misc0_clr;
+ uint32_t analog_debug_misc0_tog;
+ uint32_t ref; /* offset 0x0270 */
+ uint32_t ref_set;
+ uint32_t ref_clr;
+ uint32_t ref_tog;
+ uint8_t reserved_11[128];
+ uint32_t tempsense0; /* offset 0x0300 */
+ uint32_t tempsense0_set;
+ uint32_t tempsense0_clr;
+ uint32_t tempsense0_tog;
+ uint32_t tempsense1; /* offset 0x0310 */
+ uint32_t tempsense1_set;
+ uint32_t tempsense1_clr;
+ uint32_t tempsense1_tog;
+ uint32_t tempsense_trim; /* offset 0x0320 */
+ uint32_t tempsense_trim_set;
+ uint32_t tempsense_trim_clr;
+ uint32_t tempsense_trim_tog;
+ uint32_t lowpwr_ctrl; /* offset 0x0330 */
+ uint32_t lowpwr_ctrl_set;
+ uint32_t lowpwr_ctrl_clr;
+ uint32_t lowpwr_ctrl_tog;
+ uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */
+ uint32_t snvs_tamper_offset_ctrl_set;
+ uint32_t snvs_tamper_offset_ctrl_clr;
+ uint32_t snvs_tamper_offset_ctrl_tog;
+ uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */
+ uint32_t snvs_tamper_pull_ctrl_set;
+ uint32_t snvs_tamper_pull_ctrl_clr;
+ uint32_t snvs_tamper_pull_ctrl_tog;
+ uint32_t snvs_test; /* offset 0x0360 */
+ uint32_t snvs_test_set;
+ uint32_t snvs_test_clr;
+ uint32_t snvs_test_tog;
+ uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */
+ uint32_t snvs_tamper_trim_ctrl_set;
+ uint32_t snvs_tamper_trim_ctrl_ctrl;
+ uint32_t snvs_tamper_trim_ctrl_tog;
+ uint32_t snvs_misc_ctrl; /* offset 0x0380 */
+ uint32_t snvs_misc_ctrl_set;
+ uint32_t snvs_misc_ctrl_clr;
+ uint32_t snvs_misc_ctrl_tog;
+ uint8_t reserved_12[112];
+ uint32_t misc; /* offset 0x0400 */
+ uint8_t reserved_13[252];
+ uint32_t adc0; /* offset 0x0500 */
+ uint8_t reserved_14[12];
+ uint32_t adc1; /* offset 0x0510 */
+ uint8_t reserved_15[748];
+ uint32_t digprog; /* offset 0x0800 */
+};
+#endif
+
+#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17)
+
+#define ANADIG_PLL_LOCK 0x80000000
+
+#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12)
+#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12)
+#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20)
+#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5)
+#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12)
+
+
+#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f
+#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B
+#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016
+#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014
+
+/* PLL_ARM Bit Fields */
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80
+#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100
+#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200
+#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400
+#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800
+#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000
+#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000
+#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17
+#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000
+#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19
+#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000
+#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20
+#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000
+#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31
+
+/* PLL_DDR Bit Fields */
+#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F
+#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80
+#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100
+#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200
+#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400
+#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800
+#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000
+#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12
+#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000
+#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000
+#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000
+#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000
+#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19
+#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000
+#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20
+#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000
+#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21
+#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000
+#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23
+#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31
+
+/* PLL_480 Bit Fields */
+#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1
+#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE
+#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1
+#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10
+#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4
+#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20
+#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5
+#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40
+#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6
+#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80
+#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100
+#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200
+#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400
+#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800
+#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000
+#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000
+#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000
+#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17
+#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000
+#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18
+#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000
+#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19
+#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000
+#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20
+#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000
+#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21
+#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000
+#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22
+#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000
+#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23
+#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000
+#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000
+#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25
+#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000
+#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26
+#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000
+#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27
+#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000
+#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28
+#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000
+#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29
+#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31
+
+/* PFD_480A Bit Fields */
+#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F
+#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0
+#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40
+#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6
+#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80
+#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7
+#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00
+#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8
+#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000
+#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14
+#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000
+#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15
+#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000
+#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16
+#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000
+#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22
+#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000
+#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23
+#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000
+#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24
+#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000
+#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30
+#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000
+#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31
+/* PFD_480B Bit Fields */
+#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F
+#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0
+#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40
+#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6
+#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80
+#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7
+#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00
+#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8
+#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000
+#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14
+#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000
+#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15
+#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000
+#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16
+#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000
+#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22
+#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000
+#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23
+#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000
+#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24
+#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000
+#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30
+#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000
+#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31
+
+/* PLL_ENET Bit Fields */
+#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1
+#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0
+#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2
+#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1
+#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4
+#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2
+#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8
+#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3
+#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10
+#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12
+#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000
+#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000
+#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000
+#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19
+#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31
+
+/* PLL_AUDIO Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31
+/* PLL_AUDIO_SET Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31
+/* PLL_AUDIO_CLR Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31
+/* PLL_AUDIO_TOG Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31
+/* PLL_AUDIO_SS Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u
+#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK)
+/* PLL_AUDIO_NUM Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK)
+/* PLL_AUDIO_DENOM Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK)
+/* PLL_VIDEO Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31
+/* PLL_VIDEO_SET Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31
+/* PLL_VIDEO_CLR Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31
+/* PLL_VIDEO_TOG Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31
+/* PLL_VIDEO_SS Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u
+#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK)
+/* PLL_VIDEO_NUM Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK)
+/* PLL_VIDEO_DENOM Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK)
+/* CLK_MISC0 Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK)
+/* CLK_MISC0_SET Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK)
+/* CLK_MISC0_CLR Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK)
+/* CLK_MISC0_TOG Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK)
+
+/* REG_1P0A Bit Fields */
+#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK)
+#define PMU_REG_1P0A_BO_MASK 0x10000u
+#define PMU_REG_1P0A_BO_SHIFT 16
+#define PMU_REG_1P0A_OK_MASK 0x20000u
+#define PMU_REG_1P0A_OK_SHIFT 17
+#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK)
+#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK)
+/* REG_1P0A_SET Bit Fields */
+#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK)
+#define PMU_REG_1P0A_SET_BO_MASK 0x10000u
+#define PMU_REG_1P0A_SET_BO_SHIFT 16
+#define PMU_REG_1P0A_SET_OK_MASK 0x20000u
+#define PMU_REG_1P0A_SET_OK_SHIFT 17
+#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK)
+#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK)
+/* REG_1P0A_CLR Bit Fields */
+#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK)
+#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u
+#define PMU_REG_1P0A_CLR_BO_SHIFT 16
+#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u
+#define PMU_REG_1P0A_CLR_OK_SHIFT 17
+#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK)
+#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK)
+/* REG_1P0A_TOG Bit Fields */
+#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK)
+#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u
+#define PMU_REG_1P0A_TOG_BO_SHIFT 16
+#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u
+#define PMU_REG_1P0A_TOG_OK_SHIFT 17
+#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK)
+#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK)
+/* REG_1P0D Bit Fields */
+#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK)
+#define PMU_REG_1P0D_BO_MASK 0x10000u
+#define PMU_REG_1P0D_BO_SHIFT 16
+#define PMU_REG_1P0D_OK_MASK 0x20000u
+#define PMU_REG_1P0D_OK_SHIFT 17
+#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK)
+#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK)
+#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_OVERRIDE_SHIFT 31
+/* REG_1P0D_SET Bit Fields */
+#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK)
+#define PMU_REG_1P0D_SET_BO_MASK 0x10000u
+#define PMU_REG_1P0D_SET_BO_SHIFT 16
+#define PMU_REG_1P0D_SET_OK_MASK 0x20000u
+#define PMU_REG_1P0D_SET_OK_SHIFT 17
+#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK)
+#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK)
+#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31
+/* REG_1P0D_CLR Bit Fields */
+#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK)
+#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u
+#define PMU_REG_1P0D_CLR_BO_SHIFT 16
+#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u
+#define PMU_REG_1P0D_CLR_OK_SHIFT 17
+#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK)
+#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK)
+#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31
+/* REG_1P0D_TOG Bit Fields */
+#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK)
+#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u
+#define PMU_REG_1P0D_TOG_BO_SHIFT 16
+#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u
+#define PMU_REG_1P0D_TOG_OK_SHIFT 17
+#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK)
+#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK)
+#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2 Bit Fields */
+#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2_SET Bit Fields */
+#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2_CLR Bit Fields */
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2_TOG Bit Fields */
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31
+/* REG_LPSR_1P0 Bit Fields */
+#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK)
+/* REG_LPSR_1P0_SET Bit Fields */
+#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK)
+/* REG_LPSR_1P0_CLR Bit Fields */
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK)
+/* REG_LPSR_1P0_TOG Bit Fields */
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK)
+/* REG_3P0 Bit Fields */
+#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_RSVD0_SHIFT 3
+#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK)
+#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_RSVD1_SHIFT 13
+#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK)
+#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK)
+#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_RSVD2_SHIFT 22
+#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK)
+/* REG_3P0_SET Bit Fields */
+#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_SET_RSVD0_SHIFT 3
+#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK)
+#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_SET_RSVD1_SHIFT 13
+#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK)
+#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK)
+#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_SET_RSVD2_SHIFT 22
+#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK)
+/* REG_3P0_CLR Bit Fields */
+#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3
+#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK)
+#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13
+#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK)
+#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK)
+#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22
+#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK)
+/* REG_3P0_TOG Bit Fields */
+#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3
+#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK)
+#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13
+#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK)
+#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK)
+#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22
+#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK)
+/* REF Bit Fields */
+#define PMU_REF_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_REFTOP_PWD_SHIFT 0
+#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK)
+#define PMU_REF_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_LPBG_SEL_MASK 0x400u
+#define PMU_REF_LPBG_SEL_SHIFT 10
+#define PMU_REF_LPBG_TEST_MASK 0x800u
+#define PMU_REF_LPBG_TEST_SHIFT 11
+#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_RSVD1_SHIFT 14
+#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK)
+/* REF_SET Bit Fields */
+#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_SET_REFTOP_PWD_SHIFT 0
+#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK)
+#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_SET_LPBG_SEL_MASK 0x400u
+#define PMU_REF_SET_LPBG_SEL_SHIFT 10
+#define PMU_REF_SET_LPBG_TEST_MASK 0x800u
+#define PMU_REF_SET_LPBG_TEST_SHIFT 11
+#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_SET_RSVD1_SHIFT 14
+#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK)
+/* REF_CLR Bit Fields */
+#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0
+#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK)
+#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u
+#define PMU_REF_CLR_LPBG_SEL_SHIFT 10
+#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u
+#define PMU_REF_CLR_LPBG_TEST_SHIFT 11
+#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_CLR_RSVD1_SHIFT 14
+#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK)
+/* REF_TOG Bit Fields */
+#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0
+#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK)
+#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u
+#define PMU_REF_TOG_LPBG_SEL_SHIFT 10
+#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u
+#define PMU_REF_TOG_LPBG_TEST_SHIFT 11
+#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_TOG_RSVD1_SHIFT 14
+#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK)
+/* LOWPWR_CTRL Bit Fields */
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK)
+/* LOWPWR_CTRL_SET Bit Fields */
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK)
+/* LOWPWR_CTRL_CLR Bit Fields */
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK)
+/* LOWPWR_CTRL_TOG Bit Fields */
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
+
+
+/* HW_ANADIG_TEMPSENSE0 Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE1 Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
+
+
+#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i))
+#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i))
+#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i))
+#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i))
+#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
+
+#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
+#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
+#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
+
+#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
+#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
+#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
+
+#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
+#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
+#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
+
+#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i))
+#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i))
+#define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i))
+#define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i))
+#define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i))
+
+#define HW_CCM_GPR_RD(i) readl(CCM_GPR(i))
+#define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i))
+#define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i))
+#define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i))
+#define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i))
+
+#define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i))
+#define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i))
+#define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i))
+#define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i))
+#define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i))
+
+#define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i))
+#define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i))
+#define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i))
+#define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i))
+#define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i))
+
+#define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i))
+#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i))
+#define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i))
+#define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i))
+#define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i))
+
+#define CCM_CLK_ON_MSK 0x03
+
+#define CCM_ROOT_TGT_POST_DIV_SHIFT 0
+#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15
+#define CCM_ROOT_TGT_MUX_SHIFT 24
+#define CCM_ROOT_TGT_ENABLE_SHIFT 28
+#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F
+#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT)
+#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT)
+#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT)
+
+#define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK)
+#define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK)
+#define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK)
+
+/*
+ * Field values definition for clock slice TARGET register
+ */
+
+#define CLK_ROOT_ON 0x10000000
+#define CLK_ROOT_OFF 0x0
+#define CLK_ROOT_ENABLE_MASK 0x10000000
+#define CLK_ROOT_ENABLE_SHIFT 28
+
+#define CLK_ROOT_ALT0 0x00000000
+#define CLK_ROOT_ALT1 0x01000000
+#define CLK_ROOT_ALT2 0x02000000
+#define CLK_ROOT_ALT3 0x03000000
+#define CLK_ROOT_ALT4 0x04000000
+#define CLK_ROOT_ALT5 0x05000000
+#define CLK_ROOT_ALT6 0x06000000
+#define CLK_ROOT_ALT7 0x07000000
+
+
+#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007
+#define CLK_ROOT_POST_DIV_MASK 0x0000003f
+#define CLK_ROOT_POST_DIV_SHIFT 0
+#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK)
+
+#define CLK_ROOT_AUTO_DIV_MASK 0x00000700
+#define CLK_ROOT_AUTO_DIV_SHIFT 8
+#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK)
+
+#define CLK_ROOT_AUTO_EN_MASK 0x00001000
+#define CLK_ROOT_AUTO_EN 0x00001000
+
+#define CLK_ROOT_PRE_DIV_MASK 0x00070000
+#define CLK_ROOT_PRE_DIV_SHIFT 16
+#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK)
+
+#define CLK_ROOT_MUX_MASK 0x07000000
+#define CLK_ROOT_MUX_SHIFT 24
+
+#define CLK_ROOT_EN_MASK 0x10000000
+
+#define CLK_ROOT_AUTO_ON 0x00001000
+#define CLK_ROOT_AUTO_OFF 0x0
+
+/* ARM_A7_CLK_ROOT */
+#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ARM_M4_CLK_ROOT */
+#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ARM_M0_CLK_ROOT */
+#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* MAIN_AXI_CLK_ROOT */
+#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* DISP_AXI_CLK_ROOT */
+#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+
+/* ENET_AXI_CLK_ROOT */
+#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* NAND_USDHC_BUS_CLK_ROOT */
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
+
+/* AHB_CLK_ROOT */
+#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000
+#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+
+/* DRAM_PHYM_CLK_ROOT */
+#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000
+#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000
+
+/* DRAM_CLK_ROOT */
+#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000
+#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000
+
+/* DRAM_PHYM_ALT_CLK_ROOT */
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
+
+/* DRAM_ALT_CLK_ROOT */
+#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+
+/* USB_HSIC_CLK_ROOT */
+#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000
+
+/* PCIE_CTRL_CLK_ROOT */
+#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000
+
+/* PCIE_PHY_CLK_ROOT */
+#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* EPDC_PIXEL_CLK_ROOT */
+#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+
+/* LCDIF_PIXEL_CLK_ROOT */
+#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000
+
+/* MIPI_DSI_EXTSER_CLK_ROOT */
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* MIPI_CSI_WARP_CLK_ROOT */
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* MIPI_DPHY_REF_CLK_ROOT */
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* SAI1_CLK_ROOT */
+#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
+
+/* SAI2_CLK_ROOT */
+#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
+
+/* SAI3_CLK_ROOT */
+#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* SPDIF_CLK_ROOT */
+#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* ENET1_REF_CLK_ROOT */
+#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* ENET1_TIME_CLK_ROOT */
+#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* ENET2_REF_CLK_ROOT */
+#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* ENET2_TIME_CLK_ROOT */
+#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* ENET_PHY_REF_CLK_ROOT */
+#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* EIM_CLK_ROOT */
+#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000
+#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* NAND_CLK_ROOT */
+#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000
+#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
+#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+
+/* QSPI_CLK_ROOT */
+#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* USDHC1_CLK_ROOT */
+#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* USDHC2_CLK_ROOT */
+#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* USDHC3_CLK_ROOT */
+#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* CAN1_CLK_ROOT */
+#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000
+#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
+#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* CAN2_CLK_ROOT */
+#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000
+#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
+#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* I2C1_CLK_ROOT */
+#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* I2C2_CLK_ROOT */
+#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* I2C3_CLK_ROOT */
+#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* I2C4_CLK_ROOT */
+#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* UART1_CLK_ROOT */
+#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* UART2_CLK_ROOT */
+#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
+
+/* UART3_CLK_ROOT */
+#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* UART4_CLK_ROOT */
+#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
+
+/* UART5_CLK_ROOT */
+#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* UART6_CLK_ROOT */
+#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
+
+/* UART7_CLK_ROOT */
+#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* ECSPI1_CLK_ROOT */
+#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ECSPI2_CLK_ROOT */
+#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ECSPI3_CLK_ROOT */
+#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ECSPI4_CLK_ROOT */
+#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* PWM1_CLK_ROOT */
+#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000
+
+/* PWM2_CLK_ROOT */
+#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000
+
+/* PWM3_CLK_ROOT */
+#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+
+/* PWM4_CLK_ROOT */
+#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+
+/* FLEXTIMER1_CLK_ROOT */
+#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+
+/* FLEXTIMER2_CLK_ROOT */
+#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+
+/* SIM1_CLK_ROOT */
+#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
+
+/* SIM2_CLK_ROOT */
+#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
+
+/* GPT1_CLK_ROOT */
+#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000
+
+/* GPT2_CLK_ROOT */
+#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
+
+/* GPT3_CLK_ROOT */
+#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* GPT4_CLK_ROOT */
+#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* TRACE_CLK_ROOT */
+#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
+#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* WDOG_CLK_ROOT */
+#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+
+/* CSI_MCLK_CLK_ROOT */
+#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* AUDIO_MCLK_CLK_ROOT */
+#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* WRCLK_CLK_ROOT */
+#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000
+#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000
+#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000
+
+/* IPP_DO_CLKO1 */
+#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000
+#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000
+#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
+#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000
+
+/* IPP_DO_CLKO2 */
+#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX7_IMX_REGS_H__
+#define __ASM_ARCH_MX7_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define ROM_SW_INFO_ADDR 0x000001E8
+#define ROMCP_ARB_BASE_ADDR 0x00000000
+#define ROMCP_ARB_END_ADDR 0x00017FFF
+#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00107FFF
+#define GIC400_ARB_BASE_ADDR 0x31000000
+#define GIC400_ARB_END_ADDR 0x31007FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR 0x33007FFF
+#define M4_BOOTROM_BASE_ADDR 0x00180000
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#define GPV0_BASE_ADDR 0x32000000
+#define GPV1_BASE_ADDR 0x32100000
+#define GPV2_BASE_ADDR 0x32200000
+#define GPV3_BASE_ADDR 0x32300000
+#define GPV4_BASE_ADDR 0x32400000
+#define GPV5_BASE_ADDR 0x32500000
+#define GPV6_BASE_ADDR 0x32600000
+#define GPV7_BASE_ADDR 0x32700000
+
+#define OCRAM_ARB_BASE_ADDR 0x00900000
+#define OCRAM_ARB_END_ADDR 0x0091FFFF
+#define OCRAM_EPDC_BASE_ADDR 0x00920000
+#define OCRAM_EPDC_END_ADDR 0x0093FFFF
+#define OCRAM_PXP_BASE_ADDR 0x00940000
+#define OCRAM_PXP_END_ADDR 0x00947FFF
+#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
+#define IRAM_SIZE 0x00020000
+
+#define AIPS1_ARB_BASE_ADDR 0x30000000
+#define AIPS1_ARB_END_ADDR 0x303FFFFF
+#define AIPS2_ARB_BASE_ADDR 0x30400000
+#define AIPS2_ARB_END_ADDR 0x307FFFFF
+#define AIPS3_ARB_BASE_ADDR 0x30800000
+#define AIPS3_ARB_END_ADDR 0x30BFFFFF
+
+#define WEIM_ARB_BASE_ADDR 0x28000000
+#define WEIM_ARB_END_ADDR 0x2FFFFFFF
+
+#define QSPI0_ARB_BASE_ADDR 0x60000000
+#define QSPI0_ARB_END_ADDR 0x6FFFFFFF
+#define PCIE_ARB_BASE_ADDR 0x40000000
+#define PCIE_ARB_END_ADDR 0x4FFFFFFF
+#define PCIE_REG_BASE_ADDR 0x33800000
+#define PCIE_REG_END_ADDR 0x33803FFF
+
+#define MMDC0_ARB_BASE_ADDR 0x80000000
+#define MMDC0_ARB_END_ADDR 0xBFFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0xC0000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+
+/* Cortex-A9 MPCore private memory region */
+#define ARM_PERIPHBASE 0x31000000
+#define SCU_BASE_ADDR ARM_PERIPHBASE
+#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
+#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
+
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
+#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
+
+/* DAP base-address */
+#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR
+
+/* AIPS_TZ#1- On Platform */
+#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#1- Off Platform */
+#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
+
+#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR
+#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
+#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
+#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
+#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
+#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
+#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
+#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
+#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
+#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
+#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
+#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
+#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
+#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
+#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
+#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
+#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
+#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
+#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
+#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
+#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
+#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR
+#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
+#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
+#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
+#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
+#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
+#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
+#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
+#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
+#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
+#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
+#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
+
+/* AIPS_TZ#2- On Platform */
+#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#2- Off Platform */
+#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
+#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
+#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
+#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
+#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
+#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
+#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
+#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
+#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
+#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
+#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
+#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
+#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
+#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
+#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
+#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR
+#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
+#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
+#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
+#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
+#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
+#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
+#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
+#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
+#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
+#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
+#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
+#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
+
+/* AIPS_TZ#3 - Global enable (0) */
+#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
+#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
+#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
+#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
+#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
+#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
+#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
+#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
+#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
+#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
+#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
+
+/* AIPS_TZ#3- On Platform */
+#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#3- Off Platform */
+#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
+#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR
+#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
+#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
+#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
+#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
+#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
+#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
+#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
+#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
+#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
+#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
+#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
+#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
+#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
+#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
+#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
+#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
+#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
+#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
+#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
+#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
+#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
+#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
+#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
+#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
+#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
+#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
+#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
+#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
+
+#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
+
+#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
+#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
+
+#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
+#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
+
+#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
+
+#define FEC_QUIRK_ENET_MAC
+#define SNVS_LPGPR 0x68
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 a7rcr0;
+ u32 a7rcr1;
+ u32 m4rcr;
+ u32 reserved1;
+ u32 ercr;
+ u32 reserved2;
+ u32 hsicphy_rcr;
+ u32 usbophy1_rcr;
+ u32 usbophy2_rcr;
+ u32 mipiphy_rcr;
+ u32 pciephy_rcr;
+ u32 reserved3[10];
+ u32 sbmr1;
+ u32 srsr;
+ u32 reserved4[2];
+ u32 sisr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 gpr5;
+ u32 gpr6;
+ u32 gpr7;
+ u32 gpr8;
+ u32 gpr9;
+ u32 gpr10;
+ u32 reserved5[985];
+ u32 ddrc_rcr;
+};
+
+/* GPR0 Bit Fields */
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
+/* GPR1 Bit Fields */
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
+#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
+#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
+#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
+#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
+#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
+#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
+#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16
+#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17
+#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
+#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18
+#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
+#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
+#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
+#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
+#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
+#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
+/* GPR2 Bit Fields */
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
+#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24
+#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25
+#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
+/* GPR3 Bit Fields */
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
+/* GPR4 Bit Fields */
+#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
+#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
+#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
+#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1
+#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
+#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2
+#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
+#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
+#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
+#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
+#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
+#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5
+#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
+#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6
+#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
+#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7
+#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
+#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16
+#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
+#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17
+#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
+#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18
+#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
+#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
+#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
+#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
+#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
+#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21
+#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
+#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22
+#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
+#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
+/* GPR5 Bit Fields */
+#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
+#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
+#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
+#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
+#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
+#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6
+#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
+#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
+#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
+#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19
+#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
+#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
+#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
+#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
+#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
+#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
+#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
+#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
+/* GPR6 Bit Fields */
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
+/* GPR7 Bit Fields */
+#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
+#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
+#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
+#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
+#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
+#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
+#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
+#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
+/* GPR8 Bit Fields */
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
+#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
+#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
+/* GPR9 Bit Fields */
+#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
+#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
+/* GPR10 Bit Fields */
+#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
+#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
+#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
+#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1
+#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
+/* GPR11 Bit Fields */
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
+/* GPR12 Bit Fields */
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
+/* GPR13 Bit Fields */
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
+/* GPR14 Bit Fields */
+#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
+#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
+#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
+#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
+/* GPR15 Bit Fields */
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
+/* GPR16 Bit Fields */
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
+#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
+#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
+/* GPR17 Bit Fields */
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
+/* GPR18 Bit Fields */
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
+#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
+#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
+/* GPR19 Bit Fields */
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
+#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
+/* GPR20 Bit Fields */
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24
+#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
+/* GPR21 Bit Fields */
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
+#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
+#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
+#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
+#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
+/* GPR22 Bit Fields */
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
+#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
+#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
+#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
+#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
+#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
+#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
+#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
+#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
+#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
+#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
+#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
+#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
+#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
+#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
+
+#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
+#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
+#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
+
+struct iomuxc {
+ u32 gpr[23];
+ /* mux and pad registers */
+};
+
+struct iomuxc_gpr_base_regs {
+ u32 gpr[23]; /* 0x000 */
+};
+
+/* ECSPI registers */
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 cfg;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR
+
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data0;
+ u32 rsvd1[3];
+ u32 data1;
+ u32 rsvd2[3];
+ u32 data2;
+ u32 rsvd3[3];
+ u32 data3;
+ u32 rsvd4[3];
+ u32 read_ctrl;
+ u32 rsvd5[3];
+ u32 read_fuse_data0;
+ u32 rsvd6[3];
+ u32 read_fuse_data1;
+ u32 rsvd7[3];
+ u32 read_fuse_data2;
+ u32 rsvd8[3];
+ u32 read_fuse_data3;
+ u32 rsvd9[3];
+ u32 sw_sticky;
+ u32 rsvd10[3];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd11[3];
+ u32 crc_value;
+ u32 rsvd12[3];
+ u32 version;
+ u32 rsvd13[0xc3];
+
+ struct fuse_bank { /* offset 0x400 */
+ u32 fuse_regs[0x10];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 tester0;
+ u32 rsvd1[3];
+ u32 tester1;
+ u32 rsvd2[3];
+ u32 tester2;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank1_regs {
+ u32 tester3;
+ u32 rsvd0[3];
+ u32 tester4;
+ u32 rsvd1[3];
+ u32 tester5;
+ u32 rsvd2[3];
+ u32 cfg0;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank2_regs {
+ u32 cfg1;
+ u32 rsvd0[3];
+ u32 cfg2;
+ u32 rsvd1[3];
+ u32 cfg3;
+ u32 rsvd2[3];
+ u32 cfg4;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank3_regs {
+ u32 mem_trim0;
+ u32 rsvd0[3];
+ u32 mem_trim1;
+ u32 rsvd1[3];
+ u32 ana0;
+ u32 rsvd2[3];
+ u32 ana1;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank8_regs {
+ u32 sjc_resp_low;
+ u32 rsvd0[3];
+ u32 sjc_resp_high;
+ u32 rsvd1[3];
+ u32 usb_id;
+ u32 rsvd2[3];
+ u32 field_return;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank9_regs {
+ u32 mac_addr0;
+ u32 rsvd0[3];
+ u32 mac_addr1;
+ u32 rsvd1[3];
+ u32 mac_addr2;
+ u32 rsvd2[7];
+};
+
+struct aipstz_regs {
+ u32 mprot0;
+ u32 mprot1;
+ u32 rsvd[0xe];
+ u32 opacr0;
+ u32 opacr1;
+ u32 opacr2;
+ u32 opacr3;
+ u32 opacr4;
+};
+
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Miscellaneous Control */
+};
+
+struct dbg_monitor_regs {
+ u32 ctrl[4]; /* Control */
+ u32 master_en[4]; /* Master enable */
+ u32 irq[4]; /* IRQ */
+ u32 trap_addr_low[4]; /* Trap address low */
+ u32 trap_addr_high[4]; /* Trap address high */
+ u32 trap_id[4]; /* Trap ID */
+ u32 snvs_addr[4]; /* SNVS address */
+ u32 snvs_data[4]; /* SNVS data */
+ u32 snvs_info[4]; /* SNVS info */
+ u32 version[4]; /* Version */
+};
+
+struct rdc_regs {
+ u32 vir; /* Version information */
+ u32 reserved1[8];
+ u32 stat; /* Status */
+ u32 intctrl; /* Interrupt and Control */
+ u32 intstat; /* Interrupt Status */
+ u32 reserved2[116];
+ u32 mda[27]; /* Master Domain Assignment */
+ u32 reserved3[101];
+ u32 pdap[118]; /* Peripheral Domain Access Permissions */
+ u32 reserved4[138];
+ struct {
+ u32 mrsa; /* Memory Region Start Address */
+ u32 mrea; /* Memory Region End Address */
+ u32 mrc; /* Memory Region Control */
+ u32 mrvs; /* Memory Region Violation Status */
+ } mem_region[52];
+};
+
+struct rdc_sema_regs {
+ u8 gate[64]; /* Gate */
+ u16 rstgt; /* Reset Gate */
+};
+
+/* eLCDIF controller registers */
+struct mxs_lcdif_regs {
+ u32 hw_lcdif_ctrl; /* 0x00 */
+ u32 hw_lcdif_ctrl_set;
+ u32 hw_lcdif_ctrl_clr;
+ u32 hw_lcdif_ctrl_tog;
+ u32 hw_lcdif_ctrl1; /* 0x10 */
+ u32 hw_lcdif_ctrl1_set;
+ u32 hw_lcdif_ctrl1_clr;
+ u32 hw_lcdif_ctrl1_tog;
+ u32 hw_lcdif_ctrl2; /* 0x20 */
+ u32 hw_lcdif_ctrl2_set;
+ u32 hw_lcdif_ctrl2_clr;
+ u32 hw_lcdif_ctrl2_tog;
+ u32 hw_lcdif_transfer_count; /* 0x30 */
+ u32 reserved1[3];
+ u32 hw_lcdif_cur_buf; /* 0x40 */
+ u32 reserved2[3];
+ u32 hw_lcdif_next_buf; /* 0x50 */
+ u32 reserved3[3];
+ u32 hw_lcdif_timing; /* 0x60 */
+ u32 reserved4[3];
+ u32 hw_lcdif_vdctrl0; /* 0x70 */
+ u32 hw_lcdif_vdctrl0_set;
+ u32 hw_lcdif_vdctrl0_clr;
+ u32 hw_lcdif_vdctrl0_tog;
+ u32 hw_lcdif_vdctrl1; /* 0x80 */
+ u32 reserved5[3];
+ u32 hw_lcdif_vdctrl2; /* 0x90 */
+ u32 reserved6[3];
+ u32 hw_lcdif_vdctrl3; /* 0xa0 */
+ u32 reserved7[3];
+ u32 hw_lcdif_vdctrl4; /* 0xb0 */
+ u32 reserved8[3];
+ u32 hw_lcdif_dvictrl0; /* 0xc0 */
+ u32 reserved9[3];
+ u32 hw_lcdif_dvictrl1; /* 0xd0 */
+ u32 reserved10[3];
+ u32 hw_lcdif_dvictrl2; /* 0xe0 */
+ u32 reserved11[3];
+ u32 hw_lcdif_dvictrl3; /* 0xf0 */
+ u32 reserved12[3];
+ u32 hw_lcdif_dvictrl4; /* 0x100 */
+ u32 reserved13[3];
+ u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */
+ u32 reserved14[3];
+ u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */
+ u32 reserved15[3];
+ u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */
+ u32 reserved16[3];
+ u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */
+ u32 reserved17[3];
+ u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */
+ u32 reserved18[3];
+ u32 hw_lcdif_csc_offset; /* 0x160 */
+ u32 reserved19[3];
+ u32 hw_lcdif_csc_limit; /* 0x170 */
+ u32 reserved20[3];
+ u32 hw_lcdif_data; /* 0x180 */
+ u32 reserved21[3];
+ u32 hw_lcdif_bm_error_stat; /* 0x190 */
+ u32 reserved22[3];
+ u32 hw_lcdif_crc_stat; /* 0x1a0 */
+ u32 reserved23[3];
+ u32 hw_lcdif_lcdif_stat; /* 0x1b0 */
+ u32 reserved24[3];
+ u32 hw_lcdif_version; /* 0x1c0 */
+ u32 reserved25[3];
+ u32 hw_lcdif_debug0; /* 0x1d0 */
+ u32 reserved26[3];
+ u32 hw_lcdif_debug1; /* 0x1e0 */
+ u32 reserved27[3];
+ u32 hw_lcdif_debug2; /* 0x1f0 */
+ u32 reserved28[3];
+ u32 hw_lcdif_thres; /* 0x200 */
+ u32 reserved29[3];
+ u32 hw_lcdif_as_ctrl; /* 0x210 */
+ u32 reserved30[3];
+ u32 hw_lcdif_as_buf; /* 0x220 */
+ u32 reserved31[3];
+ u32 hw_lcdif_as_next_buf; /* 0x230 */
+ u32 reserved32[3];
+ u32 hw_lcdif_as_clrkeylow; /* 0x240 */
+ u32 reserved33[3];
+ u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */
+ u32 reserved34[3];
+ u32 hw_lcdif_as_sync_delay; /* 0x260 */
+ u32 reserved35[3];
+ u32 hw_lcdif_as_debug3; /* 0x270 */
+ u32 reserved36[3];
+ u32 hw_lcdif_as_debug4; /* 0x280 */
+ u32 reserved37[3];
+ u32 hw_lcdif_as_debug5; /* 0x290 */
+};
+
+#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
+
+#define LCDIF_CTRL_SFTRST (1 << 31)
+#define LCDIF_CTRL_CLKGATE (1 << 30)
+#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
+#define LCDIF_CTRL_READ_WRITEB (1 << 28)
+#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
+#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
+#define LCDIF_CTRL_DVI_MODE (1 << 20)
+#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
+#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
+#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
+#define LCDIF_CTRL_DATA_SELECT (1 << 16)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
+#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
+#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
+#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
+#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
+#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
+#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
+#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
+#define LCDIF_CTRL_RUN (1 << 0)
+
+#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
+#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
+#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
+#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
+#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
+#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
+#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
+#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
+#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
+#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
+#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
+#define LCDIF_CTRL1_MODE86 (1 << 1)
+#define LCDIF_CTRL1_RESET (1 << 0)
+
+#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
+#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
+#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
+#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
+#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
+
+#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
+#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
+#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
+
+#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_CUR_BUF_ADDR_OFFSET 0
+
+#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
+
+#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
+#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
+#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
+#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
+#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
+#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
+#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
+#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
+
+#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
+#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
+#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
+#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
+#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
+#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
+#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
+#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
+#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
+
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
+
+#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
+#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
+
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
+#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
+
+
+extern void check_cpu_temperature(void);
+
+extern void pcie_power_up(void);
+extern void pcie_power_off(void);
+
+/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
+ * If boot from the other mode, USB0_PWD will keep reset value
+ */
+#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
+ readl(USBOTG2_IPS_BASE_ADDR + 0x158))
+#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
+
+/* Boot device type */
+#define BOOT_TYPE_SD 0x1
+#define BOOT_TYPE_MMC 0x2
+#define BOOT_TYPE_NAND 0x3
+#define BOOT_TYPE_QSPI 0x4
+#define BOOT_TYPE_WEIM 0x5
+#define BOOT_TYPE_SPINOR 0x6
+
+struct bootrom_sw_info {
+ u8 reserved_1;
+ u8 boot_dev_instance;
+ u8 boot_dev_type;
+ u8 reserved_2;
+ u32 arm_core_freq;
+ u32 axi_freq;
+ u32 ddr_freq;
+ u32 gpt1_freq;
+ u32 reserved_3[3];
+};
+
+#endif /* __ASSEMBLER__*/
+#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/imx-common/sys_proto.h>
+
+void set_wdog_reset(struct wdog_regs *wdog);
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-#define BIT(x) (1 << (x))
-
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
#define SCIF3_BASE 0xE6EA8000
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
+#define SCIFA0_BASE 0xE6C40000
+#define SCIFA1_BASE 0xE6C50000
+#define SCIFA2_BASE 0xE6C60000
/* Module stop status register */
#define MSTPSR0 0xE6150030
#define SOC_SPEAR320 203
extern int get_socrev(void);
+int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif
/*
- * This is a copy of omap3/spl.h:
- *
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
-#define BOOT_DEVICE_NONE 0
-#define BOOT_DEVICE_XIP 1
-#define BOOT_DEVICE_NAND 2
-#define BOOT_DEVICE_ONE_NAND 3
-#define BOOT_DEVICE_MMC2 5 /*emmc*/
-#define BOOT_DEVICE_MMC1 6
-#define BOOT_DEVICE_XIPWAIT 7
-#define BOOT_DEVICE_MMC2_2 0xff
+#define BOOT0_MAGIC "eGON.BT0"
+#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
+#define SPL_HEADER_VERSION 1
+
+/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */
+#define SPL_ADDR 0x0
+
+/* boot head definition from sun4i boot code */
+struct boot_file_head {
+ uint32_t b_instruction; /* one intruction jumping to real code */
+ uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
+ uint32_t check_sum; /* generated by PC */
+ uint32_t length; /* generated by PC */
+ /*
+ * We use a simplified header, only filling in what is needed
+ * by the boot ROM. To be compatible with Allwinner tools we
+ * would need to implement the proper fields here instead of
+ * padding.
+ *
+ * Actually we want the ability to recognize our "sunxi" variant
+ * of the SPL. To do so, let's place a special signature into the
+ * "pub_head_size" field. We can reasonably expect Allwinner's
+ * boot0 to always have the upper 16 bits of this set to 0 (after
+ * all the value shouldn't be larger than the limit imposed by
+ * SRAM size).
+ * If the signature is present (at 0x14), then we know it's safe
+ * to use the remaining 8 bytes (at 0x18) for our own purposes.
+ * (E.g. sunxi-tools "fel" utility can pass information there.)
+ */
+ union {
+ uint32_t pub_head_size;
+ uint8_t spl_signature[4];
+ };
+ uint32_t fel_script_address;
+ uint32_t reserved; /* padding, align to 32 bytes */
+};
+
+#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
+
#endif
/* return the current oscillator clock frequency */
enum clock_osc_freq clock_get_osc_freq(void);
+/* return the clk_m frequency */
+unsigned int clk_m_get_rate(unsigned int parent_rate);
+
/**
* Start PLL using the provided configuration parameters.
*
void tegra30_set_up_pllp(void);
-/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */
-#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2)
+/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
+#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3)
struct clk_pll_info {
u32 m_shift:5; /* DIVM_SHIFT */
struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
};
-#define BIT(pos) (1U << pos)
-
/* DC_CMD_DISPLAY_COMMAND 0x032 */
#define CTRL_MODE_SHIFT 5
#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
u32 init:2;
};
-/**
- * tegra_spl_gpio_direction_output() - set the output value of a GPIO
- *
- * This function is only used from SPL on seaboard, which needs to enable a
- * GPIO to get the UART running. It could be done in U-Boot rather than SPL,
- * but for now, this gets it working
- */
-int tegra_spl_gpio_direction_output(int gpio, int value);
-
/**
* Configure a list of GPIOs
*
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* placeholder */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
+#define PLLC_IDDQ (1 << 26)
+
#endif /* _TEGRA114_CLOCK_H_ */
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
+#define PLLC_IDDQ (1 << 26)
+
/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
#define SOR0_CLK_SEL0 (1 << 14)
#define SOR0_CLK_SEL1 (1 << 15)
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of clocks */
CLOCK_ID_NONE = -1,
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK
-#define __ASM_ARCH_CLOCK
-
-struct prcmu {
- unsigned int armclkfix_mgt;
- unsigned int armclk_mgt;
- unsigned int svammdspclk_mgt;
- unsigned int siammdspclk_mgt;
- unsigned int reserved;
- unsigned int sgaclk_mgt;
- unsigned int uartclk_mgt;
- unsigned int msp02clk_mgt;
- unsigned int i2cclk_mgt;
- unsigned int sdmmcclk_mgt;
- unsigned int slimclk_mgt;
- unsigned int per1clk_mgt;
- unsigned int per2clk_mgt;
- unsigned int per3clk_mgt;
- unsigned int per5clk_mgt;
- unsigned int per6clk_mgt;
- unsigned int per7clk_mgt;
- unsigned int lcdclk_mgt;
- unsigned int reserved1;
- unsigned int bmlclk_mgt;
- unsigned int hsitxclk_mgt;
- unsigned int hsirxclk_mgt;
- unsigned int hdmiclk_mgt;
- unsigned int apeatclk_mgt;
- unsigned int apetraceclk_mgt;
- unsigned int mcdeclk_mgt;
- unsigned int ipi2cclk_mgt;
- unsigned int dsialtclk_mgt;
- unsigned int spare2clk_mgt;
- unsigned int dmaclk_mgt;
- unsigned int b2r2clk_mgt;
- unsigned int tvclk_mgt;
- unsigned int unused[82];
- unsigned int tcr;
- unsigned int unused1[23];
- unsigned int ape_softrst;
-};
-
-extern void u8500_clock_enable(int periph, int kern, int cluster);
-
-void db8500_clocks_init(void);
-
-#endif /* __ASM_ARCH_CLOCK */
+++ /dev/null
-/*
- * Structures and registers for GPIO access in the Nomadik SoC
- *
- * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
- * The purpose is that GPIO config found in kernel should work by simply
- * copy-paste it to U-boot.
- *
- * Ported to U-boot by:
- * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
- * Copyright (C) 2008 STMicroelectronics
- * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
- * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DB8500_GPIO_H__
-#define __DB8500_GPIO_H__
-
-/* Alternate functions: function C is set in hw by setting both A and B */
-enum db8500_gpio_alt {
- DB8500_GPIO_ALT_GPIO = 0,
- DB8500_GPIO_ALT_A = 1,
- DB8500_GPIO_ALT_B = 2,
- DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
-};
-
-enum db8500_gpio_pull {
- DB8500_GPIO_PULL_NONE,
- DB8500_GPIO_PULL_UP,
- DB8500_GPIO_PULL_DOWN
-};
-
-void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
-void db8500_gpio_make_input(unsigned gpio);
-int db8500_gpio_get_input(unsigned gpio);
-void db8500_gpio_make_output(unsigned gpio, int val);
-void db8500_gpio_set_output(unsigned gpio, int val);
-
-#endif /* __DB8500_GPIO_H__ */
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
- * The purpose is that GPIO config found in kernel should work by simply
- * copy-paste it to U-boot. Ported 2010 to U-boot by:
- * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
- *
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- *
- *
- * Based on arch/arm/mach-pxa/include/mach/mfp.h:
- * Copyright (C) 2007 Marvell International Ltd.
- * eric miao <eric.miao@marvell.com>
- */
-
-#ifndef __DB8500_PINCFG_H
-#define __DB8500_PINCFG_H
-
-#include "db8500_gpio.h"
-
-/*
- * U-boot info:
- * SLPM (sleep mode) config will be ignored by U-boot but it is still
- * possible to configure it in order to keep cut-n-paste compability
- * with Linux kernel config.
- *
- * pin configurations are represented by 32-bit integers:
- *
- * bit 0.. 8 - Pin Number (512 Pins Maximum)
- * bit 9..10 - Alternate Function Selection
- * bit 11..12 - Pull up/down state
- * bit 13 - Sleep mode behaviour (not used in U-boot)
- * bit 14 - Direction
- * bit 15 - Value (if output)
- * bit 16..18 - SLPM pull up/down state (not used in U-boot)
- * bit 19..20 - SLPM direction (not used in U-boot)
- * bit 21..22 - SLPM Value (if output) (not used in U-boot)
- *
- * to facilitate the definition, the following macros are provided
- *
- * PIN_CFG_DEFAULT - default config (0):
- * pull up/down = disabled
- * sleep mode = input/wakeup
- * direction = input
- * value = low
- * SLPM direction = same as normal
- * SLPM pull = same as normal
- * SLPM value = same as normal
- *
- * PIN_CFG - default config with alternate function
- * PIN_CFG_PULL - default config with alternate function and pull up/down
- */
-
-/* Sleep mode */
-enum db8500_gpio_slpm {
- DB8500_GPIO_SLPM_INPUT,
- DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
- DB8500_GPIO_SLPM_NOCHANGE,
- DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
-};
-
-#define PIN_NUM_MASK 0x1ff
-#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
-
-#define PIN_ALT_SHIFT 9
-#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
-#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
-#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
-#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
-#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
-#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
-
-#define PIN_PULL_SHIFT 11
-#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
-#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
-#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
-#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
-#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
-
-#define PIN_SLPM_SHIFT 13
-#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
-#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
-#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
-#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
-/* These two replace the above in DB8500v2+ */
-#define PIN_SLPM_WAKEUP_ENABLE \
- (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
-#define PIN_SLPM_WAKEUP_DISABLE \
- (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
-
-#define PIN_DIR_SHIFT 14
-#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
-#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
-#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
-#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
-
-#define PIN_VAL_SHIFT 15
-#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
-#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
-#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
-#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
-
-#define PIN_SLPM_PULL_SHIFT 16
-#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL(x) \
- (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_NONE \
- ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_UP \
- ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_DOWN \
- ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
-
-#define PIN_SLPM_DIR_SHIFT 19
-#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR(x) \
- (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
-
-#define PIN_SLPM_VAL_SHIFT 21
-#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL(x) \
- (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
-
-/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
-#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
-#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
-#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
-#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
-#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
-
-#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
-#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
-#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
-#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
-#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
-
-#define PIN_CFG_DEFAULT (0)
-
-#define PIN_CFG(num, alt) \
- (PIN_CFG_DEFAULT |\
- (PIN_NUM(num) | PIN_##alt))
-
-#define PIN_CFG_INPUT(num, alt, pull) \
- (PIN_CFG_DEFAULT |\
- (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
-
-#define PIN_CFG_OUTPUT(num, alt, val) \
- (PIN_CFG_DEFAULT |\
- (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
-
-#define PIN_CFG_PULL(num, alt, pull) \
- ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
- (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
-
-/**
- * db8500_gpio_config_pins - configure several pins at once
- * @cfgs: array of pin configurations
- * @num: number of elments in the array
- *
- * Configures several GPIO pins.
- */
-void db8500_gpio_config_pins(unsigned long *cfgs, size_t num);
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _UX500_GPIO_h
-#define _UX500_GPIO_h
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/u8500.h>
-
-#define GPIO_TOTAL_PINS 268
-
-#define GPIO_PINS_PER_BLOCK 32
-#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
-#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
-
-
-struct gpio_register {
- u32 gpio_dat; /* data register : 0x000 */
- u32 gpio_dats; /* data Set register : 0x004 */
- u32 gpio_datc; /* data Clear register : 0x008 */
- u32 gpio_pdis; /* Pull disable register : 0x00C */
- u32 gpio_dir; /* data direction register : 0x010 */
- u32 gpio_dirs; /* data dir Set register : 0x014 */
- u32 gpio_dirc; /* data dir Clear register : 0x018 */
- u32 gpio_slpm; /* Sleep mode register : 0x01C */
- u32 gpio_afsa; /* AltFun A Select reg : 0x020 */
- u32 gpio_afsb; /* AltFun B Select reg : 0x024 */
- u32 gpio_lowemi;/* low EMI Select reg : 0x028 */
- u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/
- u32 gpio_rimsc; /* rising edge intr set/clear : 0x040 */
- u32 gpio_fimsc; /* falling edge intr set/clear register : 0x044 */
- u32 gpio_mis; /* masked interrupt status register : 0x048 */
- u32 gpio_ic; /* Interrupt Clear register : 0x04C */
- u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */
- u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */
- u32 gpio_wks; /* Wakeup Status register : 0x058 */
-};
-
-/* Error values returned by functions */
-enum gpio_error {
- GPIO_OK = 0,
- GPIO_UNSUPPORTED_HW = -2,
- GPIO_UNSUPPORTED_FEATURE = -3,
- GPIO_INVALID_PARAMETER = -4,
- GPIO_REQUEST_NOT_APPLICABLE = -5,
- GPIO_REQUEST_PENDING = -6,
- GPIO_NOT_CONFIGURED = -7,
- GPIO_INTERNAL_ERROR = -8,
- GPIO_INTERNAL_EVENT = 1,
- GPIO_REMAINING_EVENT = 2,
- GPIO_NO_MORE_PENDING_EVENT = 3,
- GPIO_INVALID_CLIENT = -25,
- GPIO_INVALID_PIN = -26,
- GPIO_PIN_BUSY = -27,
- GPIO_PIN_NOT_ALLOCATED = -28,
- GPIO_WRONG_CLIENT = -29,
- GPIO_UNSUPPORTED_ALTFUNC = -30,
-};
-
-/*GPIO DEVICE ID */
-enum gpio_device_id {
- GPIO_DEVICE_ID_0,
- GPIO_DEVICE_ID_1,
- GPIO_DEVICE_ID_2,
- GPIO_DEVICE_ID_3,
- GPIO_DEVICE_ID_INVALID
-};
-
-/*
- * Alternate Function:
- * refered in altfun_table to pointout particular altfun to be enabled
- * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
- */
-enum gpio_alt_function {
- GPIO_ALT_UART_0_MODEM,
- GPIO_ALT_UART_0_NO_MODEM,
- GPIO_ALT_UART_1,
- GPIO_ALT_UART_2,
- GPIO_ALT_I2C_0,
- GPIO_ALT_I2C_1,
- GPIO_ALT_I2C_2,
- GPIO_ALT_I2C_3,
- GPIO_ALT_MSP_0,
- GPIO_ALT_MSP_1,
- GPIO_ALT_MSP_2,
- GPIO_ALT_MSP_3,
- GPIO_ALT_MSP_4,
- GPIO_ALT_MSP_5,
- GPIO_ALT_SSP_0,
- GPIO_ALT_SSP_1,
- GPIO_ALT_MM_CARD0,
- GPIO_ALT_SD_CARD0,
- GPIO_ALT_DMA_0,
- GPIO_ALT_DMA_1,
- GPIO_ALT_HSI0,
- GPIO_ALT_CCIR656_INPUT,
- GPIO_ALT_CCIR656_OUTPUT,
- GPIO_ALT_LCD_PANEL,
- GPIO_ALT_MDIF,
- GPIO_ALT_SDRAM,
- GPIO_ALT_HAMAC_AUDIO_DBG,
- GPIO_ALT_HAMAC_VIDEO_DBG,
- GPIO_ALT_CLOCK_RESET,
- GPIO_ALT_TSP,
- GPIO_ALT_IRDA,
- GPIO_ALT_USB_MINIMUM,
- GPIO_ALT_USB_I2C,
- GPIO_ALT_OWM,
- GPIO_ALT_PWL,
- GPIO_ALT_FSMC,
- GPIO_ALT_COMP_FLASH,
- GPIO_ALT_SRAM_NOR_FLASH,
- GPIO_ALT_FSMC_ADDLINE_0_TO_15,
- GPIO_ALT_SCROLL_KEY,
- GPIO_ALT_MSHC,
- GPIO_ALT_HPI,
- GPIO_ALT_USB_OTG,
- GPIO_ALT_SDIO,
- GPIO_ALT_HSMMC,
- GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
- GPIO_ALT_HSI1,
- GPIO_ALT_NOR,
- GPIO_ALT_NAND,
- GPIO_ALT_KEYPAD,
- GPIO_ALT_VPIP,
- GPIO_ALT_CAM,
- GPIO_ALT_CCP1,
- GPIO_ALT_EMMC,
- GPIO_ALT_POP_EMMC,
- GPIO_ALT_FUNMAX /* Add new alt func before this */
-};
-
-/* Defines pin assignment(Software mode or Alternate mode) */
-enum gpio_mode {
- GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */
- GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */
- GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */
- GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */
- GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */
- GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */
-};
-
-/* Defines GPIO pin direction */
-enum gpio_direction {
- GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_DIR_INPUT, /* GPIO set as input */
- GPIO_DIR_OUTPUT /* GPIO set as output */
-};
-
-/* Interrupt trigger mode */
-enum gpio_trig {
- GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_TRIG_DISABLE, /* Trigger no IT */
- GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */
- GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */
- GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */
- GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */
- GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */
-};
-
-/* Configuration parameters for one GPIO pin.*/
-struct gpio_config {
- enum gpio_mode mode;
- enum gpio_direction direction;
- enum gpio_trig trig;
- char *dev_name; /* Who owns the gpio pin */
-};
-
-/* GPIO pin data*/
-enum gpio_data {
- GPIO_DATA_LOW,
- GPIO_DATA_HIGH
-};
-
-/* GPIO behaviour in sleep mode */
-enum gpio_sleep_mode {
- GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull
- up/down enabled when in sleep
- mode. */
- GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by
- GPIO IP. So mode, direction
- and data values for GPIO pin
- in sleep mode are determined
- by configuration set to GPIO
- pin before entering to sleep
- mode. */
-};
-
-/* GPIO ability to wake the system up from sleep mode.*/
-enum gpio_wake {
- GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */
- GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */
- GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */
- GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */
- GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */
- GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */
-};
-
-/* Configuration parameters for one GPIO pin in sleep mode.*/
-struct gpio_sleep_config {
- enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
- enum gpio_wake wake; /* GPIO ability to wake up system. */
-};
-
-extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
-extern int gpio_resetpinconfig(int pin_id, char *dev_name);
-extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
-extern int gpio_readpin(int pin_id, enum gpio_data *value);
-extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
- char *dev_name);
-extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
- char *dev_name);
-
-struct gpio_altfun_data {
- u16 altfun;
- u16 start;
- u16 end;
- u16 cont;
- u8 type;
-};
-#endif
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Peripheral clusters */
-
-#define U8500_PER3_BASE 0x80000000
-#define U8500_PER2_BASE 0x80110000
-#define U8500_PER1_BASE 0x80120000
-#define U8500_PER4_BASE 0x80150000
-
-#define U8500_PER6_BASE 0xa03c0000
-#define U8500_PER7_BASE 0xa03d0000
-#define U8500_PER5_BASE 0xa03e0000
-
-/* GPIO */
-
-#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
-#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
-
-#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
-#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
-#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
-#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
-
-#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
-#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
-
-#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
-
-/* Per7 */
-#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
-
-/* Per6 */
-#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
-#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
-#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
-
-/* Per5 */
-#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
-
-/* Per4 */
-#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
-
-/* Per3 */
-#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
-#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
-
-/* Per2 */
-#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
-
-/* Per1 */
-#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
-#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
-#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
-
-/* Last page of Boot ROM */
-#define U8500_BOOTROM_BASE 0x90000000
-#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
-#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4)
-
-/* AB8500 specifics */
-
-/* address bank */
-#define AB8500_REGU_CTRL2 0x0004
-#define AB8500_MISC 0x0010
-
-/* registers */
-#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
-#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
-#define AB8500_REV_REG 0x1080
-
-#define AB8500_GPIO_SEL2_REG 0x1001
-#define AB8500_GPIO_DIR2_REG 0x1011
-#define AB8500_GPIO_DIR4_REG 0x1013
-#define AB8500_GPIO_SEL4_REG 0x1003
-#define AB8500_GPIO_OUT2_REG 0x1021
-#define AB8500_GPIO_OUT4_REG 0x1023
-
-#define LDO_VAUX3_ENABLE_MASK 0x3
-#define LDO_VAUX3_ENABLE_VAL 0x1
-#define LDO_VAUX3_SEL_MASK 0xf
-#define LDO_VAUX3_SEL_2V9 0xd
-#define LDO_VAUX3_V2_SEL_MASK 0x7
-#define LDO_VAUX3_V2_SEL_2V91 0x7
-
-
-#endif /* __ASM_ARCH_HARDWARE_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 ST-Ericsson SA
- *
- * Copied from the Linux version:
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __MACH_PRCMU_FW_V1_H
-#define __MACH_PRCMU_FW_V1_H
-
-#define AP_EXECUTE 2
-#define I2CREAD 1
-#define I2C_WR_OK 1
-#define I2C_RD_OK 2
-#define I2CWRITE 0
-
-#define PRCMU_BASE U8500_PRCMU_BASE
-#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
-#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
-#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
-#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
-#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
-#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
-#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
-#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
-#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
-#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
-#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
-#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
-#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
-
-#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
-#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
-#define PRCM_TCR (PRCMU_BASE + 0x1C8)
-#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
-#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
-#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
-/* Mailbox 5 Requests */
-#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
-#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
-#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2)
-#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3)
-
-/* Mailbox 5 ACKs */
-#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1)
-#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2)
-#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3)
-
-#define LOW_POWER_WAKEUP 1
-#define EXE_WAKEUP 0
-
-#define REQ_MB5 5
-
-#define ab8500_read prcmu_i2c_read
-#define ab8500_write prcmu_i2c_write
-
-int prcmu_i2c_read(u8 reg, u16 slave);
-int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
-
-void u8500_prcmu_enable(u32 *reg);
-void db8500_prcmu_init(void);
-
-#endif /* __MACH_PRCMU_FW_V1_H */
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-void gpio_init(void);
-int u8500_mmc_power_init(void);
-
-#endif /* _SYS_PROTO_H_ */
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __U8500_H
-#define __U8500_H
-
-/*
- * base register values for U8500
- */
-#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
- Management Unit */
-#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */
-#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
-
-/*
- * U8500 GPIO register base for 9 banks
- */
-#define U8500_GPIO_0_BASE 0x8012E000
-#define U8500_GPIO_1_BASE 0x8012E080
-#define U8500_GPIO_2_BASE 0x8000E000
-#define U8500_GPIO_3_BASE 0x8000E080
-#define U8500_GPIO_4_BASE 0x8000E100
-#define U8500_GPIO_5_BASE 0x8000E180
-#define U8500_GPIO_6_BASE 0x8011E000
-#define U8500_GPIO_7_BASE 0x8011E080
-#define U8500_GPIO_8_BASE 0xA03FE000
-
-#endif /* __U8500_H */
#ifndef __ASM_ARCH_VF610_DDRMC_H
#define __ASM_ARCH_VF610_DDRMC_H
-struct ddrmc_lvl_info {
- u16 wrlvl_reg_en;
- u16 wrlvl_dl_0;
- u16 wrlvl_dl_1;
- u16 rdlvl_gt_reg_en;
- u16 rdlvl_gt_dl_0;
- u16 rdlvl_gt_dl_1;
- u16 rdlvl_reg_en;
- u16 rdlvl_dl_0;
- u16 rdlvl_dl_1;
-};
-
struct ddr3_jedec_timings {
u8 tinit;
u32 trst_pwron;
u8 trc;
u8 trrd;
u8 tccd;
+ u8 tbst_int_interval;
u8 tfaw;
u8 trp;
u8 twtr;
u8 tckesr;
u8 tcke;
u8 trcd_int;
+ u8 tras_lockout;
u8 tdal;
+ u8 bstlen;
u16 tdll;
u8 trp_ab;
u16 tref;
u8 trfc;
+ u16 tref_int;
u8 tpdex;
u8 txpdll;
u8 txsnr;
u16 txsr;
u8 cksrx;
u8 cksre;
+ u8 freq_chg_en;
u16 zqcl;
u16 zqinit;
u8 zqcs;
u8 ref_per_zq;
+ u8 zqcs_rotate;
u8 aprebit;
+ u8 cmd_age_cnt;
+ u8 age_cnt;
+ u8 q_fullness;
+ u8 odt_rd_mapcs0;
+ u8 odt_wr_mapcs0;
u8 wlmrd;
u8 wldqsen;
};
-void ddrmc_setup_iomux(void);
+struct ddrmc_cr_setting {
+ u32 setting;
+ int cr_rnum; /* CR register ; -1 for last entry */
+};
+
+struct ddrmc_phy_setting {
+ u32 setting;
+ int phy_rnum; /* PHY register ; -1 for last entry */
+};
+
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
void ddrmc_phy_init(void);
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_lvl_info *lvl,
- int col_diff, int row_diff);
+ struct ddrmc_cr_setting *board_cr_settings,
+ struct ddrmc_phy_setting *board_phy_settings,
+ int col_diff, int row_diff);
#endif
#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
#define DDRMC_CR20_AP_EN (1 << 24)
#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
-#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
+#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
#define DDRMC_CR21_CCMAP_EN 1
#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
-#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
-#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
+#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+enum boot_device {
+ WEIM_NOR_BOOT,
+ ONE_NAND_BOOT,
+ PATA_BOOT,
+ SATA_BOOT,
+ I2C_BOOT,
+ SPI_NOR_BOOT,
+ SD1_BOOT,
+ SD2_BOOT,
+ SD3_BOOT,
+ SD4_BOOT,
+ MMC1_BOOT,
+ MMC2_BOOT,
+ MMC3_BOOT,
+ MMC4_BOOT,
+ NAND_BOOT,
+ QSPI_BOOT,
+ UNKNOWN_BOOT,
+ BOOT_DEV_NUM = UNKNOWN_BOOT,
+};
+
struct boot_mode {
const char *name;
unsigned cfg_val;
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define soc_type(rev) (((rev) >> 12) & 0xf0)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define get_soc_type() (soc_type(get_cpu_rev()))
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
+#define is_soc_type(soc) (get_soc_type() == soc)
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
void sdelay(unsigned long);
void set_chipselect_size(int const);
+void init_aips(void);
+void init_src(void);
+void imx_set_wdog_powerdown(bool enable);
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 cntfid2;
+ u32 resv2[1001];
+ u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE (1 << 0)
+#define SC_CNTCR_HDBG (1 << 1)
+#define SC_CNTCR_FREQ0 (1 << 8)
+#define SC_CNTCR_FREQ1 (1 << 9)
+
+#endif
#define MACH_TYPE_INTELMOTE2 775
#define MACH_TYPE_TRIZEPS4 776
#define MACH_TYPE_PNX4008 782
-#define MACH_TYPE_CPUAT91 787
#define MACH_TYPE_IQ81340SC 799
#define MACH_TYPE_IQ81340MC 801
#define MACH_TYPE_MICRO9 811
#define MACH_TYPE_SMDK2412 1009
#define MACH_TYPE_SMDK2413 1022
#define MACH_TYPE_AML_M5900 1024
-#define MACH_TYPE_BALLOON3 1029
#define MACH_TYPE_ECBAT91 1072
#define MACH_TYPE_ONEARM 1075
#define MACH_TYPE_SMDK2443 1084
#define MACH_TYPE_IGEP0020 2344
#define MACH_TYPE_NUC932EVB 2356
#define MACH_TYPE_OPENRD_CLIENT 2361
-#define MACH_TYPE_U8500 2368
#define MACH_TYPE_MX51_EFIKASB 2370
#define MACH_TYPE_MARVELL_JASPER 2382
#define MACH_TYPE_FLINT 2383
#define MACH_TYPE_RHINO 3360
#define MACH_TYPE_ARMLEX4210 3361
#define MACH_TYPE_SWARCOEXTMODEM 3362
-#define MACH_TYPE_SNOWBALL 3363
#define MACH_TYPE_PCM049 3364
#define MACH_TYPE_VIGOR 3365
#define MACH_TYPE_OSLO_AMUNDSEN 3366
# define machine_is_pnx4008() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT91
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT91
-# endif
-# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91)
-#else
-# define machine_is_cpuat91() (0)
-#endif
-
#ifdef CONFIG_MACH_IQ81340SC
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_aml_m5900() (0)
#endif
-#ifdef CONFIG_MACH_BALLOON3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BALLOON3
-# endif
-# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3)
-#else
-# define machine_is_balloon3() (0)
-#endif
-
#ifdef CONFIG_MACH_ECBAT91
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_omap_zoom2() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT9260
-# endif
-# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260)
-#else
-# define machine_is_cpuat9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX27
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX27
-# endif
-# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27)
-#else
-# define machine_is_eukrea_cpuimx27() (0)
-#endif
-
#ifdef CONFIG_MACH_ACS5K
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_openrd_client() (0)
#endif
-#ifdef CONFIG_MACH_U8500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_U8500
-# endif
-# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500)
-#else
-# define machine_is_u8500() (0)
-#endif
-
#ifdef CONFIG_MACH_MX51_EFIKASB
# ifdef machine_arch_type
# undef machine_arch_type
# define machine_is_swarcoextmodem() (0)
#endif
-#ifdef CONFIG_MACH_SNOWBALL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SNOWBALL
-# endif
-# define machine_is_snowball() (machine_arch_type == MACH_TYPE_SNOWBALL)
-#else
-# define machine_is_snowball() (0)
-#endif
-
#ifdef CONFIG_MACH_PCM049
# ifdef machine_arch_type
# undef machine_arch_type
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-typedef struct bd_info {
- ulong bi_arch_number; /* unique id for this board */
- ulong bi_boot_params; /* where this board expects params */
- unsigned long bi_arm_freq; /* arm frequency */
- unsigned long bi_dsp_freq; /* dsp core frequency */
- unsigned long bi_ddr_freq; /* ddr frequency */
- struct /* RAM configuration */
- {
- ulong start;
- ulong size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
-#endif
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
#ifndef CONFIG_ARM64
else
obj-y += relocate.o
endif
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y += board.o
-endif
obj-$(CONFIG_CPU_V7M) += cmd_boot.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
+++ /dev/null
-/*
- * (C) Copyright 2002-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * To match the U-Boot user interface on ARM platforms to the U-Boot
- * standard (as on PPC platforms), some messages with debug character
- * are removed from the default U-Boot build.
- *
- * Define DEBUG here if you want additional info as shown below
- * printed upon startup:
- *
- * U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274
- * IRQ Stack: 00ebff7c
- * FIQ Stack: 00ebef7c
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-#include <serial.h>
-#include <nand.h>
-#include <onenand_uboot.h>
-#include <mmc.h>
-#include <scsi.h>
-#include <status_led.h>
-#include <libfdt.h>
-#include <fdtdec.h>
-#include <post.h>
-#include <logbuff.h>
-#include <asm/sections.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ulong monitor_flash_len;
-
-#ifdef CONFIG_HAS_DATAFLASH
-extern int AT91F_DataflashInit(void);
-extern void dataflash_print_info(void);
-#endif
-
-#if defined(CONFIG_HARD_I2C) || \
- defined(CONFIG_SYS_I2C)
-#include <i2c.h>
-#endif
-
-/************************************************************************
- * Coloured LED functionality
- ************************************************************************
- * May be supplied by boards if desired
- */
-__weak void coloured_LED_init(void) {}
-__weak void red_led_on(void) {}
-__weak void red_led_off(void) {}
-__weak void green_led_on(void) {}
-__weak void green_led_off(void) {}
-__weak void yellow_led_on(void) {}
-__weak void yellow_led_off(void) {}
-__weak void blue_led_on(void) {}
-__weak void blue_led_off(void) {}
-
-/*
- ************************************************************************
- * Init Utilities *
- ************************************************************************
- * Some of this code should be moved into the core functions,
- * or dropped completely,
- * but let's get it working (again) first...
- */
-
-#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)
-#define CONFIG_BAUDRATE 115200
-#endif
-
-static int init_baudrate(void)
-{
- gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
- return 0;
-}
-
-static int display_banner(void)
-{
- printf("\n\n%s\n\n", version_string);
- debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
- (ulong)&_start,
- (ulong)&__bss_start, (ulong)&__bss_end);
-#ifdef CONFIG_MODEM_SUPPORT
- debug("Modem Support enabled\n");
-#endif
-#ifdef CONFIG_USE_IRQ
- debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
- debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
-#endif
-
- return (0);
-}
-
-/*
- * WARNING: this code looks "cleaner" than the PowerPC version, but
- * has the disadvantage that you either get nothing, or everything.
- * On PowerPC, you might see "DRAM: " before the system hangs - which
- * gives a simple yet clear indication which part of the
- * initialization if failing.
- */
-static int display_dram_config(void)
-{
- int i;
-
-#ifdef DEBUG
- puts("RAM Configuration:\n");
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
- print_size(gd->bd->bi_dram[i].size, "\n");
- }
-#else
- ulong size = 0;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- size += gd->bd->bi_dram[i].size;
-
- puts("DRAM: ");
- print_size(size, "\n");
-#endif
-
- return (0);
-}
-
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
-static int init_func_i2c(void)
-{
- puts("I2C: ");
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- puts("ready\n");
- return (0);
-}
-#endif
-
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-#include <pci.h>
-static int arm_pci_init(void)
-{
- pci_init();
- return 0;
-}
-#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
-
-/*
- * Breathe some life into the board...
- *
- * Initialize a serial port as console, and carry out some hardware
- * tests.
- *
- * The first part of initialization is running from Flash memory;
- * its main purpose is to initialize the RAM so that we
- * can relocate the monitor code to RAM.
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependent #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t) (void);
-
-__weak void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-__weak int arch_cpu_init(void)
-{
- return 0;
-}
-
-__weak int power_init_board(void)
-{
- return 0;
-}
-
- /* Record the board_init_f() bootstage (after arch_cpu_init()) */
-static int mark_bootstage(void)
-{
- bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
-
- return 0;
-}
-
-init_fnc_t *init_sequence[] = {
- arch_cpu_init, /* basic arch cpu dependent setup */
- mark_bootstage,
-#ifdef CONFIG_OF_CONTROL
- fdtdec_check_fdt,
-#endif
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
- board_early_init_f,
-#endif
- timer_init, /* initialize timer */
-#ifdef CONFIG_BOARD_POSTCLK_INIT
- board_postclk_init,
-#endif
-#ifdef CONFIG_FSL_ESDHC
- get_clocks,
-#endif
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f, /* stage 1 init of console */
- display_banner, /* say that we are here */
- print_cpuinfo, /* display cpu info (and speed) */
-#if defined(CONFIG_DISPLAY_BOARDINFO)
- checkboard, /* display board info */
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
- init_func_i2c,
-#endif
- dram_init, /* configure available RAM banks */
- NULL,
-};
-
-void board_init_f(ulong bootflag)
-{
- bd_t *bd;
- init_fnc_t **init_fnc_ptr;
- gd_t *id;
- ulong addr, addr_sp;
-#ifdef CONFIG_PRAM
- ulong reg;
-#endif
- void *new_fdt = NULL;
- size_t fdt_size = 0;
-
- memset((void *)gd, 0, sizeof(gd_t));
-
- gd->mon_len = (ulong)&__bss_end - (ulong)_start;
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
- /* FDT is at end of image */
- gd->fdt_blob = &_end;
-#endif
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
- (uintptr_t)gd->fdt_blob);
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr)() != 0) {
- hang ();
- }
- }
-
-#ifdef CONFIG_OF_CONTROL
- /* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt()) {
- panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
- "doc/README.fdt-control");
- }
-#endif
-
- debug("monitor len: %08lX\n", gd->mon_len);
- /*
- * Ram is setup, size stored in gd !!
- */
- debug("ramsize: %08lX\n", gd->ram_size);
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- /*
- * Subtract specified amount of memory to hide so that it won't
- * get "touched" at all by U-Boot. By fixing up gd->ram_size
- * the Linux kernel should now get passed the now "corrected"
- * memory size and won't touch it either. This should work
- * for arch/ppc and arch/powerpc. Only Linux board ports in
- * arch/powerpc with bootwrapper support, that recalculate the
- * memory size from the SDRAM controller setup will have to
- * get fixed.
- */
- gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-
- addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
-
-#ifdef CONFIG_LOGBUFFER
-#ifndef CONFIG_ALT_LB_ADDR
- /* reserve kernel log buffer */
- addr -= (LOGBUFF_RESERVE);
- debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
- addr);
-#endif
-#endif
-
-#ifdef CONFIG_PRAM
- /*
- * reserve protected RAM
- */
- reg = getenv_ulong("pram", 10, CONFIG_PRAM);
- addr -= (reg << 10); /* size is in kB */
- debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
-#endif /* CONFIG_PRAM */
-
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- /* reserve TLB table */
- gd->arch.tlb_size = PGTABLE_SIZE;
- addr -= gd->arch.tlb_size;
-
- /* round down to next 64 kB limit */
- addr &= ~(0x10000 - 1);
-
- gd->arch.tlb_addr = addr;
- debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
-#endif
-
- /* round down to next 4 kB limit */
- addr &= ~(4096 - 1);
- debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_FB_ADDR
- gd->fb_base = CONFIG_FB_ADDR;
-#else
- /* reserve memory for LCD display (always full pages) */
- addr = lcd_setmem(addr);
- gd->fb_base = addr;
-#endif /* CONFIG_FB_ADDR */
-#endif /* CONFIG_LCD */
-
- /*
- * reserve memory for U-Boot code, data & bss
- * round down to next 4 kB limit
- */
- addr -= gd->mon_len;
- addr &= ~(4096 - 1);
-
- debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * reserve memory for malloc() arena
- */
- addr_sp = addr - TOTAL_MALLOC_LEN;
- debug("Reserving %dk for malloc() at: %08lx\n",
- TOTAL_MALLOC_LEN >> 10, addr_sp);
- /*
- * (permanently) allocate a Board Info struct
- * and a permanent copy of the "global" data
- */
- addr_sp -= sizeof (bd_t);
- bd = (bd_t *) addr_sp;
- gd->bd = bd;
- debug("Reserving %zu Bytes for Board Info at: %08lx\n",
- sizeof (bd_t), addr_sp);
-
-#ifdef CONFIG_MACH_TYPE
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
-#endif
-
- addr_sp -= sizeof (gd_t);
- id = (gd_t *) addr_sp;
- debug("Reserving %zu Bytes for Global Data at: %08lx\n",
- sizeof (gd_t), addr_sp);
-
-#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
- /*
- * If the device tree is sitting immediate above our image then we
- * must relocate it. If it is embedded in the data section, then it
- * will be relocated with other data.
- */
- if (gd->fdt_blob) {
- fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
-
- addr_sp -= fdt_size;
- new_fdt = (void *)addr_sp;
- debug("Reserving %zu Bytes for FDT at: %08lx\n",
- fdt_size, addr_sp);
- }
-#endif
-
-#ifndef CONFIG_ARM64
- /* setup stackpointer for exeptions */
- gd->irq_sp = addr_sp;
-#ifdef CONFIG_USE_IRQ
- addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
- debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
- CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
-#endif
- /* leave 3 words for abort-stack */
- addr_sp -= 12;
-
- /* 8-byte alignment for ABI compliance */
- addr_sp &= ~0x07;
-#else /* CONFIG_ARM64 */
- /* 16-byte alignment for ABI compliance */
- addr_sp &= ~0x0f;
-#endif /* CONFIG_ARM64 */
-#else
- addr_sp += 128; /* leave 32 words for abort-stack */
- gd->irq_sp = addr_sp;
-#endif
-
- debug("New Stack Pointer is: %08lx\n", addr_sp);
-
-#ifdef CONFIG_POST
- post_bootmode_init();
- post_run(NULL, POST_ROM | post_bootmode_get(0));
-#endif
-
- /* Ram ist board specific, so move it to board code ... */
- dram_init_banksize();
- display_dram_config(); /* and display it */
-
- gd->relocaddr = addr;
- gd->start_addr_sp = addr_sp;
- gd->reloc_off = addr - (ulong)&_start;
- debug("relocation Offset is: %08lx\n", gd->reloc_off);
- if (new_fdt) {
- memcpy(new_fdt, gd->fdt_blob, fdt_size);
- gd->fdt_blob = new_fdt;
- }
- memcpy(id, (void *)gd, sizeof(gd_t));
-}
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = "*** failed ***\n";
-#endif
-
-/*
- * Tell if it's OK to load the environment early in boot.
- *
- * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
- * if this is OK (defaulting to saying it's not OK).
- *
- * NOTE: Loading the environment early can be a bad idea if security is
- * important, since no verification is done on the environment.
- *
- * @return 0 if environment should not be loaded, !=0 if it is ok to load
- */
-static int should_load_env(void)
-{
-#ifdef CONFIG_OF_CONTROL
- return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
-#elif defined CONFIG_DELAY_ENVIRONMENT
- return 0;
-#else
- return 1;
-#endif
-}
-
-#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
-static void display_fdt_model(const void *blob)
-{
- const char *model;
-
- model = (char *)fdt_getprop(blob, 0, "model", NULL);
- printf("Model: %s\n", model ? model : "<unknown>");
-}
-#endif
-
-/************************************************************************
- *
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- *
- ************************************************************************
- */
-
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- ulong malloc_start;
-#if !defined(CONFIG_SYS_NO_FLASH)
- ulong flash_size;
-#endif
-
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
- bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
-
- monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
-
- /* Enable caches */
- enable_caches();
-
- debug("monitor flash len: %08lX\n", monitor_flash_len);
- board_init(); /* Setup chipselects */
- /*
- * TODO: printing of the clock inforamtion of the board is now
- * implemented as part of bdinfo command. Currently only support for
- * davinci SOC's is added. Remove this check once all the board
- * implement this.
- */
-#ifdef CONFIG_CLOCKS
- set_cpu_clk_info(); /* Setup clock information */
-#endif
- serial_initialize();
-
- debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
-#ifdef CONFIG_LOGBUFFER
- logbuff_init_ptrs();
-#endif
-#ifdef CONFIG_POST
- post_output_backlog();
-#endif
-
- /* The Malloc area is immediately below the monitor copy in DRAM */
- malloc_start = dest_addr - TOTAL_MALLOC_LEN;
- mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
-
-#ifdef CONFIG_ARCH_EARLY_INIT_R
- arch_early_init_r();
-#endif
- power_init_board();
-
-#if !defined(CONFIG_SYS_NO_FLASH)
- puts("Flash: ");
-
- flash_size = flash_init();
- if (flash_size > 0) {
-# ifdef CONFIG_SYS_FLASH_CHECKSUM
- print_size(flash_size, "");
- /*
- * Compute and print flash CRC if flashchecksum is set to 'y'
- *
- * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
- */
- if (getenv_yesno("flashchecksum") == 1) {
- printf(" CRC: %08X", crc32(0,
- (const unsigned char *) CONFIG_SYS_FLASH_BASE,
- flash_size));
- }
- putc('\n');
-# else /* !CONFIG_SYS_FLASH_CHECKSUM */
- print_size(flash_size, "\n");
-# endif /* CONFIG_SYS_FLASH_CHECKSUM */
- } else {
- puts(failed);
- hang();
- }
-#endif
-
-#if defined(CONFIG_CMD_NAND)
- puts("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
- onenand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
- puts("MMC: ");
- mmc_initialize(gd->bd);
-#endif
-
-#ifdef CONFIG_CMD_SCSI
- puts("SCSI: ");
- scsi_init();
-#endif
-
-#ifdef CONFIG_HAS_DATAFLASH
- AT91F_DataflashInit();
- dataflash_print_info();
-#endif
-
- /* initialize environment */
- if (should_load_env())
- env_relocate();
- else
- set_default_env(NULL);
-
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
- arm_pci_init();
-#endif
-
- stdio_init(); /* get the devices list going. */
-
- jumptable_init();
-
-#if defined(CONFIG_API)
- /* Initialize API */
- api_init();
-#endif
-
- console_init_r(); /* fully init console as a device */
-
-#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
-# ifdef CONFIG_OF_CONTROL
- /* Put this here so it appears on the LCD, now it is ready */
- display_fdt_model(gd->fdt_blob);
-# else
- checkboard();
-# endif
-#endif
-
-#if defined(CONFIG_ARCH_MISC_INIT)
- /* miscellaneous arch dependent initialisations */
- arch_misc_init();
-#endif
-#if defined(CONFIG_MISC_INIT_R)
- /* miscellaneous platform dependent initialisations */
- misc_init_r();
-#endif
-
- /* set up exceptions */
- interrupt_init();
- /* enable exceptions */
- enable_interrupts();
-
- /* Initialize from environment */
- load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_BOARD_LATE_INIT
- board_late_init();
-#endif
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
- puts("Net: ");
- eth_initialize();
-#if defined(CONFIG_RESET_PHY_R)
- debug("Reset Ethernet PHY\n");
- reset_phy();
-#endif
-#endif
-
-#ifdef CONFIG_POST
- post_run(NULL, POST_RAM | post_bootmode_get(0));
-#endif
-
-#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
- /*
- * Export available size of memory for Linux,
- * taking into account the protected RAM at top of memory
- */
- {
- ulong pram = 0;
- uchar memsz[32];
-
-#ifdef CONFIG_PRAM
- pram = getenv_ulong("pram", 10, CONFIG_PRAM);
-#endif
-#ifdef CONFIG_LOGBUFFER
-#ifndef CONFIG_ALT_LB_ADDR
- /* Also take the logbuffer into account (pram is in kB) */
- pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
-#endif
-#endif
- sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
- setenv("mem", (char *)memsz);
- }
-#endif
-
- /* main_loop() can return to retry autoboot, if so just run it again. */
- for (;;) {
- main_loop();
- }
-
- /* NOTREACHED - no way out of command loop except booting */
-}
bool "Atmel AT91RM9200 evaluation kit"
select CPU_ARM920T
-config TARGET_EB_CPUX9K2
- bool "Support eb_cpux9k2"
- select CPU_ARM920T
-
-config TARGET_CPUAT91
- bool "Support cpuat91"
- select CPU_ARM920T
-
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
select CPU_ARM926EJS
bool "Ronetix pm9263 board"
select CPU_ARM926EJS
-config TARGET_STAMP9G20
- bool "Support stamp9g20"
- select CPU_ARM926EJS
-
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select CPU_ARM926EJS
select CPU_V7
select SUPPORT_SPL
-config TARGET_VL_MA2SC
- bool "Support vl_ma2sc"
- select CPU_ARM926EJS
-
config TARGET_MEESC
bool "Support meesc"
select CPU_ARM926EJS
-config TARGET_OTC570
- bool "Support otc570"
- select CPU_ARM926EJS
-
-config TARGET_CPU9260
- bool "Support cpu9260"
- select CPU_ARM926EJS
-
config TARGET_CORVUS
bool "Support corvus"
select CPU_ARM926EJS
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
-source "board/BuS/eb_cpux9k2/Kconfig"
-source "board/eukrea/cpuat91/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
-source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
-source "board/esd/otc570/Kconfig"
-source "board/eukrea/cpu9260/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
-source "board/taskit/stamp9g20/Kconfig"
endif
prompt "DaVinci board select"
optional
-config TARGET_ENBW_CMC
- bool "EnBW CMC board"
-
config TARGET_IPAM390
bool "IPAM390 board"
select SUPPORT_SPL
-config TARGET_DA830EVM
- bool "DA830 EVM board"
-
config TARGET_DA850EVM
bool "DA850 EVM board"
select SUPPORT_SPL
-config TARGET_OMAPL138_LCDK
- bool "OMAPL138 LCDK"
- select SUPPORT_SPL
-
-config TARGET_DAVINCI_DM355EVM
- bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
- bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
- bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
- bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
- bool "DVEVM board"
-
config TARGET_EA20
bool "EA20 board"
-config TARGET_DAVINCI_SCHMOOGIE
- bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
- bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
- bool "Sonata board"
+config TARGET_OMAPL138_LCDK
+ bool "OMAPL138 LCDK"
+ select SUPPORT_SPL
config TARGET_CALIMAIN
bool "Calimain board"
config SYS_SOC
default "davinci"
-source "board/enbw/enbw_cmc/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
source "board/omicron/calimain/Kconfig"
endif
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
-#define BIT(x) (1 << (x))
-
/* SOC-specific pll info */
#ifdef CONFIG_SOC_DM355
#define ARM_PLLDIV PLLC_PLLDIV1
{
enum periph_id id;
+ if (cpu_is_exynos4())
+ return exynos4_get_mmc_clk(dev_index);
+
switch (dev_index) {
case 0:
id = PERIPH_ID_SDMMC0;
return -1;
}
- if (cpu_is_exynos5())
- return clock_get_periph_rate(id);
- else if (cpu_is_exynos4())
- return exynos4_get_mmc_clk(dev_index);
-
- return 0;
+ return clock_get_periph_rate(id);
}
void set_mmc_clk(int dev_index, unsigned int div)
#include <asm/arch/hardware.h>
-#define BIT(x) (1 << (x))
-
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl; /* 00 */
#endif
-#define BIT(x) (1 << (x))
-
#define KS2_DDRPHY_PIR_OFFSET 0x04
#define KS2_DDRPHY_PGCR0_OFFSET 0x08
#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
prompt "Marvell Kirkwood board select"
optional
-config TARGET_OPENRD
- bool "Marvell OpenRD Board"
-
-config TARGET_MV88F6281GTW_GE
- bool "MV88f6281GTW_GE Board"
-
-config TARGET_RD6281A
- bool "RD6281A Board"
-
config TARGET_DREAMPLUG
bool "DreamPlug Board"
config TARGET_ICONNECT
bool "iconnect Board"
-config TARGET_TK71
- bool "TK71 Board"
-
config TARGET_KM_KIRKWOOD
bool "KM_KIRKWOOD Board"
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
-config TARGET_WIRELESS_SPACE
- bool "LaCie Wireless_space Board"
-
config TARGET_IB62X0
bool "ib62x0 Board"
config SYS_SOC
default "kirkwood"
-source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
-source "board/Marvell/rd6281a/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
-source "board/karo/tk71/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
int arch_cpu_init(void)
{
-#ifndef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
+ /*
+ * Only with disabled MMU its possible to switch the base
+ * register address on Armada 38x. Without this the SDRAM
+ * located at >= 0x4000.0000 is also not accessible, as its
+ * still locked to cache.
+ */
+ mmu_disable();
+#endif
+
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+ set_cbar(SOC_REGS_PHY_BASE + 0xC000);
+
+#if !defined(CONFIG_SPL_BUILD)
+ /*
+ * From this stage on, the SoC detection is working. As we have
+ * configured the internal register base to the value used
+ * in the macros / defines in the U-Boot header (soc.h).
+ */
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
/*
- * Only with disabled MMU its possible to switch the base
- * register address on Armada 38x. Without this the SDRAM
- * located at >= 0x4000.0000 is also not accessible, as its
- * still locked to cache.
- *
- * So to fully release / unlock this area from cache, we need
- * to first flush all caches, then disable the MMU and
- * disable the L2 cache.
+ * To fully release / unlock this area from cache, we need
+ * to flush all caches and disable the L2 cache.
*/
icache_disable();
dcache_disable();
- mmu_disable();
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif
- /* Linux expects the internal registers to be at 0xf1000000 */
- writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
- set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-
/*
* We need to call mvebu_mbus_probe() before calling
* update_sdram_window_sizes() as it disables all previously
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
-#define BIT(x) (1 << (x))
-
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
-static int init_done;
+static int init_done __attribute__((section(".data"))) = 0;
/* Timer reload and current value registers */
struct kwtmr_val {
+++ /dev/null
-if ARCH_NOMADIK
-
-choice
- prompt "Nomadik board select"
- optional
-
-config NOMADIK_NHK8815
- bool "ST 8815 Nomadik Hardware Kit"
-
-endchoice
-
-config SYS_SOC
- default "nomadik"
-
-source "board/st/nhk8815/Kconfig"
-
-endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o gpio.o
-obj-y += reset.o
+++ /dev/null
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
- NOMADIK_GPIO0_BASE,
- NOMADIK_GPIO1_BASE,
- NOMADIK_GPIO2_BASE,
- NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
- GPIO_DAT = 0x00, /* data register */
- GPIO_DATS = 0x04, /* data set */
- GPIO_DATC = 0x08, /* data clear */
- GPIO_PDIS = 0x0c, /* pull disable */
- GPIO_DIR = 0x10, /* direction */
- GPIO_DIRS = 0x14, /* direction set */
- GPIO_DIRC = 0x18, /* direction clear */
- GPIO_AFSLA = 0x20, /* alternate function select A */
- GPIO_AFSLB = 0x24, /* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
- return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
- return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
- u32 afunc, bfunc;
-
- /* alternate function is 0..3, with one bit per register */
- afunc = readl(base + GPIO_AFSLA) & ~bit;
- bfunc = readl(base + GPIO_AFSLB) & ~bit;
- if (alternate_function & 1) afunc |= bit;
- if (alternate_function & 2) bfunc |= bit;
- writel(afunc, base + GPIO_AFSLA);
- writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (dir)
- writel(bit, base + GPIO_DIRS);
- else
- writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (val)
- writel(bit, base + GPIO_DATS);
- else
- writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- return readl(base + GPIO_DAT) & bit;
-}
+++ /dev/null
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __NMK_GPIO_H__
-#define __NMK_GPIO_H__
-
-/*
- * These functions are called from the soft-i2c driver, but
- * are also used by board files to set output bits.
- */
-
-enum nmk_af { /* alternate function settings */
- GPIO_GPIO = 0,
- GPIO_ALT_A,
- GPIO_ALT_B,
- GPIO_ALT_C
-};
-
-extern void nmk_gpio_af(int gpio, int alternate_function);
-extern void nmk_gpio_dir(int gpio, int dir);
-extern void nmk_gpio_set(int gpio, int val);
-extern int nmk_gpio_get(int gpio);
-
-#endif /* __NMK_GPIO_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
-#define MTU_RIS 0x04 /* Raw interrupt status */
-#define MTU_MIS 0x08 /* Masked interrupt status */
-#define MTU_ICR 0x0C /* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
-#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
-#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
-#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA 0x80
-#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK 0x0c
-#define MTU_CRn_PRESCALE_1 0x00
-#define MTU_CRn_PRESCALE_16 0x04
-#define MTU_CRn_PRESCALE_256 0x08
-#define MTU_CRn_32BITS 0x02
-#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR 0xff0
-#define MTU_ITOP 0xff4
-
-#define MTU_PERIPH_ID0 0xfe0
-#define MTU_PERIPH_ID1 0xfe4
-#define MTU_PERIPH_ID2 0xfe8
-#define MTU_PERIPH_ID3 0xfeC
-
-#define MTU_PCELL0 0xff0
-#define MTU_PCELL1 0xff4
-#define MTU_PCELL2 0xff8
-#define MTU_PCELL3 0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
+++ /dev/null
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
- ldr r1, =0x1
- str r1, [r0, #0x18]
-
-_loop_forever:
- b _loop_forever
+++ /dev/null
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK (24 * 100 * 1000)
-#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
-#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
- ulong val;
-
- writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
- CONFIG_SYS_TIMERBASE + MTU_CR(0));
-
- /* Reset the timer */
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
- /*
- * The load-register isn't really immediate: it changes on clock
- * edges, so we must wait for our newly-written value to appear.
- * Since we might miss reading 0, wait for any change in value.
- */
- val = READ_TIMER();
- while (READ_TIMER() == val)
- ;
-
- return 0;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
- return TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
- ulong ini, end;
-
- ini = READ_TIMER();
- end = ini + USEC_TO_COUNT(usec);
- while ((signed)(end - READ_TIMER()) > 0)
- ;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
debug("DRAM init failed: %d\n", ret);
return;
}
+
+ /*
+ * Now that DRAM is initialized setup base pointer for simple malloc
+ * into RAM.
+ */
+ gd->malloc_base = CONFIG_SPL_STACK_R_ADDR;
+ gd->malloc_ptr = 0;
}
static int setup_led(void)
default "socfpga"
config SYS_CONFIG_NAME
- default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
- default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
writel(mask, &clkrst->crc_cpu_cmplx_clr);
}
+unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
+{
+ return parent_rate;
+}
+
unsigned clock_get_rate(enum clock_id clkid)
{
struct clk_pll *pll;
if (clkid == CLOCK_ID_OSC)
return parent_rate;
+ if (clkid == CLOCK_ID_CLK_M)
+ return clk_m_get_rate(parent_rate);
+
pll = get_pll(clkid);
if (!pll)
return 0;
* PLLU uses p_mask/p_shift for VCO on all but T210,
* T210 uses normal DIVP. Handled in pllinfo table.
*/
- divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
+#ifdef CONFIG_TEGRA210
+ /*
+ * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
+ * not applied. pllP_out2 does have divp applied. All other pllP_outN
+ * are divided down from pllP_out0. We only support pllP_out0 in
+ * U-Boot at the time of writing this comment.
+ */
+ if (clkid != CLOCK_ID_PERIPH)
+#endif
+ divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
do_div(rate, divm);
return rate;
}
pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+ pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
+ debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
tegra30_set_up_pllp();
+ /* clear IDDQ before accessing any other PLLC registers */
+ pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+ udelay(2);
+
/*
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val;
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+ freq = clock_get_rate(CLOCK_ID_CLK_M);
+ debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
tegra30_set_up_pllp();
+ /* clear IDDQ before accessing any other PLLC registers */
+ pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+ udelay(2);
+
/*
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val;
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+ freq = clock_get_rate(CLOCK_ID_CLK_M);
+ debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
+config TARGET_P2371_2180
+ bool "NVIDIA Tegra210 P2371-2180 board"
+ help
+ P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
+ combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+ micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
+ two GPIO expansion headers.
+
config TARGET_P2571
bool "NVIDIA Tegra210 P2571 base board"
help
source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
+source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
endif
udelay(2);
}
+unsigned int clk_m_get_rate(unsigned parent_rate)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 value, div;
+
+ value = readl(&clkrst->crc_spare_reg0);
+ div = ((value >> 2) & 0x3) + 1;
+
+ return parent_rate / div;
+}
+
void arch_timer_init(void)
{
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val;
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+ freq = clock_get_rate(CLOCK_ID_CLK_M);
+ debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
- /* ARM CNTFRQ */
-#ifndef CONFIG_ARM64
- asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
-#endif
+ if (current_el() == 3)
+ asm("msr cntfrq_el0, %0\n" : : "r" (freq));
/* Only Tegra114+ has the System Counter regs */
debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
config UNIPHIER_SMP
bool
-choice
- prompt "UniPhier SoC select"
- default MACH_PH1_PRO4
-
-config MACH_PH1_SLD3
- bool "PH1-sLD3"
+config ARCH_UNIPHIER_PH1_SLD3
+ bool "UniPhier PH1-sLD3 SoC"
select UNIPHIER_SMP
+ help
+ This enables support for UniPhier PH1-sLD3 SoC.
-config MACH_PH1_LD4
- bool "PH1-LD4"
+config ARCH_UNIPHIER_PH1_LD4
+ bool "UniPhier PH1-LD4 SoC"
+ depends on !ARCH_UNIPHIER_PH1_SLD3
+ help
+ This enables support for UniPhier PH1-LD4 SoC.
-config MACH_PH1_PRO4
- bool "PH1-Pro4"
+config ARCH_UNIPHIER_PH1_PRO4
+ bool "UniPhier PH1-Pro4 SoC"
select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
+ help
+ This enables support for UniPhier PH1-Pro4 SoC.
-config MACH_PH1_SLD8
- bool "PH1-sLD8"
-
-endchoice
+config ARCH_UNIPHIER_PH1_SLD8
+ bool "UniPhier PH1-sLD8 SoC"
+ depends on !ARCH_UNIPHIER_PH1_SLD3
+ help
+ This enables support for UniPhier PH1-sLD8 SoC.
-choice
- prompt "UniPhier Support Card select"
- optional
+config ARCH_UNIPHIER_PH1_PRO5
+ bool "UniPhier PH1-Pro5 SoC"
+ select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
+ help
+ This enables support for UniPhier PH1-Pro5 SoC.
-config PFC_MICRO_SUPPORT_CARD
- bool "Support card with PFC CPLD"
+config ARCH_UNIPHIER_PROXSTREAM2
+ bool "UniPhier ProXstream2 SoC"
+ select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
help
- This option provides support for the expansion board with PFC
- original address mapping.
+ This enables support for UniPhier ProXstream2 SoC.
- Say Y to use the on-board UART, Ether, LED devices.
+config ARCH_UNIPHIER_PH1_LD6B
+ bool "UniPhier PH1-LD6b SoC"
+ select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
+ help
+ This enables support for UniPhier PH1-LD6b SoC.
-config DCC_MICRO_SUPPORT_CARD
- bool "Support card with DCC CPLD"
+config MICRO_SUPPORT_CARD
+ bool "Use Micro Support Card"
help
- This option provides support for the expansion board with DCC-
- arranged address mapping that is compatible with legacy UniPhier
- reference boards.
+ This option provides support for the expansion board, available
+ on some UniPhier reference boards.
Say Y to use the on-board UART, Ether, LED devices.
-endchoice
-
config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
-choice
- prompt "DDR3 Frequency select"
-
-config DDR_FREQ_1600
- bool "DDR3 1600"
- depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
-
-config DDR_FREQ_1333
- bool "DDR3 1333"
- depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
-
-endchoice
-
-config DDR_FREQ
- int
- default 1333 if DDR_FREQ_1333
- default 1600 if DDR_FREQ_1600
-
endif
obj-y += lowlevel_init.o
obj-y += init_page_table.o
-obj-y += spl.o
-obj-y += memconf.o
-obj-y += ddrphy_training.o
+obj-y += boards.o
+
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
+
+obj-$(CONFIG_DEBUG_LL) += debug_ll.o
else
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+obj-y += pinctrl/ clk/
+
endif
obj-y += timer.o
+obj-y += soc_info.o
+obj-y += boot-mode/
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
-
-obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/bcu-regs.h>
+#include <mach/init.h>
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
+{
+ int shift;
+
+ writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
+ writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
+
+ /* Specify DDR channel */
+ shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
+ writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/bcu-regs.h>
+#include <mach/init.h>
+
+#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
+
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
+{
+ int shift;
+
+ writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
+ writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
+ /*
+ * 0xe0000000-0xefffffff: Ex-bus
+ * 0xf0000000-0xfbffffff: ASM bus
+ * 0xfc000000-0xffffffff: OCM bus
+ */
+ writel(0x24440000, BCSCR5);
+
+ /* Specify DDR channel */
+ shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
+ writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
+
+ shift -= 32;
+ writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+
+ return 0;
+}
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <mach/led.h>
+#include <mach/micro-support-card.h>
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
int board_init(void)
{
- led_write(U, B, O, O);
+ led_puts("Uboo");
return 0;
}
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
- gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
-}
-#endif
/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/led.h>
-#include <mach/board.h>
-
-void pin_init(void);
-void clkrst_init(void);
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+#include <mach/soc_info.h>
int board_early_init_f(void)
{
- led_write(U, 0, , );
-
- pin_init();
-
- led_write(U, 1, , );
+ led_puts("U0");
- clkrst_init();
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_pin_init();
+ led_puts("U1");
+ ph1_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ case SOC_UNIPHIER_PH1_LD4:
+ ph1_ld4_pin_init();
+ led_puts("U1");
+ ph1_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ case SOC_UNIPHIER_PH1_PRO4:
+ ph1_pro4_pin_init();
+ led_puts("U1");
+ ph1_pro4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_sld8_pin_init();
+ led_puts("U1");
+ ph1_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_pin_init();
+ led_puts("U1");
+ ph1_pro5_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ proxstream2_pin_init();
+ led_puts("U1");
+ proxstream2_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PH1_LD6B:
+ ph1_ld6b_pin_init();
+ led_puts("U1");
+ proxstream2_clk_init();
+ break;
+#endif
+ default:
+ break;
+ }
- led_write(U, 2, , );
+ led_puts("U2");
return 0;
}
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <mach/board.h>
+#include <mach/micro-support-card.h>
int board_early_init_r(void)
{
- uniphier_board_late_init();
+ support_card_late_init();
return 0;
}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <libfdt.h>
+#include <linux/kernel.h>
+#include <mach/init.h>
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+static const struct uniphier_board_data ph1_sld3_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x20000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xc0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 16,
+ .dram_ch2_base = 0xc0000000,
+ .dram_ch2_size = 0x10000000,
+ .dram_ch2_width = 16,
+ .dram_freq = 1600,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+static const struct uniphier_board_data ph1_ld4_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x10000000,
+ .dram_ch0_width = 16,
+ .dram_ch1_base = 0x90000000,
+ .dram_ch1_size = 0x10000000,
+ .dram_ch1_width = 16,
+ .dram_freq = 1600,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+static const struct uniphier_board_data ph1_pro4_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x20000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xa0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_freq = 1600,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+static const struct uniphier_board_data ph1_sld8_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x10000000,
+ .dram_ch0_width = 16,
+ .dram_ch1_base = 0x90000000,
+ .dram_ch1_size = 0x10000000,
+ .dram_ch1_width = 16,
+ .dram_freq = 1333,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+static const struct uniphier_board_data ph1_pro5_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x20000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xa0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_freq = 1866,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data proxstream2_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x40000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xc0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_ch2_base = 0xe0000000,
+ .dram_ch2_size = 0x20000000,
+ .dram_ch2_width = 16,
+ .dram_freq = 1866,
+};
+#endif
+
+struct uniphier_board_id {
+ const char *compatible;
+ const struct uniphier_board_data *param;
+};
+
+static const struct uniphier_board_id uniphier_boards[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ { "socionext,ph1-sld3", &ph1_sld3_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ { "socionext,ph1-ld4", &ph1_ld4_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ { "socionext,ph1-pro4", &ph1_pro4_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ { "socionext,ph1-sld8", &ph1_sld8_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ { "socionext,ph1-pro5", &ph1_pro5_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ { "socionext,proxstream2", &proxstream2_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ { "socionext,ph1-ld6b", &proxstream2_data, },
+#endif
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
+ if (!fdt_node_check_compatible(fdt, 0,
+ uniphier_boards[i].compatible))
+ return uniphier_boards[i].param;
+ }
+
+ return NULL;
+}
--- /dev/null
+obj-y += boot-mode.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sg-regs.h>
+#include <mach/sbc-regs.h>
+
+struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 ph1_ld4_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void ph1_ld4_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ { /* sentinel */ }
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 ph1_pro5_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void ph1_pro5_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sg-regs.h>
+#include <mach/sbc-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "External Master"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+ return readl(SG_PINMON0) & 0x3f;
+}
+
+u32 ph1_sld3_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void ph1_sld3_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 proxstream2_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void proxstream2_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sbc-regs.h>
+#include <mach/soc_info.h>
+
+u32 spl_boot_device(void)
+{
+ if (boot_is_swapped())
+ return BOOT_DEVICE_NOR;
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ return ph1_sld3_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_LD4:
+ case SOC_UNIPHIER_PH1_PRO4:
+ case SOC_UNIPHIER_PH1_SLD8:
+ return ph1_ld4_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ return ph1_pro5_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ return proxstream2_boot_device();
+#endif
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += clk-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += clk-proxstream2.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void ph1_ld4_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void ph1_pro4_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
+ SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void ph1_pro5_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void proxstream2_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mach/boot-device.h>
#include <mach/sbc-regs.h>
+#include <mach/soc_info.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int mode_sel, i;
-
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; boot_device_table[i].info; i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_LD4:
+ case SOC_UNIPHIER_PH1_PRO4:
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_ld4_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ proxstream2_boot_mode_show();
+ break;
+#endif
+ default:
+ break;
+ }
return 0;
}
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <mach/ddrphy-regs.h>
+
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8253c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a82dbc0, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000800, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <mach/ddrphy-regs.h>
+
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000000, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <mach/ddrphy-regs.h>
+
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, &phy->mr3);
+#else
+ writel(0x00000800, &phy->mr3);
+#endif
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/ddrphy-regs.h>
+
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+{
+ int dx;
+ u32 __iomem tmp, *p;
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ p = &phy->dx[dx].gcr;
+
+ tmp = readl(p);
+ /* Specify the rank that should be write leveled */
+ tmp &= ~DXGCR_WLRKEN_MASK;
+ tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
+ writel(tmp, p);
+ }
+
+ p = &phy->dtcr;
+
+ tmp = readl(p);
+ /* Specify the rank used during data bit deskew and eye centering */
+ tmp &= ~DTCR_DTRANK_MASK;
+ tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+ /* Use Multi-Purpose Register for DQS gate training */
+ tmp |= DTCR_DTMPR;
+ /* Specify the rank enabled for data-training */
+ tmp &= ~DTCR_RNKEN_MASK;
+ tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
+ writel(tmp, p);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static struct ddrphy_init_sequence init_sequence[] = {
+ {
+ "DRAM Initialization",
+ PIR_DRAMRST | PIR_DRAMINIT,
+ PGSR0_DIDONE,
+ PGSR0_DIERR
+ },
+ {
+ "Write Leveling",
+ PIR_WL,
+ PGSR0_WLDONE,
+ PGSR0_WLERR
+ },
+ {
+ "Read DQS Gate Training",
+ PIR_QSGATE,
+ PGSR0_QSGDONE,
+ PGSR0_QSGERR
+ },
+ {
+ "Write Leveling Adjustment",
+ PIR_WLADJ,
+ PGSR0_WLADONE,
+ PGSR0_WLAERR
+ },
+ {
+ "Read Bit Deskew",
+ PIR_RDDSKW,
+ PGSR0_RDDONE,
+ PGSR0_RDERR
+ },
+ {
+ "Write Bit Deskew",
+ PIR_WRDSKW,
+ PGSR0_WDDONE,
+ PGSR0_WDERR
+ },
+ {
+ "Read Eye Training",
+ PIR_RDEYE,
+ PGSR0_REDONE,
+ PGSR0_REERR
+ },
+ {
+ "Write Eye Training",
+ PIR_WREYE,
+ PGSR0_WEDONE,
+ PGSR0_WEERR
+ }
+};
+
+int ddrphy_training(struct ddrphy __iomem *phy)
+{
+ int i;
+ u32 pgsr0;
+ u32 init_flag = PIR_INIT;
+ u32 done_flag = PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ init_flag |= init_sequence[i].init_flag;
+ done_flag |= init_sequence[i].done_flag;
+ }
+
+ writel(init_flag, &phy->pir);
+
+ do {
+ if (--timeout < 0) {
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+ return -1;
+ }
+ udelay(1);
+ pgsr0 = readl(&phy->pgsr[0]);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ if (pgsr0 & init_sequence[i].err_flag) {
+ printf("%s: error: %s failed\n", __func__,
+ init_sequence[i].description);
+ return -1;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
-{
- int dx;
- u32 __iomem tmp, *p;
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- p = &phy->dx[dx].gcr;
-
- tmp = readl(p);
- /* Specify the rank that should be write leveled */
- tmp &= ~DXGCR_WLRKEN_MASK;
- tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
- writel(tmp, p);
- }
-
- p = &phy->dtcr;
-
- tmp = readl(p);
- /* Specify the rank used during data bit deskew and eye centering */
- tmp &= ~DTCR_DTRANK_MASK;
- tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
- /* Use Multi-Purpose Register for DQS gate training */
- tmp |= DTCR_DTMPR;
- /* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RNKEN_MASK;
- tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
- writel(tmp, p);
-}
-
-struct ddrphy_init_sequence {
- char *description;
- u32 init_flag;
- u32 done_flag;
- u32 err_flag;
-};
-
-static struct ddrphy_init_sequence init_sequence[] = {
- {
- "DRAM Initialization",
- PIR_DRAMRST | PIR_DRAMINIT,
- PGSR0_DIDONE,
- PGSR0_DIERR
- },
- {
- "Write Leveling",
- PIR_WL,
- PGSR0_WLDONE,
- PGSR0_WLERR
- },
- {
- "Read DQS Gate Training",
- PIR_QSGATE,
- PGSR0_QSGDONE,
- PGSR0_QSGERR
- },
- {
- "Write Leveling Adjustment",
- PIR_WLADJ,
- PGSR0_WLADONE,
- PGSR0_WLAERR
- },
- {
- "Read Bit Deskew",
- PIR_RDDSKW,
- PGSR0_RDDONE,
- PGSR0_RDERR
- },
- {
- "Write Bit Deskew",
- PIR_WRDSKW,
- PGSR0_WDDONE,
- PGSR0_WDERR
- },
- {
- "Read Eye Training",
- PIR_RDEYE,
- PGSR0_REDONE,
- PGSR0_REERR
- },
- {
- "Write Eye Training",
- PIR_WREYE,
- PGSR0_WEDONE,
- PGSR0_WEERR
- }
-};
-
-int ddrphy_training(struct ddrphy __iomem *phy)
-{
- int i;
- u32 pgsr0;
- u32 init_flag = PIR_INIT;
- u32 done_flag = PGSR0_IDONE;
- int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
- ulong start = get_timer(0);
-#endif
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- init_flag |= init_sequence[i].init_flag;
- done_flag |= init_sequence[i].done_flag;
- }
-
- writel(init_flag, &phy->pir);
-
- do {
- if (--timeout < 0) {
- printf("%s: error: timeout during DDR training\n",
- __func__);
- return -1;
- }
- udelay(1);
- pgsr0 = readl(&phy->pgsr[0]);
- } while ((pgsr0 & done_flag) != done_flag);
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- if (pgsr0 & init_sequence[i].err_flag) {
- printf("%s: error: %s failed\n", __func__,
- init_sequence[i].description);
- return -1;
- }
- }
-
-#ifdef DISPLAY_ELAPSED_TIME
- printf("%s: info: elapsed time %ld msec\n", get_timer(start));
-#endif
-
- return 0;
-}
--- /dev/null
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/linkage.h>
+#include <mach/bcu-regs.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE 115200
+#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
+
+ENTRY(debug_ll_init)
+ ldr r0, =SG_REVISION
+ ldr r1, [r0]
+ and r1, r1, #SG_REVISION_TYPE_MASK
+ mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+#define PH1_SLD3_UART_CLK 36864000
+ cmp r1, #0x25
+ bne ph1_sld3_end
+
+ sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
+
+ ldr r0, =BCSCR5
+ ldr r1, =0x24440000
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_sld3_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+#define PH1_LD4_UART_CLK 36864000
+ cmp r1, #0x26
+ bne ph1_ld4_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
+
+ ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_ld4_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+#define PH1_PRO4_UART_CLK 73728000
+ cmp r1, #0x28
+ bne ph1_pro4_end
+
+ sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_pro4_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+#define PH1_SLD8_UART_CLK 80000000
+ cmp r1, #0x29
+ bne ph1_sld8_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
+
+ ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_sld8_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+#define PH1_PRO5_UART_CLK 73728000
+ cmp r1, #0x2A
+ bne ph1_pro5_end
+
+ sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
+ sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
+ sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_pro5_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+#define PROXSTREAM2_UART_CLK 88900000
+ cmp r1, #0x2E
+ bne proxstream2_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
+ sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
+ sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+proxstream2_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#define PH1_LD6B_UART_CLK 88900000
+ cmp r1, #0x2F
+ bne ph1_ld6b_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
+ sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_ld6b_end:
+#endif
+
+init_uart:
+ addruart r0, r1, r2
+ mov r1, #UART_LCR_WLEN8 << 8
+ str r1, [r0, #0x10]
+ str r3, [r0, #0x24]
+
+ mov pc, lr
+ENDPROC(debug_ll_init)
/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/memory");
+ if (offset < 0)
+ return NULL;
+
+ return fdt_getprop(fdt, offset, "reg", lenp);
+}
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ const fdt32_t *val;
+ int len;
+
+ val = get_memory_reg_prop(gd->fdt_blob, &len);
+ if (len < sizeof(*val))
+ return -EINVAL;
+
+ gd->ram_size = fdt32_to_cpu(*(val + 1));
+
+ debug("DRAM size = %08lx\n", gd->ram_size);
return 0;
}
+
+void dram_init_banksize(void)
+{
+ const fdt32_t *val;
+ int len, i;
+
+ val = get_memory_reg_prop(gd->fdt_blob, &len);
+ if (len < 0)
+ return;
+
+ len /= sizeof(*val);
+ len /= 2;
+
+ for (i = 0; i < len; i++) {
+ gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
+ gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
+
+ debug("DRAM bank %d: start = %08lx, size = %08lx\n",
+ i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+ }
+}
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += early-clk-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += early-clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += early-clk-proxstream2.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+
+ tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /*
+ * deassert reset
+ * UMCA2: Ch1 (DDR3)
+ * UMCA1, UMC31: Ch0 (WIO1)
+ * UMCA0, UMC30: Ch0 (WIO0)
+ */
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
+ SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ if (spl_boot_device() != BOOT_DEVICE_NAND) {
+ tmp = readl(SC_RSTCTRL);
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ };
+
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
+ SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL4); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
+ SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+
+ return 0;
+}
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
+ sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
+
+ sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
+ sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
+
+ sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
+ sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
+#endif
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
- defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-void support_card_reset(void);
-void support_card_init(void);
-void support_card_late_init(void);
-int check_support_card(void);
-#else
-#define support_card_reset() do {} while (0)
-#define support_card_init() do {} while (0)
-#define support_card_late_init() do {} while (0)
-static inline int check_support_card(void)
-{
- return 0;
-}
-#endif
-
-static inline void uniphier_board_reset(void)
-{
- support_card_reset();
-}
-
-static inline void uniphier_board_init(void)
-{
- support_card_init();
-}
-
-static inline void uniphier_board_late_init(void)
-{
- support_card_late_init();
-}
-
-#endif /* ARCH_BOARD_H */
/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
-int get_boot_mode_sel(void);
-
struct boot_device_info {
u32 type;
char *info;
};
-extern struct boot_device_info boot_device_table[];
+u32 ph1_sld3_boot_device(void);
+u32 ph1_ld4_boot_device(void);
+u32 ph1_pro5_boot_device(void);
+u32 proxstream2_boot_device(void);
+
+void ph1_sld3_boot_mode_show(void);
+void ph1_ld4_boot_mode_show(void);
+void ph1_pro5_boot_mode_show(void);
+void proxstream2_boot_mode_show(void);
#endif /* _ASM_BOOT_DEVICE_H_ */
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
-#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define NR_DDRPHY_PER_CH 1
#else
#define NR_DDRPHY_PER_CH 2
#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
#ifndef __ASSEMBLY__
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/serial_reg.h>
-
-#if !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include CONFIG_DEBUG_LL_INCLUDE
-#endif
-
-#define BAUDRATE 115200
-#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
-#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
-
- .macro init_debug_uart, ra, rb, rc
- addruart \ra, \rb, \rc
- mov \rb, #UART_LCR_WLEN8 << 8
- str \rb, [\ra, #0x10]
- ldr \rb, =DIVISOR
- str \rb, [\ra, #0x24]
- .endm
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+struct uniphier_board_data {
+ unsigned long dram_ch0_base;
+ unsigned long dram_ch0_size;
+ unsigned long dram_ch0_width;
+ unsigned long dram_ch1_base;
+ unsigned long dram_ch1_size;
+ unsigned long dram_ch1_width;
+ unsigned long dram_ch2_base;
+ unsigned long dram_ch2_size;
+ unsigned long dram_ch2_width;
+ unsigned int dram_freq;
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
+
+int ph1_sld3_init(const struct uniphier_board_data *bd);
+int ph1_ld4_init(const struct uniphier_board_data *bd);
+int ph1_pro4_init(const struct uniphier_board_data *bd);
+int ph1_sld8_init(const struct uniphier_board_data *bd);
+int ph1_pro5_init(const struct uniphier_board_data *bd);
+int proxstream2_init(const struct uniphier_board_data *bd);
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
+int proxstream2_sbc_init(const struct uniphier_board_data *bd);
+#else
+static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+#endif
+
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
+
+int memconf_init(const struct uniphier_board_data *bd);
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
+int proxstream2_memconf_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+
+void ph1_sld3_pin_init(void);
+void ph1_ld4_pin_init(void);
+void ph1_pro4_pin_init(void);
+void ph1_sld8_pin_init(void);
+void ph1_pro5_pin_init(void);
+void proxstream2_pin_init(void);
+void ph1_ld6b_pin_init(void);
+
+void ph1_ld4_clk_init(void);
+void ph1_pro4_clk_init(void);
+void ph1_pro5_clk_init(void);
+void proxstream2_clk_init(void);
+
+#define pr_err(fmt, args...) printf(fmt, ##args)
+
+#endif /* __MACH_INIT_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_LED_H
-#define ARCH_LED_H
-
-#include <config.h>
-
-#define LED_CHAR_0 0x7e
-#define LED_CHAR_1 0x0c
-#define LED_CHAR_2 0xb6
-#define LED_CHAR_3 0x9e
-#define LED_CHAR_4 0xcc
-#define LED_CHAR_5 0xda
-#define LED_CHAR_6 0xfa
-#define LED_CHAR_7 0x4e
-#define LED_CHAR_8 0xfe
-#define LED_CHAR_9 0xde
-
-#define LED_CHAR_A 0xee
-#define LED_CHAR_B 0xf8
-#define LED_CHAR_C 0x72
-#define LED_CHAR_D 0xbc
-#define LED_CHAR_E 0xf2
-#define LED_CHAR_F 0xe2
-#define LED_CHAR_G 0x7a
-#define LED_CHAR_H 0xe8
-#define LED_CHAR_I 0x08
-#define LED_CHAR_J 0x3c
-#define LED_CHAR_K 0xea
-#define LED_CHAR_L 0x70
-#define LED_CHAR_M 0x6e
-#define LED_CHAR_N 0xa8
-#define LED_CHAR_O 0xb8
-#define LED_CHAR_P 0xe6
-#define LED_CHAR_Q 0xce
-#define LED_CHAR_R 0xa0
-#define LED_CHAR_S 0xc8
-#define LED_CHAR_T 0x8c
-#define LED_CHAR_U 0x7c
-#define LED_CHAR_V 0x54
-#define LED_CHAR_W 0xfc
-#define LED_CHAR_X 0xec
-#define LED_CHAR_Y 0xdc
-#define LED_CHAR_Z 0xa4
-
-#define LED_CHAR_SPACE 0x00
-#define LED_CHAR_DOT 0x01
-
-#define LED_CHAR_ (LED_CHAR_SPACE)
-
-/** Macro to translate 4 characters into integer to display led */
-#define LED_C2I(C0, C1, C2, C3) \
- (~( \
- (LED_CHAR_##C0 << 24) | \
- (LED_CHAR_##C1 << 16) | \
- (LED_CHAR_##C2 << 8) | \
- (LED_CHAR_##C3) \
- ))
-
-#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
-
-#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
-
-#ifdef __ASSEMBLY__
-
-#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
-.macro raw_led_write data
- ldr r0, =\data
- ldr r1, =LED_ADDR
- str r0, [r1]
-.endm
-
-#else /* __ASSEMBLY__ */
-
-#include <linux/io.h>
-
-#define led_write(C0, C1, C2, C3) \
-do { \
- raw_led_write(LED_C2I(C0, C1, C2, C3)); \
-} while (0)
-
-static inline void raw_led_write(u32 data)
-{
- writel(data, LED_ADDR);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#else /* CONFIG_SUPPORT_CARD_LED_BASE */
-
-#define led_write(C0, C1, C2, C3)
-#define raw_led_write(x)
-
-#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
-
-#endif /* ARCH_LED_H */
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+void support_card_late_init(void);
+int check_support_card(void);
+void led_puts(const char *s);
+#else
+static inline void support_card_reset(void)
+{
+}
+
+static inline void support_card_init(void)
+{
+}
+
+static inline void support_card_late_init(void)
+{
+}
+
+static inline int check_support_card(void)
+{
+ return 0;
+}
+
+static inline void led_puts(const char *s)
+{
+}
+#endif
+
+#endif /* ARCH_BOARD_H */
+++ /dev/null
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_PLATDEVICE_H
-#define ARCH_PLATDEVICE_H
-
-#include <dm/platdata.h>
-#include <dm/platform_data/serial-uniphier.h>
-
-#define SERIAL_DEVICE(n, ba, clk) \
-static struct uniphier_serial_platform_data serial_device##n = { \
- .base = ba, \
- .uartclk = clk \
-}; \
-U_BOOT_DEVICE(serial##n) = { \
- .name = DRIVER_NAME, \
- .platdata = &serial_device##n \
-};
-
-#endif /* ARCH_PLATDEVICE_H */
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
-#if defined(CONFIG_MACH_PH1_SLD3)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
#define SC_BASE_ADDR 0xf1840000
#else
#define SC_BASE_ADDR 0x61840000
#endif
+#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
+#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
+#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
+
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
+/* Pro4 or older */
#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+/* Pro5 or newer */
+#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
+#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
+#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
+#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
+#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
+#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
+
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
+/* Pro4 or older */
#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
+/* Pro5 or newer */
+#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
+#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
+#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
+
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
+#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
+#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+/* PH1-LD6b, ProXstream2 only */
+#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
-#if defined(CONFIG_MACH_PH1_PRO4)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
-#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
- defined(CONFIG_MACH_PH1_SLD8)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
-#endif
-
-#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
-#define SG_PINSELBITS 4
-#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
-#define SG_PINSELBITS 8
-#endif
-
-#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
-#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
- ((n) * (SG_PINSELBITS) % 32)))
-#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
-
-/* Only for PH1-Pro4 */
+/* PH1-Pro4, PH1-Pro5 */
#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
/* Input Enable */
#ifdef __ASSEMBLY__
- .macro set_pinsel, n, value, ra, rd
- ldr \ra, =SG_PINSEL_ADDR(\n)
+ .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
+ ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
ldr \rd, [\ra]
- and \rd, \rd, #SG_PINSEL_MASK(\n)
- orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
+ and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
+ orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
str \rd, [\ra]
.endm
#include <linux/types.h>
#include <linux/io.h>
-static inline void sg_set_pinsel(int n, int value)
+static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
+ unsigned mux_bits, unsigned reg_stride)
{
- writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
- | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+ unsigned shift = pin * mux_bits % 32;
+ unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+ u32 mask = (1U << mux_bits) - 1;
+ u32 tmp;
+
+ tmp = readl(reg);
+ tmp &= ~(mask << shift);
+ tmp |= (mask & muxval) << shift;
+ writel(tmp, reg);
}
#endif /* __ASSEMBLY__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_SOC_INFO_H__
+#define __MACH_SOC_INFO_H__
+
+enum uniphier_soc_id {
+ SOC_UNIPHIER_PH1_SLD3,
+ SOC_UNIPHIER_PH1_LD4,
+ SOC_UNIPHIER_PH1_PRO4,
+ SOC_UNIPHIER_PH1_SLD8,
+ SOC_UNIPHIER_PH1_PRO5,
+ SOC_UNIPHIER_PROXSTREAM2,
+ SOC_UNIPHIER_PH1_LD6B,
+ SOC_UNIPHIER_UNKNOWN,
+};
+
+#define UNIPHIER_NR_ENABLED_SOCS \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+
+#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void);
+#else
+static inline enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ return SOC_UNIPHIER_PH1_SLD3;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ return SOC_UNIPHIER_PH1_LD4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ return SOC_UNIPHIER_PH1_PRO4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ return SOC_UNIPHIER_PH1_SLD8;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ return SOC_UNIPHIER_PH1_PRO5;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ return SOC_UNIPHIER_PROXSTREAM2;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ return SOC_UNIPHIER_PH1_LD6B;
+#endif
+
+ return SOC_UNIPHIER_UNKNOWN;
+}
+#endif
+
+#endif /* __MACH_SOC_INFO_H__ */
--- /dev/null
+obj-y += init.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += init-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += init-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += init-proxstream2.o
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_ld4_init(const struct uniphier_board_data *bd)
+{
+ ph1_ld4_bcu_init(bd);
+
+ ph1_ld4_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_ld4_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = ph1_ld4_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ ph1_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_pro4_init(const struct uniphier_board_data *bd)
+{
+ ph1_pro4_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_pro4_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = ph1_pro4_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ ph1_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_pro5_init(const struct uniphier_board_data *bd)
+{
+ ph1_pro4_sbc_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_pro5_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ led_puts("L5");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_sld3_init(const struct uniphier_board_data *bd)
+{
+ ph1_sld3_bcu_init(bd);
+
+ ph1_sld3_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_sld3_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ ph1_sld3_memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ ph1_sld3_early_pin_init(bd);
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ led_puts("L5");
+
+ ph1_sld3_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_sld8_init(const struct uniphier_board_data *bd)
+{
+ ph1_ld4_bcu_init(bd);
+
+ ph1_ld4_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_sld8_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = ph1_sld8_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ ph1_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int proxstream2_init(const struct uniphier_board_data *bd)
+{
+ proxstream2_sbc_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ proxstream2_memconf_init(bd);
+
+ led_puts("L1");
+
+ proxstream2_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <mach/init.h>
+#include <mach/soc_info.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ const struct uniphier_board_data *param;
+
+ param = uniphier_get_board_param(gd->fdt_blob);
+ if (!param)
+ hang();
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ case SOC_UNIPHIER_PH1_LD4:
+ ph1_ld4_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ case SOC_UNIPHIER_PH1_PRO4:
+ ph1_pro4_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_sld8_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ proxstream2_init(param);
+ break;
+#endif
+ default:
+ break;
+ }
+}
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
ENTRY(init_page_table)
section = 0
.rept NR_SECTIONS
- .if section == TEXT_SECTION || section == STACK_SECTION
+ .if section == 0 || section == 1 || section == STACK_SECTION
attr = NORMAL
.else
attr = DEVICE
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
-#include <mach/led.h>
#include <mach/arm-mpcore.h>
#include <mach/sbc-regs.h>
#include <mach/ssc-regs.h>
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
- bl setup_lowlevel_debug
+ bl debug_ll_init
#endif
/*
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH0_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH0_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH0_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH0_SZ_512M;
- break;
- case SZ_1G:
- ret = SG_MEMCONF_CH0_SZ_1G;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH0_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH0_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH1_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH1_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH1_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH1_SZ_512M;
- break;
- case SZ_1G:
- ret = SG_MEMCONF_CH1_SZ_1G;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH1_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH1_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-void memconf_init(void)
-{
- u32 tmp;
-
- /* Set DDR size */
- tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
- tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
- tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
- writel(tmp, SG_MEMCONF);
-}
--- /dev/null
+obj-y += memconf.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += memconf-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += memconf-proxstream2.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+ switch (bd->dram_ch2_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch2_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch2_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 size\n");
+ return -EINVAL;
+ }
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int proxstream2_memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+ switch (bd->dram_ch2_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch2_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch2_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 size\n");
+ return -EINVAL;
+ }
+
+ if (size_per_word)
+ tmp &= ~SG_MEMCONF_CH2_DISABLE;
+ else
+ tmp |= SG_MEMCONF_CH2_DISABLE;
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp = 0;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
+
+ switch (bd->dram_ch0_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH0_NUM_1;
+ size_per_word = bd->dram_ch0_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH0_NUM_2;
+ size_per_word = bd->dram_ch0_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch0 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH0_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH0_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH0_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH0_SZ_512M;
+ break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH0_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch0 size\n");
+ return -EINVAL;
+ }
+
+ tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
+
+ switch (bd->dram_ch1_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH1_NUM_1;
+ size_per_word = bd->dram_ch1_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH1_NUM_2;
+ size_per_word = bd->dram_ch1_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch1 width\n");
+ return -EINVAL;
+ }
+
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH1_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH1_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH1_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH1_SZ_512M;
+ break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH1_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch1 size\n");
+ return -EINVAL;
+ }
+
+ if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
+ tmp |= SG_MEMCONF_SPARSEMEM;
+ else
+ tmp &= ~SG_MEMCONF_SPARSEMEM;
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <mach/micro-support-card.h>
+
+#define MICRO_SUPPORT_CARD_BASE 0x43f00000
+#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
+#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
+#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
+#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
+#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
+
+/*
+ * 0: reset deassert, 1: reset
+ *
+ * bit[0]: LAN, I2C, LED
+ * bit[1]: UART
+ */
+void support_card_reset_deassert(void)
+{
+ writel(0, MICRO_SUPPORT_CARD_RESET);
+}
+
+void support_card_reset(void)
+{
+ writel(3, MICRO_SUPPORT_CARD_RESET);
+}
+
+static int support_card_show_revision(void)
+{
+ u32 revision;
+
+ revision = readl(MICRO_SUPPORT_CARD_REVISION);
+ printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
+ return 0;
+}
+
+int check_support_card(void)
+{
+ printf("SC: Micro Support Card ");
+ return support_card_show_revision();
+}
+
+void support_card_init(void)
+{
+ /*
+ * After power on, we need to keep the LAN controller in reset state
+ * for a while. (200 usec)
+ * Fortunately, enough wait time is already inserted in pll_init()
+ * function. So we do not have to wait here.
+ */
+ support_card_reset_deassert();
+}
+
+#if defined(CONFIG_SMC911X)
+#include <netdev.h>
+
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, SMC911X_BASE);
+}
+#endif
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+#include <mtd/cfi_flash.h>
+#include <mach/sbc-regs.h>
+
+struct memory_bank {
+ phys_addr_t base;
+ unsigned long size;
+};
+
+static int mem_is_flash(const struct memory_bank *mem)
+{
+ const int loop = 128;
+ u32 *scratch_addr;
+ u32 saved_value;
+ int ret = 1;
+ int i;
+
+ /* just in case, use the tail of the memory bank */
+ scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
+ sizeof(u32) * loop, MAP_NOCACHE);
+
+ for (i = 0; i < loop; i++, scratch_addr++) {
+ saved_value = readl(scratch_addr);
+ writel(~saved_value, scratch_addr);
+ if (readl(scratch_addr) != saved_value) {
+ /* We assume no memory or SRAM here. */
+ writel(saved_value, scratch_addr);
+ ret = 0;
+ break;
+ }
+ }
+
+ unmap_physmem(scratch_addr, MAP_NOCACHE);
+
+ return ret;
+}
+
+/* {address, size} */
+static const struct memory_bank memory_banks[] = {
+ {0x42000000, 0x01f00000},
+};
+
+static const struct memory_bank
+*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
+
+phys_addr_t cfi_flash_bank_addr(int i)
+{
+ return flash_banks_list[i]->base;
+}
+
+unsigned long cfi_flash_bank_size(int i)
+{
+ return flash_banks_list[i]->size;
+}
+
+static void detect_num_flash_banks(void)
+{
+ const struct memory_bank *memory_bank, *end;
+
+ cfi_flash_num_flash_banks = 0;
+
+ memory_bank = memory_banks;
+ end = memory_bank + ARRAY_SIZE(memory_banks);
+
+ for (; memory_bank < end; memory_bank++) {
+ if (cfi_flash_num_flash_banks >=
+ CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+ break;
+
+ if (mem_is_flash(memory_bank)) {
+ flash_banks_list[cfi_flash_num_flash_banks] =
+ memory_bank;
+
+ debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
+ memory_bank->base, memory_bank->size);
+ cfi_flash_num_flash_banks++;
+ }
+ }
+
+ debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
+}
+#else /* CONFIG_SYS_NO_FLASH */
+void detect_num_flash_banks(void)
+{
+};
+#endif /* CONFIG_SYS_NO_FLASH */
+
+void support_card_late_init(void)
+{
+ detect_num_flash_banks();
+}
+
+static const u8 ledval_num[] = {
+ 0x7e, /* 0 */
+ 0x0c, /* 1 */
+ 0xb6, /* 2 */
+ 0x9e, /* 3 */
+ 0xcc, /* 4 */
+ 0xda, /* 5 */
+ 0xfa, /* 6 */
+ 0x4e, /* 7 */
+ 0xfe, /* 8 */
+ 0xde, /* 9 */
+};
+
+static const u8 ledval_alpha[] = {
+ 0xee, /* A */
+ 0xf8, /* B */
+ 0x72, /* C */
+ 0xbc, /* D */
+ 0xf2, /* E */
+ 0xe2, /* F */
+ 0x7a, /* G */
+ 0xe8, /* H */
+ 0x08, /* I */
+ 0x3c, /* J */
+ 0xea, /* K */
+ 0x70, /* L */
+ 0x6e, /* M */
+ 0xa8, /* N */
+ 0xb8, /* O */
+ 0xe6, /* P */
+ 0xce, /* Q */
+ 0xa0, /* R */
+ 0xc8, /* S */
+ 0x8c, /* T */
+ 0x7c, /* U */
+ 0x54, /* V */
+ 0xfc, /* W */
+ 0xec, /* X */
+ 0xdc, /* Y */
+ 0xa4, /* Z */
+};
+
+static u8 char2ledval(char c)
+{
+ if (isdigit(c))
+ return ledval_num[c - '0'];
+ else if (isalpha(c))
+ return ledval_alpha[toupper(c) - 'A'];
+
+ return 0;
+}
+
+void led_puts(const char *s)
+{
+ int i;
+ u32 val = 0;
+
+ if (!s)
+ return;
+
+ for (i = 0; i < 4; i++) {
+ val <<= 8;
+ val |= char2ledval(*s);
+ if (*s != '\0')
+ s++;
+ }
+
+ writel(~val, LED_BASE);
+}
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-endif
-
-obj-y += boot-mode.o
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/bcu-regs.h>
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-void bcu_init(void)
-{
- int shift;
-
- writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
- writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
-
- /* Specify DDR channel */
- shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
- writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-}
+++ /dev/null
-#include "../ph1-pro4/boot-mode.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8253c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a82dbc0, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000800, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
+++ /dev/null
-#include "../ph1-pro4/early_clkrst_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
- sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
-
- sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
- sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
-
- sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
- sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 36864000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 85, 1, r0, r1
- set_pinsel 88, 1, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
- u32 tmp;
-
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
- sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
- sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
- sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
- sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
- sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
- sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
- sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
- sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
- sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
- sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
- sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
- sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
- sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
- /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
-#endif
-
- tmp = readl(SG_IECTRL);
- tmp |= 0x41;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT (DPLLCTRL.bit[29:20])
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x000f0000;
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unknown frequency"
-#endif
-
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
- tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-}
+++ /dev/null
-#include "../ph1-pro4/pll_spectrum.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
- *
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0);
- writel(0x0400bc01, SBBASE1);
- writel(0x0800bf01, SBBASE3);
-
- /* enable access to sub memory when boot swap is on */
- if (boot_is_swapped())
- sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-
- sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 0x1;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- if (freq == 1333) {
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x000FF0FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- } else if (freq == 1600) {
- writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
- writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
- writel(0x5101387F, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x2F030D3F, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x43030D3F, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- }
-
- writel(0x00000006, dramcont + UMC_DRMMR1);
-
- if (freq == 1333)
- writel(0x00000290, dramcont + UMC_DRMMR2);
- else if (freq == 1600)
- writel(0x00000298, dramcont + UMC_DRMMR2);
-
- writel(0x00000800, dramcont + UMC_DRMMR3);
-
- if (freq == 1333) {
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- } else if (freq == 1600) {
- if (size == 1)
- writel(0x002B0617, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x003F0617, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- }
-
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-endif
-
-obj-y += boot-mode.o
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
-
-struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
- {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- { /* sentinel */ }
-};
-
-int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 spl_boot_device(void)
-{
- int boot_mode;
-
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-
-void clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
- SC_RSTCTRL_NRST_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
- tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
-#endif
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
- SC_CLKCTRL_CEN_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000000, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-
-void early_clkrst_init(void)
-{
- u32 tmp;
-
- /* deassert reset */
- tmp = readl(SC_RSTCTRL);
-
- tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
- if (spl_boot_device() != BOOT_DEVICE_NAND)
- tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
-
- /* privide clocks */
- tmp = readl(SC_CLKCTRL);
- tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
- sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
- sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
- sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
- sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
- sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
- sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 73728000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- ldr r0, =SC_CLKCTRL
- ldr r1, [r0]
- orr r1, r1, #SC_CLKCTRL_CEN_PERI
- str r1, [r0]
-
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 127, 0, r0, r1
- set_pinsel 128, 0, r0, r1
-
- ldr r0, =SG_LOADPINCTRL
- mov r1, #1
- str r1, [r0]
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
- sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
- sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
- sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
- sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
- sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
- sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
- sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
- sg_set_pinsel(48, 0); /* NFALE -> NFALE */
- sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
- sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
- sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
- sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
- sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
- /* sg_set_pinsel(131, 1); */ /* RXD2 -> NRYBY1 */
- /* sg_set_pinsel(132, 1); */ /* TXD2 -> XNFCE1 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
- sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
- u32 tmp;
-
- /*
- * Set Frequency
- * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
- * to FOUT ( DPLLCTRL.bit[29:20] )
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~(0x000f0000);
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unsupported frequency"
-#endif
-
- /*
- * Set Moduration rate
- * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
- */
-#if defined(DPLL_SSC_RATE_1PER)
- tmp &= ~0x00008000;
-#else
- tmp |= 0x00008000;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- tmp = readl(SC_DPLLCTRL2);
- tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- /* Set VPLL27A & VPLL27B */
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-#if defined(CONFIG_MACH_PH1_PRO4)
- /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
- return;
-#endif
-
- /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
- /* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* wait 1 usec */
- udelay(1);
-
- /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 1 usec in vpll_init() so 1 usec can be saved here.
- */
- udelay(499);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-
-void enable_dpll_ssc(void)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
- *
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0400bc01, SBBASE1); /* sub memory */
- writel(0x0800bf01, SBBASE3); /* peripherals */
-
- /* enable access to sub memory when boot swap is on */
- if (boot_is_swapped())
- sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-
- sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
- writel(0x00000001, SG_LOADPINCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 1 << 6;
- writel(tmp, SG_IECTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000001, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x07ffffff, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
-
- writel(0x03010100, ssif_base + UMC_HDMCHSEL);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DVCCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
- writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_HDMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_HDDRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_GIORST);
- writel(0x00000001, ssif_base + UMC_HD2RST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_DVCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_VPERST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
- writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
- writel(0x5101387f, dramcont + UMC_INITCTLA);
- writel(0x43030d3f, dramcont + UMC_INITCTLB);
- writel(0x00ff00ff, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000298, dramcont + UMC_DRMMR2);
- writel(0x00000000, dramcont + UMC_DRMMR3);
- writel(0x003f0617, dramcont + UMC_SPCCTLA);
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
- writel(0x04060802, dramcont + UMC_WDATACTL_D0);
- writel(0x04060802, dramcont + UMC_WDATACTL_D1);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x0000000f, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x00000000, dramcont + 0x0060);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00010000, dramcont + UMC_SPCSETD);
- writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
- void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000103, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_1, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_1, 1);
- ddrphy_training(phy0_1);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 0);
- ddrphy_training(phy1_0);
-
- writel(0x00000103, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_1, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_1, 1);
- ddrphy_training(phy1_1);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
- (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
- ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
- (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
-/* OK */
-#else
- #error Unsupported DDR configuration.
-#endif
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-endif
-
-obj-y += boot-mode.o
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/bcu-regs.h>
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-void bcu_init(void)
-{
- int shift;
-
- writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
- writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
- /*
- * 0xe0000000-0xefffffff: Ex-bus
- * 0xf0000000-0xfbffffff: ASM bus
- * 0xfc000000-0xffffffff: OCM bus
- */
- writel(0x24440000, BCSCR5);
-
- /* Specify DDR channel */
- shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
- writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
- shift -= 32;
- writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
-
-struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "External Master"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- { /* sentinel */ }
-};
-
-int get_boot_mode_sel(void)
-{
- return readl(SG_PINMON0) & 0x3f;
-}
-
-u32 spl_boot_device(void)
-{
- int boot_mode;
-
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
+++ /dev/null
-#include "../ph1-pro4/clkrst_init.c"
+++ /dev/null
-#include "../ph1-pro4/early_clkrst_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(63, 0); /* RXD0 */
- sg_set_pinsel(64, 1); /* TXD0 */
-
- sg_set_pinsel(65, 0); /* RXD1 */
- sg_set_pinsel(66, 1); /* TXD1 */
-
- sg_set_pinsel(96, 2); /* RXD2 */
- sg_set_pinsel(102, 2); /* TXD2 */
-#endif
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/bcu-regs.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 36864000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- ldr r0, =BCSCR5
- ldr r1, =0x24440000
- str r1, [r0]
-
- ldr r0, =SC_CLKCTRL
- ldr r1, [r0]
- orr r1, r1, #SC_CLKCTRL_CEN_PERI
- str r1, [r0]
-
- init_debug_uart r0, r1, r2
-
- set_pinsel 63, 0, r0, r1
- set_pinsel 64, 1, r0, r1
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <linux/sizes.h>
-#include <mach/sg-regs.h>
-
-static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH2_SZ_512M;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH2_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH2_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-u32 memconf_additional_val(void)
-{
- return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(13, 0); /* USB0OC */
- sg_set_pinsel(14, 1); /* USB0VBUS */
-
- sg_set_pinsel(15, 0); /* USB1OC */
- sg_set_pinsel(16, 1); /* USB1VBUS */
-
- sg_set_pinsel(17, 0); /* USB2OC */
- sg_set_pinsel(18, 1); /* USB2VBUS */
-
- sg_set_pinsel(19, 0); /* USB3OC */
- sg_set_pinsel(20, 1); /* USB3VBUS */
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void pll_init(void)
-{
- /* add pll init code here */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-
-void enable_dpll_ssc(void)
-{
- u32 tmp;
-
- tmp = readl(SC_DPLLCTRL);
- tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- /* only address/data multiplex mode is supported */
-
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
- *
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-
- sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- /* only address/data multiplex mode is supported */
-
- /* XECS0 : boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
-
- /* XECS1 : sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-
- /* XECS2 : peripherals */
- writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
- writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
- writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0);
- writel(0x0400bc01, SBBASE1);
- writel(0x0800bf01, SBBASE2);
-
- sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void sg_init(void)
-{
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-int umc_init(void)
-{
- /* add UMC init code here */
- printf("Implement memory init code\n");
-
- return 0;
-}
+++ /dev/null
-include $(src)/../ph1-ld4/Makefile
+++ /dev/null
-#include "../ph1-ld4/bcu_init.c"
+++ /dev/null
-#include "../ph1-pro4/boot-mode.c"
+++ /dev/null
-#include "../ph1-ld4/clkrst_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, &phy->mr3);
-#else
- writel(0x00000800, &phy->mr3);
-#endif
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-}
+++ /dev/null
-#include "../ph1-ld4/early_clkrst_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
- sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
-
- sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
-
- sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
- sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-}
+++ /dev/null
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 80000000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 70, 3, r0, r1
- set_pinsel 71, 3, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_SYS_I2C_UNIPHIER
- {
- u32 tmp;
- tmp = readl(SG_IECTRL);
- tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
- writel(tmp, SG_IECTRL);
- }
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
- sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
- sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
- sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
- sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
- sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
- sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
- sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
- sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
- sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
- sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
- sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
- sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
- sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(114, 1); */ /* TXD1 -> USB2VBUS (shared with UART) */
- /* sg_set_pinsel(115, 1); */ /* RXD1 -> USB2OD */
-#endif
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-static void dpll_init(void)
-{
- u32 tmp;
- /*
- * Set DPLL SSC parameters for DPLLCTRL3
- * [23] DIVN_TEST 0x1
- * [22:16] DIVN 0x50
- * [10] FREFSEL_TEST 0x1
- * [9:8] FREFSEL 0x2
- * [4] ICPD_TEST 0x1
- * [3:0] ICPD 0xb
- */
- tmp = readl(SC_DPLLCTRL3);
- tmp &= ~0x00ff0717;
- tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL
- * <-1%> <-2%>
- * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
- * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
- */
- tmp = readl(SC_DPLLCTRL);
- tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
- tmp |= 0x084018bf;
-#else
- tmp |= 0x084031a6;
-#endif
- writel(tmp, SC_DPLLCTRL);
-
- /*
- * Set DPLL SSC parameters for DPLLCTRL2
- * [31:29] SSC_STEP 0
- * [27] SSC_REG_REF 1
- * [26:20] SSC_M 79 (0x4f)
- * [19:0] SSC_K 964689 (0xeb851)
- */
- tmp = readl(SC_DPLLCTRL2);
- tmp &= ~0xefffffff;
- tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
- u32 tmp, clk_mode_upll, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
- tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
-
- if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x0228f5c0;
- } else {
- /* AXO: default 24.576MHz */
- tmp &= ~0x07ffffff;
- tmp |= 0x02328000;
- }
- }
-
- writel(tmp, SC_UPLLCTRL);
-
- /* set 1 to K_LD(UPLLCTRL.bit[27]) */
- tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
-
- /* wait 10 usec */
- udelay(10);
-
- /* set 1 to SNRT(UPLLCTRL.bit[28]) */
- tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
- u32 tmp, clk_mode_axosel;
-
- tmp = readl(SG_PINMON0);
- clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
- /* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-
- /* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp &= ~0x0000007f;
- tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
-
- if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
- clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
- /* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
- } else {
- /* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp &= ~0x000fffff;
- tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
- }
-
- /* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
-
- /* wait 10 usec */
- udelay(10);
-
- /* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
- tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
-
- /* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
- tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
- tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
- dpll_init();
- upll_init();
- vpll_init();
-
- /*
- * Wait 500 usec until dpll get stable
- * We wait 10 usec in upll_init() and vpll_init()
- * so 20 usec can be saved here.
- */
- udelay(480);
-}
+++ /dev/null
-#include "../ph1-ld4/pll_spectrum.c"
+++ /dev/null
-#include "../ph1-ld4/sbc_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /*
- * SBCTRL0* does not need settings because PH1-sLD8 has no support for
- * XECS0. The boot swap must be enabled to boot from the support card.
- */
-
- if (boot_is_swapped()) {
- /* XECS1 : boot memory if boot swap is on */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
- }
-
- /* XECS4 : sub memory */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
- /* XECS5 : peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0900bfff, SBBASE1); /* dummy */
- writel(0x0400bc01, SBBASE4); /* sub memory */
- writel(0x0800bf01, SBBASE5); /* peripherals */
-
- sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
- sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
- /* dummy read to assure write process */
- readl(SG_PINCTRL(0));
-}
+++ /dev/null
-#include "../ph1-ld4/sg_init.c"
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
-#ifdef CONFIG_DDR_STANDARD
- writel(0x55990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
-
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000290, dramcont + UMC_DRMMR2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, dramcont + UMC_DRMMR3);
-#else
- writel(0x00000800, dramcont + UMC_DRMMR3);
-#endif
-
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000004f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000077, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int umc_init(void)
-{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_ld4_pin_init(void)
+{
+ u32 tmp;
+
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
+ sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
+ sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
+ sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
+ sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
+ sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
+ sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
+ sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
+ sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
+ sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
+ sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
+ sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
+ sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
+ sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
+ sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */
+ /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
+ /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
+#endif
+
+ tmp = readl(SG_IECTRL);
+ tmp |= 0x41;
+ writel(tmp, SG_IECTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_ld6b_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */
+ sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */
+ sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */
+ sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */
+ sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */
+ sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */
+ sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */
+ sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */
+ sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */
+ sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */
+ sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */
+ sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */
+ sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */
+ sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */
+ sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */
+ sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */
+ sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_pro4_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */
+ sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */
+ sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */
+ sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */
+ sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */
+ sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */
+ sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */
+ sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */
+ sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */
+ sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */
+ sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */
+ sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */
+ sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */
+ sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
+ /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */
+ /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */
+ sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */
+ sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_pro5_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */
+ sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */
+ sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */
+ sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */
+ sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */
+ sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */
+ sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */
+ sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */
+ sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */
+ sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */
+ sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */
+ sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */
+ sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */
+ sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */
+ sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */
+ sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_sld3_pin_init(void)
+{
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
+ sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
+
+ sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
+ sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
+
+ sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
+ sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
+
+ sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
+ sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_sld8_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
+ sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
+ sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
+ sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
+ sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
+ sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
+ sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
+ sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
+ sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
+ sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
+ sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
+ sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
+ sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
+ sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
+ sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */
+ /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
+ /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */
+#endif
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void proxstream2_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */
+ sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */
+ sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */
+ sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */
+ sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */
+ sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */
+ sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */
+ sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */
+ sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */
+ sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */
+ sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */
+ sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */
+ sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */
+ sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */
+ sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */
+ sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */
+ sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */
+#endif
+}
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \
+ pll-spectrum-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \
+ pll-spectrum-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pll-init-ph1-pro4.o \
+ pll-spectrum-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pll-init-ph1-sld8.o \
+ pll-spectrum-ph1-ld4.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+static int dpll_init(unsigned int dram_freq)
+{
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT (DPLLCTRL.bit[29:20])
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x000f0000;
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
+
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~SC_DPLLCTRL_SSC_RATE;
+#else
+ tmp |= SC_DPLLCTRL_SSC_RATE;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+
+ return 0;
+}
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd)
+{
+ int ret;
+
+ ret = dpll_init(bd->dram_freq);
+ if (ret)
+ return ret;
+ upll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 10 usec in upll_init() and vpll_init()
+ * so 20 usec can be saved here.
+ */
+ udelay(480);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#undef DPLL_SSC_RATE_1PER
+
+static int dpll_init(unsigned int dram_freq)
+{
+ u32 tmp;
+
+ /*
+ * Set Frequency
+ * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
+ * to FOUT ( DPLLCTRL.bit[29:20] )
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~(0x000f0000);
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
+
+ /*
+ * Set Moduration rate
+ * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
+ */
+#if defined(DPLL_SSC_RATE_1PER)
+ tmp &= ~0x00008000;
+#else
+ tmp |= 0x00008000;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ tmp = readl(SC_DPLLCTRL2);
+ tmp |= SC_DPLLCTRL2_NRSTDS;
+ writel(tmp, SC_DPLLCTRL2);
+
+ return 0;
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ /* Set VPLL27A & VPLL27B */
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+ return;
+
+ /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Unset VPLA_K_LD and VPLB_K_LD bit */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set VPLA_M and VPLB_M to 0x20 */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+ /* Set VPLA_K and VPLB_K for AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066666;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* wait 1 usec */
+ udelay(1);
+
+ /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Unset VPLA_SNRST and VPLB_SNRST bit */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
+{
+ int ret;
+
+ ret = dpll_init(bd->dram_freq);
+ if (ret)
+ return ret;
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 1 usec in vpll_init() so 1 usec can be saved here.
+ */
+ udelay(499);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/init.h>
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
+{
+ /* add pll init code here */
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+static void dpll_init(void)
+{
+ u32 tmp;
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL3
+ * [23] DIVN_TEST 0x1
+ * [22:16] DIVN 0x50
+ * [10] FREFSEL_TEST 0x1
+ * [9:8] FREFSEL 0x2
+ * [4] ICPD_TEST 0x1
+ * [3:0] ICPD 0xb
+ */
+ tmp = readl(SC_DPLLCTRL3);
+ tmp &= ~0x00ff0717;
+ tmp |= 0x00d0061b;
+ writel(tmp, SC_DPLLCTRL3);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL
+ * <-1%> <-2%>
+ * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
+ * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
+ */
+ tmp = readl(SC_DPLLCTRL);
+ tmp &= ~0x3ff07fff;
+#ifdef CONFIG_DPLL_SSC_RATE_1PER
+ tmp |= 0x084018bf;
+#else
+ tmp |= 0x084031a6;
+#endif
+ writel(tmp, SC_DPLLCTRL);
+
+ /*
+ * Set DPLL SSC parameters for DPLLCTRL2
+ * [31:29] SSC_STEP 0
+ * [27] SSC_REG_REF 1
+ * [26:20] SSC_M 79 (0x4f)
+ * [19:0] SSC_K 964689 (0xeb851)
+ */
+ tmp = readl(SC_DPLLCTRL2);
+ tmp &= ~0xefffffff;
+ tmp |= 0x0cfeb851;
+ writel(tmp, SC_DPLLCTRL2);
+}
+
+static void upll_init(void)
+{
+ u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+ tmp = readl(SC_UPLLCTRL);
+ tmp &= ~0x18000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x0228f5c0;
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp &= ~0x07ffffff;
+ tmp |= 0x02328000;
+ }
+ }
+
+ writel(tmp, SC_UPLLCTRL);
+
+ /* set 1 to K_LD(UPLLCTRL.bit[27]) */
+ tmp |= 0x08000000;
+ writel(tmp, SC_UPLLCTRL);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* set 1 to SNRT(UPLLCTRL.bit[28]) */
+ tmp |= 0x10000000;
+ writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+ u32 tmp, clk_mode_axosel;
+
+ tmp = readl(SG_PINMON0);
+ clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+ /* set 1 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= 0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+
+ /* Set 0 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp &= ~0x0000007f;
+ tmp |= 0x00000020;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+ clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+ /* AXO: 25MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x00066664;
+ writel(tmp, SC_VPLL27BCTRL3);
+ } else {
+ /* AXO: default 24.576MHz */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp &= ~0x000fffff;
+ tmp |= 0x000f5800;
+ writel(tmp, SC_VPLL27BCTRL3);
+ }
+
+ /* Set 1 to VPLA_K_LD and VPLB_K_LD */
+ tmp = readl(SC_VPLL27ACTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL3);
+ tmp = readl(SC_VPLL27BCTRL3);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL3);
+
+ /* wait 10 usec */
+ udelay(10);
+
+ /* Set 0 to VPLA_SNRST and VPLB_SNRST */
+ tmp = readl(SC_VPLL27ACTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27ACTRL2);
+ tmp = readl(SC_VPLL27BCTRL2);
+ tmp |= 0x10000000;
+ writel(tmp, SC_VPLL27BCTRL2);
+
+ /* set 0 to VPLA27WP and VPLA27WP */
+ tmp = readl(SC_VPLL27ACTRL);
+ tmp &= ~0x00000001;
+ writel(tmp, SC_VPLL27ACTRL);
+ tmp = readl(SC_VPLL27BCTRL);
+ tmp |= ~0x00000001;
+ writel(tmp, SC_VPLL27BCTRL);
+}
+
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
+{
+ dpll_init();
+ upll_init();
+ vpll_init();
+
+ /*
+ * Wait 500 usec until dpll get stable
+ * We wait 10 usec in upll_init() and vpll_init()
+ * so 20 usec can be saved here.
+ */
+ udelay(480);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ tmp = readl(SC_DPLLCTRL);
+ tmp |= SC_DPLLCTRL_SSC_EN;
+ writel(tmp, SC_DPLLCTRL);
+
+ return 0;
+}
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/board.h>
+#include <mach/micro-support-card.h>
int misc_init_f(void)
{
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += sbc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += sbc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += sbc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += sbc-proxstream2.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+{
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+ /* only address/data multiplex mode is supported */
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+ /* necessary for ROM boot ?? */
+ /* system bus output enable */
+ writel(0x17, PC0CTRL);
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <linux/types.h>
+#include <mach/sg-regs.h>
+#include <mach/soc_info.h>
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+ u32 revision = readl(SG_REVISION);
+ enum uniphier_soc_id ret;
+
+ switch ((revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT) {
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
+ case 0x25:
+ ret = SOC_UNIPHIER_PH1_SLD3;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD4
+ case 0x26:
+ ret = SOC_UNIPHIER_PH1_LD4;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO4
+ case 0x28:
+ ret = SOC_UNIPHIER_PH1_PRO4;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD8
+ case 0x29:
+ ret = SOC_UNIPHIER_PH1_SLD8;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO5
+ case 0x2A:
+ ret = SOC_UNIPHIER_PH1_PRO5;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PROXSTREAM2
+ case 0x2E:
+ ret = SOC_UNIPHIER_PROXSTREAM2;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD6B
+ case 0x2F:
+ ret = SOC_UNIPHIER_PH1_LD6B;
+ break;
+#endif
+ default:
+ ret = SOC_UNIPHIER_UNKNOWN;
+ break;
+ }
+
+ return ret;
+}
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/led.h>
-#include <mach/board.h>
-
-void __weak bcu_init(void)
-{
-};
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void memconf_init(void);
-void early_clkrst_init(void);
-void early_pin_init(void);
-int umc_init(void);
-void enable_dpll_ssc(void);
-
-void spl_board_init(void)
-{
- bcu_init();
-
- sbc_init();
-
- sg_init();
-
- uniphier_board_reset();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(L, 0, , );
-
- memconf_init();
-
- led_write(L, 1, , );
-
- early_clkrst_init();
-
- led_write(L, 2, , );
-
- early_pin_init();
-
- led_write(L, 3, , );
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_write(L, 4, , );
-
- {
- int res;
-
- res = umc_init();
- if (res < 0) {
- while (1)
- ;
- }
- }
- led_write(L, 5, , );
-
- enable_dpll_ssc();
-
- led_write(L, 6, , );
-}
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/board.h>
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-
-#define PFC_MICRO_SUPPORT_CARD_RESET \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
-#define PFC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
-/*
- * 0: reset deassert, 1: reset
- *
- * bit[0]: LAN, I2C, LED
- * bit[1]: UART
- */
-void support_card_reset_deassert(void)
-{
- writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-void support_card_reset(void)
-{
- writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
- printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-
-#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
-#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
-#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
-#define DCC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
-
-void support_card_reset_deassert(void)
-{
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-void support_card_reset(void)
-{
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
-
- if (revision >= 0x67) {
- printf("(DCC CPLD version 3.%d.%d)\n",
- revision >> 4, revision & 0xf);
- return 0;
- } else {
- printf("(DCC CPLD unknown version)\n");
- return -1;
- }
-}
-#endif
-
-int check_support_card(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
-void support_card_init(void)
-{
- /*
- * After power on, we need to keep the LAN controller in reset state
- * for a while. (200 usec)
- * Fortunately, enough wait time is already inserted in pll_init()
- * function. So we do not have to wait here.
- */
- support_card_reset_deassert();
-}
-
-#if defined(CONFIG_SMC911X)
-#include <netdev.h>
-
-int board_eth_init(bd_t *bis)
-{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-#include <mtd/cfi_flash.h>
-#include <mach/sbc-regs.h>
-
-struct memory_bank {
- phys_addr_t base;
- unsigned long size;
-};
-
-static int mem_is_flash(const struct memory_bank *mem)
-{
- const int loop = 128;
- u32 *scratch_addr;
- u32 saved_value;
- int ret = 1;
- int i;
-
- /* just in case, use the tail of the memory bank */
- scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
- sizeof(u32) * loop, MAP_NOCACHE);
-
- for (i = 0; i < loop; i++, scratch_addr++) {
- saved_value = readl(scratch_addr);
- writel(~saved_value, scratch_addr);
- if (readl(scratch_addr) != saved_value) {
- /* We assume no memory or SRAM here. */
- writel(saved_value, scratch_addr);
- ret = 0;
- break;
- }
- }
-
- unmap_physmem(scratch_addr, MAP_NOCACHE);
-
- return ret;
-}
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
- /* {address, size} */
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x02000000, 0x01f00000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x01f00000},
-};
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x04000000, 0x02000000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x02000000},
- {0x04000000, 0x02000000},
-};
-#endif
-
-static const struct memory_bank
-*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
-
-phys_addr_t cfi_flash_bank_addr(int i)
-{
- return flash_banks_list[i]->base;
-}
-
-unsigned long cfi_flash_bank_size(int i)
-{
- return flash_banks_list[i]->size;
-}
-
-static void detect_num_flash_banks(void)
-{
- const struct memory_bank *memory_bank, *end;
-
- cfi_flash_num_flash_banks = 0;
-
- if (boot_is_swapped()) {
- memory_bank = memory_banks_boot_swap_on;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
- } else {
- memory_bank = memory_banks_boot_swap_off;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
- }
-
- for (; memory_bank < end; memory_bank++) {
- if (cfi_flash_num_flash_banks >=
- CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
- break;
-
- if (mem_is_flash(memory_bank)) {
- flash_banks_list[cfi_flash_num_flash_banks] =
- memory_bank;
-
- debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
- memory_bank->base, memory_bank->size);
- cfi_flash_num_flash_banks++;
- }
- }
-
- debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
-}
-#else /* CONFIG_SYS_NO_FLASH */
-void detect_num_flash_banks(void)
-{
-};
-#endif /* CONFIG_SYS_NO_FLASH */
-
-void support_card_late_init(void)
-{
- detect_num_flash_banks();
-}
--- /dev/null
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+ if (freq == 1333) {
+ writel(0x45990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958924, dramcont + UMC_CMDCTLB);
+ writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x27028B0A, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+ writel(0x000FF0FF, dramcont + UMC_INITCTLC);
+ writel(0x00000b51, dramcont + UMC_DRMMR0);
+ } else if (freq == 1600) {
+ writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
+ writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
+ writel(0x5101387F, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x2F030D3F, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x43030D3F, dramcont + UMC_INITCTLB);
+
+ writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+ writel(0x00000d71, dramcont + UMC_DRMMR0);
+ }
+
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+
+ if (freq == 1333)
+ writel(0x00000290, dramcont + UMC_DRMMR2);
+ else if (freq == 1600)
+ writel(0x00000298, dramcont + UMC_DRMMR2);
+
+ writel(0x00000800, dramcont + UMC_DRMMR3);
+
+ if (freq == 1333) {
+ if (size == 1)
+ writel(0x00240512, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+ writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+ } else if (freq == 1600) {
+ if (size == 1)
+ writel(0x002B0617, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x003F0617, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+ }
+
+ writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x00000003, dramcont + 0x7000);
+ writel(0x0000000f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000071, dramcont + 0x8008);
+ writel(0x0000003b, dramcont + UMC_DICGCTLA);
+ writel(0x020a0808, dramcont + UMC_DICGCTLB);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00000000, dramcont + UMC_SPCSETD);
+ writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
+{
+ if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
+ (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+ (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
+ bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000001, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x07ffffff, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+
+ writel(0x03010100, ssif_base + UMC_HDMCHSEL);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DVCCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+ writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_HDMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_HDDRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_GIORST);
+ writel(0x00000001, ssif_base + UMC_HD2RST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_DVCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_VPERST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+ writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
+ writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
+ writel(0x5101387f, dramcont + UMC_INITCTLA);
+ writel(0x43030d3f, dramcont + UMC_INITCTLB);
+ writel(0x00ff00ff, dramcont + UMC_INITCTLC);
+ writel(0x00000d71, dramcont + UMC_DRMMR0);
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+ writel(0x00000298, dramcont + UMC_DRMMR2);
+ writel(0x00000000, dramcont + UMC_DRMMR3);
+ writel(0x003f0617, dramcont + UMC_SPCCTLA);
+ writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
+ writel(0x04060802, dramcont + UMC_WDATACTL_D0);
+ writel(0x04060802, dramcont + UMC_WDATACTL_D1);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x0000000f, dramcont + 0x7000);
+ writel(0x0000000f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000071, dramcont + 0x8008);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x00000000, dramcont + 0x0060);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00010000, dramcont + UMC_SPCSETD);
+ writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+ void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000103, dramcont0 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_1, 1);
+ ddrphy_training(phy0_1);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 0);
+ ddrphy_training(phy1_0);
+
+ writel(0x00000103, dramcont1 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_1, 1);
+ ddrphy_training(phy1_1);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
+{
+ if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
+ (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
+ ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
+ (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
+ bd->dram_freq == 1600) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/umc-regs.h>
+#include <mach/ddrphy-regs.h>
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x55990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958944, dramcont + UMC_CMDCTLB);
+#else
+ writel(0x45990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958924, dramcont + UMC_CMDCTLB);
+#endif
+
+ writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x27028B0A, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+ writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+ writel(0x00000b51, dramcont + UMC_DRMMR0);
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+ writel(0x00000290, dramcont + UMC_DRMMR2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, dramcont + UMC_DRMMR3);
+#else
+ writel(0x00000800, dramcont + UMC_DRMMR3);
+#endif
+
+ if (size == 1)
+ writel(0x00240512, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+ writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+ writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x00000003, dramcont + 0x7000);
+ writel(0x0000004f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000077, dramcont + 0x8008);
+ writel(0x0000003b, dramcont + UMC_DICGCTLA);
+ writel(0x020a0808, dramcont + UMC_DICGCTLB);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00000000, dramcont + UMC_SPCSETD);
+ writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
+{
+ if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
+ (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+ bd->dram_freq == 1333 &&
+ bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
+}
+++ /dev/null
-if ARCH_VERSATILE
-
-config SYS_BOARD
- default "versatile"
-
-config SYS_VENDOR
- default "armltd"
-
-config SYS_SOC
- default "versatile"
-
-config SYS_CONFIG_NAME
- default "versatile"
-
-endif
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-#define BIT(x) (1<<x)
-
#endif /* _ZYNQ_GPIO_H */
prompt "Target select"
optional
+config TARGET_LWMON5
+ bool "Support lwmon5"
+
config TARGET_T3CORP
bool "Support t3corp"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
+source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long wdt_last; /* trace watch-dog triggering rate */
+#endif
+#if defined(CONFIG_LWMON5)
+ unsigned long kbd_status;
+#endif
};
#include <asm-generic/global_data.h>
};
};
+ reset@1 {
+ compatible = "sandbox,reset";
+ };
+
spi@0 {
#address-cells = <1>;
#size-cells = <0>;
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = mrc_params.mem_size;
post_code(POST_DRAM);
+ /* variable range MTRR#2: RAM area */
+ disable_caches();
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
+ 0 | MTRR_TYPE_WRBACK);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
+ (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
+ enable_caches();
+
return 0;
}
#include <common.h>
#include <mmc.h>
-#include <netdev.h>
-#include <phy.h>
#include <asm/io.h>
#include <asm/irq.h>
+#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
}
+static void quark_setup_mtrr(void)
+{
+ u32 base, mask;
+ int i;
+
+ disable_caches();
+
+ /* mark the VGA RAM area as uncacheable */
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+ /* mark other fixed range areas as cacheable */
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
+ msg_port_write(MSG_PORT_HOST_BRIDGE, i,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+ /* variable range MTRR#0: ROM area */
+ mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
+ base = CONFIG_SYS_TEXT_BASE & mask;
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
+ base | MTRR_TYPE_WRBACK);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
+ mask | MTRR_PHYS_MASK_VALID);
+
+ /* variable range MTRR#1: eSRAM area */
+ mask = ~(ESRAM_SIZE - 1);
+ base = CONFIG_ESRAM_BASE & mask;
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
+ base | MTRR_TYPE_WRBACK);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
+ mask | MTRR_PHYS_MASK_VALID);
+
+ /* enable both variable and fixed range MTRRs */
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
+ MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
+
+ enable_caches();
+}
+
static void quark_setup_bars(void)
{
/* GPIO - D31:F0:R44h */
static void quark_pcie_early_init(void)
{
- u32 pcie_cfg;
-
/*
* Step1: Assert PCIe signal PERST#
*
board_assert_perst();
/* Step2: PHY common lane reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= PCIE_PHY_LANE_RST;
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
/* wait 1 ms for PHY common lane reset */
mdelay(1);
/* Step3: PHY sideband interface reset and controller main reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= (PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
+ PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
/* wait 80ms for PLL to lock */
mdelay(80);
/* Step4: Controller sideband interface reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= PCIE_CTLR_SB_RST;
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
/* wait 20ms for controller sideband interface reset */
mdelay(20);
board_deassert_perst();
/* Step6: Controller primary interface reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= PCIE_CTLR_PRI_RST;
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
/* Mixer Load Lane 0 */
- pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0);
- pcie_cfg &= ~((1 << 6) | (1 << 7));
- msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, pcie_cfg);
+ msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
+ (1 << 6) | (1 << 7));
/* Mixer Load Lane 1 */
- pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1);
- pcie_cfg &= ~((1 << 6) | (1 << 7));
- msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, pcie_cfg);
+ msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
+ (1 << 6) | (1 << 7));
}
static void quark_usb_early_init(void)
{
- u32 usb;
-
/* The sequence below comes from Quark firmware writer guide */
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT);
- usb &= ~(1 << 1);
- usb |= ((1 << 6) | (1 << 7));
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, usb);
+ msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
+ 1 << 1, (1 << 6) | (1 << 7));
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_COMPBG);
- usb &= ~((1 << 8) | (1 << 9));
- usb |= ((1 << 7) | (1 << 10));
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_COMPBG, usb);
+ msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
+ (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
- usb |= (1 << 29);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
+ msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
- usb |= (1 << 1);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
+ msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
- usb &= ~((1 << 3) | (1 << 4) | (1 << 5));
- usb |= (1 << 6);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
+ msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
+ (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
- usb &= ~(1 << 29);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
+ msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
- usb |= (1 << 24);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
+ msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
}
-static void quark_enable_legacy_seg(void)
+static void quark_thermal_early_init(void)
{
- u32 hmisc2;
+ /* The sequence below comes from Quark firmware writer guide */
+
+ /* thermal sensor mode config */
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
+ (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
+ (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
+ (1 << 12), 1 << 9);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
+ (1 << 8) | (1 << 9), 1 << 8);
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
+ 0x7ff800, 0xc8 << 11);
+
+ /* thermal monitor catastrophic trip set point (105 celsius) */
+ msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
+
+ /* thermal monitor catastrophic trip clear point (0 celsius) */
+ msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
+
+ /* take thermal sensor out of reset */
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
+
+ /* enable thermal monitor */
+ msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
+
+ /* lock all thermal configuration */
+ msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
+}
- hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
- hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
- msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
+static void quark_enable_legacy_seg(void)
+{
+ msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
+ HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
}
int arch_cpu_init(void)
if (ret)
return ret;
+ /*
+ * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
+ * are accessed indirectly via the message port and not the traditional
+ * MSR mechanism. Only UC, WT and WB cache types are supported.
+ */
+ quark_setup_mtrr();
+
/*
* Quark SoC has some non-standard BARs (excluding PCI standard BARs)
* which need be initialized with suggested values
/* Initialize USB2 PHY */
quark_usb_early_init();
+ /* Initialize thermal sensor */
+ quark_thermal_early_init();
+
/* Turn on legacy segments (A/B/E/F) decode to system RAM */
quark_enable_legacy_seg();
x86_full_reset();
}
-int cpu_mmc_init(bd_t *bis)
+static void quark_pcie_init(void)
{
- return pci_mmc_init("Quark SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ u32 val;
+
+ /* PCIe upstream non-posted & posted request size */
+ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
+ CCFG_UPRS | CCFG_UNRS);
+ qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
+ CCFG_UPRS | CCFG_UNRS);
+
+ /* PCIe packet fast transmit mode (IPF) */
+ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
+ qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
+
+ /* PCIe message bus idle counter (SBIC) */
+ qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
+ val |= MBC_SBIC;
+ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
+ qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
+ val |= MBC_SBIC;
+ qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
}
-int cpu_eth_init(bd_t *bis)
+static void quark_usb_init(void)
{
- u32 base;
- int ret0, ret1;
+ u32 bar;
- qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
- ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+ /* Change USB EHCI packet buffer OUT/IN threshold */
+ qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
+ writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
- qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
- ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+ /* Disable USB device interrupts */
+ qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
+ writel(0x7f, bar + USBD_INT_MASK);
+ writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
+ writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
+}
- if (ret0 < 0 && ret1 < 0)
- return -1;
- else
- return 0;
+int arch_early_init_r(void)
+{
+ quark_pcie_init();
+
+ quark_usb_init();
+
+ return 0;
+}
+
+int cpu_mmc_init(bd_t *bis)
+{
+ return pci_mmc_init("Quark SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
}
void cpu_irq_init(void)
{
return pirq_init();
}
+
+void board_final_cleanup(void)
+{
+ struct quark_rcba *rcba;
+ u32 base, val;
+
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct quark_rcba *)base;
+
+ /* Initialize 'Component ID' to zero */
+ val = readl(&rcba->esd);
+ val &= ~0xff0000;
+ writel(val, &rcba->esd);
+
+ /* Lock HMBOUND for security */
+ msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
+
+ return;
+}
PCI_BDF(0, 21, 0) INTA PIRQE
PCI_BDF(0, 21, 1) INTB PIRQF
PCI_BDF(0, 21, 2) INTC PIRQG
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 1) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
>;
};
};
*/
void msg_port_io_write(u8 port, u32 reg, u32 value);
+/* clrbits, setbits, clrsetbits macros for message port access */
+
+#define msg_port_normal_read msg_port_read
+#define msg_port_normal_write msg_port_write
+
+#define msg_port_generic_clrsetbits(type, port, reg, clr, set) \
+ msg_port_##type##_write(port, reg, \
+ (msg_port_##type##_read(port, reg) \
+ & ~(clr)) | (set))
+
+#define msg_port_clrbits(port, reg, clr) \
+ msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
+#define msg_port_setbits(port, reg, set) \
+ msg_port_generic_clrsetbits(normal, port, reg, 0, set)
+#define msg_port_clrsetbits(port, reg, clr, set) \
+ msg_port_generic_clrsetbits(normal, port, reg, clr, set)
+
+#define msg_port_alt_clrbits(port, reg, clr) \
+ msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
+#define msg_port_alt_setbits(port, reg, set) \
+ msg_port_generic_clrsetbits(alt, port, reg, 0, set)
+#define msg_port_alt_clrsetbits(port, reg, clr, set) \
+ msg_port_generic_clrsetbits(alt, port, reg, clr, set)
+
+#define msg_port_io_clrbits(port, reg, clr) \
+ msg_port_generic_clrsetbits(io, port, reg, clr, 0)
+#define msg_port_io_setbits(port, reg, set) \
+ msg_port_generic_clrsetbits(io, port, reg, 0, set)
+#define msg_port_io_clrsetbits(port, reg, clr, set) \
+ msg_port_generic_clrsetbits(io, port, reg, clr, set)
+
#endif /* __ASSEMBLY__ */
#endif /* _QUARK_MSG_PORT_H_ */
/* Host Memory I/O Boundary */
#define HM_BOUND 0x08
+#define HM_BOUND_LOCK 0x00000001
/* Extended Configuration Space */
#define HEC_REG 0x09
+/* MTRR Registers */
+#define MTRR_CAP 0x40
+#define MTRR_DEF_TYPE 0x41
+
+#define MTRR_FIX_64K_00000 0x42
+#define MTRR_FIX_64K_40000 0x43
+#define MTRR_FIX_16K_80000 0x44
+#define MTRR_FIX_16K_90000 0x45
+#define MTRR_FIX_16K_A0000 0x46
+#define MTRR_FIX_16K_B0000 0x47
+#define MTRR_FIX_4K_C0000 0x48
+#define MTRR_FIX_4K_C4000 0x49
+#define MTRR_FIX_4K_C8000 0x4a
+#define MTRR_FIX_4K_CC000 0x4b
+#define MTRR_FIX_4K_D0000 0x4c
+#define MTRR_FIX_4K_D4000 0x4d
+#define MTRR_FIX_4K_D8000 0x4e
+#define MTRR_FIX_4K_DC000 0x4f
+#define MTRR_FIX_4K_E0000 0x50
+#define MTRR_FIX_4K_E4000 0x51
+#define MTRR_FIX_4K_E8000 0x52
+#define MTRR_FIX_4K_EC000 0x53
+#define MTRR_FIX_4K_F0000 0x54
+#define MTRR_FIX_4K_F4000 0x55
+#define MTRR_FIX_4K_F8000 0x56
+#define MTRR_FIX_4K_FC000 0x57
+
+#define MTRR_SMRR_PHYBASE 0x58
+#define MTRR_SMRR_PHYMASK 0x59
+
+#define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n))
+#define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n))
+
+#ifndef __ASSEMBLY__
+
+/* variable range MTRR usage */
+enum {
+ MTRR_VAR_ROM,
+ MTRR_VAR_ESRAM,
+ MTRR_VAR_RAM
+};
+
+#endif /* __ASSEMBLY__ */
+
/* Port 0x04: Remote Management Unit Message Port Registers */
/* ACPI PBLK Base Address Register */
#define PBLK_BA 0x70
+/* Control Register */
+#define RMU_CTRL 0x71
+
/* SPI DMA Base Address Register */
#define SPI_DMA_BA 0x7a
+/* Thermal Sensor Register */
+#define TS_MODE 0xb0
+#define TS_TEMP 0xb1
+#define TS_TRIP 0xb2
+
/* Port 0x05: Memory Manager Message Port Registers */
/* eSRAM Block Page Control */
/* Port 0x31: SoC Unit Port Registers */
+/* Thermal Sensor Config */
+#define TS_CFG1 0x31
+#define TS_CFG2 0x32
+#define TS_CFG3 0x33
+#define TS_CFG4 0x34
+
/* PCIe Controller Config */
#define PCIE_CFG 0x36
#define PCIE_CTLR_PRI_RST 0x00010000
/* 64KiB of RMU binary in flash */
#define RMU_BINARY_SIZE 0x10000
+/* PCIe Root Port Configuration Registers */
+
+#define PCIE_RP_CCFG 0xd0
+#define CCFG_UPRS (1 << 14)
+#define CCFG_UNRS (1 << 15)
+#define CCFG_UNSD (1 << 23)
+#define CCFG_UPSD (1 << 24)
+
+#define PCIE_RP_MPC2 0xd4
+#define MPC2_IPF (1 << 11)
+
+#define PCIE_RP_MBC 0xf4
+#define MBC_SBIC (3 << 16)
+
/* Legacy Bridge PCI Configuration Registers */
#define LB_GBA 0x44
#define LB_PM1BLK 0x48
#define LB_BC 0xd8
#define LB_RCBA 0xf0
+/* USB EHCI memory-mapped registers */
+#define EHCI_INSNREG01 0x94
+
+/* USB device memory-mapped registers */
+#define USBD_INT_MASK 0x410
+#define USBD_EP_INT_STS 0x414
+#define USBD_EP_INT_MASK 0x418
+
#ifndef __ASSEMBLY__
/* Root Complex Register Block */
entries[num_entries].type = E820_RAM;
else if (res_desc->type == RES_MEM_RESERVED)
entries[num_entries].type = E820_RESERVED;
+
+ num_entries++;
}
hdr = get_next_hob(hdr);
- num_entries++;
}
/* Mark PCIe ECAM address range as reserved */
}
/* setup vxworks bootline */
char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
-
- /* setup default IP, in case if there is nothing in environment */
- if (!getenv("ipaddr")) {
- setenv("ipaddr", "192.168.60.1");
- setenv("netmask", "255.255.255.0");
- setenv("serverip", "192.168.60.254");
- setenv("gatewayip", "192.168.60.254");
- puts("net: had no IP! made default setup.\n");
- }
-
sprintf(vxworksbootline,
"%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
DEFAULT_BOOTLINE,
+++ /dev/null
-if TARGET_EB_CPUX9K2
-
-config SYS_BOARD
- default "eb_cpux9k2"
-
-config SYS_VENDOR
- default "BuS"
-
-config SYS_CONFIG_NAME
- default "eb_cpux9k2"
-
-endif
+++ /dev/null
-EB_CPUX9K2 BOARD
-M: Jens Scharsig <esw@bus-elektronik.de>
-S: Maintained
-F: board/BuS/eb_cpux9k2/
-F: include/configs/eb_cpux9k2.h
-F: configs/eb_cpux9k2_defconfig
-F: configs/eb_cpux9k2_ram_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cpux9k2.o
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
- * Jens Scharsig <esw@bus-elektronik.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <exports.h>
-#include <net.h>
-#include <netdev.h>
-#include <nand.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_common.h>
-
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-
-#ifdef CONFIG_VIDEO
-#include <bus_vcxk.h>
-
-extern unsigned long display_width;
-extern unsigned long display_height;
-#endif
-
-#ifdef CONFIG_CMD_NAND
-void cpux9k2_nand_hw_init(void);
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- /* Correct IRDA resistor problem / Set PA23_TXD in Output */
- writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
-
- gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_STATUS_LED
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
-#ifdef CONFIG_CMD_NAND
- cpux9k2_nand_hw_init();
-#endif
- return 0;
-}
-
-int board_early_init_f(void)
-{
- at91_seriald_hw_init();
- return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-
-int misc_init_r(void)
-{
- uchar mac[8];
- uchar tm;
- uchar midx;
- uchar macn6, macn7;
-
- if (getenv("ethaddr") == NULL) {
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- (uchar *) &mac, sizeof(mac)) != 0) {
- puts("Error reading MAC from EEPROM\n");
- } else {
- tm = 0;
- macn6 = 0;
- macn7 = 0xFF;
- for (midx = 0; midx < 6; midx++) {
- if ((mac[midx] != 0) && (mac[midx] != 0xFF))
- tm++;
- macn6 += mac[midx];
- macn7 ^= mac[midx];
- }
- if ((macn6 != mac[6]) || (macn7 != mac[7]))
- tm = 0;
- if (tm)
- eth_setenv_enetaddr("ethaddr", mac);
- else
- puts("Error: invalid MAC at EEPROM\n");
- }
- }
- gd->jt->do_reset = do_reset;
-
-#ifdef CONFIG_STATUS_LED
- status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
-#endif
- return 0;
-}
-#endif
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
- udelay(10000);
- eth_init();
-}
-#endif
-
-/*
- * DRAM initialisations
- */
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-/*
- * Ethernet initialisations
- */
-
-#ifdef CONFIG_DRIVER_AT91EMAC
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
- rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
- return rc;
-}
-#endif
-
-/*
- * Disk On Chip (NAND) Millenium initialization.
- * The NAND lives in the CS2* space
- */
-#if defined(CONFIG_CMD_NAND)
-
-#define MASK_ALE (1 << 22) /* our ALE is AD22 */
-#define MASK_CLE (1 << 21) /* our CLE is AD21 */
-
-void cpux9k2_nand_hw_init(void)
-{
- unsigned long csr;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
-
- /* Setup Smart Media, fitst enable the address range of CS3 */
- writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
-
- /* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
- csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
- AT91_SMC_CSR_NWS(3) |
- AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
- AT91_SMC_CSR_WSEN;
- writel(csr, &mc->smc.csr[3]);
-
- writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr);
- writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE,
- &pio->pioc.pdr);
-
- /* Configure PC2 as input (signal Nand READY ) */
- writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per);
- writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
- writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr);
-
- /* PIOC clock enabling */
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-}
-
-static void board_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- if ((ctrl & NAND_NCE))
- writel(1, &pio->pioc.codr);
- else
- writel(1, &pio->pioc.sodr);
-
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int board_nand_dev_ready(struct mtd_info *mtd)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- cpux9k2_nand_hw_init();
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->cmd_ctrl = board_nand_hwcontrol;
- nand->dev_ready = board_nand_dev_ready;
- nand->chip_delay = 20;
- return 0;
-}
-
-#endif
-
-#if defined(CONFIG_VIDEO)
-/*
- * drv_video_init
- * FUNCTION: initialize VCxK device
- */
-
-int drv_video_init(void)
-{
-#ifdef CONFIG_SPLASH_SCREEN
- unsigned long splash;
-#endif
- char *s;
- unsigned long csr;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
-
- printf("Init Video as ");
- s = getenv("displaywidth");
- if (s != NULL)
- display_width = simple_strtoul(s, NULL, 10);
- else
- display_width = 256;
- s = getenv("displayheight");
- if (s != NULL)
- display_height = simple_strtoul(s, NULL, 10);
- else
- display_height = 256;
- printf("%ld x %ld pixel matrix\n", display_width, display_height);
-
- /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */
- csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
- AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
- AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
- AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
- writel(csr, &mc->smc.csr[2]);
- writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
-
- vcxk_init(display_width, display_height);
-#ifdef CONFIG_SPLASH_SCREEN
- s = getenv("splashimage");
- if (s != NULL) {
- splash = simple_strtoul(s, NULL, 16);
- printf("use splashimage: %lx\n", splash);
- video_display_bitmap(splash, 0, 0);
- }
-#endif
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-
-void i2c_init_board(void)
-{
- u32 pin;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
- pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-#ifdef CONFIG_STATUS_LED
-
-void __led_toggle(led_id_t mask)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- if (readl(&pio->piod.odsr) & mask)
- writel(mask, &pio->piod.codr);
- else
- writel(mask, &pio->piod.codr);
-}
-
-void __led_init(led_id_t mask, int state)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
- /* Disable peripherals on LEDs */
- writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
- /* Enable pins as outputs */
- writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
- /* Turn all LEDs OFF */
- writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
-
- __led_set(mask, state);
-}
-
-void __led_set(led_id_t mask, int state)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- if (state == STATUS_LED_ON)
- writel(mask, &pio->piod.codr);
- else
- writel(mask, &pio->piod.sodr);
-}
-
-#endif
-
-/*---------------------------------------------------------------------------*/
-
-int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 0;
- ulong side;
- ulong bright;
-
- switch (argc) {
- case 3:
- side = simple_strtoul(argv[1], NULL, 10);
- bright = simple_strtoul(argv[2], NULL, 10);
- if ((side >= 0) && (side <= 3) &&
- (bright >= 0) && (bright <= 1000)) {
- vcxk_setbrightness(side, bright);
- rcode = 0;
- } else {
- printf("parameters out of range\n");
- printf("Usage:\n%s\n", cmdtp->usage);
- rcode = 1;
- }
- break;
- default:
- printf("Usage:\n%s\n", cmdtp->usage);
- rcode = 1;
- break;
- }
- return rcode;
-}
-
-/*---------------------------------------------------------------------------*/
-
-U_BOOT_CMD(
- bright, 3, 0, do_brightness,
- "bright - sets the display brightness\n",
- " <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
-);
-
-/* EOF cpu9k2.c */
+++ /dev/null
-if TARGET_VL_MA2SC
-
-config SYS_BOARD
- default "vl_ma2sc"
-
-config SYS_VENDOR
- default "BuS"
-
-config SYS_CONFIG_NAME
- default "vl_ma2sc"
-
-endif
+++ /dev/null
-VL_MA2SC BOARD
-M: Jens Scharsig <esw@bus-elektronik.de>
-S: Maintained
-F: board/BuS/vl_ma2sc/
-F: include/configs/vl_ma2sc.h
-F: configs/vl_ma2sc_defconfig
-F: configs/vl_ma2sc_ram_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009-2012
-# Jens Scharsig <esw@bus-elekronik.de>
-# BuS Elektronik GmbH & Co. KG
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += vl_ma2sc.o
+++ /dev/null
-/*
- * (C) Copyright 2009-2012
- * Jens Scharsig <esw@bus-elekronik.de>
- * BuS Elektronik GmbH & Co. KG
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_common.h>
-#include <lcd.h>
-#include <i2c.h>
-#include <atmel_lcdc.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NAND
-static void vl_ma2sc_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
- at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
- at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
-
- /* Enable CS3 */
- csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa[0]);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
-
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
-
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
- writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
- &pmc->pcer);
-
- /* Configure RDY/BSY */
-#ifdef CONFIG_SYS_NAND_READY_PIN
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-#endif
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void vl_ma2sc_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
-
- at91_phy_reset();
-
- at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
- .vl_col = 320,
- .vl_row = 240,
- .vl_clk = 6500000,
- .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
- ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVVD_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
- .vl_tft = 1,
- .vl_hsync_len = 5, /* Horiz Sync Pulse Width */
- .vl_left_margin = 68, /* horiz back porch */
- .vl_right_margin = 20, /* horiz front porch */
- .vl_vsync_len = 2, /* vert Sync Pulse Width */
- .vl_upper_margin = 18, /* vert back porch */
- .vl_lower_margin = 4, /* vert front porch */
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-static void vl_ma2sc_lcd_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
- at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
-
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
-
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
-
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
- at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
-
- at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
-
- at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
- at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
- at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
- at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
- at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
- at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
-
- at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
-
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
- gd->fb_base = ATMEL_BASE_SRAM0;
-}
-#endif /* Config LCD */
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOCDE),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- return 0;
-}
-#endif
-
-int board_init(void)
-{
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u32 pin;
-
- pin = 0x1F000001;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
- writel((1 << 25), &pio->pioa.codr);
-
- pin = 0x1F000100;
- writel(pin, &pio->piob.idr);
- writel(pin, &pio->piob.pudr);
- writel(pin, &pio->piob.per);
- writel(pin, &pio->piob.oer);
- writel(pin, &pio->piob.codr);
- writel((1 << 24), &pio->piob.sodr);
-
- pin = 0x40000000; /* Pullup DRxD enbable */
- writel(pin, &pio->pioc.puer);
-
- pin = 0x0000000F; /* HWversion als Input */
- writel(pin, &pio->piod.idr);
- writel(pin, &pio->piod.puer);
- writel(pin, &pio->piod.per);
- writel(pin, &pio->piod.odr);
- writel(pin, &pio->piod.owdr);
-
- gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
- writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
- writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
- writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
-
-#ifdef CONFIG_CMD_NAND
- vl_ma2sc_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- vl_ma2sc_macb_hw_init();
-#endif
-#ifdef CONFIG_USB_OHCI_NEW
- at91_uhp_hw_init();
-#endif
-#ifdef CONFIG_LCD
- vl_ma2sc_lcd_hw_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- uchar buffer[8];
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u32 pin;
-
- buffer[0] = 0x04;
- buffer[1] = 0x00;
- if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
- puts("error reseting rtc clock\n\0");
-
- /* read hardware version */
-
- pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
- printf("Board: revision %c\n", pin);
- buffer[0] = pin;
- buffer[1] = 0;
- setenv("revision", (char *) buffer);
-
- pin = 0x40000000; /* Pullup DRxD enbable */
- writel(pin, &pio->pioc.puer);
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-#ifdef CONFIG_MACB
- /*
- * Initialize ethernet HW addr prior to starting Linux,
- * needed for nfsroot
- */
- eth_init();
-#endif
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
-#endif
- return rc;
-}
-
-#ifdef CONFIG_SYS_I2C_SOFT
-void i2c_init_board(void)
-{
- u32 pin;
-
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u8 sda = (1<<4);
- u8 scl = (1<<5);
-
- writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
- pin = sda | scl;
- writel(pin, &pio->piob.idr); /* Disable Interupt */
- writel(pin, &pio->piob.pudr);
- writel(pin, &pio->piob.per);
- writel(pin, &pio->piob.oer);
- writel(pin, &pio->piob.sodr);
-}
-#endif
-
-void watchdog_reset(void)
-{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- u32 pin = 0x1; /* PA0 */
-
- if ((readl(&pio->pioa.odsr) & pin) > 0)
- writel(pin, &pio->pioa.codr);
- else
- writel(pin, &pio->pioa.sodr);
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
-/*---------------------------------------------------------------------------*/
-
-int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 1;
- int row;
- int col;
- u32 pinz;
- u32 pins;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
-
- pins = 0x1F000000;
- writel(pins, &pio->pioa.idr);
- writel(pins, &pio->pioa.pudr);
- writel(pins, &pio->pioa.per);
- writel(pins, &pio->pioa.oer);
- writel(pins, &pio->pioa.sodr);
-
- pinz = 0x1F000000;
- writel(pinz, &pio->piob.idr);
- writel(pinz, &pio->piob.pudr);
- writel(pinz, &pio->piob.per);
- writel(pinz, &pio->piob.oer);
- writel(pinz, &pio->piob.sodr);
-
- for (row = 0; row < 5; row++) {
- for (col = 0; col < 5; col++) {
- writel((0x01000000 << col), &pio->piob.sodr);
- writel((0x01000000 << row), &pio->pioa.codr);
- printf("LED Test %d x %d\n", row, col);
- udelay(1000000);
- writel(pinz, &pio->piob.codr);
- writel(pins, &pio->pioa.sodr);
- }
- }
- return rcode;
-}
-
-void poweroff(void)
-{
- watchdog_reset();
- at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
- udelay(100);
- at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
- udelay(100);
- at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
- udelay(100);
- while (1)
- watchdog_reset();
-}
-
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 1;
- poweroff();
- return rcode;
-}
-
-int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
- u32 freq;
- u32 durate;
- int rcode = 1;
-
- freq = 1000;
- durate = 2;
- switch (argc) {
- case 3:
- durate = simple_strtoul(argv[2], NULL, 10);
- case 2:
- freq = simple_strtoul(argv[1], NULL, 10);
- case 1:
- break;
- default:
- cmd_usage(cmdtp);
- rcode = 1;
- break;
- }
- durate = durate * freq;
- freq = 500000 / freq;
- for (i = 0; i < durate; i++) {
- at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
- udelay(freq);
- at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
- udelay(freq);
- }
- at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
- return rcode;
-}
-
-int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rcode = 1;
- int row;
- u32 col;
- u32 pinz;
- u32 pins;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
-
- pins = 0x001F0000;
- writel(pins, &pio->pioa.idr);
- writel(pins, &pio->pioa.pudr);
- writel(pins, &pio->pioa.per);
- writel(pins, &pio->pioa.odr);
-
- pinz = 0x000F0000;
- writel(pinz, &pio->piob.idr);
- writel(pinz, &pio->piob.pudr);
- writel(pinz, &pio->piob.per);
- writel(pinz, &pio->piob.oer);
- writel(pinz, &pio->piob.codr);
-
- while (1) {
- col = 0;
- for (row = 0; row < 4; row++) {
- writel((0x00010000 << row), &pio->piob.sodr);
- udelay(10000);
- col <<= 4;
- col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
- writel(pinz, &pio->piob.codr);
- }
- printf("Matix: ");
- for (row = 0; row < 16; row++) {
- printf("%1.1d", col & 1);
- col >>= 1;
- }
- printf(" SP %d\r ",
- 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
- if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
- /* SHUTDOWN */
- row = 0;
- while (row < 1000) {
- if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
- row++;
- udelay(100);
- }
- udelay(100000);
- row = 0;
- while (row < 1000) {
- if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
- row++;
- udelay(1000);
- }
- }
- poweroff();
- while (1)
- ;
- }
- }
- return rcode;
-}
-
-/*****************************************************************************/
-
-U_BOOT_CMD(
- ledtest, 1, 0, do_ledtest,
- "test ledmatrix",
- "\n"
- );
-
-U_BOOT_CMD(
- keytest, 1, 0, do_keytest,
- "test keymatix and special keys, poweroff on pressing ON key",
- "\n"
- );
-
-U_BOOT_CMD(
- poweroff, 1, 0, do_poweroff,
- "power off",
- "\n"
- );
-
-U_BOOT_CMD(
- beep, 3, 0, do_beep,
- "[freq [duration]]",
- "freq frequence of beep\nduration duration of beep\n"
- );
-
-/*****************************************************************************/
+++ /dev/null
-if TARGET_WIRELESS_SPACE
-
-config SYS_BOARD
- default "wireless_space"
-
-config SYS_VENDOR
- default "LaCie"
-
-config SYS_CONFIG_NAME
- default "wireless_space"
-
-endif
+++ /dev/null
-WIRELESS_SPACE BOARD
-M: Albert ARIBAUD <albert.u.boot@aribaud.net>
-S: Maintained
-F: board/LaCie/wireless_space/
-F: include/configs/wireless_space.h
-F: configs/wireless_space_defconfig
+++ /dev/null
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := wireless_space.o ../common/common.o
+++ /dev/null
-#
-# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# Based on netspace_v2 kwbimage.cfg:
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand # Boot from NAND flash
-NAND_PAGE_SIZE 800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Values taken from image original LaCie U-Boot header dump!
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-
-DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-
-DATA 0xFFD01410 0x0000CCCC # DDR Address Control
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-
-DATA 0xFFD0141C 0x00000662 # DDR Mode
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-
-DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
-
-DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-DATA 0xFFD20134 0x66666666
-DATA 0xFFD20138 0x66666666
-DATA 0xFFD10000 0x01112222
-DATA 0xFFD1000C 0x00000000
-DATA 0xFFD10104 0x00000000
-DATA 0xFFD10100 0x40000000
-# End of Header extension
-DATA 0x0 0x0
+++ /dev/null
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#include "../common/common.h"
-#include "netdev.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO configuration: start FAN at low speed, USB and HDD */
-
-#define WIRELESS_SPACE_OE_LOW 0xFF006808
-#define WIRELESS_SPACE_OE_HIGH 0x0000F989
-#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080
-#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240
-
-#define WIRELESS_SPACE_REAR_BUTTON 13
-#define WIRELESS_SPACE_FRONT_BUTTON 43
-
-const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Fan speed (bit 1) */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP13_GPIO, /* Red led */
- MPP14_GPIO, /* USB fuse */
- MPP15_SATA0_ACTn,
- MPP16_GPIO, /* SATA 0 power */
- MPP17_GPIO, /* SATA 1 power */
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0, /* Gigabit Ethernet 1 */
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GE1_8,
- MPP29_GE1_9,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GE1_14,
- MPP35_GE1_15,
- MPP36_GPIO, /* Fan speed (bit 2) */
- MPP37_GPIO, /* Fan speed (bit 0) */
- MPP38_GPIO, /* Fan power */
- MPP39_GPIO, /* Fan rotation fail */
- MPP40_GPIO, /* Ethernet switch link */
- MPP41_GPIO, /* USB enable host vbus */
- MPP42_GPIO, /* LED clock control */
- MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */
- MPP44_GPIO, /* Red LED on/off */
- MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */
- MPP46_GPIO, /* Green LED on/off */
- MPP47_GPIO, /* LED (blue, green) SATA activity blink */
- MPP48_GPIO, /* Blue LED on/off */
- 0
-};
-
-struct mv88e61xx_config swcfg = {
- .name = "egiga0",
- .vlancfg = MV88E61XX_VLANCFG_ROUTER,
- .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
- .led_init = MV88E61XX_LED_INIT_EN,
- .mdip = MV88E61XX_MDIP_NOCHANGE,
- .portstate = MV88E61XX_PORTSTT_FORWARDING,
- .cpuport = 0x20,
- .ports_enabled = 0x3F,
-};
-
-int board_early_init_f(void)
-{
- /* Gpio configuration */
- mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
- WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Machine number */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* Boot parameters address */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
- if (!getenv("ethaddr")) {
- uchar mac[6];
- if (lacie_read_mac_address(mac) == 0)
- eth_setenv_enetaddr("ethaddr", mac);
- }
-#endif
- return 0;
-}
-#endif
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
- /* configure switch on egiga0 */
- mv88e61xx_switch_initialize(&swcfg);
-}
-#endif
-
-#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
-/* Return GPIO button status */
-static int
-do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (strcmp(argv[1], "button") == 0) {
- if (strcmp(argv[2], "rear") == 0)
- /* invert GPIO result for intuitive while/until use */
- return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
- else if (strcmp(argv[2], "front") == 0)
- return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
- else
- return -1;
- } else {
- return -1;
- }
-}
-
-U_BOOT_CMD(ws, 3, 0, do_ws,
- "Return GPIO button status 0=off 1=on",
- "- ws button rear|front: test buttons' states\n"
-);
-#endif
+++ /dev/null
-if TARGET_MV88F6281GTW_GE
-
-config SYS_BOARD
- default "mv88f6281gtw_ge"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "mv88f6281gtw_ge"
-
-endif
+++ /dev/null
-MV88F6281GTW_GE BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/mv88f6281gtw_ge/
-F: include/configs/mv88f6281gtw_ge.h
-F: configs/mv88f6281gtw_ge_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mv88f6281gtw_ge.o
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000a00 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x0000002A # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000000D # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000046 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E811 # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
+++ /dev/null
-/*
- * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "mv88f6281gtw_ge.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
- MV88F6281GTW_GE_OE_VAL_HIGH,
- MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_GPIO,
- MPP5_GPO,
- MPP6_SYSRST_OUTn,
- MPP7_SPI_SCn,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO,
- MPP13_GPIO,
- MPP14_GPIO,
- MPP15_GPIO,
- MPP16_GPIO,
- MPP17_GPIO,
- MPP18_GPO,
- MPP19_GPO,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_MV88E61XX_SWITCH
-void reset_phy(void)
-{
- /* configure and initialize switch */
- struct mv88e61xx_config swcfg = {
- .name = "egiga0",
- .vlancfg = MV88E61XX_VLANCFG_ROUTER,
- .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
- .led_init = MV88E61XX_LED_INIT_EN,
- .mdip = MV88E61XX_MDIP_REVERSE,
- .portstate = MV88E61XX_PORTSTT_FORWARDING,
- .cpuport = (1 << 5),
- .ports_enabled = 0x3f
- };
-
- mv88e61xx_switch_initialize(&swcfg);
-}
-#endif /* CONFIG_MV88E61XX_SWITCH */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MV88F6281GTW_GE_H
-#define __MV88F6281GTW_GE_H
-
-#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \
- |(1 << 20) | (1 << 21))) /*enable GLED,RLED */
-#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \
- |(1 << 13)|(1 << 16)|(1 << 17)))
-#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */
-#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17))
-
-
-#endif /* __MV88F6281GTW_GE_H */
+++ /dev/null
-if TARGET_OPENRD
-
-config SYS_BOARD
- default "openrd"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "openrd"
-
-endif
+++ /dev/null
-OPENRD BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/openrd/
-F: include/configs/openrd.h
-F: configs/openrd_base_defconfig
-
-OPENRD_CLIENT BOARD
-#M: -
-S: Maintained
-F: configs/openrd_client_defconfig
-F: configs/openrd_ultimate_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := openrd.o
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000042 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strength reduced
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
-# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
-# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
-# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
-# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-
-DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
-# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
-# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT: Enabled
-# bit15: 1, DDR IO ODT Unit: Use ODT block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.c:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "openrd.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(OPENRD_OE_VAL_LOW,
- OPENRD_OE_VAL_HIGH,
- OPENRD_OE_LOW, OPENRD_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD, /* Alt UART1_TXD */
- MPP14_SD_D0, /* Alt UART1_RXD */
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_TSMP9,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GPIO, /* UART1 / SD sel */
- MPP35_TDM_CH0_TX_QL,
- MPP36_TDM_SPI_CS1,
- MPP37_TDM_CH2_TX_QL,
- MPP38_TDM_CH2_RX_QL,
- MPP39_AUDIO_I2SBCLK,
- MPP40_AUDIO_I2SDO,
- MPP41_AUDIO_I2SLRC,
- MPP42_AUDIO_I2SMCLK,
- MPP43_AUDIO_I2SDI,
- MPP44_AUDIO_EXTCLK,
- MPP45_TDM_PCLK,
- MPP46_TDM_FS,
- MPP47_TDM_DRX,
- MPP48_TDM_DTX,
- MPP49_TDM_CH0_RX_QL,
- 0
- };
-
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
-#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
- gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
-#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
- gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
-#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
- gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116/88E1121 PHY */
-void mv_phy_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf(PHY_NO" Initialized on %s\n", name);
-}
-
-void reset_phy(void)
-{
- mv_phy_init("egiga0");
-
-#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
- /* Kirkwood ethernet driver is written with the assumption that in case
- * of multiple PHYs, their addresses are consecutive. But unfortunately
- * in case of OpenRD-Client, PHY addresses are not consecutive.*/
- miiphy_write("egiga1", 0xEE, 0xEE, 24);
-#endif
-
-#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
- defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
- /* configure and initialize both PHY's */
- mv_phy_init("egiga1");
-#endif
-}
-#endif /* CONFIG_RESET_PHY_R */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.h:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __OPENRD_BASE_H
-#define __OPENRD_BASE_H
-
-#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
-#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __OPENRD_BASE_H */
+++ /dev/null
-if TARGET_RD6281A
-
-config SYS_BOARD
- default "rd6281a"
-
-config SYS_VENDOR
- default "Marvell"
-
-config SYS_CONFIG_NAME
- default "rd6281a"
-
-endif
+++ /dev/null
-RD6281A BOARD
-M: Prafulla Wadaskar <prafulla@marvell.com>
-S: Maintained
-F: board/Marvell/rd6281a/
-F: include/configs/rd6281a.h
-F: configs/rd6281a_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := rd6281a.o
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000099 # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs1width=x8
-# bit7-6: 11, Cs1size=1Gb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000C52 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 1, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 0, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
-# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
-# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
-# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include "rd6281a.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(RD6281A_OE_VAL_LOW,
- RD6281A_OE_VAL_HIGH,
- RD6281A_OE_LOW, RD6281A_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GE1_14,
- MPP35_GPIO,
- MPP36_AUDIO_SPDIFI,
- MPP37_AUDIO_SPDIFO,
- MPP38_GPIO,
- MPP39_TDM_SPI_CS0,
- MPP40_TDM_SPI_SCK,
- MPP41_TDM_SPI_MISO,
- MPP42_TDM_SPI_MOSI,
- MPP43_TDM_CODEC_INTn,
- MPP44_GPIO,
- MPP45_TDM_PCLK,
- MPP46_TDM_FS,
- MPP47_TDM_DRX,
- MPP48_TDM_DTX,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-void mv_phy_88e1116_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) {
- printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
- return;
- }
- if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
- printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
- return;
- }
-
- printf("88E1116 Initialized on %s\n", name);
-}
-
-/* Configure and enable Switch and PHY */
-void reset_phy(void)
-{
- /* configure and initialize switch */
- struct mv88e61xx_config swcfg = {
- .name = "egiga0",
- .vlancfg = MV88E61XX_VLANCFG_ROUTER,
- .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
- .led_init = MV88E61XX_LED_INIT_EN,
- .portstate = MV88E61XX_PORTSTT_FORWARDING,
- .cpuport = (1 << 5),
- .ports_enabled = 0x3f,
- };
-
- mv88e61xx_switch_initialize(&swcfg);
-
- /* configure and initialize PHY */
- mv_phy_88e1116_init("egiga1");
-}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __RD6281A_H
-#define __RD6281A_H
-
-#define RD6281A_OE_LOW (~(1 << 7))
-#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12))
-#define RD6281A_OE_VAL_LOW (0)
-#define RD6281A_OE_VAL_HIGH (1 << 12)
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG 10
-#define MV88E1116_CPRSP_CR3_REG 21
-#define MV88E1116_MAC_CTRL_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-#endif /* __RD6281A_H */
SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@altera.com>
+M: Dinh Nguyen <dinguyen@opensource.altera.com>
M: Chin-Liang See <clsee@altera.com>
S: Maintained
F: board/altera/arria5-socdk/
-F: include/configs/socfpga_arria5.h
+F: include/configs/socfpga_arria5_socdk.h
F: configs/socfpga_arria5_defconfig
SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@altera.com>
+M: Dinh Nguyen <dinguyen@opensource.altera.com>
M: Chin-Liang See <clsee@altera.com>
S: Maintained
F: board/altera/cyclone5-socdk/
-F: include/configs/socfpga_cyclone5.h
+F: include/configs/socfpga_cyclone5_socdk.h
F: configs/socfpga_cyclone5_defconfig
SOCRATES BOARD
config SYS_BOARD
default "aristainetos"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "aristainetos"
config SYS_BOARD
default "aristainetos"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "aristainetos2"
config SYS_BOARD
default "aristainetos"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "aristainetos2b"
F: configs/aristainetos_defconfig
F: include/configs/aristainetos2.h
F: configs/aristainetos2_defconfig
+F: configs/aristainetos2b_defconfig
+++ /dev/null
-VERSATILE BOARD
-#M: -
-S: Maintained
-F: board/armltd/versatile/
-F: include/configs/versatile.h
-F: configs/versatileab_defconfig
-F: configs/versatilepb_defconfig
-F: configs/versatileqemu_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := versatile.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
- /* All done by Versatile's boot monitor! */
- mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
- printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f (void)
-{
- /*
- * set clock frequency:
- * VERSATILE_REFCLK is 32KHz
- * VERSATILE_TIMCLK is 1MHz
- */
- *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
- ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
- (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
-
- return 0;
-}
-
-int board_init (void)
-{
- /* arch number of Versatile Board */
-#ifdef CONFIG_ARCH_VERSATILE_AB
- gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB;
-#else
- gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- gd->flags = 0;
-
- icache_enable ();
-
- return 0;
-}
-
-
-int misc_init_r (void)
-{
- setenv("verify", "n");
- return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
-if TARGET_VEXPRESS64_BASE_FVP
-
-config SYS_BOARD
- default "vexpress64"
-
-config SYS_VENDOR
- default "armltd"
-
-config SYS_CONFIG_NAME
- default "vexpress_aemv8a"
-
-endif
-
-if TARGET_VEXPRESS64_JUNO
+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || TARGET_VEXPRESS64_BASE_FVP_DRAM
config SYS_BOARD
default "vexpress64"
S: Maintained
F: configs/vexpress_aemv8a_semi_defconfig
+VEXPRESS_AEMV8A_DRAM BOARD
+M: Ryan Harkin <ryan.harkin@linaro.org>
+S: Maintained
+F: configs/vexpress_aemv8a_dram_defconfig
+
JUNO DEVELOPMENT PLATFORM BOARD
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
config SYS_VENDOR
default "bachmann"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "ot1200"
bus = fec_get_miibus(base, -1);
if (!bus)
- return 0;
+ return -EINVAL;
/* scan phy 0 and 5 */
phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
- free(bus);
- return 0;
+ ret = -EINVAL;
+ goto free_bus;
}
/* depending on the phy address we can detect our board version */
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- free(phydev);
- free(bus);
- }
+ if (ret)
+ goto free_phydev;
+
return 0;
+
+free_phydev:
+ free(phydev);
+free_bus:
+ free(bus);
+ return ret;
}
int board_init(void)
+++ /dev/null
-if TARGET_BALLOON3
-
-config SYS_BOARD
- default "balloon3"
-
-config SYS_CONFIG_NAME
- default "balloon3"
-
-endif
+++ /dev/null
-BALLOON3 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/balloon3/
-F: include/configs/balloon3.h
-F: configs/balloon3_defconfig
+++ /dev/null
-#
-# Balloon3 Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := balloon3.o
+++ /dev/null
-/*
- * Balloon3 Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <spartan3.h>
-#include <command.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void balloon3_init_fpga(void);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of balloon3 */
- gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Init the FPGA */
- balloon3_init_fpga();
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-}
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- /* enable port 2 */
- writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
- UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-#endif
-
-#if defined(CONFIG_FPGA)
-/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
-int fpga_pgm_fn(int nassert, int nflush, int cookie)
-{
- if (nassert)
- writel(0x80, GPCR3);
- else
- writel(0x80, GPSR3);
- if (nflush)
- writel(0x100, GPCR3);
- else
- writel(0x100, GPSR3);
- return nassert;
-}
-
-/* Check GPIO83 -- INITB */
-int fpga_init_fn(int cookie)
-{
- return !(readl(GPLR2) & 0x80000);
-}
-
-/* Check GPIO84 -- BUSY */
-int fpga_busy_fn(int cookie)
-{
- return !(readl(GPLR2) & 0x100000);
-}
-
-/* Check GPIO111 -- DONE */
-int fpga_done_fn(int cookie)
-{
- return readl(GPLR3) & 0x8000;
-}
-
-/* Configure GPIO104 as GPIO and deassert it */
-int fpga_pre_config_fn(int cookie)
-{
- writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
- writel(0x100, GPCR3);
- return 0;
-}
-
-/* Configure GPIO104 as nSKTSEL */
-int fpga_post_config_fn(int cookie)
-{
- writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
- return 0;
-}
-
-/* Toggle RDnWR */
-int fpga_wr_fn(int nassert_write, int flush, int cookie)
-{
- udelay(1000);
-
- if (nassert_write)
- writel(0x100, GPCR3);
- else
- writel(0x100, GPSR3);
-
- return nassert_write;
-}
-
-/* Write program to the FPGA */
-int fpga_wdata_fn(uchar data, int flush, int cookie)
-{
- writeb(data, 0x10f00000);
- return 0;
-}
-
-/* Toggle Clock pin -- NO-OP */
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
- return assert_clk;
-}
-
-/* Toggle ChipSelect pin -- NO-OP */
-int fpga_cs_fn(int assert_clk, int flush, int cookie)
-{
- return assert_clk;
-}
-
-xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_init_fn,
- NULL, /* err */
- fpga_done_fn,
- fpga_clk_fn,
- fpga_cs_fn,
- fpga_wr_fn,
- NULL, /* rdata */
- fpga_wdata_fn,
- fpga_busy_fn,
- NULL, /* abort */
- fpga_post_config_fn,
-};
-
-xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
- (void *)&balloon3_fpga_fns, 0);
-
-/* Initialize the FPGA */
-void balloon3_init_fpga(void)
-{
- fpga_init();
- fpga_add(fpga_xilinx, &fpga);
-}
-#else
-void balloon3_init_fpga(void) {}
-#endif /* CONFIG_FPGA */
config SYS_VENDOR
default "barco"
-config SYS_SOC
- default "mx6"
-
config SYS_BOARD
default "platinum"
config SYS_VENDOR
default "barco"
-config SYS_SOC
- default "mx6"
-
config SYS_BOARD
default "platinum"
config SYS_VENDOR
default "barco"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "titanium"
config SYS_VENDOR
default "boundary"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "nitrogen6x"
#ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
- return 0;
+ return -EINVAL;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
- free(bus);
- return 0;
+ ret = -EINVAL;
+ goto free_bus;
}
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- free(phydev);
- free(bus);
- }
+ if (ret)
+ goto free_phydev;
#endif
#ifdef CONFIG_CI_UDC
usb_eth_initialize(bis);
#endif
return 0;
+
+free_phydev:
+ free(phydev);
+free_bus:
+ free(bus);
+ return ret;
}
static void setup_buttons(void)
+++ /dev/null
-if TARGET_DIG297
-
-config SYS_BOARD
- default "dig297"
-
-config SYS_VENDOR
- default "comelit"
-
-config SYS_CONFIG_NAME
- default "dig297"
-
-endif
+++ /dev/null
-DIG297 BOARD
-M: Luca Ceresoli <luca.ceresoli@comelit.it>
-S: Maintained
-F: board/comelit/dig297/
-F: include/configs/dig297.h
-F: configs/dig297_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dig297.o
+++ /dev/null
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on board/ti/beagle/beagle.c:
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/omap3-regs.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include "dig297.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NET
-static void setup_net_chip(void);
-
-#define NET_LAN9221_RESET_GPIO 12
-
-/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */
-#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT)
-#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \
- CSRDOFFTIME(7) | \
- ADVONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \
- ADVRDOFFTIME(2) | \
- ADVONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \
- WEONTIME(1) | \
- OEOFFTIME(7)| \
- OEONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \
- RDACCESSTIME(6) | \
- WRCYCLETIME(0x1D) | \
- RDCYCLETIME(0x1D))
-#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \
- WRACCESSTIME(0x1D) | \
- WRDATAONADMUXBUS(3))
-
-static const u32 gpmc_lan_config[] = {
- NET_LAN9220_GPMC_CONFIG1,
- NET_LAN9220_GPMC_CONFIG2,
- NET_LAN9220_GPMC_CONFIG3,
- NET_LAN9220_GPMC_CONFIG4,
- NET_LAN9220_GPMC_CONFIG5,
- NET_LAN9220_GPMC_CONFIG6,
- /* CONFIG7: computed by enable_gpmc_cs_config() */
-};
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-
- twl4030_power_init();
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-
- /*
- * GPIO list
- * - 159 OUT (GPIO5+31): reset for remote camera interface connector.
- * - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
- * - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
- */
-
- /* Configure GPIOs to output */
- writel(~(GPIO19 | GPIO20), &gpio1_base->oe);
- writel(~(GPIO31), &gpio5_base->oe);
-
- /* Set GPIO values */
- writel((GPIO19 | GPIO20), &gpio1_base->setdataout);
- writel(0, &gpio5_base->setdataout);
-
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif
-
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DIG297();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Configure GPMC registers */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-
- /* Make GPIO 12 as output pin and send a magic pulse through it */
- if (!gpio_request(NET_LAN9221_RESET_GPIO, "")) {
- gpio_direction_output(NET_LAN9221_RESET_GPIO, 0);
- gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
- udelay(1);
- gpio_set_value(NET_LAN9221_RESET_GPIO, 0);
- udelay(31000); /* Should be >= 30ms according to datasheet */
- gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
- }
-}
-#endif /* CONFIG_CMD_NET */
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- return rc;
-}
+++ /dev/null
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on board/ti/beagle/beagle.h:
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DIG297_H_
-#define _DIG297_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 DIG297 board",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DIG297() \
-/*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
-/*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\
- /* GPMC_nCS1/2: not available on CUS package*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
- MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
- /* GPMC_WAIT2: not available on CUS package*/\
- MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
- /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- /* GPMC_WAIT1: not available on CUS package*/\
-/*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-/*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
-/*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-/*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
-/*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
-/*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
-/*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
-/*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
-/* USB EHCI (port 2) */\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
-/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
- /*
- * McSPI1_CLK.
- * IEN needed fot the McSPI to "receive" the clock and be able to
- * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
- * omap_applications_processors/f/42/p/29444/102394.aspx#102394
- */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\
- MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\
-/* MCSPI2: to HIMAX TFT controller.*/\
- MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\
- /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
- MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\
- MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\
- MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
-/* GPIO */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\
- MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\
- MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\
- MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\
- MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\
- MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\
-/*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */
-
-#endif
config SYS_VENDOR
default "compulab"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "cm_fx6"
#endif
#ifdef CONFIG_OF_BOARD_SETUP
+#define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
int ft_board_setup(void *blob, bd_t *bd)
{
+ u32 baseboard_rev;
+ int nodeoffset;
uint8_t enetaddr[6];
+ char baseboard_name[16];
+ int err;
/* MAC addr */
if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
enetaddr, 6, 1);
}
+ baseboard_rev = cl_eeprom_get_board_rev(0);
+ err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
+ if (err || baseboard_rev == 0)
+ return 0; /* Assume not an early revision SB-FX6m baseboard */
+
+ if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
+ fdt_shrink_to_minimum(blob); /* Make room for new properties */
+ nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
+ fdt_delprop(blob, nodeoffset, "cd-gpios");
+ fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable",
+ NULL, 0, 1);
+ fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
+ NULL, 0, 1);
+ }
+
return 0;
}
#endif
u32 get_board_rev(void)
{
- return cl_eeprom_get_board_rev();
+ return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
}
static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
*/
u32 get_board_rev(void)
{
- return cl_eeprom_get_board_rev();
+ return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
};
int misc_init_r(void)
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
/* MMC1 */
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0));
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
#include <common.h>
#include <i2c.h>
+#include "eeprom.h"
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define BOARD_REV_OFFSET 0
#define BOARD_REV_OFFSET_LEGACY 6
#define BOARD_REV_SIZE 2
+#define PRODUCT_NAME_OFFSET 128
+#define PRODUCT_NAME_SIZE 16
#define MAC_ADDR_OFFSET 4
#define MAC_ADDR_OFFSET_LEGACY 0
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus)
{
uint offset;
+ int err;
- if (cl_eeprom_setup(eeprom_bus))
- return 0;
+ err = cl_eeprom_setup(eeprom_bus);
+ if (err)
+ return err;
offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
* Routine: cl_eeprom_get_board_rev
* Description: read system revision from eeprom
*/
-u32 cl_eeprom_get_board_rev(void)
+u32 cl_eeprom_get_board_rev(uint eeprom_bus)
{
char str[5]; /* Legacy representation can contain at most 4 digits */
uint offset = BOARD_REV_OFFSET_LEGACY;
if (board_rev)
return board_rev;
- if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS))
+ if (cl_eeprom_setup(eeprom_bus))
return 0;
if (cl_eeprom_layout != LAYOUT_LEGACY)
return board_rev;
};
+
+/*
+ * Routine: cl_eeprom_get_board_rev
+ * Description: read system revision from eeprom
+ *
+ * @buf: buffer to store the product name
+ * @eeprom_bus: i2c bus num of the eeprom
+ *
+ * @return: 0 on success, < 0 on failure
+ */
+int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus)
+{
+ int err;
+
+ if (buf == NULL)
+ return -EINVAL;
+
+ err = cl_eeprom_setup(eeprom_bus);
+ if (err)
+ return err;
+
+ err = cl_eeprom_read(PRODUCT_NAME_OFFSET, buf, PRODUCT_NAME_SIZE);
+ if (!err) /* Protect ourselves from invalid data (unterminated str) */
+ buf[PRODUCT_NAME_SIZE - 1] = '\0';
+
+ return err;
+}
#ifndef _EEPROM_
#define _EEPROM_
+#include <errno.h>
#ifdef CONFIG_SYS_I2C
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
-u32 cl_eeprom_get_board_rev(void);
+u32 cl_eeprom_get_board_rev(uint eeprom_bus);
+int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus);
#else
static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus)
{
return 1;
}
-static inline u32 cl_eeprom_get_board_rev(void)
+static inline u32 cl_eeprom_get_board_rev(uint eeprom_bus)
{
return 0;
}
+static inline int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus)
+{
+ return -ENOSYS;
+}
#endif
#endif
config SYS_VENDOR
default "congatec"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "cgtqmx6eval"
CGTQMX6EVAL BOARD
-#M: Leo Sartre <lsartre@adeneo-embedded.com>
-S: Orphan (since 2014-06)
+M: Otavio Salvador <otavio@ossystems.com.br>
+S: Maintained
F: board/congatec/cgtqmx6eval/
F: include/configs/cgtqmx6eval.h
F: configs/cgtqmx6qeval_defconfig
for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
if (!strcmp(mipi_levels[i].name, lv_mipi)) {
- printf("set MIPI level %s\n",
- mipi_levels[i].name);
+ printf("set MIPI level %s\n", mipi_levels[i].name);
ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
mipi_levels[i].value);
if (ret)
+++ /dev/null
-if TARGET_QONG
-
-config SYS_BOARD
- default "qong"
-
-config SYS_VENDOR
- default "davedenx"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "qong"
-
-endif
+++ /dev/null
-QONG BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/davedenx/qong/
-F: include/configs/qong.h
-F: configs/qong_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009
-# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := qong.o fpga.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-#include <fpga.h>
-#include <lattice.h>
-#include "qong_fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-static void qong_jtag_init(void)
-{
- return;
-}
-
-static void qong_fpga_jtag_set_tdi(int value)
-{
- gpio_set_value(QONG_FPGA_TDI_PIN, value);
-}
-
-static void qong_fpga_jtag_set_tms(int value)
-{
- gpio_set_value(QONG_FPGA_TMS_PIN, value);
-}
-
-static void qong_fpga_jtag_set_tck(int value)
-{
- gpio_set_value(QONG_FPGA_TCK_PIN, value);
-}
-
-static int qong_fpga_jtag_get_tdo(void)
-{
- return gpio_get_value(QONG_FPGA_TDO_PIN);
-}
-
-lattice_board_specific_func qong_fpga_fns = {
- qong_jtag_init,
- qong_fpga_jtag_set_tdi,
- qong_fpga_jtag_set_tms,
- qong_fpga_jtag_set_tck,
- qong_fpga_jtag_get_tdo
-};
-
-Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
- {
- Lattice_XP2,
- lattice_jtag_mode,
- 356519,
- (void *) &qong_fpga_fns,
- NULL,
- 0,
- "lfxp2_5e_ftbga256"
- },
-};
-
-int qong_fpga_init(void)
-{
- int i;
-
- fpga_init();
-
- for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
- fpga_add(fpga_lattice, &qong_fpga[i]);
- }
- return 0;
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
- *
- * Based on board/freescale/mx31ads/lowlevel_init.S
- * by Guennadi Liakhovetski.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.macro SETUP_RAM cfg, ctl
- /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
- REG 0xB8001010, 0x00000004
- ldr r3, =\cfg
- ldr r2, =WEIM_ESDCFG0
- str r3, [r2]
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- ldr r3, =\ctl
- ldr r2, =WEIM_ESDCTL0
- str r3, [r2]
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
-.endm
-/* RedBoot: To support 133MHz DDR */
-.macro init_drive_strength
- /*
- * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
- * in SW_PAD_CTL registers
- */
-
- /* SDCLK */
- ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
- ldr r0, [r1, #0x6C]
- bic r0, r0, #(1 << 12)
- str r0, [r1, #0x6C]
-
- /* CAS */
- ldr r0, [r1, #0x70]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x70]
-
- /* RAS */
- ldr r0, [r1, #0x74]
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x74]
-
- /* CS2 (CSD0) */
- ldr r0, [r1, #0x7C]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x7C]
-
- /* DQM3 */
- ldr r0, [r1, #0x84]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x84]
-
- /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
-pad_loop:
- ldr r0, [r1, #0x88]
- bic r0, r0, #(1 << 22)
- bic r0, r0, #(1 << 12)
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x88]
- add r1, r1, #4
- subs r2, r2, #0x1
- bne pad_loop
-.endm /* init_drive_strength */
-
-.globl lowlevel_init
-lowlevel_init:
-
- init_drive_strength
-
- /* Image Processing Unit: */
- /* Too early to switch display on? */
- /* Switch on Display Interface */
- REG IPU_CONF, IPU_CONF_DI_EN
- /* Clock Control Module: */
- REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
- /* Switch to MCU PLL */
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- /* 399-133-66.5 */
- ldr r0, =CCM_BASE
- ldr r1, =0xFF871650
- /* PDR0 */
- str r1, [r0, #0x4]
- ldr r1, MPCTL_PARAM_399
- /* MPCTL */
- str r1, [r0, #0x10]
-
- /* Set UPLL=240MHz, USB=60MHz */
- ldr r1, =0x49FCFE7F
- /* PDR1 */
- str r1, [r0, #0x8]
- ldr r1, UPCTL_PARAM_240
- /* UPCTL */
- str r1, [r0, #0x14]
- /* default CLKO to 1/8 of the ARM core */
- mov r1, #0x00000208
- /* COSR */
- str r1, [r0, #0x1c]
-
- /* Default: 1, 4, 12, 1 */
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
-check_ddr_module:
-/* Set stackpointer in internal RAM to call get_ram_size */
- ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
- stmfd sp!, {r0-r11, ip, lr}
- mov ip, lr /* save link reg across call */
-
- ldr r0,=0x08000000
- SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
- ldr r0,=0x80000000
- ldr r1,=0x10000000
- bl get_ram_size
- ldr r1,=0x10000000
- cmp r0,r1
- beq restore_regs
- SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
- ldr r0,=0x80000000
- ldr r1,=0x08000000
- bl get_ram_size
- ldr r1,=0x08000000
- cmp r0,r1
- beq restore_regs
-
-restore_regs:
- ldmfd sp!, {r0-r11, ip, lr}
- mov lr, ip /* restore link reg */
-
- mov pc, lr
-
-
-MPCTL_PARAM_399:
- .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
-UPCTL_PARAM_240:
- .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
-
- .equ ESDCFG0_128MB, \
- (0 << 21) + /* tXP */ \
- (1 << 20) + /* tWTR */ \
- (2 << 18) + /* tRP */ \
- (1 << 16) + /* tMRD */ \
- (0 << 15) + /* tWR */ \
- (5 << 12) + /* tRAS */ \
- (1 << 10) + /* tRRD */ \
- (3 << 8) + /* tCAS */ \
- (2 << 4) + /* tRCD */ \
- (0x0F << 0) /* tRC */
-
- .equ ESDCTL0_128MB, \
- (1 << 31) + /* enable */ \
- (0 << 28) + /* mode */ \
- (0 << 27) + /* supervisor protect */ \
- (2 << 24) + /* 13 rows */ \
- (2 << 20) + /* 10 cols */ \
- (2 << 16) + /* 32 bit */ \
- (3 << 13) + /* 7.81us (64ms/8192) */ \
- (0 << 10) + /* power down timer */ \
- (0 << 8) + /* full page */ \
- (1 << 7) + /* burst length */ \
- (0 << 0) /* precharge timer */
-
- .equ ESDCFG0_256MB, \
- (3 << 21) + /* tXP */ \
- (0 << 20) + /* tWTR */ \
- (2 << 18) + /* tRP */ \
- (1 << 16) + /* tMRD */ \
- (0 << 15) + /* tWR */ \
- (5 << 12) + /* tRAS */ \
- (1 << 10) + /* tRRD */ \
- (3 << 8) + /* tCAS */ \
- (2 << 4) + /* tRCD */ \
- (7 << 0) /* tRC */
-
- .equ ESDCTL0_256MB, \
- (1 << 31) + \
- (0 << 28) + \
- (0 << 27) + \
- (3 << 24) + /* 14 rows */ \
- (2 << 20) + /* 10 cols */ \
- (2 << 16) + \
- (4 << 13) + /* 3.91us (64ms/16384) */ \
- (0 << 10) + \
- (0 << 8) + \
- (1 << 7) + \
- (0 << 0)
+++ /dev/null
-/*
- *
- * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <asm/gpio.h>
-#include "qong_fpga.h"
-#include <watchdog.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-static void qong_fpga_reset(void)
-{
- gpio_set_value(QONG_FPGA_RST_PIN, 0);
- udelay(30);
- gpio_set_value(QONG_FPGA_RST_PIN, 1);
-
- udelay(300);
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_QONG_FPGA
- /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
- static const struct mxc_weimcs cs1 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(1, &cs1);
-
- /* setup pins for FPGA */
- mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
-
- /* FPGA reset Pin */
- /* rstn = 0 */
- gpio_direction_output(QONG_FPGA_RST_PIN, 0);
-
- /* set interrupt pin as input */
- gpio_direction_input(QONG_FPGA_IRQ_PIN);
-
- /* FPGA JTAG Interface */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
- gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
- gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
- gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
- gpio_direction_input(QONG_FPGA_TDO_PIN);
-#endif
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* setup pins for SPI (pmic) */
- mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
- mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
- mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
- mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
- mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
-
- /* Setup pins for USB2 Host */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
-
-#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
- mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
- mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
- mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
- mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
- mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
- mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
- mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
- mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
- mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
-
- mx31_set_gpr(MUX_PGP_UH2, 1);
-
- return 0;
-
-}
-
-int board_init(void)
-{
- /* Chip selects */
- /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
- /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
-
- /* board id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_QONG;
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- qong_fpga_init();
-
- return 0;
-}
-
-int board_late_init(void)
-{
- u32 val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
- /* Enable RTC battery */
- pmic_reg_read(p, REG_POWER_CTL0, &val);
- pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
- pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
-
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: DAVE/DENX Qong\n");
- return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_QONG_FPGA
- u32 tmp;
-
- tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
- printf("FPGA: ");
- printf("version register = %u.%u.%u\n",
- (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
-#endif
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
- return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
-#else
- return 0;
-#endif
-}
-
-#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
-static void board_nand_setup(void)
-{
- /* CS3: NAND 8-bit */
- static const struct mxc_weimcs cs3 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(3, &cs3);
-
- mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
-
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
-
- /* Make sure to reset the fpga else you cannot access NAND */
- qong_fpga_reset();
-
- /* Enable NAND flash */
- gpio_set_value(15, 1);
- gpio_set_value(14, 1);
- gpio_direction_output(15, 0);
- gpio_direction_input(16);
- gpio_direction_input(14);
-
-}
-
-int qong_nand_rdy(void *chip)
-{
- udelay(1);
- return gpio_get_value(16);
-}
-
-void qong_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- if (chip >= 0)
- gpio_set_value(15, 0);
- else
- gpio_set_value(15, 1);
-
-}
-
-void qong_nand_plat_init(void *chip)
-{
- struct nand_chip *nand = (struct nand_chip *)chip;
- nand->chip_delay = 20;
- nand->select_chip = qong_nand_select_chip;
- nand->options &= ~NAND_BUSWIDTH_16;
- board_nand_setup();
-}
-
-#endif
+++ /dev/null
-/*
- *
- * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef QONG_FPGA_H
-#define QONG_FPGA_H
-
-#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
-#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
-#define QONG_FPGA_PERIPH_SIZE (1 << 24)
-
-#define QONG_FPGA_TCK_PIN 26
-#define QONG_FPGA_TMS_PIN 25
-#define QONG_FPGA_TDI_PIN 8
-#define QONG_FPGA_TDO_PIN 7
-#define QONG_FPGA_RST_PIN 48
-#define QONG_FPGA_IRQ_PIN 40
-
-int qong_fpga_init(void);
-#endif /* QONG_FPGA_H */
-if TARGET_DA830EVM
-
-config SYS_BOARD
- default "da8xxevm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "da830evm"
-
-endif
-
if TARGET_DA850EVM
config SYS_BOARD
+++ /dev/null
-/*
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- *
- * Base on code from TI. Original Notices follow:
- *
- * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
- *
- * Modified for DA8xx EVM.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct pinmux_resource pinmuxes[] = {
-#ifdef CONFIG_SPI_FLASH
- PINMUX_ITEM(spi0_pins_base),
- PINMUX_ITEM(spi0_pins_scs0),
- PINMUX_ITEM(spi0_pins_ena),
-#endif
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(i2c0_pins),
-#ifdef CONFIG_USB_DA8XX
- PINMUX_ITEM(usb_pins),
-#endif
-#ifdef CONFIG_USE_NAND
- PINMUX_ITEM(emifa_pins),
- PINMUX_ITEM(emifa_pins_cs0),
- PINMUX_ITEM(emifa_pins_cs2),
- PINMUX_ITEM(emifa_pins_cs3),
-#endif
-#if defined(CONFIG_DRIVER_TI_EMAC)
- PINMUX_ITEM(emac_pins_rmii),
- PINMUX_ITEM(emac_pins_mdio),
- PINMUX_ITEM(emac_pins_rmii_clk_source),
-#endif
-#ifdef CONFIG_DAVINCI_MMC
- PINMUX_ITEM(mmc0_pins_8bit)
-#endif
-};
-
-static const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
- { DAVINCI_LPSC_SPI0 }, /* Serial Flash */
- { DAVINCI_LPSC_EMAC }, /* image download */
- { DAVINCI_LPSC_UART2 }, /* console */
- { DAVINCI_LPSC_GPIO },
-#ifdef CONFIG_DAVINCI_MMC
- { DAVINCI_LPSC_MMC_SD },
-#endif
-
-};
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .host_caps = MMC_MODE_8BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
- mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
-
- printf("%x\n", mmc_sd0.input_clk);
-
- /* Add slot-0 to mmc subsystem */
- return davinci_mmc_init(bis, &mmc_sd0);
-}
-#endif
-
-int board_init(void)
-{
-#ifndef CONFIG_USE_IRQ
- irq_init();
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
- /* EMIFA 100MHz clock select */
- writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
- &davinci_syscfg_regs->cfgchip3);
- /* NAND CS setup */
- writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(2) |
- DAVINCI_ABCR_WHOLD(0) |
- DAVINCI_ABCR_RSETUP(0) |
- DAVINCI_ABCR_RSTROBE(2) |
- DAVINCI_ABCR_RHOLD(0) |
- DAVINCI_ABCR_TA(2) |
- DAVINCI_ABCR_ASIZE_8BIT),
- &davinci_emif_regs->ab2cr);
-#endif
-
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /*
- * Power on required peripherals
- * ARM does not have access by default to PSC0 and PSC1
- * assuming here that the DSP bootloader has set the IOPU
- * such that PSC access is available to ARM
- */
- if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
- return 1;
-
- /* setup the SUSPSRC for ARM to control emulation suspend */
- writel(readl(&davinci_syscfg_regs->suspsrc) &
- ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
- DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART2),
- &davinci_syscfg_regs->suspsrc);
-
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
- return 1;
-
- /* enable the console UART */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
-
- return(0);
-}
-
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DRIVER_TI_EMAC)
-
-#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
-
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- u_int8_t mac_addr[6];
- u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
- struct eth_device *dev;
-
- /* Read Ethernet MAC address from EEPROM */
- if (dvevm_read_mac_address(mac_addr))
- /* set address env if not already set */
- davinci_sync_env_enetaddr(mac_addr);
-
- /* read the address back from env */
- if (!eth_getenv_enetaddr("ethaddr", mac_addr))
- return -1;
-
- /* enable the Ethernet switch in the 3 port PHY */
- if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
- switch_start_cmd, sizeof(switch_start_cmd))) {
- printf("Ethernet switch start failed!\n");
- return -1;
- }
-
- /* finally, initialise the driver */
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- dev = eth_get_dev();
-
- /* provide the resulting addr to the driver */
- memcpy(dev->enetaddr, mac_addr, 6);
- dev->write_hwaddr(dev);
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
+++ /dev/null
-if TARGET_DAVINCI_DM355EVM
-
-config SYS_BOARD
- default "dm355evm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm355evm"
-
-endif
+++ /dev/null
-DM355EVM BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm355evm/
-F: include/configs/davinci_dm355evm.h
-F: configs/davinci_dm355evm_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm355evm.o
+++ /dev/null
-#
-# Spectrum Digital DM355 EVM board
-# dm355evm board has 1 bank of 128 MB DDR RAM
-# Physical Address: 8000'0000 to 8800'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#include <net.h>
-#include <netdev.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * With the DM355 EVM, u-boot is *always* a third stage loader,
- * unless a JTAG debugger handles the first two stages:
- *
- * - 1st stage is ROM Boot Loader (RBL), which searches for a
- * second stage loader in one of three places based on SW7:
- * NAND (with MMC/SD fallback), MMC/SD, or UART.
- *
- * - 2nd stage is User Boot Loader (UBL), using at most 30KB
- * of on-chip SRAM, responsible for lowlevel init, and for
- * loading the third stage loader into DRAM.
- *
- * - 3rd stage, that's us!
- */
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* We expect the UBL to have handled "lowlevel init", which
- * involves setting up at least:
- * - clocks
- * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
- * + clock divisors for those PLLs
- * + LPSC_DDR module enabled
- * + LPSC_TIMER0 module (still) enabled
- * - EMIF
- * + DDR init and timings
- * + AEMIF timings (for NAND and DM9000)
- * - pinmux
- *
- * Some of that is repeated here, mostly as a precaution.
- */
-
- /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
- * could be too if we used A12 as a GPIO during NAND chipselect
- * (and Linux did too), letting us control the LED on A7/GPIO61.
- */
- REG(PINMUX2) = 0x0c08;
-
- /* UART0 may still be in SyncReset if we didn't boot from UART */
- davinci_enable_uart0();
-
- /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
- lpsc_on(DAVINCI_LPSC_TPCC);
- lpsc_on(DAVINCI_LPSC_TPTC0);
- lpsc_on(DAVINCI_LPSC_TPTC1);
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-
-static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long wbase = (unsigned long) this->IO_ADDR_W;
- unsigned long rbase = (unsigned long) this->IO_ADDR_R;
-
- if (chip == 1) {
- __set_bit(14, &wbase);
- __set_bit(14, &rbase);
- } else {
- __clear_bit(14, &wbase);
- __clear_bit(14, &rbase);
- }
- this->IO_ADDR_W = (void *)wbase;
- this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
- nand->select_chip = nand_dm355evm_select_chip;
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .input_clk = 108000000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_1,
-};
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-static struct davinci_mmc mmc_sd1 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
- .input_clk = 108000000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_1,
-};
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
- int err;
-
- /* Add slot-0 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd0);
- if (err)
- return err;
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
- /* Add slot-1 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd1);
-#endif
-
- return err;
-}
-#endif
+++ /dev/null
-if TARGET_DAVINCI_DM355LEOPARD
-
-config SYS_BOARD
- default "dm355leopard"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm355leopard"
-
-endif
+++ /dev/null
-DM355LEOPARD BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm355leopard/
-F: include/configs/davinci_dm355leopard.h
-F: configs/davinci_dm355leopard_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm355leopard.o
+++ /dev/null
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#include <net.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- struct davinci_gpio *gpio01_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
- struct davinci_gpio *gpio23_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
- struct davinci_gpio *gpio67_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
-
- gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* GIO 9 & 10 are used for IO */
- writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
-
- /* Interrupt set GIO 9 */
- writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
-
- /* set GIO 9 input */
- writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
-
- /* Both edge trigger GIO 9 */
- writel((readl(&gpio01_base->set_rising) | (1 << 9)),
- &gpio01_base->set_rising);
- writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
-
- /* output low */
- writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
- &gpio01_base->set_data);
-
- /* set GIO 10 output */
- writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
-
- /* output high */
- writel((readl(&gpio01_base->set_data) | (1 << 10)),
- &gpio01_base->set_data);
-
- /* set GIO 32 output */
- writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
-
- /* output High */
- writel((readl(&gpio23_base->set_data) | (1 << 0)),
- &gpio23_base->set_data);
-
- /* Enable UART1 MUX Lines */
- writel((readl(PINMUX0) & ~3), PINMUX0);
- writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
- writel((readl(&gpio67_base->set_data) | (1 << 6)),
- &gpio67_base->set_data);
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
+++ /dev/null
-if TARGET_DAVINCI_DM365EVM
-
-config SYS_BOARD
- default "dm365evm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm365evm"
-
-endif
+++ /dev/null
-DM365EVM BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm365evm/
-F: include/configs/davinci_dm365evm.h
-F: configs/davinci_dm365evm_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm365evm.o
+++ /dev/null
-#
-# Spectrum Digital DM365 EVM board
-# DM365 EVM board has 1 bank of 128 MB DDR RAM
-# Physical Address: 8000'0000 to 8800'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/gpio.h>
-#include <netdev.h>
-#include <asm/arch/davinci_misc.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-int board_eth_init(bd_t *bis)
-{
- uint8_t eeprom_enetaddr[6];
- int i;
- struct davinci_gpio *gpio1_base =
- (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
-
- /* Configure PINMUX 3 to enable EMAC pins */
- writel((readl(PINMUX3) | 0x1affff), PINMUX3);
-
- /* Configure GPIO20 as output */
- writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
-
- /* Toggle GPIO 20 */
- for (i = 0; i < 20; i++) {
- /* GPIO 20 low */
- writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
- &gpio1_base->out_data);
-
- udelay(1000);
-
- /* GPIO 20 high */
- writel((readl(&gpio1_base->out_data) | (1 << 20)),
- &gpio1_base->out_data);
- }
-
- /* Configure I2C pins so that EEPROM can be read */
- writel((readl(PINMUX3) | 0x01400000), PINMUX3);
-
- /* Read Ethernet MAC address from EEPROM */
- if (dvevm_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- davinci_emac_initialize();
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long wbase = (unsigned long) this->IO_ADDR_W;
- unsigned long rbase = (unsigned long) this->IO_ADDR_R;
-
- if (chip == 1) {
- __set_bit(14, &wbase);
- __set_bit(14, &rbase);
- } else {
- __clear_bit(14, &wbase);
- __clear_bit(14, &rbase);
- }
- this->IO_ADDR_W = (void *)wbase;
- this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
- nand->select_chip = nand_dm365evm_select_chip;
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
- .input_clk = 121500000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-static struct davinci_mmc mmc_sd1 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
- .input_clk = 121500000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
- int err;
-
- /* Add slot-0 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd0);
- if (err)
- return err;
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-#define PUPDCTL1 0x01c4007c
- /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
- writel((readl(PINMUX4) | 0x55400000), PINMUX4);
- writel((readl(PINMUX0) | 0x00010000), PINMUX0);
-
- /* Configure MMC/SD pins as pullup */
- writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
-
- /* Add slot-1 to mmc subsystem */
- err = davinci_mmc_init(bis, &mmc_sd1);
-#endif
-
- return err;
-}
-#endif
+++ /dev/null
-if TARGET_DAVINCI_DM6467EVM
-
-config SYS_BOARD
- default "dm6467evm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dm6467evm"
-
-endif
+++ /dev/null
-DM6467EVM BOARD
-#M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Orphan (since 2014-08)
-F: board/davinci/dm6467evm/
-F: include/configs/davinci_dm6467evm.h
-F: configs/davinci_dm6467evm_defconfig
-F: configs/davinci_dm6467Tevm_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dm6467evm.o
+++ /dev/null
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define REV_DM6467EVM 0
-#define REV_DM6467TEVM 1
-/*
- * get_board_rev() - setup to pass kernel board revision information
- * Returns:
- * bit[0-3] System clock frequency
- * 0000b - 27 MHz
- * 0001b - 33 MHz
- */
-u32 get_board_rev(void)
-{
-
-#ifdef CONFIG_DAVINCI_DM6467TEVM
- return REV_DM6467TEVM;
-#else
- return REV_DM6467EVM;
-#endif
-
-}
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
- lpsc_on(DAVINCI_DM646X_LPSC_UART0);
- lpsc_on(DAVINCI_DM646X_LPSC_I2C);
- lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-
- /* Enable GIO3.3V cells used for EMAC */
- REG(VDD3P3V_PWDN) = 0x80000c0;
-
- /* Select UART function on UART0 */
- REG(PINMUX0) &= ~(0x0000003f << 18);
- REG(PINMUX1) &= ~(0x00000003);
-
- return 0;
-}
-
-#if defined(CONFIG_DRIVER_TI_EMAC)
-
-int board_eth_init(bd_t *bis)
-{
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif
+++ /dev/null
-if TARGET_DAVINCI_DVEVM
-
-config SYS_BOARD
- default "dvevm"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_dvevm"
-
-endif
+++ /dev/null
-DVEVM BOARD
-#M: -
-S: Maintained
-F: board/davinci/dvevm/
-F: include/configs/davinci_dvevm.h
-F: configs/davinci_dvevm_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dvevm.o
-obj-y += board_init.o
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-
- mov pc, lr
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* Configure AEMIF pins (although this should be configured at boot time
- * with pull-up/pull-down resistors) */
- REG(PINMUX0) = 0x00000c1f;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
- lpsc_on(DAVINCI_LPSC_USB);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-int misc_init_r(void)
-{
- uint8_t video_mode;
- uint8_t eeprom_enetaddr[6];
-
- /* Read Ethernet MAC address from EEPROM if available. */
- if (dvevm_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- i2c_read(0x39, 0x00, 1, &video_mode, 1);
-
- setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
-
- return(0);
-}
-
-#ifdef CONFIG_USB_DAVINCI
-
-/* IO Expander I2C address and USB VBUS enable mask */
-#define IOEXP_I2C_ADDR 0x3A
-#define IOEXP_VBUSEN_MASK 1
-
-/*
- * This function enables USB VBUS by writting to IO expander using I2C.
- * Note that the I2C is already initialized at this stage. This
- * function is used by davinci specific USB wrapper code.
- */
-void enable_vbus(void)
-{
- uchar data; /* IO Expander data to enable VBUS */
-
- /* Write to IO expander to enable VBUS */
- i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
- data &= ~IOEXP_VBUSEN_MASK;
- i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
-}
-#endif
+++ /dev/null
-if TARGET_DAVINCI_SCHMOOGIE
-
-config SYS_BOARD
- default "schmoogie"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_schmoogie"
-
-endif
+++ /dev/null
-SCHMOOGIE BOARD
-#M: -
-S: Maintained
-F: board/davinci/schmoogie/
-F: include/configs/davinci_schmoogie.h
-F: configs/davinci_schmoogie_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := schmoogie.o
-obj-y += board_init.o
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-
- mov pc, lr
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* Configure AEMIF pins (although this should be configured at boot time
- * with pull-up/pull-down resistors) */
- REG(PINMUX0) = 0x00000c1f;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-int misc_init_r(void)
-{
- u_int8_t tmp[20], buf[10];
- int i = 0;
-
- /* Set serial number from UID chip */
- const u_int8_t crc_tbl[256] = {
- 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
- 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
- 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
- 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
- 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
- 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
- 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
- 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
- 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
- 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
- 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
- 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
- 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
- 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
- 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
- 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
- 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
- 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
- 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
- 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
- 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
- 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
- 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
- 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
- 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
- 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
- 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
- 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
- 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
- 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
- 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
- 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
- };
-
- /* Set serial number from UID chip */
- if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
- printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
- setenv("serial#", "FAILED");
- } else {
- if (buf[0] != 0x70) {
- /* Device Family Code */
- printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
- setenv("serial#", "FAILED");
- }
- }
- /* Now check CRC */
- tmp[0] = 0;
- for (i = 0; i < 8; i++)
- tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
-
- if (tmp[0] != 0) {
- printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
- setenv("serial#", "FAILED");
- } else {
- /* CRC OK, set "serial" env variable */
- sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
- buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
- setenv("serial#", (char *)&tmp[0]);
- }
-
- return(0);
-}
+++ /dev/null
-if TARGET_DAVINCI_SFFSDR
-
-config SYS_BOARD
- default "sffsdr"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_sffsdr"
-
-endif
+++ /dev/null
-SFFSDR BOARD
-#M: -
-S: Maintained
-F: board/davinci/sffsdr/
-F: include/configs/davinci_sffsdr.h
-F: configs/davinci_sffsdr_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sffsdr.o
-obj-y += board_init.o
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-
- mov pc, lr
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
-# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
-#
-# Lyrtech SFF SDR board (ARM926EJS) cpu
-#
-# SFF SDR board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 87FF'FFFF
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
-# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
-#
-# we load ourself to 8400'0000 to provide at least 32MB spacing
-# between us and the Integrity kernel image
-CONFIG_SYS_TEXT_BASE = 0x84000000
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
-#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
-
-#define INTEGRITY_SYSCFG_OFFSET 0x7E8
-#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
-#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* arch number of the board */
- gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-/* Read ethernet MAC address from Integrity data structure inside EEPROM.
- * Returns 1 if found, 0 otherwise.
- */
-static int sffsdr_read_mac_address(uint8_t *buf)
-{
- u_int32_t value, mac[2], address;
-
- /* Read Integrity data structure checkword. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- if (value != INTEGRITY_CHECKWORD_VALUE)
- return 0;
-
- /* Read SYSCFG structure offset. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- address = 0x800 + (int) value; /* Address of SYSCFG structure. */
-
- /* Read NET CONFIG structure offset. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
- address += 12; /* Address of NET INTERFACE CONFIG structure. */
-
- /* Read NET INTERFACE CONFIG 2 structure offset. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
- goto err;
- address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
- * CONFIG 2 structure. */
-
- /* Read MAC address. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
- goto err;
-
- buf[0] = mac[0] >> 24;
- buf[1] = mac[0] >> 16;
- buf[2] = mac[0] >> 8;
- buf[3] = mac[0];
- buf[4] = mac[1] >> 24;
- buf[5] = mac[1] >> 16;
-
- return 1; /* Found */
-
-err:
- printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
- return 0;
-}
-
-/* Platform dependent initialisation. */
-int misc_init_r(void)
-{
- uint8_t i2cbuf;
- uint8_t eeprom_enetaddr[6];
-
- /* EMIF-A CS3 configuration for FPGA. */
- REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
-
- /* Configure I2C switch (PCA9543) to enable channel 0. */
- i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
- if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
- CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
- printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
- return 1;
- }
-
- /* Read Ethernet MAC address from EEPROM if available. */
- if (sffsdr_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- return(0);
-}
+++ /dev/null
-if TARGET_DAVINCI_SONATA
-
-config SYS_BOARD
- default "sonata"
-
-config SYS_VENDOR
- default "davinci"
-
-config SYS_CONFIG_NAME
- default "davinci_sonata"
-
-endif
+++ /dev/null
-SONATA BOARD
-#M: -
-S: Maintained
-F: board/davinci/sonata/
-F: include/configs/davinci_sonata.h
-F: configs/davinci_sonata_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sonata.o
-obj-y += board_init.o
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
- * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
- * Visioneering if they reinvented the wheel once again to make sure :)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-.globl dv_board_init
-dv_board_init:
-#ifdef SONATA_BOARD_GPIOWP
- /* Set PINMUX0 to enable GPIO4 */
- ldr r0, _PINMUX0
- ldr r1, GPIO4_EN_MASK
- ldr r2, [r0]
- and r2, r2, r1
- str r2, [r0]
-
- /* Enable GPIO LPSC module */
- ldr r0, PTSTAT
-
-gpio_ptstat_loop1:
- ldr r2, [r0]
- tst r2, $0x00000001
- bne gpio_ptstat_loop1
-
- ldr r1, MDCTL_GPIO
- ldr r2, [r1]
- and r2, r2, $0xfffffff8
- orr r2, r2, $0x00000003
- str r2, [r1]
-
- orr r2, r2, $0x00000200
- str r2, [r1]
-
- ldr r1, PTCMD
- mov r2, $0x00000001
- str r2, [r1]
-
-gpio_ptstat_loop2:
- ldr r2, [r0]
- tst r2, $0x00000001
- bne gpio_ptstat_loop2
-
- ldr r0, MDSTAT_GPIO
-gpio_mdstat_loop:
- ldr r2, [r0]
- and r2, r2, $0x0000001f
- teq r2, $0x00000003
- bne gpio_mdstat_loop
-
- /* GPIO4 -> output */
- ldr r0, GPIO_DIR01
- mov r1, $0x10
- ldr r2, [r0]
- bic r2, r2, r0
- str r2, [r0]
-
- /* Set it to 0 (Write Protect) */
- ldr r0, GPIO_CLR_DATA01
- str r1, [r0]
-#endif
-
- mov pc, lr
-
-#ifdef SONATA_BOARD_GPIOWP
-.ltorg
-
-GPIO4_EN_MASK:
- .word 0xf77fffff
-MDCTL_GPIO:
- .word 0x01c41a68
-MDSTAT_GPIO:
- .word 0x01c41868
-GPIO_DIR01:
- .word 0x01c67010
-GPIO_CLR_DATA01:
- .word 0x01c6701c
-#endif
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier: GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- /* Configure AEMIF pins (although this should be configured at boot time
- * with pull-up/pull-down resistors) */
- REG(PINMUX0) = 0x00000c1f;
-
- davinci_errata_workarounds();
-
- /* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
- /* Powerup the DSP */
- dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
- davinci_enable_uart0();
- davinci_enable_emac();
- davinci_enable_i2c();
-
- lpsc_on(DAVINCI_LPSC_TIMER1);
- timer_init();
-
- return(0);
-}
-
-int misc_init_r(void)
-{
- uint8_t eeprom_enetaddr[6];
-
- /* Read Ethernet MAC address from EEPROM if available. */
- if (dvevm_read_mac_address(eeprom_enetaddr))
- davinci_sync_env_enetaddr(eeprom_enetaddr);
-
- return(0);
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-
-/* Set WP on deselect, write enable on select */
-static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
-{
-#define GPIO_SET_DATA01 0x01c67018
-#define GPIO_CLR_DATA01 0x01c6701c
-#define GPIO_NAND_WP (1 << 4)
-#ifdef SONATA_BOARD_GPIOWP
- if (chip < 0) {
- REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
- } else {
- REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
- }
-#endif
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
- nand->select_chip = nand_sonata_select_chip;
- return 0;
-}
-
-#endif /* CONFIG_NAND_DAVINCI */
};
const unsigned long iocsr_scan_chain3_table[] = {
- 0x0CC20D80,
+ 0x0C420D80,
0x0C3000FF,
0x0A804001,
0x07900000,
0x00001000,
0xA0000034,
0x0D000001,
- 0xC0680618,
- 0x45034071,
- 0x1A681A01,
- 0x806180D0,
- 0x34071C06,
- 0x01A034D0,
- 0x380D0000,
- 0x0820680E,
- 0x034D0340,
+ 0xC0680A28,
+ 0x45034030,
+ 0x12481A01,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A01450,
+ 0x280D0000,
+ 0x30C0680A,
+ 0x02490340,
0xD000001A,
- 0x0680E380,
+ 0x0680A280,
0x10040000,
0x00200000,
0x10040000,
0x00001000,
0xA0000034,
0x0D000001,
- 0xC0680618,
- 0x45034071,
- 0x1A681A01,
- 0x80E380D0,
- 0x34071C06,
+ 0xC0680A28,
+ 0x49034030,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
0x01A00040,
- 0x380D0002,
- 0x71C0680E,
- 0x034D0340,
- 0xD01A681A,
- 0x06806180,
+ 0x280D0002,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD00A281A,
+ 0x0680A280,
0x10040000,
0x00200000,
0x10040000,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
- 0x01C3A800,
+ 0x01C3A890,
0xAA0D4000,
0x01C3A800,
0x00040100,
0x2A835000,
0x0070EA00,
0x2A835000,
- 0x0070EA00,
+ 0x0070EA24,
0x2A835000,
0x0070EA00,
0x00010040,
0x14F3690D,
0x1A041414,
0x00D00000,
- 0x04864000,
- 0x69A47A01,
- 0x932CA3DA,
- 0xF459651E,
- 0x03549248,
+ 0x18864000,
+ 0x49247A06,
+ 0x9A28A3D7,
+ 0xF511451E,
+ 0x0356E388,
0x821A0000,
0x0000D000,
- 0x030C0680,
- 0xDA69A47A,
- 0x1E9228A3,
- 0x48F45965,
- 0x000354D3,
+ 0x05140680,
+ 0xD749247A,
+ 0x1E9A28A3,
+ 0x88F51145,
+ 0x00034EE3,
0x00080000,
0x00001000,
0x00080200,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
- 0x01C3A800,
+ 0x01C3A890,
0xAA0D4000,
0x01C3A800,
0x00040000,
0x2A835000,
0x0070EA00,
0x2A835000,
- 0x0070EA00,
+ 0x0070EA24,
0x2A835000,
0x0070EA00,
0x00015000,
0x14F3690D,
0x1A041414,
0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xE228A3D6,
- 0xF459651E,
- 0x034CD348,
- 0x821A0041,
+ 0x18864000,
+ 0x49247A06,
+ 0xEBCF23D7,
+ 0xF611451E,
+ 0x034E9248,
+ 0x821A038E,
0x0000D000,
0x00000680,
- 0xD669A47A,
- 0x1E9228A3,
- 0x48F45965,
- 0x00034492,
+ 0xD749247A,
+ 0x1E9BCF23,
+ 0x88F61145,
+ 0x00034EE3,
0x00080000,
0x00001000,
0x00080000,
0xAA0D4000,
0x01C3A800,
0xAA0D4000,
- 0x01C3A800,
+ 0x01C3A890,
0xAA0D4000,
0x01C3A800,
0x00040000,
0x14F3690D,
0x1A041414,
0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0x9228A3D6,
- 0xF459651E,
- 0x034CD348,
+ 0x18864000,
+ 0x49247A06,
+ 0x9A28A3D7,
+ 0xF431451E,
+ 0x034E9248,
0x821A0000,
0x0000D000,
0x00000680,
- 0xD659647A,
- 0x1E932CA3,
- 0x48F65965,
- 0x00034CD3,
+ 0xD749247A,
+ 0x1E9A28A3,
+ 0x88F61145,
+ 0x000356E3,
0x00080000,
0x00001000,
0x00080000,
0x14F1690D,
0x1A041414,
0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0x932CA3D6,
- 0xF659651E,
- 0x034CD348,
+ 0x08864000,
+ 0x49247A02,
+ 0xEBCF23DB,
+ 0xF431451E,
+ 0x0356E388,
0x821A0000,
0x0000D000,
0x00000680,
- 0xD669A47A,
- 0x1E9228A3,
- 0x48F45965,
- 0x00034CD3,
+ 0xD749247A,
+ 0x1EEBCF23,
+ 0x88F43E79,
+ 0x000356A2,
0x00080000,
0x00001000,
0x00080000,
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 375
+#define IO_DELAY_PER_OPA_TAP 312
#define IO_DLL_CHAIN_LENGTH 8
#define IO_DQDQS_OUT_PHASE_MAX 0
#define IO_DQS_EN_DELAY_MAX 31
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
-#define TINIT_CNTR0_VAL 82
+#define TINIT_CNTR0_VAL 99
#define TINIT_CNTR1_VAL 32
#define TINIT_CNTR2_VAL 32
-#define TRESET_CNTR0_VAL 82
+#define TRESET_CNTR0_VAL 99
#define TRESET_CNTR1_VAL 99
#define TRESET_CNTR2_VAL 10
const u32 ac_rom_init[] = {
0x20700000,
0x20780000,
- 0x10080221,
- 0x10080320,
+ 0x10080421,
+ 0x10080520,
0x10090044,
0x100a0008,
0x100b0000,
0x10380400,
- 0x10080241,
- 0x100802c0,
+ 0x10080441,
+ 0x100804c0,
0x100a0024,
0x10090010,
0x100b0000,
config SYS_VENDOR
default "embest"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "embestmx6boards"
+++ /dev/null
-if TARGET_ENBW_CMC
-
-config SYS_BOARD
- default "enbw_cmc"
-
-config SYS_VENDOR
- default "enbw"
-
-config SYS_CONFIG_NAME
- default "enbw_cmc"
-
-endif
+++ /dev/null
-ENBW_CMC BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/enbw/enbw_cmc/
-F: include/configs/enbw_cmc.h
-F: configs/enbw_cmc_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := enbw_cmc.o
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on da830evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <linux/ctype.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sdmmc_defs.h>
-#include <asm/arch/timer_defs.h>
-#include <asm/davinci_rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct lpsc_resource lpsc[] = {
- { DAVINCI_LPSC_AEMIF },
- { DAVINCI_LPSC_SPI1 },
- { DAVINCI_LPSC_ARM_RAM_ROM },
- { DAVINCI_LPSC_UART0 },
- { DAVINCI_LPSC_EMAC },
- { DAVINCI_LPSC_UART0 },
- { DAVINCI_LPSC_GPIO },
- { DAVINCI_LPSC_DDR_EMIF },
- { DAVINCI_LPSC_UART1 },
- { DAVINCI_LPSC_UART2 },
- { DAVINCI_LPSC_MMC_SD1 },
- { DAVINCI_LPSC_USB20 },
- { DAVINCI_LPSC_USB11 },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-static const struct pinmux_config enbw_pins[] = {
- { pinmux(0), 8, 0 },
- { pinmux(0), 8, 1 },
- { pinmux(0), 8, 2 },
- { pinmux(0), 8, 3 },
- { pinmux(0), 8, 4 },
- { pinmux(0), 8, 5 },
- { pinmux(1), 4, 0 },
- { pinmux(1), 8, 1 },
- { pinmux(1), 8, 2 },
- { pinmux(1), 8, 3 },
- { pinmux(1), 8, 4 },
- { pinmux(1), 8, 5 },
- { pinmux(1), 8, 6 },
- { pinmux(1), 4, 7 },
- { pinmux(2), 8, 0 },
- { pinmux(5), 1, 0 },
- { pinmux(5), 1, 3 },
- { pinmux(5), 1, 7 },
- { pinmux(5), 1, 5 },
- { pinmux(5), 1, 4 },
- { pinmux(5), 1, 3 },
- { pinmux(5), 1, 2 },
- { pinmux(5), 1, 1 },
- { pinmux(5), 1, 0 },
- { pinmux(6), 8, 0 },
- { pinmux(6), 8, 1 },
- { pinmux(6), 8, 2 },
- { pinmux(6), 8, 3 },
- { pinmux(6), 8, 4 },
- { pinmux(6), 8, 5 },
- { pinmux(6), 1, 7 },
- { pinmux(7), 8, 2 },
- { pinmux(7), 1, 3 },
- { pinmux(7), 8, 6 },
- { pinmux(7), 1, 7 },
- { pinmux(13), 8, 2 },
- { pinmux(13), 8, 3 },
- { pinmux(13), 8, 4 },
- { pinmux(13), 8, 5 },
- { pinmux(13), 8, 6 },
- { pinmux(13), 8, 7 },
- { pinmux(14), 8, 0 },
- { pinmux(14), 8, 1 },
- { pinmux(16), 8, 1 },
- { pinmux(16), 8, 2 },
- { pinmux(16), 8, 3 },
- { pinmux(16), 8, 4 },
- { pinmux(16), 8, 5 },
- { pinmux(16), 8, 6 },
- { pinmux(16), 8, 7 },
- { pinmux(17), 1, 0 },
- { pinmux(17), 1, 1 },
- { pinmux(17), 1, 2 },
- { pinmux(17), 8, 3 },
- { pinmux(17), 8, 4 },
- { pinmux(17), 8, 5 },
- { pinmux(17), 8, 6 },
- { pinmux(17), 8, 7 },
- { pinmux(18), 8, 0 },
- { pinmux(18), 8, 1 },
- { pinmux(18), 2, 2 },
- { pinmux(18), 2, 3 },
- { pinmux(18), 2, 4 },
- { pinmux(18), 8, 6 },
- { pinmux(18), 8, 7 },
- { pinmux(19), 8, 0 },
- { pinmux(19), 2, 1 },
- { pinmux(19), 2, 2 },
- { pinmux(19), 2, 3 },
- { pinmux(19), 2, 4 },
- { pinmux(19), 8, 5 },
- { pinmux(19), 8, 6 },
-};
-
-const struct pinmux_resource pinmuxes[] = {
- PINMUX_ITEM(emac_pins_mii),
- PINMUX_ITEM(emac_pins_mdio),
- PINMUX_ITEM(i2c0_pins),
- PINMUX_ITEM(emifa_pins_cs2),
- PINMUX_ITEM(emifa_pins_cs3),
- PINMUX_ITEM(emifa_pins_cs4),
- PINMUX_ITEM(emifa_pins_nand),
- PINMUX_ITEM(emifa_pins_nor),
- PINMUX_ITEM(spi1_pins_base),
- PINMUX_ITEM(spi1_pins_scs0),
- PINMUX_ITEM(uart1_pins_txrx),
- PINMUX_ITEM(uart2_pins_txrx),
- PINMUX_ITEM(uart2_pins_rtscts),
- PINMUX_ITEM(enbw_pins),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-struct gpio_config {
- char name[GPIO_NAME_SIZE];
- unsigned char bank;
- unsigned char gpio;
- unsigned char out;
- unsigned char value;
-};
-
-static const struct gpio_config enbw_gpio_config_hut[] = {
- { "RS485 enable", 8, 11, 1, 0 },
- { "RS485 iso", 8, 10, 1, 1 },
- { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
- { "W2HUT RS485 iso", 8, 8, 1, 1 },
-};
-
-static const struct gpio_config enbw_gpio_config_w[] = {
- { "RS485 enable", 8, 11, 1, 0 },
- { "RS485 iso", 8, 10, 1, 0 },
- { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
- { "W2HUT RS485 iso", 8, 8, 1, 0 },
-};
-
-static const struct gpio_config enbw_gpio_config[] = {
- { "LAN reset", 7, 15, 1, 1 },
- { "ena 11V PLC", 7, 14, 1, 0 },
- { "ena 1.5V PLC", 7, 13, 1, 0 },
- { "disable VBUS", 7, 12, 1, 1 },
- { "PLC reset", 6, 13, 1, 0 },
- { "LCM RS", 6, 12, 1, 0 },
- { "LCM R/W", 6, 11, 1, 0 },
- { "PLC pairing", 6, 10, 1, 1 },
- { "PLC MDIO CLK", 6, 9, 1, 0 },
- { "HK218", 6, 8, 1, 0 },
- { "HK218 Rx", 6, 1, 1, 1 },
- { "TPM reset", 6, 0, 1, 0 },
- { "Board-Type", 3, 9, 0, 0 },
- { "HW-ID0", 2, 7, 0, 0 },
- { "HW-ID1", 2, 6, 0, 0 },
- { "HW-ID2", 2, 3, 0, 0 },
- { "PV-IF RxD ena", 0, 15, 1, 1 },
- { "LED1", 1, 15, 1, 1 },
- { "LED2", 0, 1, 1, 1 },
- { "LED3", 0, 2, 1, 1 },
- { "LED4", 0, 3, 1, 1 },
- { "LED5", 0, 4, 1, 1 },
- { "LED6", 0, 5, 1, 0 },
- { "LED7", 0, 6, 1, 0 },
- { "LED8", 0, 14, 1, 0 },
- { "USER1", 0, 12, 0, 0 },
- { "USER2", 0, 13, 0, 0 },
-};
-
-#define PHY_POWER 0x0800
-
-static void enbw_cmc_switch(int port, int on)
-{
- const char *devname;
- unsigned char phyaddr = 3;
- unsigned char reg = 0;
- unsigned short data;
-
- if (port == 1)
- phyaddr = 2;
-
- devname = miiphy_get_current_dev();
- if (!devname) {
- printf("Error: no mii device\n");
- return;
- }
- if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
- printf("Error reading from the PHY addr=%02x reg=%02x\n",
- phyaddr, reg);
- return;
- }
-
- if (on)
- data &= ~PHY_POWER;
- else
- data |= PHY_POWER;
-
- if (miiphy_write(devname, phyaddr, reg, data) != 0) {
- printf("Error writing to the PHY addr=%02x reg=%02x\n",
- phyaddr, reg);
- return;
- }
-}
-
-static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz)
-{
- int i, ret;
-
- for (i = 0; i < sz; i++) {
- int gpio = conf[i].bank * 16 +
- conf[i].gpio;
-
- ret = gpio_request(gpio, conf[i].name);
- if (ret) {
- printf("%s: Could not get %s gpio\n", __func__,
- conf[i].name);
- return ret;
- }
-
- if (conf[i].out)
- gpio_direction_output(gpio,
- conf[i].value);
- else
- gpio_direction_input(gpio);
- }
-
- return 0;
-}
-
-int board_init(void)
-{
- int board_type, hw_id;
-
-#ifndef CONFIG_USE_IRQ
- irq_init();
-#endif
- /* address of boot parameters, not used as booting with DTT */
- gd->bd->bi_boot_params = 0;
-
- enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config));
-
- /* detect HW version */
- board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE);
- hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) +
- (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) +
- (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2);
- printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"),
- hw_id);
- if (board_type)
- enbw_cmc_init_gpio(enbw_gpio_config_w,
- ARRAY_SIZE(enbw_gpio_config_w));
- else
- enbw_cmc_init_gpio(enbw_gpio_config_hut,
- ARRAY_SIZE(enbw_gpio_config_hut));
-
- /* setup the SUSPSRC for ARM to control emulation suspend */
- clrbits_le32(&davinci_syscfg_regs->suspsrc,
- (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
- DAVINCI_SYSCFG_SUSPSRC_UART2));
-
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#define KSZ_CMD_READ 0x03
-#define KSZ_CMD_WRITE 0x02
-#define KSZ_ID 0x95
-
-static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val)
-{
- unsigned long flags = SPI_XFER_BEGIN;
- int ret;
- int cmd_len;
- u8 cmd[2];
-
- cmd[0] = KSZ_CMD_READ;
- cmd[1] = reg;
- cmd_len = 2;
-
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
- if (ret) {
- debug("Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
- return -EINVAL;
- }
- flags |= SPI_XFER_END;
- *val = 0;
- cmd_len = 1;
- ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags);
- if (ret) {
- debug("Failed to read (%zu bytes): %d\n",
- cmd_len, ret);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int enbw_cmc_switch_read_ident(struct spi_slave *spi)
-{
- int ret;
- u8 val;
-
- ret = enbw_cmc_switch_read(spi, 0, &val);
- if (ret) {
- debug("Failed to read\n");
- return -EINVAL;
- }
-
- if (val != KSZ_ID)
- return -EINVAL;
-
- return 0;
-}
-
-static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg,
- unsigned long val)
-{
- unsigned long flags = SPI_XFER_BEGIN;
- int ret;
- int cmd_len;
- u8 cmd[3];
-
- cmd[0] = KSZ_CMD_WRITE;
- cmd[1] = reg;
- cmd[2] = val;
- cmd_len = 3;
- flags |= SPI_XFER_END;
-
- ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
- if (ret) {
- debug("Failed to send command (%zu bytes): %d\n",
- cmd_len, ret);
- return -EINVAL;
- }
-
- udelay(1000);
- ret = enbw_cmc_switch_read(spi, reg, &cmd[0]);
- if (ret) {
- debug("Failed to read\n");
- return -EINVAL;
- }
- if (val != cmd[0])
- debug("warning: reg: %lx va: %x soll: %lx\n",
- reg, cmd[0], val);
-
- return 0;
-}
-
-static int enbw_cmc_eof(unsigned char *ptr)
-{
- if (*ptr == 0xff)
- return 1;
-
- return 0;
-}
-
-static char *enbw_cmc_getnewline(char *ptr)
-{
- while (*ptr != 0x0a) {
- ptr++;
- if (enbw_cmc_eof((unsigned char *)ptr))
- return NULL;
- }
-
- ptr++;
- return ptr;
-}
-
-static char *enbw_cmc_getvalue(char *ptr, int *value)
-{
- int end = 0;
-
- *value = -EINVAL;
-
- if (!isxdigit(*ptr))
- end = 1;
-
- while (end) {
- if ((*ptr == '#') || (*ptr == ';')) {
- ptr = enbw_cmc_getnewline(ptr);
- return ptr;
- }
- if (ptr != NULL) {
- if (isxdigit(*ptr)) {
- end = 0;
- } else if (*ptr == 0x0a) {
- ptr++;
- return ptr;
- } else {
- ptr++;
- if (enbw_cmc_eof((unsigned char *)ptr))
- return NULL;
- }
- } else {
- return NULL;
- }
- }
- *value = (int)simple_strtoul((const char *)ptr, &ptr, 16);
- ptr++;
- return ptr;
-}
-
-static struct spi_slave *enbw_cmc_init_spi(void)
-{
- struct spi_slave *spi;
- int ret;
-
- spi = spi_setup_slave(0, 0, 1000000, 0);
- if (!spi) {
- printf("Failed to set up slave\n");
- return NULL;
- }
-
- ret = spi_claim_bus(spi);
- if (ret) {
- debug("Failed to claim SPI bus: %d\n", ret);
- goto err_claim_bus;
- }
-
- ret = enbw_cmc_switch_read_ident(spi);
- if (ret)
- goto err_read;
-
- return spi;
-err_read:
- spi_release_bus(spi);
-err_claim_bus:
- spi_free_slave(spi);
- return NULL;
-}
-
-static int enbw_cmc_config_switch(unsigned long addr)
-{
- struct spi_slave *spi;
- char *ptr = (char *)addr;
- int value, reg;
- int ret = 0;
-
- debug("configure switch with file on addr: 0x%lx\n", addr);
-
- spi = enbw_cmc_init_spi();
- if (!spi)
- return -EINVAL;
-
- while (ptr != NULL) {
- ptr = enbw_cmc_getvalue(ptr, ®);
- if (ptr != NULL) {
- ptr = enbw_cmc_getvalue(ptr, &value);
- if ((ptr != NULL) && (value >= 0))
- if (enbw_cmc_switch_write(spi, reg, value)) {
- /* error writing to switch */
- ptr = NULL;
- ret = -EINVAL;
- }
- }
- }
-
- spi_release_bus(spi);
- spi_free_slave(spi);
- return ret;
-}
-
-static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned long addr;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- addr = simple_strtoul(argv[1], NULL, 16);
- enbw_cmc_config_switch(addr);
-
- return 0;
-}
-
-U_BOOT_CMD(switch, 3, 1, do_switch,
- "switch addr",
- "[addr]"
-);
-
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
- struct spi_slave *spi;
- const char *s;
- size_t len = 0;
- int config = 1;
-
- davinci_emac_mii_mode_sel(0);
-
- /* send a config file to the switch */
- s = hwconfig_subarg("switch", "config", &len);
- if (len) {
- unsigned long addr = simple_strtoul(s, NULL, 16);
-
- config = enbw_cmc_config_switch(addr);
- }
-
- if (config) {
- /*
- * no valid config file -> do we have some args in
- * hwconfig ?
- */
- if ((hwconfig_subarg("switch", "lan", &len)) ||
- (hwconfig_subarg("switch", "lmn", &len))) {
- /* If so start switch */
- spi = enbw_cmc_init_spi();
- if (spi) {
- if (enbw_cmc_switch_write(spi, 1, 0))
- config = 0;
- udelay(10000);
- if (enbw_cmc_switch_write(spi, 1, 1))
- config = 0;
- spi_release_bus(spi);
- spi_free_slave(spi);
- }
- } else {
- config = 0;
- }
- }
- if (!davinci_emac_initialize()) {
- printf("Error: Ethernet init failed!\n");
- return -1;
- }
-
- if (config) {
- if (hwconfig_subarg_cmp("switch", "lan", "on"))
- /* Switch port lan on */
- enbw_cmc_switch(1, 1);
- else
- enbw_cmc_switch(1, 0);
-
- if (hwconfig_subarg_cmp("switch", "lmn", "on"))
- /* Switch port pwl on */
- enbw_cmc_switch(2, 1);
- else
- enbw_cmc_switch(2, 0);
- }
-
- return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_PREBOOT
-static uchar kbd_magic_prefix[] = "key_magic_";
-static uchar kbd_command_prefix[] = "key_cmd_";
-
-struct kbd_data_t {
- char s1;
-};
-
-struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
-{
- /* read SW1 + SW2 */
- kbd_data->s1 = gpio_get_value(12) +
- (gpio_get_value(13) << 1);
- return kbd_data;
-}
-
-static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
-{
- char s1 = str[0];
-
- if (s1 >= '0' && s1 <= '9')
- s1 -= '0';
- else if (s1 >= 'a' && s1 <= 'f')
- s1 = s1 - 'a' + 10;
- else if (s1 >= 'A' && s1 <= 'F')
- s1 = s1 - 'A' + 10;
- else
- return -1;
-
- if (s1 != kbd_data->s1)
- return -1;
-
- return 0;
-}
-
-static char *key_match(const struct kbd_data_t *kbd_data)
-{
- char magic[sizeof(kbd_magic_prefix) + 1];
- char *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can be appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- kbd_magic_keys = getenv("magic_keys");
- if (kbd_magic_keys == NULL)
- kbd_magic_keys = "";
-
- /*
- * loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix = kbd_magic_keys; *suffix ||
- suffix == kbd_magic_keys; ++suffix) {
- sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
-
- if (compare_magic(kbd_data, getenv(magic)) == 0) {
- char cmd_name[sizeof(kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
- cmd = getenv(cmd_name);
-
- return cmd;
- }
- }
-
- return NULL;
-}
-#endif /* CONFIG_PREBOOT */
-
-int misc_init_r(void)
-{
- char *s, buf[32];
-#ifdef CONFIG_PREBOOT
- struct kbd_data_t kbd_data;
- /* Decode keys */
- char *str = strdup(key_match(get_keys(&kbd_data)));
- /* Set or delete definition */
- setenv("preboot", str);
- free(str);
-#endif /* CONFIG_PREBOOT */
-
- /* count all restarts, and save this in an environment var */
- s = getenv("restartcount");
-
- if (s)
- sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1);
- else
- strcpy(buf, "1");
-
- setenv("restartcount", buf);
- saveenv();
-
-#ifdef CONFIG_HW_WATCHDOG
- davinci_hw_watchdog_enable();
-#endif
-
- return 0;
-}
-
-struct cmc_led {
- char name[20];
- unsigned char bank;
- unsigned char gpio;
-};
-
-struct cmc_led led_table[] = {
- {"led1", 1, 15},
- {"led2", 0, 1},
- {"led3", 0, 2},
- {"led4", 0, 3},
- {"led5", 0, 4},
- {"led6", 0, 5},
- {"led7", 0, 6},
- {"led8", 0, 14},
-};
-
-static int cmc_get_led_state(struct cmc_led *led)
-{
- int value;
- int gpio = led->bank * 16 + led->gpio;
-
- value = gpio_get_value(gpio);
-
- return value;
-}
-
-static int cmc_set_led_state(struct cmc_led *led, int state)
-{
- int gpio = led->bank * 16 + led->gpio;
-
- gpio_set_value(gpio, state);
- return 0;
-}
-
-static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- struct cmc_led *led;
- int found = 0;
- int i = 0;
- int only_print = 0;
- int len = ARRAY_SIZE(led_table);
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if (argc < 3)
- only_print = 1;
-
- led = led_table;
- while ((!found) && (i < len)) {
- if (strcmp(argv[1], led->name) == 0) {
- found = 1;
- } else {
- led++;
- i++;
- }
- }
- if (!found)
- return cmd_usage(cmdtp);
-
- if (only_print) {
- if (cmc_get_led_state(led))
- printf("on\n");
- else
- printf("off\n");
-
- return 0;
- }
- if (strcmp(argv[2], "on") == 0)
- cmc_set_led_state(led, 1);
- else
- cmc_set_led_state(led, 0);
-
- return 0;
-}
-
-U_BOOT_CMD(led, 3, 1, do_led,
- "switch on/off board led",
- "[name] [on/off]"
-);
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
- davinci_hw_watchdog_reset();
-}
-#endif
-
-#if defined(CONFIG_POST)
-void arch_memory_failure_handle(void)
-{
- struct davinci_gpio *gpio = davinci_gpio_bank01;
- int state = 1;
-
- /*
- * if memor< failure blink with the LED 1,2 and 3
- * as we running from flash, we cannot use the gpio
- * api here, so access the gpio pin direct through
- * the gpio register.
- */
- while (1) {
- if (state) {
- clrbits_le32(&gpio->out_data, 0x80000006);
- state = 0;
- } else {
- setbits_le32(&gpio->out_data, 0x80000006);
- state = 1;
- }
- udelay(500);
- }
-}
-#endif
-
-ulong post_word_load(void)
-{
- struct davinci_rtc *reg =
- (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
-
- return in_be32(®->scratch2);
-}
-
-void post_word_store(ulong value)
-{
- struct davinci_rtc *reg =
- (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
-
- /*
- * write RTC kick register to enable write
- * for RTC Scratch registers. Cratch0 and 1 are
- * used for bootcount values.
- */
- writel(RTC_KICK0R_WE, ®->kick0r);
- writel(RTC_KICK1R_WE, ®->kick1r);
- out_be32(®->scratch2, value);
-}
-
-void board_gpio_init(void)
-{
- struct davinci_gpio *gpio = davinci_gpio_bank01;
-
- /*
- * set LED (gpio Interface not usable here)
- * set LED pins to output and state 0
- */
- clrbits_le32(&gpio->dir, 0x8000407e);
- clrbits_le32(&gpio->out_data, 0x8000407e);
- /* set LED 1 - 5 to state on */
- setbits_le32(&gpio->out_data, 0x8000001e);
-
- /*
- * set some gpio pins to low, this is needed early,
- * so we have no gpio Interface here
- * gpios:
- * 8[8] Mode PV select low
- * 8[9] Debug Rx Enable low
- * 8[10] Mode Select PV low
- * 8[11] Counter Interface RS485 Rx-Enable low
- */
- gpio = davinci_gpio_bank8;
- clrbits_le32(&gpio->dir, 0x00000f00);
- clrbits_le32(&gpio->out_data, 0x0f00);
-}
-
-int board_late_init(void)
-{
- cmc_set_led_state(&led_table[4], 0);
-
- return 0;
-}
-
-void show_boot_progress(int val)
-{
- switch (val) {
- case 1:
- cmc_set_led_state(&led_table[4], 1);
- break;
- case 4:
- cmc_set_led_state(&led_table[4], 0);
- break;
- case 15:
- cmc_set_led_state(&led_table[4], 1);
- break;
- }
-}
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd1 = {
- .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
- .input_clk = 228000000,
- .host_caps = MMC_MODE_4BIT,
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .version = MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
- mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID);
- /* Add slot-0 to mmc subsystem */
- return davinci_mmc_init(bis, &mmc_sd1);
-}
-#endif
+++ /dev/null
-if TARGET_OTC570
-
-config SYS_BOARD
- default "otc570"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "otc570"
-
-endif
+++ /dev/null
-OTC570 BOARD
-M: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-S: Maintained
-F: board/esd/otc570/
-F: include/configs/otc570.h
-F: configs/otc570_defconfig
-F: configs/otc570_dataflash_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += otc570.o
-obj-$(CONFIG_HAS_DATAFLASH) += partition.o
+++ /dev/null
-/*
- * (C) Copyright 2010-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <netdev.h>
-#ifdef CONFIG_LCD
-# include <atmel_lcdc.h>
-# include <lcd.h>
-# ifdef CONFIG_LCD_INFO
-# include <nand.h>
-# include <version.h>
-# endif
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-static int hw_rev = -1; /* hardware revision */
-
-int get_hw_rev(void)
-{
- if (hw_rev >= 0)
- return hw_rev;
-
- hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
- hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
-
- if (hw_rev == 15)
- hw_rev = 0;
-
- return hw_rev;
-}
-
-#ifdef CONFIG_CMD_NAND
-static void otc570_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
-
- /* Enable CS3 */
- csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa[0]);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
- &smc->cs[3].setup);
-
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
-
- writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(12),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif /* CONFIG_CMD_NAND */
-
-#ifdef CONFIG_MACB
-static void otc570_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
- at91_macb_hw_init();
-}
-#endif
-
-/*
- * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
- * controller debugging
- * The ET1100 is located at physical address 0x70000000
- * Its process memory is located at physical address 0x70001000
- */
-static void otc570_ethercat_hw_init(void)
-{
- at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
-
- /* Configure SMC EBI1_CS0 for EtherCAT */
- writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
- &smc1->cs[0].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
- AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
- &smc1->cs[0].pulse);
- writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
- &smc1->cs[0].cycle);
- /*
- * Configure behavior at external wait signal, byte-select mode, 16 bit
- * data bus width, none data float wait states and TDF optimization
- */
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
- AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
- AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
-
- /* Configure RDY/BSY */
- at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
-}
-
-#ifdef CONFIG_LCD
-/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
-vidinfo_t panel_info = {
- .vl_col = 640,
- .vl_row = 480,
- .vl_clk = 25175000,
- .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
-
- .vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
- .vl_tft = 1, /* 0 = passive, 1 = TFT */
- .vl_vsync_len = 1, /* Length of vertical sync in NOL */
- .vl_upper_margin = 35, /* Idle lines at the frame start */
- .vl_lower_margin = 5, /* Idle lines at the end of the frame */
- .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
- .vl_left_margin = 112, /* Idle cycles at the line beginning */
- .vl_right_margin = 1, /* Idle cycles at the end of the line */
-
- .mmio = ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
-}
-
-void lcd_disable(void)
-{
- at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
-}
-
-static void otc570_lcd_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
- at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
- at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
- at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
- at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
-
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
-}
-
-#ifdef CONFIG_LCD_INFO
-void lcd_show_board_info(void)
-{
- ulong dram_size, nand_size;
- int i;
- char temp[32];
-
- dram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- dram_size += gd->bd->bi_dram[i].size;
- nand_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
-
- lcd_printf("\n%s\n", U_BOOT_VERSION);
- lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate()));
- lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
- dram_size >> 20,
- nand_size >> 20 );
- lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
- lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
- lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
-}
-#endif /* CONFIG_LCD_INFO */
-#endif /* CONFIG_LCD */
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
- return rc;
-}
-
-int checkboard(void)
-{
- char str[32];
-
- puts("Board : esd ARM9 HMI Panel - OTC570");
- if (getenv_f("serial#", str, sizeof(str)) > 0) {
- puts(", serial# ");
- puts(str);
- }
- printf("\n");
- printf("Hardware-revision: 1.%d\n", get_hw_rev());
- printf("Mach-type : %lu\n", gd->bd->bi_arch_number);
- return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- char *str;
-
- char *serial = getenv("serial#");
- if (serial) {
- str = strchr(serial, '_');
- if (str && (strlen(str) >= 4)) {
- serialnr->high = (*(str + 1) << 8) | *(str + 2);
- serialnr->low = simple_strtoul(str + 3, NULL, 16);
- }
- } else {
- serialnr->high = 0;
- serialnr->low = 0;
- }
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
-{
- return hw_rev | 0x100;
-}
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- char str[64];
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
- at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
- /* Set USART_MODE = 1 (RS485) */
- writel(1, 0xFFF8C004);
-
- printf("USART0: ");
-
- if (getenv_f("usart0", str, sizeof(str)) == -1) {
- printf("No entry - assuming 1-wire\n");
- /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
- at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
- } else {
- if (strcmp(str, "1-wire") == 0) {
- printf("%s\n", str);
- at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
- } else if (strcmp(str, "rs485") == 0) {
- printf("%s\n", str);
- at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
- } else {
- printf("Wrong entry - assuming 1-wire ");
- printf("(valid values are '1-wire' or 'rs485')\n");
- at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
- }
- }
-#ifdef CONFIG_LCD
- printf("Display memory address: 0x%08lX\n", gd->fb_base);
-#endif
-
- return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-int board_early_init_f(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* enable all clocks */
- writel((1 << ATMEL_ID_PIOA) |
- (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOCDE) |
- (1 << ATMEL_ID_TWI) |
- (1 << ATMEL_ID_SPI0) |
-#ifdef CONFIG_LCD
- (1 << ATMEL_ID_LCDC) |
-#endif
- (1 << ATMEL_ID_UHP),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- /* arch number of OTC570-Board */
- gd->bd->bi_arch_number = MACH_TYPE_OTC570;
-
- return 0;
-}
-
-int board_init(void)
-{
- /* initialize ET1100 Controller */
- otc570_ethercat_hw_init();
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- otc570_nand_hw_init();
-#endif
-#ifdef CONFIG_HAS_DATAFLASH
- at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
- otc570_macb_hw_init();
-#endif
-#ifdef CONFIG_AT91_CAN
- at91_can_hw_init();
-#endif
-#ifdef CONFIG_USB_OHCI_NEW
- at91_uhp_hw_init();
-#endif
-#ifdef CONFIG_LCD
- otc570_lcd_hw_init();
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ulf Samuelsson <ulf@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <asm/hardware.h>
-#include <dataflash.h>
-
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
-};
-
-/* define the area offsets */
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
- {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
- {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
-};
+++ /dev/null
-if TARGET_IMA3_MX53
-
-config SYS_BOARD
- default "ima3-mx53"
-
-config SYS_VENDOR
- default "esg"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "ima3-mx53"
-
-endif
+++ /dev/null
-IMA3-MX53 BOARD
-#M: -
-S: Maintained
-F: board/esg/ima3-mx53/
-F: include/configs/ima3-mx53.h
-F: configs/ima3-mx53_defconfig
+++ /dev/null
-#
-# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
-#
-# Based on ti/evm/Makefile
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ima3-mx53.o
+++ /dev/null
-/*
- * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <asm/gpio.h>
-
-/* NOR flash configuration */
-#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
-#define IMA3_MX53_CS0GCR2 0
-#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
-#define IMA3_MX53_CS0RCR2 0
-#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
-#define IMA3_MX53_CS0WCR2 0
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void weim_nor_settings(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
- writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
- writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
- writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
- writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
- writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
- writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
- writel(0x0, &weim_regs->wcr);
-
- set_chipselect_size(CS0_128);
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
- NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- int ret;
-
- ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
-
- return ret;
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
-
-int board_mmc_init(bd_t *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
- gpio_direction_input(IMX_GPIO_NR(1, 1));
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-#endif
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
-
-static void setup_iomux_spi(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
- /* SSEL 0 */
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
- gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
-}
-
-int board_early_init_f(void)
-{
- /* configure I/O pads */
- setup_iomux_uart();
- setup_iomux_fec();
-
- weim_nor_settings();
-
- /* configure spi */
- setup_iomux_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- mxc_set_sata_internal_clock();
-
- return 0;
-}
-
-#if defined(CONFIG_RESET_PHY_R)
-#include <miiphy.h>
-
-void reset_phy(void)
-{
- unsigned short reg;
-
- /* reset the phy */
- miiphy_reset("FEC", CONFIG_PHY_ADDR);
-
- /* set hard link to 100Mbit, full-duplex */
- miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®);
- reg &= ~BMCR_ANENABLE;
- reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
- miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
-
- miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®);
- reg |= (1 << 5);
- miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
-}
-#endif
-
-int checkboard(void)
-{
- puts("Board: IMA3_MX53\n");
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2012
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM nor
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-/* IOMUX for RAM only */
-DATA 4 0x53fa8554 0x300020
-DATA 4 0x53fa8560 0x300020
-DATA 4 0x53fa8594 0x300020
-DATA 4 0x53fa8584 0x300020
-DATA 4 0x53fa8558 0x300040
-DATA 4 0x53fa8568 0x300040
-DATA 4 0x53fa8590 0x300040
-DATA 4 0x53fa857c 0x300040
-DATA 4 0x53fa8564 0x300040
-DATA 4 0x53fa8580 0x300040
-DATA 4 0x53fa8570 0x300220
-DATA 4 0x53fa8578 0x300220
-DATA 4 0x53fa872c 0x300000
-DATA 4 0x53fa8728 0x300000
-DATA 4 0x53fa871c 0x300000
-DATA 4 0x53fa8718 0x300000
-DATA 4 0x53fa8574 0x300020
-DATA 4 0x53fa8588 0x300020
-DATA 4 0x53fa855c 0x0
-DATA 4 0x53fa858c 0x0
-DATA 4 0x53fa856c 0x300040
-DATA 4 0x53fa86f0 0x300000
-DATA 4 0x53fa8720 0x300000
-DATA 4 0x53fa86fc 0x0
-DATA 4 0x53fa86f4 0x0
-DATA 4 0x53fa8714 0x0
-DATA 4 0x53fa8724 0x4000000
-
-/* DDR RAM */
-DATA 4 0x63fd9088 0x40404040
-DATA 4 0x63fd9090 0x40404040
-DATA 4 0x63fd907C 0x01420143
-DATA 4 0x63fd9080 0x01450146
-DATA 4 0x63fd9018 0x00111740
-DATA 4 0x63fd9000 0x84190000
-
-/* esdcfgX */
-DATA 4 0x63fd900C 0x9f5152e3
-DATA 4 0x63fd9010 0xb68e8a63
-DATA 4 0x63fd9014 0x01ff00db
-
-/* Read/Write command delay */
-DATA 4 0x63fd902c 0x000026d2
-
-/* Out of reset delays */
-DATA 4 0x63fd9030 0x00ff0e21
-
-/* ESDCTL ODT timing control */
-DATA 4 0x63fd9008 0x12273030
-
-/* ESDCTL power down control */
-DATA 4 0x63fd9004 0x0002002d
-
-/* Set registers in DDR memory chips */
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x052080b0
-DATA 4 0x63fd901c 0x04008040
-
-/* ESDCTL refresh control */
-DATA 4 0x63fd9020 0x00005800
-
-/* PHY ZQ HW control */
-DATA 4 0x63fd9040 0x05380003
-
-/* PHY ODT control */
-DATA 4 0x63fd9058 0x00022222
-
-/* start DDR3 */
-DATA 4 0x63fd901c 0x00000000
+++ /dev/null
-if TARGET_CPU9260
-
-config SYS_BOARD
- default "cpu9260"
-
-config SYS_VENDOR
- default "eukrea"
-
-config SYS_CONFIG_NAME
- default "cpu9260"
-
-endif
+++ /dev/null
-CPU9260 BOARD
-M: Eric Benard <eric@eukrea.com>
-S: Maintained
-F: board/eukrea/cpu9260/
-F: include/configs/cpu9260.h
-F: configs/cpu9260_defconfig
-F: configs/cpu9260_128M_defconfig
-F: configs/cpu9260_nand_defconfig
-F: configs/cpu9260_nand_128M_defconfig
-F: configs/cpu9G20_defconfig
-F: configs/cpu9G20_128M_defconfig
-F: configs/cpu9G20_nand_defconfig
-F: configs/cpu9G20_nand_128M_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net
-# Lead Tech Design <www.leadtechdesign.com>
-# Ilko Iliev <www.ronetix.at>
-#
-# (C) Copyright 2009
-# Eric Benard <eric@eukrea.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu9260.o
-obj-y += led.o
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- *
- * (C) Copyright 2009-2011
- * Eric Benard <eric@eukrea.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-#ifdef CONFIG_CMD_NAND
-static void cpu9260_nand_hw_init(void)
-{
- unsigned long csa;
- at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
- at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable CS3 */
- csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
-#if defined(CONFIG_CPU9G20)
- writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-#elif defined(CONFIG_CPU9260)
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-#endif
-
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-#ifdef CONFIG_MACB
-static void cpu9260_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
- at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
-
- at91_phy_reset();
-
- at91_macb_hw_init();
-}
-#endif
-
-int board_early_init_f(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- writel((1 << ATMEL_ID_PIOA) |
- (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC),
- &pmc->pcer);
-
- at91_seriald_hw_init();
-
- return 0;
-}
-
-
-int board_init(void)
-{
- /* arch number of the board */
-#if defined(CONFIG_CPU9G20)
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
-#elif defined(CONFIG_CPU9260)
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
-#endif
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_CMD_NAND
- cpu9260_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- cpu9260_macb_hw_init();
-#endif
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
-#endif
- return rc;
-}
+++ /dev/null
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
- STATUS_LED_OFF, STATUS_LED_OFF};
-
-void coloured_LED_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* Enable clock */
- writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
- at91_set_pio_output(CONFIG_RED_LED, 1);
- at91_set_pio_output(CONFIG_GREEN_LED, 1);
- at91_set_pio_output(CONFIG_YELLOW_LED, 1);
- at91_set_pio_output(CONFIG_BLUE_LED, 1);
-
- at91_set_pio_value(CONFIG_RED_LED, 1);
- at91_set_pio_value(CONFIG_GREEN_LED, 1);
- at91_set_pio_value(CONFIG_YELLOW_LED, 1);
- at91_set_pio_value(CONFIG_BLUE_LED, 1);
-}
-
-void red_led_off(void)
-{
- at91_set_pio_value(CONFIG_RED_LED, 1);
- saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void green_led_off(void)
-{
- at91_set_pio_value(CONFIG_GREEN_LED, 1);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
-}
-
-void yellow_led_off(void)
-{
- at91_set_pio_value(CONFIG_YELLOW_LED, 1);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
-}
-
-void blue_led_off(void)
-{
- at91_set_pio_value(CONFIG_BLUE_LED, 1);
- saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
-}
-
-void red_led_on(void)
-{
- at91_set_pio_value(CONFIG_RED_LED, 0);
- saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void green_led_on(void)
-{
- at91_set_pio_value(CONFIG_GREEN_LED, 0);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
-}
-
-void yellow_led_on(void)
-{
- at91_set_pio_value(CONFIG_YELLOW_LED, 0);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
-}
-
-void blue_led_on(void)
-{
- at91_set_pio_value(CONFIG_BLUE_LED, 0);
- saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
- blue_led_off();
- else
- blue_led_on();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
- red_led_off();
- else
- red_led_on();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
- green_led_off();
- else
- green_led_on();
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
- yellow_led_off();
- else
- yellow_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (STATUS_LED_BLUE == mask) {
- if (STATUS_LED_ON == state)
- blue_led_on();
- else
- blue_led_off();
- } else if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
- red_led_on();
- else
- red_led_off();
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == state)
- green_led_on();
- else
- green_led_off();
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == state)
- yellow_led_on();
- else
- yellow_led_off();
- }
-}
+++ /dev/null
-if TARGET_CPUAT91
-
-config SYS_BOARD
- default "cpuat91"
-
-config SYS_VENDOR
- default "eukrea"
-
-config SYS_CONFIG_NAME
- default "cpuat91"
-
-endif
+++ /dev/null
-CPUAT91 BOARD
-M: Eric Benard <eric@eukrea.com>
-S: Maintained
-F: board/eukrea/cpuat91/
-F: include/configs/cpuat91.h
-F: configs/cpuat91_defconfig
-F: configs/cpuat91_ram_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de. <http://lists.denx.de/mailman/listinfo/u-boot>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := cpuat91.o
+++ /dev/null
-/*
- * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com>
- * Eric Benard <eric@eukrea.com>
- * based on at91rm9200dk.c which is :
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* arch number of CPUAT91-Board */
- gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- at91_seriald_hw_init();
- return 0;
-}
-
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_AT91EMAC
-int board_eth_init(bd_t *bis)
-{
- return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-void i2c_init_board(void)
-{
- u32 pin;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-
- writel(1 << AT91_ID_PIOA, &pmc->pcer);
- pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
- writel(pin, &pio->pioa.idr);
- writel(pin, &pio->pioa.pudr);
- writel(pin, &pio->pioa.per);
- writel(pin, &pio->pioa.oer);
- writel(pin, &pio->pioa.sodr);
-}
-#endif
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6qarm2"
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6qsabreauto"
MX6QSABREAUTO BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6qsabreauto/
F: include/configs/mx6qsabreauto.h
F: configs/mx6dlsabreauto_defconfig
F: configs/mx6qsabreauto_defconfig
+F: configs/mx6qpsabreauto_defconfig
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6sabresd"
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6slevk"
MX6SLEVK BOARD
M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6slevk/
F: include/configs/mx6slevk.h
F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spl_defconfig
F: configs/mx6slevk_spinor_defconfig
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6sxsabresd"
-if TARGET_MX6UL_14X14_EVK
+if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK
config SYS_BOARD
default "mx6ul_14x14_evk"
config SYS_VENDOR
default "freescale"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6ul_14x14_evk"
F: board/freescale/mx6ul_14x14_evk/
F: include/configs/mx6ul_14x14_evk.h
F: configs/mx6ul_14x14_evk_defconfig
+F: configs/mx6ul_9x9_evk_defconfig
--- /dev/null
+How to use U-boot on Freescale MX6UL 14x14 EVK
+-----------------------------------------------
+
+- Build U-boot for MX6UL 14x14 EVK:
+
+$ make mrproper
+$ make mx6ul_14x14_evk_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+SW601: 0 0 1 0
+Sw602: 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+- Insert the micro SD card in the board, power it up and U-boot messages should
+come up.
#include <linux/sizes.h>
#include <mmc.h>
#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-fsl.h>
gpio_direction_output(IOX_OE, 1);
};
-void iox74lv_set(int index)
-{
- int i;
-
- gpio_direction_output(IOX_OE, 0);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
-
- if (i == index)
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
- else
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- for (i = 7; i >= 0; i--) {
- gpio_direction_output(IOX_SHCP, 0);
- gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
- udelay(500);
- gpio_direction_output(IOX_SHCP, 1);
- udelay(500);
- }
-
- gpio_direction_output(IOX_STCP, 0);
- udelay(500);
- /*
- * shift register will be output to pins
- */
- gpio_direction_output(IOX_STCP, 1);
-
- gpio_direction_output(IOX_OE, 1);
-};
-
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC and EEPROM */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
.gp = IMX_GPIO_NR(1, 29),
},
};
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ if (is_mx6ul_9x9_evk()) {
+ struct pmic *pfuze;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ pfuze = pmic_get("PFUZE3000");
+ ret = pmic_probe(pfuze);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
+ pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
+ reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®);
+ reg |= 0x1;
+ pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+
+ /* SW1B step ramp up time from 2us to 4us/25mV */
+ reg = 0x40;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
+
+ /* SW1B mode to APS/PFM */
+ reg = 0xc;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
+
+ /* SW1B standby voltage set to 0.975V */
+ reg = 0xb;
+ pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
+ }
+
+ return 0;
+}
+#endif
#endif
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_SIZE;
+ gd->ram_size = imx_ddr_size();
return 0;
}
MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
-int board_qspi_init(void)
+static int board_qspi_init(void)
{
/* Set the iomux */
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
add_board_boot_modes(board_boot_modes);
#endif
- return 0;
-}
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", "EVK");
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
+ if (is_mx6ul_9x9_evk())
+ setenv("board_rev", "9X9");
+ else
+ setenv("board_rev", "14X14");
+#endif
+
+ return 0;
}
int checkboard(void)
{
- puts("Board: MX6UL 14x14 EVK\n");
+ if (is_mx6ul_9x9_evk())
+ puts("Board: MX6UL 9x9 EVK\n");
+ else
+ puts("Board: MX6UL 14x14 EVK\n");
return 0;
}
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
-const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+ .grp_ddr_type = 0x00080000,
+#else
+ .grp_ddr_type = 0x000c0000,
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000000,
+ .dram_odt1 = 0x00000000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00003030,
+ .dram_sdqs1 = 0x00003030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x20000000,
+ .p0_mprddlctl = 0x4040484f,
+ .p0_mpwrdlctl = 0x40405247,
+ .mpzqlp2ctl = 0x1b4700c7,
+};
+
+static struct mx6_lpddr2_cfg mem_ddr = {
+ .mem_speed = 800,
+ .density = 2,
+ .width = 16,
+ .banks = 4,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .trcd_lp = 1500,
+ .trppb_lp = 1500,
+ .trpab_lp = 2000,
+ .trasmin = 4250,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 18,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .walat = 0,
+ .ralat = 5,
+ .mif3_mode = 3,
+ .bi_on = 1,
+ .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
+ .rtt_nom = 0,
+ .sde_to_rst = 0, /* LPDDR2 does not need this field */
+ .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
+ .ddr_type = DDR_TYPE_LPDDR2,
+};
+
+#else
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_reset = 0x00000030,
};
-const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
- .grp_addds = 0x00000030,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_ddrpke = 0x00000000,
- .grp_ddrmode = 0x00020000,
- .grp_ddr_type = 0x000c0000,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00070007,
.p0_mpdgctrl0 = 0x41490145,
.p0_mprddlctl = 0x40404546,
.p0_mpwrdlctl = 0x4040524D,
};
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0,
+ .cs_density = 20,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+};
+
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.trcmin = 4875,
.trasmin = 3500,
};
+#endif
static void ccgr_init(void)
{
static void spl_dram_init(void)
{
- struct mx6_ddr_sysinfo sysinfo = {
- .dsize = 0,
- .cs_density = 20,
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 2,
- .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .ddr_type = DDR_TYPE_DDR3,
- };
-
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
--- /dev/null
+if TARGET_MX7DSABRESD
+
+config SYS_BOARD
+ default "mx7dsabresd"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx7dsabresd"
+
+endif
--- /dev/null
+MX7DSABRESD BOARD
+M: Adrian Alonso <aalonso@freescale.com>
+S: Maintained
+F: board/freescale/mx7dsabresd
+F: include/configs/mx7dsabresd.h
+F: configs/mx7dsabresd_defconfig
--- /dev/null
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx7dsabresd.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f040404
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <i2c.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
+ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
+ .gp = IMX_GPIO_NR(4, 8),
+ },
+ .sda = {
+ .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
+ .gp = IMX_GPIO_NR(4, 9),
+ },
+};
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
+ MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#define IOX_SDI IMX_GPIO_NR(1, 9)
+#define IOX_STCP IMX_GPIO_NR(1, 12)
+#define IOX_SHCP IMX_GPIO_NR(1, 13)
+
+static iomux_v3_cfg_t const iox_pads[] = {
+ /* IOX_SDI */
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_STCP */
+ MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* IOX_SHCP */
+ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*
+ * PCIE_DIS_B --> Q0
+ * PCIE_RST_B --> Q1
+ * HDMI_RST_B --> Q2
+ * PERI_RST_B --> Q3
+ * SENSOR_RST_B --> Q4
+ * ENET_RST_B --> Q5
+ * PERI_3V3_EN --> Q6
+ * LCD_PWR_EN --> Q7
+ */
+enum qn {
+ PCIE_DIS_B,
+ PCIE_RST_B,
+ HDMI_RST_B,
+ PERI_RST_B,
+ SENSOR_RST_B,
+ ENET_RST_B,
+ PERI_3V3_EN,
+ LCD_PWR_EN,
+};
+
+enum qn_func {
+ qn_reset,
+ qn_enable,
+ qn_disable,
+};
+
+enum qn_level {
+ qn_low = 0,
+ qn_high = 1,
+};
+
+static enum qn_level seq[3][2] = {
+ {0, 1}, {1, 1}, {0, 0}
+};
+
+static enum qn_func qn_output[8] = {
+ qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
+ qn_enable
+};
+
+static void iox74lv_init(void)
+{
+ int i;
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+
+ for (i = 7; i >= 0; i--) {
+ gpio_direction_output(IOX_SHCP, 0);
+ gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
+ udelay(500);
+ gpio_direction_output(IOX_SHCP, 1);
+ udelay(500);
+ }
+ gpio_direction_output(IOX_STCP, 0);
+ udelay(500);
+ /*
+ * shift register will be output to pins
+ */
+ gpio_direction_output(IOX_STCP, 1);
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
+#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR},
+};
+
+static int mmc_get_env_devno(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 dev_no = (*p)->boot_dev_instance;
+
+ /* If not boot from sd/mmc, use default value */
+ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ if (dev_no == 2)
+ dev_no--;
+
+ return dev_no;
+}
+
+static int mmc_map_to_kernel_blk(int dev_no)
+{
+ if (dev_no == 1)
+ dev_no++;
+
+ return dev_no;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = 1; /* Assume uSDHC3 emmc is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc2 USDHC3 (eMMC)
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
+ gpio_direction_input(USDHC1_CD_GPIO);
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
+ gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
+ gpio_direction_output(USDHC3_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC3_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int check_mmc_autodetect(void)
+{
+ char *autodetect_str = getenv("mmcautodetect");
+
+ if ((autodetect_str != NULL) &&
+ (strcmp(autodetect_str, "yes") == 0)) {
+ return 1;
+ }
+
+ return 0;
+}
+
+static void mmc_late_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_devno();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ setenv_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+ mmc_map_to_kernel_blk(dev_no));
+ setenv("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
+
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_fec();
+
+ ret = fecmxc_initialize_multi(bis, 0,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+ if (ret)
+ printf("FEC1 MXC: %s:failed\n", __func__);
+
+ return ret;
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+ = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+ (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+ IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+ return set_clk_enet(ENET_125MHz);
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
+
+ iox74lv_init();
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("PFUZE3000");
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
+ pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
+ reg |= 0x1;
+ pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+
+ return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ mmc_late_init();
+#endif
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ /*
+ * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+ * since we use PMIC_PWRON to reset the board.
+ */
+ clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: i.MX7D SABRESD\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+static iomux_v3_cfg_t const usb_otg1_pads[] = {
+ MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_otg2_pads[] = {
+ MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ ARRAY_SIZE(usb_otg1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ ARRAY_SIZE(usb_otg2_pads));
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+#endif
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
+ /* levelling */
+ { DDRMC_CR97_WRLVL_EN, 97 },
+ { DDRMC_CR98_WRLVL_DL_0(0), 98 },
+ { DDRMC_CR99_WRLVL_DL_1(0), 99 },
+ { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
+ { DDRMC_CR105_RDLVL_DL_0(0), 105 },
+ { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
+ { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
+ /* AXI */
+ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
+ { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+ { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+ DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+ { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+ DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+ { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+ { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+ DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+ { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+ { DDRMC_CR126_PHY_RDLAT(8), 126 },
+ { DDRMC_CR132_WRLAT_ADJ(5) |
+ DDRMC_CR132_RDLAT_ADJ(6), 132 },
+ { DDRMC_CR137_PHYCTL_DL(2), 137 },
+ { DDRMC_CR138_PHY_WRLV_MXDL(256) |
+ DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
+ { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) |
+ DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+ { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
+ { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+ DDRMC_CR143_RDLV_MXDL(128), 143 },
+ { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+ DDRMC_CR144_PHY_RDLV_DLL(3) |
+ DDRMC_CR144_PHY_RDLV_EN(3), 144 },
+ { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
+ { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
+ { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
+ { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
+ { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+ DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
+
+ { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1) |
+ DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+ DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
+ { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
+ { DDRMC_CR158_TWR(6), 158 },
+ { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+ DDRMC_CR161_TODTH_WR(2), 161 },
+ /* end marker */
+ { 0, -1 }
+};
+
int dram_init(void)
{
- struct ddrmc_lvl_info lvl = {
- .wrlvl_reg_en = 1,
- .wrlvl_dl_0 = 0,
- .wrlvl_dl_1 = 0,
- .rdlvl_gt_reg_en = 1,
- .rdlvl_gt_dl_0 = 4,
- .rdlvl_gt_dl_1 = 4,
- .rdlvl_reg_en = 1,
- .rdlvl_dl_0 = 0,
- .rdlvl_dl_1 = 0,
- };
-
static const struct ddr3_jedec_timings timings = {
- .tinit = 5,
- .trst_pwron = 80000,
- .cke_inactive = 200000,
- .wrlat = 5,
- .caslat_lin = 12,
- .trc = 21,
- .trrd = 4,
- .tccd = 4,
- .tfaw = 20,
- .trp = 6,
- .twtr = 4,
- .tras_min = 15,
- .tmrd = 4,
- .trtp = 4,
- .tras_max = 28080,
- .tmod = 12,
- .tckesr = 4,
- .tcke = 3,
- .trcd_int = 6,
- .tdal = 12,
- .tdll = 512,
- .trp_ab = 6,
- .tref = 3120,
- .trfc = 44,
- .tpdex = 3,
- .txpdll = 10,
- .txsnr = 48,
- .txsr = 468,
- .cksrx = 5,
- .cksre = 5,
- .zqcl = 256,
- .zqinit = 512,
- .zqcs = 64,
- .ref_per_zq = 64,
- .aprebit = 10,
- .wlmrd = 40,
- .wldqsen = 25,
+ .tinit = 5,
+ .trst_pwron = 80000,
+ .cke_inactive = 200000,
+ .wrlat = 5,
+ .caslat_lin = 12,
+ .trc = 21,
+ .trrd = 4,
+ .tccd = 4,
+ .tbst_int_interval = 0,
+ .tfaw = 20,
+ .trp = 6,
+ .twtr = 4,
+ .tras_min = 15,
+ .tmrd = 4,
+ .trtp = 4,
+ .tras_max = 28080,
+ .tmod = 12,
+ .tckesr = 4,
+ .tcke = 3,
+ .trcd_int = 6,
+ .tras_lockout = 0,
+ .tdal = 12,
+ .bstlen = 0,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 3120,
+ .trfc = 44,
+ .tref_int = 0,
+ .tpdex = 3,
+ .txpdll = 10,
+ .txsnr = 48,
+ .txsr = 468,
+ .cksrx = 5,
+ .cksre = 5,
+ .freq_chg_en = 0,
+ .zqcl = 256,
+ .zqinit = 512,
+ .zqcs = 64,
+ .ref_per_zq = 64,
+ .zqcs_rotate = 0,
+ .aprebit = 10,
+ .cmd_age_cnt = 64,
+ .age_cnt = 64,
+ .q_fullness = 7,
+ .odt_rd_mapcs0 = 0,
+ .odt_wr_mapcs0 = 1,
+ .wlmrd = 40,
+ .wldqsen = 25,
};
- ddrmc_setup_iomux();
+ ddrmc_setup_iomux(NULL, 0);
- ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3);
+ ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
config SYS_VENDOR
default "gateworks"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "gw_ventana"
+++ /dev/null
-if TARGET_MX51_EFIKAMX
-
-config SYS_BOARD
- default "mx51_efikamx"
-
-config SYS_VENDOR
- default "genesi"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "mx51_efikamx"
-
-endif
+++ /dev/null
-MX51_EFIKAMX BOARD
-#M: -
-S: Maintained
-F: board/genesi/mx51_efikamx/
-F: include/configs/mx51_efikamx.h
-F: configs/mx51_efikamx_defconfig
-F: configs/mx51_efikasb_defconfig
+++ /dev/null
-#
-# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
-#
-# BASED ON: imx51evk
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := efikamx.o efikamx-usb.o
+++ /dev/null
-/*
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <usb.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx51.h>
-#include <asm/gpio.h>
-#include <usb/ehci-fsl.h>
-#include <usb/ulpi.h>
-#include <errno.h>
-
-#include "../../../drivers/usb/host/ehci.h"
-
-/*
- * Configure the USB H1 and USB H2 IOMUX
- */
-void setup_iomux_usb(void)
-{
- static const iomux_v3_cfg_t usb_h1_pads[] = {
- MX51_PAD_USBH1_CLK__USBH1_CLK,
- MX51_PAD_USBH1_DIR__USBH1_DIR,
- MX51_PAD_USBH1_STP__USBH1_STP,
- MX51_PAD_USBH1_NXT__USBH1_NXT,
- MX51_PAD_USBH1_DATA0__USBH1_DATA0,
- MX51_PAD_USBH1_DATA1__USBH1_DATA1,
- MX51_PAD_USBH1_DATA2__USBH1_DATA2,
- MX51_PAD_USBH1_DATA3__USBH1_DATA3,
- MX51_PAD_USBH1_DATA4__USBH1_DATA4,
- MX51_PAD_USBH1_DATA5__USBH1_DATA5,
- MX51_PAD_USBH1_DATA6__USBH1_DATA6,
- MX51_PAD_USBH1_DATA7__USBH1_DATA7,
- };
-
- static const iomux_v3_cfg_t usb_pads[] = {
- MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
- MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
- NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
- NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
- NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
- };
-
- imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
-
- if (machine_is_efikasb()) {
- static const iomux_v3_cfg_t usb_h2_pads[] = {
- MX51_PAD_EIM_A24__USBH2_CLK,
- MX51_PAD_EIM_A25__USBH2_DIR,
- MX51_PAD_EIM_A26__USBH2_STP,
- MX51_PAD_EIM_A27__USBH2_NXT,
- MX51_PAD_EIM_D16__USBH2_DATA0,
- MX51_PAD_EIM_D17__USBH2_DATA1,
- MX51_PAD_EIM_D18__USBH2_DATA2,
- MX51_PAD_EIM_D19__USBH2_DATA3,
- MX51_PAD_EIM_D20__USBH2_DATA4,
- MX51_PAD_EIM_D21__USBH2_DATA5,
- MX51_PAD_EIM_D22__USBH2_DATA6,
- MX51_PAD_EIM_D23__USBH2_DATA7,
- };
-
- imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
- ARRAY_SIZE(usb_h2_pads));
- }
-
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
-}
-
-/*
- * Enable devices connected to USB BUSes
- */
-static void efika_usb_enable_devices(void)
-{
- /* Enable Bluetooth */
- gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(2, 11), 1);
-
- /* Enable WiFi */
- gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
- udelay(10000);
-
- /* Reset the WiFi chip */
- gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(2, 10), 1);
-}
-
-/*
- * Reset USB HUB (or HUBs on EfikaSB)
- */
-static void efika_usb_hub_reset(void)
-{
- /* HUB reset */
- gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
- udelay(1000);
- gpio_set_value(IMX_GPIO_NR(1, 5), 0);
- udelay(1000);
- gpio_set_value(IMX_GPIO_NR(1, 5), 1);
-}
-
-/*
- * Reset USB PHY (or PHYs on EfikaSB)
- */
-static void efika_usb_phy_reset(void)
-{
- /* SMSC 3317 PHY reset */
- gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
- udelay(1000);
- gpio_set_value(IMX_GPIO_NR(2, 9), 1);
-}
-
-static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
- iomux_v3_cfg_t stp_pad_gpio,
- iomux_v3_cfg_t stp_pad_usb)
-{
- int ret;
- struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
- struct ulpi_viewport ulpi_vp;
-
- imx_iomux_v3_setup_pad(stp_pad_gpio);
- gpio_direction_output(stp_gpio, 0);
- udelay(1000);
- gpio_set_value(stp_gpio, 1);
- udelay(1000);
-
- imx_iomux_v3_setup_pad(stp_pad_usb);
- udelay(10000);
-
- ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
- ulpi_vp.port_num = 0;
-
- ret = ulpi_init(&ulpi_vp);
- if (ret) {
- printf("Efika USB ULPI initialization failed\n");
- return;
- }
-
- /* ULPI set flags */
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
- ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
- ULPI_OTG_EXTVBUSIND);
- ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
- ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
- ULPI_FC_SUSPENDM);
- ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
-
- /* Set VBus */
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- /*
- * Set VBusChrg
- *
- * NOTE: This violates USB specification, but otherwise, USB on Efika
- * doesn't work.
- */
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
-}
-
-int board_ehci_hcd_init(int port)
-{
- /* Init iMX51 EHCI */
- efika_usb_phy_reset();
- efika_usb_hub_reset();
- efika_usb_enable_devices();
-
- return 0;
-}
-
-/* This overrides a weak function */
-void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
- uint32_t *reg)
-{
- uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT);
- struct usb_ehci *ehci = (struct usb_ehci *)port;
- struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
- struct ulpi_viewport ulpi_vp;
-
- ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
- ulpi_vp.port_num = 0;
-
- ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
-
- mdelay(50);
-
- /* terminate the reset */
- *reg = ehci_readl(status_reg);
- *reg |= EHCI_PS_PE;
-}
-
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
-{
- uint32_t tmp;
-
- if (port == 0) {
- /* Adjust UTMI PHY frequency to 24MHz */
- tmp = readl(OTG_BASE_ADDR + 0x80c);
- tmp = (tmp & ~0x3) | 0x01;
- writel(tmp, OTG_BASE_ADDR + 0x80c);
- } else if (port == 1) {
- efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
- MX51_PAD_USBH1_STP__GPIO1_27,
- MX51_PAD_USBH1_STP__USBH1_STP);
- } else if ((port == 2) && machine_is_efikasb()) {
- efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
- MX51_PAD_EIM_A26__GPIO2_20,
- MX51_PAD_EIM_A26__USBH2_STP);
- }
-
- if (port)
- mdelay(10);
-}
-
-/*
- * Ethernet on the Smarttop is on the USB bus. Rather than give an error about
- * "CPU Net Initialization Failed", just pass this test since no other settings
- * are required. Smartbook doesn't have built-in Ethernet but we will let it
- * pass anyway considering someone may have plugged in a USB stick and all
- * they need to do is run "usb start".
- */
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx51.h>
-#include <asm/gpio.h>
-#include <asm/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/imx-common/spi.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc13892.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Compile-time error checking
- */
-#ifndef CONFIG_MXC_SPI
-#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
-#endif
-
-/*
- * Board revisions
- *
- * Note that we get these revisions here for convenience, but we only set
- * up for the production model Smarttop (1.3) and Smartbook (2.0).
- *
- */
-#define EFIKAMX_BOARD_REV_11 0x1
-#define EFIKAMX_BOARD_REV_12 0x2
-#define EFIKAMX_BOARD_REV_13 0x3
-#define EFIKAMX_BOARD_REV_14 0x4
-
-#define EFIKASB_BOARD_REV_13 0x1
-#define EFIKASB_BOARD_REV_20 0x2
-
-/*
- * Board identification
- */
-static u32 get_mx_rev(void)
-{
- u32 rev = 0;
- /*
- * Retrieve board ID:
- *
- * gpio: 16 17 11
- * ==============
- * r1.1: 1+ 1 1
- * r1.2: 1 1 0
- * r1.3: 1 0 1
- * r1.4: 1 0 0
- *
- * + note: r1.1 does not strap this pin properly so it needs to
- * be hacked or ignored.
- */
-
- /* set to 1 in order to get correct value on board rev 1.1 */
- gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
- gpio_direction_input(IMX_GPIO_NR(3, 11));
- gpio_direction_input(IMX_GPIO_NR(3, 16));
- gpio_direction_input(IMX_GPIO_NR(3, 17));
-
- rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
- rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
- rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
-
- return (~rev & 0x7) + 1;
-}
-
-static iomux_v3_cfg_t const efikasb_revision_pads[] = {
- MX51_PAD_EIM_CS3__GPIO2_28,
- MX51_PAD_EIM_CS4__GPIO2_29,
-};
-
-static inline u32 get_sb_rev(void)
-{
- u32 rev = 0;
-
- imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
- ARRAY_SIZE(efikasb_revision_pads));
- gpio_direction_input(IMX_GPIO_NR(2, 28));
- gpio_direction_input(IMX_GPIO_NR(2, 29));
-
- rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
- rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
-
- return rev;
-}
-
-inline uint32_t get_efikamx_rev(void)
-{
- if (machine_is_efikamx())
- return get_mx_rev();
- else if (machine_is_efikasb())
- return get_sb_rev();
-}
-
-u32 get_board_rev(void)
-{
- return get_cpu_rev() | (get_efikamx_rev() << 8);
-}
-
-/*
- * DRAM initialization
- */
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-/*
- * UART configuration
- */
-static iomux_v3_cfg_t const efikamx_uart_pads[] = {
- MX51_PAD_UART1_RXD__UART1_RXD,
- MX51_PAD_UART1_TXD__UART1_TXD,
- MX51_PAD_UART1_RTS__UART1_RTS,
- MX51_PAD_UART1_CTS__UART1_CTS,
-};
-
-/*
- * SPI configuration
- */
-static iomux_v3_cfg_t const efikamx_spi_pads[] = {
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
- MX51_PAD_CSPI1_SS0__GPIO4_24,
- MX51_PAD_CSPI1_SS1__GPIO4_25,
- MX51_PAD_GPIO1_6__GPIO1_6,
-};
-
-#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
-#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
-
-/*
- * PMIC configuration
- */
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 1) ? 121 : -1;
-}
-
-static void power_init(void)
-{
- unsigned int val;
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(CONFIG_FSL_PMIC_BUS);
- if (ret)
- return;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return;
-
- /* Write needed to Power Gate 2 register */
- pmic_reg_read(p, REG_POWER_MISC, &val);
- val &= ~PWGT2SPIEN;
- pmic_reg_write(p, REG_POWER_MISC, val);
-
- /* Externally powered */
- pmic_reg_read(p, REG_CHARGE, &val);
- val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
- pmic_reg_write(p, REG_CHARGE, val);
-
- /* power up the system first */
- pmic_reg_write(p, REG_POWER_MISC, PWUP);
-
- /* Set core voltage to 1.1V */
- pmic_reg_read(p, REG_SW_0, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
- pmic_reg_write(p, REG_SW_0, val);
-
- /* Setup VCC (SW2) to 1.25 */
- pmic_reg_read(p, REG_SW_1, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(p, REG_SW_1, val);
-
- /* Setup 1V2_DIG1 (SW3) to 1.25 */
- pmic_reg_read(p, REG_SW_2, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(p, REG_SW_2, val);
- udelay(50);
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, &mxc_ccm->cacrr);
-
- /* Set switchers in Auto in NORMAL mode & STANDBY mode */
- /* Setup the switcher mode for SW1 & SW2*/
- pmic_reg_read(p, REG_SW_4, &val);
- val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
- (SWMODE_MASK << SWMODE2_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(p, REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- pmic_reg_read(p, REG_SW_5, &val);
- val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
- (SWMODE_MASK << SWMODE4_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
- pmic_reg_write(p, REG_SW_5, val);
-
- /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
- pmic_reg_read(p, REG_SETTING_0, &val);
- val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
- val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
- pmic_reg_write(p, REG_SETTING_0, val);
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- pmic_reg_read(p, REG_SETTING_1, &val);
- val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
- val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
- pmic_reg_write(p, REG_SETTING_1, val);
-
- /* Enable VGEN1, VGEN2, VDIG, VPLL */
- pmic_reg_read(p, REG_MODE_0, &val);
- val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
- pmic_reg_write(p, REG_MODE_0, val);
-
- /* Configure VGEN3 and VCAM regulators to use external PNP */
- val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(p, REG_MODE_1, val);
- udelay(200);
-
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
- VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- pmic_reg_read(p, REG_POWER_CTL2, &val);
- val |= WDIRESET;
- pmic_reg_write(p, REG_POWER_CTL2, val);
-
- udelay(2500);
-}
-#else
-static inline void power_init(void) { }
-#endif
-
-/*
- * MMC configuration
- */
-#ifdef CONFIG_FSL_ESDHC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR},
- {MMC_SDHC2_BASE_ADDR},
-};
-
-static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- MX51_PAD_GPIO1_1__SD1_WP,
-};
-
-#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
-
-static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
- MX51_PAD_GPIO1_0__SD1_CD,
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
-};
-
-#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
-#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
-
-static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
- MX51_PAD_SD2_CMD__SD2_CMD,
- MX51_PAD_SD2_CLK__SD2_CLK,
- MX51_PAD_SD2_DATA0__SD2_DATA0,
- MX51_PAD_SD2_DATA1__SD2_DATA1,
- MX51_PAD_SD2_DATA2__SD2_DATA2,
- MX51_PAD_SD2_DATA3__SD2_DATA3,
- MX51_PAD_GPIO1_7__SD2_WP,
- MX51_PAD_GPIO1_8__SD2_CD,
-};
-
-#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
-#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
-
-static inline uint32_t efikamx_mmc_getcd(u32 base)
-{
- if (base == MMC_SDHC1_BASE_ADDR)
- if (machine_is_efikamx())
- return EFIKAMX_SDHC1_CD;
- else
- return EFIKASB_SDHC1_CD;
- else
- return EFIKASB_SDHC2_CD;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
- int ret = !gpio_get_value(cd);
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
-
- /*
- * All Efika MX boards use eSDHC1 with a common write-protect GPIO
- */
- imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
- ARRAY_SIZE(efikamx_sdhc1_pads));
- gpio_direction_input(EFIKAMX_SDHC1_WP);
-
- /*
- * Smartbook and Smarttop differ on the location of eSDHC1
- * carrier-detect GPIO
- */
- if (machine_is_efikamx()) {
- imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
- gpio_direction_input(EFIKAMX_SDHC1_CD);
- } else if (machine_is_efikasb()) {
- imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
- gpio_direction_input(EFIKASB_SDHC1_CD);
- }
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-
- if (machine_is_efikasb()) {
-
- imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
- ARRAY_SIZE(efikasb_sdhc2_pads));
- gpio_direction_input(EFIKASB_SDHC2_CD);
- gpio_direction_input(EFIKASB_SDHC2_WP);
- if (!ret)
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
- }
-
- return ret;
-}
-#endif
-
-/*
- * PATA
- */
-static iomux_v3_cfg_t const efikamx_pata_pads[] = {
- MX51_PAD_NANDF_WE_B__PATA_DIOW,
- MX51_PAD_NANDF_RE_B__PATA_DIOR,
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
- MX51_PAD_NANDF_CLE__PATA_RESET_B,
- MX51_PAD_NANDF_WP_B__PATA_DMACK,
- MX51_PAD_NANDF_RB0__PATA_DMARQ,
- MX51_PAD_NANDF_RB1__PATA_IORDY,
- MX51_PAD_GPIO_NAND__PATA_INTRQ,
- MX51_PAD_NANDF_CS2__PATA_CS_0,
- MX51_PAD_NANDF_CS3__PATA_CS_1,
- MX51_PAD_NANDF_CS4__PATA_DA_0,
- MX51_PAD_NANDF_CS5__PATA_DA_1,
- MX51_PAD_NANDF_CS6__PATA_DA_2,
- MX51_PAD_NANDF_D15__PATA_DATA15,
- MX51_PAD_NANDF_D14__PATA_DATA14,
- MX51_PAD_NANDF_D13__PATA_DATA13,
- MX51_PAD_NANDF_D12__PATA_DATA12,
- MX51_PAD_NANDF_D11__PATA_DATA11,
- MX51_PAD_NANDF_D10__PATA_DATA10,
- MX51_PAD_NANDF_D9__PATA_DATA9,
- MX51_PAD_NANDF_D8__PATA_DATA8,
- MX51_PAD_NANDF_D7__PATA_DATA7,
- MX51_PAD_NANDF_D6__PATA_DATA6,
- MX51_PAD_NANDF_D5__PATA_DATA5,
- MX51_PAD_NANDF_D4__PATA_DATA4,
- MX51_PAD_NANDF_D3__PATA_DATA3,
- MX51_PAD_NANDF_D2__PATA_DATA2,
- MX51_PAD_NANDF_D1__PATA_DATA1,
- MX51_PAD_NANDF_D0__PATA_DATA0,
-};
-
-/*
- * EHCI USB
- */
-#ifdef CONFIG_CMD_USB
-extern void setup_iomux_usb(void);
-#else
-static inline void setup_iomux_usb(void) { }
-#endif
-
-/*
- * LED configuration
- *
- * Smarttop LED pad config is done in the DCD
- *
- */
-#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
-#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
-#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
-
-static iomux_v3_cfg_t const efikasb_led_pads[] = {
- MX51_PAD_GPIO1_3__GPIO1_3,
- MX51_PAD_EIM_CS0__GPIO2_25,
-};
-
-#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
-#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
-
-/*
- * Board initialization
- */
-int board_early_init_f(void)
-{
- if (machine_is_efikasb()) {
- imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
- ARRAY_SIZE(efikasb_led_pads));
- gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
- gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
- } else if (machine_is_efikamx()) {
- /*
- * Set up GPIO directions for LEDs.
- * IOMUX has been done in the DCD already.
- * Turn the red LED on for pre-relocation code.
- */
- gpio_direction_output(EFIKAMX_LED_BLUE, 0);
- gpio_direction_output(EFIKAMX_LED_GREEN, 0);
- gpio_direction_output(EFIKAMX_LED_RED, 1);
- }
-
- /*
- * Both these pad configurations for UART and SPI are kind of redundant
- * since they are the Power-On Defaults for the i.MX51. But, it seems we
- * should make absolutely sure that they are set up correctly.
- */
- imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
- ARRAY_SIZE(efikamx_uart_pads));
- imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
- ARRAY_SIZE(efikamx_spi_pads));
-
- /* not technically required for U-Boot operation but do it anyway. */
- gpio_direction_input(EFIKAMX_PMIC_IRQ);
- /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
- gpio_direction_output(EFIKAMX_SPI_SS0, 0);
- gpio_direction_output(EFIKAMX_SPI_SS1, 1);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- if (machine_is_efikamx()) {
- /*
- * Set up Blue LED for "In U-Boot" status.
- * We're all relocated and ready to U-Boot!
- */
- gpio_set_value(EFIKAMX_LED_RED, 0);
- gpio_set_value(EFIKAMX_LED_GREEN, 0);
- gpio_set_value(EFIKAMX_LED_BLUE, 1);
- }
-
- power_init();
-
- imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
- ARRAY_SIZE(efikamx_pata_pads));
- setup_iomux_usb();
-
- return 0;
-}
-
-int checkboard(void)
-{
- u32 rev = get_efikamx_rev();
-
- printf("Board: Genesi Efika MX ");
- if (machine_is_efikamx())
- printf("Smarttop (1.%i)\n", rev & 0xf);
- else if (machine_is_efikasb())
- printf("Smartbook\n");
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Pegatron Corporation
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * BASED ON: imx51evk
- *
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-/*
- * Essential GPIO settings to be done as early as possible
- * PCBIDn pad settings are all the defaults except #2 which needs HVE off
- */
-DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
-DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
-DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
-DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
-DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
-DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
-DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-
-/* DDR bus IOMUX PAD settings */
-DATA 4 0x73fa850c 0x20c5 # SDODT1
-DATA 4 0x73fa8510 0x20c5 # SDODT0
-DATA 4 0x73fa84ac 0xc5 # SDWE
-DATA 4 0x73fa84b0 0xc5 # SDCKE0
-DATA 4 0x73fa84b4 0xc5 # SDCKE1
-DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
-DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
-DATA 4 0x73fa882c 0x2 # DRAM_B4
-DATA 4 0x73fa88a4 0x2 # DRAM_B0
-DATA 4 0x73fa88ac 0x2 # DRAM_B1
-DATA 4 0x73fa88b8 0x2 # DRAM_B2
-DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
-DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
-DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
-DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-
-/*
- * Setting DDR for micron
- * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
- * CAS=3 BL=4
- */
-/* ESDCTL_ESDCTL0 */
-DATA 4 0x83fd9000 0x82a20000
-/* ESDCTL_ESDCTL1 */
-DATA 4 0x83fd9008 0x82a20000
-/* ESDCTL_ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCFG0 */
-DATA 4 0x83fd9004 0x3f3574aa
-/* ESDCTL_ESDCFG1 */
-DATA 4 0x83fd900c 0x3f3574aa
-
-/* Init DRAM on CS0 */
-/* ESDCTL_ESDSCR */
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x0000801a
-DATA 4 0x83fd9014 0x0000801b
-DATA 4 0x83fd9014 0x00448019
-DATA 4 0x83fd9014 0x07328018
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x06328018
-DATA 4 0x83fd9014 0x03808019
-DATA 4 0x83fd9014 0x00408019
-DATA 4 0x83fd9014 0x00008000
-
-/* Init DRAM on CS1 */
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x0000801e
-DATA 4 0x83fd9014 0x0000801f
-DATA 4 0x83fd9014 0x0000801d
-DATA 4 0x83fd9014 0x0732801c
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x0632801c
-DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0040801d
-DATA 4 0x83fd9014 0x00008004
-
-/* Write to CTL0 */
-DATA 4 0x83fd9000 0xb2a20000
-/* Write to CTL1 */
-DATA 4 0x83fd9008 0xb2a20000
-/* ESDMISC */
-DATA 4 0x83fd9010 0x000ad6d0
-/* ESDCTL_ESDCDLYGD */
-DATA 4 0x83fd9034 0x90000000
-DATA 4 0x83fd9014 0x00000000
+++ /dev/null
-/*
- * Copyright (C) 2009 Pegatron Corporation
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * BASED ON: imx51evk
- *
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
-*/
-/* DDR bus IOMUX PAD settings */
-DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
-DATA 4 0x73fa850c 0x20c5 # SDODT1
-DATA 4 0x73fa8510 0x20c5 # SDODT0
-DATA 4 0x73fa8848 0x4 # DDR_A1
-DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
-DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
-DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
-DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
-DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
-DATA 4 0x73fa8820 0x0 # DDRPKS
-DATA 4 0x73fa84ac 0xe5 # SDWE
-DATA 4 0x73fa84b0 0xe5 # SDCKE0
-DATA 4 0x73fa84b4 0xe5 # SDCKE1
-DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
-DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
-
-/*
- * Setting DDR for micron
- * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
- * CAS=3 BL=4
- */
-/* ESDCTL_ESDCTL0 */
-DATA 4 0x83fd9000 0x82a20000
-/* ESDCTL_ESDCTL1 */
-DATA 4 0x83fd9008 0x82a20000
-/* ESDCTL_ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCFG0 */
-DATA 4 0x83fd9004 0x333574aa
-/* ESDCTL_ESDCFG1 */
-DATA 4 0x83fd900c 0x333574aa
-
-/* Init DRAM on CS0 */
-/* ESDCTL_ESDSCR */
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x0000801a
-DATA 4 0x83fd9014 0x0000801b
-DATA 4 0x83fd9014 0x00448019
-DATA 4 0x83fd9014 0x07328018
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x06328018
-DATA 4 0x83fd9014 0x03808019
-DATA 4 0x83fd9014 0x00408019
-DATA 4 0x83fd9014 0x00008000
-
-/* Init DRAM on CS1 */
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x0000801e
-DATA 4 0x83fd9014 0x0000801f
-DATA 4 0x83fd9014 0x0000801d
-DATA 4 0x83fd9014 0x0732801c
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x0632801c
-DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0042801d
-DATA 4 0x83fd9014 0x00008004
-
-/* Write to CTL0 */
-DATA 4 0x83fd9000 0xb2a20000
-/* Write to CTL1 */
-DATA 4 0x83fd9008 0xb2a20000
-/* ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCDLYGD */
-DATA 4 0x83fd9034 0x90000000
-DATA 4 0x83fd9014 0x00000000
+++ /dev/null
-if TARGET_TT01
-
-config SYS_BOARD
- default "tt01"
-
-config SYS_VENDOR
- default "hale"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "tt01"
-
-endif
+++ /dev/null
-TT01 BOARD
-M: Helmut Raiger <helmut.raiger@hale.at>
-S: Maintained
-F: board/hale/tt01/
-F: include/configs/tt01.h
-F: configs/tt01_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tt01.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
- mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <command.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc13783.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BOARD_STRING "Board: HALE TT-01"
-
-/* Clock configuration */
-#define CCM_CCMR_SETUP 0x074B0BF5
-
-static void board_setup_clocks(void)
-{
- struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
- volatile int wait = 0x10000;
-
- writel(CCM_CCMR_SETUP, &ccm->ccmr);
- while (wait--)
- ;
-
- writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
- writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
-
- /* Set up clock to 532MHz */
- writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
- PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
- PDR0_MCU_PODF(0), &ccm->pdr0);
- writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
- &ccm->mpctl);
- writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
- &ccm->spctl);
-}
-
-/* DRAM configuration */
-
-#define ESDMISC_MDDR_SETUP 0x00000004
-#define ESDMISC_MDDR_RESET_DL 0x0000000c
-/*
- * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
- * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
- * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
- * tRCD = 011, tRC = 010
- * note: all but tWTR (1), tRC (111) are reset defaults,
- * the same values work in the jtag configuration
- *
- * Bluetechnix setup has 0x75e73a (for 128MB) =
- * 0b 0111 0101 1110 0111 0011 1010
- * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
- * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
- * tRCD = 011, tRC = 010
- */
-#define ESDCFG0_MDDR_SETUP 0x006ac73a
-#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
-#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
- ESDCTL_DSIZ(2) | ESDCTL_BL(1))
-#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
-#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
-#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
-#define ESDCTL_RW ESDCTL_SETTINGS
-
-static void board_setup_sdram(void)
-{
- u32 *pad;
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-
- /*
- * setup pad control for the controller pins
- * no loopback, no pull, no keeper, no open drain,
- * standard input, standard drive, slow slew rate
- */
- for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
- pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
- *pad = 0;
-
- /* set up MX31 DDR Memory Controller */
- writel(ESDMISC_MDDR_SETUP, &esdc->misc);
- writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
-
- /* perform DDR init sequence for CSD0 */
- writel(ESDCTL_PRECHARGE, &esdc->ctl0);
- writel(0x12344321, CSD0_BASE+0x0f00);
- writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
- writel(0x12344321, CSD0_BASE);
- writel(0x12344321, CSD0_BASE);
- writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
- writeb(0xda, CSD0_BASE+0x33);
- writeb(0xff, CSD0_BASE+0x1000000);
- writel(ESDCTL_RW, &esdc->ctl0);
- writel(0xDEADBEEF, CSD0_BASE);
- writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
-}
-
-static void tt01_spi3_hw_init(void)
-{
- /* CSPI3 */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
- /* CSPI3, SS0 = Atlas */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
-
- /* start CSPI3 clock (3 = always on except if PLL off) */
- setbits_le32(CCM_CGR0, 3 << 16);
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS4: FPGA incl. network controller */
- struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- /* this seems essential, won't start without, but why? */
- writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
-
- board_setup_clocks();
- board_setup_sdram();
- mxc_setup_weimcs(4, &cs4);
-
- /* Setup UART2 and SPI3 pins */
- mx31_uart2_hw_init();
- tt01_spi3_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
- hw_watchdog_init();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts(BOARD_STRING "\n");
- return 0;
-}
-
-#ifdef CONFIG_MXC_MMC
-int board_mmc_init(bd_t *bis)
-{
- u32 val;
- struct pmic *p;
- int ret;
-
- /*
- * this is the first driver to use the pmic, so call
- * pmic_init() here. board_late_init() is too late for
- * the MMC driver.
- */
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- /* configure pins for SDHC1 only */
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
- mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
-
- /* turn on power V_MMC1 */
- if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
- pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
-
- return mxc_mmc_init(bis);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-void video_get_info_str(int line_number, char *info)
-{
- u32 srev = get_cpu_rev();
-
- switch (line_number) {
- case 2:
- sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
- (srev & 0xF0) >> 4, (srev & 0x0F),
- ((srev & 0x8000) ? " unknown" : ""),
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- break;
- case 3:
- strcpy(info, " " BOARD_STRING);
- break;
- default:
- info[0] = 0;
- }
-}
-#endif
config SYS_CONFIG_NAME
default "hikey"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 4
+ default 4
+ help
+ The hi6220 SoC has 5 UARTs. For example to use UART0 enter 1 here.
+
endif
Compile u-boot
==============
-make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
-make CROSS_COMPILE=aarch64-linux-gnu-
+ > mkdir -p ./aarch64/bin
+ > cd ./aarch64
+ > git clone http://git.denx.de/u-boot.git
+ > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+ > make CROSS_COMPILE=aarch64-linux-gnu-
+ > cp u-boot.bin ./aarch64/bin/u-boot-hikey.bin
ARM Trusted Firmware (ATF) & l-loader
=====================================
This u-boot port has been tested with l-loader, booting ATF, which then boots
u-boot as the bl33.bin executable.
+Get the BL30 mcu binary.
+ > wget -P aarch64/bin https://builds.96boards.org/releases/hikey/linaro/binaries/15.05/mcuimage.bin
+
1. Get ATF source code
-git clone https://github.com/96boards/arm-trusted-firmware.git
+ > cd ./aarch64
+ > git clone https://github.com/96boards/arm-trusted-firmware.git
+ > cd ./arm-trusted-firmware
-2. Compile ATF I use the makefile here
-http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/build-tf.mak
+2. Compile ATF, I use the build-tf.mak in the directory with this README, and copy it to ATF directory
+ > cp ../u-boot/board/hisilicon/hikey/build-tf.mak .
+ > make -f build-tf.mak build
3. Get l-loader
-git clone https://github.com/96boards/l-loader.git
-
-4. Make sym links to ATF bip / fip binaries
-ln -s /home/griffinp/aarch64/bl1-hikey.bin bl1.bin
-ln -s /home/griffinp/aarch64/fip-hikey.bin fip.bin
+ > cd ../
+ > git clone https://github.com/96boards/l-loader.git
+ > cd ./l-loader
-arm-linux-gnueabihf-gcc -c -o start.o start.S
-arm-linux-gnueabihf-gcc -c -o debug.o debug.S
-arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader
-arm-linux-gnueabihf-objcopy -O binary loader temp
+4. Make sym links to ATF bl1 / fip binaries
+ > ln -s ../bin/bl1-hikey.bin bl1.bin
+ > ln -s ../bin/fip-hikey.bin fip.bin
-python gen_loader.py -o l-loader.bin --img_loader=temp --img_bl1=bl1.bin
-sudo bash -x generate_ptable.sh
-python gen_loader.py -o ptable.img --img_prm_ptable=prm_ptable.img --img_sec_ptable=sec_ptable.img
+ > arm-linux-gnueabihf-gcc -c -o start.o start.S
+ > arm-linux-gnueabihf-gcc -c -o debug.o debug.S
+ > arm-linux-gnueabihf-ld -Bstatic -Tl-loader.lds -Ttext 0xf9800800 start.o debug.o -o loader
+ > arm-linux-gnueabihf-objcopy -O binary loader temp
+ > python gen_loader.py -o ../bin/l-loader.bin --img_loader=temp --img_bl1=bl1.bin
+ > sudo bash -x generate_ptable.sh
+ > python gen_loader.py -o ../bin/ptable.img --img_prm_ptable=./prm_ptable.img --img_sec_ptable=./sec_ptable.img
These instructions are adapted from
https://github.com/96boards/documentation/wiki/HiKeyUEFI
FLASHING
========
-1. Connect jumper J2 to go into recovery mode and flash l-loader.bin with
- fastboot using the hisi-idt.py utility
+1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
+fastboot using the hisi-idt.py utility.
+
+ > cd ../
+ > git clone https://github.com/96boards/burn-boot.git
-> git clone https://github.com/96boards/burn-boot.git
-> sudo python /home/griffinp/Software/hikey/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=/tmp/l-loader.bin
+The command below assumes HiKey enumerated as the first USB serial port
+ > sudo ./burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=./bin/l-loader.bin
-2. Once LED 0 comes on solid, it should be detected as a fastboot device
- (on some boards I've found this to be unreliable)
+2. Once LED 0 comes on solid, it should be detected as a fastboot device by plugging a USB A to mini B
+ cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable).
-sudo fastboot devices
+ > sudo fastboot devices
+
+0123456789ABCDEF fastboot
3. Flash the images
-wget https://builds.96boards.org/releases/hikey/nvme.img
-sudo fastboot flash ptable ptable.img
-sudo fastboot flash fastboot fip.bin
-sudo fastboot flash nvme nvme.img
+ > wget -P aarch64/bin wget https://builds.96boards.org/releases/hikey/linaro/binaries/latest/nvme.img
+ > sudo fastboot flash ptable ./bin/ptable.img
+ > sudo fastboot flash fastboot ./bin/fip-hikey.bin
+ > sudo fastboot flash nvme ./bin/nvme.img
-4. Disconnect jumper J2, and reset the board and you will now (hopefully)
+4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
have ATF, booting u-boot from eMMC. On 'new' boards I've had to do the
flashing twice in the past to avoid an ATF error.
+ Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
+ will get 'dwc_otg_core_host_init: Timeout!' errors.
+
See working boot trace below: -
-debug EMMC boot: print init OK
debug EMMC boot: send RST_N .
debug EMMC boot: start eMMC boot......
load fastboot1!
+
Switch to aarch64 mode. CPU0 executes at 0xf9801000!
+
+INFO: BL1: 0xf9810000 - 0xf9817000 [size = 28672]
NOTICE: Booting Trusted Firmware
-NOTICE: BL1: v1.1(release):a0c0399
-NOTICE: BL1: Built : 13:23:48, May 22 2015
+NOTICE: BL1: v1.1(debug):e8b7174
+NOTICE: BL1: Built : 19:16:44, Sep 8 2015
+INFO: BL1: RAM 0xf9810000 - 0xf9817000
+NOTICE: syspll frequency:1190494208Hz
NOTICE: succeed to init lpddr3 rank0 dram phy
INFO: lpddr3_freq_init, set ddrc 533mhz
INFO: init ddr3 rank0
INFO: init ddr3 rank0
INFO: ddr3 rank1 init pass
INFO: Elpida DDR
+INFO: ddr test value:0xa5a55a5a
+INFO: Hisilicon HiKey platform is initialized
+INFO: Using FIP
+INFO: Loading file 'bl2.bin' at address 0xf9818000
+INFO: File 'bl2.bin' loaded: 0xf9818000 - 0xf9821100
NOTICE: BL1: Booting BL2
+INFO: BL1: BL2 address = 0xf9818000
+INFO: BL1: BL2 spsr = 0x3c5
INFO: [BDID] [fff91c18] midr: 0x410fd033
INFO: [BDID] [fff91c1c] board type: 0
INFO: [BDID] [fff91c20] board id: 0x2b
INFO: acpu_dvfs_set_freq: start prof is 0x4
INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
INFO: acpu_dvfs_set_freq: voltage:
-INFO: - 0: 0x3a
-INFO: - 1: 0x3a
-INFO: - 2: 0x4a
-INFO: - 3: 0x5b
-INFO: - 4: 0x6b
-NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):a0c0399
-NOTICE: BL2: Built : 10:19:28, May 27 2015
+INFO: - 0: 0x49
+INFO: - 1: 0x49
+INFO: - 2: 0x50
+INFO: - 3: 0x60
+INFO: - 4: 0x78
+NOTICE: acpu_dvfs_set_freq: set acpu freq success!NOTICE: BL2: v1.1(debug):e8b7174
+NOTICE: BL2: Built : 19:16:46, Sep 8 2015
INFO: BL2: Loading BL3-0
INFO: Using FIP
-WARNING: Failed to access image 'bl30.bin' (-1)
-ERROR: Failed to load BL3-0 (-1)
-ERROR: Please burn mcu image:
-ERROR: sudo fastboot flash mcuimage mcuimage.bin
+INFO: Loading file 'bl30.bin' at address 0x1000000
+INFO: Skip reserving memory: 0x1000000 - 0x1023270
+INFO: File 'bl30.bin' loaded: 0x1000000 - 0x1023270
+INFO: bl2_plat_handle_bl30: [1000000] 3a334d43 34313032 2f38302f 30203133
+INFO: bl2_plat_handle_bl30: [10000c8] 0 0 b 0
+INFO: bl2_plat_handle_bl30: [1000190] 17 0 0 0
+INFO: bl2_plat_handle_bl30: [1023260] 0 0 0 0
+INFO: hisi_mcu_load_image: mcu sections 0:
+INFO: hisi_mcu_load_image: src = 0x1000200
+INFO: hisi_mcu_load_image: dst = 0xf6000000
+INFO: hisi_mcu_load_image: size = 512
+INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x7600 0x201 0x1eae1 0x1ea71
+INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x7600 0x201 0x1eae1 0x1ea71
+INFO: hisi_mcu_load_image: mcu sections 1:
+INFO: hisi_mcu_load_image: src = 0x1000400
+INFO: hisi_mcu_load_image: dst = 0xf6000200
+INFO: hisi_mcu_load_image: size = 27828
+INFO: hisi_mcu_load_image: [SRC 0x1000400] 0xbf00bf00 0x4815b672 0x48154780 0x60014915
+INFO: hisi_mcu_load_image: [DST 0xf6000200] 0xbf00bf00 0x4815b672 0x48154780 0x60014915
+INFO: hisi_mcu_load_image: mcu sections 2:
+INFO: hisi_mcu_load_image: src = 0x10070b4
+INFO: hisi_mcu_load_image: dst = 0xf6007200
+INFO: hisi_mcu_load_image: size = 1024
+INFO: hisi_mcu_load_image: [SRC 0x10070b4] 0x55 0x0 0x0 0x0
+INFO: hisi_mcu_load_image: [DST 0xf6007200] 0x55 0x0 0x0 0x0
+INFO: hisi_mcu_load_image: mcu sections 3:
+INFO: hisi_mcu_load_image: src = 0x10074b4
+INFO: hisi_mcu_load_image: dst = 0xfff8e000
+INFO: hisi_mcu_load_image: size = 12704
+INFO: hisi_mcu_load_image: [SRC 0x10074b4] 0x55 0x0 0x0 0x0
+INFO: hisi_mcu_load_image: [DST 0xfff8e000] 0x55 0x0 0x0 0x0
+INFO: hisi_mcu_load_image: mcu sections 4:
+INFO: hisi_mcu_load_image: src = 0x100a654
+INFO: hisi_mcu_load_image: dst = 0x5e00000
+INFO: hisi_mcu_load_image: size = 82912
+INFO: hisi_mcu_load_image: [SRC 0x100a654] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0
+INFO: hisi_mcu_load_image: [DST 0x5e00000] 0x4ff0e92d 0x2cc5f645 0x2600b0ab 0x2c7cf6c0
+INFO: hisi_mcu_load_image: mcu sections 5:
+INFO: hisi_mcu_load_image: src = 0x101ea34
+INFO: hisi_mcu_load_image: dst = 0x5e143e0
+INFO: hisi_mcu_load_image: size = 12816
+INFO: hisi_mcu_load_image: [SRC 0x101ea34] 0x33323130 0x37363534 0x42413938 0x46454443
+INFO: hisi_mcu_load_image: [DST 0x5e143e0] 0x33323130 0x37363534 0x42413938 0x46454443
+INFO: hisi_mcu_load_image: mcu sections 6:
+INFO: hisi_mcu_load_image: src = 0x1021c44
+INFO: hisi_mcu_load_image: dst = 0x5e1c1d0
+INFO: hisi_mcu_load_image: size = 3060
+INFO: hisi_mcu_load_image: [SRC 0x1021c44] 0x0 0x0 0x0 0x0
+INFO: hisi_mcu_load_image: [DST 0x5e1c1d0] 0x0 0x0 0x0 0x0
+INFO: hisi_mcu_load_image: mcu sections 7:
+INFO: hisi_mcu_load_image: src = 0x1022838
+INFO: hisi_mcu_load_image: dst = 0x5e1cdc4
+INFO: hisi_mcu_load_image: size = 2616
+INFO: hisi_mcu_load_image: [SRC 0x1022838] 0xf80000a0 0x0 0xf80000ac 0x0
+INFO: hisi_mcu_load_image: [DST 0x5e1cdc4] 0xf80000a0 0x0 0xf80000ac 0x0
+INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
+INFO: bl2_plat_handle_bl30: mcu pc is 42933301
+INFO: bl2_plat_handle_bl30: AO_SC_PERIPH_CLKSTAT4 is 39018f09
INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
INFO: BL2: Loading BL3-1
INFO: Using FIP
INFO: Loading file 'bl31.bin' at address 0xf9858000
-INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9860010
+INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf9861010
INFO: BL2: Loading BL3-2
INFO: Using FIP
WARNING: Failed to access image 'bl32.bin' (-1)
INFO: BL2: Loading BL3-3
INFO: Using FIP
INFO: Loading file 'bl33.bin' at address 0x35000000
-INFO: File 'bl33.bin' loaded: 0x35000000 - 0x35042938
+INFO: File 'bl33.bin' loaded: 0x35000000 - 0x3504c468
NOTICE: BL1: Booting BL3-1
-NOTICE: BL3-1: v1.1(debug):a0c0399
-NOTICE: BL3-1: Built : 10:19:31, May 27 2015
+INFO: BL1: BL3-1 address = 0xf9858000
+INFO: BL1: BL3-1 spsr = 0x3cd
+INFO: BL1: BL3-1 params address = 0xf9821920
+INFO: BL1: BL3-1 plat params address = 0x0
+NOTICE: BL3-1: v1.1(debug):e8b7174
+NOTICE: BL3-1: Built : 19:16:49, Sep 8 2015
INFO: BL3-1: Initializing runtime services
INFO: BL3-1: Preparing for EL3 exit to normal world
INFO: BL3-1: Next image address = 0x35000000
INFO: BL3-1: Next image spsr = 0x3c9
-
-U-Boot 2015.04-00007-g1b3d379-dirty (May 27 2015 - 10:18:16) hikey
+U-Boot 2015.10-rc2 (Sep 08 2015 - 20:29:33 +0100)hikey
DRAM: 1008 MiB
-MMC: sd_card_detect: SD card present
+HI6553 PMIC init
+MMC: config_sd_carddetect: SD card not present
HiKey DWMMC: 0, HiKey DWMMC: 1
+Card did not respond to voltage select!
+** Bad device mmc 1 **
+Using default environment
+
In: serial
Out: serial
Err: serial
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
+starting USB...
+USB0: Core Release: 3.00a
+scanning bus 0 for devices... 2 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+ scanning usb for ethernet devices... 0 Ethernet Device(s) found
--- /dev/null
+CROSS_COMPILE := aarch64-linux-gnu-
+output_dir := $(PWD)/../bin
+makejobs := $(shell grep '^processor' /proc/cpuinfo | sort -u | wc -l)
+makethreads := $(shell dc -e "$(makejobs) 1 + p")
+make_options := GCC49_AARCH64_PREFIX=$CROSS_COMPILE \
+ -j$(makethreads) -l$(makejobs)
+
+BL30_HIKEY := $(output_dir)/mcuimage.bin
+BL33_HIKEY := $(output_dir)/u-boot-hikey.bin
+
+.PHONY: help
+help:
+ @echo "**** Common Makefile ****"
+ @echo "example:"
+ @echo "make -f build-tf.mak build"
+
+.PHONY: have-crosscompiler
+have-crosscompiler:
+ @echo -n "Check that $(CROSS_COMPILE)gcc is available..."
+ @which $(CROSS_COMPILE)gcc > /dev/null ; \
+ if [ ! $$? -eq 0 ] ; then \
+ echo "ERROR: cross-compiler $(CROSS_COMPILE)gcc not in PATH=$$PATH!" ; \
+ echo "ABORTING." ; \
+ exit 1 ; \
+ else \
+ echo "OK" ;\
+ fi
+
+build: have-crosscompiler FORCE
+ @echo "Build TF for Hikey..."
+ rm -rf build/
+ CROSS_COMPILE=$(CROSS_COMPILE) \
+ make all fip \
+ BL30=$(BL30_HIKEY) \
+ BL33=$(BL33_HIKEY) \
+ DEBUG=1 \
+ PLAT=hikey
+ @echo "Copy resulting binaries..."
+ cp build/hikey/debug/bl1.bin $(output_dir)/bl1-hikey.bin
+ cp build/hikey/debug/fip.bin $(output_dir)/fip-hikey.bin
+
+FORCE:
*/
#include <common.h>
#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
#include <errno.h>
#include <malloc.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
+static const struct pl01x_serial_platdata serial_platdata = {
+#if CONFIG_CONS_INDEX == 1
+ .base = HI6220_UART0_BASE,
+#elif CONFIG_CONS_INDEX == 4
+ .base = HI6220_UART3_BASE,
+#else
+#error "Unsuported console index value."
+#endif
+ .type = TYPE_PL011,
+ .clock = 19200000
+};
+
+U_BOOT_DEVICE(hikey_seriala) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_uart_init(void)
+{
+ switch (CONFIG_CONS_INDEX) {
+ case 1:
+ hi6220_pinmux_config(PERIPH_ID_UART0);
+ break;
+ case 4:
+ hi6220_pinmux_config(PERIPH_ID_UART3);
+ break;
+ default:
+ debug("%s: Unsupported UART selected\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ board_uart_init();
+ return 0;
+}
+#endif
+
struct peri_sc_periph_regs *peri_sc =
(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
int board_init(void)
{
- gd->flags = 0;
-
return 0;
}
+++ /dev/null
-if TARGET_LP8X4X
-
-config SYS_BOARD
- default "lp8x4x"
-
-config SYS_VENDOR
- default "icpdas"
-
-config SYS_CONFIG_NAME
- default "lp8x4x"
-
-endif
+++ /dev/null
-LP8X4X BOARD
-M: Sergey Yanovich <ynvich@gmail.com>
-S: Maintained
-F: board/icpdas/lp8x4x/
-F: include/configs/lp8x4x.h
-F: configs/lp8x4x_defconfig
+++ /dev/null
-#
-# ICPDAS LP-8x4x Support
-#
-# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := lp8x4x.o
+++ /dev/null
-/*
- * ICP DAS LP-8x4x Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * adapted from Voipac PXA270 Support by
- * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
-#include <asm/arch/pxa.h>
-#include <netdev.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- if (index !=0 || init != USB_INIT_HOST)
- return -1;
-
- writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
-
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- continue; /* required by checkpath.pl */
-
- writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
- writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
- writel(readl(UHCRHDA) | 0x800, UHCRHDA);
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- return 0;
-}
-
-int usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- if (index !=0 || init != USB_INIT_HOST)
- return -1;
-
- return usb_board_stop();
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
IGEP0033 BOARD
-M: Enric Balletbo i Serra <eballetbo@iseebcn.com>
+M: Enric Balletbo i Serra <eballetbo@gmail.com>
S: Maintained
F: board/isee/igep0033/
F: include/configs/am335x_igep0033.h
IGEP00X0 BOARD
-M: Enric Balletbo i Serra <eballetbo@iseebcn.com>
+M: Enric Balletbo i Serra <eballetbo@gmail.com>
S: Maintained
F: board/isee/igep00x0/
F: include/configs/omap3_igep00x0.h
{
switch (gd->bd->bi_arch_number) {
case MACH_TYPE_IGEP0020:
- setenv("dtbfile", "omap3-igep0020.dtb");
+ setenv("fdtfile", "omap3-igep0020.dtb");
break;
case MACH_TYPE_IGEP0030:
- setenv("dtbfile", "omap3-igep0030.dtb");
+ setenv("fdtfile", "omap3-igep0030.dtb");
break;
}
}
+++ /dev/null
-if TARGET_JORNADA
-
-config SYS_BOARD
- default "jornada"
-
-config SYS_CONFIG_NAME
- default "jornada"
-
-endif
+++ /dev/null
-JORNADA BOARD
-M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
-S: Maintained
-F: board/jornada/
-F: include/configs/jornada.h
-F: configs/jornada_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# 2004 (c) MontaVista Software, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := jornada.o
-obj-y += setup.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * 2004 (c) MontaVista Software, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <SA-1100.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
- gd->bd->bi_boot_params = 0xc0000100;
-
-
- /*
- * Turn on flashing.
- * Would be nice to have some protection but
- * that would have to be implemented in the
- * flash init function, which isnt possible yet.
- */
- PPSR |= (1 << 7);
- PPDR |= (1 << 7);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return (0);
-}
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- * 2004 (c) MontaVista Software, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/*-----------------------------------------------------------------------
- * Board defines:
- */
-
-#define MDCNFG 0x00
-#define MDCAS00 0x04
-#define MDCAS01 0x08
-#define MDCAS02 0x0C
-#define MSC0 0x10
-#define MSC1 0x14
-#define MECR 0x18
-#define MDREFR 0x1C
-#define MDCAS20 0x20
-#define MDCAS21 0x24
-#define MDCAS22 0x28
-#define MSC2 0x2C
-#define SMCNFG 0x30
-
-#define GPDR 0x04
-#define GPSR 0x08
-#define GPCR 0x0C
-#define GAFR 0x1C
-
-#define PPDR 0x00
-#define PPSR 0x04
-#define PPAR 0x08
-
-#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
-#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
-#define MDREFR_K0DB2 (1 << 18)
-#define MDREFR_K1DB2 (1 << 22)
-#define MDREFR_K2DB2 (1 << 26)
-
-#define MDREFR_K0RUN (1 << 17)
-#define MDREFR_K1RUN (1 << 21)
-#define MDREFR_K2RUN (1 << 25)
-
-#define MDREFR_SLFRSH (1 << 31)
-#define MDREFR_E1PIN (1 << 20)
-
-#define PSSR 0x04
-#define PSSR_DH 0x00000008
-#define POSR 0x08
-#define RCSR 0x04
-
-/*-----------------------------------------------------------------------
- * Setup parameters for the board:
- */
-MEM_BASE: .long 0xa0000000
-MEM_START: .long 0xc0000000
-PWR_BASE: .word 0x90020000
-RST_BASE: .long 0x90030000
-PPC_BASE: .long 0x90060000
-GPIO_BASE: .long 0x90040000
-IC_BASE: .word 0x90050000
-
-cpuspeed: .word 0xa0
-/* calculated from old blob bootloader */
-mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
-mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
-mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
-mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
-msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
-msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
-mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
-mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
-mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
-mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
-mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
-msc2: .long 0x201d2959 /* msc2 0x201d2959 */
-smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
-
-pin_set_out: .long 0x37ff70
-pin_set_dir: .long 0x11480
-
-gpdr_set: .long 0x0B3A0900
-gpsr_set: .long 0x02100800
-gpcr_set: .long 0x092A0100
-gafr_set: .long 0x08600000
-
-.globl lowlevel_init
-lowlevel_init:
-
-
- /* this is required for flashing */
- ldr r0, PPC_BASE
- ldr r1, pin_set_out
- str r1, [r0, #PPSR]
- ldr r1, pin_set_dir
- str r1, [r0, #PPDR]
-
- /* Setting up the memory and stuff */
- /***********************************/
-
- ldr r0, MEM_BASE
-
- ldr r1, mdcnfg
- str r1, [r0, #MDCNFG]
- ldr r1, mdcas00
- str r1, [r0, #MDCAS00]
- ldr r1, mdcas01
- str r1, [r0, #MDCAS01]
- ldr r1, mdcas02
- str r1, [r0, #MDCAS02]
- ldr r1, mdcas20
- str r1, [r0, #MDCAS20]
- ldr r1, mdcas21
- str r1, [r0, #MDCAS21]
- ldr r1, mdcas22
- str r1, [r0, #MDCAS22]
-
- /* clear kxDB2 */
- ldr r2, [r0, #MDREFR]
- bic r2, r2, #MDREFR_K0DB2
- bic r2, r2, #MDREFR_K1DB2
- bic r2, r2, #MDREFR_K2DB2
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_TRASR(7)
-
- mov r4, #0x2000
- spin: subs r4, r4, #1
- bne spin
-
- ldr r1, PWR_BASE
- mov r2, #PSSR_DH
- str r2, [r1, #PSSR]
-
- ldr r2, [r0, #MDREFR]
- bic r2, r2, #MDREFR_K0DB2
- bic r2, r2, #MDREFR_K1DB2
- bic r2, r2, #MDREFR_K2DB2
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_TRASR(7)
- orr r2, r2, #MDREFR_DRI(12)
- orr r2, r2, #MDREFR_K0DB2
- orr r2, r2, #MDREFR_K1DB2
- orr r2, r2, #MDREFR_K2DB2
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_K0RUN
- orr r2, r2, #MDREFR_K1RUN
- orr r2, r2, #MDREFR_K2RUN
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- bic r2, r2, #MDREFR_SLFRSH
- str r2, [r0, #MDREFR]
-
- ldr r2, [r0, #MDREFR]
- orr r2, r2, #MDREFR_E1PIN
- str r2, [r0, #MDREFR]
-
- ldr r2, MEM_START
-.rept 8
- ldr r3, [r2]
-.endr
-
- ldr r2, [r0, #MDCNFG]
- orr r2, r2, #0x00000003
- orr r2, r2, #0x00030000
- str r2, [r0, #MDCNFG]
-
- ldr r1, msc0
- str r1, [r0, #MSC0]
- ldr r1, msc1
- str r1, [r0, #MSC1]
- ldr r1, msc2
- str r1, [r0, #MSC2]
- ldr r1, smcnfg
- str r1, [r0, #SMCNFG]
- ldr r1, mecr
- str r1, [r0, #MECR]
-
- mov pc, lr
+++ /dev/null
-if TARGET_TK71
-
-config SYS_BOARD
- default "tk71"
-
-config SYS_VENDOR
- default "karo"
-
-config SYS_CONFIG_NAME
- default "tk71"
-
-endif
+++ /dev/null
-TK71 BOARD
-#M: -
-S: Maintained
-F: board/karo/tk71/
-F: include/configs/tk71.h
-F: configs/tk71_defconfig
+++ /dev/null
-#
-# Copyright (C) 2012 Marek Vasut <marex@denx.de>
-# on behalf of DENX Software Engineering GmbH
-#
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := tk71.o
+++ /dev/null
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# adopted to TK71 by
-# Nils Faerber <nils.faerber@kernelconcepts.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30 # DDR Configuration register
-# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1)
-# bit3-0: TRAS lsbs
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000034 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000000 # DDR Address Control
-# bit1-0: 01, Cs0width=x16
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 01, Cs1width=x16
-# bit7-6: 10, Cs1size=512Mb
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000652 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000042 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 0, DDR drive strenght normal
-# bit2: 0, DDR ODT control lsd (disabled)
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, (disabled)
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 0
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low)
-# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
-# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
-# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
-# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
-# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
-# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
-# bit14: 1, M_STARTBURST_IN ODT: Enabled
-# bit15: 1, DDR IO ODT Unit: Use ODT block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
+++ /dev/null
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TK71_OE_LOW (~0)
-#define TK71_OE_HIGH (~0)
-#define TK71_OE_VAL_LOW (0)
-#define TK71_OE_VAL_HIGH (0)
-
-int board_early_init_f(void)
-{
- /*
- * default gpio configuration
- * There are maximum 64 gpios controlled through 2 sets of registers
- * the below configuration configures mainly initial LED status
- */
- mvebu_config_gpio(TK71_OE_VAL_LOW,
- TK71_OE_VAL_HIGH,
- TK71_OE_LOW, TK71_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO,
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_SD_CLK,
- MPP13_SD_CMD,
- MPP14_SD_D0,
- MPP15_SD_D1,
- MPP16_SD_D2,
- MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GE1_0,
- MPP21_GE1_1,
- MPP22_GE1_2,
- MPP23_GE1_3,
- MPP24_GE1_4,
- MPP25_GE1_5,
- MPP26_GE1_6,
- MPP27_GE1_7,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GE1_10,
- MPP31_GE1_11,
- MPP32_GE1_12,
- MPP33_GE1_13,
- MPP34_GPIO,
- MPP35_GPIO,
- MPP36_GPIO,
- MPP37_GPIO,
- MPP38_GPIO,
- MPP39_GPIO,
- MPP40_GPIO,
- MPP41_GPIO,
- MPP42_GPIO,
- MPP43_GPIO,
- MPP44_GPIO,
- MPP45_GPIO,
- MPP46_GPIO,
- MPP47_GPIO,
- MPP48_GPIO,
- MPP49_GPIO,
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-
-#define MV88E1116_MAC_CTRL2_REG 21
-#define MV88E1116_PGADR_REG 22
-#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-
-static void mv_phy_88e1118_init(char *name)
-{
- u16 reg;
- u16 devadr;
-
- if (miiphy_set_current_dev(name))
- return;
-
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __func__);
- return;
- }
-
- /*
- * Enable RGMII delay on Tx and Rx for CPU port
- * Ref: sec 4.7.2 of chip datasheet
- */
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
-
- printf("88E1118 Initialized on %s\n", name);
-}
-
-/* Configure and enable Switch and PHY */
-void reset_phy(void)
-{
- /* configure and initialize PHY */
- mv_phy_88e1118_init("egiga0");
-
-}
-#endif
+++ /dev/null
-if TARGET_TX25
-
-config SYS_BOARD
- default "tx25"
-
-config SYS_VENDOR
- default "karo"
-
-config SYS_SOC
- default "mx25"
-
-config SYS_CONFIG_NAME
- default "tx25"
-
-endif
+++ /dev/null
-TX25 BOARD
-M: John Rigby <jcrigby@gmail.com>
-S: Maintained
-F: board/karo/tx25/
-F: include/configs/tx25.h
-F: configs/tx25_defconfig
+++ /dev/null
-#
-# (C) Copyright 2009 DENX Software Engineering
-# Author: John Rigby <jcrigby@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += lowlevel_init.o
-endif
-obj-y += tx25.o
+++ /dev/null
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on U-Boot and RedBoot sources for several different i.mx
- * platforms.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/macro.h>
-#include <asm/arch/macro.h>
-
-.macro init_clocks
- /*
- * clocks
- *
- * first enable CLKO debug output
- * 0x40000000 enables the debug CLKO signal
- * 0x05000000 sets CLKO divider to 6
- * 0x00600000 makes CLKO parent clk the USB clk
- */
- write32 0x53f80064, 0x45600000
-
- /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
- write32 0x53f80008, 0x20034000
-
- /*
- * PCDR2: NFC = 33.25 MHz
- * This is required for the NAND Flash of this board, which is a Samsung
- * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
- * the NFC driver in symmetric (i.e. one-cycle) mode.
- */
- write32 0x53f80020, 0x01010103
-
- /*
- * enable all implemented clocks in all three
- * clock control registers
- */
- write32 0x53f8000c, 0x1fffffff
- write32 0x53f80010, 0xffffffff
- write32 0x53f80014, 0xfdfff
-.endm
-
-.macro init_ddrtype
- /*
- * ddr_type is 3.3v SDRAM
- */
- write32 0x43fac454, 0x800
-.endm
-
-/*
- * sdram controller init
- */
-.macro init_sdram_bank bankaddr, ctl, cfg
- ldr r0, =0xb8001000
- ldr r2, =\bankaddr
- /*
- * reset SDRAM controller
- * then wait for initialization to complete
- */
- ldr r1, =(1 << 1)
- str r1, [r0, #0x10]
-1: ldr r3, [r0, #0x10]
- tst r3, #(1 << 31)
- beq 1b
-
- ldr r1, =0x95728
- str r1, [r0, #\cfg] /* config */
-
- ldr r1, =0x92116480 /* control | precharge */
- str r1, [r0, #\ctl] /* write command to controller */
- str r1, [r2, #0x400] /* command encoded in address */
-
- ldr r1, =0xa2116480 /* auto refresh */
- str r1, [r0, #\ctl]
- ldrb r3, [r2] /* read dram twice to auto refresh */
- ldrb r3, [r2]
-
- ldr r1, =0xb2116480 /* control | load mode */
- str r1, [r0, #\ctl] /* write command to controller */
- strb r1, [r2, #0x33] /* command encoded in address */
-
- ldr r1, =0x82116480 /* control | normal (0)*/
- str r1, [r0, #\ctl] /* write command to controller */
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- init_aips
- init_max
- init_m3if
- init_clocks
-
- init_sdram_bank 0x80000000, 0x0, 0x4
-
- init_sdram_bank 0x90000000, 0x8, 0xc
- mov pc, lr
+++ /dev/null
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on imx27lite.c:
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- * And:
- * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx25.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong bootflag)
-{
- /*
- * copy ourselves from where we are running to where we were
- * linked at. Use ulong pointers as all addresses involved
- * are 4-byte-aligned.
- */
- ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
- asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
- asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
- asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
- asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
- for (dst = start_ptr; dst < end_ptr; dst++)
- *dst = *(dst+(run_ptr-link_ptr));
- /*
- * branch to nand_boot's link-time address.
- */
- asm volatile("ldr pc, =nand_boot");
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define FEC_OUT_PAD_CTRL 0
-
-#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
-#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
-
-void tx25_fec_init(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX25_PAD_FEC_RX_DV__FEC_RX_DV,
- MX25_PAD_FEC_RDATA0__FEC_RDATA0,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
- MX25_PAD_FEC_MDIO__FEC_MDIO,
- MX25_PAD_FEC_RDATA1__FEC_RDATA1,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
-
- NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */
- NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */
- };
-
- static const iomux_v3_cfg_t fec_cfg_pads[] = {
- MX25_PAD_FEC_RDATA0__GPIO_3_10,
- MX25_PAD_FEC_RDATA1__GPIO_3_11,
- MX25_PAD_FEC_RX_DV__GPIO_3_12,
- };
-
- debug("tx25_fec_init\n");
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
- /* drop PHY power and assert reset (low) */
- gpio_direction_output(GPIO_FEC_RESET_B, 0);
- gpio_direction_output(GPIO_FEC_ENABLE_B, 0);
-
- mdelay(5);
-
- debug("resetting phy\n");
-
- /* turn on PHY power leaving reset asserted */
- gpio_set_value(GPIO_FEC_ENABLE_B, 1);
-
- mdelay(10);
-
- /*
- * Setup some strapping pins that are latched by the PHY
- * as reset goes high.
- *
- * Set PHY mode to 111
- * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
- * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
- * mode2 is tied high so nothing to do
- *
- * Turn on RMII mode
- * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
- */
- /*
- * set each mux mode to gpio mode
- */
- imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
- ARRAY_SIZE(fec_cfg_pads));
-
- /*
- * set each to 1 and make each an output
- */
- gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
- gpio_direction_output(IMX_GPIO_NR(3, 11), 1);
- gpio_direction_output(IMX_GPIO_NR(3, 12), 1);
-
- mdelay(22); /* this value came from RedBoot */
-
- /*
- * deassert PHY reset
- */
- gpio_set_value(GPIO_FEC_RESET_B, 1);
-
- mdelay(5);
-
- /*
- * set FEC pins back
- */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-#else
-#define tx25_fec_init()
-#endif
-
-#ifdef CONFIG_MXC_UART
-/*
- * Set up input pins with hysteresis and 100-k pull-ups
- */
-#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define UART1_OUT_PAD_CTRL 0
-
-static void tx25_uart1_init(void)
-{
- static const iomux_v3_cfg_t uart1_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-#else
-#define tx25_uart1_init()
-#endif
-
-int board_init()
-{
- tx25_uart1_init();
-
- /* board id for linux */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
-}
-
-int board_late_init(void)
-{
- tx25_fec_init();
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-#if CONFIG_NR_DRAM_BANKS > 1
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
-#else
-
-#endif
-}
-
-int checkboard(void)
-{
- printf("KARO TX25\n");
- return 0;
-}
config SYS_VENDOR
default "kosagi"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "novena"
+++ /dev/null
-if TARGET_IMX27LITE
-
-config SYS_BOARD
- default "imx27lite"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_SOC
- default "mx27"
-
-config SYS_CONFIG_NAME
- default "imx27lite"
-
-endif
-
-if TARGET_MAGNESIUM
-
-config SYS_BOARD
- default "imx27lite"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_SOC
- default "mx27"
-
-config SYS_CONFIG_NAME
- default "magnesium"
-
-endif
+++ /dev/null
-IMX27LITE BOARD
-M: Wolfgang Denk <wd@denx.de>
-S: Maintained
-F: board/logicpd/imx27lite/
-F: include/configs/imx27lite.h
-F: configs/imx27lite_defconfig
-
-MAGNESIUM BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: include/configs/magnesium.h
-F: configs/magnesium_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx27lite.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * Copyright (C) 2007 Sascha Hauer, Pengutronix
- * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
- struct system_control_regs *sc_regs =
- (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-#endif
-
- gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-#ifdef CONFIG_MXC_UART
- mx27_uart1_init_pins();
-#endif
-#ifdef CONFIG_FEC_MXC
- mx27_fec_init_pins();
- imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
- gpio_set_value(GPIO_PORTC | 31, 1);
-#endif
-#ifdef CONFIG_MXC_MMC
-#if defined(CONFIG_MAGNESIUM)
- mx27_sd1_init_pins();
-#else
- mx27_sd2_init_pins();
-#endif
-#endif
-
-#if defined(CONFIG_SYS_NAND_LARGEPAGE)
- /*
- * set in FMCR NF_FMS Bit(5) to 1
- * (NAND Flash with 2 Kbyte page size)
- */
- writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
-#if CONFIG_NR_DRAM_BANKS > 1
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
- PHYS_SDRAM_2_SIZE);
-#endif
-}
-
-int checkboard(void)
-{
- puts("Board: ");
- puts(CONFIG_BOARDNAME);
- return 0;
-}
+++ /dev/null
-/*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
- *
- * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-#include <asm/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
-SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
-SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
-SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
-SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
- ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
- ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
- ESDCTL_ROW13 | ESDCTL_COL10)
-SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
-
-.macro init_aipi
- /*
- * setup AIPI1 and AIPI2
- */
- write32 AIPI1_PSR0, AIPI1_PSR0_VAL
- write32 AIPI1_PSR1, AIPI1_PSR1_VAL
- write32 AIPI2_PSR0, AIPI2_PSR0_VAL
- write32 AIPI2_PSR1, AIPI2_PSR1_VAL
-
-.endm /* init_aipi */
-
-.macro init_clock
- ldr r0, =CSCR
- /* disable MPLL/SPLL first */
- ldr r1, [r0]
- bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
- str r1, [r0]
-
- write32 MPCTL0, MPCTL0_VAL
- write32 SPCTL0, SPCTL0_VAL
-
- write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
-
- /*
- * add some delay here
- */
- wait_timer 0x1000
-
- /* peripheral clock divider */
- write32 PCDR0, PCDR0_VAL
- write32 PCDR1, PCDR1_VAL
-
- /* Configure PCCR0 and PCCR1 */
- write32 PCCR0, PCCR0_VAL
- write32 PCCR1, PCCR1_VAL
-
-.endm /* init_clock */
-
-.macro sdram_init
- ldr r0, SOC_ESDCTL_BASE_W
- mov r2, #PHYS_SDRAM_1
-
- /* Do initial reset */
- mov r1, #ESDMISC_MDDR_DL_RST
- str r1, [r0, #ESDMISC_ROF]
-
- /* Hold for more than 200ns */
- wait_timer 0x10000
-
- /* Activate LPDDR iface */
- mov r1, #ESDMISC_MDDREN
- str r1, [r0, #ESDMISC_ROF]
-
- /* Check The chip version TO1 or TO2 */
- ldr r1, SOC_SI_ID_REG_W
- ldr r1, [r1]
- ands r1, r1, #0xF0000000
- /* add Latency on CAS only for TO2 */
- ldreq r1, SDRAM_ESDCFG_T2_W
- ldrne r1, SDRAM_ESDCFG_T1_W
- str r1, [r0, #ESDCFG0_ROF]
-
- /* Run initialization sequence */
- ldr r1, SDRAM_PRECHARGE_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_AUTOREF_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_LOADMODE_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
- ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
- add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
- ldrb r1, [r3]
-
- ldr r1, SDRAM_NORMAL_CMD_W
- str r1, [r0, #ESDCTL0_ROF]
-
-#if (CONFIG_NR_DRAM_BANKS > 1)
- /* 2nd sdram */
- mov r2, #PHYS_SDRAM_2
-
- /* Check The chip version TO1 or TO2 */
- ldr r1, SOC_SI_ID_REG_W
- ldr r1, [r1]
- ands r1, r1, #0xF0000000
- /* add Latency on CAS only for TO2 */
- ldreq r1, SDRAM_ESDCFG_T2_W
- ldrne r1, SDRAM_ESDCFG_T1_W
- str r1, [r0, #ESDCFG1_ROF]
-
- /* Run initialization sequence */
- ldr r1, SDRAM_PRECHARGE_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_AUTOREF_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
- ldr r1, [r2, #SDRAM_ALL_VAL]
- ldr r1, [r2, #SDRAM_ALL_VAL]
-
- ldr r1, SDRAM_LOADMODE_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
- ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
- add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
- ldrb r1, [r3]
-
- ldr r1, SDRAM_NORMAL_CMD_W
- str r1, [r0, #ESDCTL1_ROF]
-#endif /* CONFIG_NR_DRAM_BANKS > 1 */
-
-.endm /* sdram_init */
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
- init_aipi
-
- init_clock
-
- sdram_init
-
- mov pc,r10
+++ /dev/null
-if TARGET_IMX31_LITEKIT
-
-config SYS_BOARD
- default "imx31_litekit"
-
-config SYS_VENDOR
- default "logicpd"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "imx31_litekit"
-
-endif
+++ /dev/null
-IMX31_LITEKIT BOARD
-#M: -
-S: Maintained
-F: board/logicpd/imx31_litekit/
-F: include/configs/imx31_litekit.h
-F: configs/imx31_litekit_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx31_litekit.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS0: Nor Flash */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
- };
-
- /* CS4: Network Controller */
- static const struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
- mxc_setup_weimcs(4, &cs4);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* SPI2 */
- mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
- mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
- mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
- mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
- mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
- mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
- /* start SPI2 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: i.MX31 Litekit\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
+++ /dev/null
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- REG IPU_CONF, IPU_CONF_DI_EN
- REG CCM_CCMR, 0x074B0BF5
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
-
- REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
- REG 0x43FAC26C, 0 /* SDCLK */
- REG 0x43FAC270, 0 /* CAS */
- REG 0x43FAC274, 0 /* RAS */
- REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
- REG 0x43FAC284, 0 /* DQM3 */
- REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- REG 0x43FAC28C, 0
- REG 0x43FAC290, 0
- REG 0x43FAC294, 0
- REG 0x43FAC298, 0
- REG 0x43FAC29C, 0
- REG 0x43FAC2A0, 0
- REG 0x43FAC2A4, 0
- REG 0x43FAC2A8, 0
- REG 0x43FAC2AC, 0
- REG 0x43FAC2B0, 0
- REG 0x43FAC2B4, 0
- REG 0x43FAC2B8, 0
- REG 0x43FAC2BC, 0
- REG 0x43FAC2C0, 0
- REG 0x43FAC2C4, 0
- REG 0x43FAC2C8, 0
- REG 0x43FAC2CC, 0
- REG 0x43FAC2D0, 0
- REG 0x43FAC2D4, 0
- REG 0x43FAC2D8, 0
- REG 0x43FAC2DC, 0
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
--- /dev/null
+if TARGET_LWMON5
+
+config SYS_BOARD
+ default "lwmon5"
+
+config SYS_CONFIG_NAME
+ default "lwmon5"
+
+config DISPLAY_BOARDINFO
+ bool
+ default y
+
+endif
--- /dev/null
+LWMON5 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/lwmon5/
+F: include/configs/lwmon5.h
+F: configs/lwmon5_defconfig
--- /dev/null
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = lwmon5.o kbd.o sdram.o
+extra-y += init.o
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# lwmon5 (440EPx)
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
+
+ /* TLB-entry for the FPGA Chip select 2 */
+ tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for the FPGA Chip select 3 */
+ tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for the LIME Controller */
+ tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
+
+ /*TLB-entry PCI registers*/
+ tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
+
+ /* TLB-entry for peripherals */
+ tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <i2c.h>
+#include <command.h>
+#include <post.h>
+#include <serial.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h> /* for strdup */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+/*--------------------- Local macros and constants --------------------*/
+#define _NOT_USED_ 0xFFFFFFFF
+
+/*------------------------- dspic io expander -----------------------*/
+#define DSPIC_PON_STATUS_REG 0x80A
+#define DSPIC_PON_INV_STATUS_REG 0x80C
+#define DSPIC_PON_KEY_REG 0x810
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define KEYBD_CMD_READ_KEYS 0x01
+#define KEYBD_CMD_READ_VERSION 0x02
+#define KEYBD_CMD_READ_STATUS 0x03
+#define KEYBD_CMD_RESET_ERRORS 0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK 0x3F
+#define KEYBD_STATUS_H_RESET 0x20
+#define KEYBD_STATUS_BROWNOUT 0x10
+#define KEYBD_STATUS_WD_RESET 0x08
+#define KEYBD_STATUS_OVERLOAD 0x04
+#define KEYBD_STATUS_ILLEGAL_WR 0x02
+#define KEYBD_STATUS_ILLEGAL_RD 0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN 2 /* version information */
+
+/*
+ * This is different from the "old" lwmon dsPIC kbd controller
+ * implementation. Now the controller still answers with 9 bytes,
+ * but the last 3 bytes are always "0x06 0x07 0x08". So we just
+ * set the length to compare to 6 instead of 9.
+ */
+#define KEYBD_DATALEN 6 /* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function: int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: This function is the board_postclk_init() method implementation
+Z* for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+ kbd_init();
+
+ return (0);
+}
+
+static void kbd_init (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar tmp_data[KEYBD_DATALEN];
+ uchar val, errcd;
+ int i;
+
+ i2c_set_bus_num(0);
+
+ gd->arch.kbd_status = 0;
+
+ /* Forced by PIC. Delays <= 175us loose */
+ udelay(1000);
+
+ /* Read initial keyboard error code */
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &errcd, 1);
+ /* clear unused bits */
+ errcd &= KEYBD_STATUS_MASK;
+ /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+ errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+ if (errcd) {
+ gd->arch.kbd_status |= errcd << 8;
+ }
+ /* Reset error code and verify */
+ val = KEYBD_CMD_RESET_ERRORS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ udelay(1000); /* delay NEEDED by keyboard PIC !!! */
+
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &val, 1);
+
+ val &= KEYBD_STATUS_MASK; /* clear unused bits */
+ if (val) { /* permanent error, report it */
+ gd->arch.kbd_status |= val;
+ return;
+ }
+
+ /*
+ * Read current keyboard state.
+ *
+ * After the error reset it may take some time before the
+ * keyboard PIC picks up a valid keyboard scan - the total
+ * scan time is approx. 1.6 ms (information by Martin Rajek,
+ * 28 Sep 2002). We read a couple of times for the keyboard
+ * to stabilize, using a big enough delay.
+ * 10 times should be enough. If the data is still changing,
+ * we use what we get :-(
+ */
+
+ memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
+ for (i=0; i<10; ++i) {
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+ /* consistent state, done */
+ break;
+ }
+ /* remeber last state, delay, and retry */
+ memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+ udelay (5000);
+ }
+}
+
+
+/* Read a register from the dsPIC. */
+int _dspic_read(ushort reg, ushort *data)
+{
+ uchar buf[sizeof(*data)];
+ int rval;
+
+ if (i2c_read(dspic_addr, reg, 2, buf, 2))
+ return -1;
+
+ rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
+ *data = (buf[0] << 8) | buf[1];
+
+ return rval;
+}
+
+
+/***********************************************************************
+F* Function: int misc_init_r (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned, even in the case of a keyboard
+P* error.
+ *
+Z* Intention: This function is the misc_init_r() method implementation
+Z* for the lwmon board.
+Z* The keyboard controller is initialized and the result
+Z* of a read copied to the environment variable "keybd".
+Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z* this key, and if found display to the LCD will be enabled.
+Z* The keys in "keybd" are checked against the magic
+Z* keycommands defined in the environment.
+Z* See also key_match().
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r_kbd (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar kbd_init_status = gd->arch.kbd_status >> 8;
+ uchar kbd_status = gd->arch.kbd_status;
+ uchar val;
+ ushort data, inv_data;
+ char *str;
+ int i;
+
+ if (kbd_init_status) {
+ printf ("KEYBD: Error %02X\n", kbd_init_status);
+ }
+ if (kbd_status) { /* permanent error, report it */
+ printf ("*** Keyboard error code %02X ***\n", kbd_status);
+ sprintf (keybd_env, "%02X", kbd_status);
+ setenv ("keybd", keybd_env);
+ return 0;
+ }
+
+ /*
+ * Now we know that we have a working keyboard, so disable
+ * all output to the LCD except when a key press is detected.
+ */
+
+ if ((console_assign (stdout, "serial") < 0) ||
+ (console_assign (stderr, "serial") < 0)) {
+ printf ("Can't assign serial port as output device\n");
+ }
+
+ /* Read Version */
+ val = KEYBD_CMD_READ_VERSION;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+ printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+ /* Read current keyboard state */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ /* read out start key from bse01 received via can */
+ _dspic_read(DSPIC_PON_STATUS_REG, &data);
+ /* check highbyte from status register */
+ if (data > 0xFF) {
+ _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
+
+ /* check inverse data */
+ if ((data+inv_data) == 0xFFFF) {
+ /* don't overwrite local key */
+ if (kbd_data[1] == 0) {
+ /* read key value */
+ _dspic_read(DSPIC_PON_KEY_REG, &data);
+ str = (char *)&data;
+ /* swap bytes */
+ kbd_data[1] = str[1];
+ kbd_data[2] = str[0];
+ printf("CAN received startkey: 0x%X\n", data);
+ }
+ }
+ }
+
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ }
+
+ setenv ("keybd", keybd_env);
+
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+ if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
+ if ((console_assign (stdout, "lcd") < 0) ||
+ (console_assign (stderr, "lcd") < 0)) {
+ printf ("Can't assign LCD display as output device\n");
+ }
+ }
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
+ setenv ("preboot", str); /* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+ if (str != NULL) {
+ free (str);
+ }
+ return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+ uchar compare[KEYBD_DATALEN-1];
+ char *nxt;
+ int i;
+
+ /* Don't include modifier byte */
+ memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+ uchar c;
+ int k;
+
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+ if (str == (uchar *)nxt) { /* invalid character */
+ break;
+ }
+
+ /*
+ * Check if this key matches the input.
+ * Set matches to zero, so they match only once
+ * and we can find duplicates or extra keys
+ */
+ for (k = 0; k < sizeof(compare); ++k) {
+ if (compare[k] == '\0') /* only non-zero entries */
+ continue;
+ if (c == compare[k]) { /* found matching key */
+ compare[k] = '\0';
+ break;
+ }
+ }
+ if (k == sizeof(compare)) {
+ return -1; /* unmatched key */
+ }
+ }
+
+ /*
+ * A full match leaves no keys in the `compare' array,
+ */
+ for (i = 0; i < sizeof(compare); ++i) {
+ if (compare[i])
+ {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/***********************************************************************
+F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters: uchar *kbd_data
+P* - The keys to match against our magic definitions
+P*
+P* Returnvalue: uchar *
+P* - != NULL: Pointer to the corresponding command(s)
+P* NULL: No magic is about to happen
+ *
+Z* Intention: Check if pressed key(s) match magic sequence,
+Z* and return the command string associated with that key(s).
+Z*
+Z* If no key press was decoded, NULL is returned.
+Z*
+Z* Note: the first character of the argument will be
+Z* overwritten with the "magic charcter code" of the
+Z* decoded key(s), or '\0'.
+Z*
+Z* Note: the string points to static environment data
+Z* and must be saved before you call any function that
+Z* modifies the environment.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ uchar *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can pe appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ debug ("### Check magic \"%s\"\n", magic);
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+ cmd = getenv (cmd_name);
+ debug ("### Set PREBOOT to $(%s): \"%s\"\n",
+ cmd_name, cmd ? cmd : "<<NULL>>");
+ *kbd_data = *suffix;
+ return ((uchar *)cmd);
+ }
+ }
+ debug ("### Delete PREBOOT\n");
+ *kbd_data = '\0';
+ return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+/***********************************************************************
+F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char * const argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: Implement the "kbd" command.
+Z* The keyboard status is read. The result is printed on
+Z* the console and written into the "keybd" environment
+Z* variable.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar val;
+ int i;
+
+#if 0 /* Done in kbd_init */
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ puts ("Keys:");
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ printf (" %02x", kbd_data[i]);
+ }
+ putc ('\n');
+ setenv ("keybd", keybd_env);
+ return 0;
+}
+
+U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "read keyboard status",
+ ""
+);
+
+/*----------------------------- Utilities -----------------------------*/
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar val;
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <post.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
+
+ulong flash_get_size(ulong base, int banknum);
+int misc_init_r_kbd(void);
+
+int board_early_init_f(void)
+{
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ /* PLB Write pipelining disabled. Denali Core workaround */
+ mtdcr(PLB4A0_ACR, 0xDE000000);
+ mtdcr(PLB4A1_ACR, 0xDE000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
+ mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
+ mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
+ mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
+ mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* Trace Pins are disabled. SDR0_PFC0 Register */
+ mtsdr(SDR0_PFC0, 0x0);
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ /* SMII via ZMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+
+ /* enable SPI (SCP) */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ mtsdr(SDR0_PFC4, 0x80000000);
+
+ /* PCI arbiter disabled */
+ /* PCI Host Configuration disbaled */
+ mfsdr(SDR0_PCI0, reg);
+ reg = 0;
+ mtsdr(SDR0_PCI0, 0x00000000 | reg);
+
+ gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
+
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+ /* enable the CAN transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
+
+ reg = 0; /* reuse as counter */
+ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+ in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
+ & ~CONFIG_SYS_DSPIC_TEST_MASK);
+ while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
+ udelay(1000);
+ }
+ if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
+ /* set "boot error" flag */
+ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+ in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
+ CONFIG_SYS_DSPIC_TEST_MASK);
+ }
+#endif
+
+ /*
+ * Reset PHY's:
+ * The PHY's need a 2nd reset pulse, since the MDIO address is latched
+ * upon reset, and with the first reset upon powerup, the addresses are
+ * not latched reliable, since the IRQ line is multiplexed with an
+ * MDIO address. A 2nd reset at this time will make sure, that the
+ * correct address is latched.
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+ udelay(1000);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
+ udelay(1000);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+
+ return 0;
+}
+
+/*
+ * Override weak default with board specific version
+ */
+phys_addr_t cfi_flash_bank_addr(int bank)
+{
+ return lwmon5_cfi_flash_bank_addr[bank];
+}
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+ return flash_info[idx].size;
+}
+
+int board_early_init_r(void)
+{
+ u32 val0, val1;
+
+ /*
+ * lwmon5 is manufactured in 2 different board versions:
+ * The lwmon5a board has 64MiB NOR flash instead of the
+ * 128MiB of the original lwmon5. Unfortunately the CFI driver
+ * will report 2 banks of 64MiB even for the smaller flash
+ * chip, since the bank is mirrored. To fix this, we bring
+ * one bank into CFI query mode and read its response. This
+ * enables us to detect the real number of flash devices/
+ * banks which will be used later on by the common CFI driver.
+ */
+
+ /* Put bank 0 into CFI command mode and read */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
+ val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
+ val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
+
+ /* Reset flash again out of query mode */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
+
+ /* When not identical, we have 2 different flash devices/banks */
+ if (val0 != val1)
+ return 0;
+
+ /*
+ * Now we're sure that we're running on a LWMON5a board with
+ * only 64MiB NOR flash in one bank:
+ *
+ * Set flash base address and bank count for CFI driver probing.
+ */
+ cfi_flash_num_flash_banks = 1;
+ lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1, sdr0_srst;
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mfebc(PB0CR, pbcr);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(PB0CR, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
+
+ /* Env protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
+
+ /*
+ * USB suff...
+ */
+
+ /* Reset USB */
+ /* Reset of USB2PHY0 must be active at least 10 us */
+ mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
+ udelay(2000);
+
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
+ SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
+ SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
+ udelay(2000);
+
+ /* Errata CHIP_6 */
+
+ /* 1. Set internal PHY configuration */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* 2. De-assert internal PHY reset */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+
+ /* 3. Wait for more than 1 ms */
+ udelay(2000);
+
+ /* 4. De-assert USB 2.0 Host main reset */
+ mfsdr(SDR0_SRST0, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst);
+ udelay(1000);
+
+ /* 5. De-assert reset of OPB2 cores */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+ udelay(1000);
+
+ /* 6. Set EHCI Configure FLAG */
+
+ /* 7. Reassert internal PHY reset: */
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
+ udelay(1000);
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+ /*
+ * Init matrix keyboard
+ */
+ misc_init_r_kbd();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: %s", __stringify(CONFIG_HOSTNAME));
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+void hw_watchdog_reset(void)
+{
+ int val;
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long ct = get_ticks();
+
+ /*
+ * Don't allow watch-dog triggering more frequently than
+ * the predefined value CONFIG_WD_MAX_RATE [ticks].
+ */
+ if (ct >= gd->arch.wdt_last) {
+ if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
+ return;
+ } else {
+ /* Time base counter had been reset */
+ if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
+ CONFIG_WD_MAX_RATE)
+ return;
+ }
+ gd->arch.wdt_last = get_ticks();
+#endif
+
+ /*
+ * Toggle watchdog output
+ */
+ val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
+ gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
+}
+
+int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if ((strcmp(argv[1], "on") == 0))
+ gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
+ else if ((strcmp(argv[1], "off") == 0))
+ gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
+ else
+ return cmd_usage(cmdtp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ eepromwp, 2, 0, do_eeprom_wp,
+ "eeprom write protect off/on",
+ "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
+);
+
+#if defined(CONFIG_VIDEO)
+#include <video_fb.h>
+#include <mb862xx.h>
+
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs [] = {
+ { 0x0100, 0x00000f00 },
+ { 0x0020, 0x801401df },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x00000000 },
+ { 0x002c, 0x00000000 },
+ { 0x0110, 0x00000000 },
+ { 0x0114, 0x00000000 },
+ { 0x0118, 0x01df0280 },
+ { 0x0004, 0x031f0000 },
+ { 0x0008, 0x027f027f },
+ { 0x000c, 0x015f028f },
+ { 0x0010, 0x020c0000 },
+ { 0x0014, 0x01df01ea },
+ { 0x0018, 0x00000000 },
+ { 0x001c, 0x01e00280 },
+ { 0x0100, 0x80010f00 },
+ { 0x0, 0x0 }
+};
+
+const gdc_regs *board_get_regs(void)
+{
+ return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init(void)
+{
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ mb862xx.winSizeX = 640;
+ mb862xx.winSizeY = 480;
+ mb862xx.gdfBytesPP = 2;
+ mb862xx.gdfIndex = GDF_15BIT_555RGB;
+
+ return CONFIG_SYS_LIME_BASE_0;
+}
+
+#define DEFAULT_BRIGHTNESS 0x64
+
+static void board_backlight_brightness(int brightness)
+{
+ if (brightness > 0) {
+ /* pwm duty, lamp on */
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
+ } else {
+ /* lamp off */
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
+ }
+}
+
+void board_backlight_switch(int flag)
+{
+ char * param;
+ int rc;
+
+ if (flag) {
+ param = getenv("brightness");
+ rc = param ? simple_strtol(param, NULL, 10) : -1;
+ if (rc < 0)
+ rc = DEFAULT_BRIGHTNESS;
+ } else {
+ rc = 0;
+ }
+ board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str(int line_number, char *info)
+{
+ if (line_number == 1)
+ strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
+ else
+ info [0] = '\0';
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+#endif /* CONFIG_VIDEO */
+
+void board_reset(void)
+{
+ gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * lwmon5 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+ char s[8];
+
+ env_init();
+ getenv_f("boot_os", s, sizeof(s));
+ if ((s != NULL) && (strcmp(s, "yes") == 0))
+ return 0;
+
+ return 1;
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+ const gdc_regs *regs = board_get_regs();
+
+ /*
+ * Setup PFC registers, mainly for ethernet support
+ * later on in Linux
+ */
+ board_early_init_f();
+
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
+ udelay(300);
+ out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
+
+ while (regs->index) {
+ out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
+ regs->index, regs->value);
+ regs++;
+ }
+
+ board_backlight_brightness(DEFAULT_BRIGHTNESS);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/ppc440.h>
+#include <watchdog.h>
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CONFIG_4xx_DCACHE
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
+#endif
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+extern void dcbz_area(u32 start_address, u32 num_bytes);
+
+static u32 is_ecc_enabled(void)
+{
+ u32 val;
+
+ mfsdram(DDR0_22, val);
+ val &= DDR0_22_CTRL_RAW_MASK;
+ if (val)
+ return 1;
+ else
+ return 0;
+}
+
+void board_add_ram_info(int use_default)
+{
+ PPC4xx_SYS_INFO board_cfg;
+ u32 val;
+
+ if (is_ecc_enabled())
+ puts(" (ECC");
+ else
+ puts(" (ECC not");
+
+ get_sys_info(&board_cfg);
+ printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+ mfsdram(DDR0_03, val);
+ val = DDR0_03_CASLAT_DECODE(val);
+ printf(", CL%d)", val);
+}
+
+#ifdef CONFIG_DDR_ECC
+static void wait_ddr_idle(void)
+{
+ /*
+ * Controller idle status cannot be determined for Denali
+ * DDR2 code. Just return here.
+ */
+}
+
+static void program_ecc(u32 start_address,
+ u32 num_bytes,
+ u32 tlb_word2_i_value)
+{
+ u32 val;
+ u32 current_addr = start_address;
+ u32 size;
+ int bytes_remaining;
+
+ sync();
+ wait_ddr_idle();
+
+ /*
+ * Because of 440EPx errata CHIP 11, we don't touch the last 256
+ * bytes of SDRAM.
+ */
+ bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
+
+ /*
+ * We have to write the ECC bytes by zeroing and flushing in smaller
+ * steps, since the whole 256MByte takes too long for the external
+ * watchdog.
+ */
+ while (bytes_remaining > 0) {
+ size = min((64 << 20), bytes_remaining);
+
+ /* Write zero's to SDRAM */
+ dcbz_area(current_addr, size);
+
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(current_addr, current_addr + size);
+
+ current_addr += 64 << 20;
+ bytes_remaining -= 64 << 20;
+ WATCHDOG_RESET();
+ }
+
+ sync();
+ wait_ddr_idle();
+
+ /* Clear error status */
+ mfsdram(DDR0_00, val);
+ mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+ /* Set 'int_mask' parameter to functionnal value */
+ mfsdram(DDR0_01, val);
+ mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
+
+ sync();
+ wait_ddr_idle();
+}
+#endif
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+ /* CL=4 */
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+ mtsdram(DDR0_04, 0x0B030300);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0003C812);
+ mtsdram(DDR0_07, 0x00090100);
+ mtsdram(DDR0_08, 0x03c80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_11, 0x000CC800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1e000000);
+ mtsdram(DDR0_18, 0x1e1e1e1e);
+ mtsdram(DDR0_19, 0x1e1e1e1e);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
+#else
+ mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+ mtsdram(DDR0_23, 0x01000000);
+ mtsdram(DDR0_24, 0x01010001);
+
+ mtsdram(DDR0_26, 0x2D93028A);
+ mtsdram(DDR0_27, 0x0784682B);
+
+ mtsdram(DDR0_28, 0x00000080);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000008);
+
+ mtsdram(DDR0_43, 0x050A0200);
+ mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+
+ denali_wait_for_dlllock();
+
+#if defined(CONFIG_DDR_DATA_EYE)
+ /* -----------------------------------------------------------+
+ * Perform data eye search if requested.
+ * ----------------------------------------------------------*/
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+ TLB_WORD2_I_ENABLE);
+ denali_core_search_data_eye();
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif
+
+ /*
+ * Program tlb entries for this size (dynamic)
+ */
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+ MY_TLB_WORD2_I_ENABLE);
+
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
+ /*
+ * Setup 2nd TLB with same physical address but different virtual address
+ * with cache enabled. This is done for fast ECC generation.
+ */
+ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
+
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
+}
+++ /dev/null
-if TARGET_OMAP3_MVBLX
-
-config SYS_BOARD
- default "mvblx"
-
-config SYS_VENDOR
- default "matrix_vision"
-
-config SYS_CONFIG_NAME
- default "omap3_mvblx"
-
-endif
+++ /dev/null
-MVBLX BOARD
-M: Michael Jones <michael.jones@matrix-vision.de>
-S: Maintained
-F: board/matrix_vision/mvblx/
-F: include/configs/omap3_mvblx.h
-F: configs/omap3_mvblx_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mvblx.o fpga.o
-obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-
-ccflags-y += -Werror
+++ /dev/null
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <linux/byteorder/generic.h>
-#include "fpga.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
- fpga_null_fn, /* Altera_pre_fn */
- fpga_config_fn,
- fpga_status_fn,
- fpga_done_fn,
- fpga_wr_fn,
- fpga_null_fn,
- fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
- Altera_CYC2,
- fast_passive_parallel,
- Altera_EP3C5_SIZE,
- (void *) &altera_fns,
- NULL,
- 0
-};
-
-#define GPIO_RESET 43
-#define GPIO_DCLK 65
-#define GPIO_nSTATUS 157
-#define GPIO_CONF_DONE 158
-#define GPIO_nCONFIG 159
-#define GPIO_DATA0 54
-#define GPIO_DATA1 55
-#define GPIO_DATA2 56
-#define GPIO_DATA3 57
-#define GPIO_DATA4 58
-#define GPIO_DATA5 60
-#define GPIO_DATA6 61
-#define GPIO_DATA7 62
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* return FPGA_SUCCESS on success, else FPGA_FAIL
- */
-int mvblx_init_fpga(void)
-{
- fpga_debug("Initializing FPGA interface\n");
- fpga_init();
- fpga_add(fpga_altera, &cyclone2);
-
- if (gpio_request(GPIO_DCLK, "dclk") ||
- gpio_request(GPIO_nSTATUS, "nStatus") ||
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
- gpio_request(GPIO_CONF_DONE, "conf_done") ||
-#endif
- gpio_request(GPIO_nCONFIG, "nConfig") ||
- gpio_request(GPIO_DATA0, "data0") ||
- gpio_request(GPIO_DATA1, "data1") ||
- gpio_request(GPIO_DATA2, "data2") ||
- gpio_request(GPIO_DATA3, "data3") ||
- gpio_request(GPIO_DATA4, "data4") ||
- gpio_request(GPIO_DATA5, "data5") ||
- gpio_request(GPIO_DATA6, "data6") ||
- gpio_request(GPIO_DATA7, "data7")) {
- printf("%s: error requesting GPIOs.", __func__);
- return FPGA_FAIL;
- }
-
- /* set up outputs */
- gpio_direction_output(GPIO_DCLK, 0);
- gpio_direction_output(GPIO_nCONFIG, 0);
- gpio_direction_output(GPIO_DATA0, 0);
- gpio_direction_output(GPIO_DATA1, 0);
- gpio_direction_output(GPIO_DATA2, 0);
- gpio_direction_output(GPIO_DATA3, 0);
- gpio_direction_output(GPIO_DATA4, 0);
- gpio_direction_output(GPIO_DATA5, 0);
- gpio_direction_output(GPIO_DATA6, 0);
- gpio_direction_output(GPIO_DATA7, 0);
-
- /* NB omap_free_gpio() resets to an input, so we can't
- * free ie. nCONFIG, or else the FPGA would reset
- * Q: presumably gpio_free() has the same effect?
- */
-
- /* set up inputs */
- gpio_direction_input(GPIO_nSTATUS);
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
- gpio_direction_input(GPIO_CONF_DONE);
-#endif
-
- fpga_config_fn(0, 1, 0);
- udelay(60);
-
- return FPGA_SUCCESS;
-}
-
-int fpga_null_fn(int cookie)
-{
- return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
- fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
- if (flush) {
- gpio_set_value(GPIO_nCONFIG, !assert);
- udelay(1);
- gpio_set_value(GPIO_nCONFIG, assert);
- }
-
- return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
- int result = 0;
-
- /* since revA of BLX, we will not get this signal. */
- udelay(10);
-#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
- fpga_debug("not waiting for CONF_DONE.");
- result = 1;
-#else
- fpga_debug("CONF_DONE check ... ");
- if (gpio_get_value(GPIO_CONF_DONE)) {
- fpga_debug("high\n");
- result = 1;
- } else
- fpga_debug("low\n");
- gpio_free(GPIO_CONF_DONE);
-#endif
-
- return result;
-}
-
-int fpga_status_fn(int cookie)
-{
- int result = 0;
- fpga_debug("STATUS check ... ");
-
- result = gpio_get_value(GPIO_nSTATUS);
-
- if (result < 0)
- fpga_debug("error\n");
- else if (result > 0)
- fpga_debug("high\n");
- else
- fpga_debug("low\n");
-
- return result;
-}
-
-static inline int _write_fpga(u8 byte)
-{
- gpio_set_value(GPIO_DATA0, byte & 0x01);
- gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
- gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
- gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
- gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
- gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
- gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
- gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
-
- /* clock */
- gpio_set_value(GPIO_DCLK, 1);
- udelay(1);
- gpio_set_value(GPIO_DCLK, 0);
- udelay(1);
-
- return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
- unsigned char *data = (unsigned char *) buf;
- int i;
- int headerlen = len - cyclone2.size;
-
- if (headerlen < 0)
- return FPGA_FAIL;
- else if (headerlen == sizeof(uint32_t)) {
- const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
- char fpgavers_str[fpgavers_len];
- snprintf(fpgavers_str, fpgavers_len, "0x%08x",
- be32_to_cpup((uint32_t*)data));
- setenv("fpgavers", fpgavers_str);
- }
-
- fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
- for (i = headerlen; i < len; i++)
- _write_fpga(data[i]);
- fpga_debug("-%s\n", __func__);
-
- return FPGA_SUCCESS;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern int mvblx_init_fpga(void);
-
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
+++ /dev/null
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from Beagle and Overo
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach-types.h>
-#include "mvblx.h"
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- printf("mvBlueLYNX-X\n");
- if (get_cpu_family() == CPU_OMAP36XX)
- setenv("mpurate", "1000");
- else
- setenv("mpurate", "600");
-
- twl4030_power_init();
-
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif /* CONFIG_CMD_NET */
-
- mvblx_init_fpga();
-
- mac_read_from_eeprom();
-
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_MVBLX();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
- twl4030_power_mmc_init(1);
-}
-#endif
-
-#if defined(CONFIG_CMD_NET)
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
- writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
- writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
- writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
- writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
- writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
- writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-
- /* Make GPIO 139 as output pin */
- writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
-
- /* Now send a pulse on the GPIO pin */
- writel(GPIO11, &gpio5_base->setdataout);
- udelay(1);
- writel(GPIO11, &gpio5_base->cleardataout);
- udelay(1);
- writel(GPIO11, &gpio5_base->setdataout);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
-
-int overwrite_console(void)
-{
- /* return true if console should be overwritten */
- return 0;
-}
-
-#endif /* CONFIG_CMD_NET */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _MVBLX_H_
-#define _MVBLX_H_
-
-#include <asm/arch/sys_proto.h>
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 mvBlueLYNX-X camera",
- "no NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MVBLX() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card 1*/\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
- MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
- MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
- /*Expansion card 2 */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
- MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
- MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
- /* USB EHCI (port 2) not used */\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
- MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
- MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
- MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
- /* USB EHCI (port 1) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-#endif
+++ /dev/null
-/*
- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
- * York Sun (yorksun@freescale.com)
- * Haiying Wang (haiying.wang@freescale.com)
- * Timur Tabi (timur@freescale.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-
-/* #define DEBUG */
-
-/*
- * static eeprom: EEPROM layout
- */
-static struct __attribute__ ((__packed__)) eeprom {
- u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
- u8 sn[10]; /* 0x10 - 0x19 Serial Number */
- u8 date[6]; /* 0x1A - 0x1F Build Date */
- u8 mac[6]; /* 0x20 - 0x25 MAC address */
- u8 reserved[10];/* 0x26 - 0x2f reserved */
- u32 crc; /* x+1 CRC32 checksum */
-} e;
-
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
-
-/**
- * show_eeprom - display the contents of the EEPROM
- */
-static void show_eeprom(void)
-{
- unsigned int crc;
- char safe_string[16];
-
-#ifdef DEBUG
- int i;
-#endif
- u8 *p;
-
- /* ID */
- strncpy(safe_string, (char *)e.id, sizeof(e.id));
- safe_string[sizeof(e.id)-1] = 0;
- printf("ID: mvBlueLYNX-X%s\n", safe_string);
-
- /* Serial number */
- strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
- safe_string[sizeof(e.sn)-1] = 0;
- printf("SN: %s\n", safe_string);
-
- /* Build date, BCD date values, as YYMMDDhhmmss */
- printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
- e.date[0], e.date[1], e.date[2],
- e.date[3] & 0x7F, e.date[4], e.date[5],
- e.date[3] & 0x80 ? "PM" : "");
-
- /* Show MAC address */
- p = e.mac;
- printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
- p[0], p[1], p[2], p[3], p[4], p[5]);
-
- crc = crc32(0, (void *)&e, sizeof(e) - 4);
-
- if (crc == be32_to_cpu(e.crc))
- printf("CRC: %08x\n", be32_to_cpu(e.crc));
- else
- printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
-
-#ifdef DEBUG
- printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
- for (i = 0; i < sizeof(e); i++) {
- if ((i % 16) == 0)
- printf("%02X: ", i);
- printf("%02X ", ((u8 *)&e)[i]);
- if (((i % 16) == 15) || (i == sizeof(e) - 1))
- printf("\n");
- }
-#endif
-}
-
-/**
- * read_eeprom - read the EEPROM into memory
- */
-static int read_eeprom(void)
-{
- int ret;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- unsigned int bus;
-#endif
-
- if (has_been_read)
- return 0;
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
- ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- (uchar *)&e, sizeof(e));
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- i2c_set_bus_num(bus);
-#endif
-
-#ifdef DEBUG
- show_eeprom();
-#endif
-
- has_been_read = (ret == 0) ? 1 : 0;
-
- return ret;
-}
-
-/**
- * update_crc - update the CRC
- *
- * This function should be called after each update to the EEPROM structure,
- * to make sure the CRC is always correct.
- */
-static void update_crc(void)
-{
- u32 crc;
-
- crc = crc32(0, (void *)&e, sizeof(e) - 4);
- e.crc = cpu_to_be32(crc);
-}
-
-/**
- * prog_eeprom - write the EEPROM from memory
- */
-static int prog_eeprom(void)
-{
- int ret = 0;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- unsigned int bus;
-#endif
-
- update_crc();
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
- ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- (uchar *)&e, sizeof(e));
-
- if (!ret) {
- /* Verify the write by reading back the EEPROM and comparing */
- struct eeprom e2;
-#ifdef DEBUG
- printf("%s verifying...\n", __func__);
-#endif
- ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
- (uchar *)&e2, sizeof(e2));
-
- if (!ret && memcmp(&e, &e2, sizeof(e)))
- ret = -1;
- }
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- i2c_set_bus_num(bus);
-#endif
-
- if (ret) {
- printf("Programming failed.\n");
- has_been_read = 0;
- return -1;
- }
-
- printf("Programming passed.\n");
- return 0;
-}
-
-/**
- * h2i - converts hex character into a number
- *
- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
- * the integer equivalent.
- */
-static inline u8 h2i(char p)
-{
- if ((p >= '0') && (p <= '9'))
- return p - '0';
-
- if ((p >= 'A') && (p <= 'F'))
- return (p - 'A') + 10;
-
- if ((p >= 'a') && (p <= 'f'))
- return (p - 'a') + 10;
-
- return 0;
-}
-
-/**
- * set_date - stores the build date into the EEPROM
- *
- * This function takes a pointer to a string in the format "YYMMDDhhmmss"
- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
- * and stores it in the build date field of the EEPROM local copy.
- */
-static void set_date(const char *string)
-{
- unsigned int i;
-
- if (strlen(string) != 12) {
- printf("Usage: mac date YYMMDDhhmmss\n");
- return;
- }
-
- for (i = 0; i < 6; i++)
- e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
-
- update_crc();
-}
-
-/**
- * set_mac_address - stores a MAC address into the EEPROM
- *
- * This function takes a pointer to MAC address string
- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
- * stores it in the MAC address field in the EEPROM local copy.
- */
-static void set_mac_address(const char *string)
-{
- char *p = (char *) string;
- unsigned int i;
-
- for (i = 0; *p && (i < 6); i++) {
- e.mac[i] = simple_strtoul(p, &p, 16);
- if (*p == ':')
- p++;
- }
-
- update_crc();
-}
-
-int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
-
- if (argc == 1) {
- show_eeprom();
- return 0;
- }
-
- cmd = argv[1][0];
-
- if (cmd == 'r') {
-#ifdef DEBUG
- printf("%s read\n", __func__);
-#endif
- read_eeprom();
- return 0;
- }
-
- if (argc == 2) {
- switch (cmd) {
- case 's': /* save */
-#ifdef DEBUG
- printf("%s save\n", __func__);
-#endif
- prog_eeprom();
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
- }
-
- /* We know we have at least one parameter */
-
- switch (cmd) {
- case 'n': /* serial number */
-#ifdef DEBUG
- printf("%s serial number\n", __func__);
-#endif
- memset(e.sn, 0, sizeof(e.sn));
- strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
- update_crc();
- break;
- case 'd': /* date BCD format YYMMDDhhmmss */
- set_date(argv[2]);
- break;
- case 'e': /* errata */
- printf("mac errata not implemented\n");
- break;
- case 'i': /* id */
- memset(e.id, 0, sizeof(e.id));
- strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
- update_crc();
- break;
- case 'p': /* ports */
- printf("mac ports not implemented (always 1 port)\n");
- break;
- case '0' ... '9':
- /* we only have "mac 0" but any digit can be used here */
- set_mac_address(argv[2]);
- break;
- case 'h': /* help */
- default:
- return cmd_usage(cmdtp);
- }
-
- return 0;
-}
-
-static inline int is_portrait(void)
-{
- int i;
- unsigned int orient_index = 0; /* idx of char which determines orientation */
-
- for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
- if (e.id[i] == '-') {
- orient_index = i+1;
- break;
- }
- }
-
- return (orient_index &&
- (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
-}
-
-int mac_read_from_eeprom(void)
-{
- u32 crc, crc_offset = offsetof(struct eeprom, crc);
- u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
-#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
-#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
-
- if (read_eeprom()) {
- printf("EEPROM Read failed.\n");
- return -1;
- }
-
- crc = crc32(0, (void *)&e, crc_offset);
- crcp = (void *)&e + crc_offset;
- if (crc != be32_to_cpu(*crcp)) {
- printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
- be32_to_cpu(e.crc));
- return -1;
- }
-
- if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
- memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
- char ethaddr[18];
-
- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
- e.mac[0],
- e.mac[1],
- e.mac[2],
- e.mac[3],
- e.mac[4],
- e.mac[5]);
- /* Only initialize environment variables that are blank
- * (i.e. have not yet been set)
- */
- if (!getenv("ethaddr"))
- setenv("ethaddr", ethaddr);
- }
-
- if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
- memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
- char serial_num[12];
-
- strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
- /* Only initialize environment variables that are blank
- * (i.e. have not yet been set)
- */
- if (!getenv("serial#"))
- setenv("serial#", serial_num);
- }
-
- /* decide which fpga file to load depending on orientation */
- if (is_portrait())
- setenv("fpgafilename", FILENAME_PORTRAIT);
- else
- setenv("fpgafilename", FILENAME_LANDSCAPE);
-
- /* TODO should I calculate CRC here? */
- return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
- char *serial = getenv("serial#");
-
- if (serial && (strlen(serial) > 3)) {
- /* use the numerical part of the serial number LXnnnnnn */
- serialnr->high = 0;
- serialnr->low = simple_strtoul(serial + 2, NULL, 10);
- } else {
- serialnr->high = 0;
- serialnr->low = 0;
- }
-}
-#endif
--- /dev/null
+if TARGET_P2371_2180
+
+config SYS_BOARD
+ default "p2371-2180"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "p2371-2180"
+
+endif
--- /dev/null
+P2371-2180 BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p2371-2180/
+F: include/configs/p2371-2180.h
+F: configs/p2371-2180_defconfig
--- /dev/null
+#
+# (C) Copyright 2013-2015
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p2371-2180.o
--- /dev/null
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+#include "pinmux-config-p2371-2180.h"
+
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return;
+ }
+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xF2;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+}
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_clear_tristate_input_clamping();
+
+ gpio_config_table(p2371_2180_gpio_inits,
+ ARRAY_SIZE(p2371_2180_gpio_inits));
+
+ pinmux_config_pingrp_table(p2371_2180_pingrps,
+ ARRAY_SIZE(p2371_2180_pingrps));
+
+ pinmux_config_drvgrp_table(p2371_2180_drvgrps,
+ ARRAY_SIZE(p2371_2180_drvgrps));
+}
--- /dev/null
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py p2371-2180".
+ */
+
+#ifndef _PINMUX_CONFIG_P2371_2180_H_
+#define _PINMUX_CONFIG_P2371_2180_H_
+
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(A5, IN),
+ GPIO_INIT(B0, IN),
+ GPIO_INIT(B1, IN),
+ GPIO_INIT(B2, IN),
+ GPIO_INIT(B3, IN),
+ GPIO_INIT(C0, IN),
+ GPIO_INIT(C1, IN),
+ GPIO_INIT(C2, IN),
+ GPIO_INIT(C3, IN),
+ GPIO_INIT(C4, IN),
+ GPIO_INIT(E4, IN),
+ GPIO_INIT(E5, IN),
+ GPIO_INIT(E6, IN),
+ GPIO_INIT(H0, OUT0),
+ GPIO_INIT(H1, OUT0),
+ GPIO_INIT(H2, IN),
+ GPIO_INIT(H3, OUT0),
+ GPIO_INIT(H4, OUT0),
+ GPIO_INIT(H5, IN),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, IN),
+ GPIO_INIT(I0, OUT0),
+ GPIO_INIT(I1, IN),
+ GPIO_INIT(I2, OUT0),
+ GPIO_INIT(K4, IN),
+ GPIO_INIT(K5, OUT0),
+ GPIO_INIT(K6, IN),
+ GPIO_INIT(K7, IN),
+ GPIO_INIT(L1, IN),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S5, OUT0),
+ GPIO_INIT(S6, OUT0),
+ GPIO_INIT(S7, OUT0),
+ GPIO_INIT(T0, OUT0),
+ GPIO_INIT(T1, OUT0),
+ GPIO_INIT(U2, IN),
+ GPIO_INIT(U3, IN),
+ GPIO_INIT(V1, OUT0),
+ GPIO_INIT(V2, OUT0),
+ GPIO_INIT(V3, IN),
+ GPIO_INIT(V5, OUT0),
+ GPIO_INIT(V6, OUT0),
+ GPIO_INIT(X0, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X2, IN),
+ GPIO_INIT(X3, IN),
+ GPIO_INIT(X4, IN),
+ GPIO_INIT(X5, IN),
+ GPIO_INIT(X6, IN),
+ GPIO_INIT(X7, IN),
+ GPIO_INIT(Y0, IN),
+ GPIO_INIT(Y1, IN),
+ GPIO_INIT(Z0, IN),
+ GPIO_INIT(Z2, IN),
+ GPIO_INIT(Z3, OUT0),
+ GPIO_INIT(BB0, IN),
+ GPIO_INIT(BB2, OUT0),
+ GPIO_INIT(BB3, IN),
+ GPIO_INIT(CC1, IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config p2371_2180_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
+ PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
+ PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
+ PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_P2371_2180_H */
+++ /dev/null
-if TARGET_PALMLD
-
-config SYS_BOARD
- default "palmld"
-
-config SYS_CONFIG_NAME
- default "palmld"
-
-endif
+++ /dev/null
-PALMLD BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/palmld/
-F: include/configs/palmld.h
-F: configs/palmld_defconfig
+++ /dev/null
-#
-# Palm LifeDrive Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := palmld.o
+++ /dev/null
-/*
- * Palm LifeDrive Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of PalmLD */
- gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Set PWM for LCD */
- writel(0x7, PWM_CTRL0);
- writel(0x16c, PWM_PERVAL0);
- writel(0x11a, PWM_PWDUTY0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
-}
+++ /dev/null
-if TARGET_PALMTC
-
-config SYS_BOARD
- default "palmtc"
-
-config SYS_CONFIG_NAME
- default "palmtc"
-
-endif
+++ /dev/null
-PALMTC BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/palmtc/
-F: include/configs/palmtc.h
-F: configs/palmtc_defconfig
+++ /dev/null
-#
-# Palm Tungsten|C Support
-#
-# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := palmtc.o
+++ /dev/null
-/*
- * Palm Tungsten|C Support
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* Arch number of Palm Tungsten|C */
- gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
-
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Set PWM for LCD */
- writel(0x5f, PWM_CTRL1);
- writel(0x3ff, PWM_PERVAL1);
- writel(892, PWM_PWDUTY1);
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
+++ /dev/null
-if TARGET_PALMTREO680
-
-config SYS_BOARD
- default "palmtreo680"
-
-config SYS_CONFIG_NAME
- default "palmtreo680"
-
-endif
+++ /dev/null
-PALMTREO680 BOARD
-#M: Mike Dunn <mikedunn@newsguy.com>
-S: Orphan (since 2014-06)
-F: board/palmtreo680/
-F: include/configs/palmtreo680.h
-F: configs/palmtreo680_defconfig
+++ /dev/null
-#
-# Palm Treo680 Support
-#
-# Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
-#
-# This file is released under the terms of GPL v2 and any later version.
-# See the file COPYING in the root directory of the source tree for details.
-
-obj-y := palmtreo680.o
+++ /dev/null
-
-README for the Palm Treo 680.
-
-Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
-
-You may reproduce the contents of this file entirely or in part, but please
-credit me by name if you do. Thanks.
-
-
-Intro
-=====
-
-Yes, you can program u-boot onto the flash of your Palm Treo 680 so that u-boot
-(then Linux, Android, ...) runs at power-up. This document describes how, and
-gives some implementation details on this port of u-boot and describes how the
-Treo 680 boots from reset.
-
-But first, I probably don't need to tell you that after doing this, your phone
-will no longer run PalmOS. You *may* be able to later restore your phone to its
-original state by creating a backup image of the flash before writing u-boot
-(details below), but this is not heavily tested and should not be relied upon.
-There is also the possibility that something may go wrong during the process of
-programming u-boot, leaving you with a bricked phone. If you follow these
-instructions carefully this chance will be minimized, but I do not recommend
-that you program u-boot onto a phone that you can not afford to lose, and
-certainly not one that contains important data that is not backed up elsewhere.
-I AM NOT RESPONSIBLE FOR THE LOSS OF YOUR PHONE. DO THIS AT YOUR OWN RISK.
-Having said that, feel free to send me a note cursing me out if something does
-go wrong, but please tell me what happened exactly. For that matter, I'd love
-to hear from you if you succeed.
-
-
-Details on the SPL
-==================
-
-The docg4 features a 2k region at the start of its address space that interfaces
-to the system bus like a NOR flash. This allows the docg4 to function as a boot
-ROM. The Treo 680 uses this feature. The contents of this 2k region are
-write-protected and can not be reprogrammed. Fortunately, the code it contains
-does what we need to do, at least partially. After some essential hardware
-initialization (like the SDRAM controller), it runs an IPL (initial program
-loader) that copies 128K (no more, no less) from flash to a fixed address in
-SDRAM (0xa1700000) and jumps to it. 128K is too small for u-boot, so we use it
-to load a u-boot secondary program loader (SPL). But since our SPL only
-occupies a little over 1k, we can economize on flash usage by having the IPL
-load a portion of u-boot proper as well. We let the IPL load the first 128k of
-a concatenated spl + u-boot image, and because the SPL is placed before u-boot
-proper, the IPL jumps to the SPL, which copies the portion of u-boot that the
-IPL has already loaded to its correct SDRAM address, and then loads the
-remainder of u-boot and jumps to it.
-
-
-The docg4's "reliable mode"
-===========================
-
-This is a special mode of operation of the docg4's integrated controller whereby
-consecutive pairs of 2k regions are used in parallel (in some fashion) to store
-2k of data. In other words, the normal capacity is halved, but the data
-integrity is improved. In this mode, the data is read or written from pages in
-even-numbered 2k regions (regions starting at 0x000, 0x1000, 0x2000, ...). The
-odd-numbered 2k regions (regions starting at 0x800, 0x1800, 0x2800, ...) are
-transparently used in parallel. In reliable mode, the odd-numbered 2k regions
-are not meant to be read or written directly.
-
-Reliable mode is used by the IPL because there is not enough space in its 2k
-footprint to implement the BCH ecc algorithm. Data that is read while reliable
-mode is enabled must have been written in reliable mode, or the read fails.
-However, data written in reliable mode can also be read in normal mode (just not
-as reliably), but only from the even-numbered 2k regions; the odd-numbered 2k
-regions appear to contain junk, and will generate ecc errors. When the IPL and
-SPL read from flash, the odd-numbered 2k regions are explicitly skipped. The
-same is true for the flash_u-boot utility when it writes the u-boot image in
-reliable mode.
-
-The docg4 Linux driver supports writing in reliable mode (it is enabled by the
-module parameter), but not reading. However, the u-boot docg4_spl driver does
-read in reliable mode, in the same fashion as the IPL.
-
-
-Details on the IPL and its data format
-======================================
-
-Starting from block 5 and counting upward, the IPL will search for and load the
-first two blocks it finds that contain a magic number in the oob of the first
-page of the block. The contents are loaded to SDRAM starting at address
-0xa1700000. After two blocks have been loaded, it jumps to 0xa1700000. The
-number of blocks loaded and the load address in SDRAM are hard-coded; only the
-flash offset of the blocks can vary at run-time (based on the presence of the
-magic number).
-
-In addition to using the docg4's reliable mode, the IPL expects each 512 byte
-page to be written redundantly in the subsequent page. The hardware is capable
-of detecting bit errors (but not correcting them), and if a bit error is
-detected when a page is read, the page contents are discarded and the subsequent
-page is read.
-
-Reliable mode reduces the capacity of a block by half, and the redundant pages
-reduce it by half again. As a result, the normal 256k capacity of a block is
-reduced to 64k for the purposes of the IPL/SPL.
-
-For the sake of simplicity and uniformity, the u-boot SPL mimics the operation
-of the IPL, and expects the image to be stored in the same format.
-
-
-Instructions on Programming u-boot to flash
-===========================================
-
-To program u-boot to your flash, you will need to boot the Linux kernel on your
-phone using a PalmOS bootloader such as cocoboot. The details of building and
-running Linux on your Treo (cross-compiling, creating a root filesystem,
-configuring the kernel, etc) are beyond the scope of this document. The
-remainder of this document describes in detail how to program u-boot to the
-flash using Linux running on the Treo.
-
-
-Hardware Prerequisites
-======================
-
-A Palm Treo 680:
- (dugh)
-
-A Palm usb cable:
- You'll need this to establish a usbtty console connection to u-boot from a
- desktop PC. Currently there is no support in u-boot for the pxa27x keypad
- (coming soon), so a serial link must be used for the console.
- These cables are still widely available if you don't already have one.
-
-A Linux desktop PC.
- You may be able to use Windows for the u-boot console if you have a usb driver
- that is compatible with the Linux usbserial driver, but for programming u-boot
- to flash, you'll really want to use a Linux PC.
-
-
-Treo-side Software Prerequisites
-================================
-
-Linux bootloader for PalmOS:
-
- Cocoboot is the only one I'm aware of. If you don't already have this, you
- can download it from
- https://download.enlightenment.org/misc/Illume/Treo-650/2008-11-13/sdcard-base.tar.gz
- which is a compressed tar archive of the contents of an sd card containing
- cocoboot. Use mkdosfs to create a fat16 filesystem on the first primary
- partition of the card, mount the partition, and extract the tar file to it.
- You will probably need to edit the cocoboot.conf file to customize the
- parameters passed to the kernel.
-
-
-Linux kernel:
-
- The kernel on the Treo 680 is still a little rough around the edges, and the
- official kernel frequently breaks on the Treo :( A development kernel
- specifically for the Treo 680 can be found on github:
- http://github.com/mike-dunn/linux-treo680
- The master branch of this tree has been tested on the Treo, and I recommend
- using this kernel for programming u-boot. As of this writing, there may be a
- bug in the docg4 nand flash driver that sometimes causes block erasures to
- fail. This has been fixed in the above tree.
-
- If you choose to use the official kernel, it must contain the docg4 driver that
- includes the reliable_mode module parameter. This was a later enhancement to
- the driver, and was merged to the kernel as of v3.8. Do not try to use an
- earlier kernel that contains the docg4 driver without support for writing in
- reliable mode. If you try to program u-boot to flash with the docg4 driver
- loaded without the reliable_mode parameter enabled, you *will* brick your
- phone!
-
- For the purpose of programming u-boot to flash, the following options must be
- enabled in the Treo kernel's .config:
-
- CONFIG_MTD=y
- CONFIG_MTD_CMDLINE_PARTS=y
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_NAND_DOCG4=m
-
- Note that the docg4 nand driver is configured as a module, because we will
- want to load and unload it with reliable_mode enabled or disabled as needed.
-
- You will also need to specify mtd partitions on the kernel command line. In
- the instructions that follow, we will assume that the flash blocks to which
- u-boot will be programmed are defined by the second partition on the device.
- The u-boot config file (include/configs/palmtreo680.h) places the u-boot image
- at the start of block 6 (offset 0x180000), which is the first writable
- (non-protected) block on the flash (this is also where the PalmOS SPL starts).
- The u-boot image occupies four blocks, so to create the u-boot partition, pass
- this command line to the kernel:
- mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part)
- This will create three partitions:
- protected_part: the first six blocks, which are read-only
- bootloader_part: the next four blocks, for the u-boot image
- filesys_part: the remainder of the device
- The mtdchar kernel device driver will use device nodes /dev/mtd0, /dev/mtd1,
- and /dev/mtd2 for these partitions, respectively. Ensure that your root file
- system at least has /dev/mtd1 if you are not running udev or mdev.
-
-Userspace Utilities:
-
- In addition to everything necessary to provide a useful userspace environment
- (busybox is indispensable, of course), you will need the mtd-utils package on
- your root filesystem. I use version 1.5.0 of mtd-utils, and I suggest you use
- this version as well, or at leat a version very close to this one, as
- mtd-utils has tended to be fluid.
-
- Note that busybox includes a version of mtd-utils. These are deficient and
- should not be used. When you run one of these utilities (nanddump, etc),
- ensure you are invoking the separate executable from mtd-utils, and not the
- one built into busybox. I recommend that you configure busybox with its
- mtd-utils disabled to avoid any possibility of confusion.
-
- You will also need to cross-compile the userspace Linux utility in
- tools/palmtreo680/flash_u-boot.c, which we will run on the Treo to perform the
- actual write of the u-boot image to flash. This utility links against libmtd
- from the mtd-utils package.
-
-
-Desktop PC-side Software Prerequisites
-======================================
-
-Terminal emulator application:
- minicom, kermit, etc.
-
-Linux kernel:
- Compiled with CONFIG_USB_SERIAL enabled. Build this as a module.
-
-
-Recommended (Not directly related to u-boot)
-============================================
-
-Working directly on the Treo's tiny screen and keypad is difficult and
-error-prone. I recommend that you log into the Linux kernel running on your
-Treo from your desktop PC using ethernet over usb. The desktop's kernel must be
-configured with CONFIG_USB_USBNET, CONFIG_USB_NET_CDCETHER, and
-CONFIG_USB_NET_CDC_SUBSET. The Treo's kernel will need CONFIG_USB_ETH, and its
-init script will need to start an ssh daemon like dropbear. Note that the usb0
-network interface will not appear on the desktop PC until the Treo kernel's usb
-ethernet gadget driver has initialized. You must wait for this to occur (watch
-the PC's kernel log) before you can assign usb0 an ip address and log in to the
-Treo. If you also build the Treo's kernel with CONFIG_IP_PNP enabled, you can
-pass its ip address on the kernel command line, and obviate the need to
-initialize the network interface in your init script.
-
-Having the Palm usb cable connected to the host has the added benefit of keeping
-power supplied to your Treo, reducing the drain on the battery. If something
-goes wrong while you're programming u-boot to the flash, you will have lots of
-time to correct it before the battery dies.
-
-I have encountered a situation where the kernel is sometimes unable to mount a
-root filesystem on the mmc card due to the mmc controller not initializing in
-time, (and CONFIG_MMC_UNSAFE_RESUME doesn't seem to help) so I recommend that
-you build a minimal root filesystem into the kernel using the kernel's initramfs
-feature (CONFIG_BLK_DEV_INITRD). If you want your root filesystem on the mmc
-card, your init script can mount and switch_root to the mmc card after a short
-sleep. But keep in mind that in this case you won't be able to use an mmc card
-to transfer files between your desktop and the Treo once Linux is running.
-Another option for transfering files is to mount an nfs filesystem exported by
-the desktop PC. For greatest convenience, you can export the root filesystem
-itself from your desktop PC and switch_root to it in your init script. This
-will work if your initramfs init script contains a loop that waits for you to
-initialize the usb0 network interface on the desktop PC; e.g., loop while a ping
-to the desktop PC returns an error. After the loop exits, do the nfs mount and
-call switch_root. (You can not use the kernel nfsroot feature because the
-network will not be up when the kernel expects it to be; i.e., not until you
-configure the usb0 interface on the desktop.) Use the nfs 'nolock' option when
-mounting to avoid the need to run a portmapper like rpcbind.
-
-
-Preliminaries
-=============
-
-Once Linux is running on your Treo, you may want to perform a few sanity checks
-before programming u-boot. These checks will verify my assumptions regarding
-all the Treo 680s out there, and also ensure that the flash and mtd-utils are
-working correctly. If you are impatient and reckless, you may skip this
-section, but see disclaimer at the top of this file!
-
-Load the docg4 driver:
-
- $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
-
-We tell the driver to use the docg4's "reliable mode" when writing because this
-is the format required by the IPL, which runs from power-up and loads the first
-portion of u-boot. We must ignore bad blocks because linux mtd uses out-of-band
-(oob) bytes to mark bad blocks, which will cause the blocks written by PalmOS to
-be misidentified as "bad" by libmtd.
-
-Check the kernel log to ensure that all's well:
-
- $ dmesg | tail
- <... snip ...>
- docg4 docg4: NAND device: 128MiB Diskonchip G4 detected
- 3 cmdlinepart partitions found on MTD device Msys_Diskonchip_G4
- Creating 3 MTD partitions on "Msys_Diskonchip_G4":
- 0x000000000000-0x000000180000 : "protected_part"
- 0x000000180000-0x000000280000 : "bootloader_part"
- 0x000000280000-0x000008000000 : "filesys_part"
-
-Ensure that the partition boundaries are as shown. (If no partitions are shown,
-did you remember to pass them to the kernel on the command line?) We will write
-u-boot to bootloader_part, which starts at offset 0x180000 (block 6) and spans 4
-256k blocks. This partition is accessed through the device node /dev/mtd1.
-
-The docg4 contains a read-only table that identifies blocks that were marked as
-bad at the factory. This table is in the page at offset 0x2000, which is within
-the partition protected_part (/dev/mtd0). There is a slight chance that one or
-more of the four blocks that we will use for u-boot is listed in the table, so
-use nanddump to inspect the table to see if this is the case:
-
- $ nanddump -p -l 512 -s 0x2000 -o /dev/mtd0
- ECC failed: 0
- ECC corrected: 0
- Number of bad blocks: 0
- Number of bbt blocks: 0
- Block size 262144, page size 512, OOB size 16
- Dumping data starting at 0x00002000 and ending at 0x00002200...
- 0x00002000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
- <... snip ...>
-
-The format of the table is simple: one bit per block, with block numbers
-increasing from left to right, starting with block 0 as the most significant bit
-of the first byte. A bit will be clear if the corresponding block is bad. We
-want to use blocks 6 throgh 9, so both of the two least significant bits of the
-first byte must be set, as must the two most significant bits of the second
-byte. If this is not true in your case (you are very unlucky), you should use
-the first contiguous set of four good blocks after block 6, and adjust the
-partition boundaries accordingly. You will also have to change the value of
-CONFIG_SYS_NAND_U_BOOT_OFFS in include/configs/palmtreo680.h and recompile
-u-boot. Because the two blocks loaded by the IPL do not have to be contiguous,
-but our SPL expects them to be, you will need to erase any good blocks that are
-at an offset prior to CONFIG_SYS_NAND_U_BOOT_OFFS, so that the IPL does not find
-the magic number in oob and load it. Once you have done all this, the
-instructions in this file still apply, except that the instructions below for
-restoring the original PalmOS block contents may need to be modified.
-
-Next, use nanddump to verify that the PalmOS SPL is where we expect it to be.
-The SPL can be identified by a magic number in the oob bytes of the first page
-of each of the two blocks containing the SPL image. Pages are 512 bytes in
-size, so to dump the first page, plus the oob:
-
- $ nanddump -p -l 512 -s 0 -o /dev/mtd1
- ECC failed: 0
- ECC corrected: 0
- Number of bad blocks: 0
- Number of bbt blocks: 0
- Block size 262144, page size 512, OOB size 16
- Dumping data starting at 0x00000000 and ending at 0x00000200...
- 0x00000000: 0a 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
- <... snip ...>
- 0x000001f0: 13 4c 21 60 13 4d 2a 69 13 4b 29 69 89 1a 99 42
- OOB Data: 42 49 50 4f 30 30 30 10 3a e2 00 92 be a0 11 ff
-
-Verify that the first seven bytes of oob data match those in the above line.
-(This is ASCII "BIPO000".)
-
-Do the same for the next block:
- $ nanddump -p -l 512 -s 0x40000 -o /dev/mtd1
-
-The first seven oob bytes in last line should read:
-
- OOB Data: 42 49 50 4f 30 30 31 81 db 8e 8f 46 07 9b 59 ff
-
-(This is ASCII "BIPO001".)
-
-For additional assurance, verify that the next block does *not* contain SPL
-data.
-
- $ nanddump -p -l 512 -s 0x80000 -o /dev/mtd1
-
-It doesn't matter what the oob contains, as long as the first four bytes are
-*not* ASCII "BIPO". PalmOS should only be using two blocks for the SPL
-(although we will need four for u-boot).
-
-If you want, you can back up the contents of bootloader_part to a file. You may
-be able to restore it later, if desired (see "Restoring PalmOS" below).
-
- $ nanddump -l 0x100000 -s 0 -o -f bootloader_part.orig /dev/mtd1
-
-nanddump will spew voluminous warnings about uncorrectable ecc errors. This is
-a consequence of reading pages that were written in reliable mode, and is
-expected (these should all occur on pages in odd-numbered 2k regions; i.e.,
-0x800, 0xa00, 0xc00, 0xe00, 0x1800, 0x1a00, ...). The size of the file
-bootloader_part.orig should be 1081344, which is 2048 pages, each of size 512
-plus 16 oob bytes. If you are using initramfs for the root filesystem, don't
-forget to copy the file to permanent storage, such as an mmc card.
-
-If all of the above went well, you can now program u-boot.
-
-
-Programming u-boot
-==================
-
-Our u-boot includes a small SPL that must be prepended to u-boot proper. From
-the base u-boot source directory on your desktop PC:
-
- $ cat spl/u-boot-spl.bin u-boot.bin > u-boot-concat.bin
-
-cd to the tools/palmtreo680/ directory, and cross-compile flash_u-boot.c for the
-Treo:
-
- $(CC) -o flash_u-boot $(CFLAGS) $(INCLUDEPATH) $(LIBPATH) flash_u-boot.c -lmtd
-
-Substitute variable values from your cross-compilation environment as
-appropriate. Note that it links to libmtd from mtd-utils, and this must be
-included in $(LIBPATH) and $(INCLUDEPATH).
-
-Transfer u-boot-concat.bin and the compiled flash_u-boot utility to the Treo's
-root filesystem. On the Treo, cd to the directory where these files were
-placed.
-
-Load the docg4 driver if you have not already done so.
-
- $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
-
-Erase the blocks to which we will write u-boot:
-
- $ flash_erase /dev/mtd1 0x00 4
-
-If no errors are reported, write u-boot to the flash:
-
- $ ./flash_u-boot u-boot-concat.bin /dev/mtd1
-
-You can use nanddump (see above) to verify that the data was written. This
-time, "BIPO" should be seen in the first four oob bytes of the first page of all
-four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000.
-
-Shutdown linux, remove and re-insert the battery, hold your breath...
-
-
-Enjoying u-boot
-===============
-
-After you insert the battery, the u-boot splash screen should appear on the lcd
-after a few seconds. With the usb cable connecting the Treo to your PC, in the
-kernel log of your PC you should see
-
- <6>usb 3-1: New USB device found, idVendor=0525, idProduct=a4a6
- <6>usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
- <6>usb 3-1: Product: U-Boot 2013.01-00167-gd62ef56-dirty
- <6>usb 3-1: Manufacturer: Das U-Boot
-
-Load the usbserial module on your desktop PC:
-
- $ modprobe usbserial vendor=0x0525 product=0xa4a6
-
-and run your favorite terminal emulation utility (minicom, kermit, etc) with the
-serial device set to /dev/ttyUSB0 (assuming this is your only usb serial
-device). You should be at the u-boot console (type 'help').
-
-There is not much that is unique about using u-boot on the palm treo 680.
-Kernels can be loaded from mmc, flash, and from the desktop PC via kermit. You
-can expand the size of the second partition on the flash to contain a kernel, or
-else put the kernel(s) in their own partition.
-
-Nand commands work as expected, with the excepton that blocks not written by the
-linux mtd subsystem may be misidentified by the u-boot docg4 driver as "bad" if
-they contain data in the oob bytes. This will be the case for the blocks
-containing the u-boot image, for example. To work around this, use 'nand scrub'
-instead of 'nand erase' to erase these blocks, and 'nand read.raw' to read them
-to memory. (It would be useful if u-boot's nand commands provided a way to
-explicitly ignore "bad" blocks, because read.raw does not perform ecc.) The
-'nand dump' command will read these "bad" blocks, however.
-
-Currently u-boot itself can only be programmed to flash from Linux; there is no
-support for reliable mode in u-boot's docg4 flash driver. This should be
-corrected soon.
-
-
-Customizing
-===========
-
-If you change u-boot's configuration significantly (adding or removing
-features), you may have to adjust the value of CONFIG_SYS_NAND_U_BOOT_SIZE.
-This is the size of the concatenated spl + u-boot image, and tells the SPL how
-many flash blocks it needs to load. It will be rounded up to the next 64k
-boundary (the spl flash block capacity), so it does not have to be exact, but
-you must ensure that it is not less than the actual image size. If it is larger
-than the image, blocks may be needlessly loaded, but if too small, u-boot may
-only be partially loaded, resulting in a boot failure (bricked phone), so better
-to be too large. The flash_u-boot utility will work with any size image and
-write the required number of blocks, provided that the partition is large
-enough.
-
-As the first writable block on the device, block 6 seems to make the most sense
-as the flash offset for writing u-boot (and this is where PalmOS places its
-SPL). But you can place it elsewhere if you like. If you do, you need to
-adjust CONFIG_SYS_NAND_U_BOOT_OFFS accordingly, and you must ensure that blocks
-preceeding the ones containing u-boot do *not* have the magic number in oob (the
-IPL looks for this). In other words, make sure that any blocks that previously
-contained the u-boot image or PalmOS SPL are erased (and optionally written with
-something else) so that the IPL does not load it. Also make sure that the new
-u-boot starting offset is at the start of a flash partition (check the kernel
-log after loading the docg4 driver), and pass the corresponding mtd device file
-to the flash_u-boot utility.
-
-The u-boot built-in default environment is used because a writable environment
-in flash did not seem worth the cost of a 256k flash block. But adding this
-should be straightforward.
-
-
-Restoring PalmOS
-================
-
-If you backed up the contents of bootloader_part flash partition earlier, you
-should be able to restore it with the shell script shown below. The first two
-blocks of data contain the PalmOS SPL and were written in reliable mode, whereas
-the next two blocks were written in normal mode, so the script has to load and
-unload the docg4 driver. Make sure that the mtd-utils nandwrite and flash_erase
-are in your path (and are not those from busybox). Also double-check that the
-backup image file bootloader_part.orig is exactly 1081344 bytes in length. If
-not, it was not backed up correctly. Run the script as:
-
- ./restore_bootpart bootloader_part.orig /dev/mtd1
-
-The script will take a minute or so to run. When it finishes, you may want to
-verify with nanddump that the data looks correct before you cycle power, because
-if the backup or restore failed, your phone will be bricked. Note that as a
-consequence of reliable mode, the odd-numbered 2k regions in the first two
-blocks will not exactly match the contents of the backup file, (so unfortunately
-we can't simply dump the flash contents to a file and do a binary diff with the
-original back-up image to verify that it was restored correctly). Also,
-nanddump will report uncorrectable ecc errors when it reads those regions.
-
-#!/bin/sh
-
-if [ $# -ne 2 ]; then
- echo "usage: $0: <image file> <mtd device node>"
- exit 1
-fi
-
-# reliable mode used for the first two blocks
-modprobe -r docg4
-modprobe docg4 ignore_badblocks=1 reliable_mode=1 || exit 1
-
-# erase all four blocks
-flash_erase $2 0 4
-
-# Program the first two blocks in reliable mode.
-# 2k (4 pages) is written at a time, skipping alternate 2k regions
-# Note that "2k" is 2112 bytes, including 64 oob bytes
-file_ofs=0
-flash_ofs=0
-page=0
-while [ $page -ne 1024 ]; do
- dd if=$1 bs=2112 skip=$file_ofs count=1 | nandwrite -o -n -s $flash_ofs $2 - || exit 1
- file_ofs=$((file_ofs+2))
- flash_ofs=$((flash_ofs+0x1000))
- page=$((page+8))
-done;
-
-# normal mode used for the next two blocks
-modprobe -r docg4
-modprobe docg4 ignore_badblocks=1 || exit 1
-dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1
-modprobe -r docg4
-
-TODO
-====
-
- - Keypad support.
- - Interactive boot menu using keypad and lcd.
- - Add reliable mode support to the u-boot docg4 driver.
- - U-boot command that will write a new image to the bootloader partition in
- flash.
- - Linux FTD support.
+++ /dev/null
-/*
- * Palm Treo 680 Support
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <nand.h>
-#include <malloc.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch-pxa/pxa.h>
-#include <asm/arch-pxa/regs-mmc.h>
-#include <asm/io.h>
-#include <asm/global_data.h>
-#include <u-boot/crc.h>
-#include <linux/mtd/docg4.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct nand_chip docg4_nand_chip;
-
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
- gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- /* IPL initializes SDRAM (we're already running from it) */
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_LCD
-void lcd_enable(void)
-{
- /*
- * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
- * driver code. We need it as an output gpio.
- */
- writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
-
- /* power-up and enable the lcd */
- writel(0x00400000, GPSR(86)); /* enable; drive high */
- writel(0x00002000, GPSR(77)); /* power; drive high */
- writel(0x02000000, GPCR(25)); /* enable_n; drive low */
-
- /* turn on LCD backlight and configure PWM for reasonable brightness */
- writel(0x00, PWM_CTRL0);
- writel(0x1b1, PWM_PERVAL0);
- writel(0xfd, PWM_PWDUTY0);
- writel(0x00000040, GPSR(38)); /* backlight power on */
-}
-#endif
-
-#ifdef CONFIG_MMC
-int board_mmc_init(bd_t *bis)
-{
- writel(1 << 10, GPSR(42)); /* power on */
- return pxa_mmc_register(0);
-}
-#endif
-
-void board_nand_init(void)
-{
- /* we have one 128M diskonchip G4 */
-
- struct mtd_info *mtd = &nand_info[0];
- struct nand_chip *nand = &docg4_nand_chip;
- if (docg4_nand_init(mtd, nand, 0))
- hang();
-}
-
-#ifdef CONFIG_SPL_BUILD
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- extern const void *_start, *_end; /* boundaries of spl in memory */
-
- /* size of spl; ipl loads this, and then a portion of u-boot */
- const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
-
- /* the flash offset of the blocks that are loaded by the spl */
- const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
- DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
-
- /* total number of bytes loaded by IPL */
- const size_t ipl_load_size =
- DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
-
- /* number of bytes of u-boot proper that was loaded by the IPL */
- const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
-
- /* number of remaining bytes of u-boot that the SPL must load */
- const size_t spl_load_size =
- CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
-
- /* memory address where we resume loading u-boot */
- void *const load_addr =
- (void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
-
- /*
- * Copy the portion of u-boot already read from flash by the IPL to its
- * correct load address.
- */
- memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
-
- /*
- * Resume loading u-boot where the IPL left off.
- */
- nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
-
-#ifdef CONFIG_NAND_ENV_DST
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST);
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
-#endif
-#endif
- /*
- * Jump to U-Boot image
- */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- (*uboot)();
-}
-
-void board_init_f(ulong bootflag)
-{
- nand_boot();
-}
-
-#endif /* CONFIG_SPL_BUILD */
--- /dev/null
+if TARGET_PCM052
+
+config SYS_BOARD
+ default "pcm052"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_SOC
+ default "vf610"
+
+config SYS_CONFIG_NAME
+ default "pcm052"
+
+endif
--- /dev/null
+PCM052 BOARD
+M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
+S: Maintained
+F: board/phytec/pcm052/
+F: include/configs/pcm052.h
+F: configs/pcm052_defconfig
--- /dev/null
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pcm052.o
--- /dev/null
+/*
+ * Copyright 2015 3ADEV <http://www.3adev.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
+ * do not match our settings. Let us (re)define our own settings here.
+ */
+
+#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm
+#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \
+ PAD_CTL_INPUT_DIFFERENTIAL)
+#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \
+ PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_INPUT_DIFFERENTIAL)
+
+enum {
+ PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
+ PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
+ PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
+ PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
+ PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+ PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
+};
+
+static struct ddrmc_cr_setting pcm052_cr_settings[] = {
+ /* not in the datasheets, but in the original code */
+ { 0x00002000, 105 },
+ { 0x00000020, 110 },
+ /* AXI */
+ { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
+ { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+ { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+ DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+ { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+ DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+ { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+ { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+ DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+ { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+ { DDRMC_CR126_PHY_RDLAT(11), 126 },
+ { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
+ { DDRMC_CR137_PHYCTL_DL(2), 137 },
+ { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) |
+ DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+ { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1) |
+ DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+ DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
+ { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
+ { DDRMC_CR158_TWR(6), 158 },
+ { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
+ DDRMC_CR161_TODTH_WR(6), 161 },
+ /* end marker */
+ { 0, -1 }
+};
+
+/* PHY settings -- most of them differ from default in imx-regs.h */
+
+#define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
+#define PCM052_DDRMC_PHY_CTRL 0x00290000
+#define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
+#define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
+
+static struct ddrmc_phy_setting pcm052_phy_settings[] = {
+ { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
+ { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
+ { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
+ { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
+ { DDRMC_PHY_DQS_TIMING, 1 },
+ { DDRMC_PHY_DQS_TIMING, 17 },
+ { DDRMC_PHY_DQS_TIMING, 33 },
+ { DDRMC_PHY_DQS_TIMING, 49 },
+ { PCM052_DDRMC_PHY_CTRL, 2 },
+ { PCM052_DDRMC_PHY_CTRL, 18 },
+ { PCM052_DDRMC_PHY_CTRL, 34 },
+ { DDRMC_PHY_MASTER_CTRL, 3 },
+ { DDRMC_PHY_MASTER_CTRL, 19 },
+ { DDRMC_PHY_MASTER_CTRL, 35 },
+ { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
+ { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
+ { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
+ { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
+ { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
+
+ /* end marker */
+ { 0, -1 }
+};
+
+int dram_init(void)
+{
+ static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+ .tinit = 5,
+ .trst_pwron = 80000,
+ .cke_inactive = 200000,
+ .wrlat = 5,
+ .caslat_lin = 12,
+ .trc = 6,
+ .trrd = 4,
+ .tccd = 4,
+ .tbst_int_interval = 4,
+ .tfaw = 18,
+ .trp = 6,
+ .twtr = 4,
+ .tras_min = 15,
+ .tmrd = 4,
+ .trtp = 4,
+ .tras_max = 14040,
+ .tmod = 12,
+ .tckesr = 4,
+ .tcke = 3,
+ .trcd_int = 6,
+ .tras_lockout = 1,
+ .tdal = 10,
+ .bstlen = 3,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 1542,
+ .trfc = 64,
+ .tref_int = 5,
+ .tpdex = 3,
+ .txpdll = 10,
+ .txsnr = 68,
+ .txsr = 506,
+ .cksrx = 5,
+ .cksre = 5,
+ .freq_chg_en = 1,
+ .zqcl = 256,
+ .zqinit = 512,
+ .zqcs = 64,
+ .ref_per_zq = 64,
+ .zqcs_rotate = 1,
+ .aprebit = 10,
+ .cmd_age_cnt = 255,
+ .age_cnt = 255,
+ .q_fullness = 0,
+ .odt_rd_mapcs0 = 1,
+ .odt_wr_mapcs0 = 1,
+ .wlmrd = 40,
+ .wldqsen = 25,
+ };
+
+ static const iomux_v3_cfg_t pcm052_pads[] = {
+ PCM052_VF610_PAD_DDR_A15__DDR_A_15,
+ PCM052_VF610_PAD_DDR_A14__DDR_A_14,
+ PCM052_VF610_PAD_DDR_A13__DDR_A_13,
+ PCM052_VF610_PAD_DDR_A12__DDR_A_12,
+ PCM052_VF610_PAD_DDR_A11__DDR_A_11,
+ PCM052_VF610_PAD_DDR_A10__DDR_A_10,
+ PCM052_VF610_PAD_DDR_A9__DDR_A_9,
+ PCM052_VF610_PAD_DDR_A8__DDR_A_8,
+ PCM052_VF610_PAD_DDR_A7__DDR_A_7,
+ PCM052_VF610_PAD_DDR_A6__DDR_A_6,
+ PCM052_VF610_PAD_DDR_A5__DDR_A_5,
+ PCM052_VF610_PAD_DDR_A4__DDR_A_4,
+ PCM052_VF610_PAD_DDR_A3__DDR_A_3,
+ PCM052_VF610_PAD_DDR_A2__DDR_A_2,
+ PCM052_VF610_PAD_DDR_A1__DDR_A_1,
+ PCM052_VF610_PAD_DDR_A0__DDR_A_0,
+ PCM052_VF610_PAD_DDR_BA2__DDR_BA_2,
+ PCM052_VF610_PAD_DDR_BA1__DDR_BA_1,
+ PCM052_VF610_PAD_DDR_BA0__DDR_BA_0,
+ PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B,
+ PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0,
+ PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0,
+ PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0,
+ PCM052_VF610_PAD_DDR_D15__DDR_D_15,
+ PCM052_VF610_PAD_DDR_D14__DDR_D_14,
+ PCM052_VF610_PAD_DDR_D13__DDR_D_13,
+ PCM052_VF610_PAD_DDR_D12__DDR_D_12,
+ PCM052_VF610_PAD_DDR_D11__DDR_D_11,
+ PCM052_VF610_PAD_DDR_D10__DDR_D_10,
+ PCM052_VF610_PAD_DDR_D9__DDR_D_9,
+ PCM052_VF610_PAD_DDR_D8__DDR_D_8,
+ PCM052_VF610_PAD_DDR_D7__DDR_D_7,
+ PCM052_VF610_PAD_DDR_D6__DDR_D_6,
+ PCM052_VF610_PAD_DDR_D5__DDR_D_5,
+ PCM052_VF610_PAD_DDR_D4__DDR_D_4,
+ PCM052_VF610_PAD_DDR_D3__DDR_D_3,
+ PCM052_VF610_PAD_DDR_D2__DDR_D_2,
+ PCM052_VF610_PAD_DDR_D1__DDR_D_1,
+ PCM052_VF610_PAD_DDR_D0__DDR_D_0,
+ PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B,
+ PCM052_VF610_PAD_DDR_WE__DDR_WE_B,
+ PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
+ PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0,
+ PCM052_VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+
+ ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
+ pcm052_phy_settings, 1, 2);
+
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+static void setup_iomux_enet(void)
+{
+ static const iomux_v3_cfg_t enet0_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+/*
+ * I2C2 is the only I2C used, on pads PTA22/PTA23.
+ */
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ VF610_PAD_PTA22__I2C2_SCL,
+ VF610_PAD_PTA23__I2C2_SDA,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+ static const iomux_v3_cfg_t nfc_pads[] = {
+ VF610_PAD_PTD31__NF_IO15,
+ VF610_PAD_PTD30__NF_IO14,
+ VF610_PAD_PTD29__NF_IO13,
+ VF610_PAD_PTD28__NF_IO12,
+ VF610_PAD_PTD27__NF_IO11,
+ VF610_PAD_PTD26__NF_IO10,
+ VF610_PAD_PTD25__NF_IO9,
+ VF610_PAD_PTD24__NF_IO8,
+ VF610_PAD_PTD23__NF_IO7,
+ VF610_PAD_PTD22__NF_IO6,
+ VF610_PAD_PTD21__NF_IO5,
+ VF610_PAD_PTD20__NF_IO4,
+ VF610_PAD_PTD19__NF_IO3,
+ VF610_PAD_PTD18__NF_IO2,
+ VF610_PAD_PTD17__NF_IO1,
+ VF610_PAD_PTD16__NF_IO0,
+ VF610_PAD_PTB24__NF_WE_B,
+ VF610_PAD_PTB25__NF_CE0_B,
+ VF610_PAD_PTB27__NF_RE_B,
+ VF610_PAD_PTC26__NF_RB_B,
+ VF610_PAD_PTC27__NF_ALE,
+ VF610_PAD_PTC28__NF_CLE
+ };
+
+ imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+static void setup_iomux_qspi(void)
+{
+ static const iomux_v3_cfg_t qspi0_pads[] = {
+ VF610_PAD_PTD0__QSPI0_A_QSCK,
+ VF610_PAD_PTD1__QSPI0_A_CS0,
+ VF610_PAD_PTD2__QSPI0_A_DATA3,
+ VF610_PAD_PTD3__QSPI0_A_DATA2,
+ VF610_PAD_PTD4__QSPI0_A_DATA1,
+ VF610_PAD_PTD5__QSPI0_A_DATA0,
+ VF610_PAD_PTD7__QSPI0_B_QSCK,
+ VF610_PAD_PTD8__QSPI0_B_CS0,
+ VF610_PAD_PTD9__QSPI0_B_DATA3,
+ VF610_PAD_PTD10__QSPI0_B_DATA2,
+ VF610_PAD_PTD11__QSPI0_B_DATA1,
+ VF610_PAD_PTD12__QSPI0_B_DATA0,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
+}
+
+#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* eSDHC1 is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t esdhc1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+ };
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+
+static void clock_init(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+ clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+ CCM_CCGR0_UART1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+ CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+ CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+ CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+ CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+ CCM_CCGR2_QSPI0_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+ CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+ CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+ CCM_CCGR4_GPC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+ CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+ CCM_CCGR7_SDHC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+ CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+ CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK);
+
+ clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+ ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+ clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+ ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+ clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+ CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+ clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+ CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+ CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+ CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+ CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+ CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+ CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+ clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+ CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+ CCM_CACRR_ARM_CLK_DIV(0));
+ clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+ CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
+ CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+ CCM_CSCMR1_NFC_CLK_SEL(0));
+ clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+ CCM_CSCDR1_RMII_CLK_EN);
+ clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+ CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+ CCM_CSCDR2_NFC_EN);
+ clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+ CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+ CCM_CSCDR3_QSPI0_X2_DIV(1) |
+ CCM_CSCDR3_QSPI0_X4_DIV(3) |
+ CCM_CSCDR3_NFC_PRE_DIV(5));
+ clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+ CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+ struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ clock_init();
+ mscm_init();
+ setup_iomux_uart();
+ setup_iomux_enet();
+ setup_iomux_i2c();
+ setup_iomux_qspi();
+ setup_iomux_nfc();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /*
+ * Enable external 32K Oscillator
+ *
+ * The internal clock experiences significant drift
+ * so we must use the external oscillator in order
+ * to maintain correct time in the hwclock
+ */
+ setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: PCM-052\n");
+
+ return 0;
+}
+++ /dev/null
-if TARGET_PXA255_IDP
-
-config SYS_BOARD
- default "pxa255_idp"
-
-config SYS_CONFIG_NAME
- default "pxa255_idp"
-
-endif
+++ /dev/null
-PXA255_IDP BOARD
-M: Cliff Brake <cliff.brake@gmail.com>
-S: Maintained
-F: board/pxa255_idp/
-F: include/configs/pxa255_idp.h
-F: configs/pxa255_idp_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pxa_idp.o
+++ /dev/null
-Tested:
-
-- MMC
-- Ethernet
-- BL console (on serial port connector J5)
-- flash support
-
-Todo:
-
-- display support
-- PCMCIA support
+++ /dev/null
-Notes on the Vibren PXA255 IDP.
-
-Chip select usage:
-
-CS0 - flash
-CS1 - alt flash (Mdoc or main flash)
-CS2 - high speed expansion bus
-CS3 - Media Q, low speed exp bus
-CS4 - low speed exp bus
-CS5 - low speed exp bus
- - IDE: offset 0x03000000 (abs: 0x17000000)
- - Eth: offset 0x03400000 (abs: 0x17400000)
- - core voltage latch: offset 0x03800000 (abs: 0x17800000)
- - CPLD: offset 0x03C00000 (abs: 0x17C00000)
-
-PCMCIA Power control
-
-MAX1602EE w/ code pulled high (Cirrus code)
-vx = 5v
-vy = 3v
-
- Bit pattern
- PWR 3,2,1,0
-vcc vpp A1VCC A0VCC A1VPP A0VPP
-=====================================================
-0 0 0 0 0 0 0x0
-3 (vy) 0 1 0 1 1 0xB
-3 (vy) 3 (vy) 1 0 0 1 0x9
-3 (vy) 12(12in) 1 0 1 0 0xA
-5 (vx) 0 0 1 1 1 0x7
-5 (vx) 5 (vx) 0 1 0 1 0x5
-5 (vx 12(12in) 0 1 1 0 0x6
-
-Display power sequencing:
-
-- VDD applied
-- within 1sec, activate scanning signals
-- wait at least 50mS - scanning signals must be active before activating DISP
-
-Signal mapping:
-Schematic LV8V31 signal name
-=========================================
-LCD_ENAVLCD DISP
-LCD_PWR Applies VDD to board
-
-Both of the above signals are controlled by the CPLD
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2004
- * BEC Systems <http://bec-systems.com>
- * Cliff Brake <cliff.brake@gmail.com>
- * Support for Accelent/Vibren PXA255 IDP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of Lubbock-Board */
- gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* turn on serial ports */
- *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
-
- /* set PWM for LCD */
- /* a value that works is 60Hz, 77% duty cycle */
- writel(readl(CKEN) | CKEN0_PWM0, CKEN);
- writel(0x3f, PWM_CTRL0);
- writel(0x3ff, PWM_PERVAL0);
- writel(792, PWM_PWDUTY0);
-
- /* clear reset to AC97 codec */
- writel(readl(CKEN) | CKEN2_AC97, CKEN);
- writel(GCR_COLD_RST, GCR);
-
- /* enable LCD backlight */
- /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
-
- /* test display */
- /* lcd_puts("This is a test\nTest #2\n"); */
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-int board_late_init(void)
-{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef DEBUG_BLINKC_ENABLE
-
-void delay_c(void)
-{
- /* reset OSCR to 0 */
- writel(0, OSCR);
- while (readl(OSCR) > 0x10000)
- ;
-
- while (readl(OSCR) < 0xd4000)
- ;
-}
-
-void blink_c(void)
-{
- int led_bit = (1<<10);
-
- writel(led_bit, GPDR0);
- writel(led_bit, GPCR0);
- delay_c();
- writel(led_bit, GPSR0);
- delay_c();
- writel(led_bit, GPCR0);
-}
-
-int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("IDPCMD started\n");
- return 0;
-}
-
-U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
- "custom IDP command",
- "no args at this time"
-);
-
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-gafr0_l: 0x80001005
-gafr0_u: 0xa5128012
-gafr1_l: 0x699a9558
-gafr1_u: 0xaaa5aa6a
-gafr2_l: 0xaaaaaaaa
-gafr2_u: 0x2
-gpcr0: 0x1800400
-gpcr1: 0x0
-gpcr2: 0x0
-gpdr0: 0xc1818440
-gpdr1: 0xfcffab82
-gpdr2: 0x1ffff
-gpsr0: 0x8000
-gpsr1: 0x3f0002
-gpsr2: 0x1c000
-
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
-#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x2
-#define CONFIG_SYS_GPCR0_VAL 0x1800400
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPDR0_VAL 0xc1818440
-#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
-#define CONFIG_SYS_GPDR2_VAL 0x1ffff
-#define CONFIG_SYS_GPSR0_VAL 0x8000
-#define CONFIG_SYS_GPSR1_VAL 0x3f0002
-#define CONFIG_SYS_GPSR2_VAL 0x1c000
-
-
-GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
-GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
-GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
-GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
-GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
-GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
-GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
-GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
-GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
-GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
-GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
-GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
-GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
-GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
-GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
-GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
-GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
-GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
-GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
-GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
-GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
-GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
-GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
-GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
-GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
-GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
-GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
-GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
-GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
-GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
-GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
-GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
-GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
-GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
-GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
-GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
-GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
-GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
-GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
-GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
-GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
-GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
-GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
-GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
-GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
-GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
-GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
-GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
-GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
-GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
-GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
-GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
-GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
-GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
-GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
-GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
-GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
-GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
-GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
-GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
-GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
-GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
-GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
-GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
-GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
-GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
-GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
-GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
-GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
-GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
-GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
-GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
-GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
-GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
-GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
-GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
-GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
-GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
-GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
-GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
-GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
-GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
-GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
+++ /dev/null
-#!/usr/bin/python
-
-# (C) Copyright 2004
-# BEC Systems <http://bec-systems.com>
-# Cliff Brake <cliff.brake@gmail.com>
-
-# SPDX-License-Identifier: GPL-2.0+
-
-# calculations for PXA255 registers
-
-class gpio:
- dir = '0'
- set = '0'
- clr = '0'
- alt = '0'
- desc = ''
-
- def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
- self.dir = dir
- self.set = set
- self.clr = clr
- self.alt = alt
- self.desc = desc
-
-
-# the following is a dictionary of all GPIOs in the system
-# the key is the GPIO number
-
-
-pxa255_alt_func = {
- 0: ['gpio', 'none', 'none', 'none'],
- 1: ['gpio', 'gpio reset', 'none', 'none'],
- 2: ['gpio', 'none', 'none', 'none'],
- 3: ['gpio', 'none', 'none', 'none'],
- 4: ['gpio', 'none', 'none', 'none'],
- 5: ['gpio', 'none', 'none', 'none'],
- 6: ['gpio', 'MMC clk', 'none', 'none'],
- 7: ['gpio', '48MHz clock', 'none', 'none'],
- 8: ['gpio', 'MMC CS0', 'none', 'none'],
- 9: ['gpio', 'MMC CS1', 'none', 'none'],
- 10: ['gpio', 'RTC Clock', 'none', 'none'],
- 11: ['gpio', '3.6MHz', 'none', 'none'],
- 12: ['gpio', '32KHz', 'none', 'none'],
- 13: ['gpio', 'none', 'MBGNT', 'none'],
- 14: ['gpio', 'MBREQ', 'none', 'none'],
- 15: ['gpio', 'none', 'nCS_1', 'none'],
- 16: ['gpio', 'none', 'PWM0', 'none'],
- 17: ['gpio', 'none', 'PWM1', 'none'],
- 18: ['gpio', 'RDY', 'none', 'none'],
- 19: ['gpio', 'DREQ[1]', 'none', 'none'],
- 20: ['gpio', 'DREQ[0]', 'none', 'none'],
- 21: ['gpio', 'none', 'none', 'none'],
- 22: ['gpio', 'none', 'none', 'none'],
- 23: ['gpio', 'none', 'SSP SCLK', 'none'],
- 24: ['gpio', 'none', 'SSP SFRM', 'none'],
- 25: ['gpio', 'none', 'SSP TXD', 'none'],
- 26: ['gpio', 'SSP RXD', 'none', 'none'],
- 27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
- 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
- 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
- 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
- 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
- 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
- 33: ['gpio', 'none', 'nCS_5', 'none'],
- 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
- 35: ['gpio', 'FF CTS', 'none', 'none'],
- 36: ['gpio', 'FF DCD', 'none', 'none'],
- 37: ['gpio', 'FF DSR', 'none', 'none'],
- 38: ['gpio', 'FF RI', 'none', 'none'],
- 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
- 40: ['gpio', 'none', 'FF DTR', 'none'],
- 41: ['gpio', 'none', 'FF RTS', 'none'],
- 42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
- 43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
- 44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
- 45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
- 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
- 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
- 48: ['gpio', 'HW TXD', 'nPOE', 'none'],
- 49: ['gpio', 'HW RXD', 'nPWE', 'none'],
- 50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
- 51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
- 52: ['gpio', 'none', 'nPCE[1]', 'none'],
- 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
- 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
- 55: ['gpio', 'none', 'nPREG', 'none'],
- 56: ['gpio', 'nPWAIT', 'none', 'none'],
- 57: ['gpio', 'nIOIS16', 'none', 'none'],
- 58: ['gpio', 'none', 'LDD[0]', 'none'],
- 59: ['gpio', 'none', 'LDD[1]', 'none'],
- 60: ['gpio', 'none', 'LDD[2]', 'none'],
- 61: ['gpio', 'none', 'LDD[3]', 'none'],
- 62: ['gpio', 'none', 'LDD[4]', 'none'],
- 63: ['gpio', 'none', 'LDD[5]', 'none'],
- 64: ['gpio', 'none', 'LDD[6]', 'none'],
- 65: ['gpio', 'none', 'LDD[7]', 'none'],
- 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
- 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
- 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
- 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
- 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
- 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
- 72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
- 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
- 74: ['gpio', 'none', 'LCD_FCLK', 'none'],
- 75: ['gpio', 'none', 'LCD_LCLK', 'none'],
- 76: ['gpio', 'none', 'LCD_PCLK', 'none'],
- 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
- 78: ['gpio', 'none', 'nCS_2', 'none'],
- 79: ['gpio', 'none', 'nCS_3', 'none'],
- 80: ['gpio', 'none', 'nCS_4', 'none'],
- 81: ['gpio', 'NSSPSCLK', 'none', 'none'],
- 82: ['gpio', 'NSSPSFRM', 'none', 'none'],
- 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
- 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
-}
-
-
-#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
-
-gpio_list = []
-
-for i in range(0,85):
- gpio_list.append(gpio())
-
-#chip select GPIOs
-gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
-gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
-gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
-gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
-gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
-gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
-gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
-gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
-gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
-gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
-gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
-gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
-gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
-
-# PCMCIA stuff
-gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
-gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
-gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
-gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
-gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
-gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
-gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
-gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
-gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
-gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
-
-# SSP port
-gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
-gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
-gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
-gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
-gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
-
-# audio codec
-gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
-gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
-gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
-gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
-gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
-
-# serial ports
-gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
-gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
-gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
-gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
-gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
-gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
-gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
-gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
-
-gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
-gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
-gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
-gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
-
-gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
-gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
-
-# misc GPIO signals
-gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
-gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
-gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
-gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
-gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
-gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
-gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
-gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
-gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
-gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
-gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
-gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
-gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
-gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
-gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
-
-# LCD GPIOs
-gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
-gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
-gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
-gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
-gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
-gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
-gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
-gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
-gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
-gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
-gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
-gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
-gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
-gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
-gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
-gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
-gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
-gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
-gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
-gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
-
-# calculate registers
-pxa_regs = {
- 'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
- 'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
- 'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
- 'gafr0_l':0, 'gafr0_u':0,
- 'gafr1_l':0, 'gafr1_u':0,
- 'gafr2_l':0, 'gafr2_u':0,
-}
-
-# U-boot define names
-uboot_reg_names = {
- 'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
- 'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
- 'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
- 'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
- 'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
- 'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
-}
-
-# bit mappings
-
-bit_mappings = [
-
-{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
-{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
-{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
-{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} },
-{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
-{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
-{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
-{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
-{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
-
-]
-
-def stuff_bits(bit_mapping, gpio_list):
- gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
-
- for gpio in gpios:
- for reg in bit_mapping['regs'].keys():
- value = eval( 'gpio_list[gpio].%s' % (reg) )
- if ( value ):
- # we have a high bit
- bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
- bit = value << (bit_shift)
- pxa_regs[bit_mapping['regs'][reg]] |= bit
-
-for i in bit_mappings:
- stuff_bits(i, gpio_list)
-
-# now print out all regs
-registers = pxa_regs.keys()
-registers.sort()
-for reg in registers:
- print '%s: 0x%x' % (reg, pxa_regs[reg])
-
-# print define to past right into U-Boot source code
-
-print
-print
-
-for reg in registers:
- print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
-
-# print all GPIOS
-print
-print
-
-for i in range(len(gpio_list)):
- gpio_i = gpio_list[i]
- alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
- print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
-
-
#include <fdt_support.h>
#include <fdt_simplefb.h>
#include <lcd.h>
+#include <memalign.h>
#include <mmc.h>
#include <asm/gpio.h>
#include <asm/arch/mbox.h>
--- /dev/null
+if TARGET_STOUT
+
+config SYS_BOARD
+ default "stout"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "stout"
+
+endif
--- /dev/null
+STOUT BOARD
+M: Cogent Embedded, Inc. <source@cogentembedded.com>
+S: Maintained
+F: board/renesas/stout/
+F: include/configs/stout.h
+F: configs/stout_defconfig
--- /dev/null
+#
+# board/renesas/stout/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Europe GmbH
+# Copyright (C) 2015 Renesas Electronics Corporation
+# Copyright (C) 2015 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := stout.o cpld.o qos.o ../rcar-gen2-common/common.o
--- /dev/null
+/*
+ * Stout board CPLD access support
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include "cpld.h"
+
+#define SCLK GPIO_GP_3_24
+#define SSTBZ GPIO_GP_3_25
+#define MOSI GPIO_GP_3_26
+#define MISO GPIO_GP_3_27
+
+#define CPLD_ADDR_MODE 0x00 /* RW */
+#define CPLD_ADDR_MUX 0x01 /* RW */
+#define CPLD_ADDR_HDMI 0x02 /* RW */
+#define CPLD_ADDR_DIPSW 0x08 /* R */
+#define CPLD_ADDR_RESET 0x80 /* RW */
+#define CPLD_ADDR_VERSION 0xFF /* R */
+
+static u32 cpld_read(u8 addr)
+{
+ int i;
+ u32 data = 0;
+
+ for (i = 0; i < 8; i++) {
+ gpio_set_value(MOSI, addr & 0x80); /* MSB first */
+ gpio_set_value(SCLK, 1);
+ addr <<= 1;
+ gpio_set_value(SCLK, 0);
+ }
+
+ gpio_set_value(MOSI, 0); /* READ */
+ gpio_set_value(SSTBZ, 0);
+ gpio_set_value(SCLK, 1);
+ gpio_set_value(SCLK, 0);
+ gpio_set_value(SSTBZ, 1);
+
+ for (i = 0; i < 32; i++) {
+ gpio_set_value(SCLK, 1);
+ data <<= 1;
+ data |= gpio_get_value(MISO); /* MSB first */
+ gpio_set_value(SCLK, 0);
+ }
+
+ return data;
+}
+
+static void cpld_write(u8 addr, u32 data)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ gpio_set_value(MOSI, data & (1 << 31)); /* MSB first */
+ gpio_set_value(SCLK, 1);
+ data <<= 1;
+ gpio_set_value(SCLK, 0);
+ }
+
+ for (i = 0; i < 8; i++) {
+ gpio_set_value(MOSI, addr & 0x80); /* MSB first */
+ gpio_set_value(SCLK, 1);
+ addr <<= 1;
+ gpio_set_value(SCLK, 0);
+ }
+
+ gpio_set_value(MOSI, 1); /* WRITE */
+ gpio_set_value(SSTBZ, 0);
+ gpio_set_value(SCLK, 1);
+ gpio_set_value(SCLK, 0);
+ gpio_set_value(SSTBZ, 1);
+}
+
+/* LSI pin pull-up control */
+#define PUPR3 0xe606010C
+#define PUPR3_SD3_DAT1 (1 << 27)
+
+void cpld_init(void)
+{
+ u32 val;
+
+ /* PULL-UP on MISO line */
+ val = readl(PUPR3);
+ val |= PUPR3_SD3_DAT1;
+ writel(val, PUPR3);
+
+ gpio_request(SCLK, NULL);
+ gpio_request(SSTBZ, NULL);
+ gpio_request(MOSI, NULL);
+ gpio_request(MISO, NULL);
+
+ gpio_direction_output(SCLK, 0);
+ gpio_direction_output(SSTBZ, 1);
+ gpio_direction_output(MOSI, 0);
+ gpio_direction_input(MISO);
+
+ /* dummy read */
+ cpld_read(CPLD_ADDR_VERSION);
+
+ printf("CPLD version: 0x%08x\n",
+ cpld_read(CPLD_ADDR_VERSION));
+ printf("H2 Mode setting (MD0..28): 0x%08x\n",
+ cpld_read(CPLD_ADDR_MODE));
+ printf("Multiplexer settings: 0x%08x\n",
+ cpld_read(CPLD_ADDR_MUX));
+ printf("HDMI setting: 0x%08x\n",
+ cpld_read(CPLD_ADDR_HDMI));
+ printf("DIPSW (SW3): 0x%08x\n",
+ cpld_read(CPLD_ADDR_DIPSW));
+
+#ifdef CONFIG_SH_SDHI
+ /* switch MUX to SD0 */
+ val = cpld_read(CPLD_ADDR_MUX);
+ val &= ~MUX_MSK_SD0;
+ val |= MUX_VAL_SD0;
+ cpld_write(CPLD_ADDR_MUX, val);
+#endif
+}
+
+static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 addr, val;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
+ addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
+ addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
+ printf("cpld invalid addr\n");
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 3 && strcmp(argv[1], "read") == 0) {
+ printf("0x%x\n", cpld_read(addr));
+ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+ val = simple_strtoul(argv[3], NULL, 16);
+ if (addr == CPLD_ADDR_MUX) {
+ /* never mask SCIFA0 console */
+ val &= ~MUX_MSK_SCIFA0_USB;
+ val |= MUX_VAL_SCIFA0_USB;
+ }
+ cpld_write(addr, val);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ cpld, 4, 1, do_cpld,
+ "CPLD access",
+ "read addr\n"
+ "cpld write addr val\n"
+);
+
+void reset_cpu(ulong addr)
+{
+ cpld_write(CPLD_ADDR_RESET, 1);
+}
--- /dev/null
+/*
+ * Stout board CPLD definition
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _CPLD_H_
+#define _CPLD_H_
+
+/* power-up behaviour */
+#define MODE_MSK_FREE_RUN 0x00000001
+#define MODE_VAL_FREE_RUN 0x00000000
+#define MODE_MSK_STEP_UP 0x00000001
+#define MODE_VAL_STEP_UP 0x00000000
+
+/* boot source */
+#define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E
+#define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004
+#define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E
+#define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008
+#define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E
+#define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C
+
+/* booting CPU */
+#define MODE_MSK_BOOT_CA15 0x000000C0
+#define MODE_VAL_BOOT_CA15 0x00000000
+#define MODE_MSK_BOOT_CA7 0x000000C0
+#define MODE_VAL_BOOT_CA7 0x00000040
+#define MODE_MSK_BOOT_SH4 0x000000C0
+#define MODE_VAL_BOOT_SH4 0x000000C0
+
+/* JTAG connection */
+#define MODE_MSK_JTAG_CORESIGHT 0xC0301C00
+#define MODE_VAL_JTAG_CORESIGHT 0x00200000
+#define MODE_MSK_JTAG_SH4 0xC0301C00
+#define MODE_VAL_JTAG_SH4 0x00300000
+
+/* DDR3 (PLL) speed */
+#define MODE_MSK_DDR3_1600 0x00080000
+#define MODE_VAL_DDR3_1600 0x00000000
+#define MODE_MSK_DDR3_1333 0x00080000
+#define MODE_VAL_DDR3_1333 0x00080000
+
+/* ComboPhy0 mode */
+#define MODE_MSK_PHY0_SATA0 0x01000000
+#define MODE_VAL_PHY0_SATA0 0x00000000
+#define MODE_MSK_PHY0_PCIE 0x01000000
+#define MODE_VAL_PHY0_PCIE 0x01000000
+
+/* ComboPhy1 mode */
+#define MODE_MSK_PHY1_SATA1 0x00800000
+#define MODE_VAL_PHY1_SATA1 0x00000000
+#define MODE_MSK_PHY1_USB3 0x00800000
+#define MODE_VAL_PHY1_USB3 0x00800000
+
+/*
+ * Illegal multiplexer combinations.
+ * MUX Conflicts
+ * name with any one of
+ * VIN0_BT656 VIN0_full, SD2
+ * VIN0_full VIN0_BT656, SD2, AVB, VIN2_(all)
+ * VIN1_BT656 VIN1_(others), SD0
+ * VIN1_10bit VIN1_(others), SD0, VIN3_with*, I2C1
+ * VIN1_12bit VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all)
+ * VIN2_BT656 VIN0_full, VIN2_(others), AVB,
+ * VIN2_withSYNC VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all),
+ * VIN3_with*
+ * VIN2_withFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all)
+ * VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1,
+ * SCIFA0_(all), VIN3_with*
+ * VIN3_BT656 VIN3_(others), IRQ3
+ * VIN3_withFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
+ * VIN2_withSYNCandFIELD, VIN1_10bit
+ * VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC,
+ * VIN2_withSYNCandFIELD, VIN1_10bit, I2C1
+ * AVB VIN0_full, VIN2_(all)
+ * QSPI_ONBOARD VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS
+ * QSPI_COMEXPRESS VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD
+ * I2C1 VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
+ * VIN3_withSYNCandFIELD
+ * IRQ3 VIN3_(all)
+ * SCIFA0_USB VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
+ * SCIFA0_COMEXPRESS
+ * SCIFA0_COMEXPRESS VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD,
+ * SCIFA0_USB
+ * SCIFA2 PWM210
+ * ETH_ONBOARD ETH_COMEXPRESS
+ * ETH_COMEXPRESS ETH_ONBOARD
+ * SD0 VIN1_(all)
+ * SD2 VIN0_(all)
+ * PWM210 SCIFA2
+ */
+
+/* connected to COM Express connector and CN6 for camera, BT656 only */
+#define MUX_MSK_VIN0_BT656 0x00001001
+#define MUX_VAL_VIN0_BT656 0x00000000
+/* connected to COM Express connector and CN6 for camera, all modes */
+#define MUX_MSK_VIN0_full 0x00001007
+#define MUX_VAL_VIN0_full 0x00000002
+/* connected to COM Express connector, BT656 only */
+#define MUX_MSK_VIN1_BT656 0x00000801
+#define MUX_VAL_VIN1_BT656 0x00000800
+/* connected to COM Express connector, all 10-bit modes */
+#define MUX_MSK_VIN1_10bit 0x00000821
+#define MUX_VAL_VIN1_10bit 0x00000800
+/* connected to COM Express connector, all 12-bit modes */
+#define MUX_MSK_VIN1_12bit 0x000008A1
+#define MUX_VAL_VIN1_12bit 0x00000880
+/* connected to COM Express connector, BT656 only */
+#define MUX_MSK_VIN2_BT656 0x00000007
+#define MUX_VAL_VIN2_BT656 0x00000006
+/* connected to COM Express connector, modes with sync signals */
+#define MUX_MSK_VIN2_withSYNC 0x000000A7
+#define MUX_VAL_VIN2_withSYNC 0x00000086
+/* connected to COM Express connector, modes with field, clken signals */
+#define MUX_MSK_VIN2_withFIELD 0x0000000F
+#define MUX_VAL_VIN2_withFIELD 0x0000000E
+/* connected to COM Express connector, modes with sync, field, clken signals */
+#define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF
+#define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E
+/* connected to COM Express connector, BT656 only */
+#define MUX_MSK_VIN3_BT656 0x00000101
+#define MUX_VAL_VIN3_BT656 0x00000100
+/* connected to COM Express connector, modes with field, clken signals */
+#define MUX_MSK_VIN3_withFIELD 0x00000121
+#define MUX_VAL_VIN3_withFIELD 0x00000120
+/* connected to COM Express connector, modes with sync, field, clken signals */
+#define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161
+#define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120
+/* connected to COM Express connector (RGMII) */
+#define MUX_MSK_AVB 0x00000003
+#define MUX_VAL_AVB 0x00000000
+/* connected to on-board QSPI flash */
+#define MUX_MSK_QSPI_ONBOARD 0x00000019
+#define MUX_VAL_QSPI_ONBOARD 0x00000000
+/* connected to COM Express connector */
+#define MUX_MSK_QSPI_COMEXPRESS 0x00000019
+#define MUX_VAL_QSPI_COMEXPRESS 0x00000010
+/* connected to COM Express connector and PMIC */
+#define MUX_MSK_I2C1 0x00000061
+#define MUX_VAL_I2C1 0x00000060
+/* connected to HDMI driver */
+#define MUX_MSK_IRQ3 0x00000101
+#define MUX_VAL_IRQ3 0x00000000
+/* connected to USB/FTDI */
+#define MUX_MSK_SCIFA0_USB 0x00004081
+#define MUX_VAL_SCIFA0_USB 0x00004000
+/* connected to COM Express connector */
+#define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081
+#define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000
+/* connected to COM Express connector */
+#define MUX_MSK_SCIFA2 0x00002001
+#define MUX_VAL_SCIFA2 0x00000000
+/* connected to on-board 10/100 Phy */
+#define MUX_MSK_ETH_ONBOARD 0x00000600
+#define MUX_VAL_ETH_ONBOARD 0x00000000
+/* connected to COM Express connector (RMII) */
+#define MUX_MSK_ETH_COMEXPRESS 0x00000600
+#define MUX_VAL_ETH_COMEXPRESS 0x00000400
+/* connected to on-board MicroSD slot */
+#define MUX_MSK_SD0 0x00000801
+#define MUX_VAL_SD0 0x00000000
+/* connected to COM Express connector */
+#define MUX_MSK_SD2 0x00001001
+#define MUX_VAL_SD2 0x00001000
+/* connected to COM Express connector */
+#define MUX_MSK_PWM210 0x00002001
+#define MUX_VAL_PWM210 0x00002000
+
+#define HDMI_MSK 0x07
+#define HDMI_OFF 0x00
+#define HDMI_ONBOARD 0x07
+#define HDMI_COMEXPRESS 0x05
+#define HDMI_ONBOARD_NODDC 0x03
+#define HDMI_COMEXPRESS_NODDC 0x01
+
+void cpld_init(void);
+
+#endif /* _CPLD_H_ */
--- /dev/null
+/*
+ * board/renesas/stout/qos.c
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+/* QoS version 0.955 for ES1 */
+static void qos_init_es1(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x80FF1C1E, &s3c->s3cadsplcr);
+ writel(0x1F060505, &s3c->s3crorr);
+ writel(0x1F020100, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00800080, &s3c_qos->s3cqos0);
+ writel(0x22000010, &s3c_qos->s3cqos1);
+ writel(0x22002200, &s3c_qos->s3cqos2);
+ writel(0x2F002200, &s3c_qos->s3cqos3);
+ writel(0x2F002F00, &s3c_qos->s3cqos4);
+ writel(0x22000010, &s3c_qos->s3cqos5);
+ writel(0x22002200, &s3c_qos->s3cqos6);
+ writel(0x2F002200, &s3c_qos->s3cqos7);
+ writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00800080, &s3c_qos->s3cqos0);
+ writel(0x22000010, &s3c_qos->s3cqos1);
+ writel(0x22002200, &s3c_qos->s3cqos2);
+ writel(0x2F002200, &s3c_qos->s3cqos3);
+ writel(0x2F002F00, &s3c_qos->s3cqos4);
+ writel(0x22000010, &s3c_qos->s3cqos5);
+ writel(0x22002200, &s3c_qos->s3cqos6);
+ writel(0x2F002200, &s3c_qos->s3cqos7);
+ writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80918099, &s3c_qos->s3cqos0);
+ writel(0x20410010, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20410FFF, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00810089, &s3c_qos->s3cqos0);
+ writel(0x20410001, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20410FFF, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ writel(0x00200808, &s3c->s3carcr11);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000203, &qos_addr->dblgcnt);
+ writel(0x00002064, &qos_addr->dbtmval0);
+ writel(0x00002048, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00002019, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002019, &qos_addr->dbthres0);
+ writel(0x00002019, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000000, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000203, &qos_addr->dblgcnt);
+ writel(0x00002064, &qos_addr->dbtmval0);
+ writel(0x00002048, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00002019, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002019, &qos_addr->dbthres0);
+ writel(0x00002019, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000000, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00B800C0, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+ writel(0x00200000, &mxi->mxs3cracr);
+ writel(0x00200000, &mxi->mxs3cwacr);
+ writel(0x00200000, &mxi->mxaxiracr);
+ writel(0x00200000, &mxi->mxaxiwacr);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000D, &mxi_qos->du0);
+ writel(0x0000000D, &mxi_qos->du1);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200D, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000000, &axi_qos->qosqon);
+}
+
+#if defined(CONFIG_QOS_PRI_MEDIA)
+#define is_qos_pri_media() 1
+#else
+#define is_qos_pri_media() 0
+#endif
+
+#if defined(CONFIG_QOS_PRI_NORMAL)
+#define is_qos_pri_normal() 1
+#else
+#define is_qos_pri_normal() 0
+#endif
+
+#if defined(CONFIG_QOS_PRI_GFX)
+#define is_qos_pri_gfx() 1
+#else
+#define is_qos_pri_gfx() 0
+#endif
+
+/* QoS version 0.963 for ES2 */
+static void qos_init_es2(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x80000000, &s3c->s3cadsplcr);
+ if (is_qos_pri_media()) {
+ writel(0x1F060302, &s3c->s3crorr);
+ writel(0x07070302, &s3c->s3cworr);
+ } else if (is_qos_pri_normal()) {
+ writel(0x1F060504, &s3c->s3crorr);
+ writel(0x07070503, &s3c->s3cworr);
+ } else if (is_qos_pri_gfx()) {
+ writel(0x1F060606, &s3c->s3crorr);
+ writel(0x07070606, &s3c->s3cworr);
+ }
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ if (is_qos_pri_media())
+ writel(0x20AA2300, &s3c_qos->s3cqos3);
+ else if (is_qos_pri_normal())
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ else if (is_qos_pri_gfx())
+ writel(0x20AA2100, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ if (is_qos_pri_media())
+ writel(0x20AA2300, &s3c_qos->s3cqos7);
+ else if (is_qos_pri_normal())
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ else if (is_qos_pri_gfx())
+ writel(0x20AA2100, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ if (is_qos_pri_media())
+ writel(0x20AA2300, &s3c_qos->s3cqos3);
+ else if (is_qos_pri_normal())
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ else if (is_qos_pri_gfx())
+ writel(0x20AA2100, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ if (is_qos_pri_media())
+ writel(0x20AA2300, &s3c_qos->s3cqos7);
+ else if (is_qos_pri_normal())
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ else if (is_qos_pri_gfx())
+ writel(0x20AA2100, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00828092, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ writel(0x00310808, &s3c->s3carcr11);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000016, &mxi->mxwtcr);
+ writel(0x00B800C0, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000E, &mxi_qos->du0);
+ writel(0x0000000E, &mxi_qos->du1);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002299, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020dc, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020dc, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
+
+void qos_init(void)
+{
+ if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
+ qos_init_es2();
+ else
+ qos_init_es1();
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
--- /dev/null
+/*
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
--- /dev/null
+/*
+ * board/renesas/stout/stout.c
+ * This file is Stout board support.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 1.4GHz */
+ if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+ u32 stat = 0;
+ u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+ << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ do {
+ stat = readl(PLLECR) & PLL0ST;
+ } while (stat == 0x0);
+ }
+
+ /* QoS(Quality-of-Service) Init */
+ qos_init();
+}
+
+#define TMU0_MSTP125 (1 << 25)
+#define SCIFA0_MSTP204 (1 << 4)
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI2_MSTP312 (1 << 12)
+#define ETHER_MSTP813 (1 << 13)
+
+#define MSTPSR3 0xE6150048
+#define SMSTPCR3 0xE615013C
+
+#define SD2CKCR 0xE6150078
+#define SD2_97500KHZ 0x7
+
+int board_early_init_f(void)
+{
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ /* SCIFA0 */
+ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+ /* SDHI0,2 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD2_97500KHZ, SD2CKCR);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7790_pinmux_init();
+
+ cpld_init();
+
+#ifdef CONFIG_SH_ETHER
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ1, NULL);
+
+ gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */
+ gpio_direction_output(GPIO_GP_3_31, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_3_31, 1);
+ udelay(1);
+#endif
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_ETHER
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+#endif
+
+ return ret;
+}
+
+/* Stout has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DAT0, NULL);
+ gpio_request(GPIO_FN_SD0_DAT1, NULL);
+ gpio_request(GPIO_FN_SD0_DAT2, NULL);
+ gpio_request(GPIO_FN_SD0_DAT3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD2_DAT0, NULL);
+ gpio_request(GPIO_FN_SD2_DAT1, NULL);
+ gpio_request(GPIO_FN_SD2_DAT2, NULL);
+ gpio_request(GPIO_FN_SD2_DAT3, NULL);
+ gpio_request(GPIO_FN_SD2_CLK, NULL);
+ gpio_request(GPIO_FN_SD2_CMD, NULL);
+ gpio_request(GPIO_FN_SD2_CD, NULL);
+
+ /* SDHI0 - needs CPLD mux setup */
+ gpio_request(GPIO_GP_3_30, NULL);
+ gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */
+ gpio_request(GPIO_GP_5_24, NULL);
+ gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI2 - needs CPLD mux setup */
+ gpio_request(GPIO_GP_3_29, NULL);
+ gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */
+ gpio_request(GPIO_GP_5_25, NULL);
+ gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
+#endif
+ return ret;
+}
+
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+static const struct sh_serial_platdata serial_platdata = {
+ .base = SCIFA0_BASE,
+ .type = PORT_SCIFA,
+ .clk = CONFIG_MP_CLK_FREQ,
+};
+
+U_BOOT_DEVICE(stout_serials) = {
+ .name = "serial_sh",
+ .platdata = &serial_platdata,
+};
#include <errno.h>
#include <version.h>
#include <malloc.h>
+#include <memalign.h>
#include <linux/sizes.h>
#include <asm/arch/cpu.h>
#include <asm/gpio.h>
+++ /dev/null
-if TARGET_SCB9328
-
-config SYS_BOARD
- default "scb9328"
-
-config SYS_SOC
- default "imx"
-
-config SYS_CONFIG_NAME
- default "scb9328"
-
-endif
+++ /dev/null
-SCB9328 BOARD
-M: Torsten Koschorrek <koschorrek@synertronixx.de>
-S: Maintained
-F: board/scb9328/
-F: include/configs/scb9328.h
-F: configs/scb9328_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := scb9328.o flash.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- * hopefully may work with other configurations.
- */
-
-#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
-# define FLASH_BUS vu_char
-# define FLASH_BUS_RET u_char
-# if ( SCB9328_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# else
-# error "With 8bit bus only one chip is allowed"
-# endif
-
-
-#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
-# define FLASH_BUS vu_short
-# define FLASH_BUS_RET u_short
-# if ( SCB9328_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 8 )| x )
-# else
-# error "With 16bit bus only 1 or 2 chip(s) are allowed"
-# endif
-
-
-#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
-# define FLASH_BUS vu_long
-# define FLASH_BUS_RET u_long
-# if ( SCB9328_FLASH_INTERLEAVE == 1 )
-# define FLASH_CMD( x ) x
-# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
-# define FLASH_CMD( x ) (( x << 16 )| x )
-# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
-# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-# else
-# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-# endif
-
-#else
-# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
- FLASH_BUS *addr = (FLASH_BUS *) 0;
-
- /* cppcheck-suppress nullPointer */
- *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
- /* cppcheck-suppress nullPointer */
- return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
- int ok = 1;
- ulong start;
-
- start = get_timer(0);
- while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
- FLASH_CMD (CFI_INTEL_SR_READY)) {
- if (get_timer(start) > timeout && timeout != 0) {
- ok = 0;
- break;
- }
- }
- return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-# error "SCB9328 platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
- int i;
- unsigned long address = SCB9328_FLASH_BASE;
-
- flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
- flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[0].flash_id = INTEL_MANUFACT;
- memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
- flash_info[0].start[i] = address;
-#ifdef SCB9328_FLASH_UNLOCK
- /* Some devices are hw locked after start. */
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
- flash_ready (0);
- *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
- address += SCB9328_FLASH_SECT_SIZE;
- }
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
- return SCB9328_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- printf (" Intel vendor\n");
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if (!(i % 5)) {
- printf ("\n");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, non_protected = 0, sector;
- int rc = ERR_OK;
-
- FLASH_BUS *address;
-
- for (sector = s_first; sector <= s_last; sector++) {
- if (!info->protect[sector]) {
- non_protected++;
- }
- }
-
- if (!non_protected) {
- return ERR_PROTECTED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
- flag = disable_interrupts ();
-
-
- /* Start erase on unprotected sectors */
- for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
- if (info->protect[sector]) {
- printf ("Protected sector %2d skipping...\n", sector);
- continue;
- } else {
- printf ("Erasing sector %2d ... ", sector);
- }
-
- address = (FLASH_BUS *) (info->start[sector]);
-
- *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
- *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
- if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- printf ("ok.\n");
- } else {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- break;
- }
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- }
- if (ctrlc ())
- printf ("User Interrupt!\n");
-
- /* allow flash to settle - wait 10 ms */
- udelay_masked (10000);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
- FLASH_BUS *address = (FLASH_BUS *) dest;
- int rc = ERR_OK;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*address & data) != data) {
- return ERR_NOT_ERASED;
- }
-
- /*
- * Disable interrupts which might cause a timeout
- * here. Remember that our exception vectors are
- * at address 0 in the flash, and we don't want a
- * (ticker) exception to happen while the flash
- * chip is in programming mode.
- */
-
- flag = disable_interrupts ();
-
- *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
- *address = data;
-
- if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
- *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
- rc = ERR_TIMOUT;
- printf ("timeout! Aborting...\n");
- }
-
- *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
- if (flag) {
- enable_interrupts ();
- }
-
- return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong read_addr, write_addr;
- FLASH_BUS data;
- int i, result = ERR_OK;
-
-
- read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
- write_addr = read_addr;
- if (read_addr != addr) {
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (read_addr < addr || cnt == 0) {
- data |= *((uchar *) read_addr) << i * 8;
- } else {
- data |= (*src++) << i * 8;
- cnt--;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- }
- for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
- if ((result = write_data (info, write_addr,
- *((FLASH_BUS *) src))) != ERR_OK) {
- return result;
- }
- write_addr += sizeof (FLASH_BUS);
- src += sizeof (FLASH_BUS);
- }
- if (cnt > 0) {
- read_addr = write_addr;
- data = 0;
- for (i = 0; i < sizeof (FLASH_BUS); i++) {
- if (cnt > 0) {
- data |= (*src++) << i * 8;
- cnt--;
- } else {
- data |= *((uchar *) read_addr) << i * 8;
- }
- read_addr++;
- }
- if ((result = write_data (info, write_addr, data)) != 0) {
- return result;
- }
- }
- return ERR_OK;
-}
+++ /dev/null
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef FLASH_INTEL_H
-#define FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define CFI_CHIP_INTEL_28F320J3A 0x0016
-#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
-#define CFI_CHIP_INTEL_28F640J3A 0x0017
-#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
-#define CFI_CHIP_INTEL_28F128J3A 0x0018
-#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define CFI_CHIP_INTEL_28F640K3 0x8801
-#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
-#define CFI_CHIP_INTEL_28F128K3 0x8802
-#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
-#define CFI_CHIP_INTEL_28F256K3 0x8803
-#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
-#define CFI_CHIP_INTEL_28F640K18 0x8805
-#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
-#define CFI_CHIP_INTEL_28F128K18 0x8806
-#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
-#define CFI_CHIP_INTEL_28F256K18 0x8807
-#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
-
-#endif /* FLASH_INTEL_H */
+++ /dev/null
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
- mov r10, lr
-
-/* Change PERCLK1DIV to 14 ie 14+1 */
- ldr r0, =PCDR
- ldr r1, =CONFIG_SYS_PCDR_VAL
- str r1, [r0]
-
-/* set MCU PLL Control Register 0 */
-
- ldr r0, =MPCTL0
- ldr r1, =CONFIG_SYS_MPCTL0_VAL
- str r1, [r0]
-
-/* set mpll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<21)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
-/* set System PLL Control Register 0 */
-
- ldr r0, =SPCTL0
- ldr r1, =CONFIG_SYS_SPCTL0_VAL
- str r1, [r0]
-
-/* set spll restart bit */
- ldr r0, =CSCR
- ldr r1, [r0]
- orr r1,r1,#(1<<22)
- str r1, [r0]
-
- mov r2,#0x10
-1:
- mov r3,#0x2000
-2:
- subs r3,r3,#1
- bne 2b
-
- subs r2,r2,#1
- bne 1b
-
- ldr r0, =CSCR
- ldr r1, =CONFIG_SYS_CSCR_VAL
- str r1, [r0]
-
-/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
- *this.....
- *
- * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
- * register 1, this stops it using the output of the PLL and thus runs at the
- * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
- * use the value set in the CM_OSC registers...regardless of what you set it
- * too! Thus, although i thought i was running at 140MHz, i'm actually running
- * at 40!..
-
- * Slapping this into my bootloader does the trick...
-
- * MRC p15,0,r0,c1,c0,0 ; read core configuration register
- * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
- * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
- * register
- */
- MRC p15,0,r0,c1,c0,0
- ORR r0,r0,#0xC0000000
- MCR p15,0,r0,c1,c0,0
-
- ldr r0, =GPR(0)
- ldr r1, =CONFIG_SYS_GPR_A_VAL
- str r1, [r0]
-
- ldr r0, =GIUS(0)
- ldr r1, =CONFIG_SYS_GIUS_A_VAL
- str r1, [r0]
-
-/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
-
- ldr r0, =FMCR
- ldr r1, =CONFIG_SYS_FMCR_VAL
- str r1, [r0]
-
- ldr r0, =CS0U
- ldr r1, =CONFIG_SYS_CS0U_VAL
- str r1, [r0]
-
- ldr r0, =CS0L
- ldr r1, =CONFIG_SYS_CS0L_VAL
- str r1, [r0]
-
- ldr r0, =CS1U
- ldr r1, =CONFIG_SYS_CS1U_VAL
- str r1, [r0]
-
- ldr r0, =CS1L
- ldr r1, =CONFIG_SYS_CS1L_VAL
- str r1, [r0]
-
- ldr r0, =CS2U
- ldr r1, =CONFIG_SYS_CS2U_VAL
- str r1, [r0]
-
- ldr r0, =CS2L
- ldr r1, =CONFIG_SYS_CS2L_VAL
- str r1, [r0]
-
- ldr r0, =CS3U
- ldr r1, =CONFIG_SYS_CS3U_VAL
- str r1, [r0]
-
- ldr r0, =CS3L
- ldr r1, =CONFIG_SYS_CS3L_VAL
- str r1, [r0]
-
- ldr r0, =CS4U
- ldr r1, =CONFIG_SYS_CS4U_VAL
- str r1, [r0]
-
- ldr r0, =CS4L
- ldr r1, =CONFIG_SYS_CS4L_VAL
- str r1, [r0]
-
- ldr r0, =CS5U
- ldr r1, =CONFIG_SYS_CS5U_VAL
- str r1, [r0]
-
- ldr r0, =CS5L
- ldr r1, =CONFIG_SYS_CS5L_VAL
- str r1, [r0]
-
-/* SDRAM Setup */
-
- ldr r0, =SDCTL0
- ldr r1, =PRECHARGE_CMD
- str r1, [r0]
-
- ldr r0, =0x08200000
- ldr r1, =0x0 /* Issue Precharge all Command */
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =AUTOREFRESH_CMD
- str r1, [r0]
-
- ldr r0, =0x08000000
- ldr r1, =0x0 /* Issue AutoRefresh Command */
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =0xb10a8300
- str r1, [r0]
-
- ldr r0, =0x08223000 /* CAS Latency 2 */
- ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
- str r1, [r0]
-
- ldr r0, =SDCTL0
- ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
- str r1, [r0]
-
- mov pc,r10
+++ /dev/null
-/*
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
- gd->bd->bi_boot_params = 0x08000100;
-
- return 0;
-}
-
-int dram_init (void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1,
- SCB9328_SDRAM_1_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
- gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
-}
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
- return;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
pin_to_mask(AT91_PIN_PA17) |
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
- pin_to_mask(AT91_PIN_PA28),
+ pin_to_mask(AT91_PIN_PA28) |
+ pin_to_mask(AT91_PIN_PA29),
&pioa->pudr);
at91_phy_reset();
pin_to_mask(AT91_PIN_PA17) |
pin_to_mask(AT91_PIN_PA25) |
pin_to_mask(AT91_PIN_PA26) |
- pin_to_mask(AT91_PIN_PA28),
+ pin_to_mask(AT91_PIN_PA28) |
+ pin_to_mask(AT91_PIN_PA29),
&pioa->puer);
/* Initialize EMAC=MACB hardware */
int board_init(void)
{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- smartweb_nand_hw_init();
-#ifdef CONFIG_MACB
- smartweb_macb_hw_init();
-#endif
/* power LED red */
at91_set_gpio_output(AT91_PIN_PC6, 0);
at91_set_gpio_output(AT91_PIN_PC7, 1);
at91_udc_probe(&board_udc_data);
#endif
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ smartweb_nand_hw_init();
+#ifdef CONFIG_MACB
+ smartweb_macb_hw_init();
+#endif
return 0;
}
void spl_board_init(void)
{
+ /* power LED orange */
at91_set_gpio_output(AT91_PIN_PC6, 1);
at91_set_gpio_output(AT91_PIN_PC7, 1);
/* alarm LED orange */
/* check if both button are pressed */
if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
- at91_get_gpio_value(AT91_PIN_PA29) == 0) {
- debug("Recovery button pressed\n");
+ at91_get_gpio_value(AT91_PIN_PA29) == 0) {
+ smartweb_nand_hw_init();
nand_init();
spl_nand_erase_one(0, 0);
}
config SYS_VENDOR
default "solidrun"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "mx6cuboxi"
+++ /dev/null
-if TARGET_SNOWBALL
-
-config SYS_BOARD
- default "snowball"
-
-config SYS_VENDOR
- default "st-ericsson"
-
-config SYS_SOC
- default "u8500"
-
-config SYS_CONFIG_NAME
- default "snowball"
-
-endif
+++ /dev/null
-SNOWBALL BOARD
-M: Mathieu Poirier <mathieu.poirier@linaro.org>
-S: Maintained
-F: board/st-ericsson/snowball/
-F: include/configs/snowball.h
-F: configs/snowball_defconfig
+++ /dev/null
-#
-# Copyright (C) ST-Ericsson SA 2009
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ccflags-y += -D__RELEASE -D__STN_8500
-
-obj-y := snowball.o
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2010
- * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
- * The purpose is that GPIO config found in kernel should work by simply
- * copy-paste it to U-boot.
- *
- * Ported to U-boot by:
- * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
- **
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- */
-
-#ifndef __DB8500_PINS_H
-#define __DB8500_PINS_H
-
-#include <asm/arch/db8500_pincfg.h>
-
-#define GPIO0_GPIO PIN_CFG(0, GPIO)
-#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
-#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
-#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
-
-#define GPIO1_GPIO PIN_CFG(1, GPIO)
-#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
-#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
-#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
-
-#define GPIO2_GPIO PIN_CFG(2, GPIO)
-#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
-#define GPIO2_NONE PIN_CFG(2, ALT_B)
-#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
-
-#define GPIO3_GPIO PIN_CFG(3, GPIO)
-#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
-#define GPIO3_NONE PIN_CFG(3, ALT_B)
-#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
-
-#define GPIO4_GPIO PIN_CFG(4, GPIO)
-#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP)
-#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
-
-#define GPIO5_GPIO PIN_CFG(5, GPIO)
-#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP)
-#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
-
-#define GPIO6_GPIO PIN_CFG(6, GPIO)
-#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP)
-#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
-
-#define GPIO7_GPIO PIN_CFG(7, GPIO)
-#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP)
-#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
-
-#define GPIO8_GPIO PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP)
-#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP)
-
-#define GPIO9_GPIO PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP)
-#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP)
-
-#define GPIO10_GPIO PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP)
-#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP)
-#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
-
-#define GPIO11_GPIO PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP)
-#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP)
-#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
-
-#define GPIO12_GPIO PIN_CFG(12, GPIO)
-#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
-#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
-
-#define GPIO13_GPIO PIN_CFG(13, GPIO)
-#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
-
-#define GPIO14_GPIO PIN_CFG(14, GPIO)
-#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
-
-#define GPIO15_GPIO PIN_CFG(15, GPIO)
-#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
-#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
-
-#define GPIO16_GPIO PIN_CFG(16, GPIO)
-#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP)
-#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
-
-#define GPIO17_GPIO PIN_CFG(17, GPIO)
-#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP)
-#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
-
-#define GPIO18_GPIO PIN_CFG(18, GPIO)
-#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A)
-#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
-#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
-
-#define GPIO19_GPIO PIN_CFG(19, GPIO)
-#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A)
-#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
-#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
-
-#define GPIO20_GPIO PIN_CFG(20, GPIO)
-#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A)
-#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
-#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
-
-#define GPIO21_GPIO PIN_CFG(21, GPIO)
-#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A)
-#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
-#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
-
-#define GPIO22_GPIO PIN_CFG(22, GPIO)
-#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A)
-#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
-#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
-
-#define GPIO23_GPIO PIN_CFG(23, GPIO)
-#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A)
-#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
-#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
-
-#define GPIO24_GPIO PIN_CFG(24, GPIO)
-#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A)
-#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
-#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
-
-#define GPIO25_GPIO PIN_CFG(25, GPIO)
-#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A)
-#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
-#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
-
-#define GPIO26_GPIO PIN_CFG(26, GPIO)
-#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A)
-#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
-#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
-
-#define GPIO27_GPIO PIN_CFG(27, GPIO)
-#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A)
-#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
-#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
-
-#define GPIO28_GPIO PIN_CFG(28, GPIO)
-#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A)
-#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
-#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
-
-#define GPIO29_GPIO PIN_CFG(29, GPIO)
-#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
-#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
-#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
-
-#define GPIO30_GPIO PIN_CFG(30, GPIO)
-#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
-#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
-#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
-
-#define GPIO31_GPIO PIN_CFG(31, GPIO)
-#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
-#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
-#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
-
-#define GPIO32_GPIO PIN_CFG(32, GPIO)
-#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
-#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
-#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
-
-#define GPIO33_GPIO PIN_CFG(33, GPIO)
-#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
-#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
-#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
-
-#define GPIO34_GPIO PIN_CFG(34, GPIO)
-#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
-#define GPIO34_NONE PIN_CFG(34, ALT_B)
-#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
-
-#define GPIO35_GPIO PIN_CFG(35, GPIO)
-#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
-#define GPIO35_NONE PIN_CFG(35, ALT_B)
-#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
-
-#define GPIO36_GPIO PIN_CFG(36, GPIO)
-#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
-#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
-#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
-
-#define GPIO64_GPIO PIN_CFG(64, GPIO)
-#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
-#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
-#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
-
-#define GPIO65_GPIO PIN_CFG(65, GPIO)
-#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
-#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
-#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
-
-#define GPIO66_GPIO PIN_CFG(66, GPIO)
-#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
-#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
-#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
-
-#define GPIO67_GPIO PIN_CFG(67, GPIO)
-#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
-#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
-#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
-
-#define GPIO68_GPIO PIN_CFG(68, GPIO)
-#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
-#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
-#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
-
-#define GPIO69_GPIO PIN_CFG(69, GPIO)
-#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
-#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
-#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
-
-#define GPIO70_GPIO PIN_CFG(70, GPIO)
-#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
-#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
-#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
-
-#define GPIO71_GPIO PIN_CFG(71, GPIO)
-#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
-#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
-#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
-
-#define GPIO72_GPIO PIN_CFG(72, GPIO)
-#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
-#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
-#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
-
-#define GPIO73_GPIO PIN_CFG(73, GPIO)
-#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
-#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
-#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
-
-#define GPIO74_GPIO PIN_CFG(74, GPIO)
-#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
-#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
-#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
-
-#define GPIO75_GPIO PIN_CFG(75, GPIO)
-#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
-#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
-#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
-
-#define GPIO76_GPIO PIN_CFG(76, GPIO)
-#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
-#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
-#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
-
-#define GPIO77_GPIO PIN_CFG(77, GPIO)
-#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
-#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
-#define GPIO77_NONE PIN_CFG(77, ALT_C)
-
-#define GPIO78_GPIO PIN_CFG(78, GPIO)
-#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
-#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
-#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
-
-#define GPIO79_GPIO PIN_CFG(79, GPIO)
-#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
-#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
-#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
-
-#define GPIO80_GPIO PIN_CFG(80, GPIO)
-#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
-#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
-#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
-
-#define GPIO81_GPIO PIN_CFG(81, GPIO)
-#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
-#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
-#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
-
-#define GPIO82_GPIO PIN_CFG(82, GPIO)
-#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
-#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
-
-#define GPIO83_GPIO PIN_CFG(83, GPIO)
-#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
-#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
-
-#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP)
-#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
-#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
-
-#define GPIO85_GPIO PIN_CFG(85, GPIO)
-#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
-#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
-
-#define GPIO86_GPIO PIN_CFG(86, GPIO)
-#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
-#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
-#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
-
-#define GPIO87_GPIO PIN_CFG(87, GPIO)
-#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
-#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
-#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
-
-#define GPIO88_GPIO PIN_CFG(88, GPIO)
-#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
-#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
-#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
-
-#define GPIO89_GPIO PIN_CFG(89, GPIO)
-#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
-#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
-#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
-
-#define GPIO90_GPIO PIN_CFG(90, GPIO)
-#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
-#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
-#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
-
-#define GPIO91_GPIO PIN_CFG(91, GPIO)
-#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
-#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
-#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
-
-#define GPIO92_GPIO PIN_CFG(92, GPIO)
-#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
-#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
-#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
-
-#define GPIO93_GPIO PIN_CFG(93, GPIO)
-#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
-#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
-#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
-
-#define GPIO94_GPIO PIN_CFG(94, GPIO)
-#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
-#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
-#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
-
-#define GPIO95_GPIO PIN_CFG(95, GPIO)
-#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
-#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
-#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
-
-#define GPIO96_GPIO PIN_CFG(96, GPIO)
-#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
-#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
-#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
-
-#define GPIO97_GPIO PIN_CFG(97, GPIO)
-#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
-#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
-#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
-
-#define GPIO128_GPIO PIN_CFG(128, GPIO)
-#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A)
-#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
-
-#define GPIO129_GPIO PIN_CFG(129, GPIO)
-#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A)
-#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
-
-#define GPIO130_GPIO PIN_CFG(130, GPIO)
-#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A)
-#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
-#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
-
-#define GPIO131_GPIO PIN_CFG(131, GPIO)
-#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A)
-#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
-
-#define GPIO132_GPIO PIN_CFG(132, GPIO)
-#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A)
-#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
-
-#define GPIO133_GPIO PIN_CFG(133, GPIO)
-#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A)
-#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
-
-#define GPIO134_GPIO PIN_CFG(134, GPIO)
-#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A)
-#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
-
-#define GPIO135_GPIO PIN_CFG(135, GPIO)
-#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A)
-#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
-
-#define GPIO136_GPIO PIN_CFG(136, GPIO)
-#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A)
-#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
-
-#define GPIO137_GPIO PIN_CFG(137, GPIO)
-#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A)
-#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
-
-#define GPIO138_GPIO PIN_CFG(138, GPIO)
-#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A)
-#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
-
-#define GPIO139_GPIO PIN_CFG(139, GPIO)
-#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
-#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
-#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
-
-#define GPIO140_GPIO PIN_CFG(140, GPIO)
-#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
-#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
-#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
-
-#define GPIO141_GPIO PIN_CFG(141, GPIO)
-#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
-#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
-#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
-
-#define GPIO142_GPIO PIN_CFG(142, GPIO)
-#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
-#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
-#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
-
-#define GPIO143_GPIO PIN_CFG(143, GPIO)
-#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
-
-#define GPIO144_GPIO PIN_CFG(144, GPIO)
-#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
-
-#define GPIO145_GPIO PIN_CFG(145, GPIO)
-#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
-
-#define GPIO146_GPIO PIN_CFG(146, GPIO)
-#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
-
-#define GPIO147_GPIO PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP)
-
-#define GPIO148_GPIO PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP)
-
-#define GPIO149_GPIO PIN_CFG(149, GPIO)
-#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
-#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
-#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
-
-#define GPIO150_GPIO PIN_CFG(150, GPIO)
-#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
-#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
-
-#define GPIO151_GPIO PIN_CFG(151, GPIO)
-#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
-#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
-#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
-
-#define GPIO152_GPIO PIN_CFG(152, GPIO)
-#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
-#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
-#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
-
-#define GPIO153_GPIO PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN)
-#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
-#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
-
-#define GPIO154_GPIO PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN)
-#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
-#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
-
-#define GPIO155_GPIO PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN)
-#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
-#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
-
-#define GPIO156_GPIO PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN)
-#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
-#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
-
-#define GPIO157_GPIO PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP)
-#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
-#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
-
-#define GPIO158_GPIO PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP)
-#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
-#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
-
-#define GPIO159_GPIO PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP)
-#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
-#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
-
-#define GPIO160_GPIO PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP)
-#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
-#define GPIO160_NONE PIN_CFG(160, ALT_C)
-
-#define GPIO161_GPIO PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN)
-#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
-#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
-
-#define GPIO162_GPIO PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN)
-#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
-#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
-
-#define GPIO163_GPIO PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN)
-#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
-#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
-
-#define GPIO164_GPIO PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP)
-#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
-#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
-
-#define GPIO165_GPIO PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP)
-#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
-#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
-
-#define GPIO166_GPIO PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP)
-#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
-#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
-
-#define GPIO167_GPIO PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP)
-#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
-#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
-
-#define GPIO168_GPIO PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP)
-#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
-#define GPIO168_NONE PIN_CFG(168, ALT_C)
-
-#define GPIO169_GPIO PIN_CFG(169, GPIO)
-#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
-#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
-#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
-
-#define GPIO170_GPIO PIN_CFG(170, GPIO)
-#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
-#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
-#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
-
-#define GPIO171_GPIO PIN_CFG(171, GPIO)
-#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
-#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
-#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
-
-#define GPIO192_GPIO PIN_CFG(192, GPIO)
-#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
-
-#define GPIO193_GPIO PIN_CFG(193, GPIO)
-#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
-
-#define GPIO194_GPIO PIN_CFG(194, GPIO)
-#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
-
-#define GPIO195_GPIO PIN_CFG(195, GPIO)
-#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
-
-#define GPIO196_GPIO PIN_CFG(196, GPIO)
-#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
-
-#define GPIO197_GPIO PIN_CFG(197, GPIO)
-#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A)
-
-#define GPIO198_GPIO PIN_CFG(198, GPIO)
-#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A)
-
-#define GPIO199_GPIO PIN_CFG(199, GPIO)
-#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A)
-
-#define GPIO200_GPIO PIN_CFG(200, GPIO)
-#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A)
-
-#define GPIO201_GPIO PIN_CFG(201, GPIO)
-#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A)
-
-#define GPIO202_GPIO PIN_CFG(202, GPIO)
-#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A)
-#define GPIO202_PWL PIN_CFG(202, ALT_B)
-#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
-
-#define GPIO203_GPIO PIN_CFG(203, GPIO)
-#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A)
-
-#define GPIO204_GPIO PIN_CFG(204, GPIO)
-#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A)
-
-#define GPIO205_GPIO PIN_CFG(205, GPIO)
-#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A)
-
-#define GPIO206_GPIO PIN_CFG(206, GPIO)
-#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A)
-
-#define GPIO207_GPIO PIN_CFG(207, GPIO)
-#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A)
-
-#define GPIO208_GPIO PIN_CFG(208, GPIO)
-#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
-
-#define GPIO209_GPIO PIN_CFG(209, GPIO)
-#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
-#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
-
-#define GPIO210_GPIO PIN_CFG(210, GPIO)
-#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
-
-#define GPIO211_GPIO PIN_CFG(211, GPIO)
-#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
-
-#define GPIO212_GPIO PIN_CFG(212, GPIO)
-#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
-#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
-
-#define GPIO213_GPIO PIN_CFG(213, GPIO)
-#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
-#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
-
-#define GPIO214_GPIO PIN_CFG(214, GPIO)
-#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
-#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
-
-#define GPIO215_GPIO PIN_CFG(215, GPIO)
-#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
-#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
-#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
-
-#define GPIO216_GPIO PIN_CFG(216, GPIO)
-#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
-#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP)
-
-#define GPIO217_GPIO PIN_CFG(217, GPIO)
-#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
-#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
-#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
-
-#define GPIO218_GPIO PIN_CFG(218, GPIO)
-#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
-#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP)
-
-#define GPIO219_GPIO PIN_CFG(219, GPIO)
-#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
-#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
-
-#define GPIO220_GPIO PIN_CFG(220, GPIO)
-#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
-#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
-#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
-
-#define GPIO221_GPIO PIN_CFG(221, GPIO)
-#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
-#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
-
-#define GPIO222_GPIO PIN_CFG(222, GPIO)
-#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
-#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
-
-#define GPIO223_GPIO PIN_CFG(223, GPIO)
-#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
-#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
-#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
-
-#define GPIO224_GPIO PIN_CFG(224, GPIO)
-#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
-#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
-#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
-
-#define GPIO225_GPIO PIN_CFG(225, GPIO)
-#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
-#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
-#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
-
-#define GPIO226_GPIO PIN_CFG(226, GPIO)
-#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
-#define GPIO226_PWL PIN_CFG(226, ALT_B)
-#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
-
-#define GPIO227_GPIO PIN_CFG(227, GPIO)
-#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
-
-#define GPIO228_GPIO PIN_CFG(228, GPIO)
-#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
-
-#define GPIO229_GPIO PIN_CFG(229, GPIO)
-#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
-#define GPIO229_PWL PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP)
-
-#define GPIO230_GPIO PIN_CFG(230, GPIO)
-#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
-#define GPIO230_PWL PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP)
-
-#define GPIO256_GPIO PIN_CFG(256, GPIO)
-#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
-
-#define GPIO257_GPIO PIN_CFG(257, GPIO)
-#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
-
-#define GPIO258_GPIO PIN_CFG(258, GPIO)
-#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
-#define GPIO258_NONE PIN_CFG(258, ALT_B)
-#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
-
-#define GPIO259_GPIO PIN_CFG(259, GPIO)
-#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
-
-#define GPIO260_GPIO PIN_CFG(260, GPIO)
-#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
-
-#define GPIO261_GPIO PIN_CFG(261, GPIO)
-#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
-
-#define GPIO262_GPIO PIN_CFG(262, GPIO)
-#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
-
-#define GPIO263_GPIO PIN_CFG(263, GPIO)
-#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
-
-#define GPIO264_GPIO PIN_CFG(264, GPIO)
-#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
-
-#define GPIO265_GPIO PIN_CFG(265, GPIO)
-#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
-
-#define GPIO266_GPIO PIN_CFG(266, GPIO)
-#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
-
-#define GPIO267_GPIO PIN_CFG(267, GPIO)
-#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/db8500_pincfg.h>
-#include <asm/arch/prcmu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-
-#ifdef CONFIG_MMC
-#include "../../../drivers/mmc/arm_pl180_mmci.h"
-#endif
-#include "db8500_pins.h"
-
-/*
- * Get a global data pointer
- */
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Memory controller register
- */
-#define DMC_BASE_ADDR 0x80156000
-#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
-
-/*
- * GPIO pin config common for MOP500/HREF boards
- */
-unsigned long gpio_cfg_common[] = {
- /* I2C */
- GPIO147_I2C0_SCL,
- GPIO148_I2C0_SDA,
- GPIO16_I2C1_SCL,
- GPIO17_I2C1_SDA,
- GPIO10_I2C2_SDA,
- GPIO11_I2C2_SCL,
- GPIO229_I2C3_SDA,
- GPIO230_I2C3_SCL,
-
- /* SSP0, to AB8500 */
- GPIO143_SSP0_CLK,
- GPIO144_SSP0_FRM,
- GPIO145_SSP0_RXD | PIN_PULL_DOWN,
- GPIO146_SSP0_TXD,
-
- /* MMC0 (MicroSD card) */
- GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
- GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
- GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
- GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
- GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
- GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
- GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
- GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
- GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
- GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
- GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
-
- /* MMC4 (On-board eMMC) */
- GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
- GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
- GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
- GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
- GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
- GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
- GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
- GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
- GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
- GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
- GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
-
- /* UART2, console */
- GPIO29_U2_RXD | PIN_INPUT_PULLUP,
- GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
- GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
- GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
-
- /*
- * USB, pin 256-267 USB, Is probably already setup correctly from
- * BootROM/boot stages, but we don't trust that and set it up anyway
- */
- GPIO256_USB_NXT,
- GPIO257_USB_STP,
- GPIO258_USB_XCLK,
- GPIO259_USB_DIR,
- GPIO260_USB_DAT7,
- GPIO261_USB_DAT6,
- GPIO262_USB_DAT5,
- GPIO263_USB_DAT4,
- GPIO264_USB_DAT3,
- GPIO265_USB_DAT2,
- GPIO266_USB_DAT1,
- GPIO267_USB_DAT0,
-};
-
-unsigned long gpio_cfg_snowball[] = {
- /* MMC0 (MicroSD card) */
- GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */
- GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */
- GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */
-
- /* eMMC */
- GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */
-
- /* LAN */
- GPIO131_SM_ADQ8,
- GPIO132_SM_ADQ9,
- GPIO133_SM_ADQ10,
- GPIO134_SM_ADQ11,
- GPIO135_SM_ADQ12,
- GPIO136_SM_ADQ13,
- GPIO137_SM_ADQ14,
- GPIO138_SM_ADQ15,
-
- /* RSTn_LAN */
- GPIO141_GPIO | PIN_OUTPUT_HIGH,
-};
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init(void)
-{
- /*
- * Setup board (bd) and board-info (bi).
- * bi_arch_number: Unique id for this board. It will passed in r1 to
- * Linux startup code and is the machine_id.
- * bi_boot_params: Where this board expects params.
- */
- gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
- gd->bd->bi_boot_params = 0x00000100;
-
- /* Configure GPIO pins needed by U-boot */
- db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
-
- db8500_gpio_config_pins(gpio_cfg_snowball,
- ARRAY_SIZE(gpio_cfg_snowball));
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->ram_size = gd->bd->bi_dram[0].size =
- get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- return 0;
-}
-
-static int raise_ab8500_gpio16(void)
-{
- int ret;
-
- /* selection */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x80;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret);
- if (ret < 0)
- goto out;
-
- /* direction */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x80;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret);
- if (ret < 0)
- goto out;
-
- /* out */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x80;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret);
-
-out:
- return ret;
-}
-
-static int raise_ab8500_gpio26(void)
-{
- int ret;
-
- /* selection */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x2;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret);
- if (ret < 0)
- goto out;
-
- /* out */
- ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG);
- if (ret < 0)
- goto out;
-
- ret |= 0x2;
- ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret);
-
-out:
- return ret;
-}
-
-int board_late_init(void)
-{
- /* enable 3V3 for LAN controller */
- if (raise_ab8500_gpio26() >= 0) {
- /* Turn on FSMC device */
- writel(0x1, 0x8000f000);
- writel(0x1, 0x8000f008);
-
- /* setup FSMC for LAN controler */
- writel(0x305b, 0x80000000);
-
- /* run at the highest possible speed */
- writel(0x01010210, 0x80000004);
- } else
- printf("error: can't raise GPIO26\n");
-
- /* enable 3v6 for GBF chip */
- if ((raise_ab8500_gpio16() < 0))
- printf("error: cant' raise GPIO16\n");
-
- /* empty UART RX FIFO */
- while (tstc())
- (void) getc();
-
- return 0;
-}
-
-#ifdef CONFIG_MMC
-/*
- * emmc_host_init - initialize the emmc controller.
- * Configure GPIO settings, set initial clock and power for emmc slot.
- * Initialize mmc struct and register with mmc framework.
- */
-static int emmc_host_init(void)
-{
- struct pl180_mmc_host *host;
-
- host = malloc(sizeof(struct pl180_mmc_host));
- if (!host)
- return -ENOMEM;
- memset(host, 0, sizeof(*host));
-
- host->base = (struct sdi_registers *)CFG_EMMC_BASE;
- host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
- host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
- SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
- strcpy(host->name, "EMMC");
- host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
- host->voltages = VOLTAGE_WINDOW_MMC;
- host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
- host->clock_max = ARM_MCLK / 2;
- host->clock_in = ARM_MCLK;
- host->version2 = 1;
-
- return arm_pl180_mmci_init(host);
-}
-
-/*
- * mmc_host_init - initialize the external mmc controller.
- * Configure GPIO settings, set initial clock and power for mmc slot.
- * Initialize mmc struct and register with mmc framework.
- */
-static int mmc_host_init(void)
-{
- struct pl180_mmc_host *host;
- u32 sdi_u32;
-
- host = malloc(sizeof(struct pl180_mmc_host));
- if (!host)
- return -ENOMEM;
- memset(host, 0, sizeof(*host));
-
- host->base = (struct sdi_registers *)CFG_MMC_BASE;
- sdi_u32 = 0xBF;
- writel(sdi_u32, &host->base->power);
- host->pwr_init = 0xBF;
- host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
- SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
- strcpy(host->name, "MMC");
- host->caps = MMC_MODE_8BIT;
- host->b_max = 0;
- host->voltages = VOLTAGE_WINDOW_SD;
- host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
- host->clock_max = ARM_MCLK / 2;
- host->clock_in = ARM_MCLK;
- host->version2 = 1;
-
- return arm_pl180_mmci_init(host);
-}
-
-/*
- * board_mmc_init - initialize all the mmc/sd host controllers.
- * Called by generic mmc framework.
- */
-int board_mmc_init(bd_t *bis)
-{
- int error;
-
- (void) bis;
-
- error = emmc_host_init();
- if (error) {
- printf("emmc_host_init() %d\n", error);
- return -1;
- }
-
- u8500_mmc_power_init();
-
- error = mmc_host_init();
- if (error) {
- printf("mmc_host_init() %d\n", error);
- return -1;
- }
-
- return 0;
-}
-#endif /* CONFIG_MMC */
+++ /dev/null
-if TARGET_U8500_HREF
-
-config SYS_BOARD
- default "u8500"
-
-config SYS_VENDOR
- default "st-ericsson"
-
-config SYS_SOC
- default "u8500"
-
-config SYS_CONFIG_NAME
- default "u8500_href"
-
-endif
+++ /dev/null
-U8500 BOARD
-#M: -
-S: Maintained
-F: board/st-ericsson/u8500/
-F: include/configs/u8500_href.h
-F: configs/u8500_href_defconfig
+++ /dev/null
-#
-# Copyright (C) ST-Ericsson SA 2009
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ccflags-y += -D__RELEASE -D__STN_8500
-
-obj-y := u8500_href.o gpio.o
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/gpio.h>
-
-static struct gpio_register *addr_gpio_register[] = {
- (void *)U8500_GPIO_0_BASE,
- (void *)U8500_GPIO_1_BASE,
- (void *)U8500_GPIO_2_BASE,
- (void *)U8500_GPIO_3_BASE,
- (void *)U8500_GPIO_4_BASE,
- (void *)U8500_GPIO_5_BASE,
- (void *)U8500_GPIO_6_BASE,
- (void *)U8500_GPIO_7_BASE,
- (void *)U8500_GPIO_8_BASE,
-};
-
-struct gpio_altfun_data altfun_table[] = {
- {
- .altfun = GPIO_ALT_I2C_0,
- .start = 147,
- .end = 148,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_I2C_1,
- .start = 16,
- .end = 17,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_I2C_2,
- .start = 10,
- .end = 11,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_I2C_3,
- .start = 229,
- .end = 230,
- .cont = 0,
- .type = GPIO_ALTF_C,
- },
- {
- .altfun = GPIO_ALT_UART_0_MODEM,
- .start = 0,
- .end = 3,
- .cont = 1,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_UART_0_MODEM,
- .start = 33,
- .end = 36,
- .cont = 0,
- .type = GPIO_ALTF_C,
- },
- {
- .altfun = GPIO_ALT_UART_1,
- .start = 4,
- .end = 7,
- .cont = 0,
- .type =
- GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_UART_2,
- .start = 18,
- .end = 19,
- .cont = 1,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_UART_2,
- .start = 29,
- .end = 32,
- .cont = 0,
- .type = GPIO_ALTF_C,
- },
- {
- .altfun = GPIO_ALT_MSP_0,
- .start = 12,
- .end = 17,
- .cont = 1,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_MSP_0,
- .start = 21,
- .end = 21,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_MSP_1,
- .start = 33,
- .end = 36,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_MSP_2,
- .start = 192,
- .end = 196,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_LCD_PANEL,
- .start = 64,
- .end = 93,
- .cont = 1,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_LCD_PANEL,
- .start = 150,
- .end = 171,
- .cont = 0,
- .type = GPIO_ALTF_B,
- },
- {
- .altfun = GPIO_ALT_SD_CARD0,
- .start = 18,
- .end = 28,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_MM_CARD0,
- .start = 18,
- .end = 32,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_USB_OTG,
- .start = 256,
- .end = 267,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_EMMC,
- .start = 197,
- .end = 207,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
- {
- .altfun = GPIO_ALT_POP_EMMC,
- .start = 128,
- .end = 138,
- .cont = 0,
- .type = GPIO_ALTF_A,
- },
-};
-
-/*
- * Static Function declarations
- */
-enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
- enum gpio_error error = GPIO_OK;
- u32 temp_reg;
-
- switch (config->mode) {
- case GPIO_ALTF_A:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- break;
- case GPIO_ALTF_B:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- break;
- case GPIO_ALTF_C:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg |= mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- break;
- case GPIO_MODE_SOFTWARE:
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
-
- switch (config->direction) {
- case GPIO_DIR_INPUT:
- writel(mask, &p_gpio_register->gpio_dirc);
- break;
- case GPIO_DIR_OUTPUT:
- writel(mask, &p_gpio_register->gpio_dirs);
- break;
- case GPIO_DIR_LEAVE_UNCHANGED:
- break;
- default:
- return GPIO_INVALID_PARAMETER;
- }
-
- break;
- case GPIO_MODE_LEAVE_UNCHANGED:
- break;
- default:
- return GPIO_INVALID_PARAMETER;
- }
- return error;
-}
-
-enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
- enum gpio_error error = GPIO_OK;
- u32 temp_reg;
-
- temp_reg = readl(&p_gpio_register->gpio_afsa);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsa);
- temp_reg = readl(&p_gpio_register->gpio_afsb);
- temp_reg &= ~mask;
- writel(temp_reg, &p_gpio_register->gpio_afsb);
- writel(mask, &p_gpio_register->gpio_dirc);
-
- return error;
-}
-
-struct gpio_config altfun_pinconfig;
-enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func,
- int which_altfunc, char *dev_name)
-{
- int i, j, start, end;
- enum gpio_error error = -1;
-
- for (i = 0; i < ARRAY_SIZE(altfun_table); i++) {
- if (altfun_table[i].altfun != alt_func)
- continue;
-
- start = altfun_table[i].start;
- end = altfun_table[i].end;
- for (j = start; j <= end; j++) {
- if (which_altfunc == GPIO_ALTF_FIND)
- altfun_pinconfig.mode = altfun_table[i].type;
- else
- altfun_pinconfig.mode = which_altfunc;
- altfun_pinconfig.direction = GPIO_DIR_OUTPUT;
- altfun_pinconfig.dev_name = dev_name;
-
- if (which_altfunc != GPIO_ALTF_DISABLE)
- error = gpio_setpinconfig(j, &altfun_pinconfig);
- else
- error = gpio_resetgpiopin(j, dev_name);
- if (!error)
- continue;
- printf("GPIO %d configuration failure (nmdk_error:%d)",
- j, error);
- error = GPIO_INVALID_PARAMETER;
- return error;
- }
-
- if (!altfun_table[i].cont)
- break;
- }
- return error;
-}
-
-int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
-
- switch (value) {
- case GPIO_DATA_HIGH:
- writel(mask, &p_gpio_register->gpio_dats);
- break;
- case GPIO_DATA_LOW:
- writel(mask, &p_gpio_register->gpio_datc);
- break;
- default:
- printf("Invalid value passed in %s", __FUNCTION__);
- return GPIO_INVALID_PARAMETER;
- }
- return GPIO_OK;
-}
-
-int gpio_readpin(int pin_id, enum gpio_data *rv)
-{
- struct gpio_register *p_gpio_register =
- addr_gpio_register[GPIO_BLOCK(pin_id)];
- u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
-
- if ((readl(&p_gpio_register->gpio_dat) & mask) != 0)
- *rv = GPIO_DATA_HIGH;
- else
- *rv = GPIO_DATA_LOW;
- return GPIO_OK;
-}
-
-int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name)
-{
- return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name);
-}
-
-int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name)
-{
- return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name);
-}
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <i2c.h>
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/prcmu.h>
-#ifdef CONFIG_MMC
-#include "../../../drivers/mmc/arm_pl180_mmci.h"
-#endif
-
-#define NOMADIK_PER4_BASE (0x80150000)
-#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
-#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
-
-/* Power, Reset, Clock Management Unit */
-/*
- * SVA: Smart Video Accelerator
- * SIA: Smart Imaging Accelerator
- * SGA: Smart Graphic accelerator
- * B2R2: Graphic blitter
- */
-#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
-#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
-#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
-#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C)
-#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010)
-#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014)
-#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
-#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
-#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
-#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
-#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028)
-#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
-#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
-#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
-#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
-#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
-#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
-#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074)
-#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078)
-
-#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080)
-#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084)
-#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088)
-#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C)
-#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114)
-
-#define PRCM_TCR (PRCMU_BASE + 0x1C8)
-
-/*
- * Memory controller register
- */
-#define DMC_BASE_ADDR 0x80156000
-#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
-
-int board_id; /* set in board_late_init() */
-
-/* PLLs for clock management registers */
-enum {
- GATED = 0,
- PLLSOC0, /* pllsw = 001, ffs() = 1 */
- PLLSOC1, /* pllsw = 010, ffs() = 2 */
- PLLDDR, /* pllsw = 100, ffs() = 3 */
- PLLARM,
-};
-
-static struct pll_freq_regs {
- int idx; /* index fror pll_name and pll_khz arrays */
- uint32_t addr;
-} pll_freq_regs[] = {
- {PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
- {PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
- {PLLDDR, PRCM_PLLDDR_FREQ_REG},
- {PLLARM, PRCM_PLLARM_FREQ_REG},
- {0, 0},
-};
-
-static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
-static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */
-
-static struct clk_mgt_regs {
- uint32_t addr;
- uint32_t val;
- const char *descr;
-} clk_mgt_regs[] = {
- /* register content taken from bootrom settings */
- {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
- {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */
- {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
- {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
- {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
- {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */
- {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */
- {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */
- {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */
- {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
- {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */
- {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */
- {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */
- {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */
- {0, 0, NULL},
-};
-
-static void init_regs(void);
-
-DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
- printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
- init_regs();
- return 0;
-}
-
-int board_init(void)
-{
- uint32_t unused_cols_rows;
- unsigned int nrows;
- unsigned int ncols;
-
- gd->bd->bi_arch_number = 0x1A4;
- gd->bd->bi_boot_params = 0x00000100;
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-
- /*
- * Assumption: 2 CS active, both CS have same layout.
- * 15 rows max, 11 cols max (controller spec).
- * memory chip has 8 banks, I/O width 32 bit.
- * The correct way would be to read MR#8: I/O width and density,
- * but this requires locking against the PRCMU firmware.
- * Simplified approach:
- * Read number of unused rows and columns from mem controller.
- * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
- */
- unused_cols_rows = readl(DMC_CTL_97);
- nrows = 15 - (unused_cols_rows & 0x07);
- ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
- gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
-
- icache_enable();
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_SIZE_1;
-
- return 0;
-}
-
-unsigned int addr_vall_arr[] = {
- 0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
- 0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
- 0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
- 0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
- 0x80157020, 0x00000150, /* I2C 48MHz clock */
- 0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
- 0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
- 0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
- 0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
- 0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
- 0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
- 0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
- 0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
- 0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
- 0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
- 0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
- 0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
- 0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
- PRCM_APE_RESETN_SET_REG */
- 0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
- 0xA03FF000, 0x00000003, /* USB */
- 0xA03FF008, 0x00000001, /* USB */
- 0xA03FE00C, 0x00000000, /* USB */
- 0xA03FE020, 0x00000FFF, /* USB */
- 0xA03FE024, 0x00000000 /* USB */
-};
-
-#ifdef CONFIG_BOARD_LATE_INIT
-/*
- * called after all initialisation were done, but before the generic
- * mmc_initialize().
- */
-int board_late_init(void)
-{
- uchar byte;
-
- /*
- * Determine and set board_id environment variable
- * 0: mop500, 1: href500
- * Above boards have different GPIO expander chips which we can
- * distinguish by the chip id.
- *
- * The board_id environment variable is needed for the Linux bootargs.
- */
- (void) i2c_set_bus_num(0);
- (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
- if (byte == 0x01) {
- board_id = 0;
- setenv("board_id", "0");
- } else {
- board_id = 1;
- setenv("board_id", "1");
- }
-#ifdef CONFIG_MMC
- u8500_mmc_power_init();
-
- /*
- * config extended GPIO pins for level shifter and
- * SDMMC_ENABLE
- */
- if (board_id == 0) {
- /* MOP500 */
- byte = 0x0c;
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
- } else {
- /* HREF */
- /* set the direction of GPIO KPY9 and KPY10 */
- byte = 0x06;
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
- /* must be a multibyte access */
- (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
- (uchar []) {0x06, 0x06}, 2);
- }
-#endif /* CONFIG_MMC */
- /*
- * Create a memargs variable which points uses either the memargs256 or
- * memargs512 environment variable, depending on the memory size.
- * memargs is used to build the bootargs, memargs256 and memargs512 are
- * stored in the environment.
- */
- if (gd->bd->bi_dram[0].size == 0x10000000) {
- setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
- setenv("mem", "256M");
- } else {
- setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
- setenv("mem", "512M");
- }
-
- return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
-{
- writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
- writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
-}
-
-static void init_regs(void)
-{
- /* FIXME Remove magic register array settings for ED also */
- struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
-
- /* Enable timers */
- writel(1 << 17, &prcmu->tcr);
-
- u8500_prcmu_enable(&prcmu->per1clk_mgt);
- u8500_prcmu_enable(&prcmu->per2clk_mgt);
- u8500_prcmu_enable(&prcmu->per3clk_mgt);
- u8500_prcmu_enable(&prcmu->per5clk_mgt);
- u8500_prcmu_enable(&prcmu->per6clk_mgt);
- u8500_prcmu_enable(&prcmu->per7clk_mgt);
-
- u8500_prcmu_enable(&prcmu->uartclk_mgt);
- u8500_prcmu_enable(&prcmu->i2cclk_mgt);
-
- u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
-
- u8500_clock_enable(1, 9, -1); /* GPIO0 */
-
- u8500_clock_enable(2, 11, -1); /* GPIO1 */
-
- u8500_clock_enable(3, 8, -1); /* GPIO2 */
- u8500_clock_enable(5, 1, -1); /* GPIO3 */
-
- u8500_clock_enable(3, 6, 6); /* UART2 */
-
- gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
- u8500_clock_enable(3, 3, 3); /* I2C0 */
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
- gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
- gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
- gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
-
- u8500_clock_enable(1, 5, 5); /* SDI0 */
- u8500_clock_enable(2, 4, 2); /* SDI4 */
-
- u8500_clock_enable(6, 7, -1); /* MTU0 */
- u8500_clock_enable(3, 4, 4); /* SDI2 */
-
- early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
- gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
-
- /*
- * Enabling clocks for all devices which are AMBA devices in the
- * kernel. Otherwise they will not get probe()'d because the
- * peripheral ID register will not be powered.
- */
-
- /* XXX: some of these differ between ED/V1 */
-
- u8500_clock_enable(1, 1, 1); /* UART1 */
- u8500_clock_enable(1, 0, 0); /* UART0 */
-
- u8500_clock_enable(3, 2, 2); /* SSP1 */
- u8500_clock_enable(3, 1, 1); /* SSP0 */
-
- u8500_clock_enable(2, 8, -1); /* SPI0 */
- u8500_clock_enable(2, 5, 3); /* MSP2 */
-}
-
-#ifdef CONFIG_MMC
-static int u8500_mmci_board_init(void)
-{
- enum gpio_error error;
- struct gpio_register *gpio_base_address;
-
- gpio_base_address = (void *)(U8500_GPIO_0_BASE);
- gpio_base_address->gpio_dats |= 0xFFC0000;
- gpio_base_address->gpio_pdis &= ~0xFFC0000;
-
- /* save the GPIO0 AFSELA register */
- error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
- if (error != GPIO_OK) {
- printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
- return -ENODEV;
- }
- return 0;
-}
-
-int board_mmc_init(bd_t *bd)
-{
- struct pl180_mmc_host *host;
-
- if (u8500_mmci_board_init())
- return -ENODEV;
-
- host = malloc(sizeof(struct pl180_mmc_host));
- if (!host)
- return -ENOMEM;
- memset(host, 0, sizeof(*host));
-
- strcpy(host->name, "MMC");
- host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
- host->pwr_init = INIT_PWR;
- host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
- host->voltages = VOLTAGE_WINDOW_MMC;
- host->caps = 0;
- host->clock_in = ARM_MCLK;
- host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
- host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
-
- return arm_pl180_mmci_init(host);
-}
-#endif
-
-
-/*
- * get_pll_freq_khz - return PLL frequency in kHz
- */
-static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
-{
- uint32_t idf, ldf, odf, seldiv, phi;
-
- /*
- * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
- * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
- * where:
- * IDF=R(2:0) (when R=000, IDF=1d)
- * LDF = 2*D(7:0) (D must be greater than or equal to 6)
- * ODF = N(5:0) (when N=000000, 0DF=1d)
- */
-
- idf = (freq_reg & 0x70000) >> 16;
- ldf = (freq_reg & 0xff) * 2;
- odf = (freq_reg & 0x3f00) >> 8;
- seldiv = (freq_reg & 0x01000000) >> 24;
- phi = (inclk_khz * ldf) / (2 * odf * idf);
- if (seldiv)
- phi = phi/2;
-
- return phi;
-}
-
-int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uint32_t inclk_khz;
- uint32_t reg, phi;
- uint32_t clk_khz;
- unsigned int clk_sel;
- struct clk_mgt_regs *clks = clk_mgt_regs;
- struct pll_freq_regs *plls = pll_freq_regs;
-
- /*
- * Go through list of PLLs.
- * Initialise pll out frequency array (pll_khz) and print frequency.
- */
- inclk_khz = 38400; /* 38.4 MHz */
- while (plls->addr) {
- reg = readl(plls->addr);
- phi = get_pll_freq_khz(inclk_khz, reg);
- pll_khz[plls->idx] = phi;
- printf("%s PLL out frequency: %d.%d Mhz\n",
- pll_name[plls->idx], phi/1000, phi % 1000);
- plls++;
- }
-
- /* check ARM clock source */
- reg = readl(PRCM_ARM_CHGCLKREQ_REG);
- printf("A9 running on %s\n",
- (reg & 1) ? "external clock" : "ARM PLL");
-
- /* go through list of clk_mgt_reg */
- printf("\n%19s %9s %7s %9s enabled\n",
- "name(addr)", "value", "PLL", "CLK[MHz]");
- while (clks->addr) {
- reg = readl(clks->addr);
-
- /* convert bit position into array index */
- clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */
-
- if (reg & 0x200)
- clk_khz = 38400; /* CLK38 is set */
- else if ((reg & 0x1f) == 0)
- /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
- clk_khz = 0;
- else
- clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
-
- printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
- clks->descr, clks->addr, reg, pll_name[clk_sel],
- clk_khz / 1000, clk_khz % 1000,
- (reg & 0x100) ? "ena" : "dis");
- clks++;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- clkinfo, 1, 1, do_clkinfo,
- "print clock info",
- ""
-);
+++ /dev/null
-if NOMADIK_NHK8815
-
-config SYS_BOARD
- default "nhk8815"
-
-config SYS_VENDOR
- default "st"
-
-config SYS_CONFIG_NAME
- default "nhk8815"
-
-endif
+++ /dev/null
-NHK8815 BOARD
-M: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
-M: Alessandro Rubini <rubini@unipv.it>
-S: Maintained
-F: board/st/nhk8815/
-F: include/configs/nhk8815.h
-F: configs/nhk8815_defconfig
-F: configs/nhk8815_onenand_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004
-# ARM Ltd.
-# Philippe Robin, <philippe.robin@arm.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := nhk8815.o
+++ /dev/null
-
-The Nomadik 8815 CPU has a "secure" boot mode where no external access
-(not even JTAG) is allowed. The "remap" bits in the evaluation board
-are configured in order to boot from the internal ROM memory (in
-secure mode).
-
-The boot process as defined by the manufacturer executes external code
-(loaded from NAND or OneNAND) that that disables such "security" in
-order to run u-boot and later the kernel without constraints. Such
-code is a proprietary initial boot loader, called "X-Loader" (in case
-anyone wonders, it has no relations with other loaders with the same
-name and there is no GPL code inside the ST X-Loader).
-
-SDRAM configuration, PLL setup and initial loading from NAND is
-implemented in the X-Loader, so U-Boot is already running in SDRAM
-when control is handed over to it.
-
-The Makefile offers two different configurations to be used if you
-boot from Nand or OneNand.
-
- make nhk8815_config
- make nhk8815_onenand_config
-
-Both support OneNand and Nand. Since U-Boot, running in RAM, can't know
-where it was loaded from, the configurations differ in where the filesystem
-is looked for by default.
-
-
-On www.st.com/nomadik and on www.stnwireless.com there are documents,
-summary data and white papers on Nomadik. The full datasheet for
-STn8815 is not currently available on line but under specific request
-to the local ST sales offices.
+++ /dev/null
-/*
- * (C) Copyright 2005
- * STMicrolelctronics, <www.st.com>
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress(int progress)
-{
- printf("%i\n", progress);
-}
-#endif
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
- gd->bd->bi_boot_params = 0x00000100;
- writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
- writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
- writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
- writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
-
- /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
- writel(0x0000305b, REG_FSMC_BCR1);
- writel(0x00033f33, REG_FSMC_BTR1);
-
- /* Set up SMCS0 for OneNand: sram-like once again */
- writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
- writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
-
- icache_enable();
- return 0;
-}
-
-int board_late_init(void)
-{
- /* Set the two I2C gpio lines to be gpio high */
- nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1);
- nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1);
- nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
-
- /* Reset the I2C port expander, on GPIO77 */
- nmk_gpio_af(77, GPIO_GPIO);
- nmk_gpio_dir(77, 1);
- nmk_gpio_set(77, 0);
- udelay(10);
- nmk_gpio_set(77, 1);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
F: configs/Chuwi_V7_CW0825_defconfig
F: configs/Cubieboard_defconfig
F: configs/Hyundai_A7HD_defconfig
+F: configs/inet1_defconfig
F: configs/inet97fv2_defconfig
+F: configs/inet9f_rev03_defconfig
F: configs/jesurun_q5_defconfig
F: configs/Mele_A1000_defconfig
F: configs/Mele_M3_defconfig
F: configs/Mini-X_defconfig
F: configs/mk802_defconfig
F: configs/mk802ii_defconfig
+F: configs/pov_protab2_ips9_defconfig
F: include/configs/sun5i.h
F: configs/A10s-OLinuXino-M_defconfig
F: configs/A13-OLinuXino_defconfig
F: configs/Auxtek-T004_defconfig
F: configs/inet98v_rev2_defconfig
F: configs/mk802_a10s_defconfig
+F: configs/q8_a13_tablet_defconfig
F: configs/r7-tv-dongle_defconfig
F: configs/UTOO_P66_defconfig
F: include/configs/sun6i.h
F: configs/CSQ_CS908_defconfig
F: configs/Mele_A1000G_quad_defconfig
F: configs/Mele_M9_defconfig
+F: configs/Wobo_i5_defconfig
F: include/configs/sun7i.h
F: configs/A20-OLinuXino_MICRO_defconfig
F: configs/Bananapi_defconfig
F: configs/gt90h_v4_defconfig
F: configs/Ippo_q8h_v1_2_defconfig
F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig
+F: configs/q8_a23_tablet_800x480_defconfig
+F: configs/q8_a33_tablet_800x480_defconfig
+F: configs/q8_a33_tablet_1024x600_defconfig
F: include/configs/sun9i.h
F: configs/Merrii_A80_Optimus_defconfig
}
#endif
+#if !defined(CONFIG_SPL_BUILD)
+#include <asm/arch/spl.h>
+
+/*
+ * Check the SPL header for the "sunxi" variant. If found: parse values
+ * that might have been passed by the loader ("fel" utility), and update
+ * the environment accordingly.
+ */
+static void parse_spl_header(const uint32_t spl_addr)
+{
+ struct boot_file_head *spl = (void *)spl_addr;
+ if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
+ uint8_t spl_header_version = spl->spl_signature[3];
+ if (spl_header_version == SPL_HEADER_VERSION) {
+ if (spl->fel_script_address)
+ setenv_hex("fel_scriptaddr",
+ spl->fel_script_address);
+ return;
+ }
+ printf("sunxi SPL version mismatch: expected %u, got %u\n",
+ SPL_HEADER_VERSION, spl_header_version);
+ }
+}
+#endif
+
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uint8_t mac_addr[6];
int ret;
+#if !defined(CONFIG_SPL_BUILD)
+ setenv("fel_booted", NULL);
+ setenv("fel_scriptaddr", NULL);
+ /* determine if we are running in FEL mode */
+ if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
+ setenv("fel_booted", "1");
+ parse_spl_header(SPL_ADDR);
+ }
+#endif
+
ret = sunxi_get_sid(sid);
if (ret == 0 && sid[0] != 0 && sid[3] != 0) {
if (!getenv("ethaddr")) {
host->dev_index = 0;
host->bus_hz = 50000000;
- add_dwmci(host, host->bus_hz, 400000);
+ add_dwmci(host, host->bus_hz / 2, 400000);
return 0;
}
+++ /dev/null
-if TARGET_STAMP9G20
-
-config SYS_BOARD
- default "stamp9g20"
-
-config SYS_VENDOR
- default "taskit"
-
-config SYS_CONFIG_NAME
- default "stamp9g20"
-
-endif
+++ /dev/null
-STAMP9G20 BOARD
-M: Markus Hubig <mhubig@imko.de>
-S: Maintained
-F: board/taskit/stamp9g20/
-F: include/configs/stamp9g20.h
-F: configs/portuxg20_defconfig
-F: configs/stamp9g20_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Stelian Pop <stelian@popies.net>
-# Lead Tech Design <www.leadtechdesign.com>
-#
-# (C) Copyright 2012
-# Markus Hubig <mhubig@imko.de>
-# IMKO GmbH <www.imko.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += stamp9g20.o
-obj-y += led.o
+++ /dev/null
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * (C) Copyright 2012
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pmc.h>
-#include <status_led.h>
-
-static unsigned int saved_state[3] = {STATUS_LED_OFF,
- STATUS_LED_OFF, STATUS_LED_OFF};
-
-void coloured_LED_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable the clock */
- writel(ATMEL_ID_PIOC, &pmc->pcer);
-
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
-
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
-}
-
-void red_led_on(void)
-{
- at91_set_gpio_value(CONFIG_RED_LED, 1);
- saved_state[STATUS_LED_RED] = STATUS_LED_ON;
-}
-
-void red_led_off(void)
-{
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
-}
-
-void green_led_on(void)
-{
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
-}
-
-void green_led_off(void)
-{
- at91_set_gpio_value(CONFIG_GREEN_LED, 0);
- saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
-}
-
-void yellow_led_on(void)
-{
- at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
-}
-
-void yellow_led_off(void)
-{
- at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
- saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
-}
-
-void __led_init(led_id_t mask, int state)
-{
- __led_set(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
- if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
- red_led_off();
- else
- red_led_on();
-
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
- green_led_off();
- else
- green_led_on();
-
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
- yellow_led_off();
- else
- yellow_led_on();
- }
-}
-
-void __led_set(led_id_t mask, int state)
-{
- if (STATUS_LED_RED == mask) {
- if (STATUS_LED_ON == state)
- red_led_on();
- else
- red_led_off();
-
- } else if (STATUS_LED_GREEN == mask) {
- if (STATUS_LED_ON == state)
- green_led_on();
- else
- green_led_off();
-
- } else if (STATUS_LED_YELLOW == mask) {
- if (STATUS_LED_ON == state)
- yellow_led_on();
- else
- yellow_led_off();
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * Achim Ehrlich <aehrlich@taskit.de>
- * taskit GmbH <www.taskit.de>
- *
- * (C) Copyright 2012-
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_MACB
-# include <net.h>
-# include <netdev.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void stamp9G20_nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- unsigned long csa;
-
- /* Assign CS3 to NAND/SmartMedia Interface */
- csa = readl(&matrix->ebicsa);
- csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
- writel(csa, &matrix->ebicsa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
-
- /* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-
-#ifdef CONFIG_MACB
-static void stamp9G20_macb_hw_init(void)
-{
- struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
- /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
- at91_set_gpio_output(AT91_PIN_PA26, 0);
-
- /*
- * Disable pull-up on:
- * RXDV (PA17) => PHY normal mode (not Test mode)
- * ERX0 (PA14) => PHY ADDR0
- * ERX1 (PA15) => PHY ADDR1
- * ERX2 (PA25) => PHY ADDR2
- * ERX3 (PA26) => PHY ADDR3
- * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
- *
- * PHY has internal pull-down
- */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA17) |
- pin_to_mask(AT91_PIN_PA18) |
- pin_to_mask(AT91_PIN_PA28),
- &pioa->pudr);
-
- at91_phy_reset();
-
- /* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA17) |
- pin_to_mask(AT91_PIN_PA18) |
- pin_to_mask(AT91_PIN_PA28),
- &pioa->puer);
-
- /* Initialize EMAC=MACB hardware */
- at91_macb_hw_init();
-}
-#endif /* CONFIG_MACB */
-
-int board_early_init_f(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOC), &pmc->pcer);
-
- return 0;
-}
-
-int board_postclk_init(void)
-{
- /*
- * Initialize the serial interface here, because be need a running
- * timer to set PC9 to high and wait for some time to enable the
- * level converter of the RS232 interface on the PortuxG20 board.
- */
-
-#ifdef CONFIG_PORTUXG20
- at91_set_gpio_output(AT91_PIN_PC9, 1);
- mdelay(1);
-#endif
- at91_seriald_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- stamp9G20_nand_hw_init();
-#ifdef CONFIG_MACB
- stamp9G20_macb_hw_init();
-#endif
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_MACB
-int board_eth_init(bd_t *bis)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
-}
-#endif /* CONFIG_MACB */
--- /dev/null
+if TARGET_AM335X_SL50
+
+config SYS_BOARD
+ default "sl50"
+
+config SYS_VENDOR
+ default "tcl"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "am335x_sl50"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. Depending on your specific
+ board you may want something other than UART0 as for example the IDK
+ uses UART3 so enter 4 here.
+
+config DM_GPIO
+ default y
+
+config DM_SERIAL
+ default y
+
+endif
--- /dev/null
+SL50 BOARD
+M: Enric Balletbo i Serra <enric.balletbo@collabora.com>
+S: Maintained
+F: board/tcl/sl50/
+F: include/configs/am335x_sl50.h
+F: configs/am335x_sl50_defconfig
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
--- /dev/null
+/*
+ * board.c
+ *
+ * Board functions for TCL SL50 board
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static const struct ddr_data ddr3_sl50_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_sl50_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr_sl50 = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ int mpu_vdd;
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* BeagleBone PMIC Code */
+ int usb_cur_lim;
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_POWER_PATH,
+ usb_cur_lim,
+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /*
+ * Set LDO3 to 1.8V and LDO4 to 3.3V
+ */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ return &dpll_ddr_sl50;
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+ enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+ enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+ enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+ enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+ enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+ .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(400, &ioregs_bonelt,
+ &ddr3_sl50_data,
+ &ddr3_sl50_cmd_ctrl_data,
+ &ddr3_sl50_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards. We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
+ && defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ethaddr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_MII;
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the first instance.
+ */
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+ rv = usb_eth_initialize(bis);
+ if (rv < 0)
+ printf("Error %d registering USB_ETHER\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif
--- /dev/null
+/*
+ * board.h
+ *
+ * TCL SL50 boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+}
+++ /dev/null
-if TARGET_OMAP3_SDP3430
-
-config SYS_BOARD
- default "sdp3430"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap3_sdp3430"
-
-endif
+++ /dev/null
-SDP3430 BOARD
-M: Nishanth Menon <nm@ti.com>
-S: Maintained
-F: board/ti/sdp3430/
-F: include/configs/omap3_sdp3430.h
-F: configs/omap3_sdp3430_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sdp.o
+++ /dev/null
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
+++ /dev/null
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "sdp.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 SDP3430 board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#elif defined(CONFIG_ENV_IS_IN_NAND)
- "NAND",
-#else
- "NOR",
-#endif
-};
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-static const u32 gpmc_sdp_nor[] = {
- SDP3430_NOR_GPMC_CONF1,
- SDP3430_NOR_GPMC_CONF2,
- SDP3430_NOR_GPMC_CONF3,
- SDP3430_NOR_GPMC_CONF4,
- SDP3430_NOR_GPMC_CONF5,
- SDP3430_NOR_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-static const u32 gpmc_sdp_debug[] = {
- SDP3430_DEBUG_GPMC_CONF1,
- SDP3430_DEBUG_GPMC_CONF2,
- SDP3430_DEBUG_GPMC_CONF3,
- SDP3430_DEBUG_GPMC_CONF4,
- SDP3430_DEBUG_GPMC_CONF5,
- SDP3430_DEBUG_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* Timing defintions for GPMC OneNAND */
-static const u32 gpmc_sdp_onenand[] = {
- SDP3430_ONENAND_GPMC_CONF1,
- SDP3430_ONENAND_GPMC_CONF2,
- SDP3430_ONENAND_GPMC_CONF3,
- SDP3430_ONENAND_GPMC_CONF4,
- SDP3430_ONENAND_GPMC_CONF5,
- SDP3430_ONENAND_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* GPMC definitions for GPMC NAND */
-static const u32 gpmc_sdp_nand[] = {
- SDP3430_NAND_GPMC_CONF1,
- SDP3430_NAND_GPMC_CONF2,
- SDP3430_NAND_GPMC_CONF3,
- SDP3430_NAND_GPMC_CONF4,
- SDP3430_NAND_GPMC_CONF5,
- SDP3430_NAND_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* gpmc_cfg is initialized by gpmc_init and we use it here */
-extern struct gpmc *gpmc_cfg;
-
-/**
- * @brief board_init - gpmc and basic setup as phase1 of boot sequence
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* TODO: Dynamically pop out CS mapping and program accordingly */
- /* Configure devices for default ON ON ON settings */
- enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
- CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
- enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
- GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
- GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
- GPMC_SIZE_16M);
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
-#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
-
-/**
- * @brief board_eth_init Take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- */
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- int cnt = 20;
-
- writew(0x0, LAN_RESET_REGISTER);
- do {
- writew(0x1, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto reset_err_out;
- --cnt;
- } while (readw(LAN_RESET_REGISTER) != 0x1);
-
- cnt = 20;
-
- do {
- writew(0x0, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto reset_err_out;
- --cnt;
- } while (readw(LAN_RESET_REGISTER) != 0x0000);
- udelay(1000);
-
- writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
- udelay(1000);
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-reset_err_out:
-
-#endif
- return rc;
-}
-
-/**
- * @brief misc_init_r - Configure SDP board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- /* Partial setup:
- * VAUX3 - 2.8V for DVI
- * VPLL1 - 1.8V
- * VDAC - 1.8V
- * and turns on LEDA/LEDB (not needed ... NOP?)
- */
- twl4030_power_init();
-
- /* FIXME finish setup:
- * VAUX1 - 2.8V for mainboard I/O
- * VAUX2 - 2.8V for camera
- * VAUX4 - 1.8V for OMAP3 CSI
- * VMMC1 - 3.15V (init, variable) for MMC1
- * VMMC2 - 1.85V for MMC2
- * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
- * VPLL2 - 1.8V
- */
-
- return 0;
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the hardware. Many pins need to be moved from protect
- * to primary mode.
- */
-void set_muxconf_regs(void)
-{
- /* platform specific muxes */
- MUX_SDP3430();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _BOARD_SDP_H_
-#define _BOARD_SDP_H_
-
-#define OFF_IN_PD 0
-#define OFF_OUT_PD 0
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_SDP3430()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
- MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
- MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
- MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
- MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
- MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
- MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
- MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
- MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Audio InterfACe */\
- MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- /*Expansion Card */\
- MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
- MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
- MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
- MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
- MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
- MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
- MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
- MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
- MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
- MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
- MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
- MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
- MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
- MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
- MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
- MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
- MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
- MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
- MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
- MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
- MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
-
-/*
- * GPMC Timing definitions for SDP3430
- * at L3 = 166Mhz
- */
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-#define SDP3430_NOR_GPMC_CONF1 0x00001200
-#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
-#define SDP3430_NOR_GPMC_CONF3 0x00080802
-#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
-#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
-#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
-#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
-#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
-#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
-#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
-#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
-
-/* Timing defintions for GPMC OneNAND */
-#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
-#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
-#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
-#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
-#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
-#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
-
-/* GPMC definitions for GPMC NAND */
-#define SDP3430_NAND_GPMC_CONF1 0x00000800
-#define SDP3430_NAND_GPMC_CONF2 0x00141400
-#define SDP3430_NAND_GPMC_CONF3 0x00141400
-#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
-#define SDP3430_NAND_GPMC_CONF5 0x010C1414
-#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
-
-#endif /* _BOARD_SDP_H_ */
TI814X BOARD
-M: Matt Porter <matt.porter@linaro.org>
+M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/ti814x/
F: include/configs/ti814x_evm.h
TI816X BOARD
-#M: -
+M: Tom Rini <trini@konsulko.com>
S: Maintained
F: board/ti/ti816x/
F: include/configs/ti816x_evm.h
/* Change the NOR timings to optimum value to get maximum bandwidth */
emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
- emc->stat[0].waitoen = EMC_STAT_WAITOEN(1);
+ emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
#define USB_PEN_GPIO 83
+static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
+ /* levelling */
+ { DDRMC_CR97_WRLVL_EN, 97 },
+ { DDRMC_CR98_WRLVL_DL_0(0), 98 },
+ { DDRMC_CR99_WRLVL_DL_1(0), 99 },
+ { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
+ { DDRMC_CR105_RDLVL_DL_0(0), 105 },
+ { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
+ { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
+ /* AXI */
+ { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
+ { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
+ { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+ DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
+ { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+ DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
+ { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), 122 },
+ { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+ DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
+ { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
+ { DDRMC_CR126_PHY_RDLAT(8), 126 },
+ { DDRMC_CR132_WRLAT_ADJ(5) |
+ DDRMC_CR132_RDLAT_ADJ(6), 132 },
+ { DDRMC_CR137_PHYCTL_DL(2), 137 },
+ { DDRMC_CR138_PHY_WRLV_MXDL(256) |
+ DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
+ { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) |
+ DDRMC_CR139_PHY_WRLV_EN(3), 139 },
+ { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
+ { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+ DDRMC_CR143_RDLV_MXDL(128), 143 },
+ { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+ DDRMC_CR144_PHY_RDLV_DLL(3) |
+ DDRMC_CR144_PHY_RDLV_EN(3), 144 },
+ { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
+ { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
+ { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
+ { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
+ { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+ DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
+
+ { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1) |
+ DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+ DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
+ { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
+ { DDRMC_CR158_TWR(6), 158 },
+ { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+ DDRMC_CR161_TODTH_WR(2), 161 },
+ /* end marker */
+ { 0, -1 }
+};
+
static const iomux_v3_cfg_t usb_pads[] = {
VF610_PAD_PTD4__GPIO_83,
};
int dram_init(void)
{
static const struct ddr3_jedec_timings timings = {
- .tinit = 5,
- .trst_pwron = 80000,
- .cke_inactive = 200000,
- .wrlat = 5,
- .caslat_lin = 12,
- .trc = 21,
- .trrd = 4,
- .tccd = 4,
- .tfaw = 20,
- .trp = 6,
- .twtr = 4,
- .tras_min = 15,
- .tmrd = 4,
- .trtp = 4,
- .tras_max = 28080,
- .tmod = 12,
- .tckesr = 4,
- .tcke = 3,
- .trcd_int = 6,
- .tdal = 12,
- .tdll = 512,
- .trp_ab = 6,
- .tref = 3120,
- .trfc = 64,
- .tpdex = 3,
- .txpdll = 10,
- .txsnr = 48,
- .txsr = 468,
- .cksrx = 5,
- .cksre = 5,
- .zqcl = 256,
- .zqinit = 512,
- .zqcs = 64,
- .ref_per_zq = 64,
- .aprebit = 10,
- .wlmrd = 40,
- .wldqsen = 25,
+ .tinit = 5,
+ .trst_pwron = 80000,
+ .cke_inactive = 200000,
+ .wrlat = 5,
+ .caslat_lin = 12,
+ .trc = 21,
+ .trrd = 4,
+ .tccd = 4,
+ .tbst_int_interval = 0,
+ .tfaw = 20,
+ .trp = 6,
+ .twtr = 4,
+ .tras_min = 15,
+ .tmrd = 4,
+ .trtp = 4,
+ .tras_max = 28080,
+ .tmod = 12,
+ .tckesr = 4,
+ .tcke = 3,
+ .trcd_int = 6,
+ .tras_lockout = 0,
+ .tdal = 12,
+ .bstlen = 0,
+ .tdll = 512,
+ .trp_ab = 6,
+ .tref = 3120,
+ .trfc = 64,
+ .tref_int = 0,
+ .tpdex = 3,
+ .txpdll = 10,
+ .txsnr = 48,
+ .txsr = 468,
+ .cksrx = 5,
+ .cksre = 5,
+ .freq_chg_en = 0,
+ .zqcl = 256,
+ .zqinit = 512,
+ .zqcs = 64,
+ .ref_per_zq = 64,
+ .zqcs_rotate = 0,
+ .aprebit = 10,
+ .cmd_age_cnt = 64,
+ .age_cnt = 64,
+ .q_fullness = 7,
+ .odt_rd_mapcs0 = 0,
+ .odt_wr_mapcs0 = 1,
+ .wlmrd = 40,
+ .wldqsen = 25,
};
- ddrmc_setup_iomux();
+ ddrmc_setup_iomux(NULL, 0);
- ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
+ ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
config SYS_VENDOR
default "tqc"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "tqma6"
bus = fec_get_miibus(base, -1);
if (!bus)
- return 0;
+ return -EINVAL;
/* scan phy */
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
- free(bus);
- puts("No phy found\n");
- return 0;
+ ret = -EINVAL;
+ goto free_bus;
}
ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- puts("FEC MXC: probe failed\n");
- free(phydev);
- free(bus);
- }
+ if (ret)
+ goto free_phydev;
return 0;
+
+free_phydev:
+ free(phydev);
+free_bus:
+ free(bus);
+ return ret;
}
int tqma6_bb_board_early_init_f(void)
+++ /dev/null
-if TARGET_TRIZEPSIV
-
-config SYS_BOARD
- default "trizepsiv"
-
-config SYS_CONFIG_NAME
- default "trizepsiv"
-
-endif
+++ /dev/null
-TRIZEPSIV BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/trizepsiv/
-F: include/configs/trizepsiv.h
-F: configs/polaris_defconfig
-F: configs/trizepsiv_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := conxs.o eeprom.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
- *
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-#if CONFIG_MK_POLARIS
-#define BOOT_CONSOLE "serial_stuart"
-#else
-#define BOOT_CONSOLE "serial_ffuart"
-#endif
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
- writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of ConXS Board */
- gd->bd->bi_arch_number = 776;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa000003c;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- char *console=getenv("boot_console");
-
- if ((console == NULL) || (strcmp(console,"serial_btuart") &&
- strcmp(console,"serial_stuart") &&
- strcmp(console,"serial_ffuart"))) {
- console = BOOT_CONSOLE;
- }
- setenv("stdout",console);
- setenv("stdin", console);
- setenv("stderr",console);
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <dm9000.h>
-
-static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- unsigned int i;
- u8 data[2];
-
- for (i=0; i < 0x40; i++) {
- if (!(i % 0x10))
- printf("\n%08x:", i);
- dm9000_read_srom_word(i, data);
- printf(" %02x%02x", data[1], data[0]);
- }
- printf ("\n");
- return (0);
-}
-
-static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- int offset,value;
-
- if (argc < 4)
- return cmd_usage(cmdtp);
-
- offset=simple_strtoul(argv[2],NULL,16);
- value=simple_strtoul(argv[3],NULL,16);
- if (offset > 0x40) {
- printf("Wrong offset : 0x%x\n",offset);
- return cmd_usage(cmdtp);
- }
- dm9000_write_srom_word(offset, value);
- return (0);
-}
-
-int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if (strcmp (argv[1],"read") == 0)
- return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
- else if (strcmp (argv[1],"write") == 0)
- return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
- else
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- dm9000ee,4,1,do_dm9000_eeprom,
- "Read/Write eeprom connected to Ethernet Controller",
- "\ndm9000ee write <word offset> <value> \n"
- "\tdm9000ee read \n"
- "\tword:\t\t00-02 : MAC Address\n"
- "\t\t\t03-07 : DM9000 Configuration\n"
- "\t\t\t08-63 : User data"
-);
+++ /dev/null
-if TARGET_VISION2
-
-config SYS_BOARD
- default "vision2"
-
-config SYS_VENDOR
- default "ttcontrol"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "vision2"
-
-endif
+++ /dev/null
-VISION2 BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/ttcontrol/vision2/
-F: include/configs/vision2.h
-F: configs/vision2_defconfig
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := vision2.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * (C) Copyright 2010
- * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/*
- * Boot Device : one of
- * spi, nand, onenand, sd
- */
-BOOT_FROM spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-
-/*
- * #######################
- * ### Disable WDOG ###
- * #######################
- */
-DATA 2 0x73f98000 0x30
-
-/*
- * #######################
- * ### SET DDR Clk ###
- * #######################
- */
-/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
-DATA 4 0x73FD4018 0x000024C0
-
-/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
-DATA 4 0x73FD4038 0x2010241
-
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8600 0x00000107
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8604 0x00000107
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8608 0x00000187
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa860c 0x00000187
-/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
-DATA 4 0x73fa8614 0x00000107
-/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
-DATA 4 0x73fa86a8 0x00000187
-
-/*
- * #######################
- * ### Settings IOMUXC ###
- * #######################
- */
-/*
- * DDR IOMUX configuration
- * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
- * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
- */
-DATA 4 0x73fa84b8 0x000000e7
-/* PVTC MAX (at GPC, PGR reg) */
-/* DATA 4 0x73FD8004 0x1fc00000 */
-
-/* DQM0 DS high slew rate slow */
-DATA 4 0x73fa84d4 0x000000e4
-/* DQM1 DS high slew rate slow */
-DATA 4 0x73fa84d8 0x000000e4
-/* DQM2 DS high slew rate slow */
-DATA 4 0x73fa84dc 0x000000e4
-/* DQM3 DS high slew rate slow */
-DATA 4 0x73fa84e0 0x000000e4
-
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
-DATA 4 0x73fa84bc 0x000000c4
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
-DATA 4 0x73fa84c0 0x000000c4
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
-DATA 4 0x73fa84c4 0x000000c4
-/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
-DATA 4 0x73fa84c8 0x000000c4
-
-/* DRAM_DATA B0 */
-DATA 4 0x73fa88a4 0x00000004
-/* DRAM_DATA B1 */
-DATA 4 0x73fa88ac 0x00000004
-/* DRAM_DATA B2 */
-DATA 4 0x73fa88b8 0x00000004
-/* DRAM_DATA B3 */
-DATA 4 0x73fa882c 0x00000004
-
-/* DRAM_DATA B0 slew rate */
-DATA 4 0x73fa8878 0x00000000
-/* DRAM_DATA B1 slew rate */
-DATA 4 0x73fa8880 0x00000000
-/* DRAM_DATA B2 slew rate */
-DATA 4 0x73fa888c 0x00000000
-/* DRAM_DATA B3 slew rate */
-DATA 4 0x73fa889c 0x00000000
-
-/*
- * #######################
- * ### Configure SDRAM ###
- * #######################
- */
-
-/* Configure CS0 */
-/* ####################### */
-
-/* ESDCTL0: Enable controller */
-DATA 4 0x83fd9000 0x83220000
-
-/* Init DRAM on CS0 */
-/* ESDSCR: Precharge command */
-DATA 4 0x83fd9014 0x04008008
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008010
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008010
-/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
-DATA 4 0x83fd9014 0x00338018
-/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
-DATA 4 0x83fd9014 0x0020801a
-/* ESDSCR */
-DATA 4 0x83fd9014 0x00008000
-
-/* ESDSCR: EMR with full Drive strength */
-/* DATA 4 0x83fd9014 0x0000801a */
-
-/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
-DATA 4 0x83fd9000 0xC3220000
-
-/*
- * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
- * DATA 4 0x83fd9004 0xC33574AA
- */
-/*
- * micron mDDR
- * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- * DATA 4 0x83FD9004 0x101564a8
- */
-/*
- * hynix mDDR
- * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- */
-DATA 4 0x83FD9004 0x704564a8
-
-/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
-DATA 4 0x83fd9010 0x000a1700
-
-/* Configure CS1 */
-/* ####################### */
-
-/* ESDCTL1: Enable controller */
-DATA 4 0x83fd9008 0x83220000
-
-/* Init DRAM on CS1 */
-/* ESDSCR: Precharge command */
-DATA 4 0x83fd9014 0x0400800c
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008014
-/* ESDSCR: Refresh command */
-DATA 4 0x83fd9014 0x00008014
-/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
-DATA 4 0x83fd9014 0x0033801c
-/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
-DATA 4 0x83fd9014 0x0020801e
-/* ESDSCR */
-DATA 4 0x83fd9014 0x00008004
-
-/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
-DATA 4 0x83fd9008 0xC3220000
-/*
- * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
- * DATA 4 0x83fd900c 0xC33574AA
- */
-/*
- * micron mDDR
- * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- * DATA 4 0x83FD900C 0x101564a8
- */
-/*
- * hynix mDDR
- * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
- * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
- */
-DATA 4 0x83FD900C 0x704564a8
-
-/* ESDSCR (mDRAM configuration finished) */
-DATA 4 0x83FD9014 0x00000004
-
-/* ESDSCR - clear "configuration request" bit */
-DATA 4 0x83fd9014 0x00000000
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx51.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/imx-common/spi.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <power/pmic.h>
-#include <fsl_esdhc.h>
-#include <fsl_pmic.h>
-#include <mc13892.h>
-#include <linux/fb.h>
-
-#include <ipu_pixfmt.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct fb_videomode const nec_nl6448bc26_09c = {
- "NEC_NL6448BC26-09C",
- 60, /* Refresh */
- 640, /* xres */
- 480, /* yres */
- 37650, /* pixclock = 26.56Mhz */
- 48, /* left margin */
- 16, /* right margin */
- 31, /* upper margin */
- 12, /* lower margin */
- 96, /* hsync-len */
- 2, /* vsync-len */
- 0, /* sync */
- FB_VMODE_NONINTERLACED, /* vmode */
- 0, /* flag */
-};
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-void hw_watchdog_reset(void)
-{
- int val;
-
- /* toggle watchdog trigger pin */
- val = gpio_get_value(IMX_GPIO_NR(3, 2));
- val = val ? 0 : 1;
- gpio_set_value(IMX_GPIO_NR(3, 2), val);
-}
-#endif
-
-static void init_drive_strength(void)
-{
- static const iomux_v3_cfg_t ddr_pads[] = {
- NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
- NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
- NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
- NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
- NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
- NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
- NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
-
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
- MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-static void setup_weim(void)
-{
- struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
-
- pweim->cs0gcr1 = 0x004100b9;
- pweim->cs0gcr2 = 0x00000001;
- pweim->cs0rcr1 = 0x0a018000;
- pweim->cs0rcr2 = 0;
- pweim->cs0wcr1 = 0x0704a240;
-}
-
-static void setup_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
- MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == 0 && cs == 1) ? 121 : -1;
-}
-
-void spi_io_init(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
- PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
- PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
- PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-static void reset_peripherals(int reset)
-{
-#ifdef CONFIG_VISION2_HW_1_0
- static const iomux_v3_cfg_t fec_cfg_pads[] = {
- /* RXD1 */
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
- /* RXD2 */
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
- /* RXD3 */
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
- /* RXER */
- NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
- /* COL */
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
- /* RCLK */
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
- /* RXD0 */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
- MX51_PAD_NANDF_D9__FEC_RDATA0,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
- MX51_PAD_EIM_CS4__FEC_RX_ER,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
- };
-#endif
-
- if (reset) {
-
- /* reset_n is on NANDF_D15 */
- gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
-
-#ifdef CONFIG_VISION2_HW_1_0
- /*
- * set FEC Configuration lines
- * set levels of FEC config lines
- */
- gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
- gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
- gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
-
- /* set direction of FEC config lines */
- gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
- gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
- gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
- gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
-
- imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
- ARRAY_SIZE(fec_cfg_pads));
-#endif
-
- /* activate reset_n pin */
- imx_iomux_v3_setup_pad(
- NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
- PAD_CTL_DSE_MAX));
- } else {
- /* set FEC Control lines */
- gpio_direction_input(IMX_GPIO_NR(3, 25));
- udelay(500);
-
-#ifdef CONFIG_VISION2_HW_1_0
- imx_iomux_v3_setup_multiple_pads(fec_pads,
- ARRAY_SIZE(fec_pads));
-#endif
- }
-}
-
-static void power_init_mx51(void)
-{
- unsigned int val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_PMIC);
- if (ret)
- return;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return;
-
- /* Write needed to Power Gate 2 register */
- pmic_reg_read(p, REG_POWER_MISC, &val);
-
- /* enable VCAM with 2.775V to enable read from PMIC */
- val = VCAMCONFIG | VCAMEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- /*
- * Set switchers in Auto in NORMAL mode & STANDBY mode
- * Setup the switcher mode for SW1 & SW2
- */
- pmic_reg_read(p, REG_SW_4, &val);
- val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
- (SWMODE_MASK << SWMODE2_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(p, REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- pmic_reg_read(p, REG_SW_5, &val);
- val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
- (SWMODE_MASK << SWMODE3_SHIFT));
- val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
- pmic_reg_write(p, REG_SW_5, val);
-
-
- /* Set VGEN3 to 1.8V, VCAM to 3.0V */
- pmic_reg_read(p, REG_SETTING_0, &val);
- val &= ~(VCAM_MASK | VGEN3_MASK);
- val |= VCAM_3_0;
- pmic_reg_write(p, REG_SETTING_0, val);
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
- pmic_reg_read(p, REG_SETTING_1, &val);
- val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
- val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
- pmic_reg_write(p, REG_SETTING_1, val);
-
- /* Configure VGEN3 and VCAM regulators to use external PNP */
- val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(p, REG_MODE_1, val);
- udelay(200);
-
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
- VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- pmic_reg_read(p, REG_POWER_CTL2, &val);
- val |= WDIRESET;
- pmic_reg_write(p, REG_POWER_CTL2, val);
-
- udelay(2500);
-
-}
-#endif
-
-static void setup_gpios(void)
-{
- static const iomux_v3_cfg_t gpio_pads_1[] = {
- NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
- NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* DAB Display EN */
- NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
- };
-
- static const iomux_v3_cfg_t gpio_pads_2[] = {
- NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* Display2 TxEN */
- NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* DAB Light EN */
- NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* AUDIO_MUTE */
- NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* SPARE_OUT */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* BEEPER_EN */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* POWER_OFF */
- NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* FRAM_WE */
- NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
- PAD_CTL_DSE_MED), /* EXPANSION_EN */
- MX51_PAD_GPIO1_2__PWM1_PWMO,
- };
-
- unsigned int i;
-
- imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
-
- /* Now we need to trigger the watchdog */
- WATCHDOG_RESET();
-
- imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
-
- /*
- * Set GPIO1_4 to high and output; it is used to reset
- * the system on reboot
- */
- gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
-
- gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
- for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
- gpio_direction_output(i, 0);
-
- gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
-
- /* Set POWER_OFF high */
- gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
-
- gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
-
- gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
-
- gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
-
- WATCHDOG_RESET();
-}
-
-static void setup_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- MX51_PAD_NANDF_CS3__FEC_MDC,
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
- MX51_PAD_NANDF_D9__FEC_RDATA0,
- MX51_PAD_NANDF_CS6__FEC_TDATA3,
- MX51_PAD_NANDF_CS5__FEC_TDATA2,
- MX51_PAD_NANDF_CS4__FEC_TDATA1,
- MX51_PAD_NANDF_D8__FEC_TDATA0,
- MX51_PAD_NANDF_CS7__FEC_TX_EN,
- MX51_PAD_NANDF_CS2__FEC_TX_ER,
- MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
- MX51_PAD_EIM_CS5__FEC_CRS,
- MX51_PAD_EIM_CS4__FEC_RX_ER,
- NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {MMC_SDHC1_BASE_ADDR},
-};
-
-int get_mmc_getcd(u8 *cd, struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
- else
- *cd = 0;
-
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(bd_t *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
- PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
- };
-
- imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
-void lcd_enable(void)
-{
- static const iomux_v3_cfg_t lcd_pads[] = {
- MX51_PAD_DI1_PIN2__DI1_PIN2,
- MX51_PAD_DI1_PIN3__DI1_PIN3,
- };
-
- int ret;
-
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-
- gpio_set_value(IMX_GPIO_NR(1, 2), 1);
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
- NO_PAD_CTRL));
-
- ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
- if (ret)
- puts("LCD cannot be configured\n");
-}
-
-int board_early_init_f(void)
-{
-
-
- init_drive_strength();
-
- /* Setup debug led */
- gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
-
- /* wait a little while to give the pll time to settle */
- sdelay(100000);
-
- setup_weim();
- setup_uart();
- setup_fec();
- setup_gpios();
-
- spi_io_init();
-
- return 0;
-}
-
-static void backlight(int on)
-{
- if (on) {
- gpio_set_value(IMX_GPIO_NR(3, 1), 1);
- udelay(10000);
- gpio_set_value(IMX_GPIO_NR(3, 4), 1);
- } else {
- gpio_set_value(IMX_GPIO_NR(3, 1), 0);
- gpio_set_value(IMX_GPIO_NR(3, 4), 0);
- }
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- lcd_enable();
-
- backlight(1);
-
- return 0;
-}
-
-int board_late_init(void)
-{
- power_init_mx51();
-
- reset_peripherals(1);
- udelay(2000);
- reset_peripherals(0);
- udelay(2000);
-
- /* Early revisions require a second reset */
-#ifdef CONFIG_VISION2_HW_1_0
- reset_peripherals(1);
- udelay(2000);
- reset_peripherals(0);
- udelay(2000);
-#endif
-
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-int checkboard(void)
-{
- puts("Board: TTControl Vision II CPU V\n");
-
- return 0;
-}
-
-int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int on;
-
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- on = (strcmp(argv[1], "on") == 0);
- backlight(on);
-
- return 0;
-}
-
-U_BOOT_CMD(
- lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
- "Vision2 Backlight",
- "lcdbl [on|off]\n"
-);
config SYS_BOARD
default "udoo"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "udoo"
#ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
- return 0;
+ return -EINVAL;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
- free(bus);
- return 0;
+ ret = -EINVAL;
+ goto free_bus;
}
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- free(phydev);
- free(bus);
- }
+ if (ret)
+ goto free_phydev;
#endif
return 0;
+
+free_phydev:
+ free(phydev);
+free_bus:
+ free(bus);
+ return ret;
}
int board_mmc_init(bd_t *bis)
+++ /dev/null
-if TARGET_VPAC270
-
-config SYS_BOARD
- default "vpac270"
-
-config SYS_CONFIG_NAME
- default "vpac270"
-
-endif
+++ /dev/null
-VPAC270 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/vpac270/
-F: include/configs/vpac270.h
-F: configs/vpac270_nor_128_defconfig
-F: configs/vpac270_nor_256_defconfig
-F: configs/vpac270_ond_256_defconfig
+++ /dev/null
-#
-# Voipac PXA270 Support
-#
-# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifndef CONFIG_SPL_BUILD
-obj-y := vpac270.o
-else
-obj-y := onenand.o
-endif
+++ /dev/null
-/*
- * Voipac PXA270 OneNAND SPL
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <onenand_uboot.h>
-#include <asm/arch/pxa.h>
-
-void board_init_f(unsigned long unused)
-{
- extern uint32_t _end;
- uint32_t tmp;
-
- asm volatile("mov %0, pc" : "=r"(tmp));
- tmp >>= 24;
-
- /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */
- if (tmp == 0) {
- tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE;
- onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE);
- asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE));
- }
-
- /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */
- arch_cpu_init();
- pxa2xx_dram_init();
- onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR,
- CONFIG_SPL_ONENAND_LOAD_SIZE,
- (void *)CONFIG_SYS_TEXT_BASE);
- asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE));
-
- for (;;)
- ;
-}
-
-void __attribute__((noreturn)) hang(void)
-{
- for (;;)
- ;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = CONFIG_SPL_TEXT_BASE;
- .text.0 :
- {
- *(.vectors)
- arch/arm/cpu/pxa/start.o (.text*)
- arch/arm/lib/built-in.o (.text*)
- board/vpac270/built-in.o (.text*)
- drivers/built-in.o (.text*)
- }
-
-
- /* Start of the rest of the SPL */
- . = CONFIG_SPL_TEXT_BASE + 0x800;
-
- .text.1 :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- . = ALIGN(0x800);
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
+++ /dev/null
-/*
- * Voipac PXA270 Support
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
-#include <asm/arch/pxa.h>
-#include <netdev.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <usb.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
-
- /* Arch number of vpac270 */
- gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int dram_init(void)
-{
-#ifndef CONFIG_ONENAND
- pxa2xx_dram_init();
-#endif
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-#ifdef CONFIG_RAM_256M
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_USB
-int board_usb_init(int index, enum usb_init_type init)
-{
- writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
- UHCHR);
-
- writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
-
- while (readl(UHCHR) & UHCHR_FSBIR)
- ;
-
- writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
- writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
-
- /* Clear any OTG Pin Hold */
- if (readl(PSSR) & PSSR_OTGPH)
- writel(readl(PSSR) | PSSR_OTGPH, PSSR);
-
- writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
- writel(readl(UHCRHDA) | 0x100, UHCRHDA);
-
- /* Set port power control mask bits, only 3 ports. */
- writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
-
- /* enable port 2 */
- writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
- UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- return 0;
-}
-
-void usb_board_stop(void)
-{
- writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
- udelay(11);
- writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
-
- writel(readl(UHCCOMS) | 1, UHCCOMS);
- udelay(10);
-
- writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
-
- return;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
- return dm9000_initialize(bis);
-}
-#endif
config SYS_BOARD
default "wandboard"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "wandboard"
config SYS_BOARD
default "warp"
-config SYS_SOC
- default "mx6"
-
config SYS_CONFIG_NAME
default "warp"
+++ /dev/null
-if TARGET_XAENIAX
-
-config SYS_BOARD
- default "xaeniax"
-
-config SYS_CONFIG_NAME
- default "xaeniax"
-
-endif
+++ /dev/null
-XAENIAX BOARD
-#M: -
-S: Maintained
-F: board/xaeniax/
-F: include/configs/xaeniax.h
-F: configs/xaeniax_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := xaeniax.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#define SWAP(x) __swab16(x)
-#else
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#define SWAP(x) __swab32(x)
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info);
-static int write_data (flash_info_t *info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- switch (i) {
- case 0:
- flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
- break;
- case 1:
- flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
- flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
- break;
- default:
- panic ("configured too many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
- }
-
- /* Protect monitor and environment sectors
- */
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE,
- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0] );
-
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW *addr, flash_info_t *info)
-{
- volatile FPW value;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x5555] = (FPW) 0x00AA00AA;
- addr[0x2AAA] = (FPW) 0x00550055;
- addr[0x5555] = (FPW) 0x00900090;
-
- mb ();
- value = addr[0];
-
- switch (value) {
-
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- mb ();
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x02000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int prot, sect;
- ulong type, start;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
- }
-
- *addr = 0x00500050; /* clear status register cmd. */
- *addr = 0x00FF00FF; /* resest to read mode */
-
- printf (" done\n");
- }
- }
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#else
- wp = (addr & ~3);
- port_width = 4;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, SWAP (data))) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t *info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- disable_interrupts();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0);
-
- /* wait while polling the status register */
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of xaeniax */
- gd->bd->bi_arch_number = 585;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-if TARGET_ZIPITZ2
-
-config SYS_BOARD
- default "zipitz2"
-
-config SYS_CONFIG_NAME
- default "zipitz2"
-
-endif
+++ /dev/null
-ZIPITZ2 BOARD
-M: Marek Vasut <marek.vasut@gmail.com>
-S: Maintained
-F: board/zipitz2/
-F: include/configs/zipitz2.h
-F: configs/zipitz2_defconfig
+++ /dev/null
-#
-# Copyright (C) 2009
-# Marek Vasut <marek.vasut@gmail.com>
-#
-# Heavily based on pxa255_idp platform
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := zipitz2.o
+++ /dev/null
-/*
- * Copyright (C) 2009
- * Marek Vasut <marek.vasut@gmail.com>
- *
- * Heavily based on pxa255_idp platform
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa.h>
-#include <asm/arch/regs-mmc.h>
-#include <spi.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_SPI
-void lcd_start(void);
-#else
-inline void lcd_start(void) {};
-#endif
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- /* We have RAM, disable cache */
- dcache_disable();
- icache_disable();
-
- /* arch number of Z2 */
- gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0xa0000100;
-
- /* Enable LCD */
- lcd_start();
-
- return 0;
-}
-
-int dram_init(void)
-{
- pxa2xx_dram_init();
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bis)
-{
- pxa_mmc_register(0);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_CMD_SPI
-
-struct {
- unsigned char reg;
- unsigned short data;
- unsigned char mdelay;
-} lcd_data[] = {
- { 0x07, 0x0000, 0 },
- { 0x13, 0x0000, 10 },
- { 0x11, 0x3004, 0 },
- { 0x14, 0x200F, 0 },
- { 0x10, 0x1a20, 0 },
- { 0x13, 0x0040, 50 },
- { 0x13, 0x0060, 0 },
- { 0x13, 0x0070, 200 },
- { 0x01, 0x0127, 0 },
- { 0x02, 0x0700, 0 },
- { 0x03, 0x1030, 0 },
- { 0x08, 0x0208, 0 },
- { 0x0B, 0x0620, 0 },
- { 0x0C, 0x0110, 0 },
- { 0x30, 0x0120, 0 },
- { 0x31, 0x0127, 0 },
- { 0x32, 0x0000, 0 },
- { 0x33, 0x0503, 0 },
- { 0x34, 0x0727, 0 },
- { 0x35, 0x0124, 0 },
- { 0x36, 0x0706, 0 },
- { 0x37, 0x0701, 0 },
- { 0x38, 0x0F00, 0 },
- { 0x39, 0x0F00, 0 },
- { 0x40, 0x0000, 0 },
- { 0x41, 0x0000, 0 },
- { 0x42, 0x013f, 0 },
- { 0x43, 0x0000, 0 },
- { 0x44, 0x013f, 0 },
- { 0x45, 0x0000, 0 },
- { 0x46, 0xef00, 0 },
- { 0x47, 0x013f, 0 },
- { 0x48, 0x0000, 0 },
- { 0x07, 0x0015, 30 },
- { 0x07, 0x0017, 0 },
- { 0x20, 0x0000, 0 },
- { 0x21, 0x0000, 0 },
- { 0x22, 0x0000, 0 },
-};
-
-void zipitz2_spi_sda(int set)
-{
- /* GPIO 13 */
- if (set)
- writel((1 << 13), GPSR0);
- else
- writel((1 << 13), GPCR0);
-}
-
-void zipitz2_spi_scl(int set)
-{
- /* GPIO 22 */
- if (set)
- writel((1 << 22), GPCR0);
- else
- writel((1 << 22), GPSR0);
-}
-
-unsigned char zipitz2_spi_read(void)
-{
- /* GPIO 40 */
- return !!(readl(GPLR1) & (1 << 8));
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- /* Always valid */
- return 1;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- /* GPIO 88 low */
- writel((1 << 24), GPCR2);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- /* GPIO 88 high */
- writel((1 << 24), GPSR2);
-
-}
-
-void lcd_start(void)
-{
- int i;
- unsigned char reg[3] = { 0x74, 0x00, 0 };
- unsigned char data[3] = { 0x76, 0, 0 };
- unsigned char dummy[3] = { 0, 0, 0 };
-
- /* PWM2 AF */
- writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
- /* Enable clock to all PWM */
- writel(readl(CKEN) | 0x3, CKEN);
- /* Configure PWM2 */
- writel(0x4f, PWM_CTRL2);
- writel(0x2ff, PWM_PWDUTY2);
- writel(792, PWM_PERVAL2);
-
- /* Toggle the reset pin to reset the LCD */
- writel((1 << 19), GPSR0);
- udelay(100000);
- writel((1 << 19), GPCR0);
- udelay(20000);
- writel((1 << 19), GPSR0);
- udelay(20000);
-
- /* Program the LCD init sequence */
- for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
- reg[0] = 0x74;
- reg[1] = 0x0;
- reg[2] = lcd_data[i].reg;
- spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
- data[0] = 0x76;
- data[1] = lcd_data[i].data >> 8;
- data[2] = lcd_data[i].data & 0xff;
- spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (lcd_data[i].mdelay)
- udelay(lcd_data[i].mdelay * 1000);
- }
-
- writel((1 << 11), GPSR0);
-}
-#endif
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
+obj-$(CONFIG_CMD_ETHSW) += cmd_ethsw.o
# Power
obj-$(CONFIG_CMD_PMIC) += cmd_pmic.o
break;
}
#endif /* CONFIG_LZO */
+#ifdef CONFIG_LZ4
+ case IH_COMP_LZ4: {
+ size_t size = unc_len;
+
+ ret = ulz4fn(image_buf, image_len, load_buf, &size);
+ image_len = size;
+ break;
+ }
+#endif /* CONFIG_LZ4 */
default:
printf("Unimplemented compression type %d\n", comp);
return BOOTM_ERR_UNIMPLEMENTED;
#ifdef CONFIG_NETCONSOLE
/* Stop the ethernet stack if NetConsole could have left it up */
eth_halt();
+# ifndef CONFIG_DM_ETH
eth_unregister(eth_get_dev());
+# endif
#endif
#if defined(CONFIG_CMD_USB)
void cli_simple_loop(void)
{
- static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
+ static char lastcommand[CONFIG_SYS_CBSIZE + 1] = { 0, };
int len;
int flag;
parse_bank(bank);
}
-static void load_image(const char * const name, const ulong address)
+static int load_image(const char * const name, const ulong address)
{
struct afs_image *afi = NULL;
int i;
}
if (!afi) {
printf("image \"%s\" not found in flash\n", name);
- return;
+ return CMD_RET_FAILURE;
}
for (i = 0; i < afi->region_count; i++) {
to = afi->regions[i].load_address;
} else {
printf("no valid load address\n");
- return;
+ return CMD_RET_FAILURE;
}
memcpy((void *)to, (void *)from, afi->regions[i].size);
to,
afi->regions[i].size);
}
+ return CMD_RET_SUCCESS;
}
static void print_images(void)
}
}
+static int exists(const char * const name)
+{
+ int i;
+
+ parse_flash();
+ for (i = 0; i < num_afs_images; i++) {
+ struct afs_image *afi = &afs_images[i];
+
+ if (strcmp(afi->name, name) == 0)
+ return CMD_RET_SUCCESS;
+ }
+ return CMD_RET_FAILURE;
+}
+
static int do_afs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ int ret = CMD_RET_SUCCESS;
+
if (argc == 1) {
print_images();
+ } else if (argc == 3 && !strcmp(argv[1], "exists")) {
+ ret = exists(argv[2]);
} else if (argc == 3 && !strcmp(argv[1], "load")) {
- load_image(argv[2], 0x0);
+ ret = load_image(argv[2], 0x0);
} else if (argc == 4 && !strcmp(argv[1], "load")) {
ulong load_addr;
load_addr = simple_strtoul(argv[3], NULL, 16);
- load_image(argv[2], load_addr);
+ ret = load_image(argv[2], load_addr);
} else {
return CMD_RET_USAGE;
}
- return 0;
+ return ret;
}
U_BOOT_CMD(afs, 4, 0, do_afs, "show AFS partitions",
"no arguments\n"
" - list images in flash\n"
+ "exists <image>\n"
+ " - returns 1 if an image exists, else 0\n"
"load <image>\n"
" - load an image to the location indicated in the header\n"
"load <image> 0x<address>\n"
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Ethernet Switch commands
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <env_flags.h>
+#include <ethsw.h>
+
+static const char *ethsw_name;
+
+#define ETHSW_PORT_STATS_HELP "ethsw [port <port_no>] statistics " \
+"{ [help] | [clear] } - show an l2 switch port's statistics"
+
+static int ethsw_port_stats_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_PORT_STATS_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_LEARN_HELP "ethsw [port <port_no>] learning " \
+"{ [help] | show | auto | disable } " \
+"- enable/disable/show learning configuration on a port"
+
+static int ethsw_learn_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_LEARN_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_FDB_HELP "ethsw [port <port_no>] [vlan <vid>] fdb " \
+"{ [help] | show | flush | { add | del } <mac> } " \
+"- Add/delete a mac entry in FDB; use show to see FDB entries; " \
+"if vlan <vid> is missing, VID 1 will be used"
+
+static int ethsw_fdb_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_FDB_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_PVID_HELP "ethsw [port <port_no>] " \
+"pvid { [help] | show | <pvid> } " \
+"- set/show PVID (ingress and egress VLAN tagging) for a port"
+
+static int ethsw_pvid_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_PVID_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_VLAN_HELP "ethsw [port <port_no>] vlan " \
+"{ [help] | show | add <vid> | del <vid> } " \
+"- add a VLAN to a port (VLAN members)"
+
+static int ethsw_vlan_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_VLAN_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_PORT_UNTAG_HELP "ethsw [port <port_no>] untagged " \
+"{ [help] | show | all | none | pvid } " \
+" - set egress tagging mod for a port"
+
+static int ethsw_port_untag_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_PORT_UNTAG_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_EGR_VLAN_TAG_HELP "ethsw [port <port_no>] egress tag " \
+"{ [help] | show | pvid | classified } " \
+"- Configure VID source for egress tag. " \
+"Tag's VID could be the frame's classified VID or the PVID of the port"
+
+static int ethsw_egr_tag_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_EGR_VLAN_TAG_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_VLAN_FDB_HELP "ethsw vlan fdb " \
+"{ [help] | show | shared | private } " \
+"- make VLAN learning shared or private"
+
+static int ethsw_vlan_learn_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_VLAN_FDB_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+#define ETHSW_PORT_INGR_FLTR_HELP "ethsw [port <port_no>] ingress filtering" \
+" { [help] | show | enable | disable } " \
+"- enable/disable VLAN ingress filtering on port"
+
+static int ethsw_ingr_fltr_help_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ printf(ETHSW_PORT_INGR_FLTR_HELP"\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+static struct keywords_to_function {
+ enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS];
+ int cmd_func_offset;
+ int (*keyword_function)(struct ethsw_command_def *parsed_cmd);
+} ethsw_cmd_def[] = {
+ {
+ .cmd_keyword = {
+ ethsw_id_enable,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_enable),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_disable,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_disable),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_statistics,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_port_stats_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_statistics,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_stats),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_statistics,
+ ethsw_id_clear,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_stats_clear),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_learning,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_learn_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_learning,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_learn_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_learning,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_learn_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_learning,
+ ethsw_id_auto,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_learn),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_learning,
+ ethsw_id_disable,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_learn),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_fdb,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_fdb_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_fdb,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_fdb_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_fdb,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ fdb_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_fdb,
+ ethsw_id_flush,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ fdb_flush),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_fdb,
+ ethsw_id_add,
+ ethsw_id_add_del_mac,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ fdb_entry_add),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_fdb,
+ ethsw_id_del,
+ ethsw_id_add_del_mac,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ fdb_entry_del),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_pvid,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_pvid_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_pvid,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_pvid_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_pvid,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ pvid_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_pvid,
+ ethsw_id_pvid_no,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ pvid_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_vlan_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_vlan_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ vlan_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_add,
+ ethsw_id_add_del_no,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ vlan_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_del,
+ ethsw_id_add_del_no,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ vlan_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_untagged,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_port_untag_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_untagged,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_port_untag_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_untagged,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_untag_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_untagged,
+ ethsw_id_all,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_untag_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_untagged,
+ ethsw_id_none,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_untag_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_untagged,
+ ethsw_id_pvid,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_untag_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_egress,
+ ethsw_id_tag,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_egr_tag_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_egress,
+ ethsw_id_tag,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_egr_tag_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_egress,
+ ethsw_id_tag,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_egr_vlan_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_egress,
+ ethsw_id_tag,
+ ethsw_id_pvid,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_egr_vlan_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_egress,
+ ethsw_id_tag,
+ ethsw_id_classified,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_egr_vlan_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_fdb,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_vlan_learn_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_fdb,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_vlan_learn_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_fdb,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ vlan_learn_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_fdb,
+ ethsw_id_shared,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ vlan_learn_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_fdb,
+ ethsw_id_private,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ vlan_learn_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_ingress,
+ ethsw_id_filtering,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_ingr_fltr_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_ingress,
+ ethsw_id_filtering,
+ ethsw_id_help,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = -1,
+ .keyword_function = ðsw_ingr_fltr_help_key_func,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_ingress,
+ ethsw_id_filtering,
+ ethsw_id_show,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_ingr_filt_show),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_ingress,
+ ethsw_id_filtering,
+ ethsw_id_enable,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_ingr_filt_set),
+ .keyword_function = NULL,
+ }, {
+ .cmd_keyword = {
+ ethsw_id_ingress,
+ ethsw_id_filtering,
+ ethsw_id_disable,
+ ethsw_id_key_end,
+ },
+ .cmd_func_offset = offsetof(struct ethsw_command_func,
+ port_ingr_filt_set),
+ .keyword_function = NULL,
+ },
+};
+
+struct keywords_optional {
+ int cmd_keyword[ETHSW_MAX_CMD_PARAMS];
+} cmd_opt_def[] = {
+ {
+ .cmd_keyword = {
+ ethsw_id_port,
+ ethsw_id_port_no,
+ ethsw_id_key_end,
+ },
+ }, {
+ .cmd_keyword = {
+ ethsw_id_vlan,
+ ethsw_id_vlan_no,
+ ethsw_id_key_end,
+ },
+ }, {
+ .cmd_keyword = {
+ ethsw_id_port,
+ ethsw_id_port_no,
+ ethsw_id_vlan,
+ ethsw_id_vlan_no,
+ ethsw_id_key_end,
+ },
+ },
+};
+
+static int keyword_match_gen(enum ethsw_keyword_id key_id, int argc, char
+ *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd);
+static int keyword_match_port(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd);
+static int keyword_match_vlan(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd);
+static int keyword_match_pvid(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd);
+static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd);
+
+/*
+ * Define properties for each keyword;
+ * keep the order synced with enum ethsw_keyword_id
+ */
+struct keyword_def {
+ const char *keyword_name;
+ int (*match)(enum ethsw_keyword_id key_id, int argc, char *const argv[],
+ int *argc_nr, struct ethsw_command_def *parsed_cmd);
+} keyword[] = {
+ {
+ .keyword_name = "help",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "show",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "port",
+ .match = &keyword_match_port
+ }, {
+ .keyword_name = "enable",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "disable",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "statistics",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "clear",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "learning",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "auto",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "vlan",
+ .match = &keyword_match_vlan,
+ }, {
+ .keyword_name = "fdb",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "add",
+ .match = &keyword_match_mac_addr,
+ }, {
+ .keyword_name = "del",
+ .match = &keyword_match_mac_addr,
+ }, {
+ .keyword_name = "flush",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "pvid",
+ .match = &keyword_match_pvid,
+ }, {
+ .keyword_name = "untagged",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "all",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "none",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "egress",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "tag",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "classified",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "shared",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "private",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "ingress",
+ .match = &keyword_match_gen,
+ }, {
+ .keyword_name = "filtering",
+ .match = &keyword_match_gen,
+ },
+};
+
+/*
+ * Function used by an Ethernet Switch driver to set the functions
+ * that must be called by the parser when an ethsw command is given
+ */
+int ethsw_define_functions(const struct ethsw_command_func *cmd_func)
+{
+ int i;
+ void **aux_p;
+ int (*cmd_func_aux)(struct ethsw_command_def *);
+
+ if (!cmd_func->ethsw_name)
+ return -EINVAL;
+
+ ethsw_name = cmd_func->ethsw_name;
+
+ for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) {
+ /*
+ * get the pointer to the function send by the Ethernet Switch
+ * driver that corresponds to the proper ethsw command
+ */
+ if (ethsw_cmd_def[i].keyword_function)
+ continue;
+
+ aux_p = (void *)cmd_func + ethsw_cmd_def[i].cmd_func_offset;
+
+ cmd_func_aux = (int (*)(struct ethsw_command_def *)) *aux_p;
+ ethsw_cmd_def[i].keyword_function = cmd_func_aux;
+ }
+
+ return 0;
+}
+
+/* Generic function used to match a keyword only by a string */
+static int keyword_match_gen(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd)
+{
+ if (strcmp(argv[*argc_nr], keyword[key_id].keyword_name) == 0) {
+ parsed_cmd->cmd_to_keywords[*argc_nr] = key_id;
+
+ return 1;
+ }
+ return 0;
+}
+
+/* Function used to match the command's port */
+static int keyword_match_port(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd)
+{
+ unsigned long val;
+
+ if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd))
+ return 0;
+
+ if (*argc_nr + 1 >= argc)
+ return 0;
+
+ if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) {
+ parsed_cmd->port = val;
+ (*argc_nr)++;
+ parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_port_no;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Function used to match the command's vlan */
+static int keyword_match_vlan(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd)
+{
+ unsigned long val;
+ int aux;
+
+ if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd))
+ return 0;
+
+ if (*argc_nr + 1 >= argc)
+ return 0;
+
+ if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) {
+ parsed_cmd->vid = val;
+ (*argc_nr)++;
+ parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_vlan_no;
+ return 1;
+ }
+
+ aux = *argc_nr + 1;
+
+ if (keyword_match_gen(ethsw_id_add, argc, argv, &aux, parsed_cmd))
+ parsed_cmd->cmd_to_keywords[*argc_nr + 1] = ethsw_id_add;
+ else if (keyword_match_gen(ethsw_id_del, argc, argv, &aux, parsed_cmd))
+ parsed_cmd->cmd_to_keywords[*argc_nr + 1] = ethsw_id_del;
+ else
+ return 0;
+
+ if (*argc_nr + 2 >= argc)
+ return 0;
+
+ if (strict_strtoul(argv[*argc_nr + 2], 10, &val) != -EINVAL) {
+ parsed_cmd->vid = val;
+ (*argc_nr) += 2;
+ parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_add_del_no;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Function used to match the command's pvid */
+static int keyword_match_pvid(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd)
+{
+ unsigned long val;
+
+ if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd))
+ return 0;
+
+ if (*argc_nr + 1 >= argc)
+ return 1;
+
+ if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) {
+ parsed_cmd->vid = val;
+ (*argc_nr)++;
+ parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_pvid_no;
+ }
+
+ return 1;
+}
+
+/* Function used to match the command's MAC address */
+static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc,
+ char *const argv[], int *argc_nr,
+ struct ethsw_command_def *parsed_cmd)
+{
+ if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd))
+ return 0;
+
+ if ((*argc_nr + 1 >= argc) ||
+ !is_broadcast_ethaddr(parsed_cmd->ethaddr))
+ return 1;
+
+ if (eth_validate_ethaddr_str(argv[*argc_nr + 1])) {
+ printf("Invalid MAC address: %s\n", argv[*argc_nr + 1]);
+ return 0;
+ }
+
+ eth_parse_enetaddr(argv[*argc_nr + 1], parsed_cmd->ethaddr);
+
+ if (is_broadcast_ethaddr(parsed_cmd->ethaddr)) {
+ memset(parsed_cmd->ethaddr, 0xFF, sizeof(parsed_cmd->ethaddr));
+ return 0;
+ }
+
+ parsed_cmd->cmd_to_keywords[*argc_nr + 1] = ethsw_id_add_del_mac;
+
+ return 1;
+}
+
+/* Finds optional keywords and modifies *argc_va to skip them */
+static void cmd_keywords_opt_check(const struct ethsw_command_def *parsed_cmd,
+ int *argc_val)
+{
+ int i;
+ int keyw_opt_matched;
+ int argc_val_max;
+ int const *cmd_keyw_p;
+ int const *cmd_keyw_opt_p;
+
+ /* remember the best match */
+ argc_val_max = *argc_val;
+
+ /*
+ * check if our command's optional keywords match the optional
+ * keywords of an available command
+ */
+ for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) {
+ keyw_opt_matched = 0;
+ cmd_keyw_p = &parsed_cmd->cmd_to_keywords[keyw_opt_matched];
+ cmd_keyw_opt_p = &cmd_opt_def[i].cmd_keyword[keyw_opt_matched];
+
+ /*
+ * increase the number of keywords that
+ * matched with a command
+ */
+ while (keyw_opt_matched + *argc_val <
+ parsed_cmd->cmd_keywords_nr &&
+ *cmd_keyw_opt_p != ethsw_id_key_end &&
+ *(cmd_keyw_p + *argc_val) == *cmd_keyw_opt_p) {
+ keyw_opt_matched++;
+ cmd_keyw_p++;
+ cmd_keyw_opt_p++;
+ }
+
+ /*
+ * if all our optional command's keywords perfectly match an
+ * optional pattern, then we can move to the next defined
+ * keywords in our command; remember the one that matched the
+ * greatest number of keywords
+ */
+ if (keyw_opt_matched + *argc_val <=
+ parsed_cmd->cmd_keywords_nr &&
+ *cmd_keyw_opt_p == ethsw_id_key_end &&
+ *argc_val + keyw_opt_matched > argc_val_max)
+ argc_val_max = *argc_val + keyw_opt_matched;
+ }
+
+ *argc_val = argc_val_max;
+}
+
+/*
+ * Finds the function to call based on keywords and
+ * modifies *argc_va to skip them
+ */
+static void cmd_keywords_check(struct ethsw_command_def *parsed_cmd,
+ int *argc_val)
+{
+ int i;
+ int keyw_matched;
+ int *cmd_keyw_p;
+ int *cmd_keyw_def_p;
+
+ /*
+ * check if our command's keywords match the
+ * keywords of an available command
+ */
+ for (i = 0; i < ARRAY_SIZE(ethsw_cmd_def); i++) {
+ keyw_matched = 0;
+ cmd_keyw_p = &parsed_cmd->cmd_to_keywords[keyw_matched];
+ cmd_keyw_def_p = ðsw_cmd_def[i].cmd_keyword[keyw_matched];
+
+ /*
+ * increase the number of keywords that
+ * matched with a command
+ */
+ while (keyw_matched + *argc_val < parsed_cmd->cmd_keywords_nr &&
+ *cmd_keyw_def_p != ethsw_id_key_end &&
+ *(cmd_keyw_p + *argc_val) == *cmd_keyw_def_p) {
+ keyw_matched++;
+ cmd_keyw_p++;
+ cmd_keyw_def_p++;
+ }
+
+ /*
+ * if all our command's keywords perfectly match an
+ * available command, then we get the function we need to call
+ * to configure the Ethernet Switch
+ */
+ if (keyw_matched && keyw_matched + *argc_val ==
+ parsed_cmd->cmd_keywords_nr &&
+ *cmd_keyw_def_p == ethsw_id_key_end) {
+ *argc_val += keyw_matched;
+ parsed_cmd->cmd_function =
+ ethsw_cmd_def[i].keyword_function;
+ return;
+ }
+ }
+}
+
+/* find all the keywords in the command */
+static int keywords_find(int argc, char * const argv[],
+ struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ int j;
+ int argc_val;
+ int rc = CMD_RET_SUCCESS;
+
+ for (i = 1; i < argc; i++) {
+ for (j = 0; j < ethsw_id_count; j++) {
+ if (keyword[j].match(j, argc, argv, &i, parsed_cmd))
+ break;
+ }
+ }
+
+ /* if there is no keyword match for a word, the command is invalid */
+ for (i = 1; i < argc; i++)
+ if (parsed_cmd->cmd_to_keywords[i] == ethsw_id_key_end)
+ rc = CMD_RET_USAGE;
+
+ parsed_cmd->cmd_keywords_nr = argc;
+ argc_val = 1;
+
+ /* get optional parameters first */
+ cmd_keywords_opt_check(parsed_cmd, &argc_val);
+
+ if (argc_val == parsed_cmd->cmd_keywords_nr)
+ return CMD_RET_USAGE;
+
+ /*
+ * check the keywords and if a match is found,
+ * get the function to call
+ */
+ cmd_keywords_check(parsed_cmd, &argc_val);
+
+ /* error if not all commands' parameters were matched */
+ if (argc_val == parsed_cmd->cmd_keywords_nr) {
+ if (!parsed_cmd->cmd_function) {
+ printf("Command not available for: %s\n", ethsw_name);
+ rc = CMD_RET_FAILURE;
+ }
+ } else {
+ rc = CMD_RET_USAGE;
+ }
+
+ return rc;
+}
+
+static void command_def_init(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+
+ for (i = 0; i < ETHSW_MAX_CMD_PARAMS; i++)
+ parsed_cmd->cmd_to_keywords[i] = ethsw_id_key_end;
+
+ parsed_cmd->port = ETHSW_CMD_PORT_ALL;
+ parsed_cmd->vid = ETHSW_CMD_VLAN_ALL;
+ parsed_cmd->cmd_function = NULL;
+
+ /* We initialize the MAC address with the Broadcast address */
+ memset(parsed_cmd->ethaddr, 0xff, sizeof(parsed_cmd->ethaddr));
+}
+
+/* function to interpret commands starting with "ethsw " */
+static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct ethsw_command_def parsed_cmd;
+ int rc = CMD_RET_SUCCESS;
+
+ if (argc == 1 || argc >= ETHSW_MAX_CMD_PARAMS)
+ return CMD_RET_USAGE;
+
+ command_def_init(&parsed_cmd);
+
+ rc = keywords_find(argc, argv, &parsed_cmd);
+
+ if (rc == CMD_RET_SUCCESS)
+ rc = parsed_cmd.cmd_function(&parsed_cmd);
+
+ return rc;
+}
+
+#define ETHSW_PORT_CONF_HELP "[port <port_no>] { enable | disable | show } " \
+"- enable/disable a port; show shows a port's configuration"
+
+U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw,
+ "Ethernet l2 switch commands",
+ ETHSW_PORT_CONF_HELP"\n"
+ ETHSW_PORT_STATS_HELP"\n"
+ ETHSW_LEARN_HELP"\n"
+ ETHSW_FDB_HELP"\n"
+ ETHSW_PVID_HELP"\n"
+ ETHSW_VLAN_HELP"\n"
+ ETHSW_PORT_UNTAG_HELP"\n"
+ ETHSW_EGR_VLAN_TAG_HELP"\n"
+ ETHSW_VLAN_FDB_HELP"\n"
+ ETHSW_PORT_INGR_FLTR_HELP"\n"
+);
#include <common.h>
#include <command.h>
#include <exports.h>
-
+#include <memalign.h>
#include <nand.h>
#include <onenand_uboot.h>
#include <linux/mtd/mtd.h>
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <memalign.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <part.h>
void env_relocate_spec(void)
{
- char buf[CONFIG_ENV_SIZE];
+ char buf_env[CONFIG_ENV_SIZE];
unsigned int off = CONFIG_ENV_OFFSET;
#ifdef CONFIG_ENV_OFFSET_REDUND
- if (gd->env_valid == 2)
- off = CONFIG_ENV_OFFSET_REDUND;
-#endif
- eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- off, (uchar *)buf, CONFIG_ENV_SIZE);
-
- env_import(buf, 1);
-}
-
-int saveenv(void)
-{
- env_t env_new;
- int rc;
- unsigned int off = CONFIG_ENV_OFFSET;
-#ifdef CONFIG_ENV_OFFSET_REDUND
- unsigned int off_red = CONFIG_ENV_OFFSET_REDUND;
- char flag_obsolete = OBSOLETE_FLAG;
-#endif
-
- BUG_ON(env_ptr != NULL);
-
- rc = env_export(&env_new);
- if (rc)
- return rc;
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- if (gd->env_valid == 1) {
- off = CONFIG_ENV_OFFSET_REDUND;
- off_red = CONFIG_ENV_OFFSET;
- }
-
- env_new.flags = ACTIVE_FLAG;
-#endif
-
- rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
- off, (uchar *)&env_new, CONFIG_ENV_SIZE);
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- if (rc == 0) {
- eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
- off_red + offsetof(env_t, flags),
- (uchar *)&flag_obsolete, 1);
-
- if (gd->env_valid == 1)
- gd->env_valid = 2;
- else
- gd->env_valid = 1;
- }
-#endif
- return rc;
-}
-
-/*
- * Initialize Environment use
- *
- * We are still running from ROM, so data use is limited.
- * Use a (moderately small) buffer on the stack
- */
-#ifdef CONFIG_ENV_OFFSET_REDUND
-int env_init(void)
-{
-#ifdef ENV_IS_EMBEDDED
ulong len, crc[2], crc_tmp;
- unsigned int off, off_env[2];
- uchar buf[64], flags[2];
+ unsigned int off_env[2];
+ uchar rdbuf[64], flags[2];
int i, crc_ok[2] = {0, 0};
eeprom_init(); /* prepare for EEPROM read/write */
len = ENV_SIZE;
off = off_env[i] + offsetof(env_t, data);
while (len > 0) {
- int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+ int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len;
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off,
- buf, n);
+ rdbuf, n);
- crc_tmp = crc32(crc_tmp, buf, n);
+ crc_tmp = crc32(crc_tmp, rdbuf, n);
len -= n;
off += n;
}
if (!crc_ok[0] && !crc_ok[1]) {
gd->env_addr = 0;
gd->env_valid = 0;
-
- return 0;
} else if (crc_ok[0] && !crc_ok[1]) {
gd->env_valid = 1;
} else if (!crc_ok[0] && crc_ok[1]) {
gd->env_addr = off_env[1] + offsetof(env_t, data);
else if (gd->env_valid == 1)
gd->env_addr = off_env[0] + offsetof(env_t, data);
-#else
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
-#endif
- return 0;
-}
-#else
-int env_init(void)
-{
-#ifdef ENV_IS_EMBEDDED
+
+#else /* CONFIG_ENV_OFFSET_REDUND */
ulong crc, len, new;
- unsigned off;
- uchar buf[64];
+ uchar rdbuf[64];
eeprom_init(); /* prepare for EEPROM read/write */
new = 0;
len = ENV_SIZE;
off = offsetof(env_t, data);
-
while (len > 0) {
- int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+ int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len;
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
- CONFIG_ENV_OFFSET + off, buf, n);
- new = crc32(new, buf, n);
+ CONFIG_ENV_OFFSET + off, rdbuf, n);
+ new = crc32(new, rdbuf, n);
len -= n;
off += n;
}
gd->env_addr = 0;
gd->env_valid = 0;
}
-#else
+#endif /* CONFIG_ENV_OFFSET_REDUND */
+
+ off = CONFIG_ENV_OFFSET;
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ if (gd->env_valid == 2)
+ off = CONFIG_ENV_OFFSET_REDUND;
+#endif
+
+ eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
+ off, (uchar *)buf_env, CONFIG_ENV_SIZE);
+
+ env_import(buf_env, 1);
+}
+
+int saveenv(void)
+{
+ env_t env_new;
+ int rc;
+ unsigned int off = CONFIG_ENV_OFFSET;
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ unsigned int off_red = CONFIG_ENV_OFFSET_REDUND;
+ char flag_obsolete = OBSOLETE_FLAG;
+#endif
+
+ BUG_ON(env_ptr != NULL);
+
+ rc = env_export(&env_new);
+ if (rc)
+ return rc;
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ if (gd->env_valid == 1) {
+ off = CONFIG_ENV_OFFSET_REDUND;
+ off_red = CONFIG_ENV_OFFSET;
+ }
+
+ env_new.flags = ACTIVE_FLAG;
+#endif
+
+ rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
+ off, (uchar *)&env_new, CONFIG_ENV_SIZE);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ if (rc == 0) {
+ eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR,
+ off_red + offsetof(env_t, flags),
+ (uchar *)&flag_obsolete, 1);
+
+ if (gd->env_valid == 1)
+ gd->env_valid = 2;
+ else
+ gd->env_valid = 1;
+ }
+#endif
+ return rc;
+}
+
+/*
+ * Initialize Environment use
+ *
+ * We are still running from ROM, so data use is limited.
+ * Use a (moderately small) buffer on the stack
+ */
+int env_init(void)
+{
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 1;
-#endif
return 0;
}
-#endif
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
+#include <memalign.h>
#include <search.h>
#include <errno.h>
#include <fat.h>
*end = value;
}
+#ifdef CONFIG_CMD_NET
+int eth_validate_ethaddr_str(const char *addr)
+{
+ const char *end;
+ const char *cur;
+ int i;
+
+ cur = addr;
+ for (i = 0; i < 6; i++) {
+ skip_num(1, cur, &end, 2);
+ if (cur == end)
+ return -1;
+ if (cur + 2 == end && is_hex_prefix(cur))
+ return -1;
+ if (i != 5 && *end != ':')
+ return -1;
+ if (i == 5 && *end != '\0')
+ return -1;
+ cur = end + 1;
+ }
+
+ return 0;
+}
+#endif
+
/*
* Based on the declared type enum, validate that the value string complies
* with that format
}
break;
case env_flags_vartype_macaddr:
- cur = value;
- for (i = 0; i < 6; i++) {
- skip_num(1, cur, &end, 2);
- if (cur == end)
- return -1;
- if (cur + 2 == end && is_hex_prefix(cur))
- return -1;
- if (i != 5 && *end != ':')
- return -1;
- if (i == 5 && *end != '\0')
- return -1;
- cur = end + 1;
- }
+ if (eth_validate_ethaddr_str(value))
+ return -1;
break;
#endif
case env_flags_vartype_end:
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
+#include <memalign.h>
#include <mmc.h>
#include <search.h>
#include <errno.h>
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
+#include <memalign.h>
#include <nand.h>
#include <search.h>
#include <errno.h>
#include <environment.h>
#include <errno.h>
#include <malloc.h>
+#include <memalign.h>
#include <search.h>
#include <ubi_uboot.h>
#undef crc32
int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
ulong *rd_data, ulong *rd_len)
{
- if (!hdr->ramdisk_size)
+ if (!hdr->ramdisk_size) {
+ *rd_data = *rd_len = 0;
return -1;
+ }
printf("RAM disk load addr 0x%08x size %u KiB\n",
hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024));
{ IH_COMP_GZIP, "gzip", "gzip compressed", },
{ IH_COMP_LZMA, "lzma", "lzma compressed", },
{ IH_COMP_LZO, "lzo", "lzo compressed", },
+ { IH_COMP_LZ4, "lz4", "lz4 compressed", },
{ -1, "", "", },
};
*rd_start = 0;
*rd_end = 0;
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ /*
+ * Look for an Android boot image.
+ */
+ buf = map_sysmem(images->os.start, 0);
+ if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
+ select = argv[0];
+#endif
+
if (argc >= 2)
select = argv[1];
void *ptr;
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
- new_ptr = addr + bytes;
+ new_ptr = addr + bytes - gd->malloc_base;
if (new_ptr > gd->malloc_limit)
return NULL;
ptr = map_sysmem(addr, bytes);
#include <common.h>
#include <command.h>
#include <dm.h>
+#include <memalign.h>
#include <asm/processor.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
#include <command.h>
#include <dm.h>
#include <errno.h>
+#include <memalign.h>
#include <asm/processor.h>
#include <asm/unaligned.h>
#include <linux/ctype.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <memalign.h>
#include <stdio_dev.h>
#include <asm/byteorder.h>
#include <errno.h>
#include <inttypes.h>
#include <mapmem.h>
+#include <memalign.h>
#include <asm/byteorder.h>
#include <asm/processor.h>
#include <dm/device-internal.h>
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
-CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SYS_CLK_FREQ=912000000
+CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
-CONFIG_GMAC_TX_DELAY=3
CONFIG_VIDEO_COMPOSITE=y
+CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
-CONFIG_GMAC_TX_DELAY=3
CONFIG_VIDEO_COMPOSITE=y
+CONFIG_GMAC_TX_DELAY=3
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_VIDEO_LCD_SPI_MOSI="PA2"
-CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
-CONFIG_DRAM_CLK=408
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_M68K=y
CONFIG_TARGET_M5208EVBE=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFE00000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M5272C3=y
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M5275EVB=y
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M5282EVB=y
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M53017EVB=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333"
+CONFIG_SYS_PROMPT="-> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="-> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
+# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
CONFIG_VIDEO_LCD_SSD2828_RESET="PA26"
CONFIG_VIDEO_LCD_SPI_CS="PH9"
CONFIG_VIDEO_LCD_SPI_SCLK="PH10"
CONFIG_VIDEO_LCD_SPI_MOSI="PH11"
CONFIG_VIDEO_LCD_SPI_MISO="PH12"
-CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
-CONFIG_VIDEO_COMPOSITE=y
CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_PPC=y
CONFIG_5xx=y
CONFIG_TARGET_PATI=y
+CONFIG_SYS_PROMPT="pati=> "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="pati=> "
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_UCP1020=y
+CONFIG_SYS_PROMPT="B$ "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="B$ "
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_VCMA9=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="VCMA9 # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_MMC0_CD_PIN="PB3"
+CONFIG_USB1_VBUS_PIN="PG12"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
CONFIG_PPC=y
CONFIG_MPC512X=y
CONFIG_TARGET_AC14XX=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="ac14xx> "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="NDS32 # "
+# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SH_SDHI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
CONFIG_DFU_TFTP=y
+CONFIG_SPI_FLASH=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_SPI_FLASH=y
CONFIG_RSA=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SL50=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_AM3517_CRANE=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="AM3517_CRANE # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="AM3517_CRANE # "
CONFIG_TARGET_AM3517_EVM=y
CONFIG_SPL=y
CONFIG_FIT=y
+CONFIG_SYS_PROMPT="AM3517_EVM # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="AM3517_EVM # "
CONFIG_M68K=y
CONFIG_TARGET_AMCORE=y
+CONFIG_SYS_PROMPT="amcore $ "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="amcore $ "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA30=y
CONFIG_TARGET_APALIS_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
+CONFIG_SYS_PROMPT="Apalis T30 # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Apalis T30 # "
CONFIG_ARM=y
CONFIG_TARGET_APF27=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="BIOS> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_SYS_PROMPT="BIOS> "
CONFIG_ARC=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_TARGET_ARCANGEL4=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
-CONFIG_DM_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARC=y
CONFIG_TARGET_ARCANGEL4=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
+CONFIG_SYS_PROMPT="arcangel4# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DM=y
-CONFIG_DM_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="arcangel4# "
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ARNDALE=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="ARNDALE # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_SOUND_WM8994=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_SYS_PROMPT="ARNDALE # "
CONFIG_M68K=y
CONFIG_TARGET_ASTRO_MCF5373L=y
+CONFIG_SYS_PROMPT="URMEL > "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="URMEL > "
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9263EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9M10G45EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9N12EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9RLEK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_TARGET_AT91SAM9X5EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AVR32=y
CONFIG_TARGET_ATNGW100=y
+CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AVR32=y
CONFIG_TARGET_ATNGW100MKII=y
+CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AVR32=y
CONFIG_TARGET_ATSTK1002=y
+CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_BALLOON3=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
-CONFIG_DM_PCI=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA30=y
CONFIG_TARGET_BEAVER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
+CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_MINOTAUR=y
+CONFIG_SYS_PROMPT="minotaur> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="minotaur> "
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF537_SRV1=y
+CONFIG_SYS_PROMPT="srv1> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="srv1> "
CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_ACVILON=y
+CONFIG_SYS_PROMPT="Acvilon> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
-CONFIG_SYS_PROMPT="Acvilon> "
CONFIG_BLACKFIN=y
CONFIG_TARGET_BR4=y
+CONFIG_SYS_PROMPT="br4>"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
-CONFIG_SYS_PROMPT="br4>"
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Cairo # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NET is not set
-CONFIG_SYS_PROMPT="Cairo # "
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
+CONFIG_SYS_PROMPT="Calimain > "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="\x0b"
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="Calimain > "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA30=y
CONFIG_TARGET_CARDHU=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
+CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
CONFIG_ARCH_MX6=y
CONFIG_TARGET_CGTQMX6EVAL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
+CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_RESET=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_SPL_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_BASE=0xff690000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SIMPLE=y
CONFIG_SPL_PINCTRL=y
-CONFIG_SPL_PINCTRL_SIMPLE=y
CONFIG_ROCKCHIP_PINCTRL=y
-CONFIG_ROCKCHIP_GPIO=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DM_MMC=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_X86=y
+CONFIG_SYS_MALLOC_F_LEN=0x1800
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
-CONFIG_DM_PCI=y
-CONFIG_SPI_FLASH=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
CONFIG_DM_TPM=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
-CONFIG_DM_PCI=y
-CONFIG_SPI_FLASH=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
CONFIG_DM_TPM=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
CONFIG_TARGET_CM_FX6=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+CONFIG_SYS_PROMPT="CM-FX6 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LOADB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
-CONFIG_SYS_PROMPT="CM-FX6 # "
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_ARM=y
CONFIG_TARGET_CM_T335=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="CM-T335 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CM-T335 # "
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T3517=y
+CONFIG_SYS_PROMPT="CM-T3517 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CM-T3517 # "
CONFIG_OMAP34XX=y
CONFIG_TARGET_CM_T35=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="CM-T3x # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CM-T3x # "
CONFIG_ARM=y
CONFIG_TARGET_CM_T43=y
+CONFIG_DM_GPIO=y
CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM=y
-CONFIG_DM_GPIO=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_CM_T54=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="CM-T54 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="CM-T54 # "
CONFIG_M68K=y
CONFIG_TARGET_COBRA5272=y
+CONFIG_SYS_PROMPT="COBRA > "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="COBRA > "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_COLIBRI_T20=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
+CONFIG_SYS_PROMPT="Colibri T20 # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Colibri T20 # "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA30=y
CONFIG_TARGET_COLIBRI_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
+CONFIG_SYS_PROMPT="Colibri T30 # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Colibri T30 # "
CONFIG_ARM=y
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_SYS_PROMPT="Colibri VFxx # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
-CONFIG_SYS_PROMPT="Colibri VFxx # "
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND"
+CONFIG_SYS_PROMPT="Colibri VFxx # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_DM=y
CONFIG_NAND_VF610_NFC=y
CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y
-CONFIG_SYS_PROMPT="Colibri VFxx # "
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
-CONFIG_DM_PCI=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
CONFIG_DM_TPM=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_TPM=y
CONFIG_TARGET_CORVUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,CPU9260_128M,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9260,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9260=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,CPU9G20_128M,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPU9260=y
-CONFIG_SYS_EXTRA_OPTIONS="CPU9G20,NANDBOOT"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="CPU9G20=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPUAT91=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="CPUAT91=> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_CPUAT91=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
-CONFIG_DM_PCI=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCH_GBE=y
-CONFIG_VIDEO_VESA=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_DM_RTC=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NET2BIG_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DA830EVM=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_TARGET_DA850EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
+CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA114=y
CONFIG_TARGET_DALMORE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
+CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM355EVM=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM355 EVM # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM355LEOPARD=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM355 LEOPARD # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM365EVM=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM36x EVM # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM6467EVM=y
-CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM6467EVM=y
-CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DM6467 EVM > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DVEVM=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SCHMOOGIE=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SFFSDR=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SONATA=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1100=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1500=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1550=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
CONFIG_TARGET_DBAU1X00=y
CONFIG_DBAU1550=y
CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_SYS_PROMPT="DbAu1xx0 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="DbAu1xx0 # "
CONFIG_ARM=y
CONFIG_TARGET_DEVKIT3250=y
+CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
-CONFIG_DM_GPIO=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_DIG297=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="DIG297# "
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DOCKSTAR=y
+CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="DockStar> "
CONFIG_ARM=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_DM_GPIO=y
CONFIG_ARM=y
CONFIG_TARGET_DRACO=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_OMAP44XX=y
CONFIG_TARGET_DUOVERO=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="duovero # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="duovero # "
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_TEGRA210=y
-CONFIG_TARGET_E2220_1170=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170"
+CONFIG_SYS_PROMPT="Tegra210 (E2220-1170) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_EA20=y
+CONFIG_SYS_PROMPT="ea20 > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="ea20 > "
CONFIG_M68K=y
CONFIG_TARGET_EB_CPU5282=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400"
+CONFIG_SYS_PROMPT="\nEB+CPU5282> "
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="\nEB+CPU5282> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_EB_CPUX9K2=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_EB_CPUX9K2=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_ECO5PK=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="ECO5-PK # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="ECO5-PK # "
CONFIG_ORION5X=y
CONFIG_TARGET_EDMINIV2=y
CONFIG_SPL=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="EDMiniV2> "
+# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_ENBW_CMC=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_AT91=y
CONFIG_TARGET_ETHERNUT5=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_RESET=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_BASE=0xff690000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
+CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_ROCKCHIP_PINCTRL=y
-CONFIG_ROCKCHIP_GPIO=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_ACT8846=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
-CONFIG_DM_MMC=y
-CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_ARM=y
CONFIG_TARGET_FLEA3=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="flea3 U-Boot > "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_4xx=y
CONFIG_TARGET_FX12MM=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o"
+CONFIG_SYS_PROMPT="FX12MM:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="FX12MM:/# "
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GOFLEXHOME=y
+CONFIG_SYS_PROMPT="GoFlexHome> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="GoFlexHome> "
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SH_SDHI=y
CONFIG_AVR32=y
CONFIG_TARGET_GRASSHOPPER=y
+CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
-CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
CONFIG_AXP221_DCDC2_VOLT=1100
CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_DM_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_PROMPT="Ventana > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_PROMPT="Ventana > "
CONFIG_ARM=y
CONFIG_TARGET_H2200=y
+CONFIG_SYS_PROMPT="> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="> "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_HARMONY=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
+CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
-# 96boards HiKey
CONFIG_ARM=y
-CONFIG_TARGET_HIKEY=y
-CONFIG_NET=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
+CONFIG_SYS_PROMPT="ib62x0 => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="ib62x0 => "
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_ICONNECT=y
+CONFIG_SYS_PROMPT="iconnect => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="iconnect => "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_IMA3_MX53=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg"
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="IMA3 MX53 U-Boot > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_IMX27LITE=y
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_IMX31_LITEKIT=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="uboot> "
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="uboot> "
+# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_EMR1=4
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_USB0_ID_DET="PH4"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-CONFIG_USB_MUSB_HOST=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_EMR1=4
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_USB0_ID_DET="PH4"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-AP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="Integrator-CP # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_IPAM390=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
+CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FPGA is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
-CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA124=y
CONFIG_TARGET_JETSON_TK1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
+CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_JORNADA=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="HP Jornada# "
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2E_EVM=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="K2E EVM # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="K2E EVM # "
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2HK_EVM=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="K2HK EVM # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="K2HK EVM # "
CONFIG_ARCH_KEYSTONE=y
CONFIG_TARGET_K2L_EVM=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="K2L EVM # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="K2L EVM # "
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SH_SDHI=y
CONFIG_TARGET_KWB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
CONFIG_ARM=y
CONFIG_RMOBILE=y
CONFIG_TARGET_KZM9G=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="KZM-A9-GT# "
+# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SH_SDHI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_LP8X4X=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds"
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
# CONFIG_CMD_IMLS is not set
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr"
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
# CONFIG_CMD_IMLS is not set
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS2085AQDS=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS2085ARDB=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
-CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
--- /dev/null
+CONFIG_PPC=y
+CONFIG_4xx=y
+CONFIG_TARGET_LWMON5=y
+# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_MAGNESIUM=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_OMAP34XX=y
CONFIG_TARGET_MCX=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="mcx # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="mcx # "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_MEDCOM_WIDE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
+CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot-mONStR> "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
-CONFIG_DM_PCI=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_4xx=y
CONFIG_TARGET_ML507=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
+CONFIG_SYS_PROMPT="ml507:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="ml507:/# "
CONFIG_OMAP34XX=y
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="mt_ventoux => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="mt_ventoux => "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_MV88F6281GTW_GE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_MX51_EFIKAMX=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="Efika> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_MX51_EFIKAMX=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_CMD_NET=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DHCP=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
-CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6UL_9X9_EVK=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D"
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NAS220=y
+CONFIG_SYS_PROMPT="nas220> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="nas220> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_NOMADIK=y
-CONFIG_NOMADIK_NHK8815=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="Nomadik> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_NOMADIK=y
-CONFIG_NOMADIK_NHK8815=y
-CONFIG_SYS_EXTRA_OPTIONS="BOOT_ONENAND"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_AUTOBOOT_KEYED=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA124=y
CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
+CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_SPL_DM=y
-CONFIG_SPI_FLASH=y
+CONFIG_CROS_EC_KEYB=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
-CONFIG_CROS_EC_KEYB=y
+CONFIG_SPI_FLASH=y
+CONFIG_TEGRA114_SPI=y
CONFIG_DM_TPM=y
CONFIG_TPM_TIS_I2C=y
-CONFIG_TEGRA114_SPI=y
-CONFIG_DISPLAY_PORT=y
-CONFIG_VIDEO_TEGRA124=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_TPM=y
+CONFIG_DISPLAY_PORT=y
+CONFIG_VIDEO_TEGRA124=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
+CONFIG_TPM=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID_XU3=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="ODROID-XU3 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_SYS_PROMPT="ODROID-XU3 # "
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="Odroid # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ERRNO_STR=y
-CONFIG_SYS_PROMPT="Odroid # "
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="OMAP3_EVM # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="OMAP3_EVM # "
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="OMAP3_EVM # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="OMAP3_EVM # "
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="OMAP3_EVM # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="OMAP3_EVM # "
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_SYS_PROMPT="OMAP Logic # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
-CONFIG_SYS_PROMPT="OMAP Logic # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_MVBLX=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR="S"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="mvblx # "
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Overo # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="Overo # "
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_PANDORA=y
+CONFIG_SYS_PROMPT="Pandora # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="Pandora # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_SDP3430=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="OMAP34XX SDP # "
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_OMAPL138_LCDK=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_OPENRD=y
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_OPENRD=y
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_OPENRD=y
-CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_ORIGEN=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="ORIGEN # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_SYS_PROMPT="ORIGEN # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_OTC570=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_OTC570=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_TEGRA210=y
CONFIG_TARGET_P2371_0000=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
+CONFIG_SYS_PROMPT="Tegra210 (P2371-0000) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P2371_2180=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-2180"
+CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_TEGRA210=y
CONFIG_TARGET_P2571=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
+CONFIG_SYS_PROMPT="Tegra210 (P2571) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_PALMLD=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_PALMTC=y
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_PALMTREO680=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_PAZ00=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
+CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
CONFIG_MIPS=y
CONFIG_TARGET_PB1X00=y
CONFIG_SYS_EXTRA_OPTIONS="PB1000"
+CONFIG_SYS_PROMPT="Pb1x00 # "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Pb1x00 # "
CONFIG_PPC=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="uboot> "
+# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_PCM052=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_NAND_VF610_NFC=y
+CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_PEACH_PI=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Peach-Pi # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_SPI_FLASH=y
-CONFIG_CMD_CROS_EC=y
-CONFIG_CROS_EC=y
-CONFIG_CROS_EC_SPI=y
-CONFIG_CROS_EC_KEYB=y
-CONFIG_DM_TPM=y
-CONFIG_TPM_TIS_I2C=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65090=y
CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_TPS65090=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_DM_TPM=y
+CONFIG_TPM_TIS_I2C=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
-CONFIG_SYS_PROMPT="Peach-Pi # "
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_PEACH_PIT=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Peach-Pit # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_SPI_FLASH=y
-CONFIG_CMD_CROS_EC=y
-CONFIG_CROS_EC=y
-CONFIG_CROS_EC_SPI=y
-CONFIG_CROS_EC_KEYB=y
-CONFIG_DM_TPM=y
-CONFIG_TPM_TIS_I2C=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65090=y
CONFIG_DM_REGULATOR=y
CONFIG_REGULATOR_TPS65090=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_DM_TPM=y
+CONFIG_TPM_TIS_I2C=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
-CONFIG_SYS_PROMPT="Peach-Pit # "
CONFIG_ARM=y
CONFIG_TARGET_PEPPER=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="pepper# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="pepper# "
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_MACH_PH1_LD4=y
-CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_LD4=y
+CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_LD6B=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_PRO4=y
+CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_PRO5=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro5-4kbox"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_MACH_PH1_SLD3=y
-CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_ARCH_UNIPHIER_PH1_SLD3=y
+CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
-CONFIG_MACH_PH1_SLD8=y
-CONFIG_PFC_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
+CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_PLATINUM_PICON=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
+CONFIG_SYS_PROMPT="picon > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="picon > "
CONFIG_TARGET_PLATINUM_TITANIUM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+CONFIG_SYS_PROMPT="titanium > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="titanium > "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_PLUTUX=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
+CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9261=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
+CONFIG_SYS_PROMPT="pm9261> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="pm9261> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
+CONFIG_SYS_PROMPT="u-boot-pm9263> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="u-boot-pm9263> "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9G45=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_POGO_E02=y
+CONFIG_SYS_PROMPT="PogoE02> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="PogoE02> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_TRIZEPSIV=y
-CONFIG_SYS_EXTRA_OPTIONS="POLARIS"
-# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SH_SDHI=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_STAMP9G20=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,PORTUXG20"
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=432
+CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_USB0_ID_DET="PH4"
+CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH8"
+CONFIG_VIDEO_LCD_BL_EN="PH7"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_VIDEO_LCD_PANEL_LVDS=y
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
CONFIG_BLACKFIN=y
CONFIG_TARGET_PR1=y
+CONFIG_SYS_PROMPT="pr1>"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
-CONFIG_SYS_PROMPT="pr1>"
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_PXA255_IDP=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_PXM2=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot# "
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PG0"
+CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_USB0_VBUS_DET="PG1"
+CONFIG_USB0_ID_DET="PG2"
+CONFIG_AXP_GPIO=y
+# CONFIG_VIDEO_HDMI is not set
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A23=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=63306
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=456
+CONFIG_DRAM_ZQ=15291
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=456
+CONFIG_DRAM_ZQ=15291
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_USB_MUSB_HOST=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_DM_RTC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
-CONFIG_DM_RTC=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_VSNPRINTF=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_QONG=y
CONFIG_ARM=y
CONFIG_TARGET_RASTABAN=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot# "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_RD6281A=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_2=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARM=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI=y
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_PHYS_TO_BUS=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARM=y
CONFIG_TARGET_RUT=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_S5P_GONI=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
+CONFIG_SYS_PROMPT="Goni # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
-CONFIG_SYS_PROMPT="Goni # "
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
+CONFIG_SYS_PROMPT="Universal # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_SYS_PROMPT="Universal # "
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
-CONFIG_CLK=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_DEVRES=y
-CONFIG_DM_PCI=y
-CONFIG_PCI_SANDBOX=y
-CONFIG_SPI_FLASH_SANDBOX=y
-CONFIG_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_SANDBOX_GPIO=y
+CONFIG_SYS_I2C_SANDBOX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_RESET=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH_SANDBOX=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
-CONFIG_CROS_EC_KEYB=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_SANDBOX_SERIAL=y
-CONFIG_DM_TPM=y
-CONFIG_TPM_TIS_SANDBOX=y
-CONFIG_SYS_I2C_SANDBOX=y
-CONFIG_SANDBOX_SPI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_SANDBOX=y
-CONFIG_SANDBOX_GPIO=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_SANDBOX=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_SANDBOX=y
CONFIG_RAM=y
+CONFIG_DM_RTC=y
+CONFIG_SANDBOX_SERIAL=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
+CONFIG_SANDBOX_SPI=y
+CONFIG_DM_TPM=y
+CONFIG_TPM_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_MMC=y
-CONFIG_DM_RTC=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_SCB9328=y
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="scb9328> "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
+CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
CONFIG_SECOMX6Q=y
CONFIG_SECOMX6_2GB=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
-CONFIG_SH_SDHI=y
CONFIG_TARGET_SMARTWEB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
-CONFIG_CMD_NET=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARM=y
CONFIG_TARGET_SMDK2410=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="SMDK2410 # "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_SMDK5250=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="SMDK5250 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_SPI_FLASH=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_MAX77686=y
-CONFIG_VIDEO_BRIDGE=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_WM8994=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
CONFIG_ERRNO_STR=y
-CONFIG_SYS_PROMPT="SMDK5250 # "
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_SMDK5420=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="SMDK5420 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_SYS_PROMPT="SMDK5420 # "
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_SMDKC100=y
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
+CONFIG_SYS_PROMPT="SMDKC100 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="SMDKC100 # "
CONFIG_TARGET_SMDKV310=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="SMDKV310 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_MISC is not set
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_SYS_PROMPT="SMDKV310 # "
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_SYS_PROMPT="Snapper> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="Snapper> "
CONFIG_OMAP34XX=y
CONFIG_TARGET_SNIPER=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Sniper # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
-CONFIG_SYS_PROMPT="Sniper # "
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_SNOW=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="snow # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_SPI_FLASH=y
-CONFIG_CMD_CROS_EC=y
-CONFIG_CROS_EC=y
-CONFIG_CROS_EC_I2C=y
-CONFIG_CROS_EC_KEYB=y
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_S5P=y
-CONFIG_DEBUG_UART_BASE=0x12c30000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DM_TPM=y
-CONFIG_TPM_TIS_I2C=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_S5M8767=y
CONFIG_DM_REGULATOR_MAX77686=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_TPS65090=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
-CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
-CONFIG_SYS_PROMPT="snow # "
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_S5P=y
+CONFIG_DEBUG_UART_BASE=0x12c30000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_DM_TPM=y
+CONFIG_TPM_TIS_I2C=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
+CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_SNOWBALL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U8500 $ "
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_DM=y
+CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_DM=y
+CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_OF_CONTROL=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_OF_CONTROL=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_DM_SEQ_ALIAS=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_OF_CONTROL=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_USE_4K_SECTORS=n
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_DM_SEQ_ALIAS=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_DM=y
+CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_GPIO=y
-CONFIG_DWAPB_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_SPRING=y
+CONFIG_DM_I2C=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="spring # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SOUND=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_SPI_FLASH=y
-CONFIG_CMD_CROS_EC=y
-CONFIG_CROS_EC=y
-CONFIG_CROS_EC_I2C=y
-CONFIG_CROS_EC_KEYB=y
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_S5P=y
-CONFIG_DEBUG_UART_BASE=0x12c30000
-CONFIG_DEBUG_UART_CLOCK=100000000
-CONFIG_DM_TPM=y
-CONFIG_TPM_TIS_I2C=y
-CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_SPI_FLASH=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_S5M8767=y
CONFIG_DM_REGULATOR_MAX77686=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_TPS65090=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
-CONFIG_SYS_PROMPT="spring # "
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_S5P=y
+CONFIG_DEBUG_UART_BASE=0x12c30000
+CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_DM_TPM=y
+CONFIG_TPM_TIS_I2C=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_STAMP9G20=y
-CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARM=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="U-Boot > "
+# CONFIG_CMD_SETEXPR is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_RMOBILE=y
+CONFIG_TARGET_STOUT=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_EXTRA_OPTIONS="stv0991"
+CONFIG_SYS_PROMPT="STV0991> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_OF_CONTROL=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_PROMPT="STV0991> "
CONFIG_OMAP34XX=y
CONFIG_TARGET_TAO3530=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="TAO-3530 # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="TAO-3530 # "
CONFIG_TARGET_TAURUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_ARC=y
CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_TARGET_TB100=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
+CONFIG_SYS_PROMPT="[tb100]:~# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_SERIAL=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="[tb100]:~# "
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TBS2910=y
+CONFIG_SYS_PROMPT="Matrix U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_DM=y
CONFIG_DM_THERMAL=y
-CONFIG_SYS_PROMPT="Matrix U-Boot> "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA30=y
CONFIG_TARGET_TEC_NG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
+CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_TEC=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
+CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
CONFIG_ARM=y
CONFIG_TARGET_THUBAN=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_ARM=y
CONFIG_TARGET_TI814X_EVM=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="U-Boot# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_ARM=y
CONFIG_TARGET_TI816X_EVM=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="u-boot/ti816x# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="u-boot/ti816x# "
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TITANIUM=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
+CONFIG_SYS_PROMPT="Titanium > "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="Titanium > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_TK71=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_TRATS2=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_PROMPT="Trats2 # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_SYS_PROMPT="Trats2 # "
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
+CONFIG_SYS_PROMPT="Trats # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_SYS_PROMPT="Trats # "
CONFIG_OMAP34XX=y
CONFIG_TARGET_TRICORDER=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_TRIMSLICE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
+CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_TRIZEPSIV=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_TSERIES=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
CONFIG_TARGET_TSERIES=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
CONFIG_TARGET_TSERIES=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="U-Boot (BuR V2.0)# "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_TT01=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="TT01> "
CONFIG_OMAP34XX=y
CONFIG_TARGET_TWISTER=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="twister => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="twister => "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_TX25=y
-CONFIG_SPL=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_U8500_HREF=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="U8500 $ "
-CONFIG_SPL=y
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
-CONFIG_DM=y
-CONFIG_DM_THERMAL=y
CONFIG_TARGET_UDOO=y
+CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_USB_A9263=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_4xx=y
CONFIG_TARGET_V5FX30TEVAL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o"
+CONFIG_SYS_PROMPT="v5fx30t:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="v5fx30t:/# "
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUM=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
+CONFIG_SYS_PROMPT="VCT# "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="VCT# "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PLATINUMAVC=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_ONENAND=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_TARGET_VCT=y
CONFIG_VCT_PREMIUM=y
CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="$ "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA124=y
CONFIG_TARGET_VENICE2=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
+CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
+CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_AB"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_PB"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SYS_EXTRA_OPTIONS="ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB"
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_MISC is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_JUNO=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
+CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_DM=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_PROMPT="VExpress64# "
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM_SERIAL=y
CONFIG_DEFAULT_DEVICE_TREE="vexpress64"
+CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_DM=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_PROMPT="VExpress64# "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_VISION2=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SYS_PROMPT="Vision II U-boot > "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_VL_MA2SC=y
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="U-Boot> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_VL_MA2SC=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMLOAD"
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_SETEXPR is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_VPAC270=y
-CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_128M"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="$ "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_VPAC270=y
-CONFIG_SYS_EXTRA_OPTIONS="NOR,RAM_256M"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="$ "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_VPAC270=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M"
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="$ "
CONFIG_ARM=y
CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
CONFIG_TEGRA20=y
CONFIG_TARGET_WHISTLER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
+CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SPL_DM=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_KIRKWOOD=y
-CONFIG_TARGET_WIRELESS_SPACE=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-ONFIG_SYS_PROMPT="ws> "
CONFIG_ARM=y
CONFIG_TARGET_WOODBURN=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="woodburn U-Boot > "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
-# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="woodburn U-Boot > "
+# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_TARGET_WORK_92105=y
+CONFIG_DM_GPIO=y
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
-CONFIG_DM_GPIO=y
CONFIG_ARM=y
CONFIG_TARGET_X600=y
CONFIG_SPL=y
+CONFIG_SYS_PROMPT="X600> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_SYS_PROMPT="X600> "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_XAENIAX=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
+CONFIG_SYS_PROMPT="xlx-ppc405:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="xlx-ppc405:/# "
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
+CONFIG_SYS_PROMPT="board:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="board:/# "
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_ZIPITZ2=y
-# CONFIG_CMD_IMLS is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
CONFIG_ARM=y
CONFIG_TARGET_ZMX25=y
+CONFIG_SYS_PROMPT="zmx25> "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
CONFIG_AUTOBOOT_DELAY_STR="delaygs"
CONFIG_AUTOBOOT_STOP_STR="stopgs"
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_PROMPT="zmx25> "
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
-CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZC706=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZC70X=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
+# CONFIG_SYS_MALLOC_F is not set
CONFIG_TARGET_ZYNQ_ZYBO=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
#include <common.h>
#include <command.h>
#include <ide.h>
+#include <memalign.h>
#include "part_dos.h"
#ifdef HAVE_BLOCK_DEVICE
#include <ide.h>
#include <inttypes.h>
#include <malloc.h>
+#include <memalign.h>
#include <part_efi.h>
#include <linux/ctype.h>
#include <common.h>
#include <command.h>
+#include <memalign.h>
#include <ide.h>
#include "part_mac.h"
make cm_t35_config
make
-* BlueLYNX-X:
-
-make omap3_mvblx_config
-make
Custom commands
===============
sbc405 powerpc ppc4xx - -
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
-lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com>
alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de>
cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de>
+++ /dev/null
-On the enbw_cmc board is a KSZ8864RMN switch which needs
-configured through spi before working. This is done on
-startup from u-boot through a config file stored at an
-address specified in the "hwconfig" environment variable,
-subcommand "config".
-
-For example on the enbw_cmc board:
-
-hwconfig=switch:lan=on,pwl=off,config=0x60160000
-
-The file has the following structure:
-
-- a comment starts with a '#' or a ';' and ends with a newline
-- The switch needs for its config a reg/value pair, so we
- have two columns in the file:
- reg : contains the register address
- value: contains a 8 bit register value
- This 2 columns are seperated through space or tab.
-
-example (minimal configuration on the enbw_cmc board):
-
-;reg value comment
-;-----------------------------------------
-0x01 0x00
-0x01 0x01 ; Start Switch with this configuration
$ make ph1_sld8_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
+PH1-Pro5:
+ $ make ph1_pro5_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi-
+
+ProXstream2:
+ $ make pxs2_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi-
+
+PH1-LD6b:
+ $ make ph1_ld6b_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi-
+
You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
to use your favorite compiler.
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
their own hw_watchdog_reset routine.
+ TODO: vision2 is removed now, so perhaps this can be changed.
CONFIG_XILINX_TB_WATCHDOG
Available for Xilinx Axi platforms to service timebase watchdog timer.
PCI_BDF(0, 3, 0) INTA PIRQA
...
+Porting Hints
+-------------
+
+Quark-specific considerations:
+
+To port U-Boot to other boards based on the Intel Quark SoC, a few things need
+to be taken care of. The first important part is the Memory Reference Code (MRC)
+parameters. Quark MRC supports memory-down configuration only. All these MRC
+parameters are supplied via the board device tree. To get started, first copy
+the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
+change these values by consulting board manuals or your hardware vendor.
+Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
+The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
+but by default they are held in reset after power on. In U-Boot, PCIe
+initialization is properly handled as per Quark's firmware writer guide.
+In your board support codes, you need provide two routines to aid PCIe
+initialization, which are board_assert_perst() and board_deassert_perst().
+The two routines need implement a board-specific mechanism to assert/deassert
+PCIe PERST# pin. Care must be taken that in those routines that any APIs that
+may trigger PCI enumeration process are strictly forbidden, as any access to
+PCIe root port's configuration registers will cause system hang while it is
+held in reset. For more details, check how they are implemented by the Intel
+Galileo board support codes in board/intel/galileo/galileo.c.
+
TODO List
---------
- Audio
- Chrome OS verified boot
- SMI and ACPI support, to provide platform info and facilities to Linux
+- Desktop Management Interface (DMI) [15] support
References
----------
[12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
[13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
[14] doc/device-tree-bindings/misc/intel,irq-router.txt
+[15] http://en.wikipedia.org/wiki/Desktop_Management_Interface
# things simple and easy to look up/coordinate.
alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net>
alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com>
+alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com>
alias afleming Andy Fleming <afleming@gmail.com>
alias ag Anatolij Gustschin <agust@denx.de>
alias alisonwang Alison Wang <alison.wang@freescale.com>
alias wd Wolfgang Denk <wd@denx.de>
# Architecture aliases
-alias arch arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86
+alias arch arc, arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86
alias arches arch
+alias arc uboot, abrodkin
+
alias arm uboot, aaribaud
alias at91 uboot, abiessmann
alias davinci ti
#include <asm/errno.h>
#include <asm/io.h>
#include <malloc.h>
+#include <memalign.h>
#include <scsi.h>
#include <libata.h>
#include <linux/ctype.h>
dev->flags |= DM_FLAG_ACTIVATED;
- /* continue regardless of the result of pinctrl */
- pinctrl_select_state(dev, "default");
+ /*
+ * Process pinctrl for everything except the root device, and
+ * continue regardless of the result of pinctrl.
+ */
+ if (dev->parent)
+ pinctrl_select_state(dev, "default");
ret = uclass_pre_probe_device(dev);
if (ret)
#if CONFIG_IS_ENABLED(OF_CONTROL)
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ dev->parent->of_offset,
+ dev->of_offset, "reg",
+ 0, NULL);
if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
addr = simple_bus_translate(dev->parent, addr);
*/
#define MV_DEBUG_INIT
-#define BIT(x) (1 << (x))
-
#ifdef MV_DEBUG_INIT
#define DEBUG_INIT_S(s) puts(s)
#define DEBUG_INIT_D(d, l) printf("%x", d)
void dfu_write_transaction_cleanup(struct dfu_entity *dfu)
{
/* clear everything */
- dfu_free_buf();
dfu->crc = 0;
dfu->offset = 0;
dfu->i_blk_seq_num = 0;
dfu->r_left = dfu->get_medium_size(dfu);
if (dfu->r_left < 0)
return dfu->r_left;
- switch (dfu->layout) {
- case DFU_RAW_ADDR:
- case DFU_RAM_ADDR:
- break;
- default:
- if (dfu->r_left > dfu_buf_size) {
- printf("%s: File too big for buffer\n",
- __func__);
- return -EOVERFLOW;
- }
- }
debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left);
dfu_hash_algo->name, dfu->crc);
puts("\nUPLOAD ... done\nCtrl+C to exit ...\n");
- dfu_free_buf();
dfu->i_blk_seq_num = 0;
dfu->crc = 0;
dfu->offset = 0;
__func__, interface);
return -1;
}
+ dfu_get_buf(dfu);
return 0;
}
{
struct dfu_entity *dfu, *p, *t = NULL;
+ dfu_free_buf();
list_for_each_entry_safe_reverse(dfu, p, &dfu_list, list) {
list_del(&dfu->list);
if (dfu->free_entity)
static unsigned char *dfu_file_buf;
static long dfu_file_buf_len;
+static long dfu_file_buf_filled;
static int mmc_access_part(struct dfu_entity *dfu, struct mmc *mmc, int part)
{
return dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size;
case DFU_FS_FAT:
case DFU_FS_EXT4:
+ dfu_file_buf_filled = -1;
ret = mmc_file_op(DFU_OP_SIZE, dfu, NULL, &len);
if (ret < 0)
return ret;
+ if (len > CONFIG_SYS_DFU_MAX_FILE_SIZE)
+ return -1;
return len;
default:
printf("%s: Layout (%s) not (yet) supported!\n", __func__,
}
}
+static int mmc_file_unbuffer(struct dfu_entity *dfu, u64 offset, void *buf,
+ long *len)
+{
+ int ret;
+ long file_len;
+
+ if (dfu_file_buf_filled == -1) {
+ ret = mmc_file_op(DFU_OP_READ, dfu, dfu_file_buf, &file_len);
+ if (ret < 0)
+ return ret;
+ dfu_file_buf_filled = file_len;
+ }
+ if (offset + *len > dfu_file_buf_filled)
+ return -EINVAL;
+
+ /* Add to the current buffer. */
+ memcpy(buf, dfu_file_buf + offset, *len);
+
+ return 0;
+}
+
int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf,
long *len)
{
break;
case DFU_FS_FAT:
case DFU_FS_EXT4:
- ret = mmc_file_op(DFU_OP_READ, dfu, buf, len);
+ ret = mmc_file_unbuffer(dfu, offset, buf, len);
break;
default:
printf("%s: Layout (%s) not (yet) supported!\n", __func__,
* read on another one.
*
* In order to keep this code simple, GPIOS are considered here as
- * homogeneous and linear, from 0 to 127.
+ * homogeneous and linear, from 0 to 159.
*
* ** WARNING #1 **
*
* Please read NOTE in description of lpc32xx_gpio_get_function().
*/
-#define LPC32XX_GPIOS 128
+#define LPC32XX_GPIOS 160
struct lpc32xx_gpio_priv {
struct gpio_regs *regs;
/**
* We have 4 GPIO ports of 32 bits each
+ *
+ * Port mapping offset (32 bits each):
+ * - Port 0: 0
+ * - Port 1: 32
+ * - Port 2: 64
+ * - Port 3: GPO / GPIO (output): 96
+ * - Port 3: GPI: 128
*/
-#define MAX_GPIO 128
+#define MAX_GPIO 160
-#define GPIO_TO_PORT(gpio) ((gpio / 32) & 3)
+#define GPIO_TO_PORT(gpio) ((gpio / 32) & 7)
#define GPIO_TO_RANK(gpio) (gpio % 32)
#define GPIO_TO_MASK(gpio) (1 << (gpio % 32))
break;
case 2:
/* ports 2 and 3 share a common direction */
- case 3:
writel(mask, ®s->p2_p3_dir_clr);
break;
+ case 3:
+ /* Setup direction only for GPIO_xx. */
+ if ((mask >= 25) && (mask <= 30))
+ writel(mask, ®s->p2_p3_dir_clr);
+ break;
+ case 4:
+ /* GPI_xx; nothing to do. */
+ break;
default:
return -1;
}
value = readl(®s->p2_inp_state);
break;
case 3:
+ /* Read GPO_xx and GPIO_xx (as output) using p3_outp_state. */
+ value = readl(®s->p3_outp_state);
+ break;
+ case 4:
+ /* Read GPI_xx and GPIO_xx (as input) using p3_inp_state. */
value = readl(®s->p3_inp_state);
break;
default:
case 3:
writel(mask, ®s->p3_outp_set);
break;
+ case 4:
+ /* GPI_xx; invalid. */
default:
return -1;
}
case 3:
writel(mask, ®s->p3_outp_clr);
break;
+ case 4:
+ /* GPI_xx; invalid. */
default:
return -1;
}
break;
case 2:
/* ports 2 and 3 share a common direction */
- case 3:
writel(mask, ®s->p2_p3_dir_set);
break;
+ case 3:
+ /* Setup direction only for GPIO_xx. */
+ if ((mask >= 25) && (mask <= 30))
+ writel(mask, ®s->p2_p3_dir_set);
+ break;
+ case 4:
+ /* GPI_xx; invalid. */
default:
return -1;
}
plat = calloc(1, sizeof(*plat));
if (!plat)
return -ENOMEM;
- reg = fdtdec_get_addr(blob, node, "reg");
- if (reg != FDT_ADDR_T_NONE)
- bank = (struct s5p_gpio_bank *)((ulong)base + reg);
- plat->bank = bank;
- plat->bank_name = fdt_get_name(blob, node, NULL);
- debug("dev at %p: %s\n", bank, plat->bank_name);
+ plat->bank_name = fdt_get_name(blob, node, NULL);
ret = device_bind(parent, parent->driver,
- plat->bank_name, plat, -1, &dev);
+ plat->bank_name, plat, -1, &dev);
if (ret)
return ret;
+
dev->of_offset = node;
+
+ reg = dev_get_addr(dev);
+ if (reg != FDT_ADDR_T_NONE)
+ bank = (struct s5p_gpio_bank *)((ulong)base + reg);
+
+ plat->bank = bank;
+
+ debug("dev at %p: %s\n", bank, plat->bank_name);
}
return 0;
debug("read_bit: addr = %lx, pos = %ld, "
"r_width = %ld\n", dr->reg, pos, dr->reg_width);
- return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
+ return
+ (gpio_read_raw_reg(dr->mapped_reg + 0x4, dr->reg_width) >> pos) & 1;
}
static void gpio_write_bit(struct pinmux_data_reg *dr,
/*
* NVIDIA Tegra20 GPIO handling.
- * (C) Copyright 2010-2012
+ * (C) Copyright 2010-2012,2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
DECLARE_GLOBAL_DATA_PTR;
-enum {
- TEGRA_CMD_INFO,
- TEGRA_CMD_PORT,
- TEGRA_CMD_OUTPUT,
- TEGRA_CMD_INPUT,
-};
+static const int CONFIG_SFIO = 0;
+static const int CONFIG_GPIO = 1;
+static const int DIRECTION_INPUT = 0;
+static const int DIRECTION_OUTPUT = 1;
struct tegra_gpio_platdata {
struct gpio_ctlr_bank *bank;
int base_gpio; /* Port number for this port (0, 1,.., n-1) */
};
-/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
+/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
static int get_config(unsigned gpio)
{
struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
int type;
u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
- type = (u >> GPIO_BIT(gpio)) & 1;
+ type = (u >> GPIO_BIT(gpio)) & 1;
debug("get_config: port = %d, bit = %d is %s\n",
GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
- return type;
+ return type ? CONFIG_GPIO : CONFIG_SFIO;
}
-/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
+/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
static void set_config(unsigned gpio, int type)
{
struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
- if (type) /* GPIO */
+ if (type != CONFIG_SFIO)
u |= 1 << GPIO_BIT(gpio);
else
u &= ~(1 << GPIO_BIT(gpio));
debug("get_direction: port = %d, bit = %d, %s\n",
GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
- return dir;
+ return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
}
/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
- if (output)
+ if (output != DIRECTION_INPUT)
u |= 1 << GPIO_BIT(gpio);
else
u &= ~(1 << GPIO_BIT(gpio));
* Generic_GPIO primitives.
*/
-static int tegra_gpio_request(struct udevice *dev, unsigned offset,
- const char *label)
-{
- struct tegra_port_info *state = dev_get_priv(dev);
-
- /* Configure as a GPIO */
- set_config(state->base_gpio + offset, 1);
-
- return 0;
-}
-
/* set GPIO pin 'gpio' as an input */
static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct tegra_port_info *state = dev_get_priv(dev);
/* Configure GPIO direction as input. */
- set_direction(state->base_gpio + offset, 0);
+ set_direction(state->base_gpio + offset, DIRECTION_INPUT);
+
+ /* Enable the pin as a GPIO */
+ set_config(state->base_gpio + offset, 1);
return 0;
}
set_level(gpio, value);
/* Configure GPIO direction as output. */
- set_direction(gpio, 1);
+ set_direction(gpio, DIRECTION_OUTPUT);
+
+ /* Enable the pin as a GPIO */
+ set_config(state->base_gpio + offset, 1);
return 0;
}
for (i = 0; i < len; i++) {
switch (config[i].init) {
case TEGRA_GPIO_INIT_IN:
- gpio_direction_input(config[i].gpio);
+ set_direction(config[i].gpio, DIRECTION_INPUT);
break;
case TEGRA_GPIO_INIT_OUT0:
- gpio_direction_output(config[i].gpio, 0);
+ set_level(config[i].gpio, 0);
+ set_direction(config[i].gpio, DIRECTION_OUTPUT);
break;
case TEGRA_GPIO_INIT_OUT1:
- gpio_direction_output(config[i].gpio, 1);
+ set_level(config[i].gpio, 1);
+ set_direction(config[i].gpio, DIRECTION_OUTPUT);
break;
}
- set_config(config[i].gpio, 1);
+ set_config(config[i].gpio, CONFIG_GPIO);
}
}
}
static const struct dm_gpio_ops gpio_tegra_ops = {
- .request = tegra_gpio_request,
.direction_input = tegra_gpio_direction_input,
.direction_output = tegra_gpio_direction_output,
.get_value = tegra_gpio_get_value,
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
-obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
/*
* Register mxc i2c adapters
*/
+#ifdef CONFIG_SYS_I2C_MXC_I2C1
U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
CONFIG_SYS_MXC_I2C1_SPEED,
CONFIG_SYS_MXC_I2C1_SLAVE, 0)
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC_I2C2
U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
CONFIG_SYS_MXC_I2C2_SPEED,
CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+#endif
+
#ifdef CONFIG_SYS_I2C_MXC_I2C3
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Basic U-Boot I2C interface for STn8500/DB8500
- * Author: Michael Brandt <Michael.Brandt@stericsson.com> for ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Only 7-bit I2C device addresses are supported.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include "u8500_i2c.h"
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100) /* I2C bus timeout */
-#define U8500_I2C_FIFO_FLUSH_COUNTER 500000 /* flush "timeout" */
-#define U8500_I2C_SCL_FREQ 100000 /* I2C bus clock freq */
-#define U8500_I2C_INPUT_FREQ 48000000 /* Input clock freq */
-#define TX_FIFO_THRESHOLD 0x4
-#define RX_FIFO_THRESHOLD 0x4
-#define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */
-
-#define WRITE_FIELD(var, mask, shift, value) \
- (var = ((var & ~(mask)) | ((value) << (shift))))
-
-static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
-static unsigned int i2c_bus_num;
-static unsigned int i2c_bus_speed[] = {
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
- CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
-};
-static struct u8500_i2c_regs *i2c_dev[] = {
- (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
- (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
- (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
- (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
-};
-
-static struct {
- int periph;
- int pcken;
- int kcken;
-} i2c_clock_bits[] = {
- {3, 3, 3}, /* I2C0 */
- {1, 2, 2}, /* I2C1 */
- {1, 6, 6}, /* I2C2 */
- {2, 0, 0}, /* I2C3 */
-};
-
-static void i2c_set_bit(void *reg, u32 mask)
-{
- writel(readl(reg) | mask, reg);
-}
-
-static void i2c_clr_bit(void *reg, u32 mask)
-{
- writel(readl(reg) & ~mask, reg);
-}
-
-static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
-{
- writel((readl(reg) & ~mask) | (value << shift), reg);
-}
-
-static int __i2c_set_bus_speed(unsigned int speed)
-{
- u32 value;
- struct u8500_i2c_regs *i2c_regs;
-
- i2c_regs = i2c_dev[i2c_bus_num];
-
- /* Select standard (100 kbps) speed mode */
- i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
- U8500_I2C_CR_SHIFT_SM, 0x0);
-
- /*
- * Set the Baud Rate Counter 2 value
- * Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle )
- * Foncycle = 0 (no digital filtering)
- */
- value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
- i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
- U8500_I2C_BRCR_SHIFT_BRCNT2, value);
-
- /* ensure that BRCNT value is zero */
- i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
- U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
-
- return U8500_I2C_INPUT_FREQ/(value * 2);
-}
-
-/*
- * i2c_init - initialize the i2c bus
- *
- * speed: bus speed (in HZ)
- * slaveaddr: address of device in slave mode
- *
- * Slave mode is not implemented.
- */
-void i2c_init(int speed, int slaveaddr)
-{
- struct u8500_i2c_regs *i2c_regs;
-
- debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
-
- u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
- i2c_clock_bits[i2c_bus_num].pcken,
- i2c_clock_bits[i2c_bus_num].kcken);
-
- i2c_regs = i2c_dev[i2c_bus_num];
-
- /* Disable the controller */
- i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
-
- /* Clear registers */
- writel(0, &i2c_regs->cr);
- writel(0, &i2c_regs->scr);
- writel(0, &i2c_regs->hsmcr);
- writel(0, &i2c_regs->tftr);
- writel(0, &i2c_regs->rftr);
- writel(0, &i2c_regs->dmar);
-
- i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
-
- /*
- * Set our own address.
- * Set slave address mode to 7 bit addressing mode
- */
- i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
- i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
- U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
- /* Slave Data Set up Time */
- i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
- U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
-
- /* Disable the DMA sync logic */
- i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
- U8500_I2C_CR_SHIFT_DMA_SLE, 0);
-
- /* Disable interrupts */
- writel(0, &i2c_regs->imscr);
-
- /* Configure bus master mode */
- i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
- U8500_I2C_BUS_MASTER_MODE);
- /* Set FIFO threshold values */
- writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
- writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
-
- /* Enable the I2C Controller */
- i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
-
- bus_initialized[i2c_bus_num] = 1;
-}
-
-
-/*
- * loop_till_bit_clear - polls on a bit till it clears
- * ioreg: register where you want to check status
- * mask: bit mask for the bit you wish to check
- * timeout: timeout in ticks/s
- */
-static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
-{
- unsigned long timebase = get_timer(0);
-
- do {
- if ((readl(io_reg) & mask) == 0x0UL)
- return 0;
- } while (get_timer(timebase) < timeout);
-
- debug("loop_till_bit_clear timed out\n");
- return -1;
-}
-
-/*
- * loop_till_bit_set - polls on a bit till it is set.
- * ioreg: register where you want to check status
- * mask: bit mask for the bit you wish to check
- * timeout: timeout in ticks/s
- */
-static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
-{
- unsigned long timebase = get_timer(0);
-
- do {
- if ((readl(io_reg) & mask) != 0x0UL)
- return 0;
- } while (get_timer(timebase) < timeout);
-
- debug("loop_till_bit_set timed out\n");
- return -1;
-}
-
-/*
- * flush_fifo - flush the I2C TX and RX FIFOs
- */
-static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
-{
- int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
-
- /* Flush Tx FIFO */
- i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
- /* Flush Rx FIFO */
- i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
- while (counter--) {
- if (!(readl(&i2c_regs->cr) &
- (U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
- break;
- }
- return;
-}
-
-#ifdef DEBUG
-static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
-{
- int cause;
-
- printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
- cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
- U8500_I2C_SR_SHIFT_CAUSE;
- switch (cause) {
- case U8500_I2C_NACK_ADDR:
- printf("No Ack received after Slave Address xmission\n");
- break;
- case U8500_I2C_NACK_DATA:
- printf("Valid for MASTER_WRITE: No Ack received "
- "during data phase\n");
- break;
- case U8500_I2C_ACK_MCODE:
- printf("Master recv ack after xmission of master code"
- "in hs mode\n");
- break;
- case U8500_I2C_ARB_LOST:
- printf("Master Lost arbitration\n");
- break;
- case U8500_I2C_BERR_START:
- printf("Slave restarts\n");
- break;
- case U8500_I2C_BERR_STOP:
- printf("Slave reset\n");
- break;
- case U8500_I2C_OVFL:
- printf("Overflow\n");
- break;
- default:
- printf("Unknown error type\n");
- }
-}
-#endif
-
-/*
- * i2c_abort - called when a I2C transaction failed
- */
-static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
-{
-#ifdef DEBUG
- print_abort_reason(i2c_regs);
-#endif
- /* flush RX and TX fifos */
- flush_fifo(i2c_regs);
-
- /* Acknowledge the Master Transaction Done */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
-
- /* Acknowledge the Master Transaction Done Without Stop */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
-
- i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
-}
-
-/*
- * write addr, alias index, to I2C bus.
- */
-static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
-{
- while (alen--) {
- /* Wait until the Tx Fifo is not full */
- if (loop_till_bit_clear((void *)&i2c_regs->risr,
- U8500_I2C_INT_TXFF,
- U8500_I2C_ENDAD_COUNTER)) {
- i2c_abort(i2c_regs);
- return -1;
- }
-
- /* MSB first */
- writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
- }
-
- return 0;
-}
-
-/*
- * Internal simplified read function:
- * i2c_regs: Pointer to I2C registers for current bus
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one register)
- * value: Where to put the data
- *
- * Returns: 0 on success, not 0 on failure
- */
-static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
- uint addr, int alen, uchar *value)
-{
- u32 mcr = 0;
-
- /* Set the address mode to 7 bit */
- WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
-
- /* Store the slave address in the master control register */
- WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
-
- if (alen != 0) {
- /* Master write operation */
- mcr &= ~(U8500_I2C_MCR_OP);
-
- /* Configure the Frame length to one byte */
- WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
- U8500_I2C_MCR_SHIFT_LENGTH, 1);
-
- /* Repeated start, no stop */
- mcr &= ~(U8500_I2C_MCR_STOP);
-
- /* Write Master Control Register */
- writel(mcr, &i2c_regs->mcr);
-
- /* send addr/index */
- if (i2c_write_addr(i2c_regs, addr, alen) != 0)
- return -1;
-
- /* Check for the Master Transaction Done Without Stop */
- if (loop_till_bit_set((void *)&i2c_regs->risr,
- U8500_I2C_INT_MTDWS,
- U8500_I2C_ENDAD_COUNTER)) {
- return -1;
- }
-
- /* Acknowledge the Master Transaction Done Without Stop */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
- }
-
- /* Master control configuration for read operation */
- mcr |= U8500_I2C_MCR_OP;
-
- /* Configure the STOP condition, we read only one byte */
- mcr |= U8500_I2C_MCR_STOP;
-
- /* Set the frame length to one byte, we support only 1 byte reads */
- WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
-
- i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
- U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
-
- /*
- * receive_data_polling
- */
-
- /* Wait until the Rx FIFO is not empty */
- if (loop_till_bit_clear((void *)&i2c_regs->risr,
- U8500_I2C_INT_RXFE,
- U8500_I2C_ENDAD_COUNTER))
- return -1;
-
- /* Read the data byte from Rx FIFO */
- *value = readb(&i2c_regs->rfr);
-
- /* Wait until the work is done */
- if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
- U8500_I2C_ENDAD_COUNTER))
- return -1;
-
- /* Acknowledge the Master Transaction Done */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
-
- /* If MTD is set, Master Transaction Done Without Stop is set too */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
-
- return 0;
-}
-
-/*
- * Internal simplified write function:
- * i2c_regs: Pointer to I2C registers for current bus
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one register)
- * data: Where to read the data
- * len: How many bytes to write
- *
- * Returns: 0 on success, not 0 on failure
- */
-static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
- int alen, u8 *data, int len)
-{
- int i;
- u32 mcr = 0;
-
- /* Set the address mode to 7 bit */
- WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
-
- /* Store the slave address in the master control register */
- WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
-
- /* Write operation */
- mcr &= ~(U8500_I2C_MCR_OP);
-
- /* Current transaction is terminated by STOP condition */
- mcr |= U8500_I2C_MCR_STOP;
-
- /* Frame length: addr byte + len */
- WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
- (alen + len));
-
- /* Write MCR register */
- writel(mcr, &i2c_regs->mcr);
-
- if (i2c_write_addr(i2c_regs, addr, alen) != 0)
- return -1;
-
- for (i = 0; i < len; i++) {
- /* Wait until the Tx FIFO is not full */
- if (loop_till_bit_clear((void *)&i2c_regs->risr,
- U8500_I2C_INT_TXFF,
- U8500_I2C_ENDAD_COUNTER))
- return -1;
-
- /* it is a 32 bit register with upper 24 reserved R/O */
- writeb(data[i], &i2c_regs->tfr);
- }
-
- /* Check for Master Transaction Done */
- if (loop_till_bit_set((void *)&i2c_regs->risr,
- U8500_I2C_INT_MTD,
- U8500_I2C_ENDAD_COUNTER)) {
- printf("i2c_write_byte error2: risr %08x\n",
- i2c_regs->risr);
- return -1;
- }
-
- /* Acknowledge Master Transaction Done */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
-
- /* Acknowledge Master Transaction Done Without Stop */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
-
- return 0;
-}
-
-/*
- * Probe the given I2C chip address. Returns 0 if a chip responded,
- * not 0 on failure.
- */
-int i2c_probe(uchar chip)
-{
- u32 mcr = 0;
- struct u8500_i2c_regs *i2c_regs;
-
- if (chip == CONFIG_SYS_I2C_SLAVE)
- return 1;
-
- i2c_regs = i2c_dev[i2c_bus_num];
-
- /* Set the address mode to 7 bit */
- WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
-
- /* Store the slave address in the master control register */
- WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
-
- /* Read operation */
- mcr |= U8500_I2C_MCR_OP;
-
- /* Set the frame length to one byte */
- WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
-
- /* Current transaction is terminated by STOP condition */
- mcr |= U8500_I2C_MCR_STOP;
-
- /* Write MCR register */
- writel(mcr, &i2c_regs->mcr);
-
- /* Wait until the Rx Fifo is not empty */
- if (loop_till_bit_clear((void *)&i2c_regs->risr,
- U8500_I2C_INT_RXFE,
- U8500_I2C_ENDAD_COUNTER)) {
- i2c_abort(i2c_regs);
- return -1;
- }
-
- flush_fifo(i2c_regs);
-
- /* Acknowledge the Master Transaction Done */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
-
- /* Acknowledge the Master Transaction Done Without Stop */
- i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
-
- return 0;
-}
-
-/*
- * Read/Write interface:
- * chip: I2C chip address, range 0..127
- * addr: Memory (register) address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Where to read/write the data
- * len: How many bytes to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int i;
- int rc;
- struct u8500_i2c_regs *i2c_regs;
-
- if (alen > 2) {
- debug("I2C read: addr len %d not supported\n", alen);
- return 1;
- }
-
- i2c_regs = i2c_dev[i2c_bus_num];
-
- for (i = 0; i < len; i++) {
- rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
- if (rc != 0) {
- debug("I2C read: I/O error: %d\n", rc);
- i2c_abort(i2c_regs);
- return rc;
- }
- }
-
- return 0;
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int rc;
- struct u8500_i2c_regs *i2c_regs;
- i2c_regs = i2c_dev[i2c_bus_num];
-
- rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
- len);
- if (rc != 0) {
- debug("I2C write: I/O error\n");
- i2c_abort(i2c_regs);
- return rc;
- }
- return 0;
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
- if (bus > ARRAY_SIZE(i2c_dev) - 1) {
- debug("i2c_set_bus_num: only up to bus %d supported\n",
- ARRAY_SIZE(i2c_dev)-1);
- return -1;
- }
-
- i2c_bus_num = bus;
-
- if (!bus_initialized[i2c_bus_num])
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- return 0;
-}
-
-int i2c_set_bus_speed(unsigned int speed)
-{
-
- if (speed > U8500_I2C_MAX_STANDARD_SCL) {
- debug("i2c_set_bus_speed: only up to %d supported\n",
- U8500_I2C_MAX_STANDARD_SCL);
- return -1;
- }
-
- /* sets as side effect i2c_bus_speed[i2c_bus_num] */
- i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
-
- return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return i2c_bus_num;
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
- return i2c_bus_speed[i2c_bus_num];
-}
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _U8500_I2C_H_
-#define _U8500_I2C_H_
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/u8500.h>
-
-struct u8500_i2c_regs {
- u32 cr; /* Control Register 0x00 */
- u32 scr; /* Slave Address Register 0x04 */
- u32 hsmcr; /* HS Master code Register 0x08 */
- u32 mcr; /* Master Control Register 0x0C */
- u32 tfr; /* Transmit Fifo Register 0x10 */
- u32 sr; /* Status Register 0x14 */
- u32 rfr; /* Receiver Fifo Register 0x18 */
- u32 tftr; /* Transmit Fifo Threshold Register 0x1C */
- u32 rftr; /* Receiver Fifo Threshold Register 0x20 */
- u32 dmar; /* DMA register 0x24 */
- u32 brcr; /* Baud Rate Counter Register 0x28 */
- u32 imscr; /* Interrupt Mask Set and Clear Register 0x2C */
- u32 risr; /* Raw interrupt status register 0x30 */
- u32 misr; /* Masked interrupt status register 0x34 */
- u32 icr; /* Interrupt Set and Clear Register 0x38 */
- u32 reserved_1[(0xFE0 - 0x3c) >> 2]; /* Reserved 0x03C to 0xFE0 */
- u32 periph_id_0; /* peripheral ID 0 0xFE0 */
- u32 periph_id_1; /* peripheral ID 1 0xFE4 */
- u32 periph_id_2; /* peripheral ID 2 0xFE8 */
- u32 periph_id_3; /* peripheral ID 3 0xFEC */
- u32 cell_id_0; /* I2C cell ID 0 0xFF0 */
- u32 cell_id_1; /* I2C cell ID 1 0xFF4 */
- u32 cell_id_2; /* I2C cell ID 2 0xFF8 */
- u32 cell_id_3; /* I2C cell ID 3 0xFFC */
-};
-
-
-/* Control Register */
-
-/* Mask values for control register mask */
-#define U8500_I2C_CR_PE 0x0001 /* Peripheral enable */
-#define U8500_I2C_CR_OM 0x0006 /* Operation mode */
-#define U8500_I2C_CR_SAM 0x0008 /* Slave Addressing mode */
-#define U8500_I2C_CR_SM 0x0030 /* Speed mode */
-#define U8500_I2C_CR_SGCM 0x0040 /* Slave General call mode */
-#define U8500_I2C_CR_FTX 0x0080 /* Flush Transmit */
-#define U8500_I2C_CR_FRX 0x0100 /* Flush Receive */
-#define U8500_I2C_CR_DMA_TX_EN 0x0200 /* DMA TX Enable */
-#define U8500_I2C_CR_DMA_RX_EN 0x0400 /* DMA Rx Enable */
-#define U8500_I2C_CR_DMA_SLE 0x0800 /* DMA Synchronization Logic enable */
-#define U8500_I2C_CR_LM 0x1000 /* Loop back mode */
-#define U8500_I2C_CR_FON 0x6000 /* Filtering On */
-
-/* shift valus for control register bit fields */
-#define U8500_I2C_CR_SHIFT_PE 0 /* Peripheral enable */
-#define U8500_I2C_CR_SHIFT_OM 1 /* Operation mode */
-#define U8500_I2C_CR_SHIFT_SAM 3 /* Slave Addressing mode */
-#define U8500_I2C_CR_SHIFT_SM 4 /* Speed mode */
-#define U8500_I2C_CR_SHIFT_SGCM 6 /* Slave General call mode */
-#define U8500_I2C_CR_SHIFT_FTX 7 /* Flush Transmit */
-#define U8500_I2C_CR_SHIFT_FRX 8 /* Flush Receive */
-#define U8500_I2C_CR_SHIFT_DMA_TX_EN 9 /* DMA TX Enable */
-#define U8500_I2C_CR_SHIFT_DMA_RX_EN 10 /* DMA Rx Enable */
-#define U8500_I2C_CR_SHIFT_DMA_SLE 11 /* DMA Synch Logic enable */
-#define U8500_I2C_CR_SHIFT_LM 12 /* Loop back mode */
-#define U8500_I2C_CR_SHIFT_FON 13 /* Filtering On */
-
-/* bus operation modes */
-#define U8500_I2C_BUS_SLAVE_MODE 0
-#define U8500_I2C_BUS_MASTER_MODE 1
-#define U8500_I2C_BUS_MASTER_SLAVE_MODE 2
-
-
-/* Slave control register*/
-
-/* Mask values slave control register */
-#define U8500_I2C_SCR_ADDR 0x3FF
-#define U8500_I2C_SCR_DATA_SETUP_TIME 0xFFFF0000
-
-/* Shift values for Slave control register */
-#define U8500_I2C_SCR_SHIFT_ADDR 0
-#define U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME 16
-
-
-/* Master Control Register */
-
-/* Mask values for Master control register */
-#define U8500_I2C_MCR_OP 0x00000001 /* Operation */
-#define U8500_I2C_MCR_A7 0x000000FE /* LSB bits of Address */
-#define U8500_I2C_MCR_EA10 0x00000700 /* Extended Address */
-#define U8500_I2C_MCR_SB 0x00000800 /* Start byte procedure */
-#define U8500_I2C_MCR_AM 0x00003000 /* Address type */
-#define U8500_I2C_MCR_STOP 0x00004000 /* stop condition */
-#define U8500_I2C_MCR_LENGTH 0x03FF8000 /* Frame length */
-#define U8500_I2C_MCR_A10 0x000007FE /* Enable 10 bit address */
-/* mask for length field,stop and operation */
-#define U8500_I2C_MCR_LENGTH_STOP_OP 0x3FFC001
-
-/* Shift values for Master control values */
-#define U8500_I2C_MCR_SHIFT_OP 0 /* Operation */
-#define U8500_I2C_MCR_SHIFT_A7 1 /* LSB bits of Address */
-#define U8500_I2C_MCR_SHIFT_EA10 8 /* Extended Address */
-#define U8500_I2C_MCR_SHIFT_SB 11 /* Start byte procedure */
-#define U8500_I2C_MCR_SHIFT_AM 12 /* Address type */
-#define U8500_I2C_MCR_SHIFT_STOP 14 /* stop condition */
-#define U8500_I2C_MCR_SHIFT_LENGTH 15 /* Frame length */
-#define U8500_I2C_MCR_SHIFT_A10 1 /* Enable 10 bit address */
-
-#define U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP 0
-
-
-/* Status Register */
-
-/* Mask values for Status register */
-#define U8500_I2C_SR_OP 0x00000003 /* Operation */
-#define U8500_I2C_SR_STATUS 0x0000000C /* Controller Status */
-#define U8500_I2C_SR_CAUSE 0x00000070 /* Abort Cause */
-#define U8500_I2C_SR_TYPE 0x00000180 /* Receive Type */
-#define U8500_I2C_SR_LENGTH 0x000FF700 /* Transfer length */
-
-/* Shift values for Status register */
-#define U8500_I2C_SR_SHIFT_OP 0 /* Operation */
-#define U8500_I2C_SR_SHIFT_STATUS 2 /* Controller Status */
-#define U8500_I2C_SR_SHIFT_CAUSE 4 /* Abort Cause */
-#define U8500_I2C_SR_SHIFT_TYPE 7 /* Receive Type */
-#define U8500_I2C_SR_SHIFT_LENGTH 9 /* Transfer length */
-
-/* abort cause */
-#define U8500_I2C_NACK_ADDR 0
-#define U8500_I2C_NACK_DATA 1
-#define U8500_I2C_ACK_MCODE 2
-#define U8500_I2C_ARB_LOST 3
-#define U8500_I2C_BERR_START 4
-#define U8500_I2C_BERR_STOP 5
-#define U8500_I2C_OVFL 6
-
-
-/* Baud rate counter registers */
-
-/* Mask values for Baud rate counter register */
-#define U8500_I2C_BRCR_BRCNT2 0xFFFF /* Baud Rate Cntr BRCR for HS */
-#define U8500_I2C_BRCR_BRCNT1 0xFFFF0000 /* BRCR for Standard and Fast */
-
-/* Shift values for the Baud rate counter register */
-#define U8500_I2C_BRCR_SHIFT_BRCNT2 0
-#define U8500_I2C_BRCR_SHIFT_BRCNT1 16
-
-
-/* Interrupt Register */
-
-/* Mask values for Interrupt registers */
-#define U8500_I2C_INT_TXFE 0x00000001 /* Tx fifo empty */
-#define U8500_I2C_INT_TXFNE 0x00000002 /* Tx Fifo nearly empty */
-#define U8500_I2C_INT_TXFF 0x00000004 /* Tx Fifo Full */
-#define U8500_I2C_INT_TXFOVR 0x00000008 /* Tx Fifo over run */
-#define U8500_I2C_INT_RXFE 0x00000010 /* Rx Fifo Empty */
-#define U8500_I2C_INT_RXFNF 0x00000020 /* Rx Fifo nearly empty */
-#define U8500_I2C_INT_RXFF 0x00000040 /* Rx Fifo Full */
-#define U8500_I2C_INT_RFSR 0x00010000 /* Read From slave request */
-#define U8500_I2C_INT_RFSE 0x00020000 /* Read from slave empty */
-#define U8500_I2C_INT_WTSR 0x00040000 /* Write to Slave request */
-#define U8500_I2C_INT_MTD 0x00080000 /* Master Transcation Done*/
-#define U8500_I2C_INT_STD 0x00100000 /* Slave Transaction Done */
-#define U8500_I2C_INT_MAL 0x01000000 /* Master Arbitation Lost */
-#define U8500_I2C_INT_BERR 0x02000000 /* Bus Error */
-#define U8500_I2C_INT_MTDWS 0x10000000 /* Master Tran Done wo/ Stop */
-
-/* Max clocks (Hz) */
-#define U8500_I2C_MAX_STANDARD_SCL 100000
-#define U8500_I2C_MAX_FAST_SCL 400000
-#define U8500_I2C_MAX_HIGH_SPEED_SCL 3400000
-
-#endif /* _U8500_I2C_H_ */
provides a faster and more robust interface than I2C but the bugs
are less interesting.
-config CONFIG_FSL_SEC_MON
+config FSL_SEC_MON
bool "Enable FSL SEC_MON Driver"
help
Freescale Security Monitor block is responsible for monitoring
* (see the U_BOOT_DEVICE() declaration below) should not do anything.
* If we are that device, return an error.
*/
- if (gd->fdt_blob && dev->of_offset == -1)
+ if (state->fdt_fname && dev->of_offset == -1)
return -ENODEV;
switch (type) {
#include <common.h>
#include <errno.h>
#include <malloc.h>
+#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>
#include <asm-generic/errno.h>
if (data) {
start = get_timer(0);
- timeout = 1000;
+ timeout = 240000;
for (;;) {
mask = dwmci_readl(host, DWMCI_RINTSTS);
/* Error during data transfer. */
#include <mmc.h>
#include <part.h>
#include <malloc.h>
+#include <memalign.h>
#include <linux/list.h>
#include <div64.h>
#include "mmc_private.h"
#include <config.h>
#include <common.h>
+#include <memalign.h>
#include <mmc.h>
#include <u-boot/sha256.h>
#include "mmc_private.h"
/* determine delays */
if (hz <= 400000) {
oclk_dly = 0;
- sclk_dly = 7;
+ sclk_dly = 0;
} else if (hz <= 25000000) {
oclk_dly = 0;
sclk_dly = 5;
+#ifdef CONFIG_MACH_SUN9I
} else if (hz <= 50000000) {
- oclk_dly = 3;
- sclk_dly = 5;
+ oclk_dly = 5;
+ sclk_dly = 4;
} else {
/* hz > 50000000 */
oclk_dly = 2;
sclk_dly = 4;
+#else
+ } else if (hz <= 50000000) {
+ oclk_dly = 3;
+ sclk_dly = 4;
+ } else {
+ /* hz > 50000000 */
+ oclk_dly = 1;
+ sclk_dly = 4;
+#endif
}
writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
obj-$(CONFIG_NAND_NDFC) += ndfc.o
-obj-$(CONFIG_NAND_NOMADIK) += nomadik.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
return 0;
}
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsmc_nand_switch_ecc - switch the ECC operation between different engines
+ *
+ * @eccstrength - the number of bits that could be corrected
+ * (1 - HW, 4 - SW BCH4)
+ */
+int fsmc_nand_switch_ecc(uint32_t eccstrength)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ int err;
+
+ /*
+ * This functions is only called on SPEAr600 platforms, supporting
+ * 1 bit HW ECC. The BCH8 HW ECC (FSMC_VER8) from the ST-Ericsson
+ * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
+ * function, as it doesn't need to switch to a different ECC layout.
+ */
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ /* Setup the ecc configurations again */
+ if (eccstrength == 1) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.bytes = 3;
+ nand->ecc.strength = 1;
+ nand->ecc.layout = &fsmc_ecc1_layout;
+ nand->ecc.calculate = fsmc_read_hwecc;
+ nand->ecc.correct = nand_correct_data;
+ } else if (eccstrength == 4) {
+ /*
+ * .calculate .correct and .bytes will be set in
+ * nand_scan_tail()
+ */
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+ nand->ecc.strength = 4;
+ nand->ecc.layout = NULL;
+ } else {
+ printf("Error: ECC strength %d not supported!\n", eccstrength);
+ }
+
+ /* Update NAND handling after ECC mode switch */
+ err = nand_scan_tail(mtd);
+
+ return err;
+}
+#endif /* CONFIG_SPL_BUILD */
+
int fsmc_nand_init(struct nand_chip *nand)
{
static int chip_nr;
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
-#define BIT(x) (1 << (x))
#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
#define JZ_NAND_ECC_CTRL_RS BIT(2)
#define JZ_NAND_ECC_CTRL_RESET BIT(1)
uint32_t page_oob_size)
{
int ecc_strength;
+ int max_ecc_strength_supported;
+
+ /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
+ if (is_cpu_type(MXC_CPU_MX6SX))
+ max_ecc_strength_supported = 62;
+ else
+ max_ecc_strength_supported = 40;
/*
* Determine the ECC layout with the formula:
/ (galois_field *
mxs_nand_ecc_chunk_cnt(page_data_size));
- return round_down(ecc_strength, 2);
+ return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
}
static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
#include <command.h>
#include <watchdog.h>
#include <malloc.h>
+#include <memalign.h>
#include <div64.h>
#include <asm/errno.h>
+++ /dev/null
-/*
- * (C) Copyright 2007 STMicroelectronics, <www.st.com>
- * (C) Copyright 2009 Alessandro Rubini <rubini@unipv.it>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-
-static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */
-{
- __asm__ __volatile__(
- "eor %0, %0, %0, lsr #4\n\t"
- "eor %0, %0, %0, lsr #2\n\t"
- "eor %0, %0, %0, lsr #1\n\t"
- "ands %0, %0, #1\n\t"
- "subne %0, %0, #2\t"
- : "=r" (b) : "0" (b));
- return b;
-}
-
-/*
- * This is the ECC routine used in hardware, according to the manual.
- * HW claims to make the calculation but not the correction; so we must
- * recalculate the bytes for a comparison.
- */
-static int ecc512(const unsigned char *data, unsigned char *ecc)
-{
- int gpar = 0;
- int i, val, par;
- int pbits = 0; /* P8, P16, ... P2048 */
- int pprime = 0; /* P8', P16', ... P2048' */
- int lowbits; /* P1, P2, P4 and primes */
-
- for (i = 0; i < 512; i++) {
- par = parity((val = data[i]));
- gpar ^= val;
- pbits ^= (i & par);
- }
- /*
- * Ok, now gpar is global parity (xor of all bytes)
- * pbits are all the parity bits (non-prime ones)
- */
- par = parity(gpar);
- pprime = pbits ^ par;
- /* Put low bits in the right position for ecc[2] (bits 7..2) */
- lowbits = 0
- | (parity(gpar & 0xf0) & 0x80) /* P4 */
- | (parity(gpar & 0x0f) & 0x40) /* P4' */
- | (parity(gpar & 0xcc) & 0x20) /* P2 */
- | (parity(gpar & 0x33) & 0x10) /* P2' */
- | (parity(gpar & 0xaa) & 0x08) /* P1 */
- | (parity(gpar & 0x55) & 0x04); /* P1' */
-
- ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8));
- /* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */
- ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1)
- | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2)
- | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3)
- | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4));
-
- ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3)
- | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2)
- | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1)
- | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0));
- return 0;
-}
-
-/* This is the method in the chip->ecc field */
-static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
- uint8_t *ecc_code)
-{
- return ecc512(dat, ecc_code);
-}
-
-static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
- uint8_t *r_ecc, uint8_t *c_ecc)
-{
- struct nand_chip *chip = mtd->priv;
- uint32_t r, c, d, diff; /*read, calculated, xor of them */
-
- if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes))
- return 0;
-
- /* Reorder the bytes into ascending-order 24 bits -- see manual */
- r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2;
- c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2;
- diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */
-
- /* If 12 bits are different, one per pair, it's correctable */
- if (((diff | (diff>>1)) & 0x555555) == 0x555555) {
- int bit = ((diff & 2) >> 1)
- | ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3);
- int byte;
-
- d = diff >> 6; /* remove bit-order info */
- byte = ((d & 2) >> 1)
- | ((d & 0x8) >> 2) | ((d & 0x20) >> 3)
- | ((d & 0x80) >> 4) | ((d & 0x200) >> 5)
- | ((d & 0x800) >> 6) | ((d & 0x2000) >> 7)
- | ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9);
- /* correct the single bit */
- dat[byte] ^= 1<<bit;
- return 0;
- }
- /* If 1 bit only differs, it's one bit error in ECC, ignore */
- if ((diff ^ (1 << (ffs(diff) - 1))) == 0)
- return 0;
- /* Otherwise, uncorrectable */
- return -1;
-}
-
-static void nomadik_ecc_hwctl(struct mtd_info *mtd, int mode)
-{ /* mandatory in the structure but not used here */ }
-
-
-/* This is the layout used by older installations, we keep compatible */
-struct nand_ecclayout nomadik_ecc_layout = {
- .eccbytes = 3 * 4,
- .eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */
- 0x02, 0x03, 0x04,
- 0x12, 0x13, 0x14,
- 0x22, 0x23, 0x24,
- 0x32, 0x33, 0x34},
- .oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} },
-};
-
-#define MASK_ALE (1 << 24) /* our ALE is AD21 */
-#define MASK_CLE (1 << 23) /* our CLE is AD22 */
-
-/* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */
-static void nomadik_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- u32 pcr0 = readl(REG_FSMC_PCR0);
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- if (ctrl & NAND_NCE)
- writel(pcr0 | 0x4, REG_FSMC_PCR0);
- else
- writel(pcr0 & ~0x4, REG_FSMC_PCR0);
-
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- this->IO_ADDR_R = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */
-static int nomadik_nand_ready(struct mtd_info *mtd)
-{
- return 1; /* The ready bit is handled in hardware */
-}
-
-/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */
-static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
- u32 *p = (u32 *) buf;
-
- len >>= 2;
- writel(0, REG_FSMC_ECCR0);
- for (i = 0; i < len; i++)
- p[i] = readl(chip->IO_ADDR_R);
-}
-
-int board_nand_init(struct nand_chip *chip)
-{
- /* Set up the FSMC_PCR0 for nand access*/
- writel(0x0000004a, REG_FSMC_PCR0);
- /* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */
- writel(0x00020401, REG_FSMC_PMEM0);
- writel(0x00020404, REG_FSMC_PATT0);
-
- chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
- chip->cmd_ctrl = nomadik_nand_hwcontrol;
- chip->dev_ready = nomadik_nand_ready;
- /* The chip allows 32bit reads, so avoid the default 8bit copy */
- chip->read_buf = nomadik_nand_read_buf;
-
- /* ECC: follow the hardware-defined rulse, but do it in sw */
- chip->ecc.mode = NAND_ECC_HW;
- chip->ecc.bytes = 3;
- chip->ecc.size = 512;
- chip->ecc.strength = 1;
- chip->ecc.layout = &nomadik_ecc_layout;
- chip->ecc.calculate = nomadik_ecc_calculate;
- chip->ecc.hwctl = nomadik_ecc_hwctl;
- chip->ecc.correct = nomadik_ecc_correct;
-
- return 0;
-}
bit_pos = error_loc[count] % 8;
if (byte_pos < SECTOR_BYTES) {
dat[byte_pos] ^= 1 << bit_pos;
- printf("nand: bit-flip corrected @data=%d\n", byte_pos);
+ debug("nand: bit-flip corrected @data=%d\n", byte_pos);
} else if (byte_pos < error_max) {
read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
- printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
+ debug("nand: bit-flip corrected @oob=%d\n", byte_pos -
SECTOR_BYTES);
} else {
err = -EBADMSG;
/* correct data only, not ecc bytes */
if (errloc[i] < 8*512)
data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
- printf("corrected bitflip %u\n", errloc[i]);
+ debug("corrected bitflip %u\n", errloc[i]);
#ifdef DEBUG
puts("read_ecc: ");
/*
{ 8192, 40, 1024, 5 },
{ 16384, 56, 1024, 5 },
{ 8192, 24, 1024, 5 },
+ { 4096, 24, 1024, 5 },
};
static int nand_config = -1;
int i;
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
{
+#if CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO
+ /*
+ * u-boot-dtb.bin appended to SPL, use syndrome (like the BROM does)
+ * and try different erase block sizes to find the backup.
+ */
const uint32_t boot_offsets[] = {
0 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
1 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
2 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
4 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS,
};
- int i, syndrome;
-
- if (CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO)
- syndrome = 1; /* u-boot-dtb.bin appended to SPL */
- else
- syndrome = 0; /* u-boot-dtb.bin on its own partition */
+ const int syndrome = 1;
+#else
+ /*
+ * u-boot-dtb.bin on its own partition, do not use syndrome, u-boot
+ * partition sits after 2 eraseblocks (spl, spl-backup), look for
+ * backup u-boot 1 erase block further.
+ */
+ const uint32_t eraseblock_size = CONFIG_SYS_NAND_U_BOOT_OFFS / 2;
+ const uint32_t boot_offsets[] = {
+ CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_OFFS + eraseblock_size,
+ };
+ const int syndrome = 0;
+#endif
+ int i;
if (offs == CONFIG_SYS_NAND_U_BOOT_OFFS) {
for (i = 0; i < ARRAY_SIZE(boot_offsets); i++) {
#include <common.h>
#include <asm/io.h>
+#include <memalign.h>
#include <nand.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
{"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
{"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
{"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
+ {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
{"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
+#include <pci.h>
#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
return _dw_write_hwaddr(priv, pdata->enetaddr);
}
+static int designware_eth_bind(struct udevice *dev)
+{
+#ifdef CONFIG_DM_PCI
+ static int num_cards;
+ char name[20];
+
+ /* Create a unique device name for PCI type devices */
+ if (device_is_on_pci_bus(dev)) {
+ sprintf(name, "eth_designware#%u", num_cards++);
+ device_set_name(dev, name);
+ }
+#endif
+
+ return 0;
+}
+
static int designware_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
u32 iobase = pdata->iobase;
int ret;
+#ifdef CONFIG_DM_PCI
+ /*
+ * If we are on PCI bus, either directly attached to a PCI root port,
+ * or via a PCI bridge, fill in platdata before we probe the hardware.
+ */
+ if (device_is_on_pci_bus(dev)) {
+ pci_dev_t bdf = pci_get_bdf(dev);
+
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
+ iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+ iobase = pci_mem_to_phys(bdf, iobase);
+
+ pdata->iobase = iobase;
+ pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
+ }
+#endif
+
debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
priv->mac_regs_p = (struct eth_mac_regs *)iobase;
priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
.id = UCLASS_ETH,
.of_match = designware_eth_ids,
.ofdata_to_platdata = designware_eth_ofdata_to_platdata,
+ .bind = designware_eth_bind,
.probe = designware_eth_probe,
.ops = &designware_eth_ops,
.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+
+static struct pci_device_id supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
+ { }
+};
+
+U_BOOT_PCI_DEVICE(eth_designware, supported);
#endif
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <memalign.h>
#include <pci.h>
#include "e1000.h"
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
static void nc_send_packet(const char *buf, int len)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *eth;
+#else
struct eth_device *eth;
+#endif
int inited = 0;
uchar *pkt;
uchar *ether;
return;
if (!memcmp(nc_ether, net_null_ethaddr, 6)) {
- if (eth->state == ETH_STATE_ACTIVE)
+ if (eth_is_active(eth))
return; /* inside net loop */
output_packet = buf;
output_packet_len = len;
return;
}
- if (eth->state != ETH_STATE_ACTIVE) {
+ if (!eth_is_active(eth)) {
if (eth_is_on_demand_init()) {
if (eth_init() < 0)
return;
static int nc_stdio_tstc(struct stdio_dev *dev)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *eth;
+#else
struct eth_device *eth;
+#endif
if (input_recursion)
return 0;
return 1;
eth = eth_get_dev();
- if (eth && eth->state == ETH_STATE_ACTIVE)
+ if (eth_is_active(eth))
return 0; /* inside net loop */
input_recursion = 1;
memset(dev, 0, sizeof(*dev));
dev->duplex = -1;
- dev->link = 1;
+ dev->link = 0;
dev->interface = interface;
dev->autoneg = AUTONEG_ENABLE;
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <memalign.h>
#include <net.h>
#ifndef CONFIG_DM_ETH
#include <netdev.h>
}
/* we have a packet address, so tell the card to use it */
-#ifndef CONFIG_XAENIAX
SMC_outb (dev, packet_no, PN_REG);
-#else
- /* On Xaeniax board, we can't use SMC_outb here because that way
- * the Allocate MMU command will end up written to the command register
- * as well, which will lead to a problem.
- */
- SMC_outl (dev, packet_no << 16, 0);
-#endif
+
/* do not write new ptr value if Write data fifo not empty */
while ( saved_ptr & PTR_NOTEMPTY )
printf ("Write data fifo not empty!\n");
*/
#ifdef USE_32_BIT
SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
-#ifndef CONFIG_XAENIAX
if (length & 0x2)
SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
SMC91111_DATA_REG);
-#else
- /* On XANEIAX, we can only use 32-bit writes, so we need to handle
- * unaligned tail part specially. The standard code doesn't work.
- */
- if ((length & 3) == 3) {
- u16 * ptr = (u16*) &buf[length-3];
- SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
- SMC91111_DATA_REG);
- } else if ((length & 2) == 2) {
- u16 * ptr = (u16*) &buf[length-2];
- SMC_outl(dev, *ptr, SMC91111_DATA_REG);
- } else if (length & 1) {
- SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
- } else {
- SMC_outl(dev, 0, SMC91111_DATA_REG);
- }
-#endif
#else
SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
#endif /* USE_32_BIT */
-#ifndef CONFIG_XAENIAX
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
SMC_outw (dev, 0, SMC91111_DATA_REG);
} else {
SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
}
-#endif
/* and let the chipset deal with it */
SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
/* release packet */
/* no need to release, MMU does that now */
-#ifdef CONFIG_XAENIAX
- SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
-#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
/* release packet */
/* no need to release, MMU does that now */
-#ifdef CONFIG_XAENIAX
- SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
-#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
}
/* restore previously saved registers */
-#ifndef CONFIG_XAENIAX
SMC_outb( dev, saved_pnr, PN_REG );
-#else
- /* On Xaeniax board, we can't use SMC_outb here because that way
- * the Allocate MMU command will end up written to the command register
- * as well, which will lead to a problem.
- */
- SMC_outl(dev, saved_pnr << 16, 0);
-#endif
SMC_outw( dev, saved_ptr, PTR_REG );
return length;
udelay(1); /* Wait until not busy */
/* restore saved registers */
-#ifndef CONFIG_XAENIAX
SMC_outb( dev, saved_pnr, PN_REG );
-#else
- /* On Xaeniax board, we can't use SMC_outb here because that way
- * the Allocate MMU command will end up written to the command register
- * as well, which will lead to a problem.
- */
- SMC_outl( dev, saved_pnr << 16, 0);
-#endif
SMC_outw( dev, saved_ptr, PTR_REG );
if (!is_error) {
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
-#elif defined(CONFIG_XAENIAX)
-#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
-#define SMC_inw(a,z) ({ \
- unsigned int __p = (unsigned int)((a)->iobase + (z)); \
- unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
- if (__p & 3) __v >>= 16; \
- else __v &= 0xffff; \
- __v; })
-#define SMC_inb(a,p) ({ \
- unsigned int ___v = SMC_inw((a),(p) & ~1); \
- if ((p) & 1) ___v >>= 8; \
- else ___v &= 0xff; \
- ___v; })
#else
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
#ifdef CONFIG_XSENGINE
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
-#elif defined (CONFIG_XAENIAX)
-#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
-#define SMC_outw(a,d,p) ({ \
- dword __dwo = SMC_inl((a),(p) & ~3); \
- dword __dwn = (word)(d); \
- __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
- __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
- SMC_outl((a), __dwo, (p) & ~3); \
-})
#else
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_memac.h>
+#include <bitfield.h>
+#include <errno.h>
+#include <malloc.h>
#include <vsc9953.h>
+#include <ethsw.h>
static struct vsc9953_info vsc9953_l2sw = {
.port[0] = VSC9953_PORT_INFO_INITIALIZER(0),
.port[9] = VSC9953_PORT_INFO_INITIALIZER(9),
};
-void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus)
+void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus)
{
- if (!VSC9953_PORT_CHECK(port))
+ if (!VSC9953_PORT_CHECK(port_no))
return;
- vsc9953_l2sw.port[port].bus = bus;
+ vsc9953_l2sw.port[port_no].bus = bus;
}
-void vsc9953_port_info_set_phy_address(int port, int address)
+void vsc9953_port_info_set_phy_address(int port_no, int address)
{
- if (!VSC9953_PORT_CHECK(port))
+ if (!VSC9953_PORT_CHECK(port_no))
return;
- vsc9953_l2sw.port[port].phyaddr = address;
+ vsc9953_l2sw.port[port_no].phyaddr = address;
}
-void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int)
+void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int)
{
- if (!VSC9953_PORT_CHECK(port))
+ if (!VSC9953_PORT_CHECK(port_no))
return;
- vsc9953_l2sw.port[port].enet_if = phy_int;
+ vsc9953_l2sw.port[port_no].enet_if = phy_int;
}
-void vsc9953_port_enable(int port)
+void vsc9953_port_enable(int port_no)
{
- if (!VSC9953_PORT_CHECK(port))
+ if (!VSC9953_PORT_CHECK(port_no))
return;
- vsc9953_l2sw.port[port].enabled = 1;
+ vsc9953_l2sw.port[port_no].enabled = 1;
}
-void vsc9953_port_disable(int port)
+void vsc9953_port_disable(int port_no)
{
- if (!VSC9953_PORT_CHECK(port))
+ if (!VSC9953_PORT_CHECK(port_no))
return;
- vsc9953_l2sw.port[port].enabled = 0;
+ vsc9953_l2sw.port[port_no].enabled = 0;
}
static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr,
int regnum, int value)
{
- int timeout = 50000;
+ int timeout = 50000;
out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr,
int regnum)
{
- int value = 0xFFFF;
- int timeout = 50000;
+ int value = 0xFFFF;
+ int timeout = 50000;
while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout)
udelay(1);
static int init_phy(struct eth_device *dev)
{
- struct vsc9953_port_info *l2sw_port = dev->priv;
- struct phy_device *phydev = NULL;
+ struct vsc9953_port_info *l2sw_port = dev->priv;
+ struct phy_device *phydev = NULL;
#ifdef CONFIG_PHYLIB
if (!l2sw_port->bus)
return 0;
}
-static int vsc9953_port_init(int port)
+static int vsc9953_port_init(int port_no)
{
- struct eth_device *dev;
+ struct eth_device *dev;
/* Internal ports never have a PHY */
- if (VSC9953_INTERNAL_PORT_CHECK(port))
+ if (VSC9953_INTERNAL_PORT_CHECK(port_no))
return 0;
/* alloc eth device */
dev = (struct eth_device *)calloc(1, sizeof(struct eth_device));
if (!dev)
- return 1;
+ return -ENOMEM;
- sprintf(dev->name, "SW@PORT%d", port);
- dev->priv = &vsc9953_l2sw.port[port];
+ sprintf(dev->name, "SW@PORT%d", port_no);
+ dev->priv = &vsc9953_l2sw.port[port_no];
dev->init = NULL;
dev->halt = NULL;
dev->send = NULL;
if (init_phy(dev)) {
free(dev);
- return 1;
+ return -ENODEV;
}
return 0;
}
+static int vsc9953_vlan_table_poll_idle(void)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+ int timeout;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ timeout = 50000;
+ while (((in_le32(&l2ana_reg->ana_tables.vlan_access) &
+ VSC9953_VLAN_CMD_MASK) != VSC9953_VLAN_CMD_IDLE) && --timeout)
+ udelay(1);
+
+ return timeout ? 0 : -EBUSY;
+}
+
+#ifdef CONFIG_CMD_ETHSW
+/* Add/remove a port to/from a VLAN */
+static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+
+ val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
+ val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid);
+ out_le32(&l2ana_reg->ana_tables.vlan_tidx, val);
+
+ clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
+ VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ);
+
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+
+ val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
+ val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid);
+ out_le32(&l2ana_reg->ana_tables.vlan_tidx, val);
+
+ val = in_le32(&l2ana_reg->ana_tables.vlan_access);
+ if (!add) {
+ val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK,
+ VSC9953_VLAN_CMD_WRITE) &
+ ~(bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK,
+ (1 << port_no)));
+ ;
+ } else {
+ val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK,
+ VSC9953_VLAN_CMD_WRITE) |
+ bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK,
+ (1 << port_no));
+ }
+ out_le32(&l2ana_reg->ana_tables.vlan_access, val);
+
+ /* wait for VLAN table command to flush */
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+}
+
+/* show VLAN membership for a port */
+static void vsc9953_vlan_membership_show(int port_no)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+ u32 vid;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ printf("Port %d VLAN membership: ", port_no);
+
+ for (vid = 0; vid < VSC9953_MAX_VLAN; vid++) {
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+
+ val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
+ val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK,
+ vid);
+ out_le32(&l2ana_reg->ana_tables.vlan_tidx, val);
+
+ clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
+ VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ);
+
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+
+ val = in_le32(&l2ana_reg->ana_tables.vlan_access);
+
+ if (bitfield_extract_by_mask(val, VSC9953_VLAN_PORT_MASK) &
+ (1 << port_no))
+ printf("%d ", vid);
+ }
+ printf("\n");
+}
+#endif
+
+/* vlan table set/clear all membership of vid */
+static void vsc9953_vlan_table_membership_all_set(int vid, int set_member)
+{
+ uint val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+
+ /* read current vlan configuration */
+ val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
+ out_le32(&l2ana_reg->ana_tables.vlan_tidx,
+ bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid));
+
+ clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
+ VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ);
+
+ if (vsc9953_vlan_table_poll_idle() < 0) {
+ debug("VLAN table timeout\n");
+ return;
+ }
+
+ val = in_le32(&l2ana_reg->ana_tables.vlan_tidx);
+ out_le32(&l2ana_reg->ana_tables.vlan_tidx,
+ bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid));
+
+ clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access,
+ VSC9953_VLAN_PORT_MASK | VSC9953_VLAN_CMD_MASK,
+ VSC9953_VLAN_CMD_WRITE |
+ (set_member ? VSC9953_VLAN_PORT_MASK : 0));
+}
+
+#ifdef CONFIG_CMD_ETHSW
+/* Get PVID of a VSC9953 port */
+static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ /* Administrative down */
+ if (vsc9953_l2sw.port[port_nr].enabled) {
+ printf("Port %d is administrative down\n", port_nr);
+ return -1;
+ }
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ /* Get ingress PVID */
+ val = in_le32(&l2ana_reg->port[port_nr].vlan_cfg);
+ *pvid = bitfield_extract_by_mask(val, VSC9953_VLAN_CFG_VID_MASK);
+
+ return 0;
+}
+#endif
+
+/* Set PVID for a VSC9953 port */
+static void vsc9953_port_vlan_pvid_set(int port_no, int pvid)
+{
+ uint val;
+ struct vsc9953_analyzer *l2ana_reg;
+ struct vsc9953_rew_reg *l2rew_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+ l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
+ VSC9953_REW_OFFSET);
+
+ /* Set PVID on ingress */
+ val = in_le32(&l2ana_reg->port[port_no].vlan_cfg);
+ val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_VID_MASK, pvid);
+ out_le32(&l2ana_reg->port[port_no].vlan_cfg, val);
+
+ /* Set PVID on egress */
+ val = in_le32(&l2rew_reg->port[port_no].port_vlan_cfg);
+ val = bitfield_replace_by_mask(val, VSC9953_PORT_VLAN_CFG_VID_MASK,
+ pvid);
+ out_le32(&l2rew_reg->port[port_no].port_vlan_cfg, val);
+}
+
+static void vsc9953_port_all_vlan_pvid_set(int pvid)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_pvid_set(i, pvid);
+}
+
+/* Enable/disable vlan aware of a VSC9953 port */
+static void vsc9953_port_vlan_aware_set(int port_no, int enabled)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ if (enabled)
+ setbits_le32(&l2ana_reg->port[port_no].vlan_cfg,
+ VSC9953_VLAN_CFG_AWARE_ENA);
+ else
+ clrbits_le32(&l2ana_reg->port[port_no].vlan_cfg,
+ VSC9953_VLAN_CFG_AWARE_ENA);
+}
+
+/* Set all VSC9953 ports' vlan aware */
+static void vsc9953_port_all_vlan_aware_set(int enabled)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_aware_set(i, enabled);
+}
+
+/* Enable/disable vlan pop count of a VSC9953 port */
+static void vsc9953_port_vlan_popcnt_set(int port_no, int popcnt)
+{
+ uint val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ if (popcnt > 3 || popcnt < 0) {
+ printf("Invalid pop count value: %d\n", port_no);
+ return;
+ }
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ val = in_le32(&l2ana_reg->port[port_no].vlan_cfg);
+ val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_POP_CNT_MASK,
+ popcnt);
+ out_le32(&l2ana_reg->port[port_no].vlan_cfg, val);
+}
+
+/* Set all VSC9953 ports' pop count */
+static void vsc9953_port_all_vlan_poncnt_set(int popcnt)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_popcnt_set(i, popcnt);
+}
+
+/* Enable/disable learning for frames dropped due to ingress filtering */
+static void vsc9953_vlan_ingr_fltr_learn_drop(int enable)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ if (enable)
+ setbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK);
+ else
+ clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK);
+}
+
+/* Egress untag modes of a VSC9953 port */
+enum egress_untag_mode {
+ EGRESS_UNTAG_ALL = 0,
+ EGRESS_UNTAG_PVID_AND_ZERO,
+ EGRESS_UNTAG_ZERO,
+ EGRESS_UNTAG_NONE,
+};
+
+#ifdef CONFIG_CMD_ETHSW
+/* Get egress tagging configuration for a VSC9953 port */
+static int vsc9953_port_vlan_egr_untag_get(int port_no,
+ enum egress_untag_mode *mode)
+{
+ u32 val;
+ struct vsc9953_rew_reg *l2rew_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return -1;
+ }
+
+ l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
+ VSC9953_REW_OFFSET);
+
+ val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg);
+
+ switch (val & VSC9953_TAG_CFG_MASK) {
+ case VSC9953_TAG_CFG_NONE:
+ *mode = EGRESS_UNTAG_ALL;
+ return 0;
+ case VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO:
+ *mode = EGRESS_UNTAG_PVID_AND_ZERO;
+ return 0;
+ case VSC9953_TAG_CFG_ALL_BUT_ZERO:
+ *mode = EGRESS_UNTAG_ZERO;
+ return 0;
+ case VSC9953_TAG_CFG_ALL:
+ *mode = EGRESS_UNTAG_NONE;
+ return 0;
+ default:
+ printf("Unknown egress tagging configuration for port %d\n",
+ port_no);
+ return -1;
+ }
+}
+
+/* Show egress tagging configuration for a VSC9953 port */
+static void vsc9953_port_vlan_egr_untag_show(int port_no)
+{
+ enum egress_untag_mode mode;
+
+ if (vsc9953_port_vlan_egr_untag_get(port_no, &mode)) {
+ printf("%7d\t%17s\n", port_no, "-");
+ return;
+ }
+
+ printf("%7d\t", port_no);
+ switch (mode) {
+ case EGRESS_UNTAG_ALL:
+ printf("%17s\n", "all");
+ break;
+ case EGRESS_UNTAG_NONE:
+ printf("%17s\n", "none");
+ break;
+ case EGRESS_UNTAG_PVID_AND_ZERO:
+ printf("%17s\n", "PVID and 0");
+ break;
+ case EGRESS_UNTAG_ZERO:
+ printf("%17s\n", "0");
+ break;
+ default:
+ printf("%17s\n", "-");
+ }
+}
+#endif
+
+static void vsc9953_port_vlan_egr_untag_set(int port_no,
+ enum egress_untag_mode mode)
+{
+ struct vsc9953_rew_reg *l2rew_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
+ VSC9953_REW_OFFSET);
+
+ switch (mode) {
+ case EGRESS_UNTAG_ALL:
+ clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
+ VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_NONE);
+ break;
+ case EGRESS_UNTAG_PVID_AND_ZERO:
+ clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
+ VSC9953_TAG_CFG_MASK,
+ VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO);
+ break;
+ case EGRESS_UNTAG_ZERO:
+ clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
+ VSC9953_TAG_CFG_MASK,
+ VSC9953_TAG_CFG_ALL_BUT_ZERO);
+ break;
+ case EGRESS_UNTAG_NONE:
+ clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
+ VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_ALL);
+ break;
+ default:
+ printf("Unknown untag mode for port %d\n", port_no);
+ }
+}
+
+static void vsc9953_port_all_vlan_egress_untagged_set(
+ enum egress_untag_mode mode)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_egr_untag_set(i, mode);
+}
+
+#ifdef CONFIG_CMD_ETHSW
+
+/* Enable/disable status of a VSC9953 port */
+static void vsc9953_port_status_set(int port_no, u8 enabled)
+{
+ struct vsc9953_qsys_reg *l2qsys_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled)
+ return;
+
+ l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
+ VSC9953_QSYS_OFFSET);
+
+ if (enabled)
+ setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no],
+ VSC9953_PORT_ENA);
+ else
+ clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no],
+ VSC9953_PORT_ENA);
+}
+
+/* Start autonegotiation for a VSC9953 PHY */
+static void vsc9953_phy_autoneg(int port_no)
+{
+ if (!vsc9953_l2sw.port[port_no].phydev)
+ return;
+
+ if (vsc9953_l2sw.port[port_no].phydev->drv->startup(
+ vsc9953_l2sw.port[port_no].phydev))
+ printf("Failed to start PHY for port %d\n", port_no);
+}
+
+/* Print a VSC9953 port's configuration */
+static void vsc9953_port_config_show(int port_no)
+{
+ int speed;
+ int duplex;
+ int link;
+ u8 enabled;
+ u32 val;
+ struct vsc9953_qsys_reg *l2qsys_reg;
+
+ l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
+ VSC9953_QSYS_OFFSET);
+
+ val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]);
+ enabled = vsc9953_l2sw.port[port_no].enabled &&
+ (val & VSC9953_PORT_ENA);
+
+ /* internal ports (8 and 9) are fixed */
+ if (VSC9953_INTERNAL_PORT_CHECK(port_no)) {
+ link = 1;
+ speed = SPEED_2500;
+ duplex = DUPLEX_FULL;
+ } else {
+ if (vsc9953_l2sw.port[port_no].phydev) {
+ link = vsc9953_l2sw.port[port_no].phydev->link;
+ speed = vsc9953_l2sw.port[port_no].phydev->speed;
+ duplex = vsc9953_l2sw.port[port_no].phydev->duplex;
+ } else {
+ link = -1;
+ speed = -1;
+ duplex = -1;
+ }
+ }
+
+ printf("%8d ", port_no);
+ printf("%8s ", enabled == 1 ? "enabled" : "disabled");
+ printf("%8s ", link == 1 ? "up" : "down");
+
+ switch (speed) {
+ case SPEED_10:
+ printf("%8d ", 10);
+ break;
+ case SPEED_100:
+ printf("%8d ", 100);
+ break;
+ case SPEED_1000:
+ printf("%8d ", 1000);
+ break;
+ case SPEED_2500:
+ printf("%8d ", 2500);
+ break;
+ case SPEED_10000:
+ printf("%8d ", 10000);
+ break;
+ default:
+ printf("%8s ", "-");
+ }
+
+ printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half");
+}
+
+/* Show VSC9953 ports' statistics */
+static void vsc9953_port_statistics_show(int port_no)
+{
+ u32 rx_val;
+ u32 tx_val;
+ struct vsc9953_system_reg *l2sys_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
+ VSC9953_SYS_OFFSET);
+
+ printf("Statistics for L2 Switch port %d:\n", port_no);
+
+ /* Set counter view for our port */
+ out_le32(&l2sys_reg->sys.stat_cfg, port_no);
+
+#define VSC9953_STATS_PRINTF "%-15s %10u"
+
+ /* Get number of Rx and Tx frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx frames:", rx_val, "Tx frames:", tx_val);
+
+ /* Get number of Rx and Tx bytes */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_oct);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_oct);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx bytes:", rx_val, "Tx bytes:", tx_val);
+
+ /* Get number of Rx frames received ok and Tx frames sent ok */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_0) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_1) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_2) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_3) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_4) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_5) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_6) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_7) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_0) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_1) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_2) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_3) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_4) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_5) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_6) +
+ in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_7);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx frames ok:", rx_val, "Tx frames ok:", tx_val);
+
+ /* Get number of Rx and Tx unicast frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_uc);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_uc);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx unicast:", rx_val, "Tx unicast:", tx_val);
+
+ /* Get number of Rx and Tx broadcast frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_bc);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_bc);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx broadcast:", rx_val, "Tx broadcast:", tx_val);
+
+ /* Get number of Rx and Tx frames of 64B */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx 64B:", rx_val, "Tx 64B:", tx_val);
+
+ /* Get number of Rx and Tx frames with sizes between 65B and 127B */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx 65B-127B:", rx_val, "Tx 65B-127B:", tx_val);
+
+ /* Get number of Rx and Tx frames with sizes between 128B and 255B */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx 128B-255B:", rx_val, "Tx 128B-255B:", tx_val);
+
+ /* Get number of Rx and Tx frames with sizes between 256B and 511B */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx 256B-511B:", rx_val, "Tx 256B-511B:", tx_val);
+
+ /* Get number of Rx and Tx frames with sizes between 512B and 1023B */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx 512B-1023B:", rx_val, "Tx 512B-1023B:", tx_val);
+
+ /* Get number of Rx and Tx frames with sizes between 1024B and 1526B */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx 1024B-1526B:", rx_val, "Tx 1024B-1526B:", tx_val);
+
+ /* Get number of Rx and Tx jumbo frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx jumbo:", rx_val, "Tx jumbo:", tx_val);
+
+ /* Get number of Rx and Tx dropped frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_tail) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_0) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_1) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_2) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_3) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_4) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_5) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_6) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_7) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_0) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_1) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_2) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_3) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_4) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_5) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_6) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_7);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_drop) +
+ in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx drops:", rx_val, "Tx drops:", tx_val);
+
+ /*
+ * Get number of Rx frames with CRC or alignment errors
+ * and number of detected Tx collisions
+ */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_crc);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_col);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx CRC&align:", rx_val, "Tx coll:", tx_val);
+
+ /*
+ * Get number of Rx undersized frames and
+ * number of Tx aged frames
+ */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short);
+ tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged);
+ printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n",
+ "Rx undersize:", rx_val, "Tx aged:", tx_val);
+
+ /* Get number of Rx oversized frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long);
+ printf(VSC9953_STATS_PRINTF"\n", "Rx oversized:", rx_val);
+
+ /* Get number of Rx fragmented frames */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag);
+ printf(VSC9953_STATS_PRINTF"\n", "Rx fragments:", rx_val);
+
+ /* Get number of Rx jabber errors */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber);
+ printf(VSC9953_STATS_PRINTF"\n", "Rx jabbers:", rx_val);
+
+ /*
+ * Get number of Rx frames filtered due to classification rules or
+ * no destination ports
+ */
+ rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) +
+ in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_local);
+ printf(VSC9953_STATS_PRINTF"\n", "Rx filtered:", rx_val);
+
+ printf("\n");
+}
+
+/* Clear statistics for a VSC9953 port */
+static void vsc9953_port_statistics_clear(int port_no)
+{
+ struct vsc9953_system_reg *l2sys_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
+ VSC9953_SYS_OFFSET);
+
+ /* Clear all counter groups for our ports */
+ out_le32(&l2sys_reg->sys.stat_cfg, port_no |
+ VSC9953_STAT_CLEAR_RX | VSC9953_STAT_CLEAR_TX |
+ VSC9953_STAT_CLEAR_DR);
+}
+
+enum port_learn_mode {
+ PORT_LEARN_NONE,
+ PORT_LEARN_AUTO
+};
+
+/* Set learning configuration for a VSC9953 port */
+static void vsc9953_port_learn_mode_set(int port_no, enum port_learn_mode mode)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return;
+ }
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ switch (mode) {
+ case PORT_LEARN_NONE:
+ clrbits_le32(&l2ana_reg->port[port_no].port_cfg,
+ VSC9953_PORT_CFG_LEARN_DROP |
+ VSC9953_PORT_CFG_LEARN_CPU |
+ VSC9953_PORT_CFG_LEARN_AUTO |
+ VSC9953_PORT_CFG_LEARN_ENA);
+ break;
+ case PORT_LEARN_AUTO:
+ clrsetbits_le32(&l2ana_reg->port[port_no].port_cfg,
+ VSC9953_PORT_CFG_LEARN_DROP |
+ VSC9953_PORT_CFG_LEARN_CPU,
+ VSC9953_PORT_CFG_LEARN_ENA |
+ VSC9953_PORT_CFG_LEARN_AUTO);
+ break;
+ default:
+ printf("Unknown learn mode for port %d\n", port_no);
+ }
+}
+
+/* Get learning configuration for a VSC9953 port */
+static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ /* Administrative down */
+ if (!vsc9953_l2sw.port[port_no].enabled) {
+ printf("Port %d is administrative down\n", port_no);
+ return -1;
+ }
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ /* For now we only support HW learning (auto) and no learning */
+ val = in_le32(&l2ana_reg->port[port_no].port_cfg);
+ if ((val & (VSC9953_PORT_CFG_LEARN_ENA |
+ VSC9953_PORT_CFG_LEARN_AUTO)) ==
+ (VSC9953_PORT_CFG_LEARN_ENA | VSC9953_PORT_CFG_LEARN_AUTO))
+ *mode = PORT_LEARN_AUTO;
+ else
+ *mode = PORT_LEARN_NONE;
+
+ return 0;
+}
+
+/* wait for FDB to become available */
+static int vsc9953_mac_table_poll_idle(void)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+ u32 timeout;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ timeout = 50000;
+ while (((in_le32(&l2ana_reg->ana_tables.mac_access) &
+ VSC9953_MAC_CMD_MASK) !=
+ VSC9953_MAC_CMD_IDLE) && --timeout)
+ udelay(1);
+
+ return timeout ? 0 : -EBUSY;
+}
+
+/* enum describing available commands for the MAC table */
+enum mac_table_cmd {
+ MAC_TABLE_READ,
+ MAC_TABLE_LOOKUP,
+ MAC_TABLE_WRITE,
+ MAC_TABLE_LEARN,
+ MAC_TABLE_FORGET,
+ MAC_TABLE_GET_NEXT,
+ MAC_TABLE_AGE,
+};
+
+/* Issues a command to the FDB table */
+static int vsc9953_mac_table_cmd(enum mac_table_cmd cmd)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ switch (cmd) {
+ case MAC_TABLE_READ:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK | VSC9953_MAC_CMD_VALID,
+ VSC9953_MAC_CMD_READ);
+ break;
+ case MAC_TABLE_LOOKUP:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK, VSC9953_MAC_CMD_READ |
+ VSC9953_MAC_CMD_VALID);
+ break;
+ case MAC_TABLE_WRITE:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK |
+ VSC9953_MAC_ENTRYTYPE_MASK,
+ VSC9953_MAC_CMD_WRITE |
+ VSC9953_MAC_ENTRYTYPE_LOCKED);
+ break;
+ case MAC_TABLE_LEARN:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK |
+ VSC9953_MAC_ENTRYTYPE_MASK,
+ VSC9953_MAC_CMD_LEARN |
+ VSC9953_MAC_ENTRYTYPE_LOCKED |
+ VSC9953_MAC_CMD_VALID);
+ break;
+ case MAC_TABLE_FORGET:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK |
+ VSC9953_MAC_ENTRYTYPE_MASK,
+ VSC9953_MAC_CMD_FORGET);
+ break;
+ case MAC_TABLE_GET_NEXT:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK |
+ VSC9953_MAC_ENTRYTYPE_MASK,
+ VSC9953_MAC_CMD_NEXT);
+ break;
+ case MAC_TABLE_AGE:
+ clrsetbits_le32(&l2ana_reg->ana_tables.mac_access,
+ VSC9953_MAC_CMD_MASK |
+ VSC9953_MAC_ENTRYTYPE_MASK,
+ VSC9953_MAC_CMD_AGE);
+ break;
+ default:
+ printf("Unknown MAC table command\n");
+ }
+
+ if (vsc9953_mac_table_poll_idle() < 0) {
+ debug("MAC table timeout\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* show the FDB entries that correspond to a port and a VLAN */
+static void vsc9953_mac_table_show(int port_no, int vid)
+{
+ int rc[VSC9953_MAX_PORTS];
+ enum port_learn_mode mode[VSC9953_MAX_PORTS];
+ int i;
+ u32 val;
+ u32 vlan;
+ u32 mach;
+ u32 macl;
+ u32 dest_indx;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ /* disable auto learning */
+ if (port_no == ETHSW_CMD_PORT_ALL) {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]);
+ if (!rc[i] && mode[i] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE);
+ }
+ } else {
+ rc[port_no] = vsc9953_port_learn_mode_get(port_no,
+ &mode[port_no]);
+ if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE);
+ }
+
+ /* write port and vid to get selected FDB entries */
+ val = in_le32(&l2ana_reg->ana.anag_efil);
+ if (port_no != ETHSW_CMD_PORT_ALL) {
+ val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK,
+ port_no) | VSC9953_AGE_PORT_EN;
+ }
+ if (vid != ETHSW_CMD_VLAN_ALL) {
+ val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK,
+ vid) | VSC9953_AGE_VID_EN;
+ }
+ out_le32(&l2ana_reg->ana.anag_efil, val);
+
+ /* set MAC and VLAN to 0 to look from beginning */
+ clrbits_le32(&l2ana_reg->ana_tables.mach_data,
+ VSC9953_MAC_VID_MASK | VSC9953_MAC_MACH_MASK);
+ out_le32(&l2ana_reg->ana_tables.macl_data, 0);
+
+ /* get entries */
+ printf("%10s %17s %5s %4s\n", "EntryType", "MAC", "PORT", "VID");
+ do {
+ if (vsc9953_mac_table_cmd(MAC_TABLE_GET_NEXT) < 0) {
+ debug("GET NEXT MAC table command failed\n");
+ break;
+ }
+
+ val = in_le32(&l2ana_reg->ana_tables.mac_access);
+
+ /* get out when an invalid entry is found */
+ if (!(val & VSC9953_MAC_CMD_VALID))
+ break;
+
+ switch (val & VSC9953_MAC_ENTRYTYPE_MASK) {
+ case VSC9953_MAC_ENTRYTYPE_NORMAL:
+ printf("%10s ", "Dynamic");
+ break;
+ case VSC9953_MAC_ENTRYTYPE_LOCKED:
+ printf("%10s ", "Static");
+ break;
+ case VSC9953_MAC_ENTRYTYPE_IPV4MCAST:
+ printf("%10s ", "IPv4 Mcast");
+ break;
+ case VSC9953_MAC_ENTRYTYPE_IPV6MCAST:
+ printf("%10s ", "IPv6 Mcast");
+ break;
+ default:
+ printf("%10s ", "Unknown");
+ }
+
+ dest_indx = bitfield_extract_by_mask(val,
+ VSC9953_MAC_DESTIDX_MASK);
+
+ val = in_le32(&l2ana_reg->ana_tables.mach_data);
+ vlan = bitfield_extract_by_mask(val, VSC9953_MAC_VID_MASK);
+ mach = bitfield_extract_by_mask(val, VSC9953_MAC_MACH_MASK);
+ macl = in_le32(&l2ana_reg->ana_tables.macl_data);
+
+ printf("%02x:%02x:%02x:%02x:%02x:%02x ", (mach >> 8) & 0xff,
+ mach & 0xff, (macl >> 24) & 0xff, (macl >> 16) & 0xff,
+ (macl >> 8) & 0xff, macl & 0xff);
+ printf("%5d ", dest_indx);
+ printf("%4d\n", vlan);
+ } while (1);
+
+ /* set learning mode to previous value */
+ if (port_no == ETHSW_CMD_PORT_ALL) {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ if (!rc[i] && mode[i] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(i, mode[i]);
+ }
+ } else {
+ /* If administrative down, skip */
+ if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(port_no, mode[port_no]);
+ }
+
+ /* reset FDB port and VLAN FDB selection */
+ clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN |
+ VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN |
+ VSC9953_AGE_VID_MASK);
+}
+
+/* Add a static FDB entry */
+static int vsc9953_mac_table_add(u8 port_no, uchar mac[6], int vid)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ val = in_le32(&l2ana_reg->ana_tables.mach_data);
+ val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
+ (mac[0] << 8) | (mac[1] << 0);
+ out_le32(&l2ana_reg->ana_tables.mach_data, val);
+
+ out_le32(&l2ana_reg->ana_tables.macl_data,
+ (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) |
+ (mac[5] << 0));
+
+ /* set on which port is the MAC address added */
+ val = in_le32(&l2ana_reg->ana_tables.mac_access);
+ val = bitfield_replace_by_mask(val, VSC9953_MAC_DESTIDX_MASK, port_no);
+ out_le32(&l2ana_reg->ana_tables.mac_access, val);
+
+ if (vsc9953_mac_table_cmd(MAC_TABLE_LEARN) < 0)
+ return -1;
+
+ /* check if the MAC address was indeed added */
+ val = in_le32(&l2ana_reg->ana_tables.mach_data);
+ val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
+ (mac[0] << 8) | (mac[1] << 0);
+ out_le32(&l2ana_reg->ana_tables.mach_data, val);
+
+ out_le32(&l2ana_reg->ana_tables.macl_data,
+ (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) |
+ (mac[5] << 0));
+
+ if (vsc9953_mac_table_cmd(MAC_TABLE_READ) < 0)
+ return -1;
+
+ val = in_le32(&l2ana_reg->ana_tables.mac_access);
+
+ if ((port_no != bitfield_extract_by_mask(val,
+ VSC9953_MAC_DESTIDX_MASK))) {
+ printf("Failed to add MAC address\n");
+ return -1;
+ }
+ return 0;
+}
+
+/* Delete a FDB entry */
+static int vsc9953_mac_table_del(uchar mac[6], u16 vid)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ /* check first if MAC entry is present */
+ val = in_le32(&l2ana_reg->ana_tables.mach_data);
+ val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
+ (mac[0] << 8) | (mac[1] << 0);
+ out_le32(&l2ana_reg->ana_tables.mach_data, val);
+
+ out_le32(&l2ana_reg->ana_tables.macl_data,
+ (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) |
+ (mac[5] << 0));
+
+ if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) {
+ debug("Lookup in the MAC table failed\n");
+ return -1;
+ }
+
+ if (!(in_le32(&l2ana_reg->ana_tables.mac_access) &
+ VSC9953_MAC_CMD_VALID)) {
+ printf("The MAC address: %02x:%02x:%02x:%02x:%02x:%02x ",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ printf("VLAN: %d does not exist.\n", vid);
+ return -1;
+ }
+
+ /* FDB entry found, proceed to delete */
+ val = in_le32(&l2ana_reg->ana_tables.mach_data);
+ val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
+ (mac[0] << 8) | (mac[1] << 0);
+ out_le32(&l2ana_reg->ana_tables.mach_data, val);
+
+ out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) |
+ (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0));
+
+ if (vsc9953_mac_table_cmd(MAC_TABLE_FORGET) < 0)
+ return -1;
+
+ /* check if the MAC entry is still in FDB */
+ val = in_le32(&l2ana_reg->ana_tables.mach_data);
+ val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) |
+ (mac[0] << 8) | (mac[1] << 0);
+ out_le32(&l2ana_reg->ana_tables.mach_data, val);
+
+ out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) |
+ (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0));
+
+ if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) {
+ debug("Lookup in the MAC table failed\n");
+ return -1;
+ }
+ if (in_le32(&l2ana_reg->ana_tables.mac_access) &
+ VSC9953_MAC_CMD_VALID) {
+ printf("Failed to delete MAC address\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* age the unlocked entries in FDB */
+static void vsc9953_mac_table_age(int port_no, int vid)
+{
+ int rc[VSC9953_MAX_PORTS];
+ enum port_learn_mode mode[VSC9953_MAX_PORTS];
+ u32 val;
+ int i;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ /* set port and VID for selective aging */
+ val = in_le32(&l2ana_reg->ana.anag_efil);
+ if (port_no != ETHSW_CMD_PORT_ALL) {
+ /* disable auto learning */
+ rc[port_no] = vsc9953_port_learn_mode_get(port_no,
+ &mode[port_no]);
+ if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE);
+
+ val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK,
+ port_no) | VSC9953_AGE_PORT_EN;
+ } else {
+ /* disable auto learning on all ports */
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]);
+ if (!rc[i] && mode[i] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE);
+ }
+ }
+
+ if (vid != ETHSW_CMD_VLAN_ALL) {
+ val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, vid) |
+ VSC9953_AGE_VID_EN;
+ }
+ out_le32(&l2ana_reg->ana.anag_efil, val);
+
+ /* age the dynamic FDB entries */
+ vsc9953_mac_table_cmd(MAC_TABLE_AGE);
+
+ /* clear previously set port and VID */
+ clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN |
+ VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN |
+ VSC9953_AGE_VID_MASK);
+
+ if (port_no != ETHSW_CMD_PORT_ALL) {
+ if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(port_no, mode[port_no]);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ if (!rc[i] && mode[i] != PORT_LEARN_NONE)
+ vsc9953_port_learn_mode_set(i, mode[i]);
+ }
+ }
+}
+
+/* Delete all the dynamic FDB entries */
+static void vsc9953_mac_table_flush(int port, int vid)
+{
+ vsc9953_mac_table_age(port, vid);
+ vsc9953_mac_table_age(port, vid);
+}
+
+enum egress_vlan_tag {
+ EGR_TAG_CLASS = 0,
+ EGR_TAG_PVID,
+};
+
+/* Set egress tag mode for a VSC9953 port */
+static void vsc9953_port_vlan_egress_tag_set(int port_no,
+ enum egress_vlan_tag mode)
+{
+ struct vsc9953_rew_reg *l2rew_reg;
+
+ l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
+ VSC9953_REW_OFFSET);
+
+ switch (mode) {
+ case EGR_TAG_CLASS:
+ clrbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
+ VSC9953_TAG_VID_PVID);
+ break;
+ case EGR_TAG_PVID:
+ setbits_le32(&l2rew_reg->port[port_no].port_tag_cfg,
+ VSC9953_TAG_VID_PVID);
+ break;
+ default:
+ printf("Unknown egress VLAN tag mode for port %d\n", port_no);
+ }
+}
+
+/* Get egress tag mode for a VSC9953 port */
+static void vsc9953_port_vlan_egress_tag_get(int port_no,
+ enum egress_vlan_tag *mode)
+{
+ u32 val;
+ struct vsc9953_rew_reg *l2rew_reg;
+
+ l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET +
+ VSC9953_REW_OFFSET);
+
+ val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg);
+ if (val & VSC9953_TAG_VID_PVID)
+ *mode = EGR_TAG_PVID;
+ else
+ *mode = EGR_TAG_CLASS;
+}
+
+/* VSC9953 VLAN learning modes */
+enum vlan_learning_mode {
+ SHARED_VLAN_LEARNING,
+ PRIVATE_VLAN_LEARNING,
+};
+
+/* Set VLAN learning mode for VSC9953 */
+static void vsc9953_vlan_learning_set(enum vlan_learning_mode lrn_mode)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ switch (lrn_mode) {
+ case SHARED_VLAN_LEARNING:
+ setbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL);
+ break;
+ case PRIVATE_VLAN_LEARNING:
+ clrbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL);
+ break;
+ default:
+ printf("Unknown VLAN learn mode\n");
+ }
+}
+
+/* Get VLAN learning mode for VSC9953 */
+static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ val = in_le32(&l2ana_reg->ana.agen_ctrl);
+
+ if (!(val & VSC9953_FID_MASK_ALL)) {
+ *lrn_mode = PRIVATE_VLAN_LEARNING;
+ } else if ((val & VSC9953_FID_MASK_ALL) == VSC9953_FID_MASK_ALL) {
+ *lrn_mode = SHARED_VLAN_LEARNING;
+ } else {
+ printf("Unknown VLAN learning mode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* Enable/disable VLAN ingress filtering on a VSC9953 port */
+static void vsc9953_port_ingress_filtering_set(int port_no, int enabled)
+{
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ if (enabled)
+ setbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no);
+ else
+ clrbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no);
+}
+
+/* Return VLAN ingress filtering on a VSC9953 port */
+static int vsc9953_port_ingress_filtering_get(int port_no)
+{
+ u32 val;
+ struct vsc9953_analyzer *l2ana_reg;
+
+ l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
+ VSC9953_ANA_OFFSET);
+
+ val = in_le32(&l2ana_reg->ana.vlan_mask);
+ return !!(val & (1 << port_no));
+}
+
+static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ u8 enabled;
+
+ /* Last keyword should tell us if we should enable/disable the port */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_enable)
+ enabled = 1;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_disable)
+ enabled = 0;
+ else
+ return CMD_RET_USAGE;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_status_set(parsed_cmd->port, enabled);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_status_set(i, enabled);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_phy_autoneg(parsed_cmd->port);
+ printf("%8s %8s %8s %8s %8s\n",
+ "Port", "Status", "Link", "Speed",
+ "Duplex");
+ vsc9953_port_config_show(parsed_cmd->port);
+
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_phy_autoneg(i);
+ printf("%8s %8s %8s %8s %8s\n",
+ "Port", "Status", "Link", "Speed", "Duplex");
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_config_show(i);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_port_stats_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_statistics_show(parsed_cmd->port);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_statistics_show(i);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def
+ *parsed_cmd)
+{
+ int i;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_statistics_clear(parsed_cmd->port);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_statistics_clear(i);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_learn_show_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ enum port_learn_mode mode;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ if (vsc9953_port_learn_mode_get(parsed_cmd->port, &mode))
+ return CMD_RET_FAILURE;
+ printf("%7s %11s\n", "Port", "Learn mode");
+ switch (mode) {
+ case PORT_LEARN_NONE:
+ printf("%7d %11s\n", parsed_cmd->port, "disable");
+ break;
+ case PORT_LEARN_AUTO:
+ printf("%7d %11s\n", parsed_cmd->port, "auto");
+ break;
+ default:
+ printf("%7d %11s\n", parsed_cmd->port, "-");
+ }
+ } else {
+ printf("%7s %11s\n", "Port", "Learn mode");
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ if (vsc9953_port_learn_mode_get(i, &mode))
+ continue;
+ switch (mode) {
+ case PORT_LEARN_NONE:
+ printf("%7d %11s\n", i, "disable");
+ break;
+ case PORT_LEARN_AUTO:
+ printf("%7d %11s\n", i, "auto");
+ break;
+ default:
+ printf("%7d %11s\n", i, "-");
+ }
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ enum port_learn_mode mode;
+
+ /* Last keyword should tell us the learn mode */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_auto)
+ mode = PORT_LEARN_AUTO;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_disable)
+ mode = PORT_LEARN_NONE;
+ else
+ return CMD_RET_USAGE;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_learn_mode_set(parsed_cmd->port, mode);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_learn_mode_set(i, mode);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_fdb_show_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL &&
+ !VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+
+ if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL &&
+ !VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
+ printf("Invalid VID number: %d\n", parsed_cmd->vid);
+ return CMD_RET_FAILURE;
+ }
+
+ vsc9953_mac_table_show(parsed_cmd->port, parsed_cmd->vid);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_fdb_flush_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL &&
+ !VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+
+ if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL &&
+ !VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
+ printf("Invalid VID number: %d\n", parsed_cmd->vid);
+ return CMD_RET_FAILURE;
+ }
+
+ vsc9953_mac_table_flush(parsed_cmd->port, parsed_cmd->vid);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_fdb_entry_add_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int vid;
+
+ /* a port number must be present */
+ if (parsed_cmd->port == ETHSW_CMD_PORT_ALL) {
+ printf("Please specify a port\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+
+ /* Use VLAN 1 if VID is not set */
+ vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid);
+
+ if (!VSC9953_VLAN_CHECK(vid)) {
+ printf("Invalid VID number: %d\n", vid);
+ return CMD_RET_FAILURE;
+ }
+
+ if (vsc9953_mac_table_add(parsed_cmd->port, parsed_cmd->ethaddr, vid))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int vid;
+
+ /* Use VLAN 1 if VID is not set */
+ vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid);
+
+ if (!VSC9953_VLAN_CHECK(vid)) {
+ printf("Invalid VID number: %d\n", vid);
+ return CMD_RET_FAILURE;
+ }
+
+ if (vsc9953_mac_table_del(parsed_cmd->ethaddr, vid))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_pvid_show_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ int pvid;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+
+ if (vsc9953_port_vlan_pvid_get(parsed_cmd->port, &pvid))
+ return CMD_RET_FAILURE;
+ printf("%7s %7s\n", "Port", "PVID");
+ printf("%7d %7d\n", parsed_cmd->port, pvid);
+ } else {
+ printf("%7s %7s\n", "Port", "PVID");
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ if (vsc9953_port_vlan_pvid_get(i, &pvid))
+ continue;
+ printf("%7d %7d\n", i, pvid);
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_pvid_set_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ /* PVID number should be set in parsed_cmd->vid */
+ if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) {
+ printf("Please set a pvid value\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
+ printf("Invalid VID number: %d\n", parsed_cmd->vid);
+ return CMD_RET_FAILURE;
+ }
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_vlan_pvid_set(parsed_cmd->port, parsed_cmd->vid);
+ } else {
+ vsc9953_port_all_vlan_pvid_set(parsed_cmd->vid);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_vlan_show_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_vlan_membership_show(parsed_cmd->port);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_vlan_membership_show(i);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_vlan_set_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ int add;
+
+ /* VLAN should be set in parsed_cmd->vid */
+ if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) {
+ printf("Please set a vlan value\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) {
+ printf("Invalid VID number: %d\n", parsed_cmd->vid);
+ return CMD_RET_FAILURE;
+ }
+
+ /* keywords add/delete should be the last but one in array */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] ==
+ ethsw_id_add)
+ add = 1;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] ==
+ ethsw_id_del)
+ add = 0;
+ else
+ return CMD_RET_USAGE;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_vlan_table_membership_set(parsed_cmd->vid,
+ parsed_cmd->port, add);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_vlan_table_membership_set(parsed_cmd->vid, i,
+ add);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+static int vsc9953_port_untag_show_key_func(
+ struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+
+ printf("%7s\t%17s\n", "Port", "Untag");
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_vlan_egr_untag_show(parsed_cmd->port);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_egr_untag_show(i);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_port_untag_set_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ enum egress_untag_mode mode;
+
+ /* keywords for the untagged mode are the last in the array */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_all)
+ mode = EGRESS_UNTAG_ALL;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_none)
+ mode = EGRESS_UNTAG_NONE;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_pvid)
+ mode = EGRESS_UNTAG_PVID_AND_ZERO;
+ else
+ return CMD_RET_USAGE;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_vlan_egr_untag_set(parsed_cmd->port, mode);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_egr_untag_set(i, mode);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_egr_vlan_tag_show_key_func(
+ struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ enum egress_vlan_tag mode;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_vlan_egress_tag_get(parsed_cmd->port, &mode);
+ printf("%7s\t%12s\n", "Port", "Egress VID");
+ printf("%7d\t", parsed_cmd->port);
+ switch (mode) {
+ case EGR_TAG_CLASS:
+ printf("%12s\n", "classified");
+ break;
+ case EGR_TAG_PVID:
+ printf("%12s\n", "pvid");
+ break;
+ default:
+ printf("%12s\n", "-");
+ }
+ } else {
+ printf("%7s\t%12s\n", "Port", "Egress VID");
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ vsc9953_port_vlan_egress_tag_get(i, &mode);
+ switch (mode) {
+ case EGR_TAG_CLASS:
+ printf("%7d\t%12s\n", i, "classified");
+ break;
+ case EGR_TAG_PVID:
+ printf("%7d\t%12s\n", i, "pvid");
+ break;
+ default:
+ printf("%7d\t%12s\n", i, "-");
+ }
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_egr_vlan_tag_set_key_func(
+ struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ enum egress_vlan_tag mode;
+
+ /* keywords for the egress vlan tag mode are the last in the array */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_pvid)
+ mode = EGR_TAG_PVID;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_classified)
+ mode = EGR_TAG_CLASS;
+ else
+ return CMD_RET_USAGE;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_vlan_egress_tag_set(parsed_cmd->port, mode);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_vlan_egress_tag_set(i, mode);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_vlan_learn_show_key_func(
+ struct ethsw_command_def *parsed_cmd)
+{
+ int rc;
+ enum vlan_learning_mode mode;
+
+ rc = vsc9953_vlan_learning_get(&mode);
+ if (rc)
+ return CMD_RET_FAILURE;
+
+ switch (mode) {
+ case SHARED_VLAN_LEARNING:
+ printf("VLAN learning mode: shared\n");
+ break;
+ case PRIVATE_VLAN_LEARNING:
+ printf("VLAN learning mode: private\n");
+ break;
+ default:
+ printf("Unknown VLAN learning mode\n");
+ rc = CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ enum vlan_learning_mode mode;
+
+ /* keywords for shared/private are the last in the array */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_shared)
+ mode = SHARED_VLAN_LEARNING;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_private)
+ mode = PRIVATE_VLAN_LEARNING;
+ else
+ return CMD_RET_USAGE;
+
+ vsc9953_vlan_learning_set(mode);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_ingr_fltr_show_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ int enabled;
+
+ printf("%7s\t%18s\n", "Port", "Ingress filtering");
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ enabled = vsc9953_port_ingress_filtering_get(parsed_cmd->port);
+ printf("%7d\t%18s\n", parsed_cmd->port, enabled ? "enable" :
+ "disable");
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ enabled = vsc9953_port_ingress_filtering_get(i);
+ printf("%7d\t%18s\n", parsed_cmd->port, enabled ?
+ "enable" :
+ "disable");
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd)
+{
+ int i;
+ int enable;
+
+ /* keywords for enabling/disabling ingress filtering
+ * are the last in the array
+ */
+ if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_enable)
+ enable = 1;
+ else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] ==
+ ethsw_id_disable)
+ enable = 0;
+ else
+ return CMD_RET_USAGE;
+
+ if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) {
+ if (!VSC9953_PORT_CHECK(parsed_cmd->port)) {
+ printf("Invalid port number: %d\n", parsed_cmd->port);
+ return CMD_RET_FAILURE;
+ }
+ vsc9953_port_ingress_filtering_set(parsed_cmd->port, enable);
+ } else {
+ for (i = 0; i < VSC9953_MAX_PORTS; i++)
+ vsc9953_port_ingress_filtering_set(i, enable);
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static struct ethsw_command_func vsc9953_cmd_func = {
+ .ethsw_name = "L2 Switch VSC9953",
+ .port_enable = &vsc9953_port_status_key_func,
+ .port_disable = &vsc9953_port_status_key_func,
+ .port_show = &vsc9953_port_config_key_func,
+ .port_stats = &vsc9953_port_stats_key_func,
+ .port_stats_clear = &vsc9953_port_stats_clear_key_func,
+ .port_learn = &vsc9953_learn_set_key_func,
+ .port_learn_show = &vsc9953_learn_show_key_func,
+ .fdb_show = &vsc9953_fdb_show_key_func,
+ .fdb_flush = &vsc9953_fdb_flush_key_func,
+ .fdb_entry_add = &vsc9953_fdb_entry_add_key_func,
+ .fdb_entry_del = &vsc9953_fdb_entry_del_key_func,
+ .pvid_show = &vsc9953_pvid_show_key_func,
+ .pvid_set = &vsc9953_pvid_set_key_func,
+ .vlan_show = &vsc9953_vlan_show_key_func,
+ .vlan_set = &vsc9953_vlan_set_key_func,
+ .port_untag_show = &vsc9953_port_untag_show_key_func,
+ .port_untag_set = &vsc9953_port_untag_set_key_func,
+ .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func,
+ .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func,
+ .vlan_learn_show = &vsc9953_vlan_learn_show_key_func,
+ .vlan_learn_set = &vsc9953_vlan_learn_set_key_func,
+ .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func,
+ .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func
+};
+
+#endif /* CONFIG_CMD_ETHSW */
+
+/*****************************************************************************
+At startup, the default configuration would be:
+ - HW learning enabled on all ports; (HW default)
+ - All ports are in VLAN 1;
+ - All ports are VLAN aware;
+ - All ports have POP_COUNT 1;
+ - All ports have PVID 1;
+ - All ports have TPID 0x8100; (HW default)
+ - All ports tag frames classified to all VLANs that are not PVID;
+*****************************************************************************/
+void vsc9953_default_configuration(void)
+{
+ int i;
+
+ for (i = 0; i < VSC9953_MAX_VLAN; i++)
+ vsc9953_vlan_table_membership_all_set(i, 0);
+ vsc9953_port_all_vlan_aware_set(1);
+ vsc9953_port_all_vlan_pvid_set(1);
+ vsc9953_port_all_vlan_poncnt_set(1);
+ vsc9953_vlan_table_membership_all_set(1, 1);
+ vsc9953_vlan_ingr_fltr_learn_drop(1);
+ vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO);
+}
+
void vsc9953_init(bd_t *bis)
{
- u32 i, hdx_cfg = 0, phy_addr = 0;
- int timeout;
- struct vsc9953_system_reg *l2sys_reg;
- struct vsc9953_qsys_reg *l2qsys_reg;
- struct vsc9953_dev_gmii *l2dev_gmii_reg;
- struct vsc9953_analyzer *l2ana_reg;
- struct vsc9953_devcpu_gcb *l2dev_gcb;
+ u32 i;
+ u32 hdx_cfg = 0;
+ u32 phy_addr = 0;
+ int timeout;
+ struct vsc9953_system_reg *l2sys_reg;
+ struct vsc9953_qsys_reg *l2qsys_reg;
+ struct vsc9953_dev_gmii *l2dev_gmii_reg;
+ struct vsc9953_analyzer *l2ana_reg;
+ struct vsc9953_devcpu_gcb *l2dev_gcb;
l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET +
VSC9953_DEV_GMII_OFFSET);
VSC9953_DEVCPU_GCB);
out_le32(&l2dev_gcb->chip_regs.soft_rst,
- CONFIG_VSC9953_SOFT_SWC_RST_ENA);
+ VSC9953_SOFT_SWC_RST_ENA);
timeout = 50000;
while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) &
- CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout)
+ VSC9953_SOFT_SWC_RST_ENA) && --timeout)
udelay(1); /* busy wait for vsc9953 soft reset */
if (timeout == 0)
debug("Timeout waiting for VSC9953 to reset\n");
- out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE |
- CONFIG_VSC9953_MEM_INIT);
+ out_le32(&l2sys_reg->sys.reset_cfg, VSC9953_MEM_ENABLE |
+ VSC9953_MEM_INIT);
timeout = 50000;
while ((in_le32(&l2sys_reg->sys.reset_cfg) &
- CONFIG_VSC9953_MEM_INIT) && --timeout)
+ VSC9953_MEM_INIT) && --timeout)
udelay(1); /* busy wait for vsc9953 memory init */
if (timeout == 0)
debug("Timeout waiting for VSC9953 memory to initialize\n");
out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg)
- | CONFIG_VSC9953_CORE_ENABLE));
+ | VSC9953_CORE_ENABLE));
/* VSC9953 Setting to be done once only */
out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00);
/* Enable VSC9953 GMII Ports Port ID 0 - 7 */
if (VSC9953_INTERNAL_PORT_CHECK(i)) {
out_le32(&l2ana_reg->pfc[i].pfc_cfg,
- CONFIG_VSC9953_PFC_FC_QSGMII);
+ VSC9953_PFC_FC_QSGMII);
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
- CONFIG_VSC9953_MAC_FC_CFG_QSGMII);
+ VSC9953_MAC_FC_CFG_QSGMII);
} else {
out_le32(&l2ana_reg->pfc[i].pfc_cfg,
- CONFIG_VSC9953_PFC_FC);
+ VSC9953_PFC_FC);
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
- CONFIG_VSC9953_MAC_FC_CFG);
+ VSC9953_MAC_FC_CFG);
}
out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
- CONFIG_VSC9953_CLOCK_CFG);
+ VSC9953_CLOCK_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
- CONFIG_VSC9953_MAC_ENA_CFG);
+ VSC9953_MAC_ENA_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg,
- CONFIG_VSC9953_MAC_MODE_CFG);
+ VSC9953_MAC_MODE_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg,
- CONFIG_VSC9953_MAC_IFG_CFG);
+ VSC9953_MAC_IFG_CFG);
/* mac_hdx_cfg varies with port id*/
- hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16));
+ hdx_cfg = VSC9953_MAC_HDX_CFG | (i << 16);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg);
out_le32(&l2sys_reg->sys.front_port_mode[i],
- CONFIG_VSC9953_FRONT_PORT_MODE);
- out_le32(&l2qsys_reg->sys.switch_port_mode[i],
- CONFIG_VSC9953_PORT_ENA);
+ VSC9953_FRONT_PORT_MODE);
+ setbits_le32(&l2qsys_reg->sys.switch_port_mode[i],
+ VSC9953_PORT_ENA);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg,
- CONFIG_VSC9953_MAC_MAX_LEN);
+ VSC9953_MAC_MAX_LEN);
out_le32(&l2sys_reg->pause_cfg.pause_cfg[i],
- CONFIG_VSC9953_PAUSE_CFG);
+ VSC9953_PAUSE_CFG);
/* WAIT FOR 2 us*/
udelay(2);
}
}
- printf("VSC9953 L2 switch initialized\n");
- return;
-}
-
-#ifdef CONFIG_VSC9953_CMD
-/* Enable/disable status of a VSC9953 port */
-static void vsc9953_port_status_set(int port_nr, u8 enabled)
-{
- u32 val;
- struct vsc9953_qsys_reg *l2qsys_reg;
-
- /* Administrative down */
- if (vsc9953_l2sw.port[port_nr].enabled == 0)
- return;
-
- l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
- VSC9953_QSYS_OFFSET);
-
- val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]);
- if (enabled == 1)
- val |= (1 << 13);
- else
- val &= ~(1 << 13);
-
- out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val);
-}
-
-/* Set all VSC9953 ports' status */
-static void vsc9953_port_all_status_set(u8 enabled)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_status_set(i, enabled);
-}
-
-/* Start autonegotiation for a VSC9953 PHY */
-static void vsc9953_phy_autoneg(int port_nr)
-{
- if (!vsc9953_l2sw.port[port_nr].phydev)
- return;
-
- if (vsc9953_l2sw.port[port_nr].phydev->drv->startup(
- vsc9953_l2sw.port[port_nr].phydev))
- printf("Failed to start PHY for port %d\n", port_nr);
-}
-
-/* Start autonegotiation for all VSC9953 PHYs */
-static void vsc9953_phy_all_autoneg(void)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_phy_autoneg(i);
-}
-
-/* Print a VSC9953 port's configuration */
-static void vsc9953_port_config_show(int port)
-{
- int speed;
- int duplex;
- int link;
- u8 enabled;
- u32 val;
- struct vsc9953_qsys_reg *l2qsys_reg;
-
- l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
- VSC9953_QSYS_OFFSET);
-
- val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]);
- enabled = vsc9953_l2sw.port[port].enabled &
- ((val & 0x00002000) >> 13);
-
- /* internal ports (8 and 9) are fixed */
- if (VSC9953_INTERNAL_PORT_CHECK(port)) {
- link = 1;
- speed = SPEED_2500;
- duplex = DUPLEX_FULL;
- } else {
- if (vsc9953_l2sw.port[port].phydev) {
- link = vsc9953_l2sw.port[port].phydev->link;
- speed = vsc9953_l2sw.port[port].phydev->speed;
- duplex = vsc9953_l2sw.port[port].phydev->duplex;
- } else {
- link = -1;
- speed = -1;
- duplex = -1;
- }
- }
-
- printf("%8d ", port);
- printf("%8s ", enabled == 1 ? "enabled" : "disabled");
- printf("%8s ", link == 1 ? "up" : "down");
-
- switch (speed) {
- case SPEED_10:
- printf("%8d ", 10);
- break;
- case SPEED_100:
- printf("%8d ", 100);
- break;
- case SPEED_1000:
- printf("%8d ", 1000);
- break;
- case SPEED_2500:
- printf("%8d ", 2500);
- break;
- case SPEED_10000:
- printf("%8d ", 10000);
- break;
- default:
- printf("%8s ", "-");
- }
-
- printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half");
-}
-
-/* Print VSC9953 ports' configuration */
-static void vsc9953_port_all_config_show(void)
-{
- int i;
-
- for (i = 0; i < VSC9953_MAX_PORTS; i++)
- vsc9953_port_config_show(i);
-}
-
-/* function to interpret commands starting with "ethsw " */
-static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- u8 enable;
- u32 port;
-
- if (argc < 4)
- return -1;
-
- if (strcmp(argv[1], "port"))
- return -1;
-
- if (!strcmp(argv[3], "show")) {
- if (!strcmp(argv[2], "all")) {
- vsc9953_phy_all_autoneg();
- printf("%8s %8s %8s %8s %8s\n",
- "Port", "Status", "Link", "Speed",
- "Duplex");
- vsc9953_port_all_config_show();
- return 0;
- } else {
- port = simple_strtoul(argv[2], NULL, 10);
- if (!VSC9953_PORT_CHECK(port))
- return -1;
- vsc9953_phy_autoneg(port);
- printf("%8s %8s %8s %8s %8s\n",
- "Port", "Status", "Link", "Speed",
- "Duplex");
- vsc9953_port_config_show(port);
- return 0;
- }
- } else if (!strcmp(argv[3], "enable")) {
- enable = 1;
- } else if (!strcmp(argv[3], "disable")) {
- enable = 0;
- } else {
- return -1;
- }
+ vsc9953_default_configuration();
- if (!strcmp(argv[2], "all")) {
- vsc9953_port_all_status_set(enable);
- return 0;
- } else {
- port = simple_strtoul(argv[2], NULL, 10);
- if (!VSC9953_PORT_CHECK(port))
- return -1;
- vsc9953_port_status_set(port, enable);
- return 0;
- }
+#ifdef CONFIG_CMD_ETHSW
+ if (ethsw_define_functions(&vsc9953_cmd_func) < 0)
+ debug("Unable to use \"ethsw\" commands\n");
+#endif
- return -1;
+ printf("VSC9953 L2 switch initialized\n");
+ return;
}
-
-U_BOOT_CMD(ethsw, 5, 0, do_ethsw,
- "vsc9953 l2 switch commands",
- "port <port_nr> enable|disable\n"
- " - enable/disable an l2 switch port\n"
- " port_nr=0..9; use \"all\" for all ports\n"
- "ethsw port <port_nr> show\n"
- " - show an l2 switch port's configuration\n"
- " port_nr=0..9; use \"all\" for all ports\n"
-);
-#endif /* CONFIG_VSC9953_CMD */
{
struct udevice *bus;
- for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
+ for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
}
{
struct udevice *bus;
- for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
+ for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
size);
#ifndef CONFIG_PCI_ENUM_ONLY
/* Configure the expansion ROM address */
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
if (header_type != PCI_HEADER_TYPE_CARDBUS) {
rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
*
* The PCIe #PERST reset line _MUST_ be connected, otherwise your
* design does not conform to the specification. You must wait at
- * least 20 mS after de-asserting the #PERST so the EP device can
+ * least 20 ms after de-asserting the #PERST so the EP device can
* do self-initialisation.
*
* In case your #PERST pin is connected to a plain GPIO pin of the
* In case your #PERST toggling logic is more complex, for example
* connected via CPLD or somesuch, you can override this function
* in your board file and implement reset logic as needed. You must
- * not forget to wait at least 20 mS after de-asserting #PERST in
+ * not forget to wait at least 20 ms after de-asserting #PERST in
* this case either though.
*
* In case your #PERST line of the PCIe EP device is not connected
/*
* Wait for the clock to settle a bit, when the clock are sourced
- * from the CPU, we need about 30mS to settle.
+ * from the CPU, we need about 30 ms to settle.
*/
mdelay(50);
endif
+source "drivers/pinctrl/uniphier/Kconfig"
+
endmenu
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
+
+obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
#include <dm/device.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
-#include <dm/root.h>
#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
static int pinconfig_post_bind(struct udevice *dev)
{
- /* Scan the bus for devices */
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+ return 0;
}
#endif
}
/*
- * The pinctrl driver child nodes should be bound so that peripheral
- * devices can easily search in parent devices during later DT-parsing.
+ * If set_state callback is set, we assume this pinctrl driver is the
+ * full implementation. In this case, its child nodes should be bound
+ * so that peripheral devices can easily search in parent devices
+ * during later DT-parsing.
*/
- return pinconfig_post_bind(dev);
+ if (ops->set_state)
+ return pinconfig_post_bind(dev);
+
+ return 0;
}
UCLASS_DRIVER(pinctrl) = {
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <dm/pinctrl.h>
+#include <dm/root.h>
DECLARE_GLOBAL_DATA_PTR;
.get_periph_id = rk3288_pinctrl_get_periph_id,
};
+static int rk3288_pinctrl_bind(struct udevice *dev)
+{
+ /* scan child GPIO banks */
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
static int rk3288_pinctrl_probe(struct udevice *dev)
{
struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
.of_match = rk3288_pinctrl_ids,
.priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
.ops = &rk3288_pinctrl_ops,
+ .bind = rk3288_pinctrl_bind,
.probe = rk3288_pinctrl_probe,
};
--- /dev/null
+if ARCH_UNIPHIER
+
+config PINCTRL_UNIPHIER_CORE
+ bool
+
+config PINCTRL_UNIPHIER_PH1_LD4
+ bool "UniPhier PH1-LD4 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_PH1_LD4
+ default y
+ select PINCTRL_UNIPHIER_CORE
+
+config PINCTRL_UNIPHIER_PH1_PRO4
+ bool "UniPhier PH1-Pro4 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_PH1_PRO4
+ default y
+ select PINCTRL_UNIPHIER_CORE
+
+config PINCTRL_UNIPHIER_PH1_SLD8
+ bool "UniPhier PH1-sLD8 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_PH1_SLD8
+ default y
+ select PINCTRL_UNIPHIER_CORE
+
+config PINCTRL_UNIPHIER_PH1_PRO5
+ bool "UniPhier PH1-Pro5 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_PH1_PRO5
+ default y
+ select PINCTRL_UNIPHIER_CORE
+
+config PINCTRL_UNIPHIER_PROXSTREAM2
+ bool "UniPhier ProXstream2 SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_PROXSTREAM2
+ default y
+ select PINCTRL_UNIPHIER_CORE
+
+config PINCTRL_UNIPHIER_PH1_LD6B
+ bool "UniPhier PH1-LD6b SoC pinctrl driver"
+ depends on ARCH_UNIPHIER_PH1_LD6B
+ default y
+ select PINCTRL_UNIPHIER_CORE
+
+endif
--- /dev/null
+obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o
+
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = {
+ UNIPHIER_PINCTRL_PIN(53, 0),
+ UNIPHIER_PINCTRL_PIN(54, 0),
+ UNIPHIER_PINCTRL_PIN(55, 0),
+ UNIPHIER_PINCTRL_PIN(56, 0),
+ UNIPHIER_PINCTRL_PIN(67, 0),
+ UNIPHIER_PINCTRL_PIN(68, 0),
+ UNIPHIER_PINCTRL_PIN(69, 0),
+ UNIPHIER_PINCTRL_PIN(70, 0),
+ UNIPHIER_PINCTRL_PIN(85, 0),
+ UNIPHIER_PINCTRL_PIN(88, 0),
+ UNIPHIER_PINCTRL_PIN(156, 0),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
+ 160, 161, 162, 163, 164};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {85, 88};
+static const unsigned uart0_muxvals[] = {1, 1};
+static const unsigned uart1_pins[] = {155, 156};
+static const unsigned uart1_muxvals[] = {13, 13};
+static const unsigned uart1b_pins[] = {69, 70};
+static const unsigned uart1b_muxvals[] = {23, 23};
+static const unsigned uart2_pins[] = {128, 129};
+static const unsigned uart2_muxvals[] = {13, 13};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {53, 54};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {55, 56};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {155, 156};
+static const unsigned usb2_muxvals[] = {4, 4};
+static const unsigned usb2b_pins[] = {67, 68};
+static const unsigned usb2b_muxvals[] = {23, 23};
+
+static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1b),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb2b),
+};
+
+static const char * const ph1_ld4_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = {
+ .pins = ph1_ld4_pins,
+ .pins_count = ARRAY_SIZE(ph1_ld4_pins),
+ .groups = ph1_ld4_groups,
+ .groups_count = ARRAY_SIZE(ph1_ld4_groups),
+ .functions = ph1_ld4_functions,
+ .functions_count = ARRAY_SIZE(ph1_ld4_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static int ph1_ld4_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_ld4_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld4-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_ld4_pinctrl) = {
+ .name = "ph1-ld4-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_ld4_pinctrl_match),
+ .probe = ph1_ld4_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = {
+ UNIPHIER_PINCTRL_PIN(113, 0),
+ UNIPHIER_PINCTRL_PIN(114, 0),
+ UNIPHIER_PINCTRL_PIN(115, 0),
+ UNIPHIER_PINCTRL_PIN(116, 0),
+ UNIPHIER_PINCTRL_PIN(217, 0),
+ UNIPHIER_PINCTRL_PIN(218, 0),
+ UNIPHIER_PINCTRL_PIN(219, 0),
+ UNIPHIER_PINCTRL_PIN(220, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {115, 116};
+static const unsigned i2c2_muxvals[] = {1, 1};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+ 42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {135, 136};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart0b_pins[] = {11, 12};
+static const unsigned uart0b_muxvals[] = {2, 2};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart1b_pins[] = {113, 114};
+static const unsigned uart1b_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {2, 2};
+static const unsigned uart2b_pins[] = {86, 87};
+static const unsigned uart2b_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1b),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart2b),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const ph1_ld6b_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3",
+};
+
+static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = {
+ .pins = ph1_ld6b_pins,
+ .pins_count = ARRAY_SIZE(ph1_ld6b_pins),
+ .groups = ph1_ld6b_groups,
+ .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
+ .functions = ph1_ld6b_functions,
+ .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static int ph1_ld6b_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_ld6b_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-ld6b-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_ld6b_pinctrl) = {
+ .name = "ph1-ld6b-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_ld6b_pinctrl_match),
+ .probe = ph1_ld6b_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = {
+};
+
+static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {142, 143};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {144, 145};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {146, 147};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {148, 149};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c6_pins[] = {308, 309};
+static const unsigned i2c6_muxvals[] = {6, 6};
+static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+ 50, 51, 52, 53, 54};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {131, 132};
+static const unsigned nand_cs1_muxvals[] = {1, 1};
+static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
+ 327};
+static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {127, 128};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {129, 130};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {131, 132};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {88, 89};
+static const unsigned uart3_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {180, 181};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {182, 183};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {184, 185};
+static const unsigned usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {186, 187};
+static const unsigned usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(sd1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const ph1_pro4_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c6",
+ "nand",
+ "sd",
+ "sd1",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3",
+};
+
+static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = {
+ .pins = ph1_pro4_pins,
+ .pins_count = ARRAY_SIZE(ph1_pro4_pins),
+ .groups = ph1_pro4_groups,
+ .groups_count = ARRAY_SIZE(ph1_pro4_groups),
+ .functions = ph1_pro4_functions,
+ .functions_count = ARRAY_SIZE(ph1_pro4_functions),
+ .mux_bits = 4,
+ .reg_stride = 8,
+ .load_pinctrl = true,
+};
+
+static int ph1_pro4_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_pro4_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-pro4-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_pro4_pinctrl) = {
+ .name = "ph1-pro4-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_pro4_pinctrl_match),
+ .probe = ph1_pro4_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = {
+ UNIPHIER_PINCTRL_PIN(47, 0),
+ UNIPHIER_PINCTRL_PIN(48, 0),
+ UNIPHIER_PINCTRL_PIN(49, 0),
+ UNIPHIER_PINCTRL_PIN(50, 0),
+ UNIPHIER_PINCTRL_PIN(53, 0),
+ UNIPHIER_PINCTRL_PIN(54, 0),
+ UNIPHIER_PINCTRL_PIN(87, 0),
+ UNIPHIER_PINCTRL_PIN(88, 0),
+ UNIPHIER_PINCTRL_PIN(101, 0),
+ UNIPHIER_PINCTRL_PIN(102, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {112, 113};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {114, 115};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {116, 117};
+static const unsigned i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {118, 119};
+static const unsigned i2c3_muxvals[] = {0, 0};
+static const unsigned i2c5_pins[] = {87, 88};
+static const unsigned i2c5_muxvals[] = {2, 2};
+static const unsigned i2c5b_pins[] = {196, 197};
+static const unsigned i2c5b_muxvals[] = {2, 2};
+static const unsigned i2c5c_pins[] = {215, 216};
+static const unsigned i2c5c_muxvals[] = {2, 2};
+static const unsigned i2c6_pins[] = {101, 102};
+static const unsigned i2c6_muxvals[] = {2, 2};
+static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
+ 31, 32, 33, 34, 35};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {26, 27};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {47, 48};
+static const unsigned uart0_muxvals[] = {0, 0};
+static const unsigned uart0b_pins[] = {227, 228};
+static const unsigned uart0b_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {49, 50};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {51, 52};
+static const unsigned uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {53, 54};
+static const unsigned uart3_muxvals[] = {0, 0};
+static const unsigned usb0_pins[] = {124, 125};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {126, 127};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {128, 129};
+static const unsigned usb2_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c5b),
+ UNIPHIER_PINCTRL_GROUP(i2c5c),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const ph1_pro5_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c5",
+ "i2c6",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = {
+ .pins = ph1_pro5_pins,
+ .pins_count = ARRAY_SIZE(ph1_pro5_pins),
+ .groups = ph1_pro5_groups,
+ .groups_count = ARRAY_SIZE(ph1_pro5_groups),
+ .functions = ph1_pro5_functions,
+ .functions_count = ARRAY_SIZE(ph1_pro5_functions),
+ .mux_bits = 4,
+ .reg_stride = 8,
+ .load_pinctrl = true,
+};
+
+static int ph1_pro5_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_pro5_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-pro5-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_pro5_pinctrl) = {
+ .name = "ph1-pro5-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_pro5_pinctrl_match),
+ .probe = ph1_pro5_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = {
+ UNIPHIER_PINCTRL_PIN(32, 8),
+ UNIPHIER_PINCTRL_PIN(33, 8),
+ UNIPHIER_PINCTRL_PIN(34, 8),
+ UNIPHIER_PINCTRL_PIN(35, 8),
+ UNIPHIER_PINCTRL_PIN(36, 8),
+ UNIPHIER_PINCTRL_PIN(37, 8),
+ UNIPHIER_PINCTRL_PIN(38, 8),
+ UNIPHIER_PINCTRL_PIN(39, 8),
+ UNIPHIER_PINCTRL_PIN(40, 9),
+ UNIPHIER_PINCTRL_PIN(41, 0),
+ UNIPHIER_PINCTRL_PIN(42, 0),
+ UNIPHIER_PINCTRL_PIN(43, 0),
+ UNIPHIER_PINCTRL_PIN(44, 0),
+ UNIPHIER_PINCTRL_PIN(70, 0),
+ UNIPHIER_PINCTRL_PIN(71, 0),
+ UNIPHIER_PINCTRL_PIN(102, 10),
+ UNIPHIER_PINCTRL_PIN(103, 10),
+ UNIPHIER_PINCTRL_PIN(104, 11),
+ UNIPHIER_PINCTRL_PIN(105, 11),
+ UNIPHIER_PINCTRL_PIN(108, 13),
+ UNIPHIER_PINCTRL_PIN(109, 13),
+ UNIPHIER_PINCTRL_PIN(112, 0),
+ UNIPHIER_PINCTRL_PIN(113, 0),
+ UNIPHIER_PINCTRL_PIN(114, 0),
+ UNIPHIER_PINCTRL_PIN(115, 0),
+};
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {102, 103};
+static const unsigned i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const unsigned i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const unsigned i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const unsigned i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
+ 27, 28, 29, 30, 31};
+static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
+static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned uart0_pins[] = {70, 71};
+static const unsigned uart0_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {114, 115};
+static const unsigned uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {112, 113};
+static const unsigned uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {110, 111};
+static const unsigned uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {41, 42};
+static const unsigned usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {43, 44};
+static const unsigned usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {114, 115};
+static const unsigned usb2_muxvals[] = {1, 1};
+
+static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const ph1_sld8_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "nand",
+ "sd",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "usb0",
+ "usb1",
+ "usb2",
+};
+
+static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = {
+ .pins = ph1_sld8_pins,
+ .pins_count = ARRAY_SIZE(ph1_sld8_pins),
+ .groups = ph1_sld8_groups,
+ .groups_count = ARRAY_SIZE(ph1_sld8_groups),
+ .functions = ph1_sld8_functions,
+ .functions_count = ARRAY_SIZE(ph1_sld8_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static int ph1_sld8_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata);
+}
+
+static const struct udevice_id ph1_sld8_pinctrl_match[] = {
+ { .compatible = "socionext,ph1-sld8-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ph1_sld8_pinctrl) = {
+ .name = "ph1-sld8-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(ph1_sld8_pinctrl_match),
+ .probe = ph1_sld8_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin proxstream2_pins[] = {
+ UNIPHIER_PINCTRL_PIN(113, 0),
+ UNIPHIER_PINCTRL_PIN(114, 0),
+ UNIPHIER_PINCTRL_PIN(115, 0),
+ UNIPHIER_PINCTRL_PIN(116, 0),
+};
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned i2c0_pins[] = {109, 110};
+static const unsigned i2c0_muxvals[] = {8, 8};
+static const unsigned i2c1_pins[] = {111, 112};
+static const unsigned i2c1_muxvals[] = {8, 8};
+static const unsigned i2c2_pins[] = {171, 172};
+static const unsigned i2c2_muxvals[] = {8, 8};
+static const unsigned i2c3_pins[] = {159, 160};
+static const unsigned i2c3_muxvals[] = {8, 8};
+static const unsigned i2c5_pins[] = {183, 184};
+static const unsigned i2c5_muxvals[] = {11, 11};
+static const unsigned i2c6_pins[] = {185, 186};
+static const unsigned i2c6_muxvals[] = {11, 11};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+ 42, 43, 44, 45, 46};
+static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const unsigned nand_cs1_muxvals[] = {8, 8};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned uart0_pins[] = {217, 218};
+static const unsigned uart0_muxvals[] = {8, 8};
+static const unsigned uart0b_pins[] = {179, 180};
+static const unsigned uart0b_muxvals[] = {10, 10};
+static const unsigned uart1_pins[] = {115, 116};
+static const unsigned uart1_muxvals[] = {8, 8};
+static const unsigned uart2_pins[] = {113, 114};
+static const unsigned uart2_muxvals[] = {8, 8};
+static const unsigned uart3_pins[] = {219, 220};
+static const unsigned uart3_muxvals[] = {8, 8};
+static const unsigned uart3b_pins[] = {181, 182};
+static const unsigned uart3b_muxvals[] = {10, 10};
+static const unsigned usb0_pins[] = {56, 57};
+static const unsigned usb0_muxvals[] = {8, 8};
+static const unsigned usb1_pins[] = {58, 59};
+static const unsigned usb1_muxvals[] = {8, 8};
+static const unsigned usb2_pins[] = {60, 61};
+static const unsigned usb2_muxvals[] = {8, 8};
+static const unsigned usb3_pins[] = {62, 63};
+static const unsigned usb3_muxvals[] = {8, 8};
+
+static const struct uniphier_pinctrl_group proxstream2_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(nand_cs1),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart0b),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(uart3b),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const proxstream2_functions[] = {
+ "emmc",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "i2c3",
+ "i2c5",
+ "i2c6",
+ "nand",
+ "sd",
+ "uart0",
+ "uart0b",
+ "uart1",
+ "uart2",
+ "uart3",
+ "uart3b",
+ "usb0",
+ "usb1",
+ "usb2",
+ "usb3",
+};
+
+static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = {
+ .pins = proxstream2_pins,
+ .pins_count = ARRAY_SIZE(proxstream2_pins),
+ .groups = proxstream2_groups,
+ .groups_count = ARRAY_SIZE(proxstream2_groups),
+ .functions = proxstream2_functions,
+ .functions_count = ARRAY_SIZE(proxstream2_functions),
+ .mux_bits = 8,
+ .reg_stride = 4,
+ .load_pinctrl = false,
+};
+
+static int proxstream2_pinctrl_probe(struct udevice *dev)
+{
+ return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata);
+}
+
+static const struct udevice_id proxstream2_pinctrl_match[] = {
+ { .compatible = "socionext,proxstream2-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(proxstream2_pinctrl) = {
+ .name = "proxstream2-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(proxstream2_pinctrl_match),
+ .probe = proxstream2_pinctrl_probe,
+ .remove = uniphier_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
+ .ops = &uniphier_pinctrl_ops,
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->socdata->groups_count;
+}
+
+static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
+ unsigned selector)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->socdata->groups[selector].name;
+}
+
+static int uniphier_pinmux_get_functions_count(struct udevice *dev)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->socdata->functions_count;
+}
+
+static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
+ unsigned selector)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->socdata->functions[selector];
+}
+
+static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ int pins_count = priv->socdata->pins_count;
+ const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
+ int i;
+
+ for (i = 0; i < pins_count; i++) {
+ if (pins[i].number == pin) {
+ unsigned int iectrl;
+ u32 tmp;
+
+ iectrl = uniphier_pin_get_iectrl(pins[i].data);
+ tmp = readl(priv->base + UNIPHIER_PINCTRL_IECTRL);
+ tmp |= 1 << iectrl;
+ writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL);
+ }
+ }
+}
+
+static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
+ unsigned muxval)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned mux_bits = priv->socdata->mux_bits;
+ unsigned reg_stride = priv->socdata->reg_stride;
+ unsigned reg, reg_end, shift, mask;
+ u32 tmp;
+
+ reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
+ reg_end = reg + reg_stride;
+ shift = pin * mux_bits % 32;
+ mask = (1U << mux_bits) - 1;
+
+ /*
+ * If reg_stride is greater than 4, the MSB of each pinsel shall be
+ * stored in the offset+4.
+ */
+ for (; reg < reg_end; reg += 4) {
+ tmp = readl(priv->base + reg);
+ tmp &= ~(mask << shift);
+ tmp |= (mask & muxval) << shift;
+ writel(tmp, priv->base + reg);
+
+ muxval >>= mux_bits;
+ }
+
+ if (priv->socdata->load_pinctrl)
+ writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
+
+ /* some pins need input-enabling */
+ uniphier_pinconf_input_enable(dev, pin);
+}
+
+static int uniphier_pinmux_group_set(struct udevice *dev,
+ unsigned group_selector,
+ unsigned func_selector)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct uniphier_pinctrl_group *grp =
+ &priv->socdata->groups[group_selector];
+ int i;
+
+ for (i = 0; i < grp->num_pins; i++)
+ uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]);
+
+ return 0;
+}
+
+const struct pinctrl_ops uniphier_pinctrl_ops = {
+ .get_groups_count = uniphier_pinctrl_get_groups_count,
+ .get_group_name = uniphier_pinctrl_get_group_name,
+ .get_functions_count = uniphier_pinmux_get_functions_count,
+ .get_function_name = uniphier_pinmux_get_function_name,
+ .pinmux_group_set = uniphier_pinmux_group_set,
+ .set_state = pinctrl_generic_set_state,
+};
+
+int uniphier_pinctrl_probe(struct udevice *dev,
+ struct uniphier_pinctrl_socdata *socdata)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
+ &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = map_sysmem(addr, size);
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->socdata = socdata;
+
+ return 0;
+}
+
+int uniphier_pinctrl_remove(struct udevice *dev)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+ unmap_sysmem(priv->base);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PINCTRL_UNIPHIER_H__
+#define __PINCTRL_UNIPHIER_H__
+
+/* TODO: move this to include/linux/bug.h */
+#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); }))
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
+#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
+#define UNIPHIER_PINCTRL_IECTRL 0xd00
+
+#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl)
+
+static inline unsigned int uniphier_pin_get_iectrl(unsigned long data)
+{
+ return data;
+}
+
+/**
+ * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
+ *
+ * @number: pin number
+ * @data: additional per-pin data
+ */
+struct uniphier_pinctrl_pin {
+ unsigned number;
+ unsigned long data;
+};
+
+/**
+ * struct uniphier_pinctrl_group - pin group data for UniPhier SoC
+ *
+ * @name: pin group name
+ * @pins: array of pins that belong to the group
+ * @num_pins: number of pins in the group
+ * @muxvals: array of values to be set to pinmux registers
+ */
+struct uniphier_pinctrl_group {
+ const char *name;
+ const unsigned *pins;
+ unsigned num_pins;
+ const unsigned *muxvals;
+};
+
+/**
+ * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller
+ *
+ * @pins: array of pin data
+ * @pins_count: number of pin data
+ * @groups: array of pin group data
+ * @groups_count: number of pin group data
+ * @functions: array of pinmux function names
+ * @functions_count: number of pinmux functions
+ * @mux_bits: bit width of each pinmux register
+ * @reg_stride: stride of pinmux register address
+ * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new
+ * values in pinmux registers to become really effective
+ */
+struct uniphier_pinctrl_socdata {
+ const struct uniphier_pinctrl_pin *pins;
+ int pins_count;
+ const struct uniphier_pinctrl_group *groups;
+ int groups_count;
+ const char * const *functions;
+ int functions_count;
+ unsigned mux_bits;
+ unsigned reg_stride;
+ bool load_pinctrl;
+};
+
+#define UNIPHIER_PINCTRL_PIN(a, b) \
+{ \
+ .number = a, \
+ .data = UNIPHIER_PIN_ATTR_PACKED(b), \
+}
+
+#define UNIPHIER_PINCTRL_GROUP(grp) \
+ { \
+ .name = #grp, \
+ .pins = grp##_pins, \
+ .num_pins = ARRAY_SIZE(grp##_pins), \
+ .muxvals = grp##_muxvals + \
+ BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
+ ARRAY_SIZE(grp##_muxvals)), \
+ }
+
+/**
+ * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
+ *
+ * @base: base address of the pinctrl device
+ * @socdata: SoC specific data
+ */
+struct uniphier_pinctrl_priv {
+ void __iomem *base;
+ struct uniphier_pinctrl_socdata *socdata;
+};
+
+extern const struct pinctrl_ops uniphier_pinctrl_ops;
+
+int uniphier_pinctrl_probe(struct udevice *dev,
+ struct uniphier_pinctrl_socdata *socdata);
+
+int uniphier_pinctrl_remove(struct udevice *dev);
+
+#endif /* __PINCTRL_UNIPHIER_H__ */
config ROCKCHIP_SERIAL
bool "Rockchip on-chip UART support"
- depends on ARCH_UNIPHIER && DM_SERIAL
+ depends on ARCH_ROCKCHIP && DM_SERIAL
help
Select this to enable a debug UART for Rockchip devices. This uses
the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
writel(0, ®s->pl010_cr);
break;
case TYPE_PL011:
-#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- /* Empty RX fifo if necessary */
- if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
- while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
- readl(®s->dr);
- }
-#endif
/* disable everything */
writel(0, ®s->pl011_cr);
break;
* control register write
*/
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
-#ifdef CONFIG_PL011_SERIAL_RLCR
- {
- int i;
-
- /*
- * Program receive line control register after waiting
- * 10 bus cycles. Delay be writing to readonly register
- * 10 times
- */
- for (i = 0; i < 10; i++)
- writel(lcr, ®s->fr);
-
- writel(lcr, ®s->pl011_rlcr);
- }
-#endif
writel(lcr, ®s->pl011_lcrh);
return 0;
}
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
-# define SCIF_ORER 0x0001
+# if defined(CONFIG_SCIF_A)
+# define SCIF_ORER 0x0200
+# else
+# define SCIF_ORER 0x0001
+# endif
# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
-# define SCIF_RFDC_MASK 0x003f
+# if defined(CONFIG_SCIF_A)
+# define SCIF_RFDC_MASK 0x007f
+# else
+# define SCIF_RFDC_MASK 0x001f
+# endif
#else
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x001f
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCLSR, 0x24, 16)
SCIF_FNS(DL, 0x00, 0) /* dummy */
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+/* SCIFA and SCIF register offsets and size */
+SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
+SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
+SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
+SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
+SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
+SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
+SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
+SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
+SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
+SCIF_FNS(DL, 0, 0, 0x30, 16)
+SCIF_FNS(CKS, 0, 0, 0x34, 16)
+#if defined(CONFIG_SCIF_A)
+SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
+#else
+SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
+#endif
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
#endif
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
-#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
-SCIF_FNS(DL, 0, 0, 0x30, 16)
-SCIF_FNS(CKS, 0, 0, 0x34, 16)
-#else
SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
#endif
-#endif
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
-#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
+ #if defined(CONFIG_SCIF_A)
+ #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
+ #else
+ #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
+ #endif
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#define BIT(x) (1 << (x))
-
/* SPIGCR0 */
#define SPIGCR0_SPIENA_MASK 0x1
#define SPIGCR0_SPIRST_MASK 0x0
#include <asm/arch/ep93xx.h>
-
-#define BIT(x) (1<<(x))
#define SSPBASE SPI_BASE
#define SSPCR0 0x0000
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#define SLINK_CMD_ENB (1 << 31)
#define SLINK_CMD_GO (1 << 30)
#define SLINK_CMD_M_S (1 << 28)
+#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
+#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24)
+#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
+#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
+#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
#define SLINK_CMD_CK_SDA (1 << 21)
#define SLINK_CMD_CS_POL (1 << 13)
#define SLINK_CMD_CS_VAL (1 << 12)
static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
{
struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
+ u32 reg;
+
+ reg = readl(®s->command);
+
+ /* Set CPOL and CPHA */
+ reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
+ if (mode & SPI_CPHA)
+ reg |= SLINK_CMD_CK_SDA;
+
+ if (mode & SPI_CPOL)
+ reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
+ else
+ reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
+
+ writel(reg, ®s->command);
priv->mode = mode;
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
priv->freq = speed;
- debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs,
+ debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
priv->freq);
return 0;
uint32_t spicr;
spicr = readl(®s->spicr);
- if (priv->mode & SPI_LSB_FIRST)
+ if (mode & SPI_LSB_FIRST)
spicr |= SPICR_LSB_FIRST;
- if (priv->mode & SPI_CPHA)
+ if (mode & SPI_CPHA)
spicr |= SPICR_CPHA;
- if (priv->mode & SPI_CPOL)
+ if (mode & SPI_CPOL)
spicr |= SPICR_CPOL;
- if (priv->mode & SPI_LOOP)
+ if (mode & SPI_LOOP)
spicr |= SPICR_LOOP;
writel(spicr, ®s->spicr);
writel(confr, ®s->cr);
priv->freq = speed;
- debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
+ debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
+ priv->regs, priv->freq);
return 0;
}
confr = readl(®s->cr);
confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
- if (priv->mode & SPI_CPHA)
+ if (mode & SPI_CPHA)
confr |= ZYNQ_SPI_CR_CPHA_MASK;
- if (priv->mode & SPI_CPOL)
+ if (mode & SPI_CPOL)
confr |= ZYNQ_SPI_CR_CPOL_MASK;
writel(confr, ®s->cr);
#
obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
-obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o
+obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
#define FACTOR1 15976
#define FACTOR2 4297157
#define MEASURE_FREQ 327
+#define TEMPERATURE_MIN -40
+#define TEMPERATURE_HOT 85
+#define TEMPERATURE_MAX 125
#define TEMPSENSE0_TEMP_CNT_SHIFT 8
#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
int maxc;
};
+#if defined(CONFIG_MX6)
static int read_cpu_temperature(struct udevice *dev)
{
int temperature;
return temperature;
}
+#elif defined(CONFIG_MX7)
+static int read_cpu_temperature(struct udevice *dev)
+{
+ unsigned int reg, tmp, start;
+ unsigned int raw_25c, te1;
+ int temperature;
+ unsigned int *priv = dev_get_priv(dev);
+ u32 fuse = *priv;
+ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+ /*
+ * fuse data layout:
+ * [31:21] sensor value @ 25C
+ * [20:18] hot temperature value
+ * [17:9] sensor value of room
+ * [8:0] sensor value of hot
+ */
+
+ raw_25c = fuse >> 21;
+ if (raw_25c == 0)
+ raw_25c = 25;
+
+ te1 = (fuse >> 9) & 0x1ff;
+
+ /*
+ * now we only use single measure, every time we read
+ * the temperature, we will power on/down anadig thermal
+ * module
+ */
+ writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr);
+ writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set);
+
+ /* write measure freq */
+ reg = readl(&ccm_anatop->tempsense1);
+ reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK;
+ reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ);
+ writel(reg, &ccm_anatop->tempsense1);
+
+ writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr);
+ writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
+ writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
+
+ start = get_timer(0);
+ /* Wait max 100ms */
+ do {
+ /*
+ * Since we can not rely on finish bit, use 1ms delay to get
+ * temperature. From RM, 17us is enough to get data, but
+ * to gurantee to get the data, delay 100ms here.
+ */
+ reg = readl(&ccm_anatop->tempsense1);
+ tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+ >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
+ } while (get_timer(0) < (start + 100));
+
+ writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
+
+ /* power down anatop thermal sensor */
+ writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_set);
+ writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_clr);
+
+ /* Single point */
+ temperature = tmp - (te1 - raw_25c);
+
+ return temperature;
+}
+#endif
int imx_thermal_get_temp(struct udevice *dev, int *temp)
{
int cpu_tmp = 0;
cpu_tmp = read_cpu_temperature(dev);
+
while (cpu_tmp >= priv->critical) {
printf("CPU Temperature (%dC) too close to max (%dC)",
cpu_tmp, priv->maxc);
/* Read Temperature calibration data fuse */
fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
- /* Check for valid fuse */
- if (fuse == 0 || fuse == ~0) {
- printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
- return -EPERM;
+ if (is_soc_type(MXC_SOC_MX6)) {
+ /* Check for valid fuse */
+ if (fuse == 0 || fuse == ~0) {
+ debug("CPU: Thermal invalid data, fuse: 0x%x\n",
+ fuse);
+ return -EPERM;
+ }
+ } else if (is_soc_type(MXC_SOC_MX7)) {
+ /* No Calibration data in FUSE? */
+ if ((fuse & 0x3ffff) == 0)
+ return -EPERM;
+ /* We do not support 105C TE2 */
+ if (((fuse & 0x1c0000) >> 18) == 0x6)
+ return -EPERM;
}
/* set critical cooling temp */
#include <dm.h>
#include <usb.h>
#include <malloc.h>
+#include <memalign.h>
#include <linux/mii.h>
#include "usb_ether.h"
#include <linux/mii.h>
#include "usb_ether.h"
#include <malloc.h>
+#include <memalign.h>
#include <errno.h>
/* ASIX AX88179 based USB 3.0 Ethernet Devices */
#include <errno.h>
#include <linux/mii.h>
#include <malloc.h>
+#include <memalign.h>
#include <usb.h>
#include "usb_ether.h"
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <memalign.h>
#include <usb.h>
#include <asm/unaligned.h>
#include <linux/mii.h>
static int ci_ep_disable(struct usb_ep *ep);
static int ci_ep_queue(struct usb_ep *ep,
struct usb_request *req, gfp_t gfp_flags);
+static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req);
static struct usb_request *
ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
.enable = ci_ep_enable,
.disable = ci_ep_disable,
.queue = ci_ep_queue,
+ .dequeue = ci_ep_dequeue,
.alloc_request = ci_ep_alloc_request,
.free_request = ci_ep_free_request,
};
int bit, num, len, in;
struct ci_req *ci_req;
u8 *buf;
- uint32_t length, actlen;
+ uint32_t len_left, len_this_dtd;
struct ept_queue_item *dtd, *qtd;
ci_ep->req_primed = true;
ci_req->dtd_count = 0;
buf = ci_req->hw_buf;
- actlen = 0;
+ len_left = len;
dtd = item;
do {
- length = min(ci_req->req.length - actlen,
- (unsigned)EP_MAX_LENGTH_TRANSFER);
+ len_this_dtd = min(len_left, (unsigned)EP_MAX_LENGTH_TRANSFER);
- dtd->info = INFO_BYTES(length) | INFO_ACTIVE;
+ dtd->info = INFO_BYTES(len_this_dtd) | INFO_ACTIVE;
dtd->page0 = (unsigned long)buf;
dtd->page1 = ((unsigned long)buf & 0xfffff000) + 0x1000;
dtd->page2 = ((unsigned long)buf & 0xfffff000) + 0x2000;
dtd->page3 = ((unsigned long)buf & 0xfffff000) + 0x3000;
dtd->page4 = ((unsigned long)buf & 0xfffff000) + 0x4000;
- len -= length;
- actlen += length;
- buf += length;
+ len_left -= len_this_dtd;
+ buf += len_this_dtd;
- if (len) {
+ if (len_left) {
qtd = (struct ept_queue_item *)
memalign(ILIST_ALIGN, ILIST_ENT_SZ);
dtd->next = (unsigned long)qtd;
}
ci_req->dtd_count++;
- } while (len);
+ } while (len_left);
item = dtd;
/*
writel(bit, &udc->epprime);
}
+static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep);
+ struct ci_req *ci_req;
+
+ list_for_each_entry(ci_req, &ci_ep->queue, queue) {
+ if (&ci_req->req == _req)
+ break;
+ }
+
+ if (&ci_req->req != _req)
+ return -EINVAL;
+
+ list_del_init(&ci_req->queue);
+
+ if (ci_req->req.status == -EINPROGRESS) {
+ ci_req->req.status = -ECONNRESET;
+ if (ci_req->req.complete)
+ ci_req->req.complete(_ep, _req);
+ }
+
+ return 0;
+}
+
static int ci_ep_queue(struct usb_ep *ep,
struct usb_request *req, gfp_t gfp_flags)
{
debug("unbind config '%s'/%p\n", c->label, c);
c->unbind(c);
}
+ free(c);
}
if (composite->unbind)
composite->unbind(cdev);
#include <net.h>
#include <usb.h>
#include <malloc.h>
+#include <memalign.h>
#include <linux/ctype.h>
#include "gadget_chips.h"
#include <errno.h>
#include <common.h>
#include <malloc.h>
+#include <memalign.h>
#include <version.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
{
struct usb_gadget *gadget = cdev->gadget;
- free(cdev->config);
- cdev->config = NULL;
debug("%s: calling usb_gadget_disconnect for "
"controller '%s'\n", __func__, gadget->name);
usb_gadget_disconnect(gadget);
#include <errno.h>
#include <usb.h>
#include <malloc.h>
+#include <memalign.h>
#include <phys2bus.h>
#include <usbroothubdes.h>
#include <asm/io.h>
#include <usb.h>
#include <asm/io.h>
#include <malloc.h>
+#include <memalign.h>
#include <watchdog.h>
#include <linux/compiler.h>
#endif
#include <malloc.h>
+#include <memalign.h>
#include <usb.h>
#include "ohci.h"
#include <common.h>
#include <dm.h>
#include <errno.h>
+#include <memalign.h>
#include <usb.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
- defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
+ defined(CONFIG_ARCH_OMAP4)
static irqreturn_t generic_interrupt(int irq, void *__hci)
{
#include <i2c.h>
#include "anx9804.h"
-#define BIT(x) (1 << (x))
-
/* Registers at i2c address 0x38 */
#define ANX9804_HDCP_CONTROL_0_REG 0x01
#include <common.h>
#include <lcd.h>
+#include <memalign.h>
#include <asm/arch/mbox.h>
#include <asm/global_data.h>
board_disp_init ();
#endif
-#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
+#if (defined(CONFIG_LWMON5) || \
+ defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
/* Lamp on */
board_backlight_switch (1);
#endif
obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610))
obj-y += imx_watchdog.o
endif
obj-$(CONFIG_S5P) += s5p_wdt.o
#include <asm/io.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
-
-struct watchdog_regs {
- u16 wcr; /* Control */
- u16 wsr; /* Service */
- u16 wrsr; /* Reset Status */
-};
-
-#define WCR_WDZST 0x01
-#define WCR_WDBG 0x02
-#define WCR_WDE 0x04 /* WDOG enable */
-#define WCR_WDT 0x08
-#define WCR_SRS 0x10
-#define SET_WCR_WT(x) (x << 8)
+#include <fsl_wdog.h>
#ifdef CONFIG_IMX_WATCHDOG
void hw_watchdog_reset(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- writew(WCR_WDE, &wdog->wcr);
+ clrsetbits_le16(&wdog->wcr, 0, WCR_WDE);
+
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
while (1) {
bool "Embedded DTB for DT control"
help
If this option is enabled, the device tree will be picked up and
- built into the U-Boot image.
+ built into the U-Boot image. This is suitable for local debugging
+ and development only and is not recommended for production devices.
+ Boards in the mainline U-Boot tree should not use it.
config OF_HOSTFILE
bool "Host filed DTB for DT control"
config OF_SPL_REMOVE_PROPS
string "List of device tree properties to drop for SPL"
depends on SPL_OF_CONTROL
+ default "clocks clock-names interrupt-parent" if SPL_PINCTRL_FULL
default "pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
help
Since SPL normally runs in a reduced memory space, the device tree
#include <common.h>
#include <config.h>
+#include <memalign.h>
#include <ext4fs.h>
#include <ext_common.h>
#include "ext4_common.h"
#include <ext4fs.h>
#include <inttypes.h>
#include <malloc.h>
+#include <memalign.h>
#include <stddef.h>
#include <linux/stat.h>
#include <linux/time.h>
arr[i] = zalloc(strlen("/") + 1);
if (!arr[i])
return -ENOMEM;
-
- arr[i++] = "/";
+ memcpy(arr[i++], "/", strlen("/"));
/* add each path entry after root */
while (token != NULL) {
fail:
free(depth_dirname);
free(parse_dirname);
+ for (i = 0; i < depth; i++) {
+ if (!ptr[i])
+ break;
+ free(ptr[i]);
+ }
free(ptr);
free(parent_inode);
free(first_inode);
struct ext2_dirent *previous_dir = NULL;
char *ptr = NULL;
struct ext_filesystem *fs = get_fs();
+ int ret = -1;
/* get the first block of root */
first_block_no_of_root = blknr;
if (ext4fs_put_metadata(root_first_block_addr,
first_block_no_of_root))
goto fail;
- return inodeno;
+ ret = inodeno;
}
fail:
free(root_first_block_buffer);
- return -1;
+ return ret;
}
int ext4fs_filename_check(char *filename)
status = ext4fs_read_file(diro, 0,
__le32_to_cpu(diro->inode.size),
symlink, &actread);
- if (status == 0) {
+ if ((status < 0) || (actread == 0)) {
free(symlink);
return 0;
}
#include <common.h>
+#include <memalign.h>
#include <linux/stat.h>
#include <div64.h>
#include "ext4_common.h"
return -1;
}
- /* mount the filesystem */
- if (!ext4fs_mount(0)) {
- printf("** Error Bad ext4 partition **\n");
- goto fail;
- }
-
ret = ext4fs_write(filename, buf, len);
-
if (ret) {
printf("** Error ext4fs_write() **\n");
goto fail;
}
- ext4fs_close();
*actwrite = len;
return 0;
fail:
- ext4fs_close();
*actwrite = 0;
return -1;
#include <asm/byteorder.h>
#include <part.h>
#include <malloc.h>
+#include <memalign.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
static int disk_read(__u32 block, __u32 nr_blocks, void *buf)
{
+ ulong ret;
+
if (!cur_dev || !cur_dev->block_read)
return -1;
- return cur_dev->block_read(cur_dev->dev,
- cur_part_info.start + block, nr_blocks, buf);
+ ret = cur_dev->block_read(cur_dev->dev,
+ cur_part_info.start + block, nr_blocks, buf);
+
+ if (nr_blocks && ret == 0)
+ return -1;
+
+ return ret;
}
int fat_set_blk_dev(block_dev_desc_t *dev_desc, disk_partition_t *info)
strcpy(fnamecopy, filename);
downcase(fnamecopy);
+root_reparse:
if (*fnamecopy == '\0') {
if (!dols)
goto exit;
if (isdir && !(dentptr->attr & ATTR_DIR))
goto exit;
+ /*
+ * If we are looking for a directory, and found a directory
+ * type entry, and the entry is for the root directory (as
+ * denoted by a cluster number of 0), jump back to the start
+ * of the function, since at least on FAT12/16, the root dir
+ * lives in a hard-coded location and needs special handling
+ * to parse, rather than simply following the cluster linked
+ * list in the FAT, like other directories.
+ */
+ if (isdir && (dentptr->attr & ATTR_DIR) && !START(dentptr)) {
+ /*
+ * Modify the filename to remove the prefix that gets
+ * back to the root directory, so the initial root dir
+ * parsing code can continue from where we are without
+ * confusion.
+ */
+ strcpy(fnamecopy, nextname ?: "");
+ /*
+ * Set up state the same way as the function does when
+ * first started. This is required for the root dir
+ * parsing code operates in its expected environment.
+ */
+ subname = "";
+ cursect = mydata->rootdir_sect;
+ isdir = 0;
+ goto root_reparse;
+ }
+
if (idx >= 0)
subname = nextname;
}
static int total_sector;
static int disk_write(__u32 block, __u32 nr_blocks, void *buf)
{
+ ulong ret;
+
if (!cur_dev || !cur_dev->block_write)
return -1;
return -1;
}
- return cur_dev->block_write(cur_dev->dev,
- cur_part_info.start + block, nr_blocks, buf);
+ ret = cur_dev->block_write(cur_dev->dev,
+ cur_part_info.start + block,
+ nr_blocks, buf);
+ if (nr_blocks && ret == 0)
+ return -1;
+
+ return ret;
}
/*
set_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer,
unsigned long size)
{
- int idx = 0;
+ __u32 idx = 0;
__u32 startsect;
+ int ret;
if (clustnum > 0)
startsect = mydata->data_begin +
debug("clustnum: %d, startsect: %d\n", clustnum, startsect);
- if ((size / mydata->sect_size) > 0) {
- if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) {
- debug("Error writing data\n");
+ if ((unsigned long)buffer & (ARCH_DMA_MINALIGN - 1)) {
+ ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
+
+ printf("FAT: Misaligned buffer address (%p)\n", buffer);
+
+ while (size >= mydata->sect_size) {
+ memcpy(tmpbuf, buffer, mydata->sect_size);
+ ret = disk_write(startsect++, 1, tmpbuf);
+ if (ret != 1) {
+ debug("Error writing data (got %d)\n", ret);
+ return -1;
+ }
+
+ buffer += mydata->sect_size;
+ size -= mydata->sect_size;
+ }
+ } else if (size >= mydata->sect_size) {
+ idx = size / mydata->sect_size;
+ ret = disk_write(startsect, idx, buffer);
+ if (ret != idx) {
+ debug("Error writing data (got %d)\n", ret);
return -1;
}
- }
- if (size % mydata->sect_size) {
- __u8 tmpbuf[mydata->sect_size];
+ startsect += idx;
+ idx *= mydata->sect_size;
+ buffer += idx;
+ size -= idx;
+ }
- idx = size / mydata->sect_size;
- buffer += idx * mydata->sect_size;
- memcpy(tmpbuf, buffer, size % mydata->sect_size);
+ if (size) {
+ ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
- if (disk_write(startsect + idx, 1, tmpbuf) < 0) {
- debug("Error writing data\n");
+ memcpy(tmpbuf, buffer, size);
+ ret = disk_write(startsect, 1, tmpbuf);
+ if (ret != 1) {
+ debug("Error writing data (got %d)\n", ret);
return -1;
}
-
- return 0;
}
return 0;
debug("%llu bytes\n", filesize);
+ if (!curclust) {
+ if (filesize) {
+ debug("error: nonempty clusterless file!\n");
+ return -1;
+ }
+ return 0;
+ }
+
actsize = bytesperclust;
endclust = curclust;
do {
goto getit;
if (CHECK_CLUST(newclust, mydata->fatsize)) {
- debug("curclust: 0x%x\n", newclust);
+ debug("newclust: 0x%x\n", newclust);
debug("Invalid FAT entry\n");
return 0;
}
endclust = newclust;
actsize += bytesperclust;
}
- /* actsize >= file size */
- actsize -= bytesperclust;
- /* set remaining clusters */
- if (set_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
- debug("error: writing cluster\n");
- return -1;
- }
/* set remaining bytes */
- *gotsize += actsize;
- filesize -= actsize;
- buffer += actsize;
actsize = filesize;
-
- if (set_cluster(mydata, endclust, buffer, (int)actsize) != 0) {
+ if (set_cluster(mydata, curclust, buffer, (int)actsize) != 0) {
debug("error: writing cluster\n");
return -1;
}
filesize -= actsize;
buffer += actsize;
- if (CHECK_CLUST(curclust, mydata->fatsize)) {
- debug("curclust: 0x%x\n", curclust);
+ if (CHECK_CLUST(newclust, mydata->fatsize)) {
+ debug("newclust: 0x%x\n", newclust);
debug("Invalid FAT entry\n");
return 0;
}
}
/*
- * Fill dir_entry
+ * Set start cluster in directory entry
*/
-static void fill_dentry(fsdata *mydata, dir_entry *dentptr,
- const char *filename, __u32 start_cluster, __u32 size, __u8 attr)
+static void set_start_cluster(const fsdata *mydata, dir_entry *dentptr,
+ __u32 start_cluster)
{
if (mydata->fatsize == 32)
dentptr->starthi =
cpu_to_le16((start_cluster & 0xffff0000) >> 16);
dentptr->start = cpu_to_le16(start_cluster & 0xffff);
+}
+
+/*
+ * Fill dir_entry
+ */
+static void fill_dentry(fsdata *mydata, dir_entry *dentptr,
+ const char *filename, __u32 start_cluster, __u32 size, __u8 attr)
+{
+ set_start_cluster(mydata, dentptr, start_cluster);
dentptr->size = cpu_to_le32(size);
dentptr->attr = attr;
if (retdent) {
/* Update file size and start_cluster in a directory entry */
retdent->size = cpu_to_le32(size);
- start_cluster = FAT2CPU16(retdent->start);
- if (mydata->fatsize == 32)
- start_cluster |=
- (FAT2CPU16(retdent->starthi) << 16);
-
- ret = check_overflow(mydata, start_cluster, size);
- if (ret) {
- printf("Error: %llu overflow\n", size);
- goto exit;
- }
+ start_cluster = START(retdent);
+
+ if (start_cluster) {
+ if (size) {
+ ret = check_overflow(mydata, start_cluster,
+ size);
+ if (ret) {
+ printf("Error: %llu overflow\n", size);
+ goto exit;
+ }
+ }
- ret = clear_fatent(mydata, start_cluster);
- if (ret) {
- printf("Error: clearing FAT entries\n");
- goto exit;
- }
+ ret = clear_fatent(mydata, start_cluster);
+ if (ret) {
+ printf("Error: clearing FAT entries\n");
+ goto exit;
+ }
- ret = set_contents(mydata, retdent, buffer, size, actwrite);
- if (ret < 0) {
- printf("Error: writing contents\n");
- goto exit;
- }
- debug("attempt to write 0x%llx bytes\n", *actwrite);
+ if (!size)
+ set_start_cluster(mydata, retdent, 0);
+ } else if (size) {
+ ret = start_cluster = find_empty_cluster(mydata);
+ if (ret < 0) {
+ printf("Error: finding empty cluster\n");
+ goto exit;
+ }
- /* Flush fat buffer */
- ret = flush_fat_buffer(mydata);
- if (ret) {
- printf("Error: flush fat buffer\n");
- goto exit;
- }
+ ret = check_overflow(mydata, start_cluster, size);
+ if (ret) {
+ printf("Error: %llu overflow\n", size);
+ goto exit;
+ }
- /* Write directory table to device */
- ret = set_cluster(mydata, dir_curclust,
- get_dentfromdir_block,
- mydata->clust_size * mydata->sect_size);
- if (ret) {
- printf("Error: writing directory entry\n");
- goto exit;
+ set_start_cluster(mydata, retdent, start_cluster);
}
} else {
/* Set short name to set alias checksum field in dir_slot */
set_name(empty_dentptr, filename);
fill_dir_slot(mydata, &empty_dentptr, filename);
- ret = start_cluster = find_empty_cluster(mydata);
- if (ret < 0) {
- printf("Error: finding empty cluster\n");
- goto exit;
- }
+ if (size) {
+ ret = start_cluster = find_empty_cluster(mydata);
+ if (ret < 0) {
+ printf("Error: finding empty cluster\n");
+ goto exit;
+ }
- ret = check_overflow(mydata, start_cluster, size);
- if (ret) {
- printf("Error: %llu overflow\n", size);
- goto exit;
+ ret = check_overflow(mydata, start_cluster, size);
+ if (ret) {
+ printf("Error: %llu overflow\n", size);
+ goto exit;
+ }
+ } else {
+ start_cluster = 0;
}
/* Set attribute as archieve for regular file */
fill_dentry(mydata, empty_dentptr, filename,
start_cluster, size, 0x20);
- ret = set_contents(mydata, empty_dentptr, buffer, size,
- actwrite);
- if (ret < 0) {
- printf("Error: writing contents\n");
- goto exit;
- }
- debug("attempt to write 0x%llx bytes\n", *actwrite);
+ retdent = empty_dentptr;
+ }
- /* Flush fat buffer */
- ret = flush_fat_buffer(mydata);
- if (ret) {
- printf("Error: flush fat buffer\n");
- goto exit;
- }
+ ret = set_contents(mydata, retdent, buffer, size, actwrite);
+ if (ret < 0) {
+ printf("Error: writing contents\n");
+ goto exit;
+ }
+ debug("attempt to write 0x%llx bytes\n", *actwrite);
- /* Write directory table to device */
- ret = set_cluster(mydata, dir_curclust,
- get_dentfromdir_block,
- mydata->clust_size * mydata->sect_size);
- if (ret) {
- printf("Error: writing directory entry\n");
- goto exit;
- }
+ /* Flush fat buffer */
+ ret = flush_fat_buffer(mydata);
+ if (ret) {
+ printf("Error: flush fat buffer\n");
+ goto exit;
}
+ /* Write directory table to device */
+ ret = set_cluster(mydata, dir_curclust, get_dentfromdir_block,
+ mydata->clust_size * mydata->sect_size);
+ if (ret)
+ printf("Error: writing directory entry\n");
+
exit:
free(mydata->fatbuf);
return ret;
#include <linux/writeback.h>
#else
+#include <common.h>
+#include <malloc.h>
+#include <memalign.h>
#include <linux/compat.h>
#include <linux/stat.h>
#include <linux/err.h>
* Adrian Hunter
*/
+#include <common.h>
+#include <memalign.h>
#include "ubifs.h"
#include <u-boot/zlib.h>
* old = bitfield_extract(old_reg_val, 10, 5);
* new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
*
+ * or
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract_by_mask(old_reg_val, mask);
+ * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new);
+ *
* The numbers 10 and 5 could for example come from data
* tables which describe all bitfields in all registers.
*/
return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
}
+
+/* Produces a shift of the bitfield given a mask */
+static inline uint bitfield_shift(uint mask)
+{
+ return mask ? ffs(mask) - 1 : 0;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract_by_mask(uint reg_val, uint mask)
+{
+ uint shift = bitfield_shift(mask);
+
+ return (reg_val & mask) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace_by_mask(uint reg_val, uint mask,
+ uint bitfield_val)
+{
+ uint shift = bitfield_shift(mask);
+
+ return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
+}
u64 startoffs,
u64 szexpected);
+/* lib/lz4_wrapper.c */
+int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn);
+
/* lib/qsort.c */
void qsort(void *base, size_t nmemb, size_t size,
int(*compar)(const void *, const void *));
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
-/*
- * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
- * is used to align DMA buffers.
- */
-#ifndef __ASSEMBLY__
-#include <asm/cache.h>
-#endif
-
-/*
- * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
- * stack that meets the minimum architecture alignment requirements for DMA.
- * Such a buffer is useful for DMA operations where flushing and invalidating
- * the cache before and after a read and/or write operation is required for
- * correct operations.
- *
- * When called the macro creates an array on the stack that is sized such
- * that:
- *
- * 1) The beginning of the array can be advanced enough to be aligned.
- *
- * 2) The size of the aligned portion of the array is a multiple of the minimum
- * architecture alignment required for DMA.
- *
- * 3) The aligned portion contains enough space for the original number of
- * elements requested.
- *
- * The macro then creates a pointer to the aligned portion of this array and
- * assigns to the pointer the address of the first element in the aligned
- * portion of the array.
- *
- * Calling the macro as:
- *
- * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
- *
- * Will result in something similar to saying:
- *
- * uint32_t buffer[1024];
- *
- * The following differences exist:
- *
- * 1) The resulting buffer is guaranteed to be aligned to the value of
- * ARCH_DMA_MINALIGN.
- *
- * 2) The buffer variable created by the macro is a pointer to the specified
- * type, and NOT an array of the specified type. This can be very important
- * if you want the address of the buffer, which you probably do, to pass it
- * to the DMA hardware. The value of &buffer is different in the two cases.
- * In the macro case it will be the address of the pointer, not the address
- * of the space reserved for the buffer. However, in the second case it
- * would be the address of the buffer. So if you are replacing hard coded
- * stack buffers with this macro you need to make sure you remove the & from
- * the locations where you are taking the address of the buffer.
- *
- * Note that the size parameter is the number of array elements to allocate,
- * not the number of bytes.
- *
- * This macro can not be used outside of function scope, or for the creation
- * of a function scoped static buffer. It can not be used to create a cache
- * line aligned global buffer.
- */
-#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1)
-#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad)
-#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \
- char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \
- + (align - 1)]; \
- \
- type *name = (type *) ALIGN((uintptr_t)__##name, align)
-#define ALLOC_ALIGN_BUFFER(type, name, size, align) \
- ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1)
-#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \
- ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
-#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \
- ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
-
-/*
- * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's
- * purpose is to allow allocating aligned buffers outside of function scope.
- * Usage of this macro shall be avoided or used with extreme care!
- */
-#define DEFINE_ALIGN_BUFFER(type, name, size, align) \
- static char __##name[ALIGN(size * sizeof(type), align)] \
- __aligned(align); \
- \
- static type *name = (type *)__##name
-#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \
- DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
-
-#ifndef __ASSEMBLY__
-#include <malloc.h>
-
-static inline void *malloc_cache_aligned(size_t size)
-{
- return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN));
-}
-#endif
-
/*
* check_member() - Check the offset of a structure member
*
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
-#define CONFIG_SYS_NAND_QUIET_TEST 1
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
#define CONFIG_VSC9953
-#define CONFIG_VSC9953_CMD
+#define CONFIG_CMD_ETHSW
#ifdef CONFIG_T1040RDB
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
"boot_fdt=try\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 ro\0" \
- "mmcrootfstype=ext4 rootwait\0" \
"ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
"spiroot=/dev/mtdblock4 rw\0" \
"spirootfstype=jffs2\0" \
"spisrcaddr=0xe0000\0" \
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcloados=run mmcargs; " \
+ "mmcloados=run args_mmc; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootz ${loadaddr} - ${fdtaddr}; " \
--- /dev/null
+/*
+ * am335x_sl50.h
+ *
+ * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_AM335X_EVM_H
+#define __CONFIG_AM335X_EVM_H
+
+#include <configs/ti_am335x_common.h>
+#undef CONFIG_BOOTDELAY
+
+#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_FIT
+# define CONFIG_FIT
+#endif
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+/*#define CONFIG_MACH_TYPE 3589 Until the next sync */
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+
+#include <config_distro_defaults.h>
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x80000000\0" \
+ "pxefile_addr_r=0x80100000\0" \
+ "kernel_addr_r=0x82000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "ramdisk_addr_r=0x88080000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1)
+
+#define AM335XX_BOARD_FDTFILE \
+ "fdtfile=am335x-sl50.dtb\0" \
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ AM335XX_BOARD_FDTFILE \
+ MEM_LAYOUT_ENV_SETTINGS \
+ BOOTENV
+
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_YMODEM_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_NAND
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
+#endif
+
+#if defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x0
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#endif /* ! __CONFIG_AM335X_SL50_H */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
"usbroot=/dev/sda2 rw\0" \
"usbrootfstype=ext4 rootwait\0" \
"usbdev=0\0" \
"ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
"usbargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${usbroot} " \
"if run loadimage; then " \
"run loadfdt; " \
"echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
+ "run args_mmc; " \
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi;" \
"fi;\0" \
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_PHYLIB
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0x7f
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
+/* CPU Errata */
+#define CONFIG_ARM_ERRATA_773022
+#define CONFIG_ARM_ERRATA_774769
+
/* Power */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_CMD_DHCP
#ifdef CONFIG_SYS_USE_MMC
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+/* Use raw reserved sectors to save environment */
+#define CONFIG_ENV_OFFSET 0x2000
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#else
/* u-boot env in sd/mmc card */
#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_FAT_WRITE
#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_SIZE 0x4000
+#endif
#define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \
"setenv dtb_name at91-${board_name}.dtb; " \
+++ /dev/null
-/*
- * Balloon3 configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_BALLOON3 1 /* Balloon3 board */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "fpga load 0x0 0x50000 0x62638; " \
- "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "bootm 0xd0000;"
-#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_STUART 1
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#undef CONFIG_CMD_ENV
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FPGA_LOADMK
-#undef CONFIG_LCD
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_IS_IN_FLASH
-#else
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE 0x000000
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
-#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
-#define CONFIG_SYS_GPSR2_VAL 0x7131c000
-#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
-
-#define CONFIG_SYS_GPCR0_VAL 0x0
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPCR3_VAL 0x0
-
-#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
-#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
-#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
-#define CONFIG_SYS_GPDR3_VAL 0x000201fe
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
-#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
-#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
-#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0xffffffff
-#define CONFIG_SYS_CCCR 0x00000290
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
-#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
-#define CONFIG_SYS_MSC2_VAL 0x74a42491
-#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
-#define CONFIG_SYS_MDREFR_VAL 0x001d8018
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_BALLOON3LCD
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#endif
-
-/*
- * FPGA
- */
-#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_WAIT 1000
-#define CONFIG_MAX_FPGA_DEVICES 1
-#endif
-
-#endif /* __CONFIG_H */
/* ------------------------------------------------------------------------- */
#define BUR_COMMON_ENV \
"usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \
-"defaultip=192.168.60.253\0" \
-"defaultsip=192.168.60.254\0" \
+"brdefaultip=if test -r ${ipaddr}; then; else" \
+" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \
+" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \
"netconsole=echo switching to network console ...; " \
-"if dhcp; then setenv ncip ${serverip}; " \
-"else " \
-"setenv ncip 192.168.60.254; setenv serverip 192.168.60.254; " \
-"setenv gatewayip 192.168.60.254; setenv ipaddr 192.168.60.1; " \
-"fi; " \
+"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \
"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \
"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \
"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+#define CONFIG_PREBOOT "run brdefaultip"
#define CONFIG_CMD_TIME
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_CMD_BMODE
/* Thermal support */
-#define CONFIG_IMX6_THERMAL
-
-#define CONFIG_CMD_FUSE
-#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
-#define CONFIG_MXC_OCOTP
-#endif
+#define CONFIG_IMX_THERMAL
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Congatec"
+
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_MXC_I2C3_SPEED 400000
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
+#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
+
/*
* Display CPU and Board information
*/
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
"loadaddr=0x82000000\0" \
"baudrate=115200\0" \
"console=ttyO2,115200n8\0" \
+ "netretry=yes\0" \
"mpurate=auto\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
+#define CONFIG_ARP_TIMEOUT 200UL
+#define CONFIG_NET_RETRY_COUNT 5
#endif /* CONFIG_CMD_NET */
/* additions for new relocation code, must be added to all boards */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Ilko Iliev <www.ronetix.at>
- *
- * (C) Copyright 2009
- * Eric Benard <eric@eukrea.com>
- *
- * Configuration settings for the Eukrea CPU9260 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* to be removed once maemory-map.h is fixed */
-#define AT91_BASE_SYS 0xffffe800
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_AT91SAM9G20
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_AT91SAM9260
-#else
-#error "Unknown board"
-#endif
-
-#include <asm/arch/hardware.h>
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x23f00000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#endif
-
-/* clocks */
-#if defined(CONFIG_CPU9G20)
-#define MASTER_PLL_DIV 0x01
-#define MASTER_PLL_MUL 0x2B
-#elif defined(CONFIG_CPU9260)
-#define MASTER_PLL_DIV 0x09
-#define MASTER_PLL_MUL 0x61
-#endif
-
-/* CKGR_MOR - enable main osc. */
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOSCEN | \
- (255 << 8)) /* Main Oscillator Start-up Time */
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
- AT91_PMC_OUT | \
- ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
-#endif
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_6 | \
- AT91_PMC_PDIV_2)
-#define CONFIG_SYS_MCKR2_VAL \
- CONFIG_SYS_MCKR1_VAL
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_CSS_SLOW | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_CSS_PLLA | \
- AT91_PMC_PRES_1 | \
- AT91SAM9_PMC_MDIV_2 | \
- AT91_PMC_PDIV_1)
-#endif
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
-/* no pull-up for D[31:16] */
-#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
-
-/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
-#define CONFIG_SYS_MATRIX_EBICSA_VAL \
- (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
- AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
-
-/* SDRAM */
-/* SDRAMC_MR Mode register */
-#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
-/* SDRAMC_TR - Refresh Timer register */
-#define CONFIG_SYS_SDRC_TR_VAL1 0x287
-/* SDRAMC_CR - Configuration register*/
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_SDRC_CR_VAL_64MB \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (9 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (3 << 20) | /* Row to Column Delay */ \
- (6 << 24) | /* Active to Precharge Delay */ \
- (10 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_CR_VAL_128MB \
- (AT91_SDRAMC_NC_10 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (9 << 12) | /* Row Cycle Delay */ \
- (3 << 16) | /* Row Precharge Delay */ \
- (3 << 20) | /* Row to Column Delay */ \
- (6 << 24) | /* Active to Precharge Delay */ \
- (10 << 28)) /* Exit Self Refresh to Active Delay */
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_SDRC_CR_VAL_64MB \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_CR_VAL_128MB \
- (AT91_SDRAMC_NC_10 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-#endif
-
-/* Memory Device Register -> SDRAM */
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit */
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
- AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | \
- AT91_SMC_MODE_TDF_CYCLE(3))
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
- AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
- AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | \
- AT91_SMC_MODE_TDF_CYCLE(2))
-#endif
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_CR_PROCRST | \
- AT91_RSTC_MR_ERSTL(1) | \
- AT91_RSTC_MR_ERSTL(2))
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
- AT91_WDT_MR_WDV(0xfff) | \
- AT91_WDT_MR_WDDIS | \
- AT91_WDT_MR_WDD(0xfff))
-
-/*
- * Hardware drivers
- */
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_AT91_GPIO
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MII
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
-#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
-#else
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
-#endif
-
-/* NAND flash */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-
-/* NOR flash */
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SYS_NO_FLASH
-#else
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define PHYS_FLASH_1 0x10000000
-#define PHYS_FLASH_2 0x12000000
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- { PHYS_FLASH_1, PHYS_FLASH_2 }
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-/* LEDS */
-/* Status LED */
-#define CONFIG_STATUS_LED
-#define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_RED 0
-#define STATUS_LED_GREEN 1
-#define STATUS_LED_YELLOW 2
-#define STATUS_LED_BLUE 3
-/* Red */
-#define STATUS_LED_BIT STATUS_LED_RED
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-/* Green */
-#define STATUS_LED_BIT1 STATUS_LED_GREEN
-#define STATUS_LED_STATE1 STATUS_LED_OFF
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-/* Yellow */
-#define STATUS_LED_BIT2 STATUS_LED_YELLOW
-#define STATUS_LED_STATE2 STATUS_LED_OFF
-#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
-/* Blue */
-#define STATUS_LED_BIT3 STATUS_LED_BLUE
-#define STATUS_LED_STATE3 STATUS_LED_ON
-#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
-/* Optional value */
-#define STATUS_LED_BOOT STATUS_LED_BIT
-
-#define CONFIG_RED_LED AT91_PIO_PORTC, 11
-#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
-#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
-#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
-#endif
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-
-#if defined(CONFIG_NANDBOOT)
-#define CONFIG_SYS_USE_NANDFLASH
-#undef CONFIG_SYS_USE_FLASH
-#else
-#define CONFIG_SYS_USE_FLASH
-#undef CONFIG_SYS_USE_NANDFLASH
-#endif
-
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_BASEDIR "cpu9G20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_BASEDIR "cpu9260"
-#endif
-
-#if defined(CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "256k(u-boot)ro," \
- "128k(u-boot-env)ro," \
- "1792k(kernel)," \
- "-(rootfs);" \
- "atmel_nand:-(nand)"
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,0\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
- "run ramargs;bootm 22000000\0" \
- "flashboot=run ramargs;bootm 0x10060000\0" \
- "basedir=" CONFIG_SYS_BASEDIR "\0" \
- "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
- "off 0x10000000 0x1003ffff;erase 0x10000000 " \
- "0x1003ffff;cp.b 0x24000000 0x10000000 " \
- "$(filesize)\0" \
- "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
- " 0x10060000 0x1021ffff;erase 0x10060000 " \
- "0x1021ffff;cp.b 0x24000000 0x10060000 " \
- "$(filesize)\0" \
- "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
- "protect off 0x10220000 0x13ffffff;erase " \
- "0x10220000 0x13ffffff;cp.b 0x24000000 " \
- "0x10220000 $(filesize)\0" \
- ""
-#elif defined(CONFIG_NANDBOOT)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define MTDIDS_DEFAULT "nand0=atmel_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=atmel_nand:" \
- "128k(bootstrap)ro," \
- "256k(u-boot)ro," \
- "128k(u-boot-env)ro," \
- "128k(u-boot-env2)ro," \
- "2M(kernel)," \
- "-(rootfs)"
-
-#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
- "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,5\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
- "run ramargs;bootm 22000000\0" \
- "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
- "0x200000; bootm 0x22000000\0" \
- "basedir=" CONFIG_SYS_BASEDIR "\0" \
- "u-boot=u-boot-eukrea-cpu9260.bin\0" \
- "kernel=uImage-eukrea-cpu9260.bin\0" \
- "rootfs=image-eukrea-cpu9260.ubi\0" \
- "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
- "nand erase 20000 40000; " \
- "nand write ${loadaddr} 20000 40000\0" \
- "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
- "nand erase a0000 200000; " \
- "nand write ${loadaddr} a0000 200000\0" \
- "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
- "nand erase 2a0000 fd60000; " \
- "nand write ${loadaddr} 2a0000 ${filesize}\0"
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SILENT_CONSOLE
-#define CONFIG_NETCONSOLE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif
+++ /dev/null
-/*
- * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
- * eric@eukrea.com
- *
- * Configuration settings for the CPUAT91 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_CPUAT91_H
-#define _CONFIG_CPUAT91_H
-
-#include <linux/sizes.h>
-
-#ifdef CONFIG_RAMBOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x21F00000
-#else
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_SYS_TEXT_BASE 0
-#endif
-
-#define AT91C_XTAL_CLOCK 18432000
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
-#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
-#define CONFIG_AT91RM9200
-#define CONFIG_CPUAT91
-#define USE_920T_MMU
-
-#include <asm/hardware.h> /* needed for port definitions */
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR
-/* flash */
-#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
-#define CONFIG_SYS_MC_PUP_VAL 0x00000000
-#define CONFIG_SYS_MC_PUER_VAL 0x00000000
-#define CONFIG_SYS_MC_ASR_VAL 0x00000000
-#define CONFIG_SYS_MC_AASR_VAL 0x00000000
-#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
-#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
-#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
-
-/* sdram */
-#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
-#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
-#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
-#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
-#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID 0/* ignored in arm */
-
-#undef CONFIG_HARD_I2C
-#define AT91_PIN_SDA (1<<25)
-#define AT91_PIN_SCL (1<<26)
-
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
-#define I2C_SDA(bit) \
- if (bit) \
- writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
- else \
- writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
-#define I2C_SCL(bit) \
- if (bit) \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
- else \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
-
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CACHE
-#undef CONFIG_CMD_USB
-#undef CONFIG_CMD_DHCP
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#endif
-
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
-
-#define CONFIG_DRIVER_AT91EMAC
-#define CONFIG_SYS_RX_ETH_BUFFER 16
-#define CONFIG_RMII
-#define CONFIG_MII
-#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_KS8721_PHY
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_PROTECTION
-#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- { PHYS_FLASH_1 }
-
-#if defined(CONFIG_CMD_USB)
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_AT91C_PQFP_UHPBU
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#endif
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_DEVICE_NULLDEV
-#define CONFIG_SILENT_CONSOLE
-
-#define CONFIG_VERSION_VARIABLE
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "128k(u-boot)ro," \
- "128k(u-boot-env)," \
- "1792k(kernel)," \
- "-(rootfs)"
-
-#define CONFIG_BOOTARGS \
- "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
-
-#define CONFIG_BOOTCOMMAND "run flashboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "mtdid=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
- "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
- "10000000 ${filesize}\0" \
- "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
- "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \
- "10040000 ${filesize}\0" \
- "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
- "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \
- "21000000 10200000 ${filesize}\0" \
- "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
- "flashboot=run ramargs;bootm 10040000\0" \
- "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
- "bootm 21000000\0"
-#endif /* _CONFIG_CPUAT91_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_USE_SPIFLASH
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MACH_DAVINCI_DA830_EVM
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA830 /* TI DA830 SoC */
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0xc1080000
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Start */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- (32 << 20))
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-/*
- * I2C Configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-
-/*
- * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-/*
- * Flash & Environment
- */
-#ifdef CONFIG_USE_NAND
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_OFFSET (512 << 10)
-#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#endif
-
-#ifdef CONFIG_USE_NOR
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ (64 << 10) /* 64KB */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
-#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
-#define PHYS_FLASH_SIZE (32 << 20) /* Flash size 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
-#define CONFIG_SYS_FLASH_SPL_ACCESS
-#endif
-
-#ifdef CONFIG_USE_SPIFLASH
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE (16 << 10)
-#define CONFIG_ENV_OFFSET (256 << 10)
-#define CONFIG_ENV_SECT_SIZE 4096
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#endif
-
-/*
- * USB configuration
- */
-#define CONFIG_USB_DA8XX /* Platform hookup to MUSB controller */
-#define CONFIG_USB_MUSB_HCD
-
-/*
- * U-Boot general configuration
- */
-#undef CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND ""
-#define CONFIG_BOOTDELAY 3
-
-/*
- * U-Boot commands
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
-#endif
-
-#ifdef CONFIG_USE_NAND
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#endif
-
-#ifdef CONFIG_USE_SPIFLASH
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#endif
-
-/* SD/MMC configuration */
-#ifndef CONFIG_USE_NAND
-#define CONFIG_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#endif
-
-/*
- * Enable MMC commands only when
- * MMC support is present
- */
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_DA8XX)
-#define CONFIG_DOS_PARTITION /* include support for FAT/storage */
-#define CONFIG_CMD_FAT /* include support for FAT cmd */
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#endif
-
-#if !defined(CONFIG_USE_NAND) && \
- !defined(CONFIG_USE_NOR) && \
- !defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
-#endif
-
-#ifdef CONFIG_USB_DA8XX
-
-#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */
-#define CONFIG_CMD_USB /* include support for usb cmd */
-
-#define CONFIG_USB_STORAGE /* MSC class support */
-#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
-
-#ifdef CONFIG_USB_KEYBOARD /* HID class support */
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-
-#endif /* CONFIG_USB_MUSB_HCD */
-
-#ifdef CONFIG_USB_MUSB_UDC
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "DA830EVM"
-#endif /* CONFIG_USB_MUSB_UDC */
-
-#endif /* CONFIG_USB_DA8XX */
-
-#ifdef CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nand0=davinci_nand.1"
-#define PART_BOOT "512k(bootloader)ro,"
-#define PART_PARAMS "512k(params)ro,"
-#define PART_KERNEL "4m(kernel),"
-#define PART_REST "-(filesystem)"
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM355 EVM board */
-#define DAVINCI_DM355EVM
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SOC_DM355
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
-
-/* Serial Driver info: UART0 for console */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Ethernet: external DM9000 */
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x04014000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 2
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_MMC_MBLOCK
-
-/* USB: OTG connector */
-/* NYET -- #define CONFIG_USB_DAVINCI */
-
-/* U-Boot command configuration */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#else
-#undef CONFIG_USB_MUSB_HCD
-#undef CONFIG_CMD_USB
-#undef CONFIG_USB_STORAGE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTCOMMAND \
- "dhcp;bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200n8 " \
- "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
-#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-
-
-/* NAND configuration ... socketed with two chipselects. It normally comes
- * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
- * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
- * pretty much demands the 4-bit ECC support.) You can of course swap in
- * other parts, including small page ones.
- *
- * This presents a single read-only partition for all bootloader stuff.
- * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
- * some extra space to help cope with bad blocks in that data. Linux
- * shouldn't care about its detailed layout, and will probably want to use
- * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
- * override this default partitioning using MTDPARTS and cmdlinepart.
- */
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-/* Use same layout for 128K/256K blocks; allow some bad blocks */
-#define PART_BOOT "2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT "512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
-#define PART_REST "-(filesystem)"
-
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DAVINCI_DM355LEOPARD
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SOC_DM355 /* DM355 based board */
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
-
-/* Serial Driver info: UART0 for console */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Ethernet: external DM9000 */
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x04000000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE + 16)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
-
-/* NAND */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_HW_ECC
-
-#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/* U-Boot command configuration */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "dhcp;bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200n8 " \
- "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
-#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-#define PART_BOOT "2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT "512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
-#define PART_REST "-(filesystem)"
-
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM365 EVM board */
-#define DAVINCI_DM365EVM
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
-#define CONFIG_SOC_DM365
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
-
-/* Serial Driver info: UART0 for console */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* EEPROM definitions for EEPROM on DM365 EVM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* Network Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_MAX_CHIPS 2
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_MMC_MBLOCK
-
-#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
-#define PINMUX4_USBDRVBUS_BITSET 0x2000
-
-/* USB Configuration */
-#define CONFIG_USB_DAVINCI
-#define CONFIG_USB_MUSB_HCD
-
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_CMD_USB /* include support for usb */
-#define CONFIG_CMD_STORAGE /* include support for usb */
-#define CONFIG_CMD_FAT /* include support for FAT/storage*/
-#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
-#endif
-
-#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */
-#define CONFIG_CMD_USB /* include support for usb cmd */
-#define CONFIG_USB_STORAGE /* MSC class support */
-#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
-#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
-#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
-
-#ifdef CONFIG_USB_KEYBOARD /* HID class support */
-#define CONFIG_SYS_USB_EVENT_POLL
-
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-#endif /* CONFIG_USB_MUSB_HCD */
-
-#ifdef CONFIG_USB_MUSB_UDC
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_USBD_VENDORID 0x0451
-#define CONFIG_USBD_PRODUCTID 0x5678
-#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME "DM365VM"
-#endif /* CONFIG_USB_MUSB_UDC */
-
-/* U-Boot command configuration */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND \
- "dhcp;bootm"
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200n8 " \
- "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
-#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-
-
-/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
- * It normally comes with a 2GByte SLC part with 2KB pages
- * (and 128KB erase blocks); other
- * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
- * pretty much demands the 4-bit ECC support.) You can of course swap in
- * other parts, including small page ones.
- */
-#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-/* Use same layout for 128K/256K blocks; allow some bad blocks */
-#define PART_BOOT "2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT "512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
-#define PART_REST "-(filesystem)"
-
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM6467 EVM board */
-#define DAVINCI_DM6467EVM
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_NAND_SMALLPAGE
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* SoC Configuration */
-
-/* Clock rates detection */
-#ifndef __ASSEMBLY__
-extern unsigned int davinci_arm_clk_get(void);
-#endif
-
-/* Arm Clock frequency */
-#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
-/* Timer Input clock freq */
-#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SOC_DM646X
-
-/* EEPROM definitions for EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
-#define CONFIG_REVISION_TAG
-
-/* Serial Driver info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-#define CONFIG_SYS_NS16550_COM1 0x01c20000
-#define CONFIG_SYS_NS16550_CLK 24000000
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
-
-/* Network & Ethernet Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* Flash & Environment */
-#define CONFIG_SYS_NO_FLASH
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_MASK_CLE 0x80000
-#define CONFIG_SYS_NAND_MASK_ALE 0x40000
-#define CONFIG_SYS_NAND_CS 2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_ENV_OFFSET 0
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
-#endif
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
-#define CONFIG_BOOTARGS \
- "mem=120M console=ttyS0,115200n8 " \
- "root=/dev/hda1 rw noinitrd ip=dhcp"
-
-/* U-Boot commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-#endif
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Define this to make U-Boot skip low level initialization when loaded
- * by initial bootloader. Not required by NAND U-Boot version but IS
- * required for a NOR version used to burn the real NOR U-Boot into
- * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
- * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
- * NOR U-Boot is loaded directly from Flash so it must perform all the
- * low level initialization itself. NAND version is loaded by an initial
- * bootloader (UBL in TI-ese) that performs such an initialization so it's
- * skipped in NAND version. The third DaVinci boot mode loads a bootloader
- * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
- * performing low level init prior to loading. All that means we can NOT use
- * NAND version to put U-Boot into NOR because it doesn't have NOR support and
- * we can NOT use NOR version because it performs low level initialization
- * effectively destroying itself in DDR memory. That's why a separate NOR
- * version with this define is needed. It is loaded via UART, then one uses
- * it to somehow download a proper NOR version built WITHOUT this define to
- * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
- * NOR support into the initial bootloader so it won't be needed but DaVinci
- * static RAM might be too small for this (I have something like 2Kbytes left
- * as of now, without NOR support) so this might've not happened...
- *
-#define CONFIG_NOR_UART_BOOT
- */
-
-/*=======*/
-/* Board */
-/*=======*/
-#define DV_EVM
-#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NAND
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*====================================================*/
-/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
-/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
-/*====================================================*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
-
-#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#ifdef CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT \
- "nand0=davinci_nand.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
-#else
-#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#elif defined(CONFIG_SYS_USE_NOR)
-#ifdef CONFIG_NOR_UART_BOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#else
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
-#endif
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_DAVINCI
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-#elif defined(CONFIG_SYS_USE_NOR)
-#define CONFIG_CMD_JFFS2
-#else
-#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
-#endif
-/*==========================*/
-/* USB MSC support (if any) */
-/*==========================*/
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_CMD_USB
-#ifdef CONFIG_USB_MUSB_HCD
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*=======*/
-/* Board */
-/*=======*/
-#define SCHMOOGIE
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_USE_NAND
-#define MACH_TYPE_SCHMOOGIE 1255
-#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
-
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-/*=====================*/
-/* Board related stuff */
-/*=====================*/
-#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
-#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
-#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-#undef CONFIG_CMD_EEPROM
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Board */
-#define SFFSDR
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
-/* Serial Driver info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/* Network & Ethernet Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-/* Flash & Environment */
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-/* I2C switch definitions for PCA9543 chip */
-#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
-#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
-#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
-/* U-Boot general configuration */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
- * load address. */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
- * may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/* Linux Information */
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS \
- "mem=56M " \
- "console=ttyS0,115200n8 " \
- "root=/dev/nfs rw noinitrd ip=dhcp " \
- "nfsroot=${serverip}:/nfsroot/sffsdr " \
- "eth0=${ethaddr}"
-#define CONFIG_BOOTCOMMAND \
- "nand read 87A00000 100000 300000;" \
- "bootelf 87A00000"
-/* U-Boot commands */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Define this to make U-Boot skip low level initialization when loaded
- * by initial bootloader. Not required by NAND U-Boot version but IS
- * required for a NOR version used to burn the real NOR U-Boot into
- * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
- * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
- * NOR U-Boot is loaded directly from Flash so it must perform all the
- * low level initialization itself. NAND version is loaded by an initial
- * bootloader (UBL in TI-ese) that performs such an initialization so it's
- * skipped in NAND version. The third DaVinci boot mode loads a bootloader
- * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
- * performing low level init prior to loading. All that means we can NOT use
- * NAND version to put U-Boot into NOR because it doesn't have NOR support and
- * we can NOT use NOR version because it performs low level initialization
- * effectively destroying itself in DDR memory. That's why a separate NOR
- * version with this define is needed. It is loaded via UART, then one uses
- * it to somehow download a proper NOR version built WITHOUT this define to
- * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
- * NOR support into the initial bootloader so it won't be needed but DaVinci
- * static RAM might be too small for this (I have something like 2Kbytes left
- * as of now, without NOR support) so this might've not happened...
- *
-#define CONFIG_NOR_UART_BOOT
- */
-
-/*=======*/
-/* Board */
-/*=======*/
-#define SONATA_BOARD
-#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NOR
-#define MACH_TYPE_SONATA 1254
-#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*====================================================*/
-/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
-/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
-/*====================================================*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
-#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
-#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
-#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS 2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */
-#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
-#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE 0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
-#elif defined(CONFIG_SYS_USE_NOR)
-#ifdef CONFIG_NOR_UART_BOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#else
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
-#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
-#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
-#endif
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR 0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_CMD_NAND
-#elif defined(CONFIG_SYS_USE_NOR)
-#define CONFIG_CMD_JFFS2
-#else
-#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
-#endif
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on omap3_beagle.h:
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the Comelit DIG297 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_OMAP3_CPS
-#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
-#else
-#define MACH_TYPE_OMAP3_CPS 2751
-#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SYS_TEXT_BASE 0x80008000
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration: UART3 (ttyO2)
- */
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION
-
-/* library portions to compile in */
-#define CONFIG_RBTREE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-
-/* commands to include */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_UBI /* UBI Support */
-#define CONFIG_CMD_UBIFS /* UBIFS Support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
- "128k(uboot-env),3m(kernel),252m(ubi)"
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER
-#define CONFIG_TWL4030_LED
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access nand at */
- /* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
-
-#if defined(CONFIG_CMD_NET)
-/*
- * SMSC9220 Ethernet
- */
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE 0x2C000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-/* Environment information */
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,3\0"\
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "nandroot=ubi0:rootfs ro\0" \
- "nandrootfstype=ubifs\0" \
- "nfspath=/srv/nfs\0" \
- "tftpfilename=uImage\0" \
- "gatewayip=0.0.0.0\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}::off\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "ubi.mtd=3 " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}::off\0" \
- "netargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "root=/dev/nfs rw " \
- "nfsroot=${serverip}:${nfspath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}::off\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 100000 300000; " \
- "bootm ${loadaddr}\0" \
- "netboot=echo Booting from network ...; " \
- "run netargs; " \
- "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
- "bootm ${loadaddr}\0" \
- "resetenv=nand erase e0000 20000\0"\
-
-#define CONFIG_BOOTCOMMAND \
- "run nandboot"
-
-#define CONFIG_AUTO_COMPLETE
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
- /* works on */
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
- /* load address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#define CONFIG_SYS_FLASH_BASE boot_flash_base
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_NAND
-#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
#include "tegra210-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra210 (E2220-1170) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170"
/* Board-specific serial config */
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
-#define COUNTER_FREQUENCY 38400000
-
#endif /* _E2220_1170_H */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009
- * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
- * Jens Scharsig <esw@bus-elektronik.de>
- *
- * Configuation settings for the EB+CPUx9K2 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_EB_CPUx9K2_H_
-#define _CONFIG_EB_CPUx9K2_H_
-
-/*--------------------------------------------------------------------------*/
-
-#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
-#define USE_920T_MMU
-
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
-
-#include <asm/hardware.h> /* needed for port definitions */
-
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define MACH_TYPE_EB_CPUX9K2 1977
-#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_SYS_DCACHE_OFF
-
-/*--------------------------------------------------------------------------*/
-#ifndef CONFIG_RAMBOOT
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#else
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_TEXT_BASE 0x21800000
-#endif
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
-
-#define CONFIG_BOOT_RETRY_TIME 30
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-
-/*
- * ARM asynchronous clock
- */
-
-#define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
-#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
-
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
-/* flash */
-#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
-#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
-#define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
-#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/*
- * sdram
- */
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
- CONFIG_SYS_MALLOC_LEN)
-
-#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
-#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
-#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
-#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
-#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
-#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-/*
- * Command line configuration
- */
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_SYS_LONGHELP
-
-/*
- * MTD defines
- */
-
-#define CONFIG_FLASH_CFI_MTD
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
-#define MTDPARTS_DEFAULT "mtdparts=" \
- "physmap-flash.0:" \
- "512k(U-Boot)," \
- "128k(Env)," \
- "128k(Splash)," \
- "4M(Kernel)," \
- "384k(MiniFS)," \
- "-(FS)" \
- ";" \
- "atmel_nand:" \
- "1M(emergency)," \
- "-(data)"
-/*
- * Hardware drivers
- */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_AT91C_PQFP_UHPBUG
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_EFI_PARTITION
-
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-
-/*
- * UART/CONSOLE
- */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID 0/* ignored in arm */
-
-/*
- * network
- */
-
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_RESET_PHY_R 1
-
-#define CONFIG_DRIVER_AT91EMAC 1
-#define CONFIG_DRIVER_AT91EMAC_QUIET 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-#define CONFIG_MII 1
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * I2C-Bus
- */
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0
-
-/* Software I2C driver configuration */
-
-#define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
-#define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
-
-#define CONFIG_SYS_I2C_INIT_BOARD
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
-#define I2C_SDA(bit) \
- if (bit) \
- writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
- else \
- writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
-#define I2C_SCL(bit) \
- if (bit) \
- writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
- else \
- writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
-
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
-
-/* I2C-RTC */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#endif
-
-/* EEPROM */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
-/* FLASH organization */
-
-/* NOR-FLASH */
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define PHYS_FLASH_1 0x10000000
-#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_SYS_FLASH_ERASE_TOUT 6000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 2000
-
-/* NAND */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-
-/* Status LED's */
-
-#define CONFIG_STATUS_LED 1
-#define CONFIG_BOARD_SPECIFIC_LED 1
-
-#define STATUS_LED_BOOT 1
-#define STATUS_LED_ACTIVE 0
-
-#define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
-#define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
-#define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
-
-#define CONFIG_VIDEO 1
-
-/* Options */
-
-#ifdef CONFIG_VIDEO
-
-#define CONFIG_VIDEO_VCXK 1
-
-#define CONFIG_SPLASH_SCREEN 1
-
-#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
-#define CONFIG_SYS_VCXK_BASE 0x30000000
-
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
-#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
-
-#define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
-#define CONFIG_SYS_VCXK_ENABLE_PORT piob
-#define CONFIG_SYS_VCXK_ENABLE_DDR oer
-
-#define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
-#define CONFIG_SYS_VCXK_REQUEST_PORT piob
-#define CONFIG_SYS_VCXK_REQUEST_DDR oer
-
-#define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
-#define CONFIG_SYS_VCXK_INVERT_PORT piob
-#define CONFIG_SYS_VCXK_INVERT_DDR oer
-
-#define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
-#define CONFIG_SYS_VCXK_RESET_PORT piob
-#define CONFIG_SYS_VCXK_RESET_DDR oer
-
-#endif /* CONFIG_VIDEO */
-
-/* Environment */
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000)
-#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTCOMMAND "run nfsboot"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "dhcp $(copy_addr) uImage_cpux9k2;" \
- "run bootargsdefaults;" \
- "set bootargs $(bootargs) boot=nfs " \
- ";echo $(bootargs)" \
- ";bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "displaywidth=256\0" \
- "displayheight=512\0" \
- "displaybsteps=1023\0" \
- "ubootaddr=10000000\0" \
- "splashimage=100A0000\0" \
- "kerneladdr=100C0000\0" \
- "kernelsize=00400000\0" \
- "rootfsaddr=10520000\0" \
- "copy_addr=21200000\0" \
- "rootfssize=00AE0000\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "bootargsdefaults=set bootargs " \
- "console=ttyS0,115200 " \
- "video=vcxk_fb:xres:${displaywidth}," \
- "yres:${displayheight}," \
- "bres:${displaybsteps} " \
- "mem=62M " \
- "panic=10 " \
- "uboot=\\\"${ver}\\\" " \
- "\0" \
- "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
- "dhcp $(copy_addr) uImage_cpux9k2;" \
- "erase $(kerneladdr) +$(kernelsize);" \
- "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
- "protect on $(kerneladdr) +$(kernelsize)" \
- "\0" \
- "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
- "dhcp $(copy_addr) rfs;" \
- "erase $(rootfsaddr) +$(rootfssize);" \
- "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
- "\0" \
- "update_uboot=protect off 10000000 1007FFFF;" \
- "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
- "erase 10000000 1007FFFF;" \
- "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
- "protect on 10000000 1007FFFF;reset\0" \
- "update_splash=protect off $(splashimage) +20000;" \
- "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
- "erase $(splashimage) +20000;" \
- "cp.b $(fileaddr) $(splashimage) $(filesize);" \
- "protect on $(splashimage) +20000;reset\0" \
- "emergency=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(kerneladdr)\0" \
- "netemergency=run bootargsdefaults;" \
- "dhcp $(copy_addr) uImage_cpux9k2;" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(copy_addr)\0" \
- "norboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=local " \
- ";bootm $(kerneladdr)\0" \
- "nandboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=nand " \
- ";bootm $(kerneladdr)\0" \
- " "
-
-/*--------------------------------------------------------------------------*/
-
-#endif
-
-/* EOF */
#error "no board defined"
#endif
+#define CONFIG_SYS_GENERIC_BOARD
+
/* Initial environment and monitor configuration options. */
#define CONFIG_BOOTDELAY 2
#define CONFIG_CMDLINE_TAG 1
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
-#define CONFIG_USE_NAND
-
-/*
- * SoC Configuration
- */
-#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850 /* TI DA850 SoC */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ 24000000
-#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_DA850_LOWLEVEL
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
-#define CONFIG_DA8XX_GPIO
-#define CONFIG_HOSTNAME enbw_cmc
-
-#define MACH_TYPE_ENBW_CMC 3585
-#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-/*
- * I2C Configuration
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
-#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
-#define CONFIG_CMD_I2C
-
-#define CONFIG_CMD_DTT
-#define CONFIG_DTT_LM75
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-/*
- * SPI Configuration
- */
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
-#define CONFIG_CMD_SPI
-
-/*
- * Flash & Environment
- */
-#ifdef CONFIG_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS 3
-#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE 0x10
-#define CONFIG_SYS_NAND_MASK_ALE 0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
-#define MTDPARTS_DEFAULT \
- "mtdparts=" \
- "physmap-flash.0:" \
- "512k(U-Boot)," \
- "64k(env1)," \
- "64k(env2)," \
- "-(rest);" \
- "davinci_nand.1:" \
- "128k(dtb)," \
- "3m(kernel)," \
- "4m(rootfs)," \
- "-(userfs)"
-
-
-#define CONFIG_CMD_MTDPARTS
-
-#endif
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-/*
- * Flash configuration
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_MTD
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE (64 << 10)
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#undef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
- CONFIG_ENV_SECT_SIZE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "u-boot_addr_r=c0000000\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
- "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize};" \
- "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
- "netdev=eth0\0" \
- "rootpath=/opt/eldk-arm/arm\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "kernel_addr_r=c0700000\0" \
- "fdt_addr_r=c0600000\0" \
- "ramdisk_addr_r=c0b00000\0" \
- "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
- __stringify(CONFIG_HOSTNAME) ".dtb\0" \
- "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
- "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
- "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
- "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
- "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
- "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
- "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
- "addcon=setenv bootargs ${bootargs} console=ttyS2," \
- "${baudrate}n8\0" \
- "net_nfs=run load_fdt load_kernel; " \
- "run nfsargs addip addcon addmtd addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
- "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "bootcmd=run net_nfs\0" \
- "machid=e01\0" \
- "key_cmd_0=echo key: 0\0" \
- "key_cmd_1=echo key: 1\0" \
- "key_cmd_2=echo key: 2\0" \
- "key_cmd_3=echo key: 3\0" \
- "key_magic_0=0\0" \
- "key_magic_1=1\0" \
- "key_magic_2=2\0" \
- "key_magic_3=3\0" \
- "magic_keys=0123\0" \
- "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "logversion=2\0" \
- "\0"
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE "uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_HWCONFIG
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * U-Boot commands
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_CACHE
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifndef CONFIG_DRIVER_TI_EMAC
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_PING
-#endif
-
-#ifdef CONFIG_USE_NAND
-#define CONFIG_CMD_NAND
-
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-#define CONFIG_RBTREE
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#endif
-
-#if !defined(CONFIG_USE_NAND) && \
- !defined(CONFIG_USE_NOR) && \
- !defined(CONFIG_USE_SPIFLASH)
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
-#endif
-
-#define CONFIG_SYS_TEXT_BASE 0x60000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE 0xc0000000
-#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
-
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMC_RESET_PIN 0x04000000
-#define CONFIG_CMC_RESET_TIMEOUT 3
-
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
-#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
-#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
-
-#define CONFIG_CMD_DATE
-#define CONFIG_RTC_DAVINCI
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_MMC_MBLOCK
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-
-/* GPIO */
-#define CONFIG_ENBW_CMC_BOARD_TYPE 57
-#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
-#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
-#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
-
-/* FDT support */
-#define CONFIG_OF_LIBFDT
-
-/* LowLevel Init */
-/* PLL */
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
-
-#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
-#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
-
-/* DDR RAM */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
- DV_DDR_PHY_EXT_STRBEN | \
- (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
- (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
- (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
- (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
- (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
- (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
- (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
- (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
- (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
- (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
- (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
-
-/*
- * freq = 150MHz -> t = 7ns
- */
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
- (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
- (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
- (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
- (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
- (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
- (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
- ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
-
-/*
- * freq = 150MHz -> t=7ns
- */
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
- (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
- (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
- (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
- (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
- (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
- (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
- (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
- (2 << DV_DDR_SDTMR2_CKE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
-#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
- DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
- DAVINCI_SYSCFG_SUSPSRC_UART2 | \
- DAVINCI_SYSCFG_SUSPSRC_EMAC |\
- DAVINCI_SYSCFG_SUSPSRC_I2C)
-
-#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
- DAVINCI_ABCR_WSTROBE(6) | \
- DAVINCI_ABCR_WHOLD(1) | \
- DAVINCI_ABCR_RSETUP(2) | \
- DAVINCI_ABCR_RSTROBE(6) | \
- DAVINCI_ABCR_RHOLD(1) | \
- DAVINCI_ABCR_ASIZE_16BIT)
-
-#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
- DAVINCI_ABCR_WSTROBE(2) | \
- DAVINCI_ABCR_WHOLD(1) | \
- DAVINCI_ABCR_RSETUP(1) | \
- DAVINCI_ABCR_RSTROBE(6) | \
- DAVINCI_ABCR_RHOLD(1) | \
- DAVINCI_ABCR_ASIZE_8BIT)
-
-/*
- * NOR Bootconfiguration word:
- * Method: Direc boot
- * EMIFA access mode: 16 Bit
- */
-#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
-
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
-#define CONFIG_POST_EXTERNAL_WORD_FUNCS
-#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
-#define CONFIG_SYS_BOOTCOUNT_BE
-
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#endif /* __CONFIG_H */
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */
#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_ARCH_MISC_INIT
/* ns16550 UART is memory-mapped in Quark SoC */
#define CONFIG_CMD_GPIO
/* Thermal */
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
/* Serial */
#define CONFIG_MXC_UART
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_GSC 0
#ifndef __HIKEY_H
#define __HIKEY_H
+#include <linux/sizes.h>
+
/* We use generic board for hikey */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_POWER
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
+#define CONFIG_BOARD_EARLY_INIT_F
+
/* Physical Memory Map */
/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
#define PHYS_SDRAM_1 0x00000000
/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
-#define PHYS_SDRAM_1_SIZE 0x3f000000
+#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF
+
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define GICC_BASE 0xf6802000
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-
-/* PL011 Serial Configuration */
-#define CONFIG_PL011_SERIAL
-
-#define CONFIG_PL011_CLOCK 19200000
-#define CONFIG_PL01x_PORTS {(void *)0xF8015000}
-#define CONFIG_CONS_INDEX 0
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
+/* Serial port PL010/PL011 through the device model */
+#define CONFIG_PL01X_SERIAL
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_USB
#endif
#define CONFIG_HIKEY_GPIO
-#define CONFIG_DM_GPIO
#define CONFIG_CMD_GPIO
-#define CONFIG_DM
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
+++ /dev/null
-/*
- * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53-EVK Freescale board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SOC type must be included before imx-regs.h */
-#define CONFIG_MX53
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_OF_LIBFDT
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* Enable GPIOs */
-#define CONFIG_MXC_GPIO
-
-/* UART */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
-
-/* MMC */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/* Ethernet on FEC */
-#define CONFIG_MII
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x01
-#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR
-#define CONFIG_RESET_PHY_R
-#define CONFIG_FEC_MXC_NO_ANEG
-#define CONFIG_ETHPRIME "FEC0"
-
-/* SPI */
-#define CONFIG_HARD_SPI
-#define CONFIG_MXC_SPI
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
-
-/* SPI FLASH - not used for environment */
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_GPIO
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
-#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x70000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nor0=f0000000.flash"
-
-/* FLASH and environment organization */
-
-#define CONFIG_SYS_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
-#define CONFIG_FLASH_CFI_MTD /* with MTD support */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define HOSTNAME ima3-mx53
-
-#define CONFIG_HOSTNAME ima3-mx53
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram0 rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=${console},${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "console=ttymxc3\0" \
- "loadaddr=70800000\0" \
- "kernel_addr_r=70800000\0" \
- "ramdisk_addr_r=71000000\0" \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
- "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
- "mmcargs=setenv bootargs root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs addip addtty addmtd addmisc mmcload;" \
- "bootm\0" \
- "mmcload=fatload mmc ${mmcdev}:${mmcpart} " \
- "${loadaddr} ${uimage}\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \
- "tftp ${kernel_addr_r} ${bootfile}\0" \
- "net_self=if run net_self_load;then " \
- "run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
- "else echo Images not loades;fi\0" \
- "satargs=setenv bootargs root=/dev/sda1\0" \
- "satafile=boot/uImage\0" \
- "ssdboot=echo Booting from ssd ...; " \
- "run satargs addip addtty addmtd addmisc;" \
- "sata init;ext2load sata 0:1 ${kernel_addr_r} " \
- "${satafile};bootm\0" \
- "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \
- "uimage=uImage\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=0xf0001000\0" \
- "update=protect off 0xf0000000 +60000;" \
- "erase ${uboot_addr} +60000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-
-#define CONFIG_CMD_SATA
-#ifdef CONFIG_CMD_SATA
- #define CONFIG_DWC_AHSATA
- #define CONFIG_SYS_SATA_MAX_DEVICE 1
- #define CONFIG_DWC_AHSATA_PORT_ID 0
- #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
- #define CONFIG_LBA48
- #define CONFIG_LIBATA
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* include common defines/options for all imx27lite related boards */
-#include "imx27lite-common.h"
-/*
- * SoC Configuration
- */
-#define CONFIG_IMX27LITE
-#define CONFIG_HOSTNAME imx27
-#define CONFIG_BOARDNAME "LogicPD imx27lite\n"
-
-/*
- * Flash & Environment
- */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
-#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
-#define PHYS_FLASH_SIZE 0x200000
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
-
-/*
- * SD/MMC
- */
-#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
-
-/*
- * MTD partitions
- */
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=" \
- "physmap-flash.0:" \
- "256k(U-Boot)," \
- "1664k(user)," \
- "64k(env1)," \
- "64k(env2);" \
- "mxc_nand.0:" \
- "128k(IPL-SPL)," \
- "4m(kernel)," \
- "22m(rootfs)," \
- "-(userfs)"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the LogicPD i.MX31 Litekit board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX31 1 /* This is a mx31 */
-#define CONFIG_MX31_CLK32 32000
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
-
-/* Temporarily disabled */
-#if 0
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_FIT 1
-#define CONFIG_FIT_VERBOSE 1
-#endif
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MXC_SPI 1
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 1
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.23.168
-#define CONFIG_SERVERIP 192.168.23.2
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
- "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
- "bootcmd=run bootcmd_net\0" \
- "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
- "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
-
-
-#define CONFIG_SMC911X 1
-#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
-#define CONFIG_SMC911X_32_BIT 1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
-
-#define CONFIG_CMDLINE_EDITING 1
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE (64 * 1024)
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/*
- * JFFS2 partitions
- */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-
-/*
- * NAND flash
- */
-#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-#define CONFIG_MXC_NAND_HWECC
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
+++ /dev/null
-/*
- * Copyright 2010 (C)
- * Kristoffer Ericson <kristoffer.ericson@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SA1110 1 /* This is an SA110 CPU */
-#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_SYS_TEXT_BASE 0xC1F00000
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* Console setting */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SA1100_SERIAL 1
-#define CONFIG_SERIAL3 1 /* we use serial 3 */
-#define CONFIG_BAUDRATE 19200
-#define CONFIG_LOADS_ECHO 1
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
-#define CONFIG_BOOTCOMMAND "run boot_kernel"
-#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
-#define CONFIG_SYS_LOAD_ADDR 0xc0000000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* console buffsize */
-#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */
-#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
-#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_ERASE_TOUT (4096)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (4096)
-#define CONFIG_SYS_FLASH_INCREMENT 0x02000000
-#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */
-#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 260
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_FLASH_SHOW_PROGRESS 1
-
-/* Environment */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x00040000
-#define CONFIG_ENV_OFFSET 0x00040000
-#define CONFIG_ENV_SIZE 0x00040000
-#define CONFIG_ENV_SECT_SIZE 0x00040000
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- Monitor - 0x00000000 - 0x00040000 (256kb)
- Environment - 0x00040000 - 0x00080000 (256kb)
- Kernel - 0x00080000 - 0x00380000 (3mb)
- Rootfs - 0x00380000 - 0x........ (rest)
-*/
-
-#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
-#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
-#define CONFIG_SYS_INIT_SP_ADDR 0x0
-#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=jornada7xx-0"
-#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\
- "3m(kernel),-(user);"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "flash_kernel=protect off all; " \
- "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \
- "flash_uboot=protect off all; " \
- "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \
- "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0"
-#endif /* __CONFIG_H */
#ifndef _CONFIG_LACIE_KW_H
#define _CONFIG_LACIE_KW_H
+/*
+ * Generic board support
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+
/*
* Machine number definition
*/
#undef CONFIG_SYS_IDE_MAXDEVICE
#undef CONFIG_SYS_PROMPT
#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
#if defined(CONFIG_D2NET_V2)
#define CONFIG_SYS_PROMPT "d2v2> "
#elif defined(CONFIG_NET2BIG_V2)
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 2
+#else
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
#endif
#endif /* CONFIG_MVSATA_IDE */
+++ /dev/null
-/*
- * ICP DAS LP-8x4x configuration file
- *
- * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
-#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
-#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "bootm 80000 - 240000;"
-
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
- "init=/sbin/init rootfstype=ext4 rootwait"
-
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_LZMA /* LZMA compression support */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB
-#undef CONFIG_LCD
-#undef CONFIG_CMD_IDE
-
-/*
- * Networking Configuration
- * chip on the ICPDAS LINPAC board
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x0C000000
-#define DM9000_IO 0x0C000000
-#define DM9000_DATA 0x0C004000
-#define DM9000_IO_2 0x0D000000
-#define DM9000_DATA_2 0x0D004000
-#define CONFIG_NET_RETRY_COUNT 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa0008000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-/* Use first 64kb bank of the internal SRAM */
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
-
-/*
- * NOR FLASH
- */
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x40000
-#define CONFIG_ENV_SECT_SIZE 0x40000
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x0808c014
-#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
-#define CONFIG_SYS_GPSR2_VAL 0x0221c000
-#define CONFIG_SYS_GPSR3_VAL 0x00020000
-
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
-#define CONFIG_SYS_GPCR2_VAL 0x00100000
-#define CONFIG_SYS_GPCR3_VAL 0x0
-
-#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
-#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
-#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
-#define CONFIG_SYS_GPDR3_VAL 0x00021b81
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
-#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402
-#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
-#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
-
-#define CONFIG_SYS_PSSR_VAL 0x32
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x005002c0
-#define CONFIG_SYS_CCCR 0x02000290
-#define CONFIG_SYS_CLKCFG 0x0000000b
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
-#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
-#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
-#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
-#define CONFIG_SYS_MDREFR_VAL 0x2093e018
-#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
-#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
-#define CONFIG_SYS_MCATT0_VAL 0x0000c497
-#define CONFIG_SYS_MCATT1_VAL 0x0000c497
-#define CONFIG_SYS_MCIO0_VAL 0x00008407
-#define CONFIG_SYS_MCIO1_VAL 0x00008407
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_VOIPAC_LCD
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
-#define CONFIG_USB_STORAGE
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/*
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* EEPROM */
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SPI_FLASH_STMICRO
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_ATMEL
+#endif
+
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_CMD_SF
#define CONFIG_DM_SPI_FLASH
#endif
-#endif
/*
* Video
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
--- /dev/null
+/*
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * lwmon5.h - configuration for lwmon5 board
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Liebherr extra version info
+ */
+#define CONFIG_IDENT_STRING " - v2.0"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_LWMON5 1 /* Board is lwmon5 */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#define CONFIG_440 1 /* ... PPC440 family */
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#define CONFIG_HOSTNAME lwmon5
+
+#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
+
+#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
+#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
+#define CONFIG_MISC_INIT_R /* Call misc_init_r */
+#define CONFIG_BOARD_RESET /* Call board_reset */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
+
+#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
+#define CONFIG_SYS_LIME_BASE_0 0xc0000000
+#define CONFIG_SYS_LIME_BASE_1 0xc1000000
+#define CONFIG_SYS_LIME_BASE_2 0xc2000000
+#define CONFIG_SYS_LIME_BASE_3 0xc3000000
+#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
+#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
+#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
+#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
+
+#define CONFIG_SYS_USB2D0_BASE 0xe0000100
+#define CONFIG_SYS_USB_DEVICE 0xe0000000
+#define CONFIG_SYS_USB_HOST 0xe0000400
+
+/*
+ * Initial RAM & stack pointer
+ *
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
+ * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
+ */
+#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* unused GPT0 COMP reg */
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#define CONFIG_SYS_OCM_SIZE (16 << 10)
+/* 440EPx errata CHIP 11: don't use last 4kbytes */
+#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
+
+/* Additional registers for watchdog timer post test */
+#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
+#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
+#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
+#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
+#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
+#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
+#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
+#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 2 /* Use UART1 */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH0 0xFC000000
+#define CONFIG_SYS_FLASH1 0xF8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
+
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+/*
+ * DDR SDRAM
+ */
+#define CONFIG_SYS_MBYTES_SDRAM 256
+#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
+#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#define CONFIG_DDR_ECC /* enable ECC */
+
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
+ CONFIG_SYS_POST_CPU | \
+ CONFIG_SYS_POST_ECC | \
+ CONFIG_SYS_POST_ETHER | \
+ CONFIG_SYS_POST_FPU | \
+ CONFIG_SYS_POST_I2C | \
+ CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_OCM | \
+ CONFIG_SYS_POST_RTC | \
+ CONFIG_SYS_POST_SPR | \
+ CONFIG_SYS_POST_UART | \
+ CONFIG_SYS_POST_SYSMON | \
+ CONFIG_SYS_POST_WATCHDOG | \
+ CONFIG_SYS_POST_DSP | \
+ CONFIG_SYS_POST_BSPEC1 | \
+ CONFIG_SYS_POST_BSPEC2 | \
+ CONFIG_SYS_POST_BSPEC3 | \
+ CONFIG_SYS_POST_BSPEC4 | \
+ CONFIG_SYS_POST_BSPEC5)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
+ CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_POST_UART { \
+ "UART test", \
+ "uart", \
+ "This test verifies the UART operation.", \
+ POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
+ &uart_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_UART \
+ }
+
+#define CONFIG_POST_WATCHDOG { \
+ "Watchdog timer test", \
+ "watchdog", \
+ "This test checks the watchdog timer.", \
+ POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
+ &lwmon5_watchdog_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_WATCHDOG \
+ }
+
+#define CONFIG_POST_BSPEC1 { \
+ "dsPIC init test", \
+ "dspic_init", \
+ "This test returns result of dsPIC READY test run earlier.", \
+ POST_RAM | POST_ALWAYS, \
+ &dspic_init_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_BSPEC1 \
+ }
+
+#define CONFIG_POST_BSPEC2 { \
+ "dsPIC test", \
+ "dspic", \
+ "This test gets result of dsPIC POST and dsPIC version.", \
+ POST_RAM | POST_ALWAYS, \
+ &dspic_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_BSPEC2 \
+ }
+
+#define CONFIG_POST_BSPEC3 { \
+ "FPGA test", \
+ "fpga", \
+ "This test checks FPGA registers and memory.", \
+ POST_RAM | POST_ALWAYS | POST_MANUAL, \
+ &fpga_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_BSPEC3 \
+ }
+
+#define CONFIG_POST_BSPEC4 { \
+ "GDC test", \
+ "gdc", \
+ "This test checks GDC registers and memory.", \
+ POST_RAM | POST_ALWAYS | POST_MANUAL,\
+ &gdc_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_BSPEC4 \
+ }
+
+#define CONFIG_POST_BSPEC5 { \
+ "SYSMON1 test", \
+ "sysmon1", \
+ "This test checks GPIO_62_EPX pin indicating power failure.", \
+ POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
+ &sysmon1_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_BSPEC5 \
+ }
+
+#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
+#define CONFIG_LOGBUFFER
+/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
+#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
+#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
+#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
+#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
+#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
+ /* 64 byte page write mode using*/
+ /* last 6 bits of the address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
+#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
+
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
+ CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_2_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
+ CONFIG_SYS_I2C_DSPIC_IO_ADDR }
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+
+#define CONFIG_FIT /* enable FIT image support */
+
+#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
+
+#define CONFIG_PREBOOT "setenv bootdelay 15"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=lwmon5\0" \
+ "netdev=eth0\0" \
+ "unlock=yes\0" \
+ "logversion=2\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+ "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xxFP\0" \
+ "bootfile=/tftpboot/lwmon5/uImage\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
+ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
+ "cp.b 200000 FFF80000 80000\0" \
+ "upd=run load update\0" \
+ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
+ "autoscr 200000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 300
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* Video console */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI /* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
+#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
+#define CONFIG_USB_STORAGE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
+
+#ifndef DEBUG
+#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
+#endif
+#define CONFIG_WD_PERIOD 40000 /* in usec */
+#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP 0x03000280
+#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
+
+/* Memory Bank 1 (Lime) initialization */
+#define CONFIG_SYS_EBC_PB1AP 0x01004380
+#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_EBC_PB2AP 0x01004400
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
+
+/* Memory Bank 3 (FPGA2) initialization */
+#define CONFIG_SYS_EBC_PB3AP 0x01004400
+#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
+
+#define CONFIG_SYS_EBC_CFG 0xb8400000
+
+/*
+ * Graphics (Fujitsu Lime)
+ */
+/* SDRAM Clock frequency adjustment register */
+#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
+#if 1 /* 133MHz is not tested enough, use 100MHz for now */
+/* Lime Clock frequency is to set 100MHz */
+#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
+#else
+/* Lime Clock frequency for 133MHz */
+#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
+#endif
+
+/* SDRAM Parameter register */
+#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
+/*
+ * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ * and pixel flare on display when 133MHz was configured. According to
+ * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
+ * Grade
+ */
+#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
+#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
+#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
+#else
+#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
+#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
+#endif
+
+/*
+ * GPIO Setup
+ */
+#define CONFIG_SYS_GPIO_PHY1_RST 12
+#define CONFIG_SYS_GPIO_FLASH_WP 14
+#define CONFIG_SYS_GPIO_PHY0_RST 22
+#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
+#define CONFIG_SYS_GPIO_DSPIC_READY 51
+#define CONFIG_SYS_GPIO_CAN_ENABLE 53
+#define CONFIG_SYS_GPIO_LSB_ENABLE 54
+#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
+#define CONFIG_SYS_GPIO_HIGHSIDE 56
+#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
+#define CONFIG_SYS_GPIO_BOARD_RESET 58
+#define CONFIG_SYS_GPIO_LIME_S 59
+#define CONFIG_SYS_GPIO_LIME_RST 60
+#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
+#define CONFIG_SYS_GPIO_WATCHDOG 63
+
+#define GPIO49_VAL 1
+
+/*
+ * PPC440 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
+}, \
+{ \
+/* GPIO Core 1 */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
+} \
+}
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+#endif /* __CONFIG_H */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
#endif
+++ /dev/null
-/*
- * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
- *
- * based on:
- * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* include common defines/options for all imx27lite related boards */
-#include "imx27lite-common.h"
-
-/*
- * SoC Configuration
- */
-#define CONFIG_MAGNESIUM
-#define CONFIG_HOSTNAME magnesium
-#define CONFIG_BOARDNAME "Projectiondesign magnesium\n"
-
-/*
- * Flash & Environment
- */
-#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */
-#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000)
-#define PHYS_FLASH_SIZE 0x800000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */
-
-/*
- * NAND
- */
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/*
- * SD/MMC
- */
-#define CONFIG_MXC_MCI_REGS_BASE 0x10013000
-
-/*
- * MTD partitions
- */
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
-#define MTDPARTS_DEFAULT \
- "mtdparts=" \
- "physmap-flash.0:" \
- "256k(U-Boot)," \
- "7680k(user)," \
- "128k(env1)," \
- "128k(env2);" \
- "mxc_nand.0:" \
- "128k(IPL-SPL)," \
- "4m(kernel)," \
- "22m(rootfs)," \
- "-(userfs)"
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_MV88F6281GTW_GE_H
-#define _CONFIG_MV88F6281GTW_GE_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_USB
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Unwanted stuffs from mv-common.h */
-#undef CONFIG_CMD_EXT2
-#undef CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_UBI
-#undef CONFIG_CMD_UBIFS
-#undef CONFIG_RBTREE
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_ENV_IS_IN_SPI_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#endif
-#define CONFIG_ENV_SIZE 0x1000 /* 4k */
-#define CONFIG_ENV_ADDR 0x30000
-#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \
- "512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
- "x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */
-#endif /* CONFIG_CMD_NET */
-
-#endif /* _CONFIG_MV88F6281GTW_GE_H */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
/* RTC */
#define CONFIG_RTC_IMXDI
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX51EVK Board
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-/* An i.MX51 CPU */
-#define CONFIG_MX51
-
-#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX)
-#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB)
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0x97800000
-
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_DATE
-
-/*
- * Environmental settings
- */
-
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
-#define CONFIG_ENV_SIZE (4 * 1024)
-
-/*
- * ATAG setup
- */
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Hardware drivers
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_MXC_GPIO
-
-/*
- * SPI Interface
- */
-#ifdef CONFIG_CMD_SPI
-
-#define CONFIG_HARD_SPI
-#define CONFIG_MXC_SPI
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-
-/* SPI FLASH */
-#ifdef CONFIG_CMD_SF
-
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SF_DEFAULT_CS 1
-#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_SPI_MODE (SPI_MODE_0)
-#define CONFIG_FSL_ENV_IN_SF
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SYS_NO_FLASH
-
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-/* SPI PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 0
-#define CONFIG_FSL_PMIC_CS (0 | 120 << 8)
-#define CONFIG_FSL_PMIC_CLK 25000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-#endif
-
-/*
- * MMC Configs
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
-#endif
-
-/*
- * ATA/IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define CONFIG_LBA48
-#undef CONFIG_IDE_LED
-#undef CONFIG_IDE_RESET
-
-#define CONFIG_MX51_PATA
-
-#define __io
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0
-#define CONFIG_SYS_ATA_REG_OFFSET 0xa0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8
-
-#define CONFIG_SYS_ATA_STRIDE 4
-
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MXC_ATA_PIO_MODE 4
-#endif
-
-/*
- * USB
- */
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_MX5
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT
-#define CONFIG_MXC_USB_PORT 1
-#if (CONFIG_MXC_USB_PORT == 0)
-#define CONFIG_MXC_USB_PORTSC (1 << 28)
-#define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY
-#else
-#define CONFIG_MXC_USB_PORTSC (2 << 30)
-#define CONFIG_MXC_USB_FLAGS 0
-#endif
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
-#define CONFIG_PREBOOT
-/* USB NET */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#endif
-#endif /* CONFIG_CMD_USB */
-
-/*
- * Filesystems
- */
-#ifdef CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_LOADADDR 0x90800000
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x90010000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145
-#define CONFIG_SYS_MAIN_PWR_ON
-
-#endif
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* MMC Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* PMIC Configs */
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* PMIC Controller */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* MMC Configs */
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#include "mx6_common.h"
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
+ "dfuspi=dfu 0 sf 0:0:10000000:0\0" \
+ "dfu_alt_info_spl=spl raw 0x400\0" \
+ "dfu_alt_info_img=u-boot raw 0x10000\0" \
+ "dfu_alt_info=spl raw 0x400\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "FSL"
+
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
+
+/* USB Device Firmware Update support */
+#define CONFIG_CMD_DFU
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define CONFIG_DFU_SF
#endif
#endif /* __MX6QSABRE_COMMON_CONFIG_H */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
#include "imx6_spl.h"
#endif
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
#endif
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
#endif /* __CONFIG_H */
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
#include "imx6_spl.h"
#endif
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
#endif
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
#define CONFIG_CMD_TIME
#include "mx6_common.h"
#include <asm/imx-common/gpio.h>
+#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
+
/* SPL options */
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
#include "imx6_spl.h"
-#define CONFIG_ROM_UNIFIED_SECTIONS
-#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#endif
-#undef CONFIG_BOOTM_NETBSD
-#undef CONFIG_BOOTM_PLAN9
-#undef CONFIG_BOOTM_RTEMS
-
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-
/* I2C configs */
#define CONFIG_CMD_I2C
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
-#define PHYS_SDRAM_SIZE SZ_512M
-#undef CONFIG_CMD_IMLS
+/* PMIC only for 9X9 EVK */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
+#endif
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
"console=ttymxc0\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "fdt_file=imx6ul-14x14-evk.dtb\0" \
+ "fdt_file=undefined\0" \
"fdt_addr=0x83000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"fi; " \
"else " \
"bootz; " \
- "fi;\0"
+ "fi;\0" \
+ "findfdt="\
+ "if test $fdt_file = undefined; then " \
+ "if test $board_name = EVK && test $board_rev = 9X9; then " \
+ "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \
+ "if test $board_name = EVK && test $board_rev = 14X14; then " \
+ "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \
+ "if test $fdt_file = undefined; then " \
+ "echo WARNING: Could not determine dtb to use; fi; " \
+ "fi;\0" \
#define CONFIG_BOOTCOMMAND \
+ "run findfdt;" \
"mmc dev ${mmcdev};" \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"else run netboot; fi"
/* Miscellaneous configurable options */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
-#define CONFIG_FEC_DMA_MINALIGN 64
#endif
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX7_COMMON_H
+#define __MX7_COMMON_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#ifndef CONFIG_MX7
+#define CONFIG_MX7
+#endif
+
+/* Timer settings */
+#define CONFIG_MXC_GPT_HCLK
+#define CONFIG_SYSCOUNTER_TIMER
+#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+
+/* Enable iomux-lpsr support */
+#define CONFIG_IOMUX_LPSR
+#define CONFIG_IMX_FIXED_IVT_OFFSET
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_ROM_UNIFIED_SECTIONS
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_LOADADDR 0x80800000
+#define CONFIG_SYS_TEXT_BASE 0x87800000
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 3
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Filesystems and image support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+
+/* Miscellaneous configurable options */
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+#define CONFIG_CMD_GPIO
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+/* Fuses */
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D SABRESD board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX7D_SABRESD_CONFIG_H
+#define __MX7D_SABRESD_CONFIG_H
+
+#include "mx7_common.h"
+
+#define CONFIG_DBG_MONITOR
+#define PHYS_SDRAM_SIZE SZ_1G
+
+/* Network */
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_BROADCOM
+/* ENET1 */
+#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+ "rdinit=/linuxrc " \
+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+ "g_mass_storage.iSerialNumber=\"\" "\
+ "clk_ignore_unused "\
+ "\0" \
+ "initrd_addr=0x83800000\0" \
+ "initrd_high=0xffffffff\0" \
+ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx7d-sdb.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX7
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#define CONFIG_IMX_THERMAL
+
+#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * STMicroelectronics.
- * Configuration settings for the "Nomadik Hardware Kit" NHK-8815,
- * the evaluation board for the Nomadik 8815 System on Chip.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <nomadik.h>
-
-#define CONFIG_NOMADIK_8815 /* cpu variant */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
-
-/* commands */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_SYS_NO_FLASH
-/* There is NAND storage */
-#define CONFIG_NAND_NOMADIK
-#define CONFIG_CMD_JFFS2
-
-/* user interface */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* boot config */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"
-#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \
- " fsload 0x800000 initrd.gz.uimg;" \
- " bootm 0x100000 0x800000"
-
-/* memory-related information */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/
-#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20))
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
-
-#define CONFIG_BOARD_LATE_INIT /* call board_late_init during start up */
-
-/* timing informazion */
-#define CONFIG_SYS_TIMERBASE 0x101E2000
-
-/* serial port (PL011) configuration */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CFG_SERIAL0 0x101FD000
-#define CFG_SERIAL1 0x101FB000
-
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
-#define CONFIG_PL011_CLOCK 48000000
-
-/* i2c, for the port extenders (uses gpio.c in board directory) */
-#ifndef __ASSEMBLY__
-#include <asm/arch/gpio.h>
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT 1 /* I2C bit-banged */
-#define I2C_SOFT_DEFS
-#define CONFIG_SYS_I2C_SOFT_SPEED 400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define __SDA 63
-#define __SCL 62
-#define I2C_SDA(x) nmk_gpio_set(__SDA, x)
-#define I2C_SCL(x) nmk_gpio_set(__SCL, x)
-#define I2C_READ (nmk_gpio_get(__SDA)!=0)
-#define I2C_ACTIVE nmk_gpio_dir(__SDA, 1)
-#define I2C_TRISTATE nmk_gpio_dir(__SDA, 0)
-#define I2C_DELAY (udelay(2))
-#endif /* __ASSEMBLY__ */
-
-/* Ethernet */
-#define PCI_MEMORY_VADDR 0xe8000000
-#define PCI_IO_VADDR 0xee000000
-#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
-#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
-
-#define CONFIG_SMC91111 /* Using SMC91c111*/
-#define CONFIG_SMC91111_BASE 0x34000300
-#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_IP_DEFRAG /* Allows faster download, TFTP and NFS */
-#define CONFIG_TFTP_BLOCKSIZE 4096
-#define CONFIG_NFS_READ_SIZE 4096
-
-/* Storage information: onenand and nand */
-#define CONFIG_CMD_ONENAND
-#define CONFIG_MTD_ONENAND_VERIFY_WRITE
-#define CONFIG_SYS_ONENAND_BASE 0x30000000
-
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */
-
-/*
- * Filesystem information
- *
- * Since U-Boot has been loaded to RAM by vendor code, we could use
- * either or both OneNand and Nand. However, we need to know where the
- * filesystem lives. Comments below report vendor-selected partitions
- */
-#ifdef CONFIG_BOOT_ONENAND
- /* Partition Size Start
- * XloaderTOC + X-Loader 256KB 0x00000000
- * Memory init function 256KB 0x00040000
- * U-Boot + env 2MB 0x00080000
- * Sysimage (kernel + ramdisk) 4MB 0x00280000
- * JFFS2 Root filesystem 22MB 0x00680000
- * JFFS2 User Data 227.5MB 0x01C80000
- */
-# define CONFIG_JFFS2_DEV "onenand0"
-# define CONFIG_JFFS2_PART_SIZE 0x01600000
-# define CONFIG_JFFS2_PART_OFFSET 0x00680000
-# define CONFIG_ENV_IS_IN_ONENAND
-# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
-# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE)
-
-#else /* BOOT_NAND */
- /* Partition Size Start
- * XloaderTOC + X-Loader 256KB 0x00000000
- * Memory init function 256KB 0x00040000
- * U-Boot + env 2MB 0x00080000
- * Kernel Image 3MB 0x00280000
- * JFFS2 Root filesystem 22MB 0x00580000
- * JFFS2 User Data 100.5MB 0x01b80000
- */
-# define CONFIG_JFFS2_DEV "nand0"
-# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/
-# define CONFIG_JFFS2_PART_SIZE 0x01600000
-# define CONFIG_JFFS2_PART_OFFSET 0x00580000
-# define CONFIG_ENV_IS_IN_NAND
-# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
-# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE)
-
-#endif /* CONFIG_BOOT_ONENAND */
-
-/* this is needed to make hello_world.c and other stuff happy */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#endif /* __CONFIG_H */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_EDID
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MXC
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST 1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST 1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#include <configs/ti_omap3_common.h>
#include <asm/mach-types.h>
+#undef CONFIG_BOOTDELAY
+
/*
* Display CPU and Board information
*/
/*#undef CONFIG_ENV_IS_NOWHERE*/
+#ifndef CONFIG_SPL_BUILD
+
+#include <config_distro_defaults.h>
+
+/* Environment */
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define MEM_LAYOUT_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ "scriptaddr=0x87E00000\0" \
+ "pxefile_addr_r=0x87F00000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "usbtty=cdc_acm\0" \
- "loadaddr=0x82000000\0" \
- "dtbaddr=0x81600000\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "usbtty=cdc_acm\0" \
- "console=ttyO2,115200n8\0" \
- "mpurate=auto\0" \
- "vram=12M\0" \
- "dvimode=1024x768MR-16@60\0" \
- "defaultdisplay=dvi\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nandroot=/dev/mtdblock4 rw\0" \
- "nandrootfstype=jffs2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapfb.debug=y " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapfb.debug=y " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr}\0" \
- "mmcbootfdt=echo Booting with DT from mmc ...; " \
- "bootz ${loadaddr} - ${dtbaddr}\0" \
- "nandboot=echo Booting from onenand ...; " \
- "run nandargs; " \
- "onenand read ${loadaddr} 280000 400000; " \
- "bootz ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadzimage; then " \
- "if test -n $dtbfile; then " \
- "if run loadfdt; then " \
- "run mmcbootfdt;" \
- "fi;" \
- "fi;" \
- "run mmcboot;" \
- "fi;" \
- "fi;" \
- "run nandboot;" \
+ ENV_DEVICE_SETTINGS \
+ MEM_LAYOUT_SETTINGS \
+ BOOTENV
+
+#endif
/*
* FLASH and environment organization
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
+++ /dev/null
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from omap3_beagle.h:
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the TI OMAP3530 Beagle board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
-#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT 1
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-#define CONFIG_SERIAL_TAG 1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
- /* Sector */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 */
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
-
-/* silent console by default */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_SILENT_CONSOLE 1
-
-/* USB */
-#define CONFIG_USB_MUSB_UDC 1
-#define CONFIG_USB_OMAP3 1
-#define CONFIG_TWL4030_USB 1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE 1
-#define CONFIG_USB_TTY 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
-#define CONFIG_USBD_VENDORID 0x164c
-#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
-#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
-#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
-#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
-
-/* no FLASH available */
-#define CONFIG_SYS_NO_FLASH
-
-/* commands to include */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_FPGA_LOADMK
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER 1
-
-/* Environment information */
-#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
-#define CONFIG_BOOTDELAY 0
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "silent=true\0" \
- "loadaddr=0x82000000\0" \
- "usbtty=cdc_acm\0" \
- "console=ttyO0,115200n8\0" \
- "mpurate=600\0" \
- "vram=12M\0" \
- "dvimode=1024x768-24@60\0" \
- "defaultdisplay=dvi\0" \
- "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
- "/lib/firmware/mvblx/${fpgafilename}; then " \
- "fpga load 0 ${loadaddr} ${filesize}; " \
- "fi;\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "mpurate=${mpurate} " \
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapfb.debug=y " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype} " \
- "mvfw.fpgavers=${fpgavers} " \
- "${cmdline_suffix}\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "mmcbootcmd= " \
- "echo Trying mmc${mmcdev}; " \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loading boot environment from mmc${mmcdev}; " \
- "run importbootenv; " \
- "fi;" \
- "run loadfpga; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi;" \
- "fi\0"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv mmcdev 1;" \
- "run mmcbootcmd || " \
- "setenv mmcdev 0;" \
- "run mmcbootcmd"
-
-
-#define CONFIG_AUTO_COMPLETE 1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
-#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
-#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-#define CONFIG_ENV_IS_NOWHERE 1
-
-/*----------------------------------------------------------------------------
- * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_SMC911X 1
- #define CONFIG_SMC911X_32_BIT
- #define CONFIG_SMC911X_BASE 0x2C000000
-#endif /* (CONFIG_CMD_NET) */
-
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_EEPROM_BUS_NUM 2
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_OMAP3_SPI
-
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#endif /* __CONFIG_H */
#endif /* CONFIG_NAND */
/* Board NAND Info. */
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
/* Environment information */
+++ /dev/null
-/*
- * (C) Copyright 2006-2009
- * Texas Instruments Incorporated.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- * Nishanth Menon <nm@ti.com>
- *
- * Configuration settings for the 3430 TI SDP3430 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* TODO: REMOVE THE FOLLOWING
- * Retained the following till size.h is removed in u-boot
- */
-#include <linux/sizes.h>
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC /* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * NOTE: these #defines presume standard SDP jumper settings.
- * In particular:
- * - 26 MHz clock (not 19.2 or 38.4 MHz)
- * - Boot from 128MB NOR, not NAND or OneNAND
- *
- * At this writing, OMAP3 U-Boot support doesn't permit concurrent
- * support for all the flash types the board supports.
- */
-#define CONFIG_DISPLAY_CPUINFO 1
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-/* Clock Defines */
-#define V_OSCK 26000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_REVISION_TAG 1
-
-#define CONFIG_OF_LIBFDT 1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * Hardware drivers
- */
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER 1
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
- * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
- * support UART boot (that's only for UART3); it prevents sharing a Linux
- * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
- *
- * UART boot uses UART3 on J9, and the SDP user's guide says to use
- * that for console. Downsides of using J9: you can't use IRDA too;
- * since UART3 isn't in the CORE power domain, it may be a bit less
- * usable in certain PM-sensitive debug scenarios.
- */
-#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
-
-#ifdef CONSOLE_J9
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3 /* UART3 */
-#else
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SERIAL1 1 /* UART1 */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/*
- * I2C for power management setup
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/* OMITTED: single 1 Gbit MT29F1G NAND flash */
-
-/*
- * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
- */
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
-
-#define CONFIG_SYS_FLASH_CFI_WIDTH 2
-#define PHYS_FLASH_SIZE (128 << 20)
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
-
-/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
-#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
-/*--------------------------------------------------------------------------*/
-
-/* Enabled commands */
-#define CONFIG_CMD_DHCP /* DHCP Support */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-#define CONFIG_CMD_MMC /* MMC support */
-
-/*--------------------------------------------------------------------------*/
-/*
- * MMC boot support
- */
-
-#if defined(CONFIG_CMD_MMC)
-#define CONFIG_GENERIC_MMC 1
-#define CONFIG_MMC 1
-#define CONFIG_OMAP_HSMMC 1
-#define CONFIG_DOS_PARTITION 1
-#endif
-
-/*----------------------------------------------------------------------------
- * SMSC9115 Ethernet from SMSC9118 family
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE DEBUG_BASE
-#define CONFIG_LAN91C96_EXT_PHY
-
-#define CONFIG_BOOTP_SEND_HOSTNAME
-/*
- * BOOTP fields
- */
-#define CONFIG_BOOTP_SUBNETMASK 0x00000001
-#define CONFIG_BOOTP_GATEWAY 0x00000002
-#define CONFIG_BOOTP_HOSTNAME 0x00000004
-#define CONFIG_BOOTP_BOOTPATH 0x00000010
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * Environment setup
- *
- * Default boot order: mmc bootscript, MMC uImage, NOR image.
- * Network booting environment must be configured at site.
- */
-
-/* allow overwriting serial config and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyS0,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "norargs=setenv bootargs console=${console} " \
- "root=/dev/mtdblock3 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from MMC/SD ...; " \
- "autoscr ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from MMC/SD ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "norboot=echo Booting from NOR ...; " \
- "run norargs; " \
- "bootm 0x80000\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "if mmcinit; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run norboot; " \
- "fi; " \
- "fi; " \
- "else run norboot; fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
- * a basic sanity check ONLY
- * IF you would like to increase coverage, increase the end address
- * or run the test with custom options
- */
-#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
-#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * NOR FLASH usage ... default nCS0:
- * - one 256KB sector for U-Boot
- * - one 256KB sector for its parameters (not all used)
- * - eight sectors (2 MB) for kernel
- * - rest for JFFS2
- */
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-
-/*
- * NAND FLASH usage ... default nCS1:
- * - four 128KB sectors for X-Loader
- * - four 128KB sectors for U-Boot
- * - two 128KB sector for its parameters
- * - 32 sectors (4 MB) for kernel
- * - rest for filesystem
- */
-
-/*
- * OneNAND FLASH usage ... default nCS2:
- * - four 128KB sectors for X-Loader
- * - two 128KB sectors for U-Boot
- * - one 128KB sector for its parameters
- * - sixteen sectors (2 MB) for kernel
- * - rest for filesystem
- */
-
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#endif /* __CONFIG_H */
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
#endif
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+ "dfu_alt_info_emmc=" \
+ "rawemmc raw 0 3751936;" \
+ "boot part 1 1;" \
+ "rootfs part 1 2;" \
+ "MLO fat 1 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 1 1;" \
+ "spl-os-image fat 1 1;" \
+ "u-boot.img fat 1 1;" \
+ "uEnv.txt fat 1 1\0"
+
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0x4000000;" \
+ "fdt ram 0x80f80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFUARGS \
+ "dfu_bufsiz=0x10000\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_RAM
+
#include <configs/ti_omap5_common.h>
#define CONFIG_CONS_INDEX 3
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+/* USB GADGET */
+#define CONFIG_USB_DWC3_PHY_OMAP
+#define CONFIG_USB_DWC3_OMAP
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0403
+#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_USB_GADGET_DUALSPEED
+
+/* USB Device Firmware Update support */
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_RAM
+#define CONFIG_CMD_DFU
+
+#define CONFIG_DFU_MMC
+
/* Enabled commands */
#define CONFIG_CMD_DHCP /* DHCP Support */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.h:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_OPENRD_H
-#define _CONFIG_OPENRD_H
-
-/*
- * Version number information
- */
-#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
-#else
-# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
-# define CONFIG_IDENT_STRING "\nOpenRD-Client"
-# else
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_IDENT_STRING "\nOpenRD-Base"
-# else
-# error Unknown OpenRD board specified
-# endif
-# endif
-#endif
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_OPENRD_BASE /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x60000
-#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
-/*
- * Environment is right behind U-Boot in flash. Make sure U-Boot
- * doesn't grow into the environment area.
- */
-#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define MTDIDS_DEFAULT "nand0=nand_mtd"
-#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
- "0x400000@0x100000(uImage),"\
- "0x1fb00000@0x500000(rootfs)"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
- "mtdids="MTDIDS_DEFAULT"\0" \
- "mtdparts="MTDPARTS_DEFAULT"\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-# ifdef CONFIG_BOARD_IS_OPENRD_BASE
-# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-# else
-# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-# endif
-# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
-# define CONFIG_PHY_BASE_ADR 0x0
-# define PHY_NO "88E1121"
-# else
-# define CONFIG_PHY_BASE_ADR 0x8
-# define PHY_NO "88E1116"
-# endif
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MVEBU_MMC
-#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
-#endif /* CONFIG_CMD_MMC */
-
-#endif /* _CONFIG_OPENRD_BASE_H */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
+++ /dev/null
-/*
- * (C) Copyright 2010-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * Configuation settings for the esd OTC570 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
- * adapting the initial boot program.
- * Since the linker has to swallow that define, we must use a pure
- * hex number here!
- */
-#define CONFIG_SYS_TEXT_BASE 0x20002000
-
-/*
- * since a number of boards are not being listed in linux
- * arch/arm/tools/mach-types any more, the mach-types have to be
- * defined here
- */
-#define MACH_TYPE_OTC570 2166
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
-
-/* Misc CPU related */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-
-#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
-#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-/*
- * Hardware drivers
- */
-
-/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
-/* general purpose I/O */
-#define CONFIG_AT91_GPIO
-
-/* Console output */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/* LCD */
-#define CONFIG_LCD
-#undef CONFIG_SPLASH_SCREEN
-
-#ifdef CONFIG_LCD
-# define LCD_BPP LCD_COLOR8
-
-# ifndef CONFIG_SPLASH_SCREEN
-# define CONFIG_LCD_LOGO
-# define CONFIG_LCD_INFO
-# undef CONFIG_LCD_INFO_BELOW_LOGO
-# endif /* CONFIG_SPLASH_SCREEN */
-
-# undef LCD_TEST_PATTERN
-# define CONFIG_SYS_WHITE_ON_BLACK
-# define CONFIG_ATMEL_LCD
-# define CONFIG_SYS_CONSOLE_IS_IN_ENV
-# define CONFIG_OTC570_LCD_BASE (CONFIG_SYS_SDRAM_BASE + 0x03fa5000)
-# define CONFIG_CMD_BMP
-#endif /* CONFIG_LCD */
-
-/* RTC and I2C stuff */
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#ifdef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED 100000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-
-/* Configure data and clock pins for pio */
-# define I2C_INIT { \
- at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
- at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
-}
-# define I2C_SOFT_DECLARATIONS
-/* Configure data pin as output */
-# define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
-/* Configure data pin as input */
-# define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
-/* Read data pin */
-# define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4)
-/* Set data pin */
-# define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
-/* Set clock pin */
-# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
-# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-
-/* LED */
-#define CONFIG_AT91_LED
-
-/*
- * SDRAM: 1 bank, min 32, max 128 MB
- * Initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
-
-/*
- * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above
- * that address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-/* DataFlash */
-#ifdef CONFIG_SYS_USE_DATAFLASH
-# define CONFIG_ATMEL_DATAFLASH_SPI
-# define CONFIG_HAS_DATAFLASH
-# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
-# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
-# define AT91_SPI_CLK 15000000
-# define DATAFLASH_TCSS (0x1a << 16)
-# define DATAFLASH_TCHS (0x1 << 24)
-#endif
-
-/* NOR flash is not populated, disable it */
-#define CONFIG_SYS_NO_FLASH
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-# define CONFIG_NAND_ATMEL
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */
-# define CONFIG_SYS_NAND_DBW_8
-# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_FIT
-#define CONFIG_NET_RETRY_COUNT 20
-#undef CONFIG_RESET_PHY_R
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_FAT
-
-/* CAN */
-#define CONFIG_AT91_CAN
-
-/* hw-controller addresses */
-#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */
-
-#ifdef CONFIG_SYS_USE_DATAFLASH
-
-/* bootstrap + u-boot + env in dataflash on CS0 */
-# define CONFIG_ENV_IS_IN_DATAFLASH
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
- 0x8400)
-# define CONFIG_ENV_OFFSET 0x4200
-# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
- CONFIG_ENV_OFFSET)
-# define CONFIG_ENV_SIZE 0x4200
-
-#elif CONFIG_SYS_USE_NANDFLASH
-
-/* bootstrap + u-boot + env + linux in nandflash */
-# define CONFIG_ENV_IS_IN_NAND 1
-# define CONFIG_ENV_OFFSET 0xC0000
-# define CONFIG_ENV_SIZE 0x20000
-
-#endif
-
-#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
- 128*1024, 0x1000)
-
-#endif
#include "tegra210-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra210 (P2371-0000) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000"
/* Board-specific serial config */
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
-#define COUNTER_FREQUENCY 38400000
-
#endif /* _P2371_0000_H */
--- /dev/null
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _P2371_2180_H
+#define _P2371_2180_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+/* USB2.0 Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY 19200000
+
+#endif /* _P2371_2180_H */
#include "tegra210-common.h"
/* High-level configuration options */
-#define V_PROMPT "Tegra210 (P2571) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
/* Board-specific serial config */
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
-#define COUNTER_FREQUENCY 38400000
#define CONFIG_OF_BOARD_SETUP
#endif /* _P2571_H */
+++ /dev/null
-/*
- * Palm LifeDrive configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_BOOTCOMMAND \
- "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
- "source 0xa0000000; " \
- "else " \
- "bootm 0x0x60000; " \
- "fi; "
-#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 9600
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_IDE
-#define CONFIG_LCD
-#define CONFIG_PXA_LCD
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_LQ038J7DH53
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#else
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_SIZE 0x4000
-
-/*
- * IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define CONFIG_LBA48
-#undef CONFIG_IDE_LED
-#undef CONFIG_IDE_RESET
-
-#define __io
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x10
-#define CONFIG_SYS_ATA_REG_OFFSET 0x10
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x10
-
-#define CONFIG_SYS_ATA_STRIDE 1
-#endif
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012
-#define CONFIG_SYS_GAFR1_L_VAL 0x69988056
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa
-#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x01040001
-#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
-#define CONFIG_SYS_GAFR3_U_VAL 0x00000009
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0xc26b0000
-#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93
-#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff
-#define CONFIG_SYS_GPDR3_VAL 0x006ff38d
-#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee
-#define CONFIG_SYS_GPSR1_VAL 0x03affdae
-#define CONFIG_SYS_GPSR2_VAL 0x07554000
-#define CONFIG_SYS_GPSR3_VAL 0x01bc0785
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x01ffffff
-#define CONFIG_SYS_CCCR 0x02000210
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
-#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
-#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
-#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
-#define CONFIG_SYS_MDREFR_VAL 0x201fa031
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000003
-#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
-#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
-#define CONFIG_SYS_MCATT0_VAL 0x0001c391
-#define CONFIG_SYS_MCATT1_VAL 0x0001c391
-#define CONFIG_SYS_MCIO0_VAL 0x00014611
-#define CONFIG_SYS_MCIO1_VAL 0x0001c391
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Palm Tungsten|C configuration file
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/pxa-regs.h>
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
-#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
- "source 0xa0000000; " \
- "else " \
- "bootm 0x80000; " \
- "fi; "
-#define CONFIG_BOOTARGS \
- "console=tty0 console=ttyS0,115200"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- * STUART - the lower serial port on Colibri board
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_LCD
-#define CONFIG_PXA_LCD
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_ACX517AKN
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
-
-/*
- * NOR FLASH
- */
-#ifdef CONFIG_CMD_FLASH
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#else
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_ENV_ADDR 0x40000
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x00011004
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008
-#define CONFIG_SYS_GAFR1_L_VAL 0x60888050
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa
-#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
-#define CONFIG_SYS_GPCR0_VAL 0x0
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPDR0_VAL 0xcfff8140
-#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3
-#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
-#define CONFIG_SYS_GPSR0_VAL 0x00010f8f
-#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5
-#define CONFIG_SYS_GPSR2_VAL 0x03fe0800
-
-#define CONFIG_SYS_PSSR_VAL PSSR_RDH
-
-/* Clock setup:
- * CKEN[1] - PWM1 ; CKEN[6] - FFUART
- * CKEN[12] - MMC ; CKEN[16] - LCD
- */
-#define CONFIG_SYS_CKEN 0x00011042
-#define CONFIG_SYS_CCCR 0x00000161
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x800092c2
-#define CONFIG_SYS_MSC1_VAL 0x80008000
-#define CONFIG_SYS_MSC2_VAL 0x80008000
-#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9
-#define CONFIG_SYS_MDREFR_VAL 0x00118018
-#define CONFIG_SYS_MDMRS_VAL 0x00220032
-#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00010504
-#define CONFIG_SYS_MCMEM1_VAL 0x00010504
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00010e04
-#define CONFIG_SYS_MCIO1_VAL 0x00010e04
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Palm Treo 680 configuration file
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X
-#define CONFIG_PALMTREO680
-#define CONFIG_MACH_TYPE MACH_TYPE_TREO680
-
-#define CONFIG_SYS_MALLOC_LEN (4096*1024)
-
-#define CONFIG_LZMA
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_CONS_INDEX 3
-
-/* we have nand (although technically nand *is* flash...) */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_LCD
-/* #define CONFIG_KEYBOARD */ /* TODO */
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_ACX544AKN
-#define CONFIG_LCD_LOGO
-#define LCD_BPP LCD_COLOR16
-#define CONFIG_FB_ADDR 0x5c000000 /* internal SRAM */
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN /* requires "splashimage" env var */
-#define CONFIG_SPLASH_SCREEN_ALIGN /* requires "splashpos" env var */
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#define CONFIG_SYS_LONGHELP
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ "
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x0E000000
-#define CONFIG_SYS_GAFR0_U_VAL 0xA500001A
-#define CONFIG_SYS_GAFR1_L_VAL 0x60000002
-#define CONFIG_SYS_GAFR1_U_VAL 0xAAA07959
-#define CONFIG_SYS_GAFR2_L_VAL 0x02AAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL 0x41440F08
-#define CONFIG_SYS_GAFR3_L_VAL 0x56AA95FF
-#define CONFIG_SYS_GAFR3_U_VAL 0x00001401
-#define CONFIG_SYS_GPCR0_VAL 0x1FF80400
-#define CONFIG_SYS_GPCR1_VAL 0x03003FC1
-#define CONFIG_SYS_GPCR2_VAL 0x01C1E000
-#define CONFIG_SYS_GPCR3_VAL 0x01C1E000
-#define CONFIG_SYS_GPDR0_VAL 0xCFF90400
-#define CONFIG_SYS_GPDR1_VAL 0xFB22BFC1
-#define CONFIG_SYS_GPDR2_VAL 0x93CDFFDF
-#define CONFIG_SYS_GPDR3_VAL 0x0069FF81
-#define CONFIG_SYS_GPSR0_VAL 0x02000018
-#define CONFIG_SYS_GPSR1_VAL 0x00000000
-#define CONFIG_SYS_GPSR2_VAL 0x000C0000
-#define CONFIG_SYS_GPSR3_VAL 0x00080000
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x01ffffff
-#define CONFIG_SYS_CCCR 0x02000210
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
-#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
-#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
-#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
-#define CONFIG_SYS_MDREFR_VAL 0x201fa031
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-#define CONFIG_SYS_MECR_VAL 0x00000003
-#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
-#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
-#define CONFIG_SYS_MCATT0_VAL 0x0001c391
-#define CONFIG_SYS_MCATT1_VAL 0x0001c391
-#define CONFIG_SYS_MCIO0_VAL 0x00014611
-#define CONFIG_SYS_MCIO1_VAL 0x0001c391
-
-/*
- * USB
- */
-#define CONFIG_USB_DEVICE
-#define CONFIG_USB_TTY
-#define CONFIG_USB_DEV_PULLUP_GPIO 114
-
-/*
- * SPL
- */
-#define CONFIG_SPL_TEXT_BASE 0xa1700000 /* IPL loads SPL here */
-#define CONFIG_SPL_STACK 0x5c040000 /* end of internal SRAM */
-#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
-#define CONFIG_SPL_NAND_DOCG4 /* use lean docg4 nand spl driver */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* spl uses memcpy */
-
-/*
- * NAND
- */
-#define CONFIG_NAND_DOCG4
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
-#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
-#define CONFIG_BITREVERSE /* needed by docg4 driver */
-#define CONFIG_BCH /* needed by docg4 driver */
-
-/*
- * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image. It
- * will be rounded up to the next 64k boundary (the spl flash block size), so it
- * does not have to be exact, but you must ensure that it is not less than the
- * actual image size, or it may fail to boot (bricked phone)!
- * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
-*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
-
-/*
- * This is the byte offset into the flash at which the concatenated spl + u-boot
- * image is placed. It must be at the start of a block (256k boundary). Blocks
- * 0 - 5 are write-protected, so we start at block 6.
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000 /* block 6 */
-
-/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0xa0000000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-
-/* passed to linker by Makefile as arg to -Ttext option */
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c040000 /* end of internal SRAM */
-
-/*
- * environment
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_BUILD_ENVCRC
-#define CONFIG_ENV_SIZE 0x200
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=usbtty\0" \
- "stdout=usbtty\0" \
- "stderr=usbtty"
-#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
-ip=192.168.11.102:::255.255.255.0:treo:usb0"
-#define CONFIG_BOOTDELAY 3
-
-#if 0 /* example: try 2nd mmc partition, then nand */
-#define CONFIG_BOOTCOMMAND \
- "mmc rescan; " \
- "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then " \
- "bootm 0xa1000000; " \
- "elif nand read 0xa1000000 0x280000 0x240000; then " \
- "bootm 0xa1000000; " \
- "fi; "
-#endif
-
-/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
-#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
-
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the phytec PCM-052 SoM.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_VF610
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE UART1_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT (1)
+#define CONFIG_BAUDRATE 115200
+
+#undef CONFIG_CMD_IMLS
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
+
+#define CONFIG_JFFS2_NAND
+
+/* UBI */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT "nand0=NAND"
+#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
+ ",384k(bootloader)"\
+ ",128k(env1)"\
+ ",128k(env2)"\
+ ",128k(dtb)"\
+ ",6144k(kernel)"\
+ ",65536k(ramdisk)"\
+ ",450944k(root)"
+#endif
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+/* QSPI Configs*/
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C3
+#define CONFIG_SYS_I2C_MXC
+
+/* RTC (actually an RV-4162 but M41T62-compatible) */
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_RTC_BUS_NUM 2
+
+/* EEPROM (24FC256) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_BUS 2
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x82000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_SYS_TEXT_BASE 0x3f408000
+#define CONFIG_BOARD_SIZE_LIMIT 524288
+
+#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "blimg_file=u-boot.imx\0" \
+ "blsec_addr=0x81000000\0" \
+ "blimg_addr=0x81000400\0" \
+ "kernel_file=zImage\0" \
+ "kernel_addr=0x82000000\0" \
+ "fdt_file=vf610-pcm052.dtb\0" \
+ "fdt_addr=0x81000000\0" \
+ "ram_file=uRamdisk\0" \
+ "ram_addr=0x83000000\0" \
+ "filesys=rootfs.ubifs\0" \
+ "sys_addr=0x81000000\0" \
+ "tftploc=/path/to/tftp/directory/\0" \
+ "nfs_root=/path/to/nfs/root\0" \
+ "tftptimeout=1000\0" \
+ "tftptimeoutcountmax=1000000\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "bootargs_base=setenv bootargs rw mem=256M " \
+ "console=ttyLP1,115200n8\0" \
+ "bootargs_sd=setenv bootargs ${bootargs} " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
+ "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
+ "bootargs_nand=setenv bootargs ${bootargs} " \
+ "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
+ "bootargs_ram=setenv bootargs ${bootargs} " \
+ "root=/dev/ram rw initrd=${ram_addr}\0" \
+ "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
+ "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
+ "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
+ "bootz ${kernel_addr} - ${fdt_addr}\0" \
+ "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
+ "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
+ "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
+ "bootz ${kernel_addr} - ${fdt_addr}\0" \
+ "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
+ "nand read ${fdt_addr} dtb; " \
+ "nand read ${kernel_addr} kernel; " \
+ "bootz ${kernel_addr} - ${fdt_addr}\0" \
+ "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
+ "nand read ${fdt_addr} dtb; " \
+ "nand read ${kernel_addr} kernel; " \
+ "nand read ${ram_addr} ramdisk; " \
+ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
+ "update_bootloader_from_tftp=mtdparts default; " \
+ "nand read ${blsec_addr} bootloader; " \
+ "mw.b ${blimg_addr} 0xff 0x5FC00; " \
+ "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
+ "nand erase.part bootloader; " \
+ "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
+ "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
+ "${kernel_file}; " \
+ "then mtdparts default; " \
+ "nand erase.part kernel; " \
+ "nand write ${kernel_addr} kernel ${filesize}; " \
+ "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
+ "nand erase.part dtb; " \
+ "nand write ${fdt_addr} dtb ${filesize}; fi\0" \
+ "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
+ "then setenv fdtsize ${filesize}; " \
+ "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
+ "mtdparts default; " \
+ "nand erase.part dtb; " \
+ "nand write ${fdt_addr} dtb ${fdtsize}; " \
+ "nand erase.part kernel; " \
+ "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
+ "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+ "then mtdparts default; " \
+ "nand erase.part root; " \
+ "ubi part root; " \
+ "ubi create rootfs; " \
+ "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
+ "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+ "then mtdparts default; " \
+ "nand erase.part ramdisk; " \
+ "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
+
+/* miscellaneous commands */
+#define CONFIG_CMD_ELF
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80010000
+#define CONFIG_SYS_MEMTEST_END 0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM (0x80000000)
+#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_OFFSET 0xA0000
+#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND 0xC0000
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#endif
/* I2C config */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copied from lubbock.h
- *
- * (C) Copyright 2004
- * BEC Systems <http://bec-systems.com>
- * Cliff Brake <cliff.brake@gmail.com>
- * Configuation settings for the Accelent/Vibren PXA255 IDP
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/pxa-regs.h>
-
-/*
- * If we are developing, we might want to start U-Boot from RAM
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-/*
- * define the following to enable debug blinks. A debug blink function
- * must be defined in memsetup.S
- */
-#undef DEBUG_BLINK_ENABLE
-#undef DEBUG_BLINKC_ENABLE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
-
-#undef CONFIG_LCD
-#ifdef CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-
-#define CONFIG_MMC 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_BOARD_LATE_INIT
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * PXA250 IDP memory map information
- */
-
-#define IDP_CS5_ETH_OFFSET 0x03400000
-
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
-#define CONFIG_SMC_USE_32_BIT 1
-/* #define CONFIG_SMC_USE_IOFUNCS */
-
-/* the following has to be set high -- suspect something is wrong with
- * with the tftp timeout routines. FIXME!!!
- */
-#define CONFIG_NET_RETRY_COUNT 100
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
-#define CONFIG_CONS_INDEX 3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-/* #define CONFIG_INITRD_TAG 1 */
-
-/*
- * Current memory map for Vibren supplied Linux images:
- *
- * Flash:
- * 0 - 0x3ffff (size = 0x40000): bootloader
- * 0x40000 - 0x13ffff (size = 0x100000): kernel
- * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
- *
- * RAM:
- * 0xa0008000 - kernel is loaded
- * 0xa3000000 - Uboot runs (48MB into RAM)
- *
- */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "prog_boot_mmc=" \
- "mw.b 0xa0000000 0xff 0x40000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0000000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x3ffff; " \
- "erase 0x0 0x3ffff; " \
- "cp.b 0xa0000000 0x0 0x40000; " \
- "reset;" \
- "fi\0" \
- "prog_uzImage_mmc=" \
- "mw.b 0xa0000000 0xff 0x100000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0000000 uzImage; " \
- "then " \
- "protect off 0x40000 0xfffff; " \
- "erase 0x40000 0xfffff; " \
- "cp.b 0xa0000000 0x40000 0x100000; " \
- "fi\0" \
- "prog_jffs_mmc=" \
- "mw.b 0xa0000000 0xff 0x1e00000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0000000 root.jffs; " \
- "then " \
- "protect off 0x140000 0x1f3ffff; " \
- "erase 0x140000 0x1f3ffff; " \
- "cp.b 0xa0000000 0x140000 0x1e00000; " \
- "fi\0" \
- "boot_mmc=" \
- "if mmcinit && " \
- "fatload mmc 0 0xa1000000 uzImage && " \
- "then " \
- "bootm 0xa1000000; " \
- "fi\0" \
- "prog_boot_net=" \
- "mw.b 0xa0000000 0xff 0x100000; " \
- "if bootp 0xa0000000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x3ffff; " \
- "erase 0x0 0x3ffff; " \
- "cp.b 0xa0000000 0x0 0x40000; " \
- "reset; " \
- "fi\0" \
- "prog_uzImage_net=" \
- "mw.b 0xa0000000 0xff 0x100000; " \
- "if bootp 0xa0000000 uzImage; " \
- "then " \
- "protect off 0x40000 0xfffff; " \
- "erase 0x40000 0xfffff; " \
- "cp.b 0xa0000000 0x40000 0x100000; " \
- "fi\0" \
- "prog_jffs_net=" \
- "mw.b 0xa0000000 0xff 0x1e00000; " \
- "if bootp 0xa0000000 root.jffs; " \
- "then " \
- "protect off 0x140000 0x1f3ffff; " \
- "erase 0x140000 0x1f3ffff; " \
- "cp.b 0xa0000000 0x140000 0x1e00000; " \
- "fi\0"
-
-
-/* "erase_env=" */
-/* "protect off" */
-
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
-
-#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
-
-#define RTC 1 /* enable 32KHz osc */
-
-#ifdef CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
-
-/*
- * GPIO settings
- */
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
-#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x2
-#define CONFIG_SYS_GPCR0_VAL 0x1800400
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPDR0_VAL 0xc1818440
-#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
-#define CONFIG_SYS_GPDR2_VAL 0x1ffff
-#define CONFIG_SYS_GPSR0_VAL 0x8000
-#define CONFIG_SYS_GPSR1_VAL 0x3f0002
-#define CONFIG_SYS_GPSR2_VAL 0x1c000
-
-#define CONFIG_SYS_PSSR_VAL 0x20
-
-#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
-#define CONFIG_SYS_CKEN 0x0
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
-#define CONFIG_SYS_MSC1_VAL 0x43AC494C
-#define CONFIG_SYS_MSC2_VAL 0x39D449D4
-#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
-#define CONFIG_SYS_MDREFR_VAL 0x0085C017
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000003
-#define CONFIG_SYS_MCMEM0_VAL 0x00014405
-#define CONFIG_SYS_MCMEM1_VAL 0x00014405
-#define CONFIG_SYS_MCATT0_VAL 0x00014405
-#define CONFIG_SYS_MCATT1_VAL 0x00014405
-#define CONFIG_SYS_MCIO0_VAL 0x00014405
-#define CONFIG_SYS_MCIO1_VAL 0x00014405
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* put cfg at end of flash for now */
-#define CONFIG_ENV_IS_IN_FLASH 1
- /* Addr of Environment Sector */
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
-#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
- *
- * Configuration settings for the Dave/DENX QongEVB-LITE board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31 /* This is a mx31 */
-#define CONFIG_QONG
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-#define CONFIG_MXC_GPIO
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
-
-#define CONFIG_MXC_SPI
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_RTC_MC13XXX
-
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 1
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 100000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-
-/* FPGA */
-#define CONFIG_FPGA
-#define CONFIG_QONG_FPGA
-#define CONFIG_FPGA_BASE (CS1_BASE)
-#define CONFIG_FPGA_LATTICE
-#define CONFIG_FPGA_COUNT 1
-
-#ifdef CONFIG_QONG_FPGA
-/* Ethernet */
-#define CONFIG_DNET
-#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_MX3
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
-
-/* USB */
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI /* Enable EHCI USB support */
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 2
-#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
-#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#endif /* CONFIG_CMD_USB */
-
-/*
- * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
- * initial TFTP transfer, should the user wish one, significantly.
- */
-#define CONFIG_ARP_TIMEOUT 200UL
-
-#endif /* CONFIG_QONG_FPGA */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_UNZIP
-
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "uboot_addr=A0000000\0" \
- "kernel_addr=A00C0000\0" \
- "ramdisk_addr=A0300000\0" \
- "u-boot=qong/u-boot.bin\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=qong\0" \
- "bootfile=qong/uImage\0" \
- "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm\0" \
- "bootcmd=run flash_self\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
- " +${filesize};cp.b ${fileaddr} " \
- __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
- "upd=run load update\0" \
- "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
- "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
- "vmode:0\0" \
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* memtest works on first 255MB of RAM */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_MISC_INIT_R
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
-
-/*
- * NAND driver
- */
-
-#ifndef __ASSEMBLY__
-extern void qong_nand_plat_init(void *chip);
-extern int qong_nand_rdy(void *chip);
-#endif
-#define CONFIG_NAND_PLAT
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE CS3_BASE
-#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
-
-#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
-#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
-#define QONG_NAND_WRITE(addr, cmd) \
- do { \
- __REG8(addr) = cmd; \
- } while (0)
-
-#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
-#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* Flash memory is CFI compliant */
-#define CONFIG_SYS_FLASH_CFI
-/* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_CFI_DRIVER
-/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-/* Use hardware sector protection */
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * Filesystem
- */
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
- "nand0=gen_nand"
-#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:" \
- "512k(U-Boot),128k(env1),128k(env2)," \
- "2304k(kernel),13m(ramdisk),-(user);" \
- "gen_nand:" \
- "128m(nand)"
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_RD6281A_H
-#define _CONFIG_RD6281A_H
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nMarvell-RD6281A"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_MACH_RD6281A /* Machine type */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_IDE
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
-#else
-#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
-#endif
-/*
- * max 4k env size is enough, but in case of nand
- * it has to be rounded to sector size
- */
-#define CONFIG_ENV_SIZE 0x20000 /* 128k */
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
- "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
- "${x_bootcmd_usb}; bootm 0x6400000;"
-
-#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
- "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
- "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
- "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
- "x_bootcmd_usb=usb start\0" \
- "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
-#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
-#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
-#define CONFIG_PHY_BASE_ADR 0x0A
-#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /*CONFIG_MVSATA_IDE*/
-
-#endif /* _CONFIG_RD6281A_H */
+++ /dev/null
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * SPDX-License-Identifier: GPL-2.0+
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- * 2003/13/06 Initial MP10 Support copied from wepep250
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */
-#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
-
-#define CONFIG_IMX_SERIAL
-#define CONFIG_IMX_SERIAL1
-/*
- * Select serial console configuration
- */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY -1
-#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
-#define CONFIG_BOOTCOMMAND "bootm 10040000"
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.10.10.9
-#define CONFIG_SERVERIP 10.10.10.10
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP /* undef saves memory */
-#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
-
-#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0x08F00000
-
-#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
-
-#define CONFIG_BAUDRATE 115200
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG 1 /* send initrd params */
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-
-/* SDRAM Setup Values
-0x910a8300 Precharge Command CAS 3
-0x910a8200 Precharge Command CAS 2
-
-0xa10a8300 AutoRefresh Command CAS 3
-0xa10a8200 Set AutoRefresh Command CAS 2 */
-
-#define PRECHARGE_CMD 0x910a8200
-#define AUTOREFRESH_CMD 0xa10a8200
-
-/*
- * SDRAM Memory Map
- */
-/* SH FIXME */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
-#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
-#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-
-#define CONFIG_SYS_TEXT_BASE 0x10000000
-
-#define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
-
-/*
- * Configuration for FLASH memory for the Synertronixx board
- */
-
-/* #define SCB9328_FLASH_32M */
-
-/* 32MB */
-#ifdef SCB9328_FLASH_32M
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
-#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
-#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
-#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
-#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
-#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
-#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
-#else
-
-/* 16MB */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
-#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
-#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
-#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
-#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
-#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
-#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
-#endif /* SCB9328_FLASH_32M */
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
- is not so clear to me. In other words we can provide more informations
- to user, but this expects more complex flash handling we do not provide
- now.*/
-#undef CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-/* Setup for PA23 which is Reset Default PA23 but has to become
- CS5 */
-
-#define CONFIG_SYS_GPR_A_VAL 0x00800000
-#define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
-
-#define CONFIG_SYS_MONITOR_BASE 0x10000000
-#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
-#define CONFIG_ENV_SIZE 0x20000
-
-#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
-
-/*
- * CSxU_VAL:
- * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
- * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
- *
- * CSxL_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
- * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
- */
-
-#define CONFIG_SYS_CS0U_VAL 0x000F2000
-#define CONFIG_SYS_CS0L_VAL 0x11110d01
-#define CONFIG_SYS_CS1U_VAL 0x000F0a00
-#define CONFIG_SYS_CS1L_VAL 0x11110601
-#define CONFIG_SYS_CS2U_VAL 0x0
-#define CONFIG_SYS_CS2L_VAL 0x0
-
-#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
-#define CONFIG_SYS_CS3L_VAL 0x00000303
-
-#define CONFIG_SYS_CS4U_VAL 0x000F0a00
-#define CONFIG_SYS_CS4L_VAL 0x11110301
-
-/* CNC == 3 too long
- #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
-
-/* #define CONFIG_SYS_CS5U_VAL 0x00008400
- mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
- kaum langsamer ist */
-/* #define CONFIG_SYS_CS5U_VAL 0x00009400
- #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
-
-#define CONFIG_SYS_CS5U_VAL 0x00008400
-#define CONFIG_SYS_CS5L_VAL 0x00000D03
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x16000000
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE+4)
-
-/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
- f_ref=16,777MHz
-
- 0x002a141f: 191,9944MHz
- 0x040b2007: 144MHz
- 0x042a141f: 96MHz
- 0x0811140d: 64MHz
- 0x040e200e: 150MHz
- 0x00321431: 200MHz
-
- 0x08001800: 64MHz mit 16er Quarz
- 0x04001800: 96MHz mit 16er Quarz
- 0x04002400: 144MHz mit 16er Quarz
-
- 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
- |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
-
-#define CPU200
-
-#ifdef CPU200
-#define CONFIG_SYS_MPCTL0_VAL 0x00321431
-#else
-#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
-#endif
-
-/* #define BUS64 */
-#define BUS72
-
-#ifdef BUS72
-#define CONFIG_SYS_SPCTL0_VAL 0x04002400
-#endif
-
-#ifdef BUS96
-#define CONFIG_SYS_SPCTL0_VAL 0x04001800
-#endif
-
-#ifdef BUS64
-#define CONFIG_SYS_SPCTL0_VAL 0x08001800
-#endif
-
-/* Das ist der BCLK Divider, der aus der System PLL
- BCLK und HCLK erzeugt:
- 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
- 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
- 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
- 0x2f001003 : 192MHz/5=38,4MHz
- 0x2f000003 : 64MHz/1
- Bit 22: SPLL Restart
- Bit 21: MPLL Restart */
-
-#ifdef BUS64
-#define CONFIG_SYS_CSCR_VAL 0x2f030003
-#endif
-
-#ifdef BUS72
-#define CONFIG_SYS_CSCR_VAL 0x2f030403
-#endif
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR 0x08400000
-
-#define MHZ16QUARZINUSE
-
-#ifdef MHZ16QUARZINUSE
-#define CONFIG_SYSPLL_CLK_FREQ 16000000
-#else
-#define CONFIG_SYSPLL_CLK_FREQ 16780000
-#endif
-
-#define CONFIG_SYS_CLK_FREQ 16780000
-
-/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
-#define CONFIG_SYS_FMCR_VAL 0x00000001
-
-/* Bit[0:3] contain PERCLK1DIV for UART 1
- 0x000b00b ->b<- -> 192MHz/12=16MHz
- 0x000b00b ->8<- -> 144MHz/09=16MHz
- 0x000b00b ->3<- -> 64MHz/4=16MHz */
-
-#ifdef BUS96
-#define CONFIG_SYS_PCDR_VAL 0x000b00b5
-#endif
-
-#ifdef BUS64
-#define CONFIG_SYS_PCDR_VAL 0x000b00b3
-#endif
-
-#ifdef BUS72
-#define CONFIG_SYS_PCDR_VAL 0x000b00b8
-#endif
-
-#endif /* __CONFIG_H */
*
*/
#define CONFIG_MACB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_RMII /* use reduced MII inteface */
#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
#define CONFIG_AT91_WANTS_COMMON_PHY
/* General Boot Parameter */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "run flashboot"
+#define CONFIG_BOOT_RETRY_TIME 30
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE \
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * #define DEBUG 1
- */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SNOWBALL
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_U8500
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
-
-/*-----------------------------------------------------------------------
- * Size of environment and malloc() pool
- */
-/*
- * If you use U-Boot as crash kernel, make sure that it does not overwrite
- * information saved by kexec during panic. Kexec expects the start
- * address of the executable 32K above "crashkernel" address.
- */
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE (8*1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_OFFSET 0x0118000
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
-
-/*
- * PL011 Configuration
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_SERIAL_RLCR
-#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-
-/*
- * U8500 UART registers base for 3 serial devices
- */
-#define CFG_UART0_BASE 0x80120000
-#define CFG_UART1_BASE 0x80121000
-#define CFG_UART2_BASE 0x80007000
-#define CFG_SERIAL0 CFG_UART0_BASE
-#define CFG_SERIAL1 CFG_UART1_BASE
-#define CFG_SERIAL2 CFG_UART2_BASE
-#define CONFIG_PL011_CLOCK 38400000
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
- (void *)CFG_SERIAL2 }
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Devices and file systems
- */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/*
- * Commands
- */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY 1
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
-"mmc dev 1; " \
- "if run loadbootscript; " \
- "then run bootscript; " \
- "else " \
- "if run mmcload; " \
- "then run mmcboot; " \
- "else " \
- "mmc dev 0; " \
- "if run emmcloadbootscript; " \
- "then run bootscript; " \
- "else " \
- "if run emmcload; " \
- "then run emmcboot; " \
- "else " \
- "echo No media to boot from; " \
- "fi; " \
- "fi; " \
- "fi; " \
- "fi; "
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr=0x00100000\0" \
- "console=ttyAMA2,115200n8\0" \
- "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \
- "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript " \
- "from mmc ...; source ${loadaddr}\0" \
- "memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \
- "hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \
- "memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \
- "mem=64M@160M mem_mali=32M@224M " \
- "pmem_hwb=128M@256M mem=128M@384M\0" \
- "memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \
- "hwmem=168M@M160M mem=48M@328M " \
- "mem_issw=1M@383M mem=640M@384M\0" \
- "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \
- "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \
- "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \
- "commonargs=setenv bootargs console=${console} " \
- "vmalloc=300M\0" \
- "emmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p3 " \
- "rootwait\0" \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console}\0" \
- "emmcboot=echo Booting from eMMC ...; " \
- "run commonargs emmcargs memargs; " \
- "bootm ${loadaddr}\0" \
- "mmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk1p2 " \
- "rootwait earlyprintk\0" \
- "mmcboot=echo Booting from external MMC ...; " \
- "run commonargs mmcargs memargs; " \
- "bootm ${loadaddr}\0" \
- "fdt_high=0x2BC00000\0" \
- "stdout=serial,usbtty\0" \
- "stdin=serial,usbtty\0" \
- "stderr=serial,usbtty\0"
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SETUP_MEMORY_TAGS 2
-#define CONFIG_INITRD_TAG 1
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
-
-/*
- * additions for new relocation code
- */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/* landing address before relocation */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x0
-#endif
-
-/*
- * MMC related configs
- */
-#define CONFIG_ARM_PL180_MMCI
-#define MMC_BLOCK_SIZE 512
-#define CFG_EMMC_BASE 0x80114000
-#define CFG_MMC_BASE 0x80126000
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * base register values for U8500
- */
-#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */
-
-
-/*
- * U8500 GPIO register base for 9 banks
- */
-#define CONFIG_DB8500_GPIO
-#define CFG_GPIO_0_BASE 0x8012E000
-#define CFG_GPIO_1_BASE 0x8012E080
-#define CFG_GPIO_2_BASE 0x8000E000
-#define CFG_GPIO_3_BASE 0x8000E080
-#define CFG_GPIO_4_BASE 0x8000E100
-#define CFG_GPIO_5_BASE 0x8000E180
-#define CFG_GPIO_6_BASE 0x8011E000
-#define CFG_GPIO_7_BASE 0x8011E080
-#define CFG_GPIO_8_BASE 0xA03FE000
-
-#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
-#define __CONFIG_SOCFPGA_ARRIA5_H__
-
-#include <asm/arch/socfpga_base_addrs.h>
-
-/* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FAT_WRITE
-#define CONFIG_HW_WATCHDOG
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_USB_MASS_STORAGE
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-
-/* Booting Linux */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-
-/* PHY */
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
-
-/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_arria5
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "bootimage=zImage\0" \
- "fdt_addr=100\0" \
- "fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "mmcroot=/dev/mmcblk0p2\0" \
- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${mmcroot} rw rootwait;" \
- "bootz ${loadaddr} - ${fdt_addr}\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:1 ${loadaddr} ${bootimage};" \
- "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
- "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_arria5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
/*
* Cache
*/
-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 4096
/*
+++ /dev/null
-/*
- * Copyright (C) 2014 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_H__
-
-#include <asm/arch/socfpga_base_addrs.h>
-
-/* U-Boot Commands */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FAT_WRITE
-#define CONFIG_HW_WATCHDOG
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_USB_MASS_STORAGE
-
-/* Memory configurations */
-#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
-
-/* Booting Linux */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
-#define CONFIG_LOADADDR 0x01000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Ethernet on SoC (EMAC) */
-#if defined(CONFIG_CMD_NET)
-
-/* PHY */
-#define CONFIG_PHY_MICREL
-#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
-
-/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_cyclone5
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "bootimage=zImage\0" \
- "fdt_addr=100\0" \
- "fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "mmcroot=/dev/mmcblk0p2\0" \
- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${mmcroot} rw rootwait;" \
- "bootz ${loadaddr} - ${fdt_addr}\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:1 ${loadaddr} ${bootimage};" \
- "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
- "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
-
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
-
-#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_cyclone5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */
#endif
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+/* Environment is in MMC */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#endif
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_QUIET_TEST
/*
* Command support defines
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Achim Ehrlich <aehrlich@taskit.de>
- * taskit GmbH <www.taskit.de>
- *
- * (C) Copyright 2012
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * Configuation settings for the stamp9g20 CPU module.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * SoC must be defined first, before hardware.h is included.
- * In this case SoC is defined in boards.cfg.
- */
-#include <asm/hardware.h>
-
-/*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
- * program. Since the linker has to swallow that define, we must use a pure
- * hex number here!
- */
-#define CONFIG_SYS_TEXT_BASE 0x23f00000
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
-
-/* misc settings */
-#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
-#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
-#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */
-#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */
-#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
-
-/* setting board specific options */
-#ifdef CONFIG_PORTUXG20
-# define CONFIG_MACH_TYPE MACH_TYPE_PORTUXG20
-# define CONFIG_MACB
-#else
-# define CONFIG_MACH_TYPE MACH_TYPE_STAMP9G20
-#endif
-
-/*
- * SDRAM: 1 bank, 64 MB, base address 0x20000000
- * Already initialized before u-boot gets started.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (64 << 20)
-
-/*
- * Perform a SDRAM Memtest from the start of SDRAM
- * till the beginning of the U-Boot position in RAM.
- */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000)
-
-/*
- * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
- * leaving the correct space for initial global data structure above that
- * address while providing maximum stack area below.
- */
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-/* NAND flash settings */
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO /* enable the GPIO features */
-#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#define CONFIG_BAUDRATE 115200
-
-/* LED configuration */
-#define CONFIG_STATUS_LED
-#define CONFIG_BOARD_SPECIFIC_LED
-
-/* The LED PINs */
-#define CONFIG_RED_LED AT91_PIN_PC5
-#define CONFIG_GREEN_LED AT91_PIN_PC4
-#define CONFIG_YELLOW_LED AT91_PIN_PC10
-
-#define STATUS_LED_RED 0
-#define STATUS_LED_GREEN 1
-#define STATUS_LED_YELLOW 2
-
-/* Red LED */
-#define STATUS_LED_BIT STATUS_LED_RED
-#define STATUS_LED_STATE STATUS_LED_OFF
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-
-/* Green LED */
-#define STATUS_LED_BIT1 STATUS_LED_GREEN
-#define STATUS_LED_STATE1 STATUS_LED_ON
-#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
-
-/* Yellow LED */
-#define STATUS_LED_BIT2 STATUS_LED_YELLOW
-#define STATUS_LED_STATE2 STATUS_LED_OFF
-#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
-
-/* Boot status LED */
-#define STATUS_LED_BOOT STATUS_LED_GREEN
-
-/*
- * Ethernet configuration
- *
- * PortuxG20 has always ethernet but for Stamp9G20 you
- * can enable it here if your baseboard features ethernet.
- */
-
-#define CONFIG_MACB
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-
-#ifdef CONFIG_MACB
-# define CONFIG_RMII /* use reduced MII inteface */
-# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-/* BOOTP and DHCP options */
-# define CONFIG_BOOTP_BOOTFILESIZE
-# define CONFIG_BOOTP_BOOTPATH
-# define CONFIG_BOOTP_GATEWAY
-# define CONFIG_BOOTP_HOSTNAME
-# define CONFIG_NFSBOOTCOMMAND \
- "setenv autoload yes; setenv autoboot yes; " \
- "setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
- "dhcp"
-#endif /* CONFIG_MACB */
-
-/* Enable the watchdog */
-#define CONFIG_AT91SAM9_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-
-/* USB configuration */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_USB_STORAGE
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-
-/* General Boot Parameter */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "run flashboot"
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * RAM Memory address where to put the
- * Linux Kernel befor starting.
- */
-#define CONFIG_SYS_LOAD_ADDR 0x22000000
-
-/*
- * The NAND Flash partitions:
- * ==========================================
- * 0x0000000-0x001ffff -> 128k, bootstrap
- * 0x0020000-0x005ffff -> 256k, u-boot
- * 0x0060000-0x007ffff -> 128k, env1
- * 0x0080000-0x009ffff -> 128k, env2 (backup)
- * 0x0100000-0x06fffff -> 6M, kernel
- * 0x0700000-0x8000000 -> 121M, RootFS
- */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET ((128 + 256) << 10)
-#define CONFIG_ENV_OFFSET_REDUND ((128 + 256 + 128) << 10)
-#define CONFIG_ENV_SIZE (128 << 10)
-
-/*
- * Predefined environment variables.
- * Usefull to define some easy to use boot commands.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- \
- "basicargs=console=ttyS0,115200\0" \
- \
- "mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro," \
- "256k(uboot)ro,128k(env1)ro," \
- "128k(env2)ro,6M(linux),-(root)rw\0" \
- \
- "flashboot=setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/mtdblock5 rootfstype=jffs2; " \
- "nand read 0x22000000 0x100000 0x600000; " \
- "bootm 22000000\0" \
- \
- "sdboot=setenv bootargs ${basicargs} ${mtdparts} " \
- "root=/dev/mmcblk0p1 rootwait; " \
- "nand read 0x22000000 0x100000 0x600000; " \
- "bootm 22000000"
-
-/* Command line & features configuration */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_LED
-
-#ifdef CONFIG_MACB
-# define CONFIG_CMD_PING
-# define CONFIG_CMD_DHCP
-#endif /* CONFIG_MACB */
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * include/configs/stout.h
+ * This file is Stout board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __STOUT_H
+#define __STOUT_H
+
+#undef DEBUG
+#define CONFIG_R8A7790
+#define CONFIG_RMOBILE_BOARD_STRING "Stout"
+
+#include "rcar-gen2-common.h"
+
+/* #define CONFIG_BOARD_LATE_INIT */
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0xB0000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0xE8080000
+#endif
+
+/* STACK */
+#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
+#endif
+#define STACK_AREA_SIZE 0xC000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE 0x40000000
+#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_SCIF_A
+
+/* SPI */
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_QUAD
+#define CONFIG_SYS_NO_FLASH
+
+/* SH Ether */
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_RCAR
+#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
+#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
+#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
+#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
+#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
+#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
+#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_STORAGE
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA 0x00400000
+/* MSIF, SCIFA0 */
+#define CONFIG_SMSTP2_ENA 0x00002010
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA 0x00000180
+
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ 97500000
+
+#endif /* __STOUT_H */
#ifndef _SUNXI_COMMON_CONFIG_H
#define _SUNXI_COMMON_CONFIG_H
+#include <asm/arch/cpu.h>
#include <linux/stringify.h>
#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
#endif
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
-# define CONFIG_DW_SERIAL
-#endif
-
-/*
- * Display CPU information
- */
-#define CONFIG_DISPLAY_CPUINFO
-
/* Serial & console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
#define CONFIG_SYS_NS16550_CLK 24000000
-#ifndef CONFIG_DM_SERIAL
+#ifdef CONFIG_DM_SERIAL
+# define CONFIG_DW_SERIAL
+#else
# define CONFIG_SYS_NS16550_REG_SIZE -4
# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
#endif
/* CPU */
+#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
#endif
-/* 4MB of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
+/* 64MB of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
/*
* Miscellaneous configurable options
* The amount of RAM to keep free at the top of RAM when relocating u-boot,
* to use as framebuffer. This must be a multiple of 4096.
*/
-#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
-#define CONFIG_SUNXI_MAX_FB_SIZE (12 << 20)
-#else
-#define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20)
-#endif
+#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
/* Do we want to initialize a simple FB? */
#define CONFIG_VIDEO_DT_SIMPLEFB
#define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */
/*
- * 240M RAM (256M minimum minus space for the framebuffer),
+ * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
#define MEM_LAYOUT_ENV_SETTINGS \
- "bootm_size=0xf000000\0" \
+ "bootm_size=0xa000000\0" \
"kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \
"fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \
"scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \
#define BOOT_TARGET_DEVICES_USB(func)
#endif
+/* FEL boot support, auto-execute boot.scr if a script address was provided */
+#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
+ "bootcmd_fel=" \
+ "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \
+ "echo '(FEL boot)'; " \
+ "source ${fel_scriptaddr}; " \
+ "fi\0"
+#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \
+ "fel "
+
#define BOOT_TARGET_DEVICES(func) \
+ func(FEL, fel, na) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_USB(func) \
/*
* Board NAND Info.
*/
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_HZ 1000
-#define CONFIG_IMX6_THERMAL
+#define CONFIG_IMX_THERMAL
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_I2C_EDID
"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
"rdinit=/sbin/init enable_wait_mode=off\0" \
"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
- "mmc read 0x10800000 0x800 0x4000; bootm\0" \
+ "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
"run bootargs_upd; " \
#ifndef __TEGRA_COMMON_POST_H
#define __TEGRA_COMMON_POST_H
+/*
+ * Size of malloc() pool
+ */
+#ifdef CONFIG_USB_FUNCTION_DFU
+#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \
+ CONFIG_SYS_DFU_DATA_BUF_SIZE + \
+ CONFIG_SYS_DFU_MAX_FILE_SIZE)
+#else
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
+#endif
+
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+#endif
+
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
#define CONFIG_CMD_USB_MASS_STORAGE
/* DFU protocol */
#define CONFIG_USB_FUNCTION_DFU
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
+#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M
#define CONFIG_CMD_DFU
#ifdef CONFIG_MMC
#define CONFIG_DFU_MMC
#ifdef CONFIG_SPI_FLASH
#define CONFIG_DFU_SF
#endif
+#define CONFIG_DFU_RAM
#endif
#endif /* _TEGRA_COMMON_USB_GADGET_H_ */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
-/*
- * Size of malloc() pool
- */
-#ifdef CONFIG_DFU_MMC
-#define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \
- CONFIG_SYS_DFU_DATA_BUF_SIZE)
-#else
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-#endif
-
-#ifndef CONFIG_ARM64
-#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
-#endif
-
/*
* NS16550 Configuration
*/
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_FAT_WRITE
#endif
#endif /* _TEGRA_COMMON_H_ */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_SYS_TEXT_BASE 0x8010E000
+#define CONFIG_SYS_TEXT_BASE 0x80110000
/*
* Memory layout for where various images get loaded by boot scripts:
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_SYS_TEXT_BASE 0x0010E000
+#define CONFIG_SYS_TEXT_BASE 0x00110000
/*
* Memory layout for where various images get loaded by boot scripts:
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_SYS_TEXT_BASE 0x8010E000
+#define CONFIG_SYS_TEXT_BASE 0x80110000
/* Generic Interrupt Controller */
#define CONFIG_GICV2
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_SYS_TEXT_BASE 0x8010E000
+#define CONFIG_SYS_TEXT_BASE 0x80110000
/*
* Memory layout for where various images get loaded by boot scripts:
#define CONFIG_SYS_NO_FLASH
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/omap.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARCH_CPU_INIT
"ramdisk_addr_r=0x88080000\0" \
"bootm_size=0x10000000\0"
+#define DEFAULT_MMC_TI_ARGS \
+ "mmcdev=0\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "finduuid=part uuid mmc 0:2 uuid\0" \
+ "args_mmc=run finduuid;setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=PARTUUID=${uuid} rw " \
+ "rootfstype=${mmcrootfstype}\0"
+
/*
* Default to a quick boot delay.
*/
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/* TWL4030 */
-#define CONFIG_TWL4030_POWER 1
+#define CONFIG_TWL4030_POWER
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x40200800
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
"console=ttyO2,115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
+ "run args_mmc; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
+ "run args_mmc; " \
"bootm ${loadaddr}\0" \
"findfdt="\
"if test $board_name = sdp4430; then " \
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
"dofastboot=0\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
"if run loadimage; then " \
"run loadfdt; " \
"echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
+ "run args_mmc; " \
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi;" \
"fi;\0" \
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
+++ /dev/null
-/*
- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_TK71_H__
-#define __CONFIG_TK71_H__
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nKa-Ro TK71"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-#define CONFIG_KW88F6281 1 /* SOC Name */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define MACH_TYPE_TK71 2399
-#define CONFIG_MACH_TYPE MACH_TYPE_TK71
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * NAND flash
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_DEV "nand0,3"
-#endif
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0}
-#define CONFIG_PHY_BASE_ADR 0x08
-#endif
-
-/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_KIRKWOOD
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * Environment variables configurations
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_ADDR 0x80000
-#define CONFIG_ENV_OFFSET 0x80000
-
-/*
- * Default environment variables
- */
-#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
-#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
- "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
- "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
- "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
- "mtdids=nand0=orion_nand\0" \
- "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
- "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
-#define MTDIDS_DEFAULT "nand0=orion_nand"
-#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS
-
-#define PHYS_SDRAM_1 0x00000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-
-#endif /* __CONFIG_TK71_H__ */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
- *
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the LUBBOCK board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
-
-#define CONFIG_MMC 1
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define RTC
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
-#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
-#define CONFIG_STUART 1 /* we use STUART on Conxs */
-#define CONFIG_CONS_INDEX 3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_DOS_PARTITION 1
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_USB
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_SERVERIP 192.168.1.99
-#define CONFIG_BOOTCOMMAND "run boot_flash"
-#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
- " rw root=/dev/ram initrd=0xa0800000,5m"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "program_boot_mmc=" \
- "mw.b 0xa0010000 0xff 0x20000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 u-boot.bin; " \
- "then " \
- "protect off 0x0 0x1ffff; " \
- "erase 0x0 0x1ffff; " \
- "cp.b 0xa0010000 0x0 0x20000; " \
- "fi\0" \
- "program_uzImage_mmc=" \
- "mw.b 0xa0010000 0xff 0x180000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 uzImage; " \
- "then " \
- "protect off 0x40000 0x1bffff; " \
- "erase 0x40000 0x1bffff; " \
- "cp.b 0xa0010000 0x40000 0x180000; " \
- "fi\0" \
- "program_ramdisk_mmc=" \
- "mw.b 0xa0010000 0xff 0x500000; " \
- "if mmcinit && " \
- "fatload mmc 0 0xa0010000 ramdisk.gz; " \
- "then " \
- "protect off 0x1c0000 0x6bffff; " \
- "erase 0x1c0000 0x6bffff; " \
- "cp.b 0xa0010000 0x1c0000 0x500000; " \
- "fi\0" \
- "boot_mmc=" \
- "if mmcinit && " \
- "fatload mmc 0 0xa0030000 uzImage && " \
- "fatload mmc 0 0xa0800000 ramdisk.gz; " \
- "then " \
- "bootm 0xa0030000; " \
- "fi\0" \
- "boot_flash=" \
- "cp.b 0x1c0000 0xa0800000 0x500000; " \
- "bootm 0x40000\0" \
-
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-/* #define CONFIG_INITRD_TAG 1 */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-
-#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
-
-#ifdef CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x00018000
-#define CONFIG_SYS_GPSR1_VAL 0x00000000
-#define CONFIG_SYS_GPSR2_VAL 0x400dc000
-#define CONFIG_SYS_GPSR3_VAL 0x00000000
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0x00018000
-#define CONFIG_SYS_GPDR1_VAL 0x00028801
-#define CONFIG_SYS_GPDR2_VAL 0x520dc000
-#define CONFIG_SYS_GPDR3_VAL 0x0001E000
-#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
-#define CONFIG_SYS_GAFR0_U_VAL 0x00000013
-#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
-#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
-#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
-#define CONFIG_SYS_GAFR3_L_VAL 0x54000003
-#define CONFIG_SYS_GAFR3_U_VAL 0x00002401
-#define CONFIG_SYS_GRER0_VAL 0x00000000
-#define CONFIG_SYS_GRER1_VAL 0x00000000
-#define CONFIG_SYS_GRER2_VAL 0x00000000
-#define CONFIG_SYS_GRER3_VAL 0x00000000
-
-#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER3_VAL 0x00000020
-
-#if CONFIG_POLARIS
-#define CONFIG_SYS_GFER0_VAL 0x00000001
-#define CONFIG_SYS_GFER2_VAL 0x00200000
-#else
-#define CONFIG_SYS_GFER0_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
-#endif
-
-#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
-#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
-
-/*
- * Memory settings
- */
-
-#define CONFIG_SYS_MSC0_VAL 0x4df84df0
-#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
-#if CONFIG_POLARIS
-#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
-#else
-#define CONFIG_SYS_MSC2_VAL 0xa26936d4
-#endif
-#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
-#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00004204
-#define CONFIG_SYS_MCMEM1_VAL 0x00010204
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00008407
-#define CONFIG_SYS_MCIO1_VAL 0x0000c108
-
-#define CONFIG_DRIVER_DM9000 1
-
-#if CONFIG_POLARIS
-#define CONFIG_DM9000_BASE 0x0C800000
-#else
-#define CONFIG_DM9000_BASE 0x08000000
-#endif
-
-#define DM9000_IO CONFIG_DM9000_BASE
-#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
-
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-
-/*
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* write flash less slowly */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-/* Unlock to be used with Intel chips */
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-/* Flash environment locations */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
- * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * Configuration settings for the HALE TT-01 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_MX31
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
-#define CONFIG_SYS_TEXT_BASE 0xA0000000
-
-
-/*
- * Physical Memory Map:
- * CS settings are defined by i.MX31:
- * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
- * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
- * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
- *
- * HALE set-up of the bluetechnix board for now is:
- * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
- * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
- * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
- * the flash chip is a mirrorbit S29WS256N !
- * - the PSRAM is hooked to CS5 (0xB6000000)
- * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
- * - 64Mbit = 8MByte (will go away in the production set-up)
- * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
- * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
- * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
- *
- * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
- * is not used right now. We should be able to reduce the SOM to NAND flash
- * only and boot from there.
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CSD0_BASE
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
-
-/* default load address, 1MB up the road */
-#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
-
-/* Size of malloc() pool, make sure possible frame buffer fits */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
-
-/* memtest works on all but the last 1MB (u-boot) and malloc area */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END \
- (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
-
-/* CFI FLASH driver setup */
-#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-/*
- * TODO: Bluetechnix (the supplier of the SOM) did define these values
- * in their original version of u-boot (1.2 or so). This should be
- * reviewed.
- *
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- * #define CONFIG_SYS_FLASH_PROTECTION
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
-
-/*
- * FLASH and environment organization, only the Spansion chip is supported:
- * - it has 254 * 128kB + 8 * 32kB blocks
- * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
- * and 2 sectors with 128k as environment =
- * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
- * - this could be less, but this is only for developer versions of the board
- * and no-one is going to use the NOR flash anyway.
- *
- * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
- * way to large, but it avoids ENV overwrite (when updating u-boot) in case
- * size breaks the next boundary (as it has with 128k).
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (128 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/* Hardware drivers */
-
-/*
- * on TT-01 UART1 pins are used by Audio, so we use UART2
- * TT-01 implements a hardware that turns off components depending on
- * the power level. In PL=1 the RS232 transceiver is usually off,
- * make sure that the transceiver is enabled during PL=1 for testing!
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART2_BASE
-
-#define CONFIG_MXC_SPI
-#define CONFIG_MXC_GPIO
-
-/* MC13783 connected to CSPI3 and SS0 */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-
-#define CONFIG_FSL_PMIC_BUS 2
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 1000000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-/* console is UART2 on TT-01 */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* ethernet setup for the onboard smc9118 */
-#define CONFIG_MII
-#define CONFIG_SMC911X
-/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
-#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
-#define CONFIG_SMC911X_16_BIT
-
-/* mmc driver */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
-#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
-
-/* video support */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MX3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-/* splash image won't work with NAND boot, use preboot script */
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
-#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
-
-/* allow stdin, stdout and stderr variables to redirect output */
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
-#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
-#define CONFIG_PREBOOT
-
-/* allow decompressing max. 4MB */
-#define CONFIG_VIDEO_BMP_GZIP
-/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
-
-/*
- * Command definition
- */
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NAND
-/*
- * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
- * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
- * a software locking scheme.
- */
-#define CONFIG_CMD_BMP
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * currently a default setting for booting via script is implemented
- * set user to login name and serverip to tftp host, define your
- * boot behaviour in bootscript.loginname
- *
- * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
- *
- * This set-up is for the L5F30947T04 by Epson, which is
- * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
- * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"videomode=epson\0" \
-"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
- "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
-"bootcmd=dhcp bootscript.${user}; source\0"
-
-#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
-#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT)+16)
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_CMDLINE_EDITING
-
-/* MMC boot support */
-#define CONFIG_CMD_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-#define CONFIG_NAND_MXC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*
- * actually this is nothing someone wants to configure!
- * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
- * is not used by the driver.
- */
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
-#define CONFIG_MXC_NAND_HWECC
-
-/* the current u-boot driver does not use the nand flash setup! */
-#define CONFIG_SYS_NAND_LARGEPAGE
-/*
- * it's not 16 bit:
- * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
- * the current u-boot mxc_nand.c tries to auto-detect, but this only
- * reads the boot settings during reset (which might be wrong)
- */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/*
- * KARO TX25 board - SoC Configuration
- */
-#define CONFIG_MX25
-#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */
-#define CONFIG_SYS_TIMER_RATE CONFIG_MX25_CLK32
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_MAX_SIZE 2048
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-#define CONFIG_SPL_TEXT_BASE 0x810c0000
-#define CONFIG_SYS_TEXT_BASE 0x81200000
-
-#ifndef MACH_TYPE_TX25
-#define MACH_TYPE_TX25 2177
-#endif
-
-#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-
-#ifdef CONFIG_SPL_BUILD
-/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#else
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-#define CONFIG_DISPLAY_CPUINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Memory Info
- */
-/* malloc() len */
-#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
-/*
- * Board has 2 32MB banks of DRAM but there is a bug when using
- * both so only the first is configured
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE 0x02000000
-#if (CONFIG_NR_DRAM_BANKS == 2)
-#define PHYS_SDRAM_2 0x90000000
-#define PHYS_SDRAM_2_SIZE 0x02000000
-#endif
-/* 8MB DRAM test */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
-
-/*
- * Serial Info
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-
-#define CONFIG_MXC_GPIO
-
-/*
- * Flash & Environment
- */
-/* No NOR flash present */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-
-/* NAND */
-#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (0xBB000000)
-#define CONFIG_JFFS2_NAND
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* U-Boot general configuration */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* Print buffer sz */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-
-/* U-Boot commands */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_CACHE
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-#define CONFIG_MII
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "u-boot=tx25/u-boot.bin\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "hostname=tx25\0" \
- "bootfile=tx25/uImage\0" \
- "rootpath=/opt/eldk/arm\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm\0" \
- "bootcmd=run net_nfs\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \
- "upd=run load update\0" \
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_U8500
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000
-#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-/*
- * Size of malloc() pool
- */
-#ifdef CONFIG_BOOT_SRAM
-#define CONFIG_ENV_SIZE (32*1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024)
-#else
-#define CONFIG_ENV_SIZE (128*1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#endif
-
-/*
- * PL011 Configuration
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_SERIAL_RLCR
-#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
-
-/*
- * U8500 UART registers base for 3 serial devices
- */
-#define CFG_UART0_BASE 0x80120000
-#define CFG_UART1_BASE 0x80121000
-#define CFG_UART2_BASE 0x80007000
-#define CFG_SERIAL0 CFG_UART0_BASE
-#define CFG_SERIAL1 CFG_UART1_BASE
-#define CFG_SERIAL2 CFG_UART2_BASE
-#define CONFIG_PL011_CLOCK 38400000
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
- (void *)CFG_SERIAL2 }
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Devices and file systems
- */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/*
- * Commands
- */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_I2C
-
-#ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY 1
-#endif
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "run emmcboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr=0x00100000\0" \
- "console=ttyAMA2,115200n8\0" \
- "memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \
- "pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \
- "memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \
- "pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \
- "pmem_hwb=54M@256M mem=202M@310M\0" \
- "commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \
- "init=init " \
- "board_id=${board_id} " \
- "logo.${logo} " \
- "startup_graphics=${startup_graphics}\0" \
- "emmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p2 " \
- "rootdelay=1\0" \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console}\0" \
- "emmcboot=echo Booting from eMMC ...; " \
- "run commonargs emmcargs addcons memargs;" \
- "mmc read 0 ${loadaddr} 0xA0000 0x4000;" \
- "bootm ${loadaddr}\0" \
- "flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \
- "source ${loadaddr}\0" \
- "loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \
- "usbtty=cdc_acm\0" \
- "stdout=serial,usbtty\0" \
- "stdin=serial,usbtty\0" \
- "stderr=serial,usbtty\0"
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-
-#define CONFIG_SETUP_MEMORY_TAGS 2
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-
-/*
- * I2C
- */
-#define CONFIG_U8500_I2C
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */
-#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000
-#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000
-#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000
-#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000
-#define CONFIG_SYS_U8500_I2C_BUS_MAX 4
-
-#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */
-#define CONFIG_TC35892_GPIO
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
-#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */
-
-/*
- * additions for new relocation code
- */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/* landing address before relocation */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0x0
-#endif
-
-/*
- * MMC related configs
- * NB Only externa SD slot is currently supported
- */
-#define MMC_BLOCK_SIZE 512
-#define CONFIG_ARM_PL180_MMCI
-#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */
-#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
-#define CONFIG_MMC_DEV_NUM 1
-
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET 0x13F80000
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * base register values for U8500
- */
-#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
- management unit */
-#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
-
-#endif /* __CONFIG_H */
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
-#if defined(CONFIG_MACH_PH1_SLD3)
-#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 1
-#define CONFIG_DDR_NUM_CH2 1
-
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x20000000
-#define CONFIG_SDRAM1_BASE 0xc0000000
-#define CONFIG_SDRAM1_SIZE 0x20000000
-#define CONFIG_SDRAM2_BASE 0xc0000000
-#define CONFIG_SDRAM2_SIZE 0x10000000
-#endif
-
-#if defined(CONFIG_MACH_PH1_LD4)
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-#endif
-
-#if defined(CONFIG_MACH_PH1_PRO4)
-#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 2
-
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x20000000
-#define CONFIG_SDRAM1_BASE 0xa0000000
-#define CONFIG_SDRAM1_SIZE 0x20000000
-#endif
-
-#if defined(CONFIG_MACH_PH1_SLD8)
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE 0x80000000
-#define CONFIG_SDRAM0_SIZE 0x10000000
-#define CONFIG_SDRAM1_BASE 0x90000000
-#define CONFIG_SDRAM1_SIZE 0x10000000
-#endif
-
#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-/*
- * Support card address map
- */
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
-# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
-# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
-# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# define CONFIG_SUPPORT_CARD_BASE 0x08000000
-# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
-# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
-# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
-#endif
-
#ifdef CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
+/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
+#define CONFIG_SMC911X_BASE 0
#define CONFIG_SMC911X_32_BIT
/*-----------------------------------------------------------------------
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
-#ifdef CONFIG_MACH_PH1_SLD3
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
#else
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
"tftpboot; bootm;"
-#define CONFIG_BOOTARGS " earlyprintk loglevel=8"
-
#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE "fitImage"
#define LINUXBOOT_ENV_SETTINGS \
"fit_addr=0x00100000\0" \
"fit_addr_r=0x84100000\0" \
"fit_size=0x00f00000\0" \
- "norboot=run add_default_bootargs &&" \
+ "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
"bootm $fit_addr\0" \
- "nandboot=run add_default_bootargs &&" \
- "nand read $fit_addr_r $fit_addr $fit_size &&" \
+ "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
"bootm $fit_addr_r\0" \
- "tftpboot=run add_default_bootargs &&" \
- "tftpboot $fit_addr_r $bootfile &&" \
+ "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
"bootm $fit_addr_r\0"
#else
#define CONFIG_BOOTFILE "uImage"
"ramdisk_addr_r=0x84a00000\0" \
"ramdisk_size=0x00600000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \
- "norboot=run add_default_bootargs &&" \
+ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
+ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
+ "setexpr fdt_addr $nor_base + $fdt_addr &&" \
"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
- "nandboot=run add_default_bootargs &&" \
- "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
+ "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
- "tftpboot=run add_default_bootargs &&" \
- "tftpboot $kernel_addr_r $bootfile &&" \
+ "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"verify=n\0" \
+ "norbase=0x42000000\0" \
"nandupdate=nand erase 0 0x00100000 &&" \
"tftpboot u-boot-spl-dtb.bin &&" \
"nand write $loadaddr 0 0x00010000 &&" \
"tftpboot u-boot-dtb.img &&" \
"nand write $loadaddr 0x00010000 0x000f0000\0" \
- "add_default_bootargs=setenv bootargs $bootargs" \
- " console=ttyS0,$baudrate\0" \
LINUXBOOT_ENV_SETTINGS
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
-/* Memory Size & Mapping */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
-
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
-/* Thre is no memory hole */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
-#else
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
-#endif
-#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
- defined(CONFIG_MACH_PH1_SLD8)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
-#endif
-#if defined(CONFIG_MACH_PH1_PRO4)
+#else
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
/* Fuse */
#define CONFIG_CMD_FUSE
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- * Configuration for Versatile PB.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */
-#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
-
-#define CONFIG_SYS_MEMTEST_START 0x100000
-#define CONFIG_SYS_MEMTEST_END 0x10000000
-
-#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
-#define CONFIG_SYS_TIMER_RATE (1000000 / 256)
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
-/*
- * control registers
- */
-#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
-
-/*
- * System controller bit assignment
- */
-#define VERSATILE_REFCLK 0
-#define VERSATILE_TIMCLK 1
-
-#define VERSATILE_TIMER1_EnSel 15
-#define VERSATILE_TIMER2_EnSel 17
-#define VERSATILE_TIMER3_EnSel 19
-#define VERSATILE_TIMER4_EnSel 21
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE 8192
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_SMC91111
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE 0x10010000
-#undef CONFIG_SMC91111_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS \
- {(void *)CONFIG_SYS_SERIAL0, \
- (void *)CONFIG_SYS_SERIAL1 }
-#define CONFIG_CONS_INDEX 0
-
-#define CONFIG_BAUDRATE 38400
-#define CONFIG_SYS_SERIAL0 0x101F1000
-#define CONFIG_SYS_SERIAL1 0x101F2000
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
- "netdev=25,0,0xf1010000,0xf1010010,eth0 "\
- "console=ttyAMA0,38400n1"
-
-/*
- * Static configuration when assigning fixed address
- */
-#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Monitor Command Prompt */
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_ARCH_VERSATILE_AB
-# define CONFIG_SYS_PROMPT "VersatileAB # "
-#else
-# define CONFIG_SYS_PROMPT "VersatilePB # "
-#endif
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#ifdef CONFIG_ARCH_VERSATILE_QEMU
-#define CONFIG_SYS_TEXT_BASE 0x10000
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x01000000
-/*
- * Use the CFI flash driver for ease of use
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_ENV_IS_IN_FLASH 1
-/*
- * System control register
- */
-#define VERSATILE_SYS_BASE 0x10000000
-#define VERSATILE_SYS_FLASH_OFFSET 0x4C
-#define VERSATILE_FLASHCTRL \
- (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
-/* Enable writing to flash */
-#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/*
- * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
- * i.e.
- * the bottom "sector" (bottom boot), or top "sector"
- * (top boot), is a seperate erase region divided into
- * 4 (equal) smaller sectors. This, notionally, allows
- * quicker erase/rewrire of the most frequently changed
- * area......
- * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
- */
-
-#ifdef CONFIG_ARCH_VERSATILE_AB
-#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
-#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
-#define CONFIG_SYS_MAX_FLASH_SECT (520)
-#endif
-
-#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
-#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
-#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
-#define CONFIG_SYS_MAX_FLASH_SECT (260)
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0x34000000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
-
-/* The ARM Boot Monitor is shipped in the lowest sector of flash */
-
-#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
-#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
/* Link Definitions */
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
+ defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE 0x88000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#error "Unknown board variant"
#endif
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
#define GICR_BASE (0x2f100000)
#else
-#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
+ defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
#define GICD_BASE (0x2f000000)
#define GICC_BASE (0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
* be copied into DRAM
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "kernel_name=Image\0" \
+ "kernel_name=norkern\0" \
+ "kernel_alt_name=Image\0" \
"kernel_addr=0x80000000\0" \
- "fdt_name=juno\0" \
+ "initrd_name=ramdisk.img\0" \
+ "initrd_addr=0x84000000\0" \
+ "fdt_name=board.dtb\0" \
+ "fdt_alt_name=juno\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
/* Assume we boot with root on the first partition of a USB stick */
#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \
- "root=/dev/sda1 rw " \
+ "root=/dev/sda2 rw " \
"rootwait "\
- "earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\
+ "earlyprintk=pl011,0x7ff80000 debug "\
+ "user_debug=31 "\
+ "androidboot.hardware=juno "\
"loglevel=9"
/* Copy the kernel and FDT to DRAM memory and boot */
#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
+ "if test $? -eq 1; then "\
+ " echo Loading ${kernel_alt_name} instead of "\
+ "${kernel_name}; "\
+ " afs load ${kernel_alt_name} ${kernel_addr};"\
+ "fi ; "\
"afs load ${fdt_name} ${fdt_addr} ; " \
+ "if test $? -eq 1; then "\
+ " echo Loading ${fdt_alt_name} instead of "\
+ "${fdt_name}; "\
+ " afs load ${fdt_alt_name} ${fdt_addr}; "\
+ "fi ; "\
"fdt addr ${fdt_addr}; fdt resize; " \
- "booti ${kernel_addr} - ${fdt_addr}"
+ "if afs load ${initrd_name} ${initrd_addr} ; "\
+ "then "\
+ " setenv initrd_param ${initrd_addr}; "\
+ " else setenv initrd_param -; "\
+ "fi ; " \
+ "booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
"smhload ${fdt_name} ${fdt_addr}; " \
- "smhload ${initrd_name} ${initrd_addr} initrd_end; " \
+ "smhload ${initrd_name} ${initrd_addr} "\
+ "initrd_end; " \
"fdt addr ${fdt_addr}; fdt resize; " \
"fdt chosen ${initrd_addr} ${initrd_end}; " \
"booti $kernel_addr - $fdt_addr"
#define CONFIG_BOOTDELAY 1
+#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr=0x80080000\0" \
+ "initrd_addr=0x84000000\0" \
+ "fdt_addr=0x83000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0"
+
+#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
+ "0x1c090000 debug user_debug=31 "\
+ "androidboot.hardware=fvpbase "\
+ "root=/dev/vda2 rw "\
+ "rootwait "\
+ "loglevel=9"
+
+#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr"
+
+#define CONFIG_BOOTDELAY 1
+
#else
#error "Unknown board variant"
#endif
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_BOOTDELAY 3
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX51-3Stack Freescale board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-
-#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_SYS_TEXT_BASE 0x97800000
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOARD_LATE_INIT
-
-#ifndef MACH_TYPE_TTC_VISION2
-#define MACH_TYPE_TTC_VISION2 2775
-#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART3_BASE
-#define CONFIG_MXC_GPIO
-#define CONFIG_MXC_SPI
-#define CONFIG_HW_WATCHDOG
-
- /*
- * SPI Configs
- * */
-#define CONFIG_FSL_SF
-#define CONFIG_CMD_SF
-
-#define CONFIG_SPI_FLASH_STMICRO
-
-/*
- * Use gpio 4 pin 25 as chip select for SPI flash
- * This corresponds to gpio 121
- */
-#define CONFIG_SF_DEFAULT_CS 1
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 25000000
-
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_MAX_HZ 25000000
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
-
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
-#define CONFIG_ENV_SIZE (4 * 1024)
-
-#define CONFIG_FSL_ENV_IN_SF
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 0
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 2500000
-#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-
-/*
- * MMC Configs
- */
-#define CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-#define CONFIG_MMC
-
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-#define CONFIG_CMD_DATE
-
-/*
- * Eth Configs
- */
-#define CONFIG_HAS_ETH1
-#define CONFIG_MII
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-
-#define CONFIG_CMD_SPI
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "loadaddr=0x90800000\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x10000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* 166 MHz DDR RAM */
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
-#define CONFIG_SYS_MAIN_PWR_ON
-
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * Framebuffer and LCD
- */
-#define CONFIG_PREBOOT
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#define CONFIG_BMP_16BPP
-#define CONFIG_IPUV3_CLK 133000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009-2012
- * Jens Scharsig <esw@bus-elekronik.de>
- * BuS Elektronik GmbH & Co. KG
- *
- * Configuation settings for the VL_MA2SC board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*--------------------------------------------------------------------------*/
-
-#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
-#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_MISC_INIT_R
-
-#include <asm/hardware.h>
-
-#define MACH_TYPE_VL_MA2SC 2412
-#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
-
-#define CONFIG_SYS_DCACHE_OFF
-
-#ifdef CONFIG_RAMLOAD
-#define CONFIG_SYS_TEXT_BASE 0x21000000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#endif
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-
-#define CONFIG_IDENT_STRING " on MiS Activ 2"
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AT91_GPIO
-
-#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
-#define CONFIG_SYS_USE_NORFLASH
-#define CONFIG_SYS_USE_BOOT_NORFLASH
-#endif
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_WATCHDOG
-
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_ATMEL_LCD
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_BLACK_ON_WHITE
-#define LCD_BPP LCD_COLOR8
-#define CONFIG_ATMEL_LCD_BGR555
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY 3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1SUM
-/*
-#define CONFIG_CMD_SPI
-*/
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_USB
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_MD5
-#define CONFIG_SHA1
-
-/*----------------------------------------------------------------------------
- * Hardware confuguration
- *---------------------------------------------------------------------------*/
-
-/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_STORAGE
-#define CONFIG_AT91C_PQFP_UHPBUG
-
-/* I2C-Bus */
-
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
-
-#ifndef CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
-
-/* Software I2C driver configuration */
-#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
-
-#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
-#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
-
-#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
-#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
-#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
-#define I2C_SDA(bit) \
- do { \
- if (bit) \
- writel(AT91_PIN_SDA, &pio->piob.sodr); \
- else \
- writel(AT91_PIN_SDA, &pio->piob.codr); \
- } while (0);
-#define I2C_SCL(bit) \
- do { \
- if (bit) \
- writel(AT91_PIN_SCL, &pio->piob.sodr); \
- else \
- writel(AT91_PIN_SCL, &pio->piob.codr); \
- } while (0);
-#endif
-
-/* I2C-RTC */
-
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#endif
-
-/* EEPROM */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
-/* define PDC[31:16] as DATA[31:16] */
-#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
-#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
-
-/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
- (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
- AT91_MATRIX_CSA_EBI_CS1A)
-
-/* user reset enable */
-#define CONFIG_SYS_RSTC_RMR_VAL \
- (AT91_RSTC_KEY | \
- AT91_RSTC_MR_URSTEN | \
- AT91_RSTC_MR_ERSTL(15))
-
-/* Disable Watchdog */
-#define CONFIG_SYS_WDTC_WDMR_VAL \
- (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
- AT91_WDT_MR_WDV(0xFFF) | \
- AT91_WDT_MR_WDDIS | \
- AT91_WDT_MR_WDD(0xFFF))
-
-/* clocks */
-
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
-
-#define MHZ180
-#if defined(MHZ199)
-/* 199,8994 MHZ */
-#define MASTER_PLL_MUL 911
-#define MASTER_PLL_DIV 56
-#define MASTER_PLL_OUT 2
-#elif defined(MHZ180)
-/* 180 MHZ */
-#define MASTER_PLL_MUL 1875
-#define MASTER_PLL_DIV 128
-#define MASTER_PLL_OUT 2
-#elif defined(MHZTEST)
-/* Test MHZ */
-#define CONFIG_DISPLAY_CPUINFO
-#define MASTER_PLL_MUL 8
-#define MASTER_PLL_DIV 1
-#define MASTER_PLL_OUT 2
-#else
-/* 176.9472 MHZ */
-#define MASTER_PLL_MUL 72
-#define MASTER_PLL_DIV 5
-#define MASTER_PLL_OUT 2
-#endif
-
-#define CONFIG_SYS_MOR_VAL \
- (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
-
-#define CONFIG_SYS_PLLAR_VAL \
- (AT91_PMC_PLLAR_29 | \
- AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
- AT91_PMC_PLLXR_PLLCOUNT(63) | \
- AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
- AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR1_VAL \
- (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
- AT91_PMC_MCKR_MDIV_2)
-
-/* PCK/2 = MCK Master Clock from PLLA */
-#define CONFIG_SYS_MCKR2_VAL \
- (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
- AT91_PMC_MCKR_MDIV_2)
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
-
-#define CONFIG_SYS_SDRC_MR_VAL1 0
-#define CONFIG_SYS_SDRC_TR_VAL1 700
-#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_13 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_3 | \
- AT91_SDRAMC_DBW_32 | \
- (2 << 8) | /* Write Recovery Delay */ \
- (7 << 12) | /* Row Cycle Delay */ \
- (2 << 16) | /* Row Precharge Delay */ \
- (2 << 20) | /* Row to Column Delay */ \
- (5 << 24) | /* Active to Precharge Delay */ \
- (8 << 28)) /* Exit Self Refresh to Active Delay */
-
-#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
-#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
-#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
-#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
-#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
-#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
-#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
-#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
-
-/* NOR flash */
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define PHYS_FLASH_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
-
-/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL \
- (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
- AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL \
- (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
- AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
-#define CONFIG_SYS_SMC0_CYCLE0_VAL \
- (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
-#define CONFIG_SYS_SMC0_MODE0_VAL \
- (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
- AT91_SMC_MODE_DBW_16 | \
- AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
-#endif
-
-/* Ethernet */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 5
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END 0x21e00000
-
-/* Address and size of Primary Environment Sector */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x20000
-#else
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
- 38400, 57600, 9600 }
-
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN \
- ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-
-#ifndef CONFIG_RAMLOAD
-#define CONFIG_BOOTCOMMAND "run nfsboot"
-#endif
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_BOOT_RETRY_MIN 15
-
-#define CONFIG_NFSBOOTCOMMAND \
- "dhcp $(copy_addr) $(kernelname);" \
- "run bootargsdefaults;" \
- "set bootargs $(bootargs) boot=nfs " \
- ";echo $(bootargs)" \
- ";bootm"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ubootaddr=10000000\0" \
- "splashimage=10080000\0" \
- "kerneladdr=100A0000\0" \
- "kernelsize=00800000\0" \
- "minifsaddr=108A0000\0" \
- "minifssize=00060000\0" \
- "rootfsaddr=10900000\0" \
- "copy_addr=20200000\0" \
- "rootfssize=01700000\0" \
- "kernelname=uImage_vl_ma2sc\0" \
- "bootargsdefaults=set bootargs " \
- "console=ttyS0,115200 " \
- "video=atmel_lcdfb " \
- "mem=62M " \
- "panic=10 " \
- "boardrevison=\\\"${revision}\\\" " \
- "uboot=\\\"${ver}\\\" " \
- "\0" \
- "update_all=run update_kernel;run update_root;" \
- "run update_splash; run update_uboot\0" \
- "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
- "dhcp $(copy_addr) $(kernelname);" \
- "erase $(kerneladdr) +$(kernelsize);" \
- "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
- "protect on $(kerneladdr) +$(kernelsize)" \
- "\0" \
- "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
- "dhcp $(copy_addr) vl_ma2sc.root;" \
- "erase $(rootfsaddr) +$(rootfssize);" \
- "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
- "\0" \
- "update_splash=protect off $(splashimage) +20000;" \
- "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
- "erase $(splashimage) +20000;" \
- "cp.b $(fileaddr) 10080000 $(filesize);" \
- "protect on $(splashimage) +20000\0" \
- "update_uboot=protect off 10000000 1005FFFF;" \
- "dhcp $(copy_addr) u-boot_vl_ma2sc;" \
- "erase 10000000 1005FFFF;" \
- "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
- "protect on 10000000 1005FFFF;reset\0" \
- "emergency=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(kerneladdr)\0" \
- "netemergency=run bootargsdefaults;" \
- "dhcp $(copy_addr) $(kernelname);" \
- "set bootargs $(bootargs) root=initramfs boot=emergency " \
- ";bootm $(copy_addr)\0" \
- "norboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=local quiet " \
- ";bootm $(kerneladdr)\0" \
- "nandboot=run bootargsdefaults;" \
- "set bootargs $(bootargs) root=initramfs boot=nand " \
- ";bootm $(kerneladdr)\0" \
- "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
- "clearenv=protect off 10060000 1007FFFF;" \
- "erase 10060000 1007FFFF;reset\0" \
- " "
-
-#endif
+++ /dev/null
-/*
- * Voipac PXA270 configuration file
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
-#define CONFIG_SYS_TEXT_BASE 0xa0000000
-
-#ifdef CONFIG_ONENAND
-#define CONFIG_SPL_ONENAND_SUPPORT
-#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x2000
-#define CONFIG_SPL_ONENAND_LOAD_SIZE \
- (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
-#define CONFIG_SPL_TEXT_BASE 0x5c000000
-#define CONFIG_SPL_LDSCRIPT "board/vpac270/u-boot-spl.lds"
-#endif
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_BOOTCOMMAND \
- "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "if ide reset && fatload ide 0 0xa4000000 uImage; then " \
- "bootm 0xa4000000; " \
- "fi; " \
- "bootm 0x60000;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "update_onenand=" \
- "onenand erase 0x0 0x80000 ; " \
- "onenand write 0xa0000000 0x0 0x80000"
-
-#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_LZMA /* LZMA compression support */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Serial Console Configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_USB
-#undef CONFIG_LCD
-#define CONFIG_CMD_IDE
-
-#ifdef CONFIG_ONENAND
-#define CONFIG_CMD_ONENAND
-#else
-#undef CONFIG_CMD_ONENAND
-#endif
-
-/*
- * Networking Configuration
- * chip on the Voipac PXA270 board
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
-#define DM9000_IO (CONFIG_DM9000_BASE)
-#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
-#define CONFIG_NET_RETRY_COUNT 10
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#endif
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP
-#ifdef CONFIG_SYS_HUSH_PARSER
-#else
-#endif
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
-
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-
-#ifdef CONFIG_RAM_256M
-#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#endif
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#ifdef CONFIG_RAM_256M
-#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
-#else
-#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
-
-/*
- * NOR FLASH
- */
-#define CONFIG_SYS_MONITOR_BASE 0x0
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_ENV_SECT_SIZE 0x20000
-
-#if defined(CONFIG_CMD_FLASH) /* NOR */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#ifdef CONFIG_RAM_256M
-#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
-#endif
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-
-#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#ifdef CONFIG_RAM_256M
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
-#else
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#endif
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-#define CONFIG_SYS_FLASH_PROTECTION 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ONENAND_BASE 0x00000000
-
-#define CONFIG_ENV_IS_IN_ONENAND 1
-
-#else /* No flash */
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-/*
- * IDE
- */
-#ifdef CONFIG_CMD_IDE
-#define CONFIG_LBA48
-#undef CONFIG_IDE_LED
-#undef CONFIG_IDE_RESET
-
-#define __io
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
-#define CONFIG_SYS_ATA_REG_OFFSET 0x120
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
-
-#define CONFIG_SYS_ATA_STRIDE 2
-#endif
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPSR0_VAL 0x01308800
-#define CONFIG_SYS_GPSR1_VAL 0x00cf0000
-#define CONFIG_SYS_GPSR2_VAL 0x922ac000
-#define CONFIG_SYS_GPSR3_VAL 0x0161e800
-
-#define CONFIG_SYS_GPCR0_VAL 0x00010000
-#define CONFIG_SYS_GPCR1_VAL 0x0
-#define CONFIG_SYS_GPCR2_VAL 0x0
-#define CONFIG_SYS_GPCR3_VAL 0x0
-
-#define CONFIG_SYS_GPDR0_VAL 0xcbb18800
-#define CONFIG_SYS_GPDR1_VAL 0xfccfa981
-#define CONFIG_SYS_GPDR2_VAL 0x922affff
-#define CONFIG_SYS_GPDR3_VAL 0x0161e904
-
-#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
-#define CONFIG_SYS_GAFR0_U_VAL 0xa5da8510
-#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a0aa
-#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x4109a401
-#define CONFIG_SYS_GAFR3_L_VAL 0x54010310
-#define CONFIG_SYS_GAFR3_U_VAL 0x00025401
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x00500240
-#define CONFIG_SYS_CCCR 0x02000290
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9
-#define CONFIG_SYS_MSC1_VAL 0x02ccf974
-#define CONFIG_SYS_MSC2_VAL 0x00000000
-#ifdef CONFIG_RAM_256M
-#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
-#else
-#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
-#endif
-#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-/*
- * LCD
- */
-#ifdef CONFIG_LCD
-#define CONFIG_VOIPAC_LCD
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "vpac270"
-#define CONFIG_USB_STORAGE
-#endif
-
-#endif /* __CONFIG_H */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
+++ /dev/null
-/*
- * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on the netspace_v2 code which is
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_WIRELESS_SPACE_H
-#define _CONFIG_WIRELESS_SPACE_H
-
-/*
- * Machine number definition
- */
-#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */
-#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE
-#define CONFIG_IDENT_STRING " Wireless Space"
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
-/* SoC name */
-#define CONFIG_KW88F6281
-#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-
-/*
- * Commands configuration
- */
-#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_USB
-
-/*
- * Core clock definition
- */
-#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
-
-/*
- * SDRAM configuration
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-/*
- * Different SDRAM configuration and size for some of the boards derived
- * from the Network Space v2
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/* Remove or override few declarations from mv-common.h */
-#undef CONFIG_RBTREE
-#undef CONFIG_SYS_IDE_MAXBUS
-#undef CONFIG_SYS_IDE_MAXDEVICE
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */
-#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
-#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */
-#define CONFIG_MII
-#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_NETCONSOLE
-#define CONFIG_MV88E61XX_SWITCH
-#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-#define CONFIG_MV88E61XX_CMD
-#define CONFIG_CMD_TFTPPUT
-#endif /* CONFIG_CMD_NET */
-
-/*
- * SATA Driver configuration
- */
-#ifdef CONFIG_MVSATA_IDE
-#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /* CONFIG_MVSATA_IDE */
-
-/*
- * Enable GPI0 support
- */
-#define CONFIG_KIRKWOOD_GPIO
-
-/*
- * Enable I2C support
- */
-#ifdef CONFIG_CMD_I2C
-/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
-#endif /* CONFIG_CMD_I2C */
-
-/*
- * Partition support
- */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/*
- * File systems support
- */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
-/*
- * Use the HUSH parser
- */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Console configuration
- */
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/*
- * Enable device tree support
- */
-#define CONFIG_OF_LIBFDT
-
-/*
- * Environment variables configurations
- */
-
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
-#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
-#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
-
-/*
- * Board-specific command to make using buttons etc easier
- */
-
-#define CONFIG_WIRELESS_SPACE_CMD
-
-/*
- * Default environment variables
- */
-#define CONFIG_PREBOOT
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
-
-#define CONFIG_BOOTCOMMAND \
- "if run usbload || run diskload; then bootm; fi"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
- "bootfile=uImage\0" \
- "loadaddr=0x800000\0" \
- "autoload=no\0" \
- "netconsole=" \
- "set stdin $stdin,nc; " \
- "set stdout $stdout,nc; " \
- "set stderr $stderr,nc;\0" \
- "diskload=ide reset && " \
- "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
- "usbload=usb start && " \
- "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \
- "preboot=" \
- "dhcp && run netconsole\0"
-
-#endif /* _CONFIG_WIRELESS_SPACE_H */
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_MXC_SPI
#define CONFIG_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_THUMB_BUILD
#include <asm/arch/hardware.h>
#define CONFIG_MTD_ECC_SOFT
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
/* UBI/UBI config options */
#define CONFIG_MTD_DEVICE
+++ /dev/null
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2004
- * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Configuation settings for the xaeniax board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */
-#define CONFIG_XAENIAX 1 /* on a xaeniax board */
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_BOARD_LATE_INIT
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */
-#define CONFIG_CONS_INDEX 4
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_DTT
-
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.68.201
-#define CONFIG_SERVERIP 192.168.68.62
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTCOMMAND "bootm 0x00100000"
-#define CONFIG_BOOTARGS "console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Size of malloc() pool; this lives below the uppermost 128 KiB which are
- * used for the RAM copy of the uboot code
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#undef CONFIG_SYS_PROMPT
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-
-#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
-#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
-#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* FIXME */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */
-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-
-/*
- * SMSC91C111 Network Card
- */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */
-#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
-#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
-#undef CONFIG_SHOW_ACTIVITY
-#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
-
-/*
- * GPIO settings
- */
-
-/*
- * GP05 == nUSBReset is 1
- * GP10 == CFReset is 1
- * GP13 == nCFDataEnable is 1
- * GP14 == nCFAddrEnable is 1
- * GP15 == nCS1 is 1
- * GP21 == ComBrdReset is 1
- * GP24 == SFRM is 1
- * GP25 == TXD is 1
- * GP31 == SYNC is 1
- * GP33 == nCS5 is 1
- * GP39 == FFTXD is 1
- * GP41 == RTS is 1
- * GP43 == BTTXD is 1
- * GP45 == BTRTS is 1
- * GP47 == TXD is 1
- * GP48 == nPOE is 1
- * GP49 == nPWE is 1
- * GP50 == nPIOR is 1
- * GP51 == nPIOW is 1
- * GP52 == nPCE[1] is 1
- * GP53 == nPCE[2] is 1
- * GP54 == nPSKTSEL is 1
- * GP55 == nPREG is 1
- * GP78 == nCS2 is 1
- * GP79 == nCS3 is 1
- * GP80 == nCS4 is 1
- * GP82 == NSSPSFRM is 1
- * GP83 == NSSPTXD is 1
- */
-#define CONFIG_SYS_GPSR0_VAL 0x8320E420
-#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82
-#define CONFIG_SYS_GPSR2_VAL 0x000DC000
-
-/*
- * GP03 == LANReset is 0
- * GP06 == USBWakeUp is 0
- * GP11 == USBControl is 0
- * GP12 == Buzzer is 0
- * GP16 == PWM0 is 0
- * GP17 == PWM1 is 0
- * GP23 == SCLK is 0
- * GP30 == SDATA_OUT is 0
- * GP81 == NSSPCLK is 0
- */
-#define CONFIG_SYS_GPCR0_VAL 0x40C31848
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00020000
-
-/*
- * GP00 == CPUWakeUpUSB is input
- * GP01 == GP reset is input
- * GP02 == LANInterrupt is input
- * GP03 == LANReset is output
- * GP04 == USBInterrupt is input
- * GP05 == nUSBReset is output
- * GP06 == USBWakeUp is output
- * GP07 == CFReady/nBusy is input
- * GP08 == nCFCardDetect1 is input
- * GP09 == nCFCardDetect2 is input
- * GP10 == nCFReset is output
- * GP11 == USBControl is output
- * GP12 == Buzzer is output
- * GP13 == CFDataEnable is output
- * GP14 == CFAddressEnable is output
- * GP15 == nCS1 is output
- * GP16 == PWM0 is output
- * GP17 == PWM1 is output
- * GP18 == RDY is input
- * GP19 == ReaderReady is input
- * GP20 == ReaderReset is input
- * GP21 == ComBrdReset is output
- * GP23 == SCLK is output
- * GP24 == SFRM is output
- * GP25 == TXD is output
- * GP26 == RXD is input
- * GP27 == EXTCLK is input
- * GP28 == BITCLK is output
- * GP29 == SDATA_IN0 is input
- * GP30 == SDATA_OUT is output
- * GP31 == SYNC is output
- * GP32 == SYSSCLK is output
- * GP33 == nCS5 is output
- * GP34 == FFRXD is input
- * GP35 == CTS is input
- * GP36 == DCD is input
- * GP37 == DSR is input
- * GP38 == RI is input
- * GP39 == FFTXD is output
- * GP40 == DTR is output
- * GP41 == RTS is output
- * GP42 == BTRXD is input
- * GP43 == BTTXD is output
- * GP44 == BTCTS is input
- * GP45 == BTRTS is output
- * GP46 == RXD is input
- * GP47 == TXD is output
- * GP48 == nPOE is output
- * GP49 == nPWE is output
- * GP50 == nPIOR is output
- * GP51 == nPIOW is output
- * GP52 == nPCE[1] is output
- * GP53 == nPCE[2] is output
- * GP54 == nPSKTSEL is output
- * GP55 == nPREG is output
- * GP56 == nPWAIT is input
- * GP57 == nPIOS16 is input
- * GP58 == LDD[0] is output
- * GP59 == LDD[1] is output
- * GP60 == LDD[2] is output
- * GP61 == LDD[3] is output
- * GP62 == LDD[4] is output
- * GP63 == LDD[5] is output
- * GP64 == LDD[6] is output
- * GP65 == LDD[7] is output
- * GP66 == LDD[8] is output
- * GP67 == LDD[9] is output
- * GP68 == LDD[10] is output
- * GP69 == LDD[11] is output
- * GP70 == LDD[12] is output
- * GP71 == LDD[13] is output
- * GP72 == LDD[14] is output
- * GP73 == LDD[15] is output
- * GP74 == LCD_FCLK is output
- * GP75 == LCD_LCLK is output
- * GP76 == LCD_PCLK is output
- * GP77 == LCD_ACBIAS is output
- * GP78 == nCS2 is output
- * GP79 == nCS3 is output
- * GP80 == nCS4 is output
- * GP81 == NSSPCLK is output
- * GP82 == NSSPSFRM is output
- * GP83 == NSSPTXD is output
- * GP84 == NSSPRXD is input
- */
-#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68
-#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83
-#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF
-
-/*
- * GP01 == GP reset is AF01
- * GP15 == nCS1 is AF10
- * GP16 == PWM0 is AF10
- * GP17 == PWM1 is AF10
- * GP18 == RDY is AF01
- * GP23 == SCLK is AF10
- * GP24 == SFRM is AF10
- * GP25 == TXD is AF10
- * GP26 == RXD is AF01
- * GP27 == EXTCLK is AF01
- * GP28 == BITCLK is AF01
- * GP29 == SDATA_IN0 is AF10
- * GP30 == SDATA_OUT is AF01
- * GP31 == SYNC is AF01
- * GP32 == SYSCLK is AF01
- * GP33 == nCS5 is AF10
- * GP34 == FFRXD is AF01
- * GP35 == CTS is AF01
- * GP36 == DCD is AF01
- * GP37 == DSR is AF01
- * GP38 == RI is AF01
- * GP39 == FFTXD is AF10
- * GP40 == DTR is AF10
- * GP41 == RTS is AF10
- * GP42 == BTRXD is AF01
- * GP43 == BTTXD is AF10
- * GP44 == BTCTS is AF01
- * GP45 == BTRTS is AF10
- * GP46 == RXD is AF10
- * GP47 == TXD is AF01
- * GP48 == nPOE is AF10
- * GP49 == nPWE is AF10
- * GP50 == nPIOR is AF10
- * GP51 == nPIOW is AF10
- * GP52 == nPCE[1] is AF10
- * GP53 == nPCE[2] is AF10
- * GP54 == nPSKTSEL is AF10
- * GP55 == nPREG is AF10
- * GP56 == nPWAIT is AF01
- * GP57 == nPIOS16 is AF01
- * GP58 == LDD[0] is AF10
- * GP59 == LDD[1] is AF10
- * GP60 == LDD[2] is AF10
- * GP61 == LDD[3] is AF10
- * GP62 == LDD[4] is AF10
- * GP63 == LDD[5] is AF10
- * GP64 == LDD[6] is AF10
- * GP65 == LDD[7] is AF10
- * GP66 == LDD[8] is AF10
- * GP67 == LDD[9] is AF10
- * GP68 == LDD[10] is AF10
- * GP69 == LDD[11] is AF10
- * GP70 == LDD[12] is AF10
- * GP71 == LDD[13] is AF10
- * GP72 == LDD[14] is AF10
- * GP73 == LDD[15] is AF10
- * GP74 == LCD_FCLK is AF10
- * GP75 == LCD_LCLK is AF10
- * GP76 == LCD_PCLK is AF10
- * GP77 == LCD_ACBIAS is AF10
- * GP78 == nCS2 is AF10
- * GP79 == nCS3 is AF10
- * GP80 == nCS4 is AF10
- * GP81 == NSSPCLK is AF01
- * GP82 == NSSPSFRM is AF01
- * GP83 == NSSPTXD is AF01
- * GP84 == NSSPRXD is AF10
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
-#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A
-#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559
-#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
-#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000256
-
-/*
- * clock settings
- */
-/* RDH = 1
- * PH = 0
- * VFS = 0
- * BFS = 0
- * SSS = 0
- */
-#define CONFIG_SYS_PSSR_VAL 0x00000030
-
-#define CONFIG_SYS_CKEN 0x00000080 /* */
-#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
-#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
-
-
-/*
- * Memory settings
- *
- * This is the configuration for nCS0/1 -> flash banks
- * configuration for nCS1 :
- * [31] 0 -
- * [30:28] 000 -
- * [27:24] 0000 -
- * [23:20] 0000 -
- * [19] 0 -
- * [18:16] 000 -
- * configuration for nCS0:
- * [15] 0 - Slower Device
- * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
- * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
- * [03] 0 - 32 Bit bus width
- * [02:00] 010 - burst OF 4 ROM or FLASH
-*/
-#define CONFIG_SYS_MSC0_VAL 0x000023D2
-
-/* This is the configuration for nCS2/3 -> USB controller, LAN
- * configuration for nCS3: LAN
- * [31] 0 - Slower Device
- * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
- * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
- * [19] 0 - 32 Bit bus width
- * [18:16] 100 - variable latency I/O
- * configuration for nCS2: USB
- * [15] 1 - Faster Device
- * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03] 1 - 16 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC1_VAL 0x1224A26C
-
-/* This is the configuration for nCS4/5 -> LAN
- * configuration for nCS5:
- * [31] 0 -
- * [30:28] 000 -
- * [27:24] 0000 -
- * [23:20] 0000 -
- * [19] 0 -
- * [18:16] 000 -
- * configuration for nCS4: LAN
- * [15] 1 - Faster Device
- * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
- * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
- * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
- * [03] 0 - 32 Bit bus width
- * [02:00] 100 - variable latency I/O
- */
-#define CONFIG_SYS_MSC2_VAL 0x00001224
-
-/* MDCNFG: SDRAM Configuration Register
- *
- * [31:29] 000 - reserved
- * [28] 0 - no SA1111 compatiblity mode
- * [27] 0 - latch return data with return clock
- * [26] 0 - alternate addressing for pair 2/3
- * [25:24] 00 - timings
- * [23] 0 - internal banks in lower partition 2/3 (not used)
- * [22:21] 00 - row address bits for partition 2/3 (not used)
- * [20:19] 00 - column address bits for partition 2/3 (not used)
- * [18] 0 - SDRAM partition 2/3 width is 32 bit
- * [17] 0 - SDRAM partition 3 disabled
- * [16] 0 - SDRAM partition 2 disabled
- * [15:13] 000 - reserved
- * [12] 0 - no SA1111 compatiblity mode
- * [11] 1 - latch return data with return clock
- * [10] 0 - no alternate addressing for pair 0/1
- * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
- * [7] 1 - 4 internal banks in lower partition pair
- * [06:05] 10 - 13 row address bits for partition 0/1
- * [04:03] 01 - 9 column address bits for partition 0/1
- * [02] 0 - SDRAM partition 0/1 width is 32 bit
- * [01] 0 - disable SDRAM partition 1
- * [00] 1 - enable SDRAM partition 0
- */
-/* use the configuration above but disable partition 0 */
-#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9
-
-/* MDREFR: SDRAM Refresh Control Register
- *
- * [32:26] 0 - reserved
- * [25] 0 - K2FREE: not free running
- * [24] 0 - K1FREE: not free running
- * [23] 0 - K0FREE: not free running
- * [22] 0 - SLFRSH: self refresh disabled
- * [21] 0 - reserved
- * [20] 1 - APD: auto power down
- * [19] 0 - K2DB2: SDCLK2 is MemClk
- * [18] 0 - K2RUN: disable SDCLK2
- * [17] 0 - K1DB2: SDCLK1 is MemClk
- * [16] 1 - K1RUN: enable SDCLK1
- * [15] 1 - E1PIN: SDRAM clock enable
- * [14] 0 - K0DB2: SDCLK0 is MemClk
- * [13] 0 - K0RUN: disable SDCLK0
- * [12] 0 - E0PIN: disable SDCKE0
- * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
- */
-#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */
-
-/* MDMRS: Mode Register Set Configuration Register
- *
- * [31] 0 - reserved
- * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
- * [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used)
- * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
- * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
- * [15] 0 - reserved
- * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
- * [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency.
- * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
- * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
- */
-#define CONFIG_SYS_MDMRS_VAL 0x00320032
-
-#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
-#define CONFIG_SYS_SXCNFG_VAL 0x00000000
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000000
-#define CONFIG_SYS_MCMEM0_VAL 0x00010504
-#define CONFIG_SYS_MCMEM1_VAL 0x00010504
-#define CONFIG_SYS_MCATT0_VAL 0x00010504
-#define CONFIG_SYS_MCATT1_VAL 0x00010504
-#define CONFIG_SYS_MCIO0_VAL 0x00004715
-#define CONFIG_SYS_MCIO1_VAL 0x00004715
-
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
#define CONFIG_SYS_NAND_ACTL_DELAY 25
-#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_JFFS2_NAND
/*
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
#define CONFIG_NAND_FSL_ELBC
/*
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
#define CONFIG_NAND_FSL_ELBC
/*
+++ /dev/null
-/*
- * Aeronix Zipit Z2 configuration file
- *
- * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Board Configuration Options
- */
-#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
-#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#undef CONFIG_BOARD_LATE_INIT
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_PREBOOT
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x40000
-#define CONFIG_ENV_SIZE 0x20000
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define CONFIG_SYS_MALLOC_LEN (128*1024)
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_BOOTCOMMAND \
- "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
- "then " \
- "source 0xa0000000; " \
- "else " \
- "bootm 0x60000; " \
- "fi; "
-#define CONFIG_BOOTARGS \
- "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
-#define CONFIG_TIMESTAMP
-#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_LZMA /* LZMA compression support */
-
-/*
- * Serial Console Configuration
- * STUART - the lower serial port on Colibri board
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_STUART 1
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Bootloader Components Configuration
- */
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_SPI
-
-/*
- * MMC Card Configuration
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_PXA_MMC_GENERIC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*
- * SPI and LCD
- */
-#ifdef CONFIG_CMD_SPI
-#define CONFIG_SOFT_SPI
-#define CONFIG_LCD
-#define CONFIG_PXA_LCD
-#define CONFIG_LMS283GF05
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CMD_BMP
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-
-#define SPI_DELAY udelay(10)
-#define SPI_SDA(val) zipitz2_spi_sda(val)
-#define SPI_SCL(val) zipitz2_spi_scl(val)
-#define SPI_READ zipitz2_spi_read()
-#ifndef __ASSEMBLY__
-void zipitz2_spi_sda(int);
-void zipitz2_spi_scl(int);
-unsigned char zipitz2_spi_read(void);
-#endif
-#endif
-
-/*
- * KGDB
- */
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * HUSH Shell Configuration
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-/*
- * Clock Configuration
- */
-#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
-
-/*
- * SRAM Map
- */
-#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
-#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
-
-/*
- * DRAM Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
-
-/*
- * NOR FLASH
- */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
-#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
-#define CONFIG_SYS_FLASH_PROTECTION
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
-#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
-#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
-#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
-#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
-#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
-#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
-#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000020
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-#define CONFIG_SYS_GPCR3_VAL 0x00000000
-#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
-#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
-#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
-#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
-#define CONFIG_SYS_GPSR0_VAL 0x06080400
-#define CONFIG_SYS_GPSR1_VAL 0x007f0000
-#define CONFIG_SYS_GPSR2_VAL 0x032a0000
-#define CONFIG_SYS_GPSR3_VAL 0x00000180
-
-#define CONFIG_SYS_PSSR_VAL 0x30
-
-/*
- * Clock settings
- */
-#define CONFIG_SYS_CKEN 0x00511220
-#define CONFIG_SYS_CCCR 0x00000190
-
-/*
- * Memory settings
- */
-#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
-#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
-#define CONFIG_SYS_MSC2_VAL 0x0000b884
-#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
-#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
-#define CONFIG_SYS_MDMRS_VAL 0x00000000
-#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
-#define CONFIG_SYS_SXCNFG_VAL 0x40044004
-
-/*
- * PCMCIA and CF Interfaces
- */
-#define CONFIG_SYS_MECR_VAL 0x00000001
-#define CONFIG_SYS_MCMEM0_VAL 0x00014307
-#define CONFIG_SYS_MCMEM1_VAL 0x00014307
-#define CONFIG_SYS_MCATT0_VAL 0x0001c787
-#define CONFIG_SYS_MCATT1_VAL 0x0001c787
-#define CONFIG_SYS_MCIO0_VAL 0x0001430f
-#define CONFIG_SYS_MCIO1_VAL 0x0001430f
-
-#endif /* __CONFIG_H */
*/
int device_set_name(struct udevice *dev, const char *name);
+/**
+ * device_is_on_pci_bus - Test if a device is on a PCI bus
+ *
+ * @dev: device to test
+ * @return: true if it is on a PCI bus, false otherwise
+ */
+static inline bool device_is_on_pci_bus(struct udevice *dev)
+{
+ return device_get_uclass_id(dev->parent) == UCLASS_PCI;
+}
+
/* device resource management */
typedef void (*dr_release_t)(struct udevice *dev, void *res);
typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data);
*/
enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags);
+#ifdef CONFIG_CMD_NET
+/*
+ * Check if a string has the format of an Ethernet MAC address
+ */
+int eth_validate_ethaddr_str(const char *addr);
+#endif
+
#ifdef USE_HOSTCC
/*
* Look up the type of a variable directly from the .flags var.
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Ethernet Switch commands
+ */
+
+#ifndef _CMD_ETHSW_H_
+#define _CMD_ETHSW_H_
+
+#define ETHSW_MAX_CMD_PARAMS 20
+#define ETHSW_CMD_PORT_ALL -1
+#define ETHSW_CMD_VLAN_ALL -1
+
+/* IDs used to track keywords in a command */
+enum ethsw_keyword_id {
+ ethsw_id_key_end = -1,
+ ethsw_id_help,
+ ethsw_id_show,
+ ethsw_id_port,
+ ethsw_id_enable,
+ ethsw_id_disable,
+ ethsw_id_statistics,
+ ethsw_id_clear,
+ ethsw_id_learning,
+ ethsw_id_auto,
+ ethsw_id_vlan,
+ ethsw_id_fdb,
+ ethsw_id_add,
+ ethsw_id_del,
+ ethsw_id_flush,
+ ethsw_id_pvid,
+ ethsw_id_untagged,
+ ethsw_id_all,
+ ethsw_id_none,
+ ethsw_id_egress,
+ ethsw_id_tag,
+ ethsw_id_classified,
+ ethsw_id_shared,
+ ethsw_id_private,
+ ethsw_id_ingress,
+ ethsw_id_filtering,
+ ethsw_id_count, /* keep last */
+};
+
+enum ethsw_keyword_opt_id {
+ ethsw_id_port_no = ethsw_id_count + 1,
+ ethsw_id_vlan_no,
+ ethsw_id_pvid_no,
+ ethsw_id_add_del_no,
+ ethsw_id_add_del_mac,
+ ethsw_id_count_all, /* keep last */
+};
+
+struct ethsw_command_def {
+ int cmd_to_keywords[ETHSW_MAX_CMD_PARAMS];
+ int cmd_keywords_nr;
+ int port;
+ int vid;
+ uchar ethaddr[6];
+ int (*cmd_function)(struct ethsw_command_def *parsed_cmd);
+};
+
+/* Structure to be created and initialized by an Ethernet Switch driver */
+struct ethsw_command_func {
+ const char *ethsw_name;
+ int (*port_enable)(struct ethsw_command_def *parsed_cmd);
+ int (*port_disable)(struct ethsw_command_def *parsed_cmd);
+ int (*port_show)(struct ethsw_command_def *parsed_cmd);
+ int (*port_stats)(struct ethsw_command_def *parsed_cmd);
+ int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd);
+ int (*port_learn)(struct ethsw_command_def *parsed_cmd);
+ int (*port_learn_show)(struct ethsw_command_def *parsed_cmd);
+ int (*fdb_show)(struct ethsw_command_def *parsed_cmd);
+ int (*fdb_flush)(struct ethsw_command_def *parsed_cmd);
+ int (*fdb_entry_add)(struct ethsw_command_def *parsed_cmd);
+ int (*fdb_entry_del)(struct ethsw_command_def *parsed_cmd);
+ int (*pvid_show)(struct ethsw_command_def *parsed_cmd);
+ int (*pvid_set)(struct ethsw_command_def *parsed_cmd);
+ int (*vlan_show)(struct ethsw_command_def *parsed_cmd);
+ int (*vlan_set)(struct ethsw_command_def *parsed_cmd);
+ int (*port_untag_show)(struct ethsw_command_def *parsed_cmd);
+ int (*port_untag_set)(struct ethsw_command_def *parsed_cmd);
+ int (*port_egr_vlan_show)(struct ethsw_command_def *parsed_cmd);
+ int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd);
+ int (*vlan_learn_show)(struct ethsw_command_def *parsed_cmd);
+ int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd);
+ int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd);
+ int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd);
+};
+
+int ethsw_define_functions(const struct ethsw_command_func *cmd_func);
+
+#endif /* _CMD_ETHSW_H_ */
int fdtdec_next_compatible_subnode(const void *blob, int node,
enum fdt_compat_id id, int *depthp);
-/**
- * Look up an address property in a node and return it as an address.
- * The property must hold either one address with no trailing data or
- * one address with a length. This is only tested on 32-bit machines.
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant assumes a known and fixed number of cells are used to
+ * represent the address and size.
+ *
+ * You probably don't want to use this function directly except to parse
+ * non-standard properties, and never to parse the "reg" property. Instead,
+ * use one of the "auto" variants below, which automatically honor the
+ * #address-cells and #size-cells properties in the parent node.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param index which address to retrieve from a list of addresses. Often 0.
+ * @param na the number of cells used to represent an address
+ * @param ns the number of cells used to represent a size
+ * @param sizep a pointer to store the size into. Use NULL if not required
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
+ const char *prop_name, int index, int na, int ns,
+ fdt_size_t *sizep);
+
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant automatically determines the number of cells used to represent
+ * the address and size by parsing the provided parent node's #address-cells
+ * and #size-cells properties.
+ *
+ * @param blob FDT blob
+ * @param parent parent node of @node
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param index which address to retrieve from a list of addresses. Often 0.
+ * @param sizep a pointer to store the size into. Use NULL if not required
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
+ int node, const char *prop_name, int index, fdt_size_t *sizep);
+
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant automatically determines the number of cells used to represent
+ * the address and size by parsing the parent node's #address-cells
+ * and #size-cells properties. The parent node is automatically found.
+ *
+ * The automatic parent lookup implemented by this function is slow.
+ * Consequently, fdtdec_get_addr_size_auto_parent() should be used where
+ * possible.
+ *
+ * @param blob FDT blob
+ * @param parent parent node of @node
+ * @param node node to examine
+ * @param prop_name name of property to find
+ * @param index which address to retrieve from a list of addresses. Often 0.
+ * @param sizep a pointer to store the size into. Use NULL if not required
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
+ const char *prop_name, int index, fdt_size_t *sizep);
+
+/*
+ * Look up an address property in a node and return the parsed address.
+ *
+ * This variant hard-codes the number of cells used to represent the address
+ * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also
+ * always returns the first address value in the property (index 0).
+ *
+ * Use of this function is not recommended due to the hard-coding of cell
+ * counts. There is no programmatic validation that these hard-coded values
+ * actually match the device tree content in any way at all. This assumption
+ * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately
+ * set in the U-Boot build and exercising strict control over DT content to
+ * ensure use of matching #address-cells/#size-cells properties. However, this
+ * approach is error-prone; those familiar with DT will not expect the
+ * assumption to exist, and could easily invalidate it. If the assumption is
+ * invalidated, this function will not report the issue, and debugging will
+ * be required. Instead, use fdtdec_get_addr_size_auto_parent().
*
* @param blob FDT blob
* @param node node to examine
fdt_addr_t fdtdec_get_addr(const void *blob, int node,
const char *prop_name);
-/**
- * Look up an address property in a node and return it as an address.
- * The property must hold one address with a length. This is only tested
- * on 32-bit machines.
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant hard-codes the number of cells used to represent the address
+ * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also
+ * always returns the first address value in the property (index 0).
+ *
+ * Use of this function is not recommended due to the hard-coding of cell
+ * counts. There is no programmatic validation that these hard-coded values
+ * actually match the device tree content in any way at all. This assumption
+ * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately
+ * set in the U-Boot build and exercising strict control over DT content to
+ * ensure use of matching #address-cells/#size-cells properties. However, this
+ * approach is error-prone; those familiar with DT will not expect the
+ * assumption to exist, and could easily invalidate it. If the assumption is
+ * invalidated, this function will not report the issue, and debugging will
+ * be required. Instead, use fdtdec_get_addr_size_auto_parent().
*
* @param blob FDT blob
* @param node node to examine
* @param prop_name name of property to find
+ * @param sizep a pointer to store the size into. Use NULL if not required
* @return address, if found, or FDT_ADDR_T_NONE if not
*/
fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
#define MC_CCSR_BASE_ADDR \
((struct mc_ccsr_registers __iomem *)0x8340000)
-#define BIT(x) (1 << (x))
#define GCR1_P1_STOP BIT(31)
#define GCR1_P2_STOP BIT(30)
#define GCR1_P1_DE_RST BIT(23)
--- /dev/null
+/*
+ * (C) Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+struct watchdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+};
+
+#define WCR_WDZST 0x01
+#define WCR_WDBG 0x02
+#define WCR_WDE 0x04
+#define WCR_WDT 0x08
+#define WCR_SRS 0x10
+#define SET_WCR_WT(x) (x << 8)
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
#define IH_COMP_LZMA 3 /* lzma Compression Used */
#define IH_COMP_LZO 4 /* lzo Compression Used */
+#define IH_COMP_LZ4 5 /* lz4 Compression Used */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
#include <asm/types.h>
+#define BIT(nr) (1UL << (nr))
+
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ALIGNMEM_H
+#define __ALIGNMEM_H
+
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#include <malloc.h>
+
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ * architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ * elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ * uint32_t buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ * ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ * type, and NOT an array of the specified type. This can be very important
+ * if you want the address of the buffer, which you probably do, to pass it
+ * to the DMA hardware. The value of &buffer is different in the two cases.
+ * In the macro case it will be the address of the pointer, not the address
+ * of the space reserved for the buffer. However, in the second case it
+ * would be the address of the buffer. So if you are replacing hard coded
+ * stack buffers with this macro you need to make sure you remove the & from
+ * the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer. It can not be used to create a cache
+ * line aligned global buffer.
+ */
+#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1)
+#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad)
+#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \
+ char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \
+ + (align - 1)]; \
+ \
+ type *name = (type *)ALIGN((uintptr_t)__##name, align)
+#define ALLOC_ALIGN_BUFFER(type, name, size, align) \
+ ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1)
+#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \
+ ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \
+ ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/*
+ * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's
+ * purpose is to allow allocating aligned buffers outside of function scope.
+ * Usage of this macro shall be avoided or used with extreme care!
+ */
+#define DEFINE_ALIGN_BUFFER(type, name, size, align) \
+ static char __##name[ALIGN(size * sizeof(type), align)] \
+ __aligned(align); \
+ \
+ static type *name = (type *)__##name
+#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \
+ DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/**
+ * malloc_cache_aligned() - allocate a memory region aligned to cache line size
+ *
+ * This allocates memory at a cache-line boundary. The amount allocated may
+ * be larger than requested as it is rounded up to the nearest multiple of the
+ * cache-line size. This ensured that subsequent cache operations on this
+ * memory (flush, invalidate) will not affect subsequently allocated regions.
+ *
+ * @size: Minimum number of bytes to allocate
+ *
+ * @return pointer to new memory region, or NULL if there is no more memory
+ * available.
+ */
+static inline void *malloc_cache_aligned(size_t size)
+{
+ return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN));
+}
+#endif
+
+#endif /* __ALIGNMEM_H */
*/
struct udevice *eth_get_dev_by_name(const char *devname);
unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
+
/* Used only when NetConsole is enabled */
+int eth_is_active(struct udevice *dev); /* Test device for active state */
int eth_init_state_only(void); /* Set active state */
void eth_halt_state_only(void); /* Set passive state */
#endif
return NULL;
}
+/* Used only when NetConsole is enabled */
+int eth_is_active(struct eth_device *dev); /* Test device for active state */
/* Set active state */
static inline __attribute__((always_inline)) int eth_init_state_only(void)
{
+++ /dev/null
-/* Collection of constants used to access Nomadik registers */
-
-#ifndef __NOMADIK_H__
-#define __NOMADIK_H__
-
-/* Base addresses of our peripherals */
-#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
-#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */
-#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */
-#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */
-#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */
-#define NOMADIK_1NAND_BASE 0x30000000
-#define NOMADIK_GPIO0_BASE 0x101E4000
-#define NOMADIK_GPIO1_BASE 0x101E5000
-#define NOMADIK_GPIO2_BASE 0x101E6000
-#define NOMADIK_GPIO3_BASE 0x101E7000
-#define NOMADIK_CPLD_BASE 0x36000000
-#define NOMADIK_UART0_BASE 0x101FD000
-#define NOMADIK_UART1_BASE 0x101FB000
-#define NOMADIK_UART2_BASE 0x101F2000
-
-#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */
-#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */
-
-#define NOMADIK_RTC_BASE 0x101E8000
-#define NOMADIK_ETH0_BASE 0x36800300
-#define NOMADIK_CPLD_UART_BASE 0x36480000
-
-/* Chip select registers ("Flexible Static Memory Controller") */
-
-#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00)
-#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04)
-#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08)
-#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c)
-#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40)
-#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48)
-#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c)
-#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54)
-
-#endif /* __NOMADIK_H__ */
/*
- * vsc9953.h
+ * Copyright 2013, 2015 Freescale Semiconductor, Inc.
*
- * Driver for the Vitesse VSC9953 L2 Switch
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * SPDX-License-Identifier: GPL-2.0+
*
+ * Driver for the Vitesse VSC9953 L2 Switch
*/
#ifndef _VSC9953_H_
#include <config.h>
#include <miiphy.h>
#include <asm/types.h>
-#include <malloc.h>
#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
#define VSC9953_SYS_OFFSET 0x010000
+#define VSC9953_REW_OFFSET 0x030000
#define VSC9953_DEV_GMII_OFFSET 0x100000
#define VSC9953_QSYS_OFFSET 0x200000
#define VSC9953_ANA_OFFSET 0x280000
#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
#define VSC9953_PHY_REGS_OFFST 0x0000AC
-#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001
-#define CONFIG_VSC9953_CORE_ENABLE 0x80
-#define CONFIG_VSC9953_MEM_ENABLE 0x40
-#define CONFIG_VSC9953_MEM_INIT 0x20
-
-#define CONFIG_VSC9953_PORT_ENA 0x00003a00
-#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011
-#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011
-#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515
-#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043
-#define CONFIG_VSC9953_CLOCK_CFG 0x00000001
-#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001
-#define CONFIG_VSC9953_PFC_FC 0x00000001
-#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000
-#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000
-#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000
-#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe
-#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
-#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000
-#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee
-
-#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff
-#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004
+/* Macros for vsc9953_chip_regs.soft_rst register */
+#define VSC9953_SOFT_SWC_RST_ENA 0x00000001
+
+/* Macros for vsc9953_sys_sys.reset_cfg register */
+#define VSC9953_CORE_ENABLE 0x80
+#define VSC9953_MEM_ENABLE 0x40
+#define VSC9953_MEM_INIT 0x20
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
+#define VSC9953_MAC_ENA_CFG 0x00000011
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
+#define VSC9953_MAC_MODE_CFG 0x00000011
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
+#define VSC9953_MAC_IFG_CFG 0x00000515
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
+#define VSC9953_MAC_HDX_CFG 0x00001043
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
+#define VSC9953_MAC_MAX_LEN 0x000005ee
+
+/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
+#define VSC9953_CLOCK_CFG 0x00000001
+#define VSC9953_CLOCK_CFG_1000M 0x00000001
+
+/* Macros for vsc9953_sys_sys.front_port_mode register */
+#define VSC9953_FRONT_PORT_MODE 0x00000000
+
+/* Macros for vsc9953_ana_pfc.pfc_cfg register */
+#define VSC9953_PFC_FC 0x00000001
+#define VSC9953_PFC_FC_QSGMII 0x00000000
+
+/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
+#define VSC9953_MAC_FC_CFG 0x04700000
+#define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
+
+/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
+#define VSC9953_PAUSE_CFG 0x001ffffe
+
+/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
+#define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
+
+/* Macros for vsc9953_sys_sys.stat_cfg register */
+#define VSC9953_STAT_CLEAR_RX 0x00000400
+#define VSC9953_STAT_CLEAR_TX 0x00000800
+#define VSC9953_STAT_CLEAR_DR 0x00001000
+
+/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
+#define VSC9953_VCAP_MV_CFG 0x0000ffff
+#define VSC9953_VCAP_UPDATE_CTRL 0x01000004
+
+/* Macros for register vsc9953_ana_ana_tables.mac_access register */
+#define VSC9953_MAC_CMD_IDLE 0x00000000
+#define VSC9953_MAC_CMD_LEARN 0x00000001
+#define VSC9953_MAC_CMD_FORGET 0x00000002
+#define VSC9953_MAC_CMD_AGE 0x00000003
+#define VSC9953_MAC_CMD_NEXT 0x00000004
+#define VSC9953_MAC_CMD_READ 0x00000006
+#define VSC9953_MAC_CMD_WRITE 0x00000007
+#define VSC9953_MAC_CMD_MASK 0x00000007
+#define VSC9953_MAC_CMD_VALID 0x00000800
+#define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
+#define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
+#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
+#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
+#define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
+#define VSC9953_MAC_DESTIDX_MASK 0x000001f8
+#define VSC9953_MAC_VID_MASK 0x1fff0000
+#define VSC9953_MAC_MACH_MASK 0x0000ffff
+
+/* Macros for vsc9953_ana_port.vlan_cfg register */
+#define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
+#define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
+#define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
+#define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
+#define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
+
+/* Macros for vsc9953_rew_port.port_vlan_cfg register */
+#define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
+
+/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
+#define VSC9953_ANA_TBL_VID_MASK 0x00000fff
+
+/* Macros for vsc9953_ana_ana_tables.vlan_access register */
+#define VSC9953_VLAN_PORT_MASK 0x00001ffc
+#define VSC9953_VLAN_CMD_MASK 0x00000003
+#define VSC9953_VLAN_CMD_IDLE 0x00000000
+#define VSC9953_VLAN_CMD_READ 0x00000001
+#define VSC9953_VLAN_CMD_WRITE 0x00000002
+#define VSC9953_VLAN_CMD_INIT 0x00000003
+
+/* Macros for vsc9953_ana_port.port_cfg register */
+#define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
+#define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
+#define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
+#define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
+
+/* Macros for vsc9953_qsys_sys.switch_port_mode register */
+#define VSC9953_PORT_ENA 0x00002000
+
+/* Macros for vsc9953_ana_ana.agen_ctrl register */
+#define VSC9953_FID_MASK_ALL 0x00fff000
+
+/* Macros for vsc9953_ana_ana.adv_learn register */
+#define VSC9953_VLAN_CHK 0x00000400
+
+/* Macros for vsc9953_rew_port.port_tag_cfg register */
+#define VSC9953_TAG_CFG_MASK 0x00000180
+#define VSC9953_TAG_CFG_NONE 0x00000000
+#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
+#define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
+#define VSC9953_TAG_CFG_ALL 0x00000180
+#define VSC9953_TAG_VID_PVID 0x00000010
+
+/* Macros for vsc9953_ana_ana.anag_efil register */
+#define VSC9953_AGE_PORT_EN 0x00080000
+#define VSC9953_AGE_PORT_MASK 0x0007c000
+#define VSC9953_AGE_VID_EN 0x00002000
+#define VSC9953_AGE_VID_MASK 0x00001fff
+
+/* Macros for vsc9953_ana_ana_tables.mach_data register */
+#define VSC9953_MACHDATA_VID_MASK 0x1fff0000
+
#define VSC9953_MAX_PORTS 10
#define VSC9953_PORT_CHECK(port) \
(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
) ? 0 : 1 \
)
+#define VSC9953_MAX_VLAN 4096
+#define VSC9953_VLAN_CHECK(vid) \
+ (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
char *name;
};
-/* VSC9953 ANA structure for T1040 U-boot*/
+/* VSC9953 ANA structure */
-struct vsc9953_ana_port {
+struct vsc9953_ana_port {
u32 vlan_cfg;
u32 drop_cfg;
u32 qos_cfg;
struct vsc9953_ana_ana {
u32 adv_learn;
u32 vlan_mask;
+ u32 reserved;
u32 anag_efil;
u32 an_events;
u32 storm_limit_burst;
u32 port_grp_id[91];
};
-struct vsc9953_ana_pfc {
+struct vsc9953_ana_pfc {
u32 pfc_cfg;
u32 reserved1[15];
};
u32 pol_hyst;
};
-struct vsc9953_ana_common {
+struct vsc9953_ana_common {
u32 aggr_cfg;
u32 cpuq_cfg;
u32 cpuq_8021_cfg;
u32 reserved5[196];
struct vsc9953_ana_common common;
};
-/* END VSC9953 ANA structure for T1040 U-boot*/
+/* END VSC9953 ANA structure t*/
-/* VSC9953 DEV_GMII structure for T1040 U-boot*/
+/* VSC9953 DEV_GMII structure */
-struct vsc9953_dev_gmii_port_mode {
+struct vsc9953_dev_gmii_port_mode {
u32 clock_cfg;
u32 port_misc;
u32 reserved1;
u32 eee_cfg;
};
-struct vsc9953_dev_gmii_mac_cfg_status {
+struct vsc9953_dev_gmii_mac_cfg_status {
u32 mac_ena_cfg;
u32 mac_mode_cfg;
u32 mac_maxlen_cfg;
struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
};
-/* END VSC9953 DEV_GMII structure for T1040 U-boot*/
+/* END VSC9953 DEV_GMII structure */
-/* VSC9953 QSYS structure for T1040 U-boot*/
+/* VSC9953 QSYS structure */
-struct vsc9953_qsys_hsch {
+struct vsc9953_qsys_hsch {
u32 cir_cfg;
u32 reserved1;
u32 se_cfg;
u32 reserved2[20];
};
-struct vsc9953_qsys_sys {
+struct vsc9953_qsys_sys {
u32 port_mode[12];
u32 switch_port_mode[11];
u32 stat_cnt_cfg;
u32 reserved1[23];
};
-struct vsc9953_qsys_qos_cfg {
+struct vsc9953_qsys_qos_cfg {
u32 red_profile[16];
u32 res_qos_mode;
};
-struct vsc9953_qsys_drop_cfg {
+struct vsc9953_qsys_drop_cfg {
u32 egr_drop_mode;
};
-struct vsc9953_qsys_mmgt {
+struct vsc9953_qsys_mmgt {
u32 eq_cntrl;
u32 reserved1;
};
-struct vsc9953_qsys_hsch_misc {
+struct vsc9953_qsys_hsch_misc {
u32 hsch_misc_cfg;
u32 reserved1[546];
};
-struct vsc9953_qsys_res_ctrl {
+struct vsc9953_qsys_res_ctrl {
u32 res_cfg;
u32 res_stat;
};
-struct vsc9953_qsys_reg {
+struct vsc9953_qsys_reg {
struct vsc9953_qsys_hsch hsch[108];
struct vsc9953_qsys_sys sys;
struct vsc9953_qsys_qos_cfg qos_cfg;
struct vsc9953_qsys_res_ctrl res_ctrl[1024];
};
-/* END VSC9953 QSYS structure for T1040 U-boot*/
-
-/* VSC9953 SYS structure for T1040 U-boot*/
-
-struct vsc9953_sys_stat {
- u32 rx_cntrs[64];
- u32 tx_cntrs[64];
- u32 drop_cntrs[64];
+/* END VSC9953 QSYS structure */
+
+/* VSC9953 SYS structure */
+
+struct vsc9953_rx_cntrs {
+ u32 c_rx_oct;
+ u32 c_rx_uc;
+ u32 c_rx_mc;
+ u32 c_rx_bc;
+ u32 c_rx_short;
+ u32 c_rx_frag;
+ u32 c_rx_jabber;
+ u32 c_rx_crc;
+ u32 c_rx_symbol_err;
+ u32 c_rx_sz_64;
+ u32 c_rx_sz_65_127;
+ u32 c_rx_sz_128_255;
+ u32 c_rx_sz_256_511;
+ u32 c_rx_sz_512_1023;
+ u32 c_rx_sz_1024_1526;
+ u32 c_rx_sz_jumbo;
+ u32 c_rx_pause;
+ u32 c_rx_control;
+ u32 c_rx_long;
+ u32 c_rx_cat_drop;
+ u32 c_rx_red_prio_0;
+ u32 c_rx_red_prio_1;
+ u32 c_rx_red_prio_2;
+ u32 c_rx_red_prio_3;
+ u32 c_rx_red_prio_4;
+ u32 c_rx_red_prio_5;
+ u32 c_rx_red_prio_6;
+ u32 c_rx_red_prio_7;
+ u32 c_rx_yellow_prio_0;
+ u32 c_rx_yellow_prio_1;
+ u32 c_rx_yellow_prio_2;
+ u32 c_rx_yellow_prio_3;
+ u32 c_rx_yellow_prio_4;
+ u32 c_rx_yellow_prio_5;
+ u32 c_rx_yellow_prio_6;
+ u32 c_rx_yellow_prio_7;
+ u32 c_rx_green_prio_0;
+ u32 c_rx_green_prio_1;
+ u32 c_rx_green_prio_2;
+ u32 c_rx_green_prio_3;
+ u32 c_rx_green_prio_4;
+ u32 c_rx_green_prio_5;
+ u32 c_rx_green_prio_6;
+ u32 c_rx_green_prio_7;
+ u32 reserved[20];
+};
+
+struct vsc9953_tx_cntrs {
+ u32 c_tx_oct;
+ u32 c_tx_uc;
+ u32 c_tx_mc;
+ u32 c_tx_bc;
+ u32 c_tx_col;
+ u32 c_tx_drop;
+ u32 c_tx_pause;
+ u32 c_tx_sz_64;
+ u32 c_tx_sz_65_127;
+ u32 c_tx_sz_128_255;
+ u32 c_tx_sz_256_511;
+ u32 c_tx_sz_512_1023;
+ u32 c_tx_sz_1024_1526;
+ u32 c_tx_sz_jumbo;
+ u32 c_tx_yellow_prio_0;
+ u32 c_tx_yellow_prio_1;
+ u32 c_tx_yellow_prio_2;
+ u32 c_tx_yellow_prio_3;
+ u32 c_tx_yellow_prio_4;
+ u32 c_tx_yellow_prio_5;
+ u32 c_tx_yellow_prio_6;
+ u32 c_tx_yellow_prio_7;
+ u32 c_tx_green_prio_0;
+ u32 c_tx_green_prio_1;
+ u32 c_tx_green_prio_2;
+ u32 c_tx_green_prio_3;
+ u32 c_tx_green_prio_4;
+ u32 c_tx_green_prio_5;
+ u32 c_tx_green_prio_6;
+ u32 c_tx_green_prio_7;
+ u32 c_tx_aged;
+ u32 reserved[33];
+};
+
+struct vsc9953_drop_cntrs {
+ u32 c_dr_local;
+ u32 c_dr_tail;
+ u32 c_dr_yellow_prio_0;
+ u32 c_dr_yellow_prio_1;
+ u32 c_dr_yellow_prio_2;
+ u32 c_dr_yellow_prio_3;
+ u32 c_dr_yellow_prio_4;
+ u32 c_dr_yellow_prio_5;
+ u32 c_dr_yellow_prio_6;
+ u32 c_dr_yellow_prio_7;
+ u32 c_dr_green_prio_0;
+ u32 c_dr_green_prio_1;
+ u32 c_dr_green_prio_2;
+ u32 c_dr_green_prio_3;
+ u32 c_dr_green_prio_4;
+ u32 c_dr_green_prio_5;
+ u32 c_dr_green_prio_6;
+ u32 c_dr_green_prio_7;
+ u32 reserved[46];
+};
+
+struct vsc9953_sys_stat {
+ struct vsc9953_rx_cntrs rx_cntrs;
+ struct vsc9953_tx_cntrs tx_cntrs;
+ struct vsc9953_drop_cntrs drop_cntrs;
u32 reserved1[6];
};
-struct vsc9953_sys_sys {
+struct vsc9953_sys_sys {
u32 reset_cfg;
u32 reserved1;
u32 vlan_etype_cfg;
u32 reserved2[50];
};
-struct vsc9953_sys_pause_cfg {
+struct vsc9953_sys_pause_cfg {
u32 pause_cfg[11];
u32 pause_tot_cfg;
u32 tail_drop_level[11];
u32 mac_fc_cfg[10];
};
-struct vsc9953_sys_mmgt {
+struct vsc9953_sys_mmgt {
u16 free_cnt;
};
-struct vsc9953_system_reg {
+struct vsc9953_system_reg {
struct vsc9953_sys_stat stat;
struct vsc9953_sys_sys sys;
struct vsc9953_sys_pause_cfg pause_cfg;
struct vsc9953_sys_mmgt mmgt;
};
-/* END VSC9953 SYS structure for T1040 U-boot*/
+/* END VSC9953 SYS structure */
+
+/* VSC9953 REW structure */
+
+struct vsc9953_rew_port {
+ u32 port_vlan_cfg;
+ u32 port_tag_cfg;
+ u32 port_port_cfg;
+ u32 port_dscp_cfg;
+ u32 port_pcp_dei_qos_map_cfg[16];
+ u32 reserved[12];
+};
+
+struct vsc9953_rew_common {
+ u32 reserve[4];
+ u32 dscp_remap_dp1_cfg[64];
+ u32 dscp_remap_cfg[64];
+};
+
+struct vsc9953_rew_reg {
+ struct vsc9953_rew_port port[12];
+ struct vsc9953_rew_common common;
+};
+/* END VSC9953 REW structure */
-/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
+/* VSC9953 DEVCPU_GCB structure */
-struct vsc9953_chip_regs {
+struct vsc9953_chip_regs {
u32 chipd_id;
u32 gpr;
u32 soft_rst;
};
-struct vsc9953_gpio {
+struct vsc9953_gpio {
u32 gpio_out_set[10];
u32 gpio_out_clr[10];
u32 gpio_out[10];
u32 miiscan_lst_rslts_valid;
};
-struct vsc9953_mii_read_scan {
+struct vsc9953_mii_read_scan {
u32 mii_scan_results_sticky[2];
};
-struct vsc9953_devcpu_gcb {
+struct vsc9953_devcpu_gcb {
struct vsc9953_chip_regs chip_regs;
struct vsc9953_gpio gpio;
struct vsc9953_mii_mng mii_mng[2];
struct vsc9953_mii_read_scan mii_read_scan;
};
-/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
+/* END VSC9953 DEVCPU_GCB structure */
-/* VSC9953 IS* structure for T1040 U-boot*/
+/* VSC9953 IS* structure */
-struct vsc9953_vcap_core_cfg {
+struct vsc9953_vcap_core_cfg {
u32 vcap_update_ctrl;
u32 vcap_mv_cfg;
};
-struct vsc9953_vcap {
-struct vsc9953_vcap_core_cfg vcap_core_cfg;
+struct vsc9953_vcap {
+ struct vsc9953_vcap_core_cfg vcap_core_cfg;
};
-/* END VSC9953 IS* structure for T1040 U-boot*/
+/* END VSC9953 IS* structure */
#define VSC9953_PORT_INFO_INITIALIZER(idx) \
{ \
/* Structure to describe a VSC9953 switch */
struct vsc9953_info {
- struct vsc9953_port_info port[VSC9953_MAX_PORTS];
+ struct vsc9953_port_info port[VSC9953_MAX_PORTS];
};
void vsc9953_init(bd_t *bis);
-void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus);
-void vsc9953_port_info_set_phy_address(int port, int address);
-void vsc9953_port_enable(int port);
-void vsc9953_port_disable(int port);
-void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int);
+void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
+void vsc9953_port_info_set_phy_address(int port_no, int address);
+void vsc9953_port_enable(int port_no);
+void vsc9953_port_disable(int port_no);
+void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
#endif /* _VSC9953_H_ */
is performed in hardware.
endmenu
+menu "Compression Support"
+
+config LZ4
+ bool "Enable LZ4 decompression support"
+ help
+ If this option is set, support for LZ4 compressed images
+ is included. The LZ4 algorithm can run in-place as long as the
+ compressed image is loaded to the end of the output buffer, and
+ trades lower compression ratios for much faster decompression.
+
+ NOTE: This implements the release version of the LZ4 frame
+ format as generated by default by the 'lz4' command line tool.
+ This is not the same as the outdated, less efficient legacy
+ frame format currently (2015) implemented in the Linux kernel
+ (generated by 'lz4 -l'). The two formats are incompatible.
+
+endmenu
+
config ERRNO_STR
bool "Enable function for getting errno-related string message"
help
obj-y += initcall.o
obj-$(CONFIG_LMB) += lmb.o
obj-y += ldiv.o
+obj-$(CONFIG_LZ4) += lz4_wrapper.o
obj-$(CONFIG_MD5) += md5.o
obj-y += net_utils.o
obj-$(CONFIG_PHYSMEM) += physmem.o
return compat_names[id];
}
-fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
- const char *prop_name, fdt_size_t *sizep)
+fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
+ const char *prop_name, int index, int na, int ns,
+ fdt_size_t *sizep)
{
- const fdt_addr_t *cell;
+ const fdt32_t *prop, *prop_end;
+ const fdt32_t *prop_addr, *prop_size, *prop_after_size;
int len;
+ fdt_addr_t addr;
debug("%s: %s: ", __func__, prop_name);
- cell = fdt_getprop(blob, node, prop_name, &len);
- if (cell && ((!sizep && len == sizeof(fdt_addr_t)) ||
- len == sizeof(fdt_addr_t) * 2)) {
- fdt_addr_t addr = fdt_addr_to_cpu(*cell);
- if (sizep) {
- const fdt_size_t *size;
-
- size = (fdt_size_t *)((char *)cell +
- sizeof(fdt_addr_t));
- *sizep = fdt_size_to_cpu(*size);
- debug("addr=%08lx, size=%llx\n",
- (ulong)addr, (u64)*sizep);
- } else {
- debug("%08lx\n", (ulong)addr);
- }
- return addr;
+
+ if (na > (sizeof(fdt_addr_t) / sizeof(fdt32_t))) {
+ debug("(na too large for fdt_addr_t type)\n");
+ return FDT_ADDR_T_NONE;
}
- debug("(not found)\n");
- return FDT_ADDR_T_NONE;
+
+ if (ns > (sizeof(fdt_size_t) / sizeof(fdt32_t))) {
+ debug("(ns too large for fdt_size_t type)\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ prop = fdt_getprop(blob, node, prop_name, &len);
+ if (!prop) {
+ debug("(not found)\n");
+ return FDT_ADDR_T_NONE;
+ }
+ prop_end = prop + (len / sizeof(*prop));
+
+ prop_addr = prop + (index * (na + ns));
+ prop_size = prop_addr + na;
+ prop_after_size = prop_size + ns;
+ if (prop_after_size > prop_end) {
+ debug("(not enough data: expected >= %d cells, got %d cells)\n",
+ (u32)(prop_after_size - prop), ((u32)(prop_end - prop)));
+ return FDT_ADDR_T_NONE;
+ }
+
+ addr = fdtdec_get_number(prop_addr, na);
+
+ if (sizep) {
+ *sizep = fdtdec_get_number(prop_size, ns);
+ debug("addr=%08llx, size=%llx\n", (u64)addr, (u64)*sizep);
+ } else {
+ debug("addr=%08llx\n", (u64)addr);
+ }
+
+ return addr;
+}
+
+fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
+ int node, const char *prop_name, int index, fdt_size_t *sizep)
+{
+ int na, ns;
+
+ debug("%s: ", __func__);
+
+ na = fdt_address_cells(blob, parent);
+ if (na < 1) {
+ debug("(bad #address-cells)\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ ns = fdt_size_cells(blob, parent);
+ if (ns < 0) {
+ debug("(bad #size-cells)\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ debug("na=%d, ns=%d, ", na, ns);
+
+ return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na,
+ ns, sizep);
+}
+
+fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
+ const char *prop_name, int index, fdt_size_t *sizep)
+{
+ int parent;
+
+ debug("%s: ", __func__);
+
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0) {
+ debug("(no parent found)\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name,
+ index, sizep);
+}
+
+fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
+ const char *prop_name, fdt_size_t *sizep)
+{
+ int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
+
+ return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0,
+ sizeof(fdt_addr_t) / sizeof(fdt32_t),
+ ns, sizep);
}
fdt_addr_t fdtdec_get_addr(const void *blob, int node,
#include <command.h>
#include <image.h>
#include <malloc.h>
+#include <memalign.h>
#include <u-boot/zlib.h>
#include "zlib/zutil.h"
}
/* we allocate new space to make sure we can write to the array */
- if ((data = malloc(size)) == NULL) {
- debug("himport_r: can't malloc %zu bytes\n", size);
+ if ((data = malloc(size + 1)) == NULL) {
+ debug("himport_r: can't malloc %zu bytes\n", size + 1);
__set_errno(ENOMEM);
return 0;
}
memcpy(data, env, size);
+ data[size] = '\0';
dp = data;
/* make a local copy of the list of variables */
}
}
- if(!size)
+ if (!size) {
+ free(data);
return 1; /* everything OK */
+ }
if(crlf_is_lf) {
/* Remove Carriage Returns in front of Line Feeds */
unsigned ignored_crs = 0;
if (*name == 0) {
debug("INSERT: unable to use an empty key\n");
__set_errno(EINVAL);
+ free(data);
return 0;
}
--- /dev/null
+/*
+ LZ4 - Fast LZ compression algorithm
+ Copyright (C) 2011-2015, Yann Collet.
+
+ SPDX-License-Identifier: BSD-2-Clause
+
+ You can contact the author at :
+ - LZ4 source repository : https://github.com/Cyan4973/lz4
+ - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c
+*/
+
+
+/**************************************
+* Reading and writing into memory
+**************************************/
+
+/* customized version of memcpy, which may overwrite up to 7 bytes beyond dstEnd */
+static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd)
+{
+ BYTE* d = (BYTE*)dstPtr;
+ const BYTE* s = (const BYTE*)srcPtr;
+ BYTE* e = (BYTE*)dstEnd;
+ do { LZ4_copy8(d,s); d+=8; s+=8; } while (d<e);
+}
+
+
+/**************************************
+* Common Constants
+**************************************/
+#define MINMATCH 4
+
+#define COPYLENGTH 8
+#define LASTLITERALS 5
+#define MFLIMIT (COPYLENGTH+MINMATCH)
+static const int LZ4_minLength = (MFLIMIT+1);
+
+#define KB *(1 <<10)
+#define MB *(1 <<20)
+#define GB *(1U<<30)
+
+#define MAXD_LOG 16
+#define MAX_DISTANCE ((1 << MAXD_LOG) - 1)
+
+#define ML_BITS 4
+#define ML_MASK ((1U<<ML_BITS)-1)
+#define RUN_BITS (8-ML_BITS)
+#define RUN_MASK ((1U<<RUN_BITS)-1)
+
+
+/**************************************
+* Local Structures and types
+**************************************/
+typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive;
+typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive;
+typedef enum { full = 0, partial = 1 } earlyEnd_directive;
+
+
+
+/*******************************
+* Decompression functions
+*******************************/
+/*
+ * This generic decompression function cover all use cases.
+ * It shall be instantiated several times, using different sets of directives
+ * Note that it is essential this generic function is really inlined,
+ * in order to remove useless branches during compilation optimization.
+ */
+FORCE_INLINE int LZ4_decompress_generic(
+ const char* const source,
+ char* const dest,
+ int inputSize,
+ int outputSize, /* If endOnInput==endOnInputSize, this value is the max size of Output Buffer. */
+
+ int endOnInput, /* endOnOutputSize, endOnInputSize */
+ int partialDecoding, /* full, partial */
+ int targetOutputSize, /* only used if partialDecoding==partial */
+ int dict, /* noDict, withPrefix64k, usingExtDict */
+ const BYTE* const lowPrefix, /* == dest if dict == noDict */
+ const BYTE* const dictStart, /* only if dict==usingExtDict */
+ const size_t dictSize /* note : = 0 if noDict */
+ )
+{
+ /* Local Variables */
+ const BYTE* ip = (const BYTE*) source;
+ const BYTE* const iend = ip + inputSize;
+
+ BYTE* op = (BYTE*) dest;
+ BYTE* const oend = op + outputSize;
+ BYTE* cpy;
+ BYTE* oexit = op + targetOutputSize;
+ const BYTE* const lowLimit = lowPrefix - dictSize;
+
+ const BYTE* const dictEnd = (const BYTE*)dictStart + dictSize;
+ const size_t dec32table[] = {4, 1, 2, 1, 4, 4, 4, 4};
+ const size_t dec64table[] = {0, 0, 0, (size_t)-1, 0, 1, 2, 3};
+
+ const int safeDecode = (endOnInput==endOnInputSize);
+ const int checkOffset = ((safeDecode) && (dictSize < (int)(64 KB)));
+
+
+ /* Special cases */
+ if ((partialDecoding) && (oexit> oend-MFLIMIT)) oexit = oend-MFLIMIT; /* targetOutputSize too high => decode everything */
+ if ((endOnInput) && (unlikely(outputSize==0))) return ((inputSize==1) && (*ip==0)) ? 0 : -1; /* Empty output buffer */
+ if ((!endOnInput) && (unlikely(outputSize==0))) return (*ip==0?1:-1);
+
+
+ /* Main Loop */
+ while (1)
+ {
+ unsigned token;
+ size_t length;
+ const BYTE* match;
+
+ /* get literal length */
+ token = *ip++;
+ if ((length=(token>>ML_BITS)) == RUN_MASK)
+ {
+ unsigned s;
+ do
+ {
+ s = *ip++;
+ length += s;
+ }
+ while (likely((endOnInput)?ip<iend-RUN_MASK:1) && (s==255));
+ if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)(op))) goto _output_error; /* overflow detection */
+ if ((safeDecode) && unlikely((size_t)(ip+length)<(size_t)(ip))) goto _output_error; /* overflow detection */
+ }
+
+ /* copy literals */
+ cpy = op+length;
+ if (((endOnInput) && ((cpy>(partialDecoding?oexit:oend-MFLIMIT)) || (ip+length>iend-(2+1+LASTLITERALS))) )
+ || ((!endOnInput) && (cpy>oend-COPYLENGTH)))
+ {
+ if (partialDecoding)
+ {
+ if (cpy > oend) goto _output_error; /* Error : write attempt beyond end of output buffer */
+ if ((endOnInput) && (ip+length > iend)) goto _output_error; /* Error : read attempt beyond end of input buffer */
+ }
+ else
+ {
+ if ((!endOnInput) && (cpy != oend)) goto _output_error; /* Error : block decoding must stop exactly there */
+ if ((endOnInput) && ((ip+length != iend) || (cpy > oend))) goto _output_error; /* Error : input must be consumed */
+ }
+ memcpy(op, ip, length);
+ ip += length;
+ op += length;
+ break; /* Necessarily EOF, due to parsing restrictions */
+ }
+ LZ4_wildCopy(op, ip, cpy);
+ ip += length; op = cpy;
+
+ /* get offset */
+ match = cpy - LZ4_readLE16(ip); ip+=2;
+ if ((checkOffset) && (unlikely(match < lowLimit))) goto _output_error; /* Error : offset outside destination buffer */
+
+ /* get matchlength */
+ length = token & ML_MASK;
+ if (length == ML_MASK)
+ {
+ unsigned s;
+ do
+ {
+ if ((endOnInput) && (ip > iend-LASTLITERALS)) goto _output_error;
+ s = *ip++;
+ length += s;
+ } while (s==255);
+ if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)op)) goto _output_error; /* overflow detection */
+ }
+ length += MINMATCH;
+
+ /* check external dictionary */
+ if ((dict==usingExtDict) && (match < lowPrefix))
+ {
+ if (unlikely(op+length > oend-LASTLITERALS)) goto _output_error; /* doesn't respect parsing restriction */
+
+ if (length <= (size_t)(lowPrefix-match))
+ {
+ /* match can be copied as a single segment from external dictionary */
+ match = dictEnd - (lowPrefix-match);
+ memmove(op, match, length); op += length;
+ }
+ else
+ {
+ /* match encompass external dictionary and current segment */
+ size_t copySize = (size_t)(lowPrefix-match);
+ memcpy(op, dictEnd - copySize, copySize);
+ op += copySize;
+ copySize = length - copySize;
+ if (copySize > (size_t)(op-lowPrefix)) /* overlap within current segment */
+ {
+ BYTE* const endOfMatch = op + copySize;
+ const BYTE* copyFrom = lowPrefix;
+ while (op < endOfMatch) *op++ = *copyFrom++;
+ }
+ else
+ {
+ memcpy(op, lowPrefix, copySize);
+ op += copySize;
+ }
+ }
+ continue;
+ }
+
+ /* copy repeated sequence */
+ cpy = op + length;
+ if (unlikely((op-match)<8))
+ {
+ const size_t dec64 = dec64table[op-match];
+ op[0] = match[0];
+ op[1] = match[1];
+ op[2] = match[2];
+ op[3] = match[3];
+ match += dec32table[op-match];
+ LZ4_copy4(op+4, match);
+ op += 8; match -= dec64;
+ } else { LZ4_copy8(op, match); op+=8; match+=8; }
+
+ if (unlikely(cpy>oend-12))
+ {
+ if (cpy > oend-LASTLITERALS) goto _output_error; /* Error : last LASTLITERALS bytes must be literals */
+ if (op < oend-8)
+ {
+ LZ4_wildCopy(op, match, oend-8);
+ match += (oend-8) - op;
+ op = oend-8;
+ }
+ while (op<cpy) *op++ = *match++;
+ }
+ else
+ LZ4_wildCopy(op, match, cpy);
+ op=cpy; /* correction */
+ }
+
+ /* end of decoding */
+ if (endOnInput)
+ return (int) (((char*)op)-dest); /* Nb of output bytes decoded */
+ else
+ return (int) (((const char*)ip)-source); /* Nb of input bytes read */
+
+ /* Overflow error detected */
+_output_error:
+ return (int) (-(((const char*)ip)-source))-1;
+}
--- /dev/null
+/*
+ * Copyright 2015 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <compiler.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+static u16 LZ4_readLE16(const void *src) { return le16_to_cpu(*(u16 *)src); }
+static void LZ4_copy4(void *dst, const void *src) { *(u32 *)dst = *(u32 *)src; }
+static void LZ4_copy8(void *dst, const void *src) { *(u64 *)dst = *(u64 *)src; }
+
+typedef uint8_t BYTE;
+typedef uint16_t U16;
+typedef uint32_t U32;
+typedef int32_t S32;
+typedef uint64_t U64;
+
+#define FORCE_INLINE static inline __attribute__((always_inline))
+
+/* Unaltered (except removing unrelated code) from github.com/Cyan4973/lz4. */
+#include "lz4.c" /* #include for inlining, do not link! */
+
+#define LZ4F_MAGIC 0x184D2204
+
+struct lz4_frame_header {
+ u32 magic;
+ union {
+ u8 flags;
+ struct {
+ u8 reserved0:2;
+ u8 has_content_checksum:1;
+ u8 has_content_size:1;
+ u8 has_block_checksum:1;
+ u8 independent_blocks:1;
+ u8 version:2;
+ };
+ };
+ union {
+ u8 block_descriptor;
+ struct {
+ u8 reserved1:4;
+ u8 max_block_size:3;
+ u8 reserved2:1;
+ };
+ };
+ /* + u64 content_size iff has_content_size is set */
+ /* + u8 header_checksum */
+} __packed;
+
+struct lz4_block_header {
+ union {
+ u32 raw;
+ struct {
+ u32 size:31;
+ u32 not_compressed:1;
+ };
+ };
+ /* + size bytes of data */
+ /* + u32 block_checksum iff has_block_checksum is set */
+} __packed;
+
+int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn)
+{
+ const void *end = dst + *dstn;
+ const void *in = src;
+ void *out = dst;
+ int has_block_checksum;
+ int ret;
+ *dstn = 0;
+
+ { /* With in-place decompression the header may become invalid later. */
+ const struct lz4_frame_header *h = in;
+
+ if (srcn < sizeof(*h) + sizeof(u64) + sizeof(u8))
+ return -EINVAL; /* input overrun */
+
+ /* We assume there's always only a single, standard frame. */
+ if (le32_to_cpu(h->magic) != LZ4F_MAGIC || h->version != 1)
+ return -EPROTONOSUPPORT; /* unknown format */
+ if (h->reserved0 || h->reserved1 || h->reserved2)
+ return -EINVAL; /* reserved must be zero */
+ if (!h->independent_blocks)
+ return -EPROTONOSUPPORT; /* we can't support this yet */
+ has_block_checksum = h->has_block_checksum;
+
+ in += sizeof(*h);
+ if (h->has_content_size)
+ in += sizeof(u64);
+ in += sizeof(u8);
+ }
+
+ while (1) {
+ struct lz4_block_header b = { .raw = le32_to_cpu(*(u32 *)in) };
+ in += sizeof(struct lz4_block_header);
+
+ if (in - src + b.size > srcn) {
+ ret = -EINVAL; /* input overrun */
+ break;
+ }
+
+ if (!b.size) {
+ ret = 0; /* decompression successful */
+ break;
+ }
+
+ if (b.not_compressed) {
+ size_t size = min((ptrdiff_t)b.size, end - out);
+ memcpy(out, in, size);
+ out += size;
+ if (size < b.size) {
+ ret = -ENOBUFS; /* output overrun */
+ break;
+ }
+ } else {
+ /* constant folding essential, do not touch params! */
+ ret = LZ4_decompress_generic(in, out, b.size,
+ end - out, endOnInputSize,
+ full, 0, noDict, out, NULL, 0);
+ if (ret < 0) {
+ ret = -EPROTO; /* decompression error */
+ break;
+ }
+ out += ret;
+ }
+
+ in += b.size;
+ if (has_block_checksum)
+ in += sizeof(u32);
+ }
+
+ *dstn = out - dst;
+ return ret;
+}
*/
#ifndef MY_ZCALLOC /* Any system without a special alloc function */
-#ifndef __UBOOT__
+#ifdef __UBOOT__
+#include <malloc.h>
+#else
#ifndef STDC
extern voidp malloc OF((uInt size));
extern voidp calloc OF((uInt items, uInt size));
A new MAC address will be generated on every boot and it will
not be added to the environment.
+config NETCONSOLE
+ bool "NetConsole support"
+ help
+ Support the 'nc' input/output device for networked console.
+ See README.NetConsole for details.
+
endif # if NET
priv->state = ETH_STATE_PASSIVE;
}
+int eth_is_active(struct udevice *dev)
+{
+ struct eth_device_priv *priv;
+
+ if (!dev || !device_active(dev))
+ return 0;
+
+ priv = dev_get_uclass_priv(dev);
+ return priv->state == ETH_STATE_ACTIVE;
+}
+
int eth_send(void *packet, int length)
{
struct udevice *current;
.per_device_auto_alloc_size = sizeof(struct eth_device_priv),
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
-#endif
+#endif /* #ifdef CONFIG_DM_ETH */
#ifndef CONFIG_DM_ETH
eth_current->state = ETH_STATE_PASSIVE;
}
+int eth_is_active(struct eth_device *dev)
+{
+ return dev && dev->state == ETH_STATE_ACTIVE;
+}
+
int eth_send(void *packet, int length)
{
if (!eth_current)
hashtab[hash % HASHSZ] = aux;
}
-/*
- * Clear the set of configuration strings.
- */
-static void clear_config(void)
-{
- struct item *aux, *next;
- unsigned int i;
-
- for (i = 0; i < HASHSZ; i++) {
- for (aux = hashtab[i]; aux; aux = next) {
- next = aux->next;
- free(aux);
- }
- hashtab[i] = NULL;
- }
-}
-
/*
* Record the use of a CONFIG_* word.
*/
int saw_any_target = 0;
int is_first_dep = 0;
- clear_config();
-
while (m < end) {
/* Skip any "white space" */
while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
"\x73\x61\x67\x65\x73\x2e\x0a\x11\x00\x00\x00\x00\x00\x00";
static const unsigned long lzo_compressed_size = 334;
+/* lz4 -z /tmp/plain.txt > /tmp/plain.lz4 */
+static const char lz4_compressed[] =
+ "\x04\x22\x4d\x18\x64\x70\xb9\x01\x01\x00\x00\xff\x19\x49\x20\x61"
+ "\x6d\x20\x61\x20\x68\x69\x67\x68\x6c\x79\x20\x63\x6f\x6d\x70\x72"
+ "\x65\x73\x73\x61\x62\x6c\x65\x20\x62\x69\x74\x20\x6f\x66\x20\x74"
+ "\x65\x78\x74\x2e\x0a\x28\x00\x3d\xf1\x25\x54\x68\x65\x72\x65\x20"
+ "\x61\x72\x65\x20\x6d\x61\x6e\x79\x20\x6c\x69\x6b\x65\x20\x6d\x65"
+ "\x2c\x20\x62\x75\x74\x20\x74\x68\x69\x73\x20\x6f\x6e\x65\x20\x69"
+ "\x73\x20\x6d\x69\x6e\x65\x2e\x0a\x49\x66\x20\x49\x20\x77\x32\x00"
+ "\xd1\x6e\x79\x20\x73\x68\x6f\x72\x74\x65\x72\x2c\x20\x74\x45\x00"
+ "\xf4\x0b\x77\x6f\x75\x6c\x64\x6e\x27\x74\x20\x62\x65\x20\x6d\x75"
+ "\x63\x68\x20\x73\x65\x6e\x73\x65\x20\x69\x6e\x0a\xcf\x00\x50\x69"
+ "\x6e\x67\x20\x6d\x12\x00\x00\x32\x00\xf0\x11\x20\x66\x69\x72\x73"
+ "\x74\x20\x70\x6c\x61\x63\x65\x2e\x20\x41\x74\x20\x6c\x65\x61\x73"
+ "\x74\x20\x77\x69\x74\x68\x20\x6c\x7a\x6f\x2c\x63\x00\xf5\x14\x77"
+ "\x61\x79\x2c\x0a\x77\x68\x69\x63\x68\x20\x61\x70\x70\x65\x61\x72"
+ "\x73\x20\x74\x6f\x20\x62\x65\x68\x61\x76\x65\x20\x70\x6f\x6f\x72"
+ "\x6c\x79\x4e\x00\x30\x61\x63\x65\x27\x01\x01\x95\x00\x01\x2d\x01"
+ "\xb0\x0a\x6d\x65\x73\x73\x61\x67\x65\x73\x2e\x0a\x00\x00\x00\x00"
+ "\x9d\x12\x8c\x9d";
+static const unsigned long lz4_compressed_size = 276;
+
#define TEST_BUFFER_SIZE 512
return (ret != LZO_E_OK);
}
+static int compress_using_lz4(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ /* There is no lz4 compression in u-boot, so fake it. */
+ assert(in_size == strlen(plain));
+ assert(memcmp(plain, in, in_size) == 0);
+
+ if (lz4_compressed_size > out_max)
+ return -1;
+
+ memcpy(out, lz4_compressed, lz4_compressed_size);
+ if (out_size)
+ *out_size = lz4_compressed_size;
+
+ return 0;
+}
+
+static int uncompress_using_lz4(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ int ret;
+ size_t input_size = in_size;
+ size_t output_size = out_max;
+
+ ret = ulz4fn(in, input_size, out, &output_size);
+ if (out_size)
+ *out_size = output_size;
+
+ return (ret != 0);
+}
+
#define errcheck(statement) if (!(statement)) { \
fprintf(stderr, "\tFailed: %s\n", #statement); \
ret = 1; \
err += run_test("bzip2", compress_using_bzip2, uncompress_using_bzip2);
err += run_test("lzma", compress_using_lzma, uncompress_using_lzma);
err += run_test("lzo", compress_using_lzo, uncompress_using_lzo);
+ err += run_test("lz4", compress_using_lz4, uncompress_using_lz4);
printf("ut_compression %s\n", err == 0 ? "ok" : "FAILED");
err |= run_bootm_test(IH_COMP_BZIP2, compress_using_bzip2);
err |= run_bootm_test(IH_COMP_LZMA, compress_using_lzma);
err |= run_bootm_test(IH_COMP_LZO, compress_using_lzo);
+ err |= run_bootm_test(IH_COMP_LZ4, compress_using_lz4);
err |= run_bootm_test(IH_COMP_NONE, compress_using_none);
printf("ut_image_decomp %s\n", err == 0 ? "ok" : "FAILED");
int dm_leak_check_end(struct unit_test_state *uts)
{
struct mallinfo end;
- int id;
+ int id, diff;
/* Don't delete the root class, since we started with that */
for (id = UCLASS_ROOT + 1; id < UCLASS_COUNT; id++) {
}
end = mallinfo();
+ diff = end.uordblks - uts->start.uordblks;
+ if (diff > 0)
+ printf("Leak: lost %#xd bytes\n", diff);
+ else if (diff < 0)
+ printf("Leak: gained %#xd bytes\n", -diff);
ut_asserteq(uts->start.uordblks, end.uordblks);
return 0;
# Expected results are as follows:
# EXT4 tests:
# fs-test.sb.ext4.out: Summary: PASS: 17 FAIL: 2
-# fs-test.ext4.out: Summary: PASS: 11 FAIL: 8
-# fs-test.fs.ext4.out: Summary: PASS: 11 FAIL: 8
+# fs-test.ext4.out: Summary: PASS: 10 FAIL: 9
+# fs-test.fs.ext4.out: Summary: PASS: 10 FAIL: 9
# FAT tests:
# fs-test.sb.fat.out: Summary: PASS: 17 FAIL: 2
# fs-test.fat.out: Summary: PASS: 19 FAIL: 0
# fs-test.fs.fat.out: Summary: PASS: 19 FAIL: 0
-# Total Summary: TOTAL PASS: 94 TOTAL FAIL: 20
+# Total Summary: TOTAL PASS: 92 TOTAL FAIL: 22
# pre-requisite binaries list.
PREREQ_BINS="md5sum mkfs mount umount dd fallocate mkdir"
check_md5 "Test Case 9b " "$1" "$2" 6 \
"TC9: load 1MB chunk crossing 2GB boundary from $4"
- # Check 2mb chunk from the last 1MB of 2.5GB file - generic failure case
- grep -A6 "Test Case 10 " "$1" | grep -q 'Error: "filesize" not defined'
- pass_fail "TC10: load 2MB from the last 1MB of $4 - generic fail case"
+ # Check 2mb chunk from the last 1MB of 2.5GB file loads 1MB
+ grep -A6 "Test Case 10 " "$1" | grep -q "filesize=100000"
+ pass_fail "TC10: load 2MB from the last 1MB of $4 loads 1MB"
# Check 1mb chunk write
grep -A3 "Test Case 11a " "$1" | \
{
uint32_t checksum;
char *source_date_epoch;
- struct tm *time_universal;
time_t time;
image_header_t * hdr = (image_header_t *)ptr;
if (source_date_epoch != NULL) {
time = (time_t) strtol(source_date_epoch, NULL, 10);
- time_universal = gmtime(&time);
- if (time_universal == NULL) {
+ if (gmtime(&time) == NULL) {
fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
__func__);
time = 0;
- } else {
- time = mktime(time_universal);
}
} else {
time = sbuf->st_mtime;
{
unsigned long ethaddr_low, ethaddr_high;
- srand(time(0) | getpid());
+ srand(time(0) + (getpid() << 8));
/*
* setting the 2nd LSB in the most significant byte of
}
}
+static struct dcd_v2_cmd *gd_last_cmd;
+
static void set_dcd_param_v2(struct imx_header *imxhdr, uint32_t dcd_len,
int32_t cmd)
{
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ struct dcd_v2_cmd *d = gd_last_cmd;
+ struct dcd_v2_cmd *d2;
+ int len;
+
+ if (!d)
+ d = &dcd_v2->dcd_cmd;
+ d2 = d;
+ len = be16_to_cpu(d->write_dcd_command.length);
+ if (len > 4)
+ d2 = (struct dcd_v2_cmd *)(((char *)d) + len);
switch (cmd) {
case CMD_WRITE_DATA:
- dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 4);
- dcd_v2->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
+ if ((d->write_dcd_command.tag == DCD_WRITE_DATA_COMMAND_TAG) &&
+ (d->write_dcd_command.param == DCD_WRITE_DATA_PARAM))
+ break;
+ d = d2;
+ d->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+ d->write_dcd_command.length = cpu_to_be16(4);
+ d->write_dcd_command.param = DCD_WRITE_DATA_PARAM;
break;
case CMD_WRITE_CLR_BIT:
- dcd_v2->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 4);
- dcd_v2->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
+ if ((d->write_dcd_command.tag == DCD_WRITE_DATA_COMMAND_TAG) &&
+ (d->write_dcd_command.param == DCD_WRITE_CLR_BIT_PARAM))
+ break;
+ d = d2;
+ d->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+ d->write_dcd_command.length = cpu_to_be16(4);
+ d->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
break;
/*
* Check data command only supports one entry,
- * so use 0xC = size(address + value + command).
*/
case CMD_CHECK_BITS_SET:
- dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
- dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+ d = d2;
+ d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+ d->write_dcd_command.length = cpu_to_be16(4);
+ d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
break;
case CMD_CHECK_BITS_CLR:
- dcd_v2->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
- dcd_v2->write_dcd_command.length = cpu_to_be16(0xC);
- dcd_v2->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
+ d = d2;
+ d->write_dcd_command.tag = DCD_CHECK_DATA_COMMAND_TAG;
+ d->write_dcd_command.length = cpu_to_be16(4);
+ d->write_dcd_command.param = DCD_CHECK_BITS_SET_PARAM;
break;
default:
break;
}
+ gd_last_cmd = d;
}
static void set_dcd_val_v2(struct imx_header *imxhdr, char *name, int lineno,
int fld, uint32_t value, uint32_t off)
{
- dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ struct dcd_v2_cmd *d = gd_last_cmd;
+ int len;
+
+ len = be16_to_cpu(d->write_dcd_command.length);
+ off = (len - 4) >> 3;
switch (fld) {
case CFG_REG_ADDRESS:
- dcd_v2->addr_data[off].addr = cpu_to_be32(value);
+ d->addr_data[off].addr = cpu_to_be32(value);
break;
case CFG_REG_VALUE:
- dcd_v2->addr_data[off].value = cpu_to_be32(value);
+ d->addr_data[off].value = cpu_to_be32(value);
+ off++;
+ d->write_dcd_command.length = cpu_to_be16((off << 3) + 4);
break;
default:
break;
char *name, int lineno)
{
dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
+ struct dcd_v2_cmd *d = gd_last_cmd;
+ int len;
+
+ if (!d)
+ d = &dcd_v2->dcd_cmd;
+ len = be16_to_cpu(d->write_dcd_command.length);
+ if (len > 4)
+ d = (struct dcd_v2_cmd *)(((char *)d) + len);
+
+ len = (char *)d - (char *)&dcd_v2->header;
dcd_v2->header.tag = DCD_HEADER_TAG;
- dcd_v2->header.length = cpu_to_be16(
- dcd_len * sizeof(dcd_addr_data_t) + 8);
+ dcd_v2->header.length = cpu_to_be16(len);
dcd_v2->header.version = DCD_VERSION;
- set_dcd_param_v2(imxhdr, dcd_len, CMD_WRITE_DATA);
}
static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
max_dcd_entries = MAX_HW_CFG_SIZE_V1;
break;
case IMXIMAGE_V2:
+ gd_last_cmd = NULL;
set_dcd_val = set_dcd_val_v2;
set_dcd_param = set_dcd_param_v2;
set_dcd_rst = set_dcd_rst_v2;
dcd_v2_t *dcd_v2 = &hdr_v2->dcd_table;
uint32_t size, version;
- size = be16_to_cpu(dcd_v2->header.length) - 8;
- if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t))) {
+ size = be16_to_cpu(dcd_v2->header.length);
+ if (size > (MAX_HW_CFG_SIZE_V2 * sizeof(dcd_addr_data_t)) + 8) {
fprintf(stderr,
"Error: Image corrupt DCD size %d exceed maximum %d\n",
(uint32_t)(size / sizeof(dcd_addr_data_t)),
uint8_t param;
} __attribute__((packed)) write_dcd_command_t;
-typedef struct {
- ivt_header_t header;
+struct dcd_v2_cmd {
write_dcd_command_t write_dcd_command;
dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
+};
+
+typedef struct {
+ ivt_header_t header;
+ struct dcd_v2_cmd dcd_cmd;
uint32_t padding[1]; /* end up on an 8-byte boundary */
} dcd_v2_t;
#include <stdint.h>
#include "kwbimage.h"
-#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
-
-/* Structure of the main header, version 0 (Kirkwood, Dove) */
-struct main_hdr_v0 {
- uint8_t blockid; /*0 */
- uint8_t nandeccmode; /*1 */
- uint16_t nandpagesize; /*2-3 */
- uint32_t blocksize; /*4-7 */
- uint32_t rsvd1; /*8-11 */
- uint32_t srcaddr; /*12-15 */
- uint32_t destaddr; /*16-19 */
- uint32_t execaddr; /*20-23 */
- uint8_t satapiomode; /*24 */
- uint8_t rsvd3; /*25 */
- uint16_t ddrinitdelay; /*26-27 */
- uint16_t rsvd2; /*28-29 */
- uint8_t ext; /*30 */
- uint8_t checksum; /*31 */
-};
-
-struct ext_hdr_v0_reg {
- uint32_t raddr;
- uint32_t rdata;
-};
-
-#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
-
-struct ext_hdr_v0 {
- uint32_t offset;
- uint8_t reserved[0x20 - sizeof(uint32_t)];
- struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
- uint8_t reserved2[7];
- uint8_t checksum;
-};
-
-/* Structure of the main header, version 1 (Armada 370, Armada XP) */
-struct main_hdr_v1 {
- uint8_t blockid; /* 0 */
- uint8_t reserved1; /* 1 */
- uint16_t reserved2; /* 2-3 */
- uint32_t blocksize; /* 4-7 */
- uint8_t version; /* 8 */
- uint8_t headersz_msb; /* 9 */
- uint16_t headersz_lsb; /* A-B */
- uint32_t srcaddr; /* C-F */
- uint32_t destaddr; /* 10-13 */
- uint32_t execaddr; /* 14-17 */
- uint8_t reserved3; /* 18 */
- uint8_t nandblocksize; /* 19 */
- uint8_t nandbadblklocation; /* 1A */
- uint8_t reserved4; /* 1B */
- uint16_t reserved5; /* 1C-1D */
- uint8_t ext; /* 1E */
- uint8_t checksum; /* 1F */
-};
-
-/*
- * Header for the optional headers, version 1 (Armada 370, Armada XP)
- */
-struct opt_hdr_v1 {
- uint8_t headertype;
- uint8_t headersz_msb;
- uint16_t headersz_lsb;
- char data[0];
-};
-
-/*
- * Various values for the opt_hdr_v1->headertype field, describing the
- * different types of optional headers. The "secure" header contains
- * informations related to secure boot (encryption keys, etc.). The
- * "binary" header contains ARM binary code to be executed prior to
- * executing the main payload (usually the bootloader). This is
- * typically used to execute DDR3 training code. The "register" header
- * allows to describe a set of (address, value) tuples that are
- * generally used to configure the DRAM controller.
- */
-#define OPT_HDR_V1_SECURE_TYPE 0x1
-#define OPT_HDR_V1_BINARY_TYPE 0x2
-#define OPT_HDR_V1_REGISTER_TYPE 0x3
-
-#define KWBHEADER_V1_SIZE(hdr) \
- (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
-
static struct image_cfg_element *image_cfg;
static int cfgn;
#define IMAGE_CFG_ELEMENT_MAX 256
-/*
- * Byte 8 of the image header contains the version number. In the v0
- * header, byte 8 was reserved, and always set to 0. In the v1 header,
- * byte 8 has been changed to a proper field, set to 1.
- */
-static unsigned int image_version(void *header)
-{
- unsigned char *ptr = header;
- return ptr[8];
-}
-
/*
* Utility functions to manipulate boot mode and ecc modes (convert
* them back and forth between description strings and the
#define IBR_HDR_UART_ID 0x69
#define IBR_DEF_ATTRIB 0x00
-enum kwbimage_cmd {
- CMD_INVALID,
- CMD_BOOT_FROM,
- CMD_NAND_ECC_MODE,
- CMD_NAND_PAGE_SIZE,
- CMD_SATA_PIO_MODE,
- CMD_DDR_INIT_DELAY,
- CMD_DATA
-};
+#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
-enum kwbimage_cmd_types {
- CFG_INVALID = -1,
- CFG_COMMAND,
- CFG_DATA0,
- CFG_DATA1
-};
-
-/* typedefs */
-typedef struct bhr_t {
- uint8_t blockid; /*0 */
- uint8_t nandeccmode; /*1 */
+/* Structure of the main header, version 0 (Kirkwood, Dove) */
+struct main_hdr_v0 {
+ uint8_t blockid; /*0 */
+ uint8_t nandeccmode; /*1 */
uint16_t nandpagesize; /*2-3 */
uint32_t blocksize; /*4-7 */
uint32_t rsvd1; /*8-11 */
uint32_t srcaddr; /*12-15 */
uint32_t destaddr; /*16-19 */
uint32_t execaddr; /*20-23 */
- uint8_t satapiomode; /*24 */
- uint8_t rsvd3; /*25 */
+ uint8_t satapiomode; /*24 */
+ uint8_t rsvd3; /*25 */
uint16_t ddrinitdelay; /*26-27 */
uint16_t rsvd2; /*28-29 */
- uint8_t ext; /*30 */
- uint8_t checkSum; /*31 */
-} bhr_t, *pbhr_t;
+ uint8_t ext; /*30 */
+ uint8_t checksum; /*31 */
+};
-struct reg_config {
+struct ext_hdr_v0_reg {
uint32_t raddr;
uint32_t rdata;
};
-typedef struct extbhr_t {
- uint32_t dramregsoffs;
- uint8_t rsrvd1[0x20 - sizeof(uint32_t)];
- struct reg_config rcfg[KWBIMAGE_MAX_CONFIG];
- uint8_t rsrvd2[7];
- uint8_t checkSum;
-} extbhr_t, *pextbhr_t;
+#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
+
+struct ext_hdr_v0 {
+ uint32_t offset;
+ uint8_t reserved[0x20 - sizeof(uint32_t)];
+ struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
+ uint8_t reserved2[7];
+ uint8_t checksum;
+};
struct kwb_header {
- bhr_t kwb_hdr;
- extbhr_t kwb_exthdr;
+ struct main_hdr_v0 kwb_hdr;
+ struct ext_hdr_v0 kwb_exthdr;
+};
+
+/* Structure of the main header, version 1 (Armada 370, Armada XP) */
+struct main_hdr_v1 {
+ uint8_t blockid; /* 0 */
+ uint8_t reserved1; /* 1 */
+ uint16_t reserved2; /* 2-3 */
+ uint32_t blocksize; /* 4-7 */
+ uint8_t version; /* 8 */
+ uint8_t headersz_msb; /* 9 */
+ uint16_t headersz_lsb; /* A-B */
+ uint32_t srcaddr; /* C-F */
+ uint32_t destaddr; /* 10-13 */
+ uint32_t execaddr; /* 14-17 */
+ uint8_t reserved3; /* 18 */
+ uint8_t nandblocksize; /* 19 */
+ uint8_t nandbadblklocation; /* 1A */
+ uint8_t reserved4; /* 1B */
+ uint16_t reserved5; /* 1C-1D */
+ uint8_t ext; /* 1E */
+ uint8_t checksum; /* 1F */
+};
+
+/*
+ * Header for the optional headers, version 1 (Armada 370, Armada XP)
+ */
+struct opt_hdr_v1 {
+ uint8_t headertype;
+ uint8_t headersz_msb;
+ uint16_t headersz_lsb;
+ char data[0];
+};
+
+/*
+ * Various values for the opt_hdr_v1->headertype field, describing the
+ * different types of optional headers. The "secure" header contains
+ * informations related to secure boot (encryption keys, etc.). The
+ * "binary" header contains ARM binary code to be executed prior to
+ * executing the main payload (usually the bootloader). This is
+ * typically used to execute DDR3 training code. The "register" header
+ * allows to describe a set of (address, value) tuples that are
+ * generally used to configure the DRAM controller.
+ */
+#define OPT_HDR_V1_SECURE_TYPE 0x1
+#define OPT_HDR_V1_BINARY_TYPE 0x2
+#define OPT_HDR_V1_REGISTER_TYPE 0x3
+
+#define KWBHEADER_V1_SIZE(hdr) \
+ (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+
+enum kwbimage_cmd {
+ CMD_INVALID,
+ CMD_BOOT_FROM,
+ CMD_NAND_ECC_MODE,
+ CMD_NAND_PAGE_SIZE,
+ CMD_SATA_PIO_MODE,
+ CMD_DDR_INIT_DELAY,
+ CMD_DATA
+};
+
+enum kwbimage_cmd_types {
+ CFG_INVALID = -1,
+ CFG_COMMAND,
+ CFG_DATA0,
+ CFG_DATA1
};
/*
*/
void init_kwb_image_type (void);
+/*
+ * Byte 8 of the image header contains the version number. In the v0
+ * header, byte 8 was reserved, and always set to 0. In the v1 header,
+ * byte 8 has been changed to a proper field, set to 1.
+ */
+static inline unsigned int image_version(void *header)
+{
+ unsigned char *ptr = header;
+ return ptr[8];
+}
+
#endif /* _KWBIMAGE_H_ */
kwboot_img_patch_hdr(void *img, size_t size)
{
int rc;
- bhr_t *hdr;
+ struct main_hdr_v1 *hdr;
uint8_t csum;
- const size_t hdrsz = sizeof(*hdr);
+ size_t hdrsz = sizeof(*hdr);
+ int image_ver;
rc = -1;
hdr = img;
goto out;
}
- csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum;
- if (csum != hdr->checkSum) {
+ image_ver = image_version(img);
+ if (image_ver < 0) {
+ fprintf(stderr, "Invalid image header version\n");
+ errno = EINVAL;
+ goto out;
+ }
+
+ if (image_ver == 0)
+ hdrsz = sizeof(*hdr);
+ else
+ hdrsz = KWBHEADER_V1_SIZE(hdr);
+
+ csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checksum;
+ if (csum != hdr->checksum) {
errno = EINVAL;
goto out;
}
hdr->blockid = IBR_HDR_UART_ID;
- hdr->nandeccmode = IBR_HDR_ECC_DISABLED;
- hdr->nandpagesize = 0;
+ if (image_ver == 0) {
+ struct main_hdr_v0 *hdr_v0 = img;
- hdr->srcaddr = hdr->ext
- ? sizeof(struct kwb_header)
- : sizeof(*hdr);
+ hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED;
+ hdr_v0->nandpagesize = 0;
+
+ hdr_v0->srcaddr = hdr_v0->ext
+ ? sizeof(struct kwb_header)
+ : sizeof(*hdr_v0);
+ }
- hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum;
+ hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;
rc = 0;
out:
params.cmdname);
fprintf(stderr, " %s [-D dtc_options] [-f fit-image.its|-F] fit-image\n",
params.cmdname);
- fprintf(stderr, " -D => set options for device tree compiler\n"
+ fprintf(stderr, " -D => set all options for device tree compiler\n"
" -f => input filename for FIT source\n");
#ifdef CONFIG_FIT_SIGNATURE
fprintf(stderr, "Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-r]\n"
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
+#include "asm/arch/spl.h"
-/* boot head definition from sun4i boot code */
-struct boot_file_head {
- uint32_t b_instruction; /* one intruction jumping to real code */
- uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
- uint32_t check_sum; /* generated by PC */
- uint32_t length; /* generated by PC */
- /*
- * We use a simplified header, only filling in what is needed
- * by the boot ROM. To be compatible with Allwinner tools we
- * would need to implement the proper fields here instead of
- * padding.
- */
- uint8_t pad[12]; /* align to 32 bytes */
-};
-
-#define BOOT0_MAGIC "eGON.BT0"
#define STAMP_VALUE 0x5F0A6C39
/* check sum functon from sun4i boot code */
return EXIT_FAILURE;
}
- memset(img.pad, 0, BLOCK_SIZE);
+ memset(&img, 0, sizeof(img));
/* get input file size */
file_size = lseek(fd_in, 0, SEEK_END);
ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
img.header.b_instruction = cpu_to_le32(img.header.b_instruction);
img.header.length = cpu_to_le32(img.header.length);
+
+ memcpy(img.header.spl_signature, SPL_SIGNATURE, 3); /* "sunxi" marker */
+ img.header.spl_signature[3] = SPL_HEADER_VERSION;
+
gen_check_sum(&img.header);
count = write(fd_out, &img, le32_to_cpu(img.header.length));
# (https://www.kernel.org/pub/tools/crosstool/files/bin/), except the followings:
# arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
# blackfin: http://sourceforge.net/projects/adi-toolchain/files/
-# nds32: http://osdk.andestech.com/packages/
+# nds32: http://osdk.andestech.com/packages/nds32le-linux-glibc-v1.tgz
# nios2: https://sourcery.mentor.com/GNUToolchain/subscription42545
# sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu
CROSS_COMPILE = {
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <endian.h>
#include <fcntl.h>
#include <sys/stat.h>
#include <sys/types.h>
cb = (struct mx28_sd_config_block *)buf;
- cb->signature = 0x00112233;
- cb->primary_boot_tag = 0x1;
- cb->secondary_boot_tag = 0x1;
- cb->num_copies = 1;
- cb->drv_info[0].chip_num = 0x0;
- cb->drv_info[0].drive_type = 0x0;
- cb->drv_info[0].tag = 0x1;
- cb->drv_info[0].first_sector_number = sd_sector + 4;
- cb->drv_info[0].sector_count = (size - 4) / 512;
+ cb->signature = htole32(0x00112233);
+ cb->primary_boot_tag = htole32(0x1);
+ cb->secondary_boot_tag = htole32(0x1);
+ cb->num_copies = htole32(1);
+ cb->drv_info[0].chip_num = htole32(0x0);
+ cb->drv_info[0].drive_type = htole32(0x0);
+ cb->drv_info[0].tag = htole32(0x1);
+ cb->drv_info[0].first_sector_number = htole32(sd_sector + 4);
+ cb->drv_info[0].sector_count = htole32((size - 4) / 512);
wr_size = write(outfd, buf, size);
if (wr_size != size) {
projects / u-boot / commitdiff