- env:
- BUILDMAN="denx"
- env:
- - JOB="Freescale ARM"
- BUILDMAN="freescale -x powerpc,m68k"
+ - JOB="Freescale ARM32"
+ BUILDMAN="freescale -x powerpc,m68k,aarch64"
+ - env:
+ - JOB="Freescale AArch64"
+ BUILDMAN="freescale -x powerpc,m68k,armv7,arm9,arm11"
- env:
- JOB="i.MX (non-Freescale)"
BUILDMAN="mx -x freescale"
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
- default y if ARCH_SUNXI
+ default y if ARCH_SUNXI || TEGRA
default y if ARCH_LS2080A
default n
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP
+ select CMD_PXE
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
help
TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
-config ARCH_FIXUP_FDT
- bool "Enable arch_fixup_fdt() call"
- depends on ARM || MIPS
+config ARCH_FIXUP_FDT_MEMORY
+ bool "Enable arch_fixup_memory_banks() call"
default y
help
Enable FDT memory map syncup before OS boot. This feature can be
quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
+cfg: u-boot.cfg
+
all: $(ALL-y)
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "===================== WARNING ======================"
@echo ' cscope - Generate cscope index'
@echo ' ubootrelease - Output the release version string (use with make -s)'
@echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
+ @echo " cfg - Don't build, just create the .cfg files"
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'
int max_dev;
int enum_started;
int enum_ended;
- int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
+ int type; /* "external" type: DT_STOR_{IDE,USB,etc} */
char *name;
};
else
found = 1;
- /* provide hint if there are more devices in
- * this group to enumerate */
+ /*
+ * provide hint if there are more devices in
+ * this group to enumerate
+ */
if (1 < specs[type].max_dev)
*more = 1;
for (i = 0; i < specs[type].max_dev; i++)
if (di->cookie ==
(void *)blk_get_dev(specs[type].name, i)) {
- /* previous cookie found -- advance to the
- * next device, if possible */
+ /*
+ * previous cookie found -- advance to the
+ * next device, if possible
+ */
if (++i >= specs[type].max_dev) {
/* out of range, no more to enum */
else
found = 1;
- /* provide hint if there are more devices in
- * this group to enumerate */
+ /*
+ * provide hint if there are more devices in
+ * this group to enumerate
+ */
if ((i + 1) < specs[type].max_dev)
*more = 1;
}
-/*
- * returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc
- */
+/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
+
static int dev_stor_type(struct blk_desc *dd)
{
int i, j;
}
-/*
- * returns: 0/1 whether cookie points to some device in this group
- */
+/* returns: 0/1 whether cookie points to some device in this group */
+
static int dev_is_stor(int type, struct device_info *di)
{
return (dev_stor_type(di->cookie) == type) ? 1 : 0;
*/
if (di->cookie == NULL) {
-
debugf("group%d - enum restart\n", type);
/*
specs[type].enum_started = 1;
} else if (dev_is_stor(type, di)) {
-
debugf("group%d - enum continued for the next device\n", type);
if (specs[type].enum_ended) {
found = dev_stor_get(type, 0, &more, di);
} else {
-
if (specs[type].enum_ended) {
debugf("group %d - already enumerated, skipping\n", type);
return 0;
/*
* 2b. If enumerating devices in this group did not
* happen before, it means the cookie pointed to a
- * device frome some other group (another storage
+ * device from some other group (another storage
* group, or network); in this case try to take the
* first available device from our group
*/
if (found)
debugf("device found, returning cookie 0x%08x\n",
- (u_int32_t)di->cookie);
+ (u_int32_t)di->cookie);
else
debugf("no device found\n");
{
int i;
- /*
- * check: ide, usb, scsi, mmc
- */
+ /* check: ide, usb, scsi, mmc */
for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
if (dev_enum_stor(i, di))
return 1;
lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
}
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
static int cleanup_before_linux(void)
{
disable_interrupts();
bool "Support edb93xx"
select CPU_ARM920T
-config TARGET_VCMA9
- bool "Support VCMA9"
- select CPU_ARM920T
-
-config TARGET_SMDK2410
- bool "Support smdk2410"
- select CPU_ARM920T
-
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
+config TARGET_TS4600
+ bool "Support TS4600"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
source "board/hisilicon/hikey/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
-source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
+source "board/technologic/ts4600/Kconfig"
source "board/technologic/ts4800/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
bool
select MX6UL
+config MX6_DDRCAL
+ bool "Include dynamic DDR calibration routines"
+ depends on SPL
+ default n
+ help
+ Say "Y" if your board uses dynamic (per-boot) DDR calibration.
+ If unsure, say N.
+
choice
prompt "MX6 board select"
optional
bool "udoo"
select SUPPORT_SPL
+config TARGET_UDOO_NEO
+ bool "UDOO Neo"
+ select SUPPORT_SPL
+
+config TARGET_SAMTEC_VINING_2000
+ bool "samtec VIN|ING 2000"
+ select MX6SX
+ select DM
+ select DM_THERMAL
+
config TARGET_WANDBOARD
bool "wandboard"
select SUPPORT_SPL
source "board/phytec/pcm058/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/udoo/Kconfig"
+source "board/udoo/neo/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
writel(reg, &anatop->pll_enet);
#ifdef CONFIG_MX6SX
+ /* Disable enet system clcok before switching clock parent */
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+
/*
* Set enet ahb clock to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
}
#endif
+#ifndef CONFIG_SYS_NO_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR6);
+ if (enable)
+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
/***************************************************/
U_BOOT_CMD(
#include <asm/types.h>
#include <wait_bit.h>
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-
+#if defined(CONFIG_MX6_DDRCAL)
static void reset_read_data_fifos(void)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
writel(val_ctrl, reg_ctrl);
}
-int mmdc_do_write_level_calibration(void)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
u32 esdmisc_val, zq_val;
u32 errors = 0;
- u32 ldectrl[4];
+ u32 ldectrl[4] = {0};
u32 ddr_mr1 = 0x4;
+ u32 rwalat_max;
/*
* Stash old values in case calibration fails,
*/
ldectrl[0] = readl(&mmdc0->mpwldectrl0);
ldectrl[1] = readl(&mmdc0->mpwldectrl1);
- ldectrl[2] = readl(&mmdc1->mpwldectrl0);
- ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ ldectrl[2] = readl(&mmdc1->mpwldectrl0);
+ ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+ }
/* disable DDR logic power down timer */
clrbits_le32(&mmdc0->mdpdc, 0xff00);
writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
/* 3. increase walat and ralat to maximum */
- setbits_le32(&mmdc0->mdmisc,
- (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
- setbits_le32(&mmdc1->mdmisc,
- (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+ rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
+ setbits_le32(&mmdc0->mdmisc, rwalat_max);
+ if (sysinfo->dsize == 2)
+ setbits_le32(&mmdc1->mdmisc, rwalat_max);
/*
* 4 & 5. Configure the external DDR device to enter write-leveling
* mode through Load Mode Register command.
*/
if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
errors |= 1;
- if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
- errors |= 2;
+ if (sysinfo->dsize == 2)
+ if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
+ errors |= 2;
debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
/* check to see if cal failed */
if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
(readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
- (readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
- (readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
+ ((sysinfo->dsize < 2) ||
+ ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
+ (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
writel(ldectrl[0], &mmdc0->mpwldectrl0);
writel(ldectrl[1], &mmdc0->mpwldectrl1);
- writel(ldectrl[2], &mmdc1->mpwldectrl0);
- writel(ldectrl[3], &mmdc1->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ writel(ldectrl[2], &mmdc1->mpwldectrl0);
+ writel(ldectrl[3], &mmdc1->mpwldectrl1);
+ }
errors |= 4;
}
readl(&mmdc0->mpwldectrl0));
debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
readl(&mmdc0->mpwldectrl1));
- debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
- readl(&mmdc1->mpwldectrl0));
- debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
- readl(&mmdc1->mpwldectrl1));
+ if (sysinfo->dsize == 2) {
+ debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl0));
+ debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ readl(&mmdc1->mpwldectrl1));
+ }
/* We must force a readback of these values, to get them to stick */
readl(&mmdc0->mpwldectrl0);
readl(&mmdc0->mpwldectrl1);
- readl(&mmdc1->mpwldectrl0);
- readl(&mmdc1->mpwldectrl1);
+ if (sysinfo->dsize == 2) {
+ readl(&mmdc1->mpwldectrl0);
+ readl(&mmdc1->mpwldectrl1);
+ }
/* enable DDR logic power down timer: */
setbits_le32(&mmdc0->mdpdc, 0x00005500);
return errors;
}
-int mmdc_do_dqs_calibration(void)
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
bool cs0_enable_initial;
bool cs1_enable_initial;
u32 esdmisc_val;
- u32 bus_size;
u32 temp_ref;
u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
u32 errors = 0;
cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
- /* Check to see what the data bus size is */
- bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
- debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
-
precharge_all(cs0_enable, cs1_enable);
/* Write the pre-defined value into MPPDCMPR1 */
* Both PHYs for x64 configuration, if x32, do only PHY0.
*/
writel(initdelay, &mmdc0->mprddlctl);
- if (bus_size == 0x2)
+ if (sysinfo->dsize == 0x2)
writel(initdelay, &mmdc1->mprddlctl);
/* Force a measurment, for previous delay setup to take effect. */
- force_delay_measurement(bus_size);
+ force_delay_measurement(sysinfo->dsize);
/*
* ***************************
* 16 before comparing read data.
*/
setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+ if (sysinfo->dsize == 2)
+ setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
/* Set bit 28 to start automatic read DQS gating calibration */
setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
errors |= 1;
- if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
+ if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
errors |= 2;
+ /* now disable mpdgctrl0[DG_CMP_CYC] */
+ clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+ if (sysinfo->dsize == 2)
+ clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
+
/*
* DQS gating absolute offset should be modified from
* reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
&mmdc0->mpdgctrl0);
modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
&mmdc0->mpdgctrl1);
- if (bus_size == 0x2) {
+ if (sysinfo->dsize == 0x2) {
modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
&mmdc1->mpdgctrl0);
modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
errors |= 4;
- if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
+ if ((sysinfo->dsize == 0x2) &&
+ (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
errors |= 8;
debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
* Both PHYs for x64 configuration, if x32, do only PHY0.
*/
writel(initdelay, &mmdc0->mpwrdlctl);
- if (bus_size == 0x2)
+ if (sysinfo->dsize == 0x2)
writel(initdelay, &mmdc1->mpwrdlctl);
/*
* XXX This isn't in the manual. Force a measurement,
* for previous delay setup to effect.
*/
- force_delay_measurement(bus_size);
+ force_delay_measurement(sysinfo->dsize);
/*
* 9. 10. Start the automatic write calibration process
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
errors |= 16;
- if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
+ if ((sysinfo->dsize == 0x2) &&
+ (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
errors |= 32;
debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
debug("Read DQS gating calibration:\n");
debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
- debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
- debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+ if (sysinfo->dsize == 2) {
+ debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
+ debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+ }
debug("Read calibration:\n");
debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
- debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
+ if (sysinfo->dsize == 2)
+ debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
debug("Write calibration:\n");
debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
- debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
+ if (sysinfo->dsize == 2)
+ debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
/*
* Registers below are for debugging purposes. These print out
debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
- debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
- debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
- debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
- debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+ if (sysinfo->dsize == 2) {
+ debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
+ debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
+ debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
+ debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+ }
debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
mdelay(1);
}
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+ struct mx6_mmdc_calibration *calib)
+{
+ struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
+ calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
+ calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
+ calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
+ calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
+ calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
+
+ if (sysinfo->dsize == 2) {
+ calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
+ calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
+ calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
+ calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
+ calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
+ calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
+ }
+}
+
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const void *ddr_cfg)
writel(reg, &mxc_ccm->ccdr);
}
+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
+
static void init_bandgap(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
/*
* Ensure the bandgap has stabilized.
*/
*/
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
/*
- * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
- * VBGADJ bits to 2b'110 to adjust it.
+ * On i.MX6ULL,we need to set VBGADJ bits according to the
+ * REFTOP_TRIM[3:0] in fuse table
+ * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
+ * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
+ * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
+ * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
+ * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
+ * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
+ * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
+ * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
*/
- if (is_mx6ull())
- writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
-}
+ if (is_mx6ull()) {
+ val = readl(&fuse->mem0);
+ val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
+ val &= 0x7;
+ writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+ &anatop->ana_misc0_set);
+ }
+}
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
default 0x5 if SD_MODE1
default 0x6 if EMMC_MODE
default 0x7 if USB_MODE
+ default 0xa if SW_USBHOST_MODE
+ default 0xb if SW_SATA_MODE
choice
prompt "Boot mode"
- depends on ZYNQMP_ALT_BOOTMODE_ENABLED
+ depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
default JTAG
config JTAG_MODE
config USB_MODE
bool "USB"
+config SW_USBHOST_MODE
+ bool "SW USBHOST_MODE"
+
+config SW_SATA_MODE
+ bool "SW SATA_MODE"
+
endchoice
endif
#ifdef CONFIG_SPL_DFU_SUPPORT
case USB_MODE:
return BOOT_DEVICE_DFU;
+#endif
+#ifdef CONFIG_SPL_SATA_SUPPORT
+ case SW_SATA_MODE:
+ return BOOT_DEVICE_SATA;
#endif
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
- dra72-evm-revc.dtb
+ dra72-evm-revc.dtb dra71-evm.dtb
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
- am572x-idk.dtb
+ am57xx-beagle-x15-revb1.dtb \
+ am572x-idk.dtb \
+ am571x-idk.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \
--- /dev/null
+/*
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-idk-common.dtsi"
+
+/ {
+ model = "TI AM5718 IDK";
+ compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ cpu0-led {
+ label = "status0:red:cpu0";
+ gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "cpu0";
+ };
+
+ usr0-led {
+ label = "status0:green:usr";
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat-led {
+ label = "status0:blue:heartbeat";
+ gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ usr1-led {
+ label = "status1:red:usr";
+ gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ usr2-led {
+ label = "status1:green:usr";
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ mmc0-led {
+ label = "status1:blue:mmc0";
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
- chosen {
- stdout-path = &uart3;
- };
-
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
--- /dev/null
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include "am57xx-commercial-grade.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ rtc0 = &mcp_rtc;
+ rtc1 = &tps659038_rtc;
+ rtc2 = &rtc;
+ display0 = &hdmi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ vdd_3v3: fixedregulator-vdd_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ vin-supply = <®en1>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd_fixed";
+ vin-supply = <&vdd_3v3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ /* TPS51200 */
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ vin-supply = <&smps3_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "beagle-x15:usr0";
+ gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beagle-x15:usr1";
+ gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beagle-x15:usr2";
+ gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beagle-x15:usr3";
+ gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ default-state = "off";
+ };
+ };
+
+ gpio_fan: gpio_fan {
+ /* Based on 5v 500mA AFB02505HHB */
+ compatible = "gpio-fan";
+ gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0>,
+ <13000 1>;
+ #cooling-cells = <2>;
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "BeagleBoard-X15";
+ simple-audio-card,widgets =
+ "Line", "Line Out",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC2L", "Line In",
+ "MIC2R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3104>;
+ clocks = <&clkout2_clk>;
+ };
+ };
+};
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+};
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ regulators {
+ smps12_reg: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_DDR */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ /* VDD_CORE */
+ regulator-name = "smps6";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* SMPS7 unused */
+
+ smps8_reg: smps8 {
+ /* VDD_1V8 */
+ regulator-name = "smps8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* SMPS9 unused */
+
+ ldo1_reg: ldo1 {
+ /* VDD_SD / VDDSHV8 */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: ldo2 {
+ /* VDD_SHV5 */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHYA */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_1V8_PHYB */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: ldo9 {
+ /* VDD_RTC */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ regen1: regen1 {
+ /* VDD_3V3_ON */
+ regulator-name = "regen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659038_rtc: tps659038_rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&tps659038>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+
+ tps659038_pwr_button: tps659038_pwr_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <12>;
+ };
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ extcon_usb2: tps659038_usb {
+ compatible = "ti,palmas-usb-vid";
+ ti,enable-vbus-detection;
+ vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ };
+
+ tmp102: tmp102@48 {
+ compatible = "ti,tmp102";
+ reg = <0x48>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tlv320aic3104: tlv320aic3104@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3104";
+ reg = <0x18>;
+ assigned-clocks = <&clkoutmux2_clk_mux>;
+ assigned-clock-parents = <&sys_clk2_dclk_div>;
+
+ status = "okay";
+ adc-settle-ms = <40>;
+
+ AVDD-supply = <&vdd_3v3>;
+ IOVDD-supply = <&vdd_3v3>;
+ DRVDD-supply = <&vdd_3v3>;
+ DVDD-supply = <&aic_dvdd>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "at,24c32";
+ reg = <0x50>;
+ };
+};
+
+&i2c3 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ mcp_rtc: rtc@6f {
+ compatible = "microchip,mcp7941x";
+ reg = <0x6f>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <&dra7_pmx_core 0x424>;
+ interrupt-names = "irq", "wakeup";
+
+ vcc-supply = <&vdd_3v3>;
+ wakeup-source;
+ };
+};
+
+&gpio7 {
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&cpu0 {
+ cpu0-supply = <&smps12_reg>;
+ voltage-tolerance = <1>;
+};
+
+&uart3 {
+ status = "okay";
+ interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&dra7_pmx_core 0x3f8>;
+};
+
+&mac {
+ status = "okay";
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&mmc1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+};
+
+&mmc2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&vdd_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+ cap-mmc-dual-data-rate;
+};
+
+&sata {
+ status = "okay";
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ dr_mode = "host";
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&usb2 {
+ /*
+ * Stand alone usage is peripheral only.
+ * However, with some resistor modifications
+ * this port can be used via expansion connectors
+ * as "host" or "dual-role". If so, provide
+ * the necessary dr_mode override in the expansion
+ * board's DT.
+ */
+ dr_mode = "peripheral";
+};
+
+&cpu_trips {
+ cpu_alert1: cpu_alert1 {
+ temperature = <50000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+};
+
+&cpu_cooling_maps {
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+};
+
+&thermal_zones {
+ board_thermal: board_thermal {
+ polling-delay-passive = <1250>; /* milliseconds */
+ polling-delay = <1500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&tmp102 0>;
+
+ board_trips: trips {
+ board_alert0: board_alert {
+ temperature = <40000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+
+ board_crit: board_crit {
+ temperature = <105000>; /* millicelsius */
+ hysteresis = <0>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ board_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&board_alert0>;
+ cooling-device =
+ <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldoln_reg>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo4_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&pcie1 {
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&sys_clkin2>;
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am57xx-beagle-x15-common.dtsi"
+
+/ {
+ model = "TI AM5728 BeagleBoard-X15 rev B1";
+};
+
+&tpd12s015 {
+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
+ <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+};
+
+&mmc1 {
+ vmmc-supply = <&vdd_3v3>;
+ vmmc-aux-supply = <&ldo1_reg>;
+};
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-/dts-v1/;
-#include "dra74x.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "am57xx-beagle-x15-common.dtsi"
/ {
+ /* NOTE: This describes the "original" pre-production A2 revision */
model = "TI AM5728 BeagleBoard-X15";
- compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
-
- chosen {
- stdout-path = &uart3;
- };
-
- aliases {
- rtc0 = &mcp_rtc;
- rtc1 = &tps659038_rtc;
- rtc2 = &rtc;
- display0 = &hdmi0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- vdd_3v3: fixedregulator-vdd_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_3v3";
- vin-supply = <®en1>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vtt_fixed: fixedregulator-vtt {
- /* TPS51200 */
- compatible = "regulator-fixed";
- regulator-name = "vtt_fixed";
- vin-supply = <&smps3_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_default>;
-
- led@0 {
- label = "beagle-x15:usr0";
- gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led@1 {
- label = "beagle-x15:usr1";
- gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "cpu0";
- default-state = "off";
- };
-
- led@2 {
- label = "beagle-x15:usr2";
- gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led@3 {
- label = "beagle-x15:usr3";
- gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ide-disk";
- default-state = "off";
- };
- };
-
- gpio_fan: gpio_fan {
- /* Based on 5v 500mA AFB02505HHB */
- compatible = "gpio-fan";
- gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0>,
- <13000 1>;
- #cooling-cells = <2>;
- };
-
- extcon_usb1: extcon_usb1 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&extcon_usb1_pins>;
- };
-
- extcon_usb2: extcon_usb2 {
- compatible = "linux,extcon-usb-gpio";
- id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&extcon_usb2_pins>;
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- label = "hdmi";
-
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tpd12s015_out>;
- };
- };
- };
-
- tpd12s015: encoder {
- compatible = "ti,tpd12s015";
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
- gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
- <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
- <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tpd12s015_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tpd12s015_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-};
-
-&dra7_pmx_core {
- leds_pins_default: leds_pins_default {
- pinctrl-single,pins = <
- 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
- 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
- 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
- 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
- >;
- };
-
- i2c1_pins_default: i2c1_pins_default {
- pinctrl-single,pins = <
- 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
- 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
- >;
- };
-
- hdmi_pins: pinmux_hdmi_pins {
- pinctrl-single,pins = <
- 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
- 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
- >;
- };
-
- i2c3_pins_default: i2c3_pins_default {
- pinctrl-single,pins = <
- 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
- 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
- >;
- };
-
- uart3_pins_default: uart3_pins_default {
- pinctrl-single,pins = <
- 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
- 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
- >;
- };
-
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-
- cpsw_pins_default: cpsw_pins_default {
- pinctrl-single,pins = <
- /* Slave 1 */
- 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
- 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
- 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
- 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
- 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
- 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
- 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
- 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
- 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
- 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
- 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
- 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
-
- /* Slave 2 */
- 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
- 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
- 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
- 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
- 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
- 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
- 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
- 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
- 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
- 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
- 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
- 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
- >;
-
- };
-
- cpsw_pins_sleep: cpsw_pins_sleep {
- pinctrl-single,pins = <
- /* Slave 1 */
- 0x250 (PIN_INPUT | MUX_MODE15)
- 0x254 (PIN_INPUT | MUX_MODE15)
- 0x258 (PIN_INPUT | MUX_MODE15)
- 0x25c (PIN_INPUT | MUX_MODE15)
- 0x260 (PIN_INPUT | MUX_MODE15)
- 0x264 (PIN_INPUT | MUX_MODE15)
- 0x268 (PIN_INPUT | MUX_MODE15)
- 0x26c (PIN_INPUT | MUX_MODE15)
- 0x270 (PIN_INPUT | MUX_MODE15)
- 0x274 (PIN_INPUT | MUX_MODE15)
- 0x278 (PIN_INPUT | MUX_MODE15)
- 0x27c (PIN_INPUT | MUX_MODE15)
-
- /* Slave 2 */
- 0x198 (PIN_INPUT | MUX_MODE15)
- 0x19c (PIN_INPUT | MUX_MODE15)
- 0x1a0 (PIN_INPUT | MUX_MODE15)
- 0x1a4 (PIN_INPUT | MUX_MODE15)
- 0x1a8 (PIN_INPUT | MUX_MODE15)
- 0x1ac (PIN_INPUT | MUX_MODE15)
- 0x1b0 (PIN_INPUT | MUX_MODE15)
- 0x1b4 (PIN_INPUT | MUX_MODE15)
- 0x1b8 (PIN_INPUT | MUX_MODE15)
- 0x1bc (PIN_INPUT | MUX_MODE15)
- 0x1c0 (PIN_INPUT | MUX_MODE15)
- 0x1c4 (PIN_INPUT | MUX_MODE15)
- >;
- };
-
- davinci_mdio_pins_default: davinci_mdio_pins_default {
- pinctrl-single,pins = <
- /* MDIO */
- 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
- 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
- >;
- };
-
- davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
- pinctrl-single,pins = <
- 0x23c (PIN_INPUT | MUX_MODE15)
- 0x240 (PIN_INPUT | MUX_MODE15)
- >;
- };
-
- tps659038_pins_default: tps659038_pins_default {
- pinctrl-single,pins = <
- 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
- >;
- };
-
- tmp102_pins_default: tmp102_pins_default {
- pinctrl-single,pins = <
- 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
- >;
- };
-
- mcp79410_pins_default: mcp79410_pins_default {
- pinctrl-single,pins = <
- 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
- >;
- };
-
- usb1_pins: pinmux_usb1_pins {
- pinctrl-single,pins = <
- 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
- >;
- };
-
- extcon_usb1_pins: extcon_usb1_pins {
- pinctrl-single,pins = <
- 0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
- >;
- };
-
- extcon_usb2_pins: extcon_usb2_pins {
- pinctrl-single,pins = <
- 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- 0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
- 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
- 0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */
- >;
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_default>;
- clock-frequency = <400000>;
-
- tps659038: tps659038@58 {
- compatible = "ti,tps659038";
- reg = <0x58>;
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&tps659038_pins_default>;
-
- #interrupt-cells = <2>;
- interrupt-controller;
-
- ti,system-power-controller;
-
- tps659038_pmic {
- compatible = "ti,tps659038-pmic";
-
- regulators {
- smps12_reg: smps12 {
- /* VDD_MPU */
- regulator-name = "smps12";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_DDR */
- regulator-name = "smps3";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps45_reg: smps45 {
- /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
- regulator-name = "smps45";
- regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1150000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps6_reg: smps6 {
- /* VDD_CORE */
- regulator-name = "smps6";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1030000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* SMPS7 unused */
-
- smps8_reg: smps8 {
- /* VDD_1V8 */
- regulator-name = "smps8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* SMPS9 unused */
-
- ldo1_reg: ldo1 {
- /* VDD_SD */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-
- ldo2_reg: ldo2 {
- /* VDD_SHV5 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo9_reg: ldo9 {
- /* VDD_RTC */
- regulator-name = "ldo9";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldoln_reg: ldoln {
- /* VDDA_1V8_PLL */
- regulator-name = "ldoln";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldousb_reg: ldousb {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldousb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-
- regen1: regen1 {
- /* VDD_3V3_ON */
- regulator-name = "regen1";
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- tps659038_rtc: tps659038_rtc {
- compatible = "ti,palmas-rtc";
- interrupt-parent = <&tps659038>;
- interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- };
-
- tps659038_pwr_button: tps659038_pwr_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps659038>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- ti,palmas-long-press-seconds = <12>;
- };
-
- tps659038_gpio: tps659038_gpio {
- compatible = "ti,palmas-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
- tmp102: tmp102@48 {
- compatible = "ti,tmp102";
- reg = <0x48>;
- pinctrl-names = "default";
- pinctrl-0 = <&tmp102_pins_default>;
- interrupt-parent = <&gpio7>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- #thermal-sensor-cells = <1>;
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_pins_default>;
- clock-frequency = <400000>;
-
- mcp_rtc: rtc@6f {
- compatible = "microchip,mcp7941x";
- reg = <0x6f>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
-
- pinctrl-names = "default";
- pinctrl-0 = <&mcp79410_pins_default>;
-
- vcc-supply = <&vdd_3v3>;
- wakeup-source;
- };
-};
-
-&gpio7 {
- ti,no-reset-on-init;
- ti,no-idle-on-init;
-};
-
-&cpu0 {
- cpu0-supply = <&smps12_reg>;
- voltage-tolerance = <1>;
-};
-
-&uart3 {
- status = "okay";
- interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
- <&dra7_pmx_core 0x3f8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_default>;
-};
-
-&mac {
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cpsw_pins_default>;
- pinctrl-1 = <&cpsw_pins_sleep>;
- dual_emac;
-};
-
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
};
-&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <2>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <2>;
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_pins_default>;
- pinctrl-1 = <&davinci_mdio_pins_sleep>;
+&tpd12s015 {
+ gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
+ <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
};
&mmc1 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_default>;
-
vmmc-supply = <&ldo1_reg>;
- vmmc_aux-supply = <&vdd_3v3>;
- pbias-supply = <&pbias_mmc_reg>;
- bus-width = <4>;
- cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
-};
-
-&mmc2 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_default>;
-
- vmmc-supply = <&vdd_3v3>;
- bus-width = <8>;
- ti,non-removable;
- cap-mmc-dual-data-rate;
-};
-
-&sata {
- status = "okay";
-};
-
-&usb2_phy1 {
- phy-supply = <&ldousb_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldousb_reg>;
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_pins>;
-};
-
-&omap_dwc3_1 {
- extcon = <&extcon_usb1>;
-};
-
-&omap_dwc3_2 {
- extcon = <&extcon_usb2>;
-};
-
-&usb2 {
- dr_mode = "peripheral";
-};
-
-&cpu_trips {
- cpu_alert1: cpu_alert1 {
- temperature = <50000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
-};
-
-&cpu_cooling_maps {
- map1 {
- trip = <&cpu_alert1>;
- cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-};
-
-&thermal_zones {
- board_thermal: board_thermal {
- polling-delay-passive = <1250>; /* milliseconds */
- polling-delay = <1500>; /* milliseconds */
-
- /* sensor ID */
- thermal-sensors = <&tmp102 0>;
-
- board_trips: trips {
- board_alert0: board_alert {
- temperature = <40000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
-
- board_crit: board_crit {
- temperature = <105000>; /* millicelsius */
- hysteresis = <0>; /* millicelsius */
- type = "critical";
- };
- };
-
- board_cooling_maps: cooling-maps {
- map0 {
- trip = <&board_alert0>;
- cooling-device =
- <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-};
-
-&dss {
- status = "ok";
-
- vdda_video-supply = <&ldoln_reg>;
-};
-
-&hdmi {
- status = "ok";
- vdda-supply = <&ldo3_reg>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pins>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&tpd12s015_in>;
- };
- };
};
--- /dev/null
+&cpu_alert0 {
+ temperature = <80000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <90000>; /* milliCelsius */
+};
* published by the Free Software Foundation.
*/
+#include "am57xx-industrial-grade.dtsi"
+
/ {
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
};
+ chosen {
+ stdout-path = &uart3;
+ };
+
vmain: fixedregulator-vmain {
compatible = "regulator-fixed";
regulator-name = "VMAIN";
tps659038_pmic {
compatible = "ti,tps659038-pmic";
+
+ smps12-in-supply = <&vmain>;
+ smps3-in-supply = <&vmain>;
+ smps45-in-supply = <&vmain>;
+ smps6-in-supply = <&vmain>;
+ smps7-in-supply = <&vmain>;
+ smps8-in-supply = <&vmain>;
+ smps9-in-supply = <&vmain>;
+ ldo1-in-supply = <&vmain>;
+ ldo2-in-supply = <&vmain>;
+ ldo3-in-supply = <&vmain>;
+ ldo4-in-supply = <&vmain>;
+ ldo9-in-supply = <&vmain>;
+ ldoln-in-supply = <&vmain>;
+ ldousb-in-supply = <&vmain>;
+ ldortc-in-supply = <&vmain>;
+
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
- vin-supply = <&vmain>;
regulator-name = "smps12";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
smps3_reg: smps3 {
/* VDD_DDR EMIF1 EMIF2 */
- vin-supply = <&vmain>;
regulator-name = "smps3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
smps45_reg: smps45 {
/* VDD_DSPEVE on AM572 */
/* VDD_IVA + VDD_DSP on AM571 */
- vin-supply = <&vmain>;
regulator-name = "smps45";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
smps6_reg: smps6 {
/* VDD_GPU */
- vin-supply = <&vmain>;
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
smps7_reg: smps7 {
/* VDD_CORE */
- vin-supply = <&vmain>;
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
smps8_reg: smps8 {
/* 5728 - VDD_IVAHD */
/* 5718 - N.C. test point */
- vin-supply = <&vmain>;
regulator-name = "smps8";
};
smps9_reg: smps9 {
/* VDD_3_3D */
- vin-supply = <&vmain>;
regulator-name = "smps9";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
ldo1_reg: ldo1 {
/* VDDSHV8 - VSDMMC */
/* NOTE: on rev 1.3a, data supply */
- vin-supply = <&vmain>;
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
ldo2_reg: ldo2 {
/* VDDSH18V */
- vin-supply = <&vmain>;
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
ldo3_reg: ldo3 {
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
- vin-supply = <&vmain>;
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
ldo4_reg: ldo4 {
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
- vin-supply = <&vmain>;
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
ldo9_reg: ldo9 {
/* VDD_RTC */
- vin-supply = <&vmain>;
regulator-name = "ldo9";
regulator-min-microvolt = <840000>;
regulator-max-microvolt = <1160000>;
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
- vin-supply = <&vmain>;
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
- vin-supply = <&vmain>;
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
ldortc_reg: ldortc {
/* VDDA_RTC */
- vin-supply = <&vmain>;
regulator-name = "ldortc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
spi-max-frequency = <76800000>;
m25p80@0 {
- compatible = "s25fl256s1","spi-flash";
+ compatible = "s25fl256s1", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
--- /dev/null
+&cpu_alert0 {
+ temperature = <90000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <105000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <105000>; /* milliCelsius */
+};
--- /dev/null
+/*
+ * Device Tree Source for DRA7x SoC DSPEVE thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+dspeve_thermal: dspeve_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 3>;
+
+ trips {
+ dspeve_crit: dspeve_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/input/input.h>
/ {
model = "TI DRA742";
tick-timer = &timer2;
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x80000000 0x60000000>; /* 1536 MB */
+ reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
};
evm_3v3_sd: fixedregulator-sd {
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
- mmc2_3v3: fixedregulator-mmc2 {
+ evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
- regulator-name = "mmc2_3v3";
+ regulator-name = "evm_3v3_sw";
+ vin-supply = <&sysen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
+ vin-supply = <&sysen2>;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "dra7:usr1";
+ gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led1 {
+ label = "dra7:usr2";
+ gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led2 {
+ label = "dra7:usr3";
+ gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "dra7:usr4";
+ gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ USER1 {
+ label = "btnUser1";
+ linux,code = <BTN_0>;
+ gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
+ };
+
+ USER2 {
+ label = "btnUser2";
+ linux,code = <BTN_1>;
+ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&dra7_pmx_core {
vtt_pin: pinmux_vtt_pin {
pinctrl-single,pins = <
- 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
+ DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
- 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
- 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
+ DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
+ DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
- 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
- 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
+ DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
+ DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
- 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
- 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
+ DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
+ DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
>;
};
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
- 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
- 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
- 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
- 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
- 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
- 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
+ DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
+ DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
+ DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
+ DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
+ DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
+ DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
>;
};
mcspi2_pins: pinmux_mcspi2_pins {
pinctrl-single,pins = <
- 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
- 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
- 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
+ DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
+ DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+ DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
+ DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
- 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
- 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
- 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
- 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
+ DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
+ DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
- 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
- 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
- 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
- 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
- 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
- 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
- >;
- };
-
- qspi1_pins: pinmux_qspi1_pins {
- pinctrl-single,pins = <
- 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
- 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
- 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
- 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
- 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
- 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
- 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
- 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
- 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
- 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
+ DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
+ DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
- 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+ DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
- 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+ DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
- * SW5.9 (GPMC_WPN) = LOW
- * SW5.1 (NAND_BOOTn) = HIGH */
+ * SW5.1 (NAND_BOOTn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
pinctrl-single,pins = <
- 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
- 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
- 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
- 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
- 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
- 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
- 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
- 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
- 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
- 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
- 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
- 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
- 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
- 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
- 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
- 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
- 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
- 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
- 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
- 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
- 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
- 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
+ DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
+ DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
+ DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
+ DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
+ DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
+ DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
+ DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
+ DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
+ DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
+ DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
+ DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
+ DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
+ DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
+ DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
+ DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
+ DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
+ DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
+ DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+ DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
+ DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+ DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+ DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
- 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
- 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
- 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
- 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
- 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
- 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
- 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
- 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
- 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
- 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
- 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
- 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
+ DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
+ DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
+ DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
+ DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
+ DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
+ DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
+ DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
+ DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
+ DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
+ DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
+ DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
+ DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
/* Slave 2 */
- 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
- 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
- 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
- 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
- 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
- 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
- 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
- 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
- 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
- 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
- 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
- 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
+ DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
+ DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
+ DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
+ DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
+ DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
+ DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
+ DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
+ DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
+ DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
+ DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
+ DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
+ DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 */
- 0x250 (MUX_MODE15)
- 0x254 (MUX_MODE15)
- 0x258 (MUX_MODE15)
- 0x25c (MUX_MODE15)
- 0x260 (MUX_MODE15)
- 0x264 (MUX_MODE15)
- 0x268 (MUX_MODE15)
- 0x26c (MUX_MODE15)
- 0x270 (MUX_MODE15)
- 0x274 (MUX_MODE15)
- 0x278 (MUX_MODE15)
- 0x27c (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
/* Slave 2 */
- 0x198 (MUX_MODE15)
- 0x19c (MUX_MODE15)
- 0x1a0 (MUX_MODE15)
- 0x1a4 (MUX_MODE15)
- 0x1a8 (MUX_MODE15)
- 0x1ac (MUX_MODE15)
- 0x1b0 (MUX_MODE15)
- 0x1b4 (MUX_MODE15)
- 0x1b8 (MUX_MODE15)
- 0x1bc (MUX_MODE15)
- 0x1c0 (MUX_MODE15)
- 0x1c4 (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
- 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
- 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
+ DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
- 0x23c (MUX_MODE15)
- 0x240 (MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
- 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
- 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
- 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
- 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+
+ atl_pins: pinmux_atl_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
+ DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
+ >;
+ };
+
+ mcasp3_pins: pinmux_mcasp3_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
+ DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
+ DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
+ DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
+ >;
+ };
+
+ mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
+ DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
>;
};
};
/* VDD_DSPEVE */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
- regulator-max-microvolt = <1150000>;
+ regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
/* CORE_VDD */
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1060000>;
+ regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
regulator-boot-on;
};
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
+ regulator-allow-bypass;
};
ldoln_reg: ldoln {
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
+
+ /* REGEN1 is unused */
+
+ regen2: regen2 {
+ /* Needed for PMIC internal resources */
+ regulator-name = "regen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* REGEN3 is unused */
+
+ sysen1: sysen1 {
+ /* PMIC_REGEN_3V3 */
+ regulator-name = "sysen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sysen2: sysen2 {
+ /* PMIC_REGEN_DDR */
+ regulator-name = "sysen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
};
};
+ pcf_lcd: gpio@20 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
u-boot,i2c-offset-len = <0>;
};
+ tlv320aic3106: tlv320aic3106@19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
+
+ pcf_hdmi: gpio@26 {
+ compatible = "ti,pcf8575", "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ p1 {
+ /* vin6_sel_s0: high: VIN6, low: audio */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "vin6_sel_s0";
+ };
+ };
};
&i2c3 {
&mmc2 {
status = "okay";
- vmmc-supply = <&mmc2_3v3>;
+ vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
};
&qspi {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <76800000>;
m25p80@0 {
- compatible = "s25fl256s1","spi-flash";
+ compatible = "s25fl256s1", "spi-flash";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x16>;
- ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
+
+&atl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&atl_pins>;
+
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp3_pins>;
+ pinctrl-1 = <&mcasp3_sleep_pins>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ status = "okay";
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for DRA7x SoC IVA thermal
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+iva_thermal: iva_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 4>;
+
+ trips {
+ iva_crit: iva_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
-#include "skeleton.dtsi"
-
#define MAX_SOURCES 400
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48211000 0x1000>,
- <0x48212000 0x1000>,
- <0x48214000 0x2000>,
- <0x48216000 0x2000>;
+ reg = <0x0 0x48211000 0x0 0x1000>,
+ <0x0 0x48212000 0x0 0x1000>,
+ <0x0 0x48214000 0x0 0x2000>,
+ <0x0 0x48216000 0x0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
- reg = <0x48281000 0x1000>;
+ reg = <0x0 0x48281000 0x0 0x1000>;
interrupt-parent = <&gic>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ operating-points = <
+ /* kHz uV */
+ 1000000 1060000
+ 1176000 1160000
+ >;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x0 0x0 0xc0000000>;
ti,hwmods = "l3_main_1", "l3_main_2";
- reg = <0x44000000 0x1000000>,
- <0x45000000 0x1000>;
+ reg = <0x0 0x44000000 0x0 0x1000000>,
+ <0x0 0x45000000 0x0 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
ranges = <0 0x2000 0x2000>;
scm_conf: scm_conf@0 {
- compatible = "syscon";
+ compatible = "syscon", "simple-bus";
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 0x0 0x1400>;
- pbias_regulator: pbias_regulator {
- compatible = "ti,pbias-omap";
+ pbias_regulator: pbias_regulator@e00 {
+ compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
dra7_pmx_core: pinmux@1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
- reg = <0x1400 0x0464>;
+ reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
+
+ scm_conf1: scm_conf@1c04 {
+ compatible = "syscon";
+ reg = <0x1c04 0x0020>;
+ };
+
+ scm_conf_pcie: scm_conf@1c24 {
+ compatible = "syscon";
+ reg = <0x1c24 0x0024>;
+ };
+
+ sdma_xbar: dma-router@b78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xb78 0xfc>;
+ #dma-cells = <1>;
+ dma-requests = <205>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&sdma>;
+ };
+
+ edma_xbar: dma-router@c78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0xc78 0x7c>;
+ #dma-cells = <2>;
+ dma-requests = <204>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&edma>;
+ };
};
cm_core_aon: cm_core_aon@5000 {
prm_clockdomains: clockdomains {
};
};
+
+ scm_wkup: scm_conf@c000 {
+ compatible = "syscon";
+ reg = <0xc000 0x1000>;
+ };
};
axi@0 {
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie@51000000 {
+ pcie1: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ linux,pci-domain = <0>;
ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
- pcie@51000000 {
+ pcie@51800000 {
compatible = "ti,dra7-pcie";
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
#interrupt-cells = <1>;
num-lanes = <1>;
+ linux,pci-domain = <1>;
ti,hwmods = "pcie2";
phys = <&pcie2_phy>;
phy-names = "pcie-phy0";
};
};
+ ocmcram1: ocmcram@40300000 {
+ compatible = "mmio-sram";
+ reg = <0x40300000 0x80000>;
+ ranges = <0x0 0x40300000 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * This is a placeholder for an optional reserved
+ * region for use by secure software. The size
+ * of this region is not known until runtime so it
+ * is set as zero to either be updated to reserve
+ * space or left unchanged to leave all SRAM for use.
+ * On HS parts that that require the reserved region
+ * either the bootloader can update the size to
+ * the required amount or the node can be overridden
+ * from the board dts file for the secure platform.
+ */
+ sram-hs@0 {
+ compatible = "ti,secure-ram";
+ reg = <0x0 0x0>;
+ };
+ };
+
+ /*
+ * NOTE: ocmcram2 and ocmcram3 are not available on all
+ * DRA7xx and AM57xx variants. Confirm availability in
+ * the data manual for the exact part number in use
+ * before enabling these nodes in the board dts file.
+ */
+ ocmcram2: ocmcram@40400000 {
+ status = "disabled";
+ compatible = "mmio-sram";
+ reg = <0x40400000 0x100000>;
+ ranges = <0x0 0x40400000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ ocmcram3: ocmcram@40500000 {
+ status = "disabled";
+ compatible = "mmio-sram";
+ reg = <0x40500000 0x100000>;
+ ranges = <0x0 0x40500000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
#thermal-sensor-cells = <1>;
};
- dra7_ctrl_core: ctrl_core@4a002000 {
+ dsp1_system: dsp_system@40d00000 {
compatible = "syscon";
- reg = <0x4a002000 0x6d0>;
- };
-
- dra7_ctrl_general: tisyscon@4a002e00 {
- compatible = "syscon";
- reg = <0x4a002e00 0x7c>;
+ reg = <0x40d00000 0x100>;
};
sdma: dma-controller@4a056000 {
dma-requests = <127>;
};
+ edma: edma@43300000 {
+ compatible = "ti,edma3-tpcc";
+ ti,hwmods = "tpcc";
+ reg = <0x43300000 0x100000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <20 21>;
+ * for example. Note that these channels need to be
+ * masked in the xbar as well.
+ */
+ };
+
+ edma_tptc0: tptc@43400000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc0";
+ reg = <0x43400000 0x100000>;
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
+
+ edma_tptc1: tptc@43500000 {
+ compatible = "ti,edma3-tptc";
+ ti,hwmods = "tptc1";
+ reg = <0x43500000 0x100000>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
+
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
};
uart1: serial@4806a000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
reg-shift = <2>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 49>, <&sdma 50>;
+ dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
};
uart2: serial@4806c000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 51>, <&sdma 52>;
+ dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
dma-names = "tx", "rx";
};
uart3: serial@48020000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 53>, <&sdma 54>;
+ dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
dma-names = "tx", "rx";
};
uart4: serial@4806e000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 55>, <&sdma 56>;
+ dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
dma-names = "tx", "rx";
};
uart5: serial@48066000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 63>, <&sdma 64>;
+ dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
dma-names = "tx", "rx";
};
uart6: serial@48068000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 79>, <&sdma 80>;
+ dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
dma-names = "tx", "rx";
};
uart7: serial@48420000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
};
uart8: serial@48422000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48422000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
};
uart9: serial@48424000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48424000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
};
uart10: serial@4ae2b000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4ae2b000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
};
+ timer12: timer@4ae20000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae20000 0x80>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer12";
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
+
timer13: timer@48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
- status = "disabled";
};
timer14: timer@4882a000 {
reg = <0x4882a000 0x80>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer14";
- status = "disabled";
};
timer15: timer@4882c000 {
reg = <0x4882c000 0x80>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer15";
- status = "disabled";
};
timer16: timer@4882e000 {
reg = <0x4882e000 0x80>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer16";
- status = "disabled";
};
wdt2: wdt@4ae14000 {
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
- dmas = <&sdma 61>, <&sdma 62>;
+ dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
- dmas = <&sdma 47>, <&sdma 48>;
+ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
dma-names = "tx", "rx";
status = "disabled";
};
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
- dmas = <&sdma 77>, <&sdma 78>;
+ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
dma-names = "tx", "rx";
status = "disabled";
};
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
- dmas = <&sdma 57>, <&sdma 58>;
+ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
dma-names = "tx", "rx";
status = "disabled";
};
+ mmu0_dsp1: mmu@40d01000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x40d01000 0x100>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu0_dsp1";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ status = "disabled";
+ };
+
+ mmu1_dsp1: mmu@40d02000 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x40d02000 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu1_dsp1";
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ status = "disabled";
+ };
+
+ mmu_ipu1: mmu@58882000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x58882000 0x100>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu_ipu1";
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ status = "disabled";
+ };
+
+ mmu_ipu2: mmu@55082000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x55082000 0x100>;
+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu_ipu2";
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ status = "disabled";
+ };
+
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v3";
regulator-name = "abb_mpu";
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
+ dmas = <&sdma_xbar 35>,
+ <&sdma_xbar 36>,
+ <&sdma_xbar 37>,
+ <&sdma_xbar 38>,
+ <&sdma_xbar 39>,
+ <&sdma_xbar 40>,
+ <&sdma_xbar 41>,
+ <&sdma_xbar 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
status = "disabled";
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
+ dmas = <&sdma_xbar 43>,
+ <&sdma_xbar 44>,
+ <&sdma_xbar 45>,
+ <&sdma_xbar 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
- dmas = <&sdma 15>, <&sdma 16>;
+ dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
dma-names = "tx0", "rx0";
status = "disabled";
};
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
+ dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
dma-names = "tx0", "rx0";
status = "disabled";
};
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
reg = <0x4b300000 0x100>,
- <0x5c000000 0x4000000>,
- <0x4a002558 0x4>;
- reg-names = "qspi_base", "qspi_mmap",
- "qspi_ctrlmod";
+ <0x5c000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ syscon-chipselects = <&scm_conf 0x558>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
status = "disabled";
};
- omap_control_sata: control-phy@4a002374 {
- compatible = "ti,control-phy-pipe3";
- reg = <0x4a002374 0x4>;
- reg-names = "power";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- };
-
/* OCP2SCP3 */
ocp2scp@4a090000 {
compatible = "ti,omap-ocp2scp";
<0x4A096400 0x64>, /* phy_tx */
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_sata>;
+ syscon-phy-power = <&scm_conf 0x374>;
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
};
reg = <0x4a094000 0x80>, /* phy_rx */
<0x4a094400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
- ctrl-module = <&omap_control_pcie1phy>;
+ syscon-phy-power = <&scm_conf_pcie 0x1c>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy1_32khz>,
<&optfclk_pciephy1_clk>,
<&optfclk_pciephy1_div_clk>,
- <&optfclk_pciephy_div>;
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
- "div-clk", "phy-div";
+ "div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
};
reg = <0x4a095000 0x80>, /* phy_rx */
<0x4a095400 0x64>; /* phy_tx */
reg-names = "phy_rx", "phy_tx";
- ctrl-module = <&omap_control_pcie2phy>;
+ syscon-phy-power = <&scm_conf_pcie 0x20>;
+ syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
<&optfclk_pciephy2_32khz>,
<&optfclk_pciephy2_clk>,
<&optfclk_pciephy2_div_clk>,
- <&optfclk_pciephy_div>;
+ <&optfclk_pciephy_div>,
+ <&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
"wkupclk", "refclk",
- "div-clk", "phy-div";
+ "div-clk", "phy-div", "sysclk";
#phy-cells = <0>;
status = "disabled";
};
ti,hwmods = "sata";
};
- omap_control_pcie1phy: control-phy@0x4a003c40 {
- compatible = "ti,control-phy-pcie";
- reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
- reg-names = "power", "control_sma", "pcie_pcs";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- };
-
- omap_control_pcie2phy: control-pcie@0x4a003c44 {
- compatible = "ti,control-phy-pcie";
- reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
- reg-names = "power", "control_sma", "pcie_pcs";
- clocks = <&sys_clkin1>;
- clock-names = "sysclk";
- status = "disabled";
- };
-
rtc: rtc@48838000 {
compatible = "ti,am3352-rtc";
reg = <0x48838000 0x100>;
clocks = <&sys_32k_ck>;
};
- omap_control_usb2phy1: control-phy@4a002300 {
- compatible = "ti,control-phy-usb2";
- reg = <0x4a002300 0x4>;
- reg-names = "power";
- };
-
- omap_control_usb3phy1: control-phy@4a002370 {
- compatible = "ti,control-phy-pipe3";
- reg = <0x4a002370 0x4>;
- reg-names = "power";
- };
-
- omap_control_usb2phy2: control-phy@0x4a002e74 {
- compatible = "ti,control-phy-usb2-dra7";
- reg = <0x4a002e74 0x4>;
- reg-names = "power";
- };
-
/* OCP2SCP1 */
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp";
ti,hwmods = "ocp2scp1";
usb2_phy1: phy@4a084000 {
- compatible = "ti,omap-usb2";
+ compatible = "ti,dra7x-usb2", "ti,omap-usb2";
reg = <0x4a084000 0x400>;
- ctrl-module = <&omap_control_usb2phy1>;
+ syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
<&usb_otg_ss1_refclk960m>;
clock-names = "wkupclk",
};
usb2_phy2: phy@4a085000 {
- compatible = "ti,omap-usb2";
+ compatible = "ti,dra7x-usb2-phy2",
+ "ti,omap-usb2";
reg = <0x4a085000 0x400>;
- ctrl-module = <&omap_control_usb2phy2>;
+ syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
<&usb_otg_ss2_refclk960m>;
clock-names = "wkupclk",
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_usb3phy1>;
+ syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
<&usb_otg_ss1_refclk960m>;
usb1: usb@48890000 {
compatible = "snps,dwc3";
reg = <0x48890000 0x17000>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
- tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
usb2: usb@488d0000 {
compatible = "snps,dwc3";
reg = <0x488d0000 0x17000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
- tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
usb3: usb@48910000 {
compatible = "snps,dwc3";
reg = <0x48910000 0x17000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- tx-fifo-resize;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
maximum-speed = "high-speed";
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
ti,hwmods = "gpmc";
reg = <0x50000000 0x37c>; /* device IO registers */
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 4 0>;
+ dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
status = "disabled";
};
status = "disabled";
};
+ mcasp1: mcasp@48460000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp1";
+ reg = <0x48460000 0x2000>,
+ <0x45800000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
+ <&mcasp1_ahclkr_mux>;
+ clock-names = "fck", "ahclkx", "ahclkr";
+ status = "disabled";
+ };
+
+ mcasp2: mcasp@48464000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp2";
+ reg = <0x48464000 0x2000>,
+ <0x45c00000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
+ <&mcasp2_ahclkr_mux>;
+ clock-names = "fck", "ahclkx", "ahclkr";
+ status = "disabled";
+ };
+
+ mcasp3: mcasp@48468000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp3";
+ reg = <0x48468000 0x2000>,
+ <0x46000000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp4: mcasp@4846c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp4";
+ reg = <0x4846c000 0x2000>,
+ <0x48436000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp5: mcasp@48470000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp5";
+ reg = <0x48470000 0x2000>,
+ <0x4843a000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp6: mcasp@48474000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp6";
+ reg = <0x48474000 0x2000>,
+ <0x4844c000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp7: mcasp@48478000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp7";
+ reg = <0x48478000 0x2000>,
+ <0x48450000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp8: mcasp@4847c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp8";
+ reg = <0x4847c000 0x2000>,
+ <0x48454000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
};
mac: ethernet@48484000 {
- compatible = "ti,cpsw";
+ compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
- clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+ clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
- rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
+ cpts_clock_mult = <0x784CFE14>;
cpts_clock_shift = <29>;
syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
#size-cells = <1>;
+
+ /*
+ * Do not allow gating of cpsw clock as workaround
+ * for errata i877. Keeping internal clock disabled
+ * causes the device switching characteristics
+ * to degrade over time and eventually fail to meet
+ * the data manual delay time/skew specs.
+ */
+ ti,no-idle;
+
/*
* rx_thresh_pend
* rx_pend
status = "disabled";
davinci_mdio: mdio@48485000 {
- compatible = "ti,davinci_mdio";
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
clock-names = "fck", "sys_clk";
};
};
+
+ epwmss0: epwmss@4843e000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm0: pwm@4843e200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: ecap@4843e100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x4843e100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss@48440000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm1: pwm@48440200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap1: ecap@48440100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48440100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss@48442000 {
+ compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm2: pwm@48442200 {
+ compatible = "ti,dra746-ehrpwm",
+ "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap2: ecap@48442100 {
+ compatible = "ti,dra746-ecap",
+ "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48442100 0x80>;
+ clocks = <&l4_root_clk_div>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+
+ aes1: aes@4b500000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes1";
+ reg = <0x4b500000 0xa0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ aes2: aes@4b700000 {
+ compatible = "ti,omap4-aes";
+ ti,hwmods = "aes2";
+ reg = <0x4b700000 0xa0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ des: des@480a5000 {
+ compatible = "ti,omap4-des";
+ ti,hwmods = "des";
+ reg = <0x480a5000 0xa0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ sham: sham@53100000 {
+ compatible = "ti,omap5-sham";
+ ti,hwmods = "sham";
+ reg = <0x4b101000 0x300>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 119 0>;
+ dma-names = "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+
+ rng: rng@48090000 {
+ compatible = "ti,omap4-rng";
+ ti,hwmods = "rng";
+ reg = <0x48090000 0x2000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
thermal_zones: thermal-zones {
#include "omap4-cpu-thermal.dtsi"
#include "omap5-gpu-thermal.dtsi"
#include "omap5-core-thermal.dtsi"
+ #include "dra7-dspeve-thermal.dtsi"
+ #include "dra7-iva-thermal.dtsi"
};
};
--- /dev/null
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dra72-evm-common.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
+ model = "TI DRA718 EVM";
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
+ };
+
+ vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "vddshv8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ vin-supply = <&evm_5v0>;
+
+ gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0
+ 3000000 0x1>;
+ };
+
+ poweroff: gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ lp8733: lp8733@60 {
+ compatible = "ti,lp8733";
+ reg = <0x60>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&evm_5v0>;
+ ldo1-in-supply =<&evm_5v0>;
+
+ lp8733_regulators: regulators {
+ lp8733_buck0_reg: buck0 {
+ /* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
+ regulator-name = "lp8733-buck0";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8733_buck1_reg: buck1 {
+ /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
+ regulator-name = "lp8733-buck1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8733_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
+ regulator-name = "lp8733-ldo0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ lp8733_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
+ regulator-name = "lp8733-ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ lp8732: lp8732@61 {
+ compatible = "ti,lp8732";
+ reg = <0x61>;
+
+ buck0-in-supply =<&vsys_3v3>;
+ buck1-in-supply =<&vsys_3v3>;
+ ldo0-in-supply =<&vsys_3v3>;
+ ldo1-in-supply =<&vsys_3v3>;
+
+ lp8732_regulators: regulators {
+ lp8732_buck0_reg: buck0 {
+ /* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
+ regulator-name = "lp8732-buck0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8732_buck1_reg: buck1 {
+ /* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
+ regulator-name = "lp8732-buck1";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
+ regulator-name = "lp8732-ldo0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8732_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
+ regulator-name = "lp8732-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio7>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&pcf_hdmi {
+ p0 {
+ /*
+ * PM_OEn to High: Disable routing I2C3 to PM_I2C
+ * With this PM_SEL(p3) should not matter
+ */
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "pm_oe_n";
+ };
+};
+
+&mmc1 {
+ vmmc_aux-supply = <&vpo_sd_1v8_3v3>;
+};
+
+&mac {
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
+ <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
+ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
+ dual_emac;
+};
+
+&cpsw_emac0 {
+ phy-handle = <&dp83867_0>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy-handle = <&dp83867_1>;
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ dp83867_0: ethernet-phy@2 {
+ reg = <2>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+
+ dp83867_1: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ ti,impedance-control = <0x1f>;
+ };
+};
+
+/* No Sata on this device */
+&sata_phy {
+ status = "disabled";
+};
+
+&sata {
+ status = "disabled";
+};
+
+/* No RTC on this device */
+&rtc {
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&lp8733_ldo1_reg>;
+};
+
+&dss {
+ /* Supplied by VDA_1V8_PLL */
+ vdda_video-supply = <&lp8732_ldo0_reg>;
+};
+
+&hdmi {
+ /* Supplied by VDA_1V8_PHY */
+ vdda_video-supply = <&lp8732_ldo1_reg>;
+};
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+ aliases {
+ display0 = &hdmi0;
+ };
+
chosen {
stdout-path = &uart1;
tick-timer = &timer2;
};
- aliases {
- display0 = &hdmi0;
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_5v0: fixedregulator-evm5v0 {
+ /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
};
- evm_3v3: fixedregulator-evm_3v3 {
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
+ /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ evm_3v3_sw: fixedregulator-evm_3v3 {
+ /* TPS22965DSG */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ aic_dvdd: fixedregulator-aic_dvdd {
+ /* TPS77018DBVT */
+ compatible = "regulator-fixed";
+ regulator-name = "aic_dvdd";
+ vin-supply = <&evm_3v3_sw>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ evm_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_3v3_sw>;
+ enable-active-high;
+ gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_usb1 {
};
};
};
+
+ sound0: sound0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "DRA7xx-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out",
+ "Microphone", "Mic Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "Line Out", "LLOUT",
+ "Line Out", "RLOUT",
+ "MIC3L", "Mic Jack",
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ sound0_master: simple-audio-card,cpu {
+ sound-dai = <&mcasp3>;
+ system-clock-frequency = <5644800>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&atl_clkin2_ck>;
+ };
+ };
};
&dra7_pmx_core {
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
- 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
- 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
- 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
- 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
- 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
- 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
};
status = "okay";
clock-frequency = <400000>;
- tps65917: tps65917@58 {
- compatible = "ti,tps65917";
- reg = <0x58>;
-
- interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
- interrupt-controller;
- #interrupt-cells = <2>;
-
- ti,system-power-controller;
-
- tps65917_pmic {
- compatible = "ti,tps65917-pmic";
-
- tps65917_regulators: regulators {
- smps1_reg: smps1 {
- /* VDD_MPU */
- regulator-name = "smps1";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps2_reg: smps2 {
- /* VDD_CORE */
- regulator-name = "smps2";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1060000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps3_reg: smps3 {
- /* VDD_GPU IVA DSPEVE */
- regulator-name = "smps3";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1250000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- smps4_reg: smps4 {
- /* VDDS1V8 */
- regulator-name = "smps4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps5_reg: smps5 {
- /* VDD_DDR */
- regulator-name = "smps5";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: ldo1 {
- /* LDO1_OUT --> SDIO */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-allow-bypass;
- };
-
- ldo3_reg: ldo3 {
- /* VDDA_1V8_PHY */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PLL */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4_reg: ldo4 {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldo4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
- };
- };
-
- tps65917_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&tps65917>;
- interrupts = <1 IRQ_TYPE_NONE>;
- wakeup-source;
- ti,palmas-long-press-seconds = <6>;
- };
- };
-
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
u-boot,i2c-offset-len = <0>;
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ tlv320aic3106: tlv320aic3106@19 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x19>;
+ adc-settle-ms = <40>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ status = "okay";
+
+ /* Regulators */
+ AVDD-supply = <&evm_3v3_sw>;
+ IOVDD-supply = <&evm_3v3_sw>;
+ DRVDD-supply = <&evm_3v3_sw>;
+ DVDD-supply = <&aic_dvdd>;
+ };
};
&i2c5 {
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
- compatible = "nxp,pcf8575";
+ compatible = "ti,pcf8575", "nxp,pcf8575";
u-boot,i2c-offset-len = <0>;
reg = <0x26>;
gpio-controller;
};
&gpmc {
- /*
- * For the existing IOdelay configuration via U-Boot we don't
- * support NAND on dra72-evm. Keep it disabled. Enabling it
- * requires a different configuration by U-Boot.
- */
- status = "disabled";
+ status = "okay";
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* device IO registers */
+ reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
};
};
-&usb2_phy1 {
- phy-supply = <&ldo4_reg>;
-};
-
-&usb2_phy2 {
- phy-supply = <&ldo4_reg>;
-};
-
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
};
&usb1 {
- dr_mode = "otg";
+ dr_mode = "peripheral";
};
&usb2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
- vmmc_aux-supply = <&ldo1_reg>;
+ vmmc-supply = <&evm_3v3_sd>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
- vmmc-supply = <&evm_3v3>;
+ vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
&dcan1 {
status = "ok";
+ pinctrl-names = "default", "sleep", "active";
+ pinctrl-0 = <&dcan1_pins_sleep>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+ pinctrl-2 = <&dcan1_pins_default>;
};
&qspi {
&dss {
status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
};
};
};
+
+&atl {
+ assigned-clocks = <&abe_dpll_sys_clk_mux>,
+ <&atl_gfclk_mux>,
+ <&dpll_abe_ck>,
+ <&dpll_abe_m2x2_ck>,
+ <&atl_clkin2_ck>;
+ assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
+ assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
+
+ status = "okay";
+
+ atl2 {
+ bws = <DRA7_ATL_WS_MCASP2_FSX>;
+ aws = <DRA7_ATL_WS_MCASP3_FSX>;
+ };
+};
+
+&mcasp3 {
+ #sound-dai-cells = <0>;
+
+ assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clock-parents = <&atl_clkin2_ck>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ status = "okay";
+ };
+};
/ {
model = "TI DRA722 Rev C EVM";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
};
-&tps65917_regulators {
- ldo2_reg: ldo2 {
- /* LDO2_OUT --> VDDA_1V8_PHY2 */
- regulator-name = "ldo2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
};
};
+#include "dra72-evm-tps65917.dtsi"
+
+&ldo2_reg {
+ /* LDO2_OUT --> VDDA_1V8_PHY2 */
+ regulator-always-on;
+ regulator-boot-on;
+};
+
&hdmi {
- vdda_video-supply = <&ldo2_reg>;
+ vdda-supply = <&ldo2_reg>;
+};
+
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio3>;
+ interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};
&mac {
--- /dev/null
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ */
+
+&tps65917 {
+ compatible = "ti,tps65917";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ smps1-in-supply = <&vsys_3v3>;
+ smps2-in-supply = <&vsys_3v3>;
+ smps3-in-supply = <&vsys_3v3>;
+ smps4-in-supply = <&vsys_3v3>;
+ smps5-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+ ldo2-in-supply = <&vsys_3v3>;
+ ldo3-in-supply = <&vsys_3v3>;
+ ldo4-in-supply = <&evm_5v0>;
+ ldo5-in-supply = <&vsys_3v3>;
+
+ tps65917_regulators: regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-bypass;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-bypass;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+};
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <dra72-evm-common.dtsi>
-
+#include "dra72-evm-common.dtsi"
/ {
model = "TI DRA722";
- compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x80000000 0x40000000>; /* 1024 MB */
+ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
};
+&i2c1 {
+ tps65917: tps65917@58 {
+ reg = <0x58>;
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <3>;
- phy-mode = "rgmii";
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ };
};
-&dss {
- status = "ok";
-
- vdda_video-supply = <&ldo5_reg>;
-};
+#include "dra72-evm-tps65917.dtsi"
&hdmi {
vdda-supply = <&ldo3_reg>;
};
+&pcf_gpio_21 {
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+};
+
&mac {
- mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
+ slaves = <1>;
+ mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
};
clock-frequency = <32768>;
};
- sys_32k_ck: sys_32k_ck {
+ sys_clk32_crystal_ck: sys_clk32_crystal_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
+ sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <610>;
+ };
+
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
- dpll_abe_ck: dpll_abe_ck {
+ dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
clocks = <&dpll_abe_ck>;
};
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,invert-autoidle-bit;
};
- abe_clk: abe_clk {
+ abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
ti,index-power-of-two;
};
- dpll_abe_m2_ck: dpll_abe_m2_ck {
+ dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
ti,invert-autoidle-bit;
};
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: dpll_core_byp_mux {
+ dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
reg = <0x012c>;
};
- dpll_core_ck: dpll_core_ck {
+ dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
clocks = <&dpll_core_ck>;
};
- dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
clock-div = <1>;
};
- dpll_mpu_ck: dpll_mpu_ck {
+ dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
- dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
clock-div = <1>;
};
- dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+ dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
reg = <0x0240>;
};
- dpll_dsp_ck: dpll_dsp_ck {
+ dpll_dsp_ck: dpll_dsp_ck@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
};
- dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+ dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_ck>;
clock-div = <1>;
};
- dpll_iva_byp_mux: dpll_iva_byp_mux {
+ dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
reg = <0x01ac>;
};
- dpll_iva_ck: dpll_iva_ck {
+ dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
};
- dpll_iva_m2_ck: dpll_iva_m2_ck {
+ dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_ck>;
clock-div = <1>;
};
- dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+ dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
reg = <0x02e4>;
};
- dpll_gpu_ck: dpll_gpu_ck {
+ dpll_gpu_ck: dpll_gpu_ck@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
};
- dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+ dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_ck>;
ti,invert-autoidle-bit;
};
- dpll_core_m2_ck: dpll_core_m2_ck {
+ dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
clock-div = <1>;
};
- dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+ dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
reg = <0x021c>;
};
- dpll_ddr_ck: dpll_ddr_ck {
+ dpll_ddr_ck: dpll_ddr_ck@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
- dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+ dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+ dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
reg = <0x02b4>;
};
- dpll_gmac_ck: dpll_gmac_ck {
+ dpll_gmac_ck: dpll_gmac_ck@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
- dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+ dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
clock-div = <1>;
};
- dpll_eve_byp_mux: dpll_eve_byp_mux {
+ dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
reg = <0x0290>;
};
- dpll_eve_ck: dpll_eve_ck {
+ dpll_eve_ck: dpll_eve_ck@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
- dpll_eve_m2_ck: dpll_eve_m2_ck {
+ dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_eve_ck>;
clock-div = <1>;
};
- dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
clocks = <&dpll_ddr_ck>;
};
- dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+ dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
clocks = <&dpll_dsp_ck>;
};
- dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+ dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_x2_ck>;
clocks = <&dpll_gmac_ck>;
};
- dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+ dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+ dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+ dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+ dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
clock-div = <1>;
};
- l3_iclk_div: l3_iclk_div {
+ l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
clock-div = <1>;
};
- ipu1_gfclk_mux: ipu1_gfclk_mux {
+ ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
reg = <0x0520>;
};
- mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+ mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x0550>;
};
- mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+ mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x0550>;
};
- mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+ mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x0550>;
};
- timer5_gfclk_mux: timer5_gfclk_mux {
+ timer5_gfclk_mux: timer5_gfclk_mux@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
reg = <0x0558>;
};
- timer6_gfclk_mux: timer6_gfclk_mux {
+ timer6_gfclk_mux: timer6_gfclk_mux@560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
reg = <0x0560>;
};
- timer7_gfclk_mux: timer7_gfclk_mux {
+ timer7_gfclk_mux: timer7_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
reg = <0x0568>;
};
- timer8_gfclk_mux: timer8_gfclk_mux {
+ timer8_gfclk_mux: timer8_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
reg = <0x0570>;
};
- uart6_gfclk_mux: uart6_gfclk_mux {
+ uart6_gfclk_mux: uart6_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
};
};
&prm_clocks {
- sys_clkin1: sys_clkin1 {
+ sys_clkin1: sys_clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+ abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
- abe_dpll_clk_mux: abe_dpll_clk_mux {
+ abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
- abe_24m_fclk: abe_24m_fclk {
+ abe_24m_fclk: abe_24m_fclk@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
ti,dividers = <8>, <16>;
};
- aess_fclk: aess_fclk {
+ aess_fclk: aess_fclk@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
ti,max-div = <2>;
};
- abe_giclk_div: abe_giclk_div {
+ abe_giclk_div: abe_giclk_div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
ti,max-div = <2>;
};
- abe_lp_clk_div: abe_lp_clk_div {
+ abe_lp_clk_div: abe_lp_clk_div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
ti,dividers = <16>, <32>;
};
- abe_sys_clk_div: abe_sys_clk_div {
+ abe_sys_clk_div: abe_sys_clk_div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <2>;
};
- adc_gfclk_mux: adc_gfclk_mux {
+ adc_gfclk_mux: adc_gfclk_mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
- sys_clk1_dclk_div: sys_clk1_dclk_div {
+ sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,index-power-of-two;
};
- sys_clk2_dclk_div: sys_clk2_dclk_div {
+ sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin2>;
ti,index-power-of-two;
};
- per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+ per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
ti,index-power-of-two;
};
- dsp_gclk_div: dsp_gclk_div {
+ dsp_gclk_div: dsp_gclk_div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_m2_ck>;
ti,index-power-of-two;
};
- gpu_dclk: gpu_dclk {
+ gpu_dclk: gpu_dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_m2_ck>;
ti,index-power-of-two;
};
- emif_phy_dclk_div: emif_phy_dclk_div {
+ emif_phy_dclk_div: emif_phy_dclk_div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_m2_ck>;
ti,index-power-of-two;
};
- gmac_250m_dclk_div: gmac_250m_dclk_div {
+ gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
ti,index-power-of-two;
};
- l3init_480m_dclk_div: l3init_480m_dclk_div {
+ gmac_main_clk: gmac_main_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&gmac_250m_dclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
ti,index-power-of-two;
};
- usb_otg_dclk_div: usb_otg_dclk_div {
+ usb_otg_dclk_div: usb_otg_dclk_div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&usb_otg_clkin_ck>;
ti,index-power-of-two;
};
- sata_dclk_div: sata_dclk_div {
+ sata_dclk_div: sata_dclk_div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,index-power-of-two;
};
- pcie2_dclk_div: pcie2_dclk_div {
+ pcie2_dclk_div: pcie2_dclk_div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_m2_ck>;
ti,index-power-of-two;
};
- pcie_dclk_div: pcie_dclk_div {
+ pcie_dclk_div: pcie_dclk_div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&apll_pcie_m2_ck>;
ti,index-power-of-two;
};
- emu_dclk_div: emu_dclk_div {
+ emu_dclk_div: emu_dclk_div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,index-power-of-two;
};
- secure_32k_dclk_div: secure_32k_dclk_div {
+ secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&secure_32k_clk_src_ck>;
ti,index-power-of-two;
};
- clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+ clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
- clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+ clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
- clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+ clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
clock-div = <2>;
};
- eve_clk: eve_clk {
+ eve_clk: eve_clk@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
- hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+ hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
- mlb_clk: mlb_clk {
+ mlb_clk: mlb_clk@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlb_clkin_ck>;
ti,index-power-of-two;
};
- mlbp_clk: mlbp_clk {
+ mlbp_clk: mlbp_clk@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlbp_clkin_ck>;
ti,index-power-of-two;
};
- per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+ per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
ti,index-power-of-two;
};
- timer_sys_clk_div: timer_sys_clk_div {
+ timer_sys_clk_div: timer_sys_clk_div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
ti,max-div = <2>;
};
- video1_dpll_clk_mux: video1_dpll_clk_mux {
+ video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
- video2_dpll_clk_mux: video2_dpll_clk_mux {
+ video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
- wkupaon_iclk_mux: wkupaon_iclk_mux {
+ wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
- gpio1_dbclk: gpio1_dbclk {
+ gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1838>;
};
- dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+ dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x1888>;
};
- timer1_gfclk_mux: timer1_gfclk_mux {
+ timer1_gfclk_mux: timer1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1840>;
};
- uart10_gfclk_mux: uart10_gfclk_mux {
+ uart10_gfclk_mux: uart10_gfclk_mux@1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
};
};
&cm_core_clocks {
- dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+ dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
- dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
ti,bit-shift = <7>;
};
- apll_pcie_ck: apll_pcie_ck {
+ apll_pcie_ck: apll_pcie_ck@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
clock-div = <1>;
};
- dpll_per_byp_mux: dpll_per_byp_mux {
+ dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
reg = <0x014c>;
};
- dpll_per_ck: dpll_per_ck {
+ dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: dpll_per_m2_ck {
+ dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
clock-div = <1>;
};
- dpll_usb_byp_mux: dpll_usb_byp_mux {
+ dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
reg = <0x018c>;
};
- dpll_usb_ck: dpll_usb_ck {
+ dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
- dpll_usb_m2_ck: dpll_usb_m2_ck {
+ dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
ti,invert-autoidle-bit;
};
- dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+ dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
clocks = <&dpll_per_ck>;
};
- dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+ dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
clock-div = <2>;
};
- l3init_60m_fclk: l3init_60m_fclk {
+ l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
ti,dividers = <1>, <8>;
};
- clkout2_clk: clkout2_clk {
+ clkout2_clk: clkout2_clk@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkoutmux2_clk_mux>;
reg = <0x06b0>;
};
- l3init_960m_gfclk: l3init_960m_gfclk {
+ l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
reg = <0x06c0>;
};
- dss_32khz_clk: dss_32khz_clk {
+ dss_32khz_clk: dss_32khz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1120>;
};
- dss_48mhz_clk: dss_48mhz_clk {
+ dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
reg = <0x1120>;
};
- dss_dss_clk: dss_dss_clk {
+ dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
ti,set-rate-parent;
};
- dss_hdmi_clk: dss_hdmi_clk {
+ dss_hdmi_clk: dss_hdmi_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
reg = <0x1120>;
};
- dss_video1_clk: dss_video1_clk {
+ dss_video1_clk: dss_video1_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
reg = <0x1120>;
};
- dss_video2_clk: dss_video2_clk {
+ dss_video2_clk: dss_video2_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
reg = <0x1120>;
};
- gpio2_dbclk: gpio2_dbclk {
+ gpio2_dbclk: gpio2_dbclk@1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1760>;
};
- gpio3_dbclk: gpio3_dbclk {
+ gpio3_dbclk: gpio3_dbclk@1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1768>;
};
- gpio4_dbclk: gpio4_dbclk {
+ gpio4_dbclk: gpio4_dbclk@1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1770>;
};
- gpio5_dbclk: gpio5_dbclk {
+ gpio5_dbclk: gpio5_dbclk@1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1778>;
};
- gpio6_dbclk: gpio6_dbclk {
+ gpio6_dbclk: gpio6_dbclk@1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1780>;
};
- gpio7_dbclk: gpio7_dbclk {
+ gpio7_dbclk: gpio7_dbclk@1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1810>;
};
- gpio8_dbclk: gpio8_dbclk {
+ gpio8_dbclk: gpio8_dbclk@1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1818>;
};
- mmc1_clk32k: mmc1_clk32k {
+ mmc1_clk32k: mmc1_clk32k@1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1328>;
};
- mmc2_clk32k: mmc2_clk32k {
+ mmc2_clk32k: mmc2_clk32k@1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1330>;
};
- mmc3_clk32k: mmc3_clk32k {
+ mmc3_clk32k: mmc3_clk32k@1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1820>;
};
- mmc4_clk32k: mmc4_clk32k {
+ mmc4_clk32k: mmc4_clk32k@1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x1828>;
};
- sata_ref_clk: sata_ref_clk {
+ sata_ref_clk: sata_ref_clk@1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
reg = <0x1388>;
};
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
reg = <0x13f0>;
};
- usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
reg = <0x1340>;
};
- usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x0640>;
};
- usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+ usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x0688>;
};
- usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
reg = <0x0698>;
};
- atl_dpll_clk_mux: atl_dpll_clk_mux {
+ atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
reg = <0x0c00>;
};
- atl_gfclk_mux: atl_gfclk_mux {
+ atl_gfclk_mux: atl_gfclk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
reg = <0x0c00>;
};
- gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_gmac_m2_ck>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
- ti,dividers = <2>;
};
- gmac_rft_clk_mux: gmac_rft_clk_mux {
+ gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
reg = <0x13d0>;
};
- gpu_core_gclk_mux: gpu_core_gclk_mux {
+ gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
reg = <0x1220>;
};
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
reg = <0x1220>;
};
- l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&wkupaon_iclk_mux>;
ti,dividers = <8>, <16>, <32>;
};
- mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+ mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1860>;
};
- mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+ mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1860>;
};
- mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+ mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1860>;
};
- mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+ mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1868>;
};
- mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+ mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1868>;
};
- mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+ mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1898>;
};
- mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+ mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1898>;
};
- mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+ mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1878>;
};
- mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+ mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1878>;
};
- mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+ mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1904>;
};
- mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+ mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1904>;
};
- mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+ mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1908>;
};
- mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1908>;
};
- mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+ mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
reg = <0x1890>;
};
- mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+ mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
reg = <0x1890>;
};
- mmc1_fclk_mux: mmc1_fclk_mux {
+ mmc1_fclk_mux: mmc1_fclk_mux@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
reg = <0x1328>;
};
- mmc1_fclk_div: mmc1_fclk_div {
+ mmc1_fclk_div: mmc1_fclk_div@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
ti,index-power-of-two;
};
- mmc2_fclk_mux: mmc2_fclk_mux {
+ mmc2_fclk_mux: mmc2_fclk_mux@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
reg = <0x1330>;
};
- mmc2_fclk_div: mmc2_fclk_div {
+ mmc2_fclk_div: mmc2_fclk_div@1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
ti,index-power-of-two;
};
- mmc3_gfclk_mux: mmc3_gfclk_mux {
+ mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1820>;
};
- mmc3_gfclk_div: mmc3_gfclk_div {
+ mmc3_gfclk_div: mmc3_gfclk_div@1820 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
ti,index-power-of-two;
};
- mmc4_gfclk_mux: mmc4_gfclk_mux {
+ mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1828>;
};
- mmc4_gfclk_div: mmc4_gfclk_div {
+ mmc4_gfclk_div: mmc4_gfclk_div@1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
ti,index-power-of-two;
};
- qspi_gfclk_mux: qspi_gfclk_mux {
+ qspi_gfclk_mux: qspi_gfclk_mux@1838 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
reg = <0x1838>;
};
- qspi_gfclk_div: qspi_gfclk_div {
+ qspi_gfclk_div: qspi_gfclk_div@1838 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
ti,index-power-of-two;
};
- timer10_gfclk_mux: timer10_gfclk_mux {
+ timer10_gfclk_mux: timer10_gfclk_mux@1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1728>;
};
- timer11_gfclk_mux: timer11_gfclk_mux {
+ timer11_gfclk_mux: timer11_gfclk_mux@1730 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1730>;
};
- timer13_gfclk_mux: timer13_gfclk_mux {
+ timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x17c8>;
};
- timer14_gfclk_mux: timer14_gfclk_mux {
+ timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x17d0>;
};
- timer15_gfclk_mux: timer15_gfclk_mux {
+ timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x17d8>;
};
- timer16_gfclk_mux: timer16_gfclk_mux {
+ timer16_gfclk_mux: timer16_gfclk_mux@1830 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1830>;
};
- timer2_gfclk_mux: timer2_gfclk_mux {
+ timer2_gfclk_mux: timer2_gfclk_mux@1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1738>;
};
- timer3_gfclk_mux: timer3_gfclk_mux {
+ timer3_gfclk_mux: timer3_gfclk_mux@1740 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1740>;
};
- timer4_gfclk_mux: timer4_gfclk_mux {
+ timer4_gfclk_mux: timer4_gfclk_mux@1748 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1748>;
};
- timer9_gfclk_mux: timer9_gfclk_mux {
+ timer9_gfclk_mux: timer9_gfclk_mux@1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
reg = <0x1750>;
};
- uart1_gfclk_mux: uart1_gfclk_mux {
+ uart1_gfclk_mux: uart1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1840>;
};
- uart2_gfclk_mux: uart2_gfclk_mux {
+ uart2_gfclk_mux: uart2_gfclk_mux@1848 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1848>;
};
- uart3_gfclk_mux: uart3_gfclk_mux {
+ uart3_gfclk_mux: uart3_gfclk_mux@1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1850>;
};
- uart4_gfclk_mux: uart4_gfclk_mux {
+ uart4_gfclk_mux: uart4_gfclk_mux@1858 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1858>;
};
- uart5_gfclk_mux: uart5_gfclk_mux {
+ uart5_gfclk_mux: uart5_gfclk_mux@1870 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x1870>;
};
- uart7_gfclk_mux: uart7_gfclk_mux {
+ uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x18d0>;
};
- uart8_gfclk_mux: uart8_gfclk_mux {
+ uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x18e0>;
};
- uart9_gfclk_mux: uart9_gfclk_mux {
+ uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
reg = <0x18e8>;
};
- vip1_gclk_mux: vip1_gclk_mux {
+ vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
reg = <0x1020>;
};
- vip2_gclk_mux: vip2_gclk_mux {
+ vip2_gclk_mux: vip2_gclk_mux@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
reg = <0x1028>;
};
- vip3_gclk_mux: vip3_gclk_mux {
+ vip3_gclk_mux: vip3_gclk_mux@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
};
&scm_conf_clocks {
- dss_deshdcp_clk: dss_deshdcp_clk {
+ dss_deshdcp_clk: dss_deshdcp_clk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
ti,bit-shift = <0>;
reg = <0x558>;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <20>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <21>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <22>;
+ reg = <0x0558>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x6c4>;
+ };
};
aliases {
serial0 = &uart1;
+ spi0 = &qspi;
+ mmc0 = &sdhci1;
};
memory@0 {
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
#include <spl.h>
#if defined(CONFIG_MX6)
+#define MX6_MMC_PORT_MASK GENMASK(12, 11)
+#define MX6_MMC_PORT_2 BIT(11)
+
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
{
/* SD/eSD: 8.5.3, Table 8-15 */
case 0x4:
case 0x5:
- return BOOT_DEVICE_MMC1;
/* MMC/eMMC: 8.5.3 */
case 0x6:
case 0x7:
+ if ((reg & MX6_MMC_PORT_MASK) == MX6_MMC_PORT_2)
+ return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
/* NAND Flash: 8.5.2 */
case 0x8 ... 0xf:
}
if (i < display_count) {
- ret = ipuv3_fb_init(&displays[i].mode, 0,
+ ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0,
displays[i].pixfmt);
if (!ret) {
if (displays[i].enable)
void enable_thermal_clk(void);
void mxs_set_lcdclk(u32 base_addr, u32 freq);
void select_ldb_di_clock_source(enum ldb_di_clock clk);
+void enable_eim_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
#define BP_PMU_MISC2_AUDIO_DIV_MSB 23
const struct mx6sl_iomux_ddr_regs *,
const struct mx6sl_iomux_grp_regs *);
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-int mmdc_do_write_level_calibration(void);
-int mmdc_do_dqs_calibration(void);
+#if defined(CONFIG_MX6_DDRCAL)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+ struct mx6_mmdc_calibration *calib);
#endif
/* configure mx6 mmdc registers */
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
+#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
#define MX6_MMDC_P1_MDCTL 0x021b4000
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
+#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
#endif /*__ASM_ARCH_MX6_DDR_H__ */
#ifndef __ASM_ARCH_OMAP3_MUSB_H
#define __ASM_ARCH_OMAP3_MUSB_H
-extern void am35x_musb_reset(void);
-extern void am35x_musb_phy_power(u8 on);
-extern void am35x_musb_clear_irq(void);
+void am35x_musb_reset(struct udevice *dev);
+void am35x_musb_phy_power(struct udevice *dev, u8 on);
+void am35x_musb_clear_irq(struct udevice *dev);
#endif
/* STD_FUSE_OPP_VMIN_MPU_4 */
#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
-/* Common voltage and Efuse register macros */
-/* DRA74x/DRA75x/DRA72x */
-#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
-#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
-#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM
-#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM
-#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM
-
-#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
-#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
-#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM
-#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM
-#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP OPP_NOM
+#endif
+
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP OPP_NOM
+#endif
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
+/* Offset is 0.73V for LP873x */
+#define LP873X_BUCK_BASE_VOLT_UV 730000
+
/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
#define TPS659038_REG_ADDR_SMPS12 0x23
#define TPS65917_REG_ADDR_SMPS2 0x27
#define TPS65917_REG_ADDR_SMPS3 0x2F
+/* LP873X */
+#define LP873X_I2C_SLAVE_ADDR 0x60
+#define LP873X_REG_ADDR_BUCK0 0x6
+#define LP873X_REG_ADDR_BUCK1 0x7
+#define LP873X_REG_ADDR_LDO1 0xA
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#define V_OSCK 19200000 /* Clock output from T2 */
#define GPMC_BASE 0x50000000
/* EDMA3 Base address for DRA7XX and AM57XX */
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define EDMA3_BASE 0x43300000
#endif
#define EMU3 0x454
#define EMU4 0x458
#define RESETN 0x45C
-#define NMIN 0x460
+#define NMIN_DSP 0x460
#define RSTOUTN 0x464
#endif /* _MUX_DRA7XX_H_ */
#define CONTROL_CORE_ID_CODE 0x4A002204
#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
#else
#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
#endif
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define DRA7_USB_OTG_SS1_BASE 0x48890000
#define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000
#define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00
* much larger) and do not, at this time, make use of the additional
* space.
*/
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#define NON_SECURE_SRAM_IMG_END 0x4037E000
#define JTAG_MODE 0x00000000
#define BOOT_MODE_USE_ALT 0x100
#define BOOT_MODE_ALT_SHIFT 12
+/* SW secondary boot modes 0xa - 0xd */
+#define SW_USBHOST_MODE 0x0000000A
+#define SW_SATA_MODE 0x0000000B
#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
int bus;
int addr;
int pixfmt;
+ int di;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+enum {
+ OPP_LOW,
+ OPP_NOM,
+ OPP_OD,
+ OPP_HIGH,
+ NUM_OPPS,
+};
+
/**
* struct volts_efuse_data - efuse definition for voltage
* @reg: register address for efuse
* @reg_bits: Number of bits in a register address, mandatory.
*/
struct volts_efuse_data {
- u32 reg;
+ u32 reg[NUM_OPPS];
u8 reg_bits;
};
struct volts {
- u32 value;
+ u32 value[NUM_OPPS];
u32 addr;
struct volts_efuse_data efuse;
struct pmic_data *pmic;
u32 abb_tx_done_mask;
};
+enum {
+ VOLT_MPU,
+ VOLT_CORE,
+ VOLT_MM,
+ VOLT_GPU,
+ VOLT_EVE,
+ VOLT_IVA,
+ NUM_VOLT_RAILS,
+};
+
struct vcores_data {
struct volts mpu;
struct volts core;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
extern struct pmic_data tps659038;
+extern struct pmic_data lp8733;
void hw_data_init(void);
void disable_usb_clocks(int index);
void scale_vcores(struct vcores_data const *);
+int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
* security (HS) device variants by doing a specially-formed smc entry.
*/
u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
void enable_edma3_clocks(void);
void disable_edma3_clocks(void);
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio);
-
+void vmmc_pbias_config(uint voltage);
#endif /* OMAP_MMC_H_ */
struct omap_musb_board_data {
u8 interface_type;
- void (*set_phy_power)(u8 on);
- void (*clear_irq)(void);
- void (*reset)(void);
+ struct udevice *dev;
+ void (*set_phy_power)(struct udevice *dev, u8 on);
+ void (*clear_irq)(struct udevice *dev);
+ void (*reset)(struct udevice *dev);
};
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
*/
int secure_emif_firewall_lock(void);
+/*
+ * Invoke a secure HAL API to authenticate and install a Trusted Execution
+ * Environment (TEE) image.
+ */
+int secure_tee_install(u32 tee_image);
+
#endif /* _OMAP_SEC_COMMON_H_ */
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_ARCH_FIXUP_FDT
int arch_fixup_fdt(void *blob)
{
bd_t *bd = gd->bd;
return 0;
}
-#endif
if (images->ft_addr) {
off = fdt_path_offset(images->ft_addr, "/memory");
if (off < 0) {
-#ifdef CONFIG_ARCH_FIXUP_FDT
if (arch_fixup_fdt(images->ft_addr))
puts("## WARNING: fixup memory failed!\n");
-#endif
}
}
#endif
config TARGET_IPAM390
bool "IPAM390 board"
select SUPPORT_SPL
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_DA850EVM
bool "DA850 EVM board"
select SUPPORT_SPL
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_EA20
bool "EA20 board"
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SUPPORT_SPL
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_CALIMAIN
bool "Calimain board"
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
+ select SYS_DA850_PLL_INIT
+ select SYS_DA850_DDR_INIT
endchoice
config SYS_SOC
default "davinci"
+config SYS_DA850_PLL_INIT
+ bool
+
+config SYS_DA850_DDR_INIT
+ bool
+
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
puts("\nClear entire DDR3 memory to enable ECC\n");
/* save the SES MPAX regs */
- msmc_get_ses_mpax(8, 0, mpax);
+ if (cpu_is_k2g())
+ msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+ else
+ msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
/* setup edma slot 1 configuration */
slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
access slave interface so that edma driver can access */
- msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
+ if (cpu_is_k2g()) {
+ msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg,
+ MPAX_SEG_2G);
+ } else {
+ msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
+ base >> KS2_MSMC_SEG_SIZE_SHIFT,
+ KS2_MSMC_DST_SEG_BASE + seg,
+ MPAX_SEG_2G);
+ }
if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
edma_blks = KS2_MSMC_MAP_SEG_NUM <<
qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
/* restore the SES MPAX regs */
- msmc_set_ses_mpax(8, 0, mpax);
+ if (cpu_is_k2g())
+ msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
+ else
+ msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
}
static void ddr3_ecc_init_range(u32 base)
bool
select ARM64
+# Armada PLL frequency (used for NAND clock generation)
+config SYS_MVEBU_PLL_CLOCK
+ int
+ default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
+ default "1000000000" if ARMADA_38X || ARMADA_375
+
# Armada XP/38x SoC types...
config MV78230
bool
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
-/* Armada XP PLL frequency (used for NAND clock generation) */
-#define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000
-
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
- (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
+ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
+ (!defined(CONFIG_DM_USB))
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* USB 2.0 PHY Control */
};
#ifdef CONFIG_AM335X_USB0
-static void am33xx_otg0_set_phy_power(u8 on)
+static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
{
am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
}
#endif
#ifdef CONFIG_AM335X_USB1
-static void am33xx_otg1_set_phy_power(u8 on)
+static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
{
am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
}
int arch_misc_init(void)
{
+#ifndef CONFIG_DM_USB
#ifdef CONFIG_AM335X_USB0
musb_register(&otg0_plat, &otg0_board_data,
(void *)USB0_OTG_BASE);
#ifdef CONFIG_AM335X_USB1
musb_register(&otg1_plat, &otg1_board_data,
(void *)USB1_OTG_BASE);
+#endif
+#else
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_MISC, &dev);
+ if (ret || !dev)
+ return ret;
#endif
return 0;
}
gpio_direction_output(pmic->gpio, 1);
}
-static u32 optimize_vcore_voltage(struct volts const *v)
+int __weak get_voltrail_opp(int rail_offset)
+{
+ /*
+ * By default return OPP_NOM for all voltage rails.
+ */
+ return OPP_NOM;
+}
+
+static u32 optimize_vcore_voltage(struct volts const *v, int opp)
{
u32 val;
- if (!v->value)
+
+ if (!v->value[opp])
return 0;
- if (!v->efuse.reg)
- return v->value;
+ if (!v->efuse.reg[opp])
+ return v->value[opp];
switch (v->efuse.reg_bits) {
case 16:
- val = readw(v->efuse.reg);
+ val = readw(v->efuse.reg[opp]);
break;
case 32:
- val = readl(v->efuse.reg);
+ val = readl(v->efuse.reg[opp]);
break;
default:
printf("Error: efuse 0x%08x bits=%d unknown\n",
- v->efuse.reg, v->efuse.reg_bits);
- return v->value;
+ v->efuse.reg[opp], v->efuse.reg_bits);
+ return v->value[opp];
}
if (!val) {
printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
- v->efuse.reg, v->efuse.reg_bits, v->value);
- return v->value;
+ v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
+ return v->value[opp];
}
debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
- __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+ __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
+ val);
return val;
}
*/
void scale_vcores(struct vcores_data const *vcores)
{
- int i;
+ int i, opp, j, ol;
struct volts *pv = (struct volts *)vcores;
struct volts *px;
for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
- debug("%d -> ", pv->value);
- if (pv->value) {
+ opp = get_voltrail_opp(i);
+ debug("%d -> ", pv->value[opp]);
+
+ if (pv->value[opp]) {
/* Handle non-empty members only */
- pv->value = optimize_vcore_voltage(pv);
+ pv->value[opp] = optimize_vcore_voltage(pv, opp);
px = (struct volts *)vcores;
+ j = 0;
while (px < pv) {
/*
* Scan already handled non-empty members to see
* particular SMPS; the other group voltages are
* zeroed.
*/
- if (px->value) {
- if ((pv->pmic->i2c_slave_addr ==
- px->pmic->i2c_slave_addr) &&
- (pv->addr == px->addr)) {
- /* Same PMIC, same SMPS */
- if (pv->value > px->value)
- px->value = pv->value;
-
- pv->value = 0;
- }
- }
+ ol = get_voltrail_opp(j);
+ if (px->value[ol] &&
+ (pv->pmic->i2c_slave_addr ==
+ px->pmic->i2c_slave_addr) &&
+ (pv->addr == px->addr)) {
+ /* Same PMIC, same SMPS */
+ if (pv->value[opp] > px->value[ol])
+ px->value[ol] = pv->value[opp];
+
+ pv->value[opp] = 0;
+ }
px++;
+ j++;
}
}
- debug("%d\n", pv->value);
+ debug("%d\n", pv->value[opp]);
pv++;
}
- debug("cor: %d\n", vcores->core.value);
- do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
+ opp = get_voltrail_opp(VOLT_CORE);
+ debug("cor: %d\n", vcores->core.value[opp]);
+ do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
+ vcores->core.pmic);
/*
* IO delay recalibration should be done immediately after
* adjusting AVS voltages for VDD_CORE_L.
recalibrate_iodelay();
#endif
- debug("mpu: %d\n", vcores->mpu.value);
- do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
+ opp = get_voltrail_opp(VOLT_MPU);
+ debug("mpu: %d\n", vcores->mpu.value[opp]);
+ do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
+ vcores->mpu.pmic);
/* Configure MPU ABB LDO after scale */
- abb_setup(vcores->mpu.efuse.reg,
+ abb_setup(vcores->mpu.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
(*prcm)->prm_abbldo_mpu_setup,
(*prcm)->prm_abbldo_mpu_ctrl,
vcores->mpu.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("mm: %d\n", vcores->mm.value);
- do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic);
+ opp = get_voltrail_opp(VOLT_MM);
+ debug("mm: %d\n", vcores->mm.value[opp]);
+ do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
+ vcores->mm.pmic);
/* Configure MM ABB LDO after scale */
- abb_setup(vcores->mm.efuse.reg,
+ abb_setup(vcores->mm.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
(*prcm)->prm_abbldo_mm_setup,
(*prcm)->prm_abbldo_mm_ctrl,
vcores->mm.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("gpu: %d\n", vcores->gpu.value);
- do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
+ opp = get_voltrail_opp(VOLT_GPU);
+ debug("gpu: %d\n", vcores->gpu.value[opp]);
+ do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
+ vcores->gpu.pmic);
/* Configure GPU ABB LDO after scale */
- abb_setup(vcores->gpu.efuse.reg,
+ abb_setup(vcores->gpu.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
(*prcm)->prm_abbldo_gpu_setup,
(*prcm)->prm_abbldo_gpu_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->gpu.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("eve: %d\n", vcores->eve.value);
- do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
+
+ opp = get_voltrail_opp(VOLT_EVE);
+ debug("eve: %d\n", vcores->eve.value[opp]);
+ do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
+ vcores->eve.pmic);
/* Configure EVE ABB LDO after scale */
- abb_setup(vcores->eve.efuse.reg,
+ abb_setup(vcores->eve.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
(*prcm)->prm_abbldo_eve_setup,
(*prcm)->prm_abbldo_eve_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->eve.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("iva: %d\n", vcores->iva.value);
- do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
+
+ opp = get_voltrail_opp(VOLT_IVA);
+ debug("iva: %d\n", vcores->iva.value[opp]);
+ do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
+ vcores->iva.pmic);
/* Configure IVA ABB LDO after scale */
- abb_setup(vcores->iva.efuse.reg,
+ abb_setup(vcores->iva.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
(*prcm)->prm_abbldo_iva_setup,
(*prcm)->prm_abbldo_iva_ctrl,
#include <asm/io.h>
#include <asm/arch/am35x_def.h>
-void am35x_musb_reset(void)
+void am35x_musb_reset(struct udevice *dev)
{
/* Reset the musb interface */
clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
USBOTGSS_SW_RST, 0);
}
-void am35x_musb_phy_power(u8 on)
+void am35x_musb_phy_power(struct udevice *dev, u8 on)
{
unsigned long start = get_timer(0);
}
}
-void am35x_musb_clear_irq(void)
+void am35x_musb_clear_irq(struct udevice *dev)
{
clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
0, USBOTGSS_INT_CLR);
};
struct vcores_data omap4430_volts_es1 = {
- .mpu.value = 1325,
+ .mpu.value[OPP_NOM] = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030_4430es1,
- .core.value = 1200,
+ .core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030_4430es1,
- .mm.value = 1200,
+ .mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030_4430es1,
};
struct vcores_data omap4430_volts = {
- .mpu.value = 1325,
+ .mpu.value[OPP_NOM] = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030,
- .core.value = 1200,
+ .core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030,
- .mm.value = 1200,
+ .mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
struct vcores_data omap4460_volts = {
- .mpu.value = 1203,
+ .mpu.value[OPP_NOM] = 1203,
.mpu.addr = TPS62361_REG_ADDR_SET1,
.mpu.pmic = &tps62361,
- .core.value = 1200,
+ .core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
.core.pmic = &twl6030,
- .mm.value = 1200,
+ .mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
*/
struct vcores_data omap4470_volts = {
- .mpu.value = 1202,
+ .mpu.value[OPP_NOM] = 1202,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
- .core.value = 1126,
+ .core.value[OPP_NOM] = 1126,
.core.addr = SMPS_REG_ADDR_SMPS2,
.core.pmic = &twl6030,
- .mm.value = 1139,
+ .mm.value[OPP_NOM] = 1139,
.mm.addr = SMPS_REG_ADDR_SMPS5,
.mm.pmic = &twl6030,
};
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <palmas.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
+
+void vmmc_pbias_config(uint voltage)
+{
+ u32 value = 0;
+
+ value = readl((*ctrl)->control_pbiaslite);
+ value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
+ writel(value, (*ctrl)->control_pbiaslite);
+ value = readl((*ctrl)->control_pbiaslite);
+ value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
+ writel(value, (*ctrl)->control_pbiaslite);
+}
using hardware memory firewalls. This value must be smaller than the
TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
+if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
+menu "Voltage Domain OPP selections"
+
+choice
+ prompt "MPU Voltage Domain"
+ default DRA7_MPU_OPP_NOM
+ help
+ Select the Operating Performance Point(OPP) for the MPU voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_MPU_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for MPU. This is the safest
+ option for booting.
+
+endchoice
+
+choice
+ prompt "DSPEVE Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the DSPEVE voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_DSPEVE_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for DSPEVE. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_DSPEVE_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for DSPEVE.
+
+config DRA7_DSPEVE_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for DSPEVE.
+
+endchoice
+
+choice
+ prompt "IVA Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the IVA voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_IVA_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for IVA. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_IVA_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for IVA.
+
+config DRA7_IVA_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for IVA.
+
+endchoice
+
+choice
+ prompt "GPU Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the GPU voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_GPU_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for GPU. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_GPU_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for GPU.
+
+config DRA7_GPU_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for GPU.
+
+endchoice
+
+endmenu
+endif
+
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
obj-y += fdt.o
obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o
+obj-$(CONFIG_DRA7XX) += sec_entry_cpu1.o
#include <spl.h>
static u32 boot_devices[] = {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
BOOT_DEVICE_MMC2,
BOOT_DEVICE_NAND,
BOOT_DEVICE_MMC1,
static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
#endif
+static int ft_hs_add_tee(void *fdt, bd_t *bd)
+{
+ const char *path, *subpath;
+ int offs;
+
+ extern int tee_loaded;
+ if (!tee_loaded)
+ return 0;
+
+ path = "/";
+ offs = fdt_path_offset(fdt, path);
+
+ subpath = "firmware";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return 1;
+ }
+
+ subpath = "optee";
+ offs = fdt_add_subnode(fdt, offs, subpath);
+ if (offs < 0) {
+ printf("Could not create %s node.\n", subpath);
+ return 1;
+ }
+
+ fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
+ fdt_setprop_string(fdt, offs, "method", "smc");
+
+ return 0;
+}
+
static void ft_hs_fixups(void *fdt, bd_t *bd)
{
/* Check we are running on an HS/EMU device type */
if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
(ft_hs_disable_rng(fdt, bd) == 0) &&
(ft_hs_fixup_sram(fdt, bd) == 0) &&
- (ft_hs_fixup_dram(fdt, bd) == 0))
+ (ft_hs_fixup_dram(fdt, bd) == 0) &&
+ (ft_hs_add_tee(fdt, bd) == 0))
return;
} else {
printf("ERROR: Incorrect device type (GP) detected!");
}
#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
+#if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
+#define OPP_DSP_CLK_NUM 3
+#define OPP_IVA_CLK_NUM 2
+#define OPP_GPU_CLK_NUM 2
+
+const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
+ "dpll_dsp_ck",
+ "dpll_dsp_m2_ck",
+ "dpll_dsp_m3x2_ck",
+};
+
+const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
+ "dpll_iva_ck",
+ "dpll_iva_m2_ck",
+};
+
+const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
+ "dpll_gpu_ck",
+ "dpll_gpu_m2_ck",
+};
+
+/* DSPEVE voltage domain */
+u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
+ {}, /*OPP_LOW */
+ {600000000, 600000000, 400000000}, /* OPP_NOM */
+ {700000000, 700000000, 466666667}, /* OPP_OD */
+ {750000000, 750000000, 500000000}, /* OPP_HIGH */
+};
+
+/* IVA voltage domain */
+u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
+ {}, /* OPP_LOW */
+ {1165000000, 388333334}, /* OPP_NOM */
+ {860000000, 430000000}, /* OPP_OD */
+ {1064000000, 532000000}, /* OPP_HIGH */
+};
+
+/* GPU voltage domain */
+u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
+ {}, /* OPP_LOW */
+ {1277000000, 425666667}, /* OPP_NOM */
+ {1000000000, 500000000}, /* OPP_OD */
+ {1064000000, 532000000}, /* OPP_HIGH */
+};
+
+static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
+{
+ int offs, node_offs, ret, i;
+ uint32_t phandle;
+
+ offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
+ if (offs < 0) {
+ debug("Could not find cm_core_aon clocks node path offset : %s\n",
+ fdt_strerror(offs));
+ return offs;
+ }
+
+ for (i = 0; i < num; i++) {
+ node_offs = fdt_subnode_offset(fdt, offs, names[i]);
+ if (node_offs < 0) {
+ debug("Could not find clock sub-node %s: %s\n",
+ names[i], fdt_strerror(node_offs));
+ return offs;
+ }
+
+ phandle = fdt_get_phandle(fdt, node_offs);
+ if (!phandle) {
+ debug("Could not find phandle for clock %s\n",
+ names[i]);
+ return -1;
+ }
+
+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
+ phandle);
+ if (ret < 0) {
+ debug("Could not add assigned-clocks property to clock node %s: %s\n",
+ names[i], fdt_strerror(ret));
+ return ret;
+ }
+
+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
+ rates[i]);
+ if (ret < 0) {
+ debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
+ names[i], fdt_strerror(ret));
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
+{
+ const char **clk_names;
+ u32 *clk_rates;
+ int ret;
+
+ if (!is_dra72x() && !is_dra7xx())
+ return;
+
+ /* fixup DSP clocks */
+ clk_names = dra7_opp_dsp_clk_names;
+ clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ /* fixup IVA clocks */
+ clk_names = dra7_opp_iva_clk_names;
+ clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ /* fixup GPU clocks */
+ clk_names = dra7_opp_gpu_clk_names;
+ clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+}
+#else
+static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
+#endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
+
/*
* Place for general cpu/SoC FDT fixups. Board specific
* fixups should remain in the board files which is where
void ft_cpu_setup(void *fdt, bd_t *bd)
{
ft_hs_fixups(fdt, bd);
+ ft_opp_clock_fixups(fdt, bd);
}
.gpio_en = 0,
};
+/* The LP8732 and LP8733 are software-compatible, use common struct */
+struct pmic_data lp8733 = {
+ .base_offset = LP873X_BUCK_BASE_VOLT_UV,
+ .step = 5000, /* 5 mV represented in uV */
+ /*
+ * Offset codes 0 - 0x13 Invalid.
+ * Offset codes 0x14 0x17 give 10mV steps
+ * Offset codes 0x17 through 0x9D give 5mV steps
+ * So let us start with our operating range from .73V
+ */
+ .start_code = 0x17,
+ .i2c_slave_addr = 0x60,
+ .pmic_bus_init = gpi2c_init,
+ .pmic_write = palmas_i2c_write_u8,
+};
+
struct vcores_data omap5430_volts = {
- .mpu.value = VDD_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
- .core.value = VDD_CORE,
+ .core.value[OPP_NOM] = VDD_CORE,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
- .mm.value = VDD_MM,
+ .mm.value[OPP_NOM] = VDD_MM,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
struct vcores_data omap5430_volts_es2 = {
- .mpu.value = VDD_MPU_ES2,
+ .mpu.value[OPP_NOM] = VDD_MPU_ES2,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_ES2,
+ .core.value[OPP_NOM] = VDD_CORE_ES2,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
- .mm.value = VDD_MM_ES2,
+ .mm.value[OPP_NOM] = VDD_MM_ES2,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
void enable_basic_uboot_clocks(void)
{
u32 const clk_domains_essential[] = {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
(*prcm)->cm_ipu_clkstctrl,
#endif
0
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
(*prcm)->cm_ipu_i2c5_clkctrl,
#else
(*prcm)->cm_l4per_i2c5_clkctrl,
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <palmas.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#endif
omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
}
+
+#if defined(CONFIG_PALMAS_POWER)
+void vmmc_pbias_config(uint voltage)
+{
+ u32 value = 0;
+ struct vcores_data const *vcores = *omap_vcores;
+
+ value = readl((*ctrl)->control_pbias);
+ value &= ~SDCARD_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(10); /* wait 10 us */
+ value &= ~SDCARD_BIAS_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+
+ if (vcores->core.pmic->i2c_slave_addr == 0x60) {
+ if (voltage == LDO_VOLT_3V0)
+ voltage = 0x19;
+ else if (voltage == LDO_VOLT_1V8)
+ voltage = 0xa;
+ lp873x_mmc1_poweron_ldo(voltage);
+ } else {
+ palmas_mmc1_poweron_ldo(voltage);
+ }
+
+ value = readl((*ctrl)->control_pbias);
+ value |= SDCARD_BIAS_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(150); /* wait 150 us */
+ value |= SDCARD_PWRDNZ;
+ writel(value, (*ctrl)->control_pbias);
+ udelay(150); /* wait 150 us */
+}
+#endif
#include <asm/omap_sec_common.h>
#include <asm/spl.h>
#include <spl.h>
+#include <asm/cache.h>
+#include <mapmem.h>
+#include <tee/optee.h>
/* Index for signature PPA-based TI HAL APIs */
#define PPA_HAL_SERVICES_START_INDEX (0x200)
+#define PPA_SERV_HAL_TEE_LOAD_MASTER (PPA_HAL_SERVICES_START_INDEX + 23)
+#define PPA_SERV_HAL_TEE_LOAD_SLAVE (PPA_HAL_SERVICES_START_INDEX + 24)
#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26)
#define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27)
+int tee_loaded = 0;
+
+/* Argument for PPA_SERV_HAL_TEE_LOAD_MASTER */
+struct ppa_tee_load_info {
+ u32 tee_sec_mem_start; /* Physical start address reserved for TEE */
+ u32 tee_sec_mem_size; /* Size of the memory reserved for TEE */
+ u32 tee_cert_start; /* Address where signed TEE binary is loaded */
+ u32 tee_cert_size; /* Size of TEE certificate (signed binary) */
+ u32 tee_jump_addr; /* Address to jump to start TEE execution */
+ u32 tee_arg0; /* argument to TEE jump function, in r0 */
+};
+
static u32 get_sec_mem_start(void)
{
u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
return result;
}
+
+static struct ppa_tee_load_info tee_info __aligned(ARCH_DMA_MINALIGN);
+
+int secure_tee_install(u32 addr)
+{
+ struct optee_header *hdr;
+ void *loadptr;
+ u32 tee_file_size;
+ u32 sec_mem_start = get_sec_mem_start();
+ const u32 size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
+ u32 *smc_cpu1_params;
+ u32 ret;
+
+ /* If there is no protected region, there is no place to put the TEE */
+ if (size == 0) {
+ printf("Error loading TEE, no protected memory region available\n");
+ return -ENOBUFS;
+ }
+
+ hdr = (struct optee_header *)map_sysmem(addr, sizeof(struct optee_header));
+ /* 280 bytes = size of signature */
+ tee_file_size = hdr->init_size + hdr->paged_size +
+ sizeof(struct optee_header) + 280;
+
+ if ((hdr->magic != OPTEE_MAGIC) ||
+ (hdr->version != OPTEE_VERSION) ||
+ (hdr->init_load_addr_hi != 0) ||
+ (hdr->init_load_addr_lo < (sec_mem_start + sizeof(struct optee_header))) ||
+ (tee_file_size > size) ||
+ ((hdr->init_load_addr_lo + tee_file_size - 1) >
+ (sec_mem_start + size - 1))) {
+ printf("Error in TEE header. Check load address and sizes\n");
+ unmap_sysmem(hdr);
+ return CMD_RET_FAILURE;
+ }
+
+ tee_info.tee_sec_mem_start = sec_mem_start;
+ tee_info.tee_sec_mem_size = size;
+ tee_info.tee_jump_addr = hdr->init_load_addr_lo;
+ tee_info.tee_cert_start = addr;
+ tee_info.tee_cert_size = tee_file_size;
+ tee_info.tee_arg0 = hdr->init_size + tee_info.tee_jump_addr;
+ unmap_sysmem(hdr);
+ loadptr = map_sysmem(addr, tee_file_size);
+
+ debug("tee_info.tee_sec_mem_start= %08X\n", tee_info.tee_sec_mem_start);
+ debug("tee_info.tee_sec_mem_size = %08X\n", tee_info.tee_sec_mem_size);
+ debug("tee_info.tee_jump_addr = %08X\n", tee_info.tee_jump_addr);
+ debug("tee_info.tee_cert_start = %08X\n", tee_info.tee_cert_start);
+ debug("tee_info.tee_cert_size = %08X\n", tee_info.tee_cert_size);
+ debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
+ debug("tee_file_size = %d\n", tee_file_size);
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ flush_dcache_range(
+ rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
+ roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
+
+ flush_dcache_range((u32)&tee_info, (u32)&tee_info +
+ roundup(sizeof(tee_info), ARCH_DMA_MINALIGN));
+#endif
+ unmap_sysmem(loadptr);
+
+ ret = secure_rom_call(PPA_SERV_HAL_TEE_LOAD_MASTER, 0, 0, 1, &tee_info);
+ if (ret) {
+ printf("TEE_LOAD_MASTER Failed\n");
+ return ret;
+ }
+ printf("TEE_LOAD_MASTER Done\n");
+
+ if (!is_dra72x()) {
+ /* Reuse the tee_info buffer for SMC params */
+ smc_cpu1_params = (u32 *)&tee_info;
+ smc_cpu1_params[0] = 0;
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
+ roundup(sizeof(u32), ARCH_DMA_MINALIGN));
+#endif
+ ret = omap_smc_sec_cpu1(PPA_SERV_HAL_TEE_LOAD_SLAVE, 0, 0,
+ smc_cpu1_params);
+ if (ret) {
+ printf("TEE_LOAD_SLAVE Failed\n");
+ return ret;
+ }
+ printf("TEE_LOAD_SLAVE Done\n");
+ }
+
+ tee_loaded = 1;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Secure entry function for CPU Core #1
+ *
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Harinarayan Bhatta <harinarayan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+#include <linux/linkage.h>
+
+.arch_extension sec
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+.global flush_dcache_range
+#endif
+
+#define AUX_CORE_BOOT_0 0x48281800
+#define AUX_CORE_BOOT_1 0x48281804
+
+#ifdef CONFIG_DRA7XX
+/* DRA7xx ROM code function "startup_BootSlave". This function is where CPU1
+ * waits on WFE, polling on AUX_CORE_BOOT_x registers.
+ * This address is same for J6 and J6 Eco.
+ */
+#define ROM_FXN_STARTUP_BOOTSLAVE 0x00038a64
+#endif
+
+/* Assembly core where CPU1 is woken up into
+ * No need to save-restore registers, does not use stack.
+ */
+LENTRY(cpu1_entry)
+ ldr r4, =omap_smc_sec_cpu1_args
+ ldm r4, {r0,r1,r2,r3} @ Retrieve args
+
+ mov r6, #0xFF @ Indicate new Task call
+ mov r12, #0x00 @ Secure Service ID in R12
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+
+ b .Lend @ exit at end of the service execution
+ nop
+
+ @ In case of IRQ happening in Secure, then ARM will branch here.
+ @ At that moment, IRQ will be pending and ARM will jump to Non Secure
+ @ IRQ handler
+ mov r12, #0xFE
+
+ dsb
+ dmb
+ smc 0 @ SMC #0 to enter monitor mode
+
+.Lend:
+ ldr r4, =omap_smc_sec_cpu1_args
+ str r0, [r4, #0x10] @ save return value
+ ldr r4, =AUX_CORE_BOOT_0
+ mov r5, #0x0
+ str r5, [r4]
+ ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE
+ sev @ Tell CPU0 we are done
+ bx r4 @ Jump back to ROM
+END(cpu1_entry)
+
+/*
+ * u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
+ *
+ * Makes a secure ROM/PPA call on CPU Core #1 on supported platforms.
+ * Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by
+ * u-boot.
+ */
+ENTRY(omap_smc_sec_cpu1)
+ push {r4, r5, lr}
+ ldr r4, =omap_smc_sec_cpu1_args
+ stm r4, {r0,r1,r2,r3} @ Save args to memory
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ mov r0, r4
+ mov r1, #CONFIG_SYS_CACHELINE_SIZE
+ add r1, r0, r1 @ dcache is not enabled on CPU1, so
+ blx flush_dcache_range @ flush the cache on args buffer
+#endif
+ ldr r4, =AUX_CORE_BOOT_1
+ ldr r5, =cpu1_entry
+ str r5, [r4] @ Setup CPU1 entry function
+ ldr r4, =AUX_CORE_BOOT_0
+ mov r5, #0x10
+ str r5, [r4] @ Tell ROM to exit while loop
+ sev @ Wake up CPU1
+.Lwait:
+ wfe @ Wait for CPU1 to finish
+ nop
+ ldr r5, [r4] @ Check if CPU1 is done
+ cmp r5, #0
+ bne .Lwait
+
+ ldr r4, =omap_smc_sec_cpu1_args
+ ldr r0, [r4, #0x10] @ Retrieve return value
+ pop {r4, r5, pc}
+ENDPROC(omap_smc_sec_cpu1)
+
+/*
+ * Buffer to save function arguments and return value for omap_smc_sec_cpu1
+ */
+.section .data
+omap_smc_sec_cpu1_args:
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ .balign CONFIG_SYS_CACHELINE_SIZE
+ .rept CONFIG_SYS_CACHELINE_SIZE/4
+ .word 0
+ .endr
+#else
+ .rept 5
+ .word 0
+ .endr
+#endif
+END(omap_smc_sec_cpu1_args)
DECLARE_GLOBAL_DATA_PTR;
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
int do_bootm_linux(int flag, int argc, char * const argv[],
bootm_headers_t *images)
{
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
+ select ROM_EXCEPTION_VECTORS
config TARGET_MALTA
bool "Support malta"
select SUPPORTS_CPU_MIPS64_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
+ select ROM_EXCEPTION_VECTORS
config TARGET_VCT
bool "Support vct"
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
config TARGET_DBAU1X00
bool "Support dbau1x00"
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_4KC
config TARGET_PB1X00
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_4KC
config ARCH_ATH79
select SUPPORTS_CPU_MIPS64_R1
select SUPPORTS_CPU_MIPS64_R2
select SUPPORTS_CPU_MIPS64_R6
+ select ROM_EXCEPTION_VECTORS
config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select MIPS_L1_CACHE_SHIFT_4
+ select ROM_EXCEPTION_VECTORS
help
This supports IMGTEC MIPSfpga platform
endchoice
+menu "General setup"
+
+config ROM_EXCEPTION_VECTORS
+ bool "Build U-Boot image with exception vectors"
+ help
+ Enable this to include exception vectors in the U-Boot image. This is
+ required if the U-Boot entry point is equal to the address of the
+ CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
+ U-Boot booted from parallel NOR flash).
+ Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
+ In that case the image size will be reduced by 0x500 bytes.
+
+endmenu
+
menu "OS boot interface"
config MIPS_BOOT_CMDLINE_LEGACY
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config MIPS_INIT_STACK_IN_SRAM
+ bool
+ default n
+ help
+ Select this if the initial stack frame could be setup in SRAM.
+ Normally the initial stack frame is set up in DRAM which is often
+ only available after lowlevel_init. With this option the initial
+ stack frame and the early C environment is set up before
+ lowlevel_init. Thus lowlevel_init does not need to be implemented
+ in assembler.
+
config SYS_DCACHE_SIZE
int
default 0
# define STATUS_SET ST0_KX
#endif
- /*
- * For the moment disable interrupts, mark the kernel mode and
- * set ST0_KX so that the CPU does not spit fire when using
- * 64-bit addresses.
- */
- .macro setup_c0_status set clr
- .set push
- mfc0 t0, CP0_STATUS
- or t0, ST0_CU0 | \set | 0x1f | \clr
- xor t0, 0x1f | \clr
- mtc0 t0, CP0_STATUS
- .set noreorder
- sll zero, 3 # ehb
- .set pop
+ .set noreorder
+
+ .macro init_wr sel
+ MTC0 zero, CP0_WATCHLO,\sel
+ mtc0 t1, CP0_WATCHHI,\sel
+ mfc0 t0, CP0_WATCHHI,\sel
+ bgez t0, wr_done
+ nop
.endm
- .set noreorder
+ .macro uhi_mips_exception
+ move k0, t9 # preserve t9 in k0
+ move k1, a0 # preserve a0 in k1
+ li t9, 15 # UHI exception operation
+ li a0, 0 # Use hard register context
+ sdbbp 1 # Invoke UHI operation
+ .endm
+
+ .macro setup_stack_gd
+ li t0, -16
+ PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
+ and sp, t1, t0 # force 16 byte alignment
+ PTR_SUBU \
+ sp, sp, GD_SIZE # reserve space for gd
+ and sp, sp, t0 # force 16 byte alignment
+ move k0, sp # save gd pointer
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ li t2, CONFIG_SYS_MALLOC_F_LEN
+ PTR_SUBU \
+ sp, sp, t2 # reserve space for early malloc
+ and sp, sp, t0 # force 16 byte alignment
+#endif
+ move fp, sp
+
+ /* Clear gd */
+ move t0, k0
+1:
+ PTR_S zero, 0(t0)
+ blt t0, t1, 1b
+ PTR_ADDIU t0, PTRSIZE
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
+#endif
+ .endm
ENTRY(_start)
/* U-Boot entry point */
b reset
- nop
+ mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
- .org 0x10
#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* initial configuration for that EBU in order to access the flash
* device with correct parameters. This config option is board-specific.
*/
+ .org 0x10
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x0
-#elif defined(CONFIG_MALTA)
+#endif
+#if defined(CONFIG_MALTA)
/*
* Linux expects the Board ID here.
*/
+ .org 0x10
.word 0x00000420 # 0x420 (Malta Board with CoreLV)
.word 0x00000000
#endif
+#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
+ /*
+ * Exception vector entry points. When running from ROM, an exception
+ * cannot be handled. Halt execution and transfer control to debugger,
+ * if one is attached.
+ */
.org 0x200
/* TLB refill, 32 bit task */
-1: b 1b
- nop
+ uhi_mips_exception
.org 0x280
/* XTLB refill, 64 bit task */
-1: b 1b
- nop
+ uhi_mips_exception
.org 0x300
/* Cache error exception */
-1: b 1b
- nop
+ uhi_mips_exception
.org 0x380
/* General exception */
-1: b 1b
- nop
+ uhi_mips_exception
.org 0x400
/* Catch interrupt exceptions */
-1: b 1b
- nop
+ uhi_mips_exception
.org 0x480
/* EJTAG debug exception */
1: b 1b
nop
- .align 4
+ .org 0x500
+#endif
+
reset:
#if __mips_isa_rev >= 6
mfc0 t0, CP0_CONFIG, 5
b 3b
nop
- /* Clear watch registers */
-4: MTC0 zero, CP0_WATCHLO
+ /* Init CP0 Status */
+4: mfc0 t0, CP0_STATUS
+ and t0, ST0_IMPL
+ or t0, ST0_BEV | ST0_ERL | STATUS_SET
+ mtc0 t0, CP0_STATUS
+
+ /*
+ * Check whether CP0 Config1 is implemented. If not continue
+ * with legacy Watch register initialization.
+ */
+ mfc0 t0, CP0_CONFIG
+ bgez t0, wr_legacy
+ nop
+
+ /*
+ * Check WR bit in CP0 Config1 to determine if Watch registers
+ * are implemented.
+ */
+ mfc0 t0, CP0_CONFIG, 1
+ andi t0, (1 << 3)
+ beqz t0, wr_done
+ nop
+
+ /* Clear Watch Status bits and disable watch exceptions */
+ li t1, 0x7 # Clear I, R and W conditions
+ init_wr 0
+ init_wr 1
+ init_wr 2
+ init_wr 3
+ init_wr 4
+ init_wr 5
+ init_wr 6
+ init_wr 7
+ b wr_done
+ nop
+
+wr_legacy:
+ MTC0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
- /* WP(Watch Pending), SW0/1 should be cleared */
+wr_done:
+ /* Clear WP, IV and SW interrupts */
mtc0 zero, CP0_CAUSE
- setup_c0_status STATUS_SET 0
-
- /* Init Timer */
- mtc0 zero, CP0_COUNT
+ /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
mtc0 zero, CP0_COMPARE
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
nop
#endif
+#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
+ /* Set up initial stack and global data */
+ setup_stack_gd
+#endif
+
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
# endif
#endif
- /* Set up temporary stack */
- li t0, -16
- PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
- and sp, t1, t0 # force 16 byte alignment
- PTR_SUBU \
- sp, sp, GD_SIZE # reserve space for gd
- and sp, sp, t0 # force 16 byte alignment
- move k0, sp # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
- li t2, CONFIG_SYS_MALLOC_F_LEN
- PTR_SUBU \
- sp, sp, t2 # reserve space for early malloc
- and sp, sp, t0 # force 16 byte alignment
-#endif
- move fp, sp
-
- /* Clear gd */
- move t0, k0
-1:
- PTR_S zero, 0(t0)
- blt t0, t1, 1b
- PTR_ADDIU t0, PTRSIZE
-
-#ifdef CONFIG_SYS_MALLOC_F_LEN
- PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
+#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
+ /* Set up initial stack and global data */
+ setup_stack_gd
#endif
move a0, zero # a0 <-- boot_flags = 0
PTR_LA t9, board_init_f
+
jr t9
move ra, zero
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <generated/asm-offsets.h>
*/
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+#ifndef __ASSEMBLY__
/**
* mips_cache_probe() - Probe the properties of the caches
*
* functions such as flush_cache may be called.
*/
void mips_cache_probe(void);
+#endif
#endif /* __MIPS_CACHE_H__ */
if (flags == MAP_NOCACHE)
return ioremap(paddr, len);
- return (void *)paddr;
+ return (void *)CKSEG0ADDR(paddr);
}
/*
#define STATUSF_IP14 (_ULCAST_(1) << 6)
#define STATUSB_IP15 7
#define STATUSF_IP15 (_ULCAST_(1) << 7)
+#define ST0_IMPL (_ULCAST_(3) << 16)
#define ST0_CH 0x00040000
#define ST0_NMI 0x00080000
#define ST0_SR 0x00100000
#define die_if_kernel(msg, regs) \
__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+static inline void execution_hazard_barrier(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n"
+ "ehb\n"
+ ".set reorder");
+}
+
#endif /* _ASM_SYSTEM_H */
#ifndef _U_BOOT_MIPS_H_
#define _U_BOOT_MIPS_H_
+void exc_handler(void);
+void except_vec3_generic(void);
+void except_vec_ejtag_debug(void);
+
#endif /* _U_BOOT_MIPS_H_ */
obj-y += cache.o
obj-y += cache_init.o
+obj-y += genex.o
+obj-y += stack.o
+obj-y += traps.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
--- /dev/null
+/*
+ * offset.c: Calculate pt_regs and task_struct offsets.
+ *
+ * Copyright (C) 1996 David S. Miller
+ * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ *
+ * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/ptrace.h>
+#include <linux/stddef.h>
+#include <linux/kbuild.h>
+
+void output_ptreg_defines(void)
+{
+ COMMENT("MIPS pt_regs offsets.");
+ OFFSET(PT_R0, pt_regs, regs[0]);
+ OFFSET(PT_R1, pt_regs, regs[1]);
+ OFFSET(PT_R2, pt_regs, regs[2]);
+ OFFSET(PT_R3, pt_regs, regs[3]);
+ OFFSET(PT_R4, pt_regs, regs[4]);
+ OFFSET(PT_R5, pt_regs, regs[5]);
+ OFFSET(PT_R6, pt_regs, regs[6]);
+ OFFSET(PT_R7, pt_regs, regs[7]);
+ OFFSET(PT_R8, pt_regs, regs[8]);
+ OFFSET(PT_R9, pt_regs, regs[9]);
+ OFFSET(PT_R10, pt_regs, regs[10]);
+ OFFSET(PT_R11, pt_regs, regs[11]);
+ OFFSET(PT_R12, pt_regs, regs[12]);
+ OFFSET(PT_R13, pt_regs, regs[13]);
+ OFFSET(PT_R14, pt_regs, regs[14]);
+ OFFSET(PT_R15, pt_regs, regs[15]);
+ OFFSET(PT_R16, pt_regs, regs[16]);
+ OFFSET(PT_R17, pt_regs, regs[17]);
+ OFFSET(PT_R18, pt_regs, regs[18]);
+ OFFSET(PT_R19, pt_regs, regs[19]);
+ OFFSET(PT_R20, pt_regs, regs[20]);
+ OFFSET(PT_R21, pt_regs, regs[21]);
+ OFFSET(PT_R22, pt_regs, regs[22]);
+ OFFSET(PT_R23, pt_regs, regs[23]);
+ OFFSET(PT_R24, pt_regs, regs[24]);
+ OFFSET(PT_R25, pt_regs, regs[25]);
+ OFFSET(PT_R26, pt_regs, regs[26]);
+ OFFSET(PT_R27, pt_regs, regs[27]);
+ OFFSET(PT_R28, pt_regs, regs[28]);
+ OFFSET(PT_R29, pt_regs, regs[29]);
+ OFFSET(PT_R30, pt_regs, regs[30]);
+ OFFSET(PT_R31, pt_regs, regs[31]);
+ OFFSET(PT_LO, pt_regs, lo);
+ OFFSET(PT_HI, pt_regs, hi);
+ OFFSET(PT_EPC, pt_regs, cp0_epc);
+ OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
+ OFFSET(PT_STATUS, pt_regs, cp0_status);
+ OFFSET(PT_CAUSE, pt_regs, cp0_cause);
+ DEFINE(PT_SIZE, sizeof(struct pt_regs));
+ BLANK();
+}
/* adjust sp by 4K to be safe */
sp -= 4096;
- lmb_reserve(lmb, sp, CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp);
+ lmb_reserve(lmb, sp, gd->ram_top - sp);
}
static void linux_cmdline_init(void)
#endif
}
-#ifdef CONFIG_ARCH_FIXUP_FDT
int arch_fixup_fdt(void *blob)
{
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
return 0;
#endif
}
-#endif
static int boot_setup_fdt(bootm_headers_t *images)
{
--- /dev/null
+/*
+ * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2002, 2007 Maciej W. Rozycki
+ * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/asm-offsets.h>
+
+#define STATMASK 0x1f
+
+ .set noreorder
+
+ /*
+ * Macros copied and adapted from Linux MIPS
+ */
+ .macro SAVE_AT
+ .set push
+ .set noat
+ LONG_S $1, PT_R1(sp)
+ .set pop
+ .endm
+
+ .macro SAVE_TEMP
+#if __mips_isa_rev < 6
+ mfhi v1
+#endif
+#ifdef CONFIG_32BIT
+ LONG_S $8, PT_R8(sp)
+ LONG_S $9, PT_R9(sp)
+#endif
+ LONG_S $10, PT_R10(sp)
+ LONG_S $11, PT_R11(sp)
+ LONG_S $12, PT_R12(sp)
+#if __mips_isa_rev < 6
+ LONG_S v1, PT_HI(sp)
+ mflo v1
+#endif
+ LONG_S $13, PT_R13(sp)
+ LONG_S $14, PT_R14(sp)
+ LONG_S $15, PT_R15(sp)
+ LONG_S $24, PT_R24(sp)
+#if __mips_isa_rev < 6
+ LONG_S v1, PT_LO(sp)
+#endif
+ .endm
+
+ .macro SAVE_STATIC
+ LONG_S $16, PT_R16(sp)
+ LONG_S $17, PT_R17(sp)
+ LONG_S $18, PT_R18(sp)
+ LONG_S $19, PT_R19(sp)
+ LONG_S $20, PT_R20(sp)
+ LONG_S $21, PT_R21(sp)
+ LONG_S $22, PT_R22(sp)
+ LONG_S $23, PT_R23(sp)
+ LONG_S $30, PT_R30(sp)
+ .endm
+
+ .macro SAVE_SOME
+ .set push
+ .set noat
+ PTR_SUBU k1, sp, PT_SIZE
+ LONG_S sp, PT_R29(k1)
+ move sp, k1
+
+ LONG_S $3, PT_R3(sp)
+ LONG_S $0, PT_R0(sp)
+ mfc0 v1, CP0_STATUS
+ LONG_S $2, PT_R2(sp)
+ LONG_S v1, PT_STATUS(sp)
+ LONG_S $4, PT_R4(sp)
+ mfc0 v1, CP0_CAUSE
+ LONG_S $5, PT_R5(sp)
+ LONG_S v1, PT_CAUSE(sp)
+ LONG_S $6, PT_R6(sp)
+ MFC0 v1, CP0_EPC
+ LONG_S $7, PT_R7(sp)
+#ifdef CONFIG_64BIT
+ LONG_S $8, PT_R8(sp)
+ LONG_S $9, PT_R9(sp)
+#endif
+ LONG_S v1, PT_EPC(sp)
+ LONG_S $25, PT_R25(sp)
+ LONG_S $28, PT_R28(sp)
+ LONG_S $31, PT_R31(sp)
+ .set pop
+ .endm
+
+ .macro RESTORE_AT
+ .set push
+ .set noat
+ LONG_L $1, PT_R1(sp)
+ .set pop
+ .endm
+
+ .macro RESTORE_TEMP
+#if __mips_isa_rev < 6
+ LONG_L $24, PT_LO(sp)
+ mtlo $24
+ LONG_L $24, PT_HI(sp)
+ mthi $24
+#endif
+#ifdef CONFIG_32BIT
+ LONG_L $8, PT_R8(sp)
+ LONG_L $9, PT_R9(sp)
+#endif
+ LONG_L $10, PT_R10(sp)
+ LONG_L $11, PT_R11(sp)
+ LONG_L $12, PT_R12(sp)
+ LONG_L $13, PT_R13(sp)
+ LONG_L $14, PT_R14(sp)
+ LONG_L $15, PT_R15(sp)
+ LONG_L $24, PT_R24(sp)
+ .endm
+
+ .macro RESTORE_STATIC
+ LONG_L $16, PT_R16(sp)
+ LONG_L $17, PT_R17(sp)
+ LONG_L $18, PT_R18(sp)
+ LONG_L $19, PT_R19(sp)
+ LONG_L $20, PT_R20(sp)
+ LONG_L $21, PT_R21(sp)
+ LONG_L $22, PT_R22(sp)
+ LONG_L $23, PT_R23(sp)
+ LONG_L $30, PT_R30(sp)
+ .endm
+
+ .macro RESTORE_SOME
+ .set push
+ .set reorder
+ .set noat
+ mfc0 a0, CP0_STATUS
+ ori a0, STATMASK
+ xori a0, STATMASK
+ mtc0 a0, CP0_STATUS
+ li v1, ST0_CU1 | ST0_FR | ST0_IM
+ and a0, v1
+ LONG_L v0, PT_STATUS(sp)
+ nor v1, $0, v1
+ and v0, v1
+ or v0, a0
+ mtc0 v0, CP0_STATUS
+ LONG_L v1, PT_EPC(sp)
+ MTC0 v1, CP0_EPC
+ LONG_L $31, PT_R31(sp)
+ LONG_L $28, PT_R28(sp)
+ LONG_L $25, PT_R25(sp)
+#ifdef CONFIG_64BIT
+ LONG_L $8, PT_R8(sp)
+ LONG_L $9, PT_R9(sp)
+#endif
+ LONG_L $7, PT_R7(sp)
+ LONG_L $6, PT_R6(sp)
+ LONG_L $5, PT_R5(sp)
+ LONG_L $4, PT_R4(sp)
+ LONG_L $3, PT_R3(sp)
+ LONG_L $2, PT_R2(sp)
+ .set pop
+ .endm
+
+ .macro RESTORE_SP
+ LONG_L sp, PT_R29(sp)
+ .endm
+
+NESTED(except_vec3_generic, 0, sp)
+ PTR_LA k1, handle_reserved
+ jr k1
+ nop
+ END(except_vec3_generic)
+
+NESTED(except_vec_ejtag_debug, 0, sp)
+ PTR_LA k1, handle_ejtag_debug
+ jr k1
+ nop
+ END(except_vec_ejtag_debug)
+
+NESTED(handle_reserved, PT_SIZE, sp)
+ SAVE_SOME
+ SAVE_AT
+ SAVE_TEMP
+ SAVE_STATIC
+
+ PTR_LA t9, do_reserved
+ jr t9
+ move a0, sp
+ END(handle_reserved)
+
+NESTED(handle_ejtag_debug, PT_SIZE, sp)
+ .set push
+ .set noat
+ MTC0 k1, CP0_DESAVE
+
+ /* Check for SDBBP */
+ MFC0 k1, CP0_DEBUG
+ sll k1, k1, 30
+ bgez k1, ejtag_return
+ nop
+
+ SAVE_SOME
+ SAVE_AT
+ SAVE_TEMP
+ SAVE_STATIC
+
+ PTR_LA t9, do_ejtag_debug
+ jalr t9
+ move a0, sp
+
+ RESTORE_TEMP
+ RESTORE_STATIC
+ RESTORE_AT
+ RESTORE_SOME
+ RESTORE_SP
+
+ejtag_return:
+ MFC0 k1, CP0_DESAVE
+ deret
+ .set pop
+ END(handle_ejtag_debug)
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_reserve_stacks(void)
+{
+ /* reserve space for exception vector table */
+ gd->start_addr_sp -= 0x500;
+ gd->start_addr_sp &= ~0xFFF;
+ gd->irq_sp = gd->start_addr_sp;
+ debug("Reserving %d Bytes for exception vector at: %08lx\n",
+ 0x500, gd->start_addr_sp);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
+ * Copyright (C) 1995, 1996 Paul M. Antoine
+ * Copyright (C) 1998 Ulf Carlsson
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
+ * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2014, Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void show_regs(const struct pt_regs *regs)
+{
+ const int field = 2 * sizeof(unsigned long);
+ unsigned int cause = regs->cp0_cause;
+ unsigned int exccode;
+ int i;
+
+ /*
+ * Saved main processor registers
+ */
+ for (i = 0; i < 32; ) {
+ if ((i % 4) == 0)
+ printf("$%2d :", i);
+ if (i == 0)
+ printf(" %0*lx", field, 0UL);
+ else if (i == 26 || i == 27)
+ printf(" %*s", field, "");
+ else
+ printf(" %0*lx", field, regs->regs[i]);
+
+ i++;
+ if ((i % 4) == 0)
+ puts("\n");
+ }
+
+ printf("Hi : %0*lx\n", field, regs->hi);
+ printf("Lo : %0*lx\n", field, regs->lo);
+
+ /*
+ * Saved cp0 registers
+ */
+ printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
+ field, regs->cp0_epc - gd->reloc_off);
+ printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
+ field, regs->regs[31] - gd->reloc_off);
+
+ printf("Status: %08x\n", (uint32_t) regs->cp0_status);
+
+ exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
+ printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
+
+ if (1 <= exccode && exccode <= 5)
+ printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
+
+ printf("PrId : %08x\n", read_c0_prid());
+}
+
+void do_reserved(const struct pt_regs *regs)
+{
+ puts("\nOoops:\n");
+ show_regs(regs);
+ hang();
+}
+
+void do_ejtag_debug(const struct pt_regs *regs)
+{
+ const int field = 2 * sizeof(unsigned long);
+ unsigned long depc;
+ unsigned int debug;
+
+ depc = read_c0_depc();
+ debug = read_c0_debug();
+
+ printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
+ field, depc, debug);
+}
+
+static void set_handler(unsigned long offset, void *addr, unsigned long size)
+{
+ unsigned long ebase = gd->irq_sp;
+
+ memcpy((void *)(ebase + offset), addr, size);
+ flush_cache(ebase + offset, size);
+}
+
+void trap_init(ulong reloc_addr)
+{
+ unsigned long ebase = gd->irq_sp;
+
+ set_handler(0x180, &except_vec3_generic, 0x80);
+ set_handler(0x280, &except_vec_ejtag_debug, 0x80);
+
+ write_c0_ebase(ebase);
+ clear_c0_status(ST0_BEV);
+ execution_hazard_barrier();
+}
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_24KC
help
This supports QCA/Atheros ar933x family SOCs.
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
+ select ROM_EXCEPTION_VECTORS
select MIPS_TUNE_24KC
help
This supports QCA/Atheros qca953x family SOCs.
select SUPPORTS_CPU_MIPS32_R2
select MIPS_L1_CACHE_SHIFT_4
select SYS_MIPS_CACHE_INIT_RAM_LOAD
+ select ROM_EXCEPTION_VECTORS
help
This supports Microchip PIC32MZ[DA] family of microcontrollers.
#define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024)
#endif
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
static void boot_jump_linux(bootm_headers_t *images)
{
void (*kernel)(bd_t *, ulong r4, ulong r5, ulong r6,
return ret;
}
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
# SPDX-License-Identifier: GPL-2.0+
#
-head-y := arch/sh/cpu/$(CPU)/start.o
+head-y := arch/sh/lib/start.o
libs-y += arch/sh/cpu/$(CPU)/
libs-y += arch/sh/lib/
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
-PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
+PLATFORM_RELFLAGS += -fpic
LDFLAGS_FINAL = --gc-sections
PLATFORM_RELFLAGS += -ffixed-r13
# SPDX-License-Identifier: GPL-2.0+
#
-extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o
{
return 0;
}
-
-void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
-{
- /* TODO(sh maintainer): Implement this */
- while (1);
-}
+++ /dev/null
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
-
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
- .text
- .align 2
-
- .global _start
-_sh_start:
- .long 0x00000010 /* Ppower ON reset PC*/
- .long 0x00000000
- .long 0x00000010 /* Manual reset PC */
- .long 0x00000000
-_init:
- mov.l ._lowlevel_init, r0
-100: bsrf r0
- nop
- bsr 1f
- nop
-1: sts pr, r5
- mov.l ._reloc_dst, r4
- add #(_sh_start-1b), r5
- mov.l ._reloc_dst_end, r6
-
-2: mov.l @r5+, r1
- mov.l r1, @r4
- add #4, r4
- cmp/hs r6, r4
- bf 2b
-
- mov.l ._bss_start, r4
- mov.l ._bss_end, r5
- mov #0, r1
-
-3: mov.l r1, @r4 /* bss clear */
- add #4, r4
- cmp/hs r5, r4
- bf 3b
-
- mov.l ._gd_init, r13 /* global data */
- mov.l ._stack_init, r15 /* stack */
-
- #TODO(sh maintainer): Fix this up to call the correct code
- #mov.l ._sh_generic_init, r0
- #jsr @r0
- nop
-
-loop:
- bra loop
-
- .align 2
-
-._lowlevel_init: .long (lowlevel_init - (100b + 4))
-._reloc_dst: .long reloc_dst
-._reloc_dst_end: .long reloc_dst_end
-._bss_start: .long bss_start
-._bss_end: .long bss_end
-._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
-._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-#._sh_generic_init: .long sh_generic_init
# SPDX-License-Identifier: GPL-2.0+
#
-extra-y = start.o
-obj-y = cpu.o interrupts.o watchdog.o cache.o
+obj-y = cpu.o interrupts.o watchdog.o
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-/*
- * Jump to P2 area.
- * When handling TLB or caches, we need to do it from P2 area.
- */
-#define jump_to_P2() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "mov.l 1f, %0\n\t" \
- "or %1, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy) \
- : "r" (0x20000000)); \
- } while (0)
-
-/*
- * Back to P1 area.
- */
-#define back_to_P1() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "nop;nop;nop;nop;nop;nop;nop\n\t" \
- "mov.l 1f, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy)); \
- } while (0)
-
-#define CACHE_VALID 1
-#define CACHE_UPDATED 2
-
-static inline void cache_wback_all(void)
-{
- unsigned long addr, data, i, j;
-
- jump_to_P2();
- for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
- for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
- addr = CACHE_OC_ADDRESS_ARRAY
- | (j << CACHE_OC_WAY_SHIFT)
- | (i << CACHE_OC_ENTRY_SHIFT);
- data = inl(addr);
- if (data & CACHE_UPDATED) {
- data &= ~CACHE_UPDATED;
- outl(data, addr);
- }
- }
- }
- back_to_P1();
-}
-
-
-#define CACHE_ENABLE 0
-#define CACHE_DISABLE 1
-
-int cache_control(unsigned int cmd)
-{
- unsigned long ccr;
-
- jump_to_P2();
- ccr = inl(CCR);
-
- if (ccr & CCR_CACHE_ENABLE)
- cache_wback_all();
-
- if (cmd == CACHE_DISABLE)
- outl(CCR_CACHE_STOP, CCR);
- else
- outl(CCR_CACHE_INIT, CCR);
- back_to_P1();
-
- return 0;
-}
{
return 0;
}
-
-void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
-{
- /* TODO(sh maintainer): Implement this */
- while (1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
- .text
- .align 2
-
- .global _start
-_sh_start:
- mov.l ._lowlevel_init, r0
-100: bsrf r0
- nop
-
- bsr 1f
- nop
-1: sts pr, r5
- mov.l ._reloc_dst, r4
- add #(_sh_start-1b), r5
- mov.l ._reloc_dst_end, r6
-
-2: mov.l @r5+, r1
- mov.l r1, @r4
- add #4, r4
- cmp/hs r6, r4
- bf 2b
-
- mov.l ._bss_start, r4
- mov.l ._bss_end, r5
- mov #0, r1
-
-3: mov.l r1, @r4 /* bss clear */
- add #4, r4
- cmp/hs r5, r4
- bf 3b
-
- mov.l ._gd_init, r13 /* global data */
- mov.l ._stack_init, r15 /* stack */
-
- #TODO(sh maintainer): Fix this up to call the correct code
- #mov.l ._sh_generic_init, r0
- #jsr @r0
- nop
-
-loop:
- bra loop
-
- .align 2
-
-._lowlevel_init: .long (lowlevel_init - (100b + 4))
-._reloc_dst: .long reloc_dst
-._reloc_dst_end: .long reloc_dst_end
-._bss_start: .long bss_start
-._bss_end: .long bss_end
-._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
-._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-#._sh_generic_init: .long sh_generic_init
# SPDX-License-Identifier: GPL-2.0+
#
-extra-y = start.o
obj-y = cpu.o interrupts.o watchdog.o cache.o
/*
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
-#include <asm/processor.h>
#include <asm/io.h>
-
-/*
- * Jump to P2 area.
- * When handling TLB or caches, we need to do it from P2 area.
- */
-#define jump_to_P2() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "mov.l 1f, %0\n\t" \
- "or %1, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy) \
- : "r" (0x20000000)); \
- } while (0)
-
-/*
- * Back to P1 area.
- */
-#define back_to_P1() \
- do { \
- unsigned long __dummy; \
- __asm__ __volatile__( \
- "nop;nop;nop;nop;nop;nop;nop\n\t" \
- "mov.l 1f, %0\n\t" \
- "jmp @%0\n\t" \
- " nop\n\t" \
- ".balign 4\n" \
- "1: .long 2f\n" \
- "2:" \
- : "=&r" (__dummy)); \
- } while (0)
+#include <asm/processor.h>
+#include <asm/system.h>
#define CACHE_VALID 1
#define CACHE_UPDATED 2
{
unsigned long addr, data, i, j;
- jump_to_P2();
- for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
+ for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
- addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+ addr = CACHE_OC_ADDRESS_ARRAY
+ | (j << CACHE_OC_WAY_SHIFT)
| (i << CACHE_OC_ENTRY_SHIFT);
data = inl(addr);
if (data & CACHE_UPDATED) {
}
}
}
- back_to_P1();
}
-
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
-int cache_control(unsigned int cmd)
+static int cache_control(unsigned int cmd)
{
unsigned long ccr;
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
- asm volatile ("ocbwb %0" : /* no output */
+ asm volatile ("ocbp %0" : /* no output */
: "m" (__m(v)));
}
}
: "m" (__m(v)));
}
}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ flush_dcache_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+ cache_control(CACHE_ENABLE);
+}
+
+void icache_disable(void)
+{
+ cache_control(CACHE_DISABLE);
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
#include <command.h>
#include <netdev.h>
#include <asm/processor.h>
-#include <asm/cache.h>
int checkcpu(void)
{
return 0;
}
-void flush_cache (unsigned long addr, unsigned long size)
-{
- invalidate_dcache_range(addr , addr + size);
-}
-
-void icache_enable (void)
-{
- cache_control(0);
-}
-
-void icache_disable (void)
-{
- cache_control(1);
-}
-
-int icache_status (void)
-{
- return 0;
-}
-
-void dcache_enable (void)
-{
-}
-
-void dcache_disable (void)
-{
-}
-
-int dcache_status (void)
-{
- return 0;
-}
-
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
#endif
return 0;
}
-
-void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
-{
- /* TODO(sh maintainer): Implement this */
- while (1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2007, 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
- .text
- .align 2
-
- .global _start
-_sh_start:
- mov.l ._lowlevel_init, r0
-100: bsrf r0
- nop
-
- bsr 1f
- nop
-1: sts pr, r5
- mov.l ._reloc_dst, r4
- add #(_sh_start-1b), r5
- mov.l ._reloc_dst_end, r6
-
-2: mov.l @r5+, r1
- mov.l r1, @r4
- add #4, r4
- cmp/hs r6, r4
- bf 2b
-
- mov.l ._bss_start, r4
- mov.l ._bss_end, r5
- mov #0, r1
-
-3: mov.l r1, @r4 /* bss clear */
- add #4, r4
- cmp/hs r5, r4
- bf 3b
-
- mov.l ._gd_init, r13 /* global data */
- mov.l ._stack_init, r15 /* stack */
-
- #TODO(sh maintainer): Fix this up to call the correct code
- #mov.l ._sh_generic_init, r0
- #jsr @r0
- nop
-
-loop:
- bra loop
-
- .align 2
-
-._lowlevel_init: .long (lowlevel_init - (100b + 4))
-._reloc_dst: .long reloc_dst
-._reloc_dst_end: .long reloc_dst_end
-._bss_start: .long bss_start
-._bss_end: .long bss_end
-._gd_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE)
-._stack_init: .long (_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-#._sh_generic_init: .long sh_generic_init
/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2008-2009
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
+ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ * Copyright (C) 2008 Mark Jonas <mark.jonas@de.bosch.com>
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "config.h"
+
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
+
+MEMORY
+{
+ ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE
+}
+
ENTRY(_start)
SECTIONS
{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
+ reloc_dst = .;
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
.text :
{
KEEP(*/start.o (.text))
+ KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text))
+ KEEP(*(.spiboot2.text))
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
- } =0xFF
+ } >ram =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
. = ALIGN(4);
- }
+ } >ram
PROVIDE (_etext = .);
{
*(.data)
. = ALIGN(4);
- }
+ } >ram
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
- *(.got)
+ *(.got.plt) *(.got)
. = ALIGN(4);
- }
+ } >ram
PROVIDE (_egot = .);
-
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
- }
+ } >ram
PROVIDE (__init_end = .);
PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
{
*(.bss)
. = ALIGN(4);
- }
+ } >ram
PROVIDE (bss_end = .);
-
PROVIDE (__bss_end = .);
}
#if defined(CONFIG_CPU_SH4)
-int cache_control(unsigned int cmd);
-
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __raw_base_readw(base, off) __arch_base_getw(base, off)
#define __raw_base_readl(base, off) __arch_base_getl(base, off)
-/*
- * Now, pick up the machine-defined IO definitions
- */
-#if 0 /* XXX###XXX */
-#include <asm/arch/io.h>
-#endif /* XXX###XXX */
-
/*
* IO port access primitives
* -------------------------
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
- * The machine specific io.h include defines __io to translate an "IO"
- * address to a memory address.
- *
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
# SPDX-License-Identifier: GPL-2.0+
#
+extra-y += start.o
+obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
ifeq ($(CONFIG_CPU_SH2),y)
obj-y += time_sh2.o
--- /dev/null
+/*
+ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
+{
+ void (*reloc_board_init_r)(gd_t *gd, ulong dest) = board_init_r;
+
+ if (new_gd->reloc_off) {
+ memcpy((void *)new_gd->relocaddr,
+ (void *)(new_gd->relocaddr - new_gd->reloc_off),
+ new_gd->mon_len);
+
+ reloc_board_init_r += new_gd->reloc_off;
+ }
+
+ __asm__ __volatile__("mov.l %0, r15\n" : : "m" (new_gd->start_addr_sp));
+
+ while (1)
+ reloc_board_init_r(new_gd, 0x0);
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2007, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+
+ .text
+ .align 2
+
+ .global _start
+_start:
+#ifdef CONFIG_CPU_SH2
+ .long 0x00000010 /* Ppower ON reset PC*/
+ .long 0x00000000
+ .long 0x00000010 /* Manual reset PC */
+ .long 0x00000000
+#endif
+ mov.l ._lowlevel_init, r0
+100: bsrf r0
+ nop
+
+ bsr 1f
+ nop
+1: sts pr, r5
+ mov.l ._reloc_dst, r4
+ add #(_start-1b), r5
+ mov.l ._reloc_dst_end, r6
+
+2: mov.l @r5+, r1
+ mov.l r1, @r4
+ add #4, r4
+ cmp/hs r6, r4
+ bf 2b
+
+ mov.l ._bss_start, r4
+ mov.l ._bss_end, r5
+ mov #0, r1
+
+3: mov.l r1, @r4 /* bss clear */
+ add #4, r4
+ cmp/hs r5, r4
+ bf 3b
+
+ mov.l ._gd_init, r13 /* global data */
+ mov.l ._stack_init, r15 /* stack */
+
+ mov.l ._sh_generic_init, r0
+ jsr @r0
+ mov #0, r4
+
+loop:
+ bra loop
+
+ .align 2
+
+._lowlevel_init: .long (lowlevel_init - (100b + 4))
+._reloc_dst: .long _start
+._reloc_dst_end: .long reloc_dst_end
+._bss_start: .long bss_start
+._bss_end: .long bss_end
+._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
+._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
+._sh_generic_init: .long board_init_f
#define COMMAND_LINE_OFFSET 0x9000
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
__weak void board_quiesce_devices(void)
{
}
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
#ifndef CONFIG_BOARD_EARLY_INIT_F
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
#define CCM_CCMR_CONFIG 0x003F4208
#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-#define ESDCTL_0x92220000 0x92220000
-#define ESDCTL_0xA2220000 0xA2220000
-#define ESDCTL_0xB2220000 0xB2220000
-#define ESDCTL_0x82228080 0x82228080
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_PRECHARGE 0x00000400
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5 0x00F49F00
static inline void dram_wait(unsigned int count)
{
return 0;
}
-static void board_setup_sdram_bank(u32 start_address)
-
-{
- struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
- u32 *cfg_reg, *ctl_reg;
- u32 val;
-
- switch (start_address) {
- case CSD0_BASE_ADDR:
- cfg_reg = &esdc->esdcfg0;
- ctl_reg = &esdc->esdctl0;
- break;
- case CSD1_BASE_ADDR:
- cfg_reg = &esdc->esdcfg1;
- ctl_reg = &esdc->esdctl1;
- break;
- default:
- return;
- }
-
- /* Initialize MISC register for DDR2 */
- val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
- ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
- writel(val, &esdc->esdmisc);
- val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
- writel(val, &esdc->esdmisc);
-
- /*
- * according to DDR2 specs, wait a while before
- * the PRECHARGE_ALL command
- */
- dram_wait(0x20000);
-
- /* Load DDR2 config and timing */
- writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
- /* Precharge ALL */
- writel(ESDCTL_0x92220000,
- ctl_reg);
- writel(0xda, start_address + ESDCTL_PRECHARGE);
-
- /* Load mode */
- writel(ESDCTL_0xB2220000,
- ctl_reg);
- writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
- writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
- writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
- /* Precharge ALL */
- writel(ESDCTL_0x92220000,
- ctl_reg);
- writel(0xda, start_address + ESDCTL_PRECHARGE);
-
- /* Set mode auto refresh : at least two refresh are required */
- writel(ESDCTL_0xA2220000,
- ctl_reg);
- writel(0xda, start_address);
- writel(0xda, start_address);
-
- writel(ESDCTL_0xB2220000,
- ctl_reg);
- writeb(0xda, start_address + ESDCTL_DDR2_MR);
- writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
- /* OCD mode exit */
- writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
- /* Set normal mode */
- writel(ESDCTL_0x82228080,
- ctl_reg);
-
- dram_wait(0x20000);
-
- /* Do not set delay lines, only for MDDR */
-}
-
static void board_setup_sdram(void)
{
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
writel(0x2000, &esdc->esdctl0);
writel(0x2000, &esdc->esdctl1);
- board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+ 13, 10, 2, 0x8080);
}
static void setup_iomux_uart3(void)
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* GPIO used to power off ethernet */
+ MX35_PAD_STXFS4__GPIO2_31,
};
/* setup pins for FEC */
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ /* Enable power for ethernet */
+ gpio_direction_output(63, 0);
+
+ udelay(2000);
+
return 0;
}
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ struct node_info nodes[] = {
+ { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
+ { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+ };
+
+ if (getenv("fdt_noauto")) {
+ puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
+ return 0;
+ }
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+ return 0;
+}
# SPDX-License-Identifier: GPL-2.0+
obj-y := ap_sh4a_4a.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <netdev.h>
#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODEMR (0xFFCC0020)
#define MODEMR_MASK (0x6)
#define MODEMR_533MHZ (0x2)
return 0;
}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
+++ /dev/null
-Summary
-=======
-This README assumes you have read README.da850. It contains some additional
-information specific to building the omapl138-lcdk. The AIS file as generated
-by the build is, currently, not useable due to differences in the flash
-available on this board, as compared to the da850evm boards.
-
-Flash Differences
-=================
-Refer to the discussion in [1] for more detail - basically the da850evm uses
-SPI flash whereas the lcdk uses NAND flash to store the bootloader, and
-the support isn't there in the SPL code.
-
-It should be possible to add the support in the SPL code should someone be
-sufficiently motivated.
-
-Using the built image
-=====================
-The output image to use is u-boot.bin. This needs to be converted to an
-AIS file as described in [1] and then flashed using the utitilty linked to
-there and also described in README.da850. You _may_ be able to write using
-u-boot itself, but the commands in README.da850 won't work as they write to
-SPI rather than NAND.
-
-Links
-=====
-[1]
- http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/386829
\ No newline at end of file
memcmp(env_enetaddr, buff, 6))
printf("Warning: MAC address in SPI flash don't match "
"with the MAC address in the environment\n");
- printf("Default using MAC address from environment\n");
+ printf("Default using MAC address from environment\n");
}
#endif
uint8_t enetaddr[8];
if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
printf("Warning: MAC address in EEPROM don't match "
"with the MAC address in the environment\n");
- printf("Default using MAC address from environment\n");
+ printf("Default using MAC address from environment\n");
}
#endif
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+ .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
+
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
#
obj-y := espt.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: ESPT-GIGA\n");
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+#define SPI_PAD_CTRL \
+ (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
+
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
};
#endif
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+ MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+}
+
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
board_qspi_init();
#endif
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+
return 0;
}
};
#endif
+void pmic_init(void)
+{
+#define I2C_PMIC 0x2
+#define DA9063_I2C_ADDR 0x58
+#define DA9063_REG_BCORE2_CFG 0x9D
+#define DA9063_REG_BCORE1_CFG 0x9E
+#define DA9063_REG_BPRO_CFG 0x9F
+#define DA9063_REG_BIO_CFG 0xA0
+#define DA9063_REG_BMEM_CFG 0xA1
+#define DA9063_REG_BPERI_CFG 0xA2
+#define DA9063_BUCK_MODE_MASK 0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP 0x40
+#define DA9063_BUCK_MODE_SYNC 0x80
+#define DA9063_BUCK_MODE_AUTO 0xC0
+
+ uchar val;
+
+ i2c_set_bus_num(I2C_PMIC);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+}
+
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
pwm_enable(0);
#endif
+ /* board specific pmic init */
+ pmic_init();
+
return 0;
}
/* Perform DDR DRAM calibration */
udelay(100);
- mmdc_do_write_level_calibration();
- mmdc_do_dqs_calibration();
+ mmdc_do_write_level_calibration(&novena_ddr_info);
+ mmdc_do_dqs_calibration(&novena_ddr_info);
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
return (1);
}
#endif /* defined(CONFIG_PATI) */
-
-#elif defined(CONFIG_VCMA9)
- start = 0;
-
- /* search end sector */
- for (i = 0; i < info->sector_count; i++)
- if (size < info->start[i])
- break;
-
- flash_protect(FLAG_PROTECT_CLEAR,
- start,
- size,
- info);
-
- /* now erase flash */
- printf("Erasing at %lx (sector %d) (start %lx)\n",
- start,0,info->start[0]);
- if ((rc = flash_erase (info, 0, i)) != 0) {
- puts("ERROR ");
- flash_perror(rc);
- return (1);
- }
-
#endif
printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
(ulong)src, size);
+++ /dev/null
-if TARGET_VCMA9
-
-config SYS_BOARD
- default "vcma9"
-
-config SYS_VENDOR
- default "mpl"
-
-config SYS_SOC
- default "s3c24x0"
-
-config SYS_CONFIG_NAME
- default "VCMA9"
-
-endif
+++ /dev/null
-VCMA9 BOARD
-M: David Müller <d.mueller@elsoft.ch>
-S: Maintained
-F: board/mpl/vcma9/
-F: include/configs/VCMA9.h
-F: configs/VCMA9_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ../common/common_util.o
-obj-y += vcma9.o cmd_vcma9.o
-
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * adapted for VCMA9
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "vcma9.h"
-#include "../common/common_util.h"
-
-#if defined(CONFIG_CS8900)
-#include <../drivers/net/cs8900.h>
-
-static uchar cs8900_chksum(ushort data)
-{
- return((data >> 8) & 0x00FF) + (data & 0x00FF);
-}
-
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct eth_device *dev;
- char cs8900_name[10];
- if (strcmp(argv[1], "info") == 0)
- {
- vcma9_print_info();
- return 0;
- }
-#if defined(CONFIG_CS8900)
- if (strcmp(argv[1], "cs8900") == 0) {
- sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME);
- dev = eth_get_dev_by_name(cs8900_name);
- if (!dev) {
- printf("Couldn't find CS8900 driver");
- return 0;
- }
- if (strcmp(argv[2], "read") == 0) {
- uchar addr; ushort data;
-
- addr = simple_strtoul(argv[3], NULL, 16);
- cs8900_e2prom_read(dev, addr, &data);
- printf("0x%2.2X: 0x%4.4X\n", addr, data);
- } else if (strcmp(argv[2], "write") == 0) {
- uchar addr; ushort data;
-
- addr = simple_strtoul(argv[3], NULL, 16);
- data = simple_strtoul(argv[4], NULL, 16);
- cs8900_e2prom_write(dev, addr, data);
- } else if (strcmp(argv[2], "setaddr") == 0) {
- uchar addr, i, csum; ushort data;
- uchar ethaddr[6];
-
- /* check for valid ethaddr */
- if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
- addr = 1;
- data = 0x2158;
- cs8900_e2prom_write(dev, addr, data);
- csum = cs8900_chksum(data);
- addr++;
- for (i = 0; i < 6; i+=2) {
- data = ethaddr[i+1] << 8 |
- ethaddr[i];
- cs8900_e2prom_write(dev, addr, data);
- csum += cs8900_chksum(data);
- addr++;
- }
- /* calculate header link byte */
- data = 0xA100 | (addr * 2);
- cs8900_e2prom_write(dev, 0, data);
- csum += cs8900_chksum(data);
- /* write checksum word */
- cs8900_e2prom_write(dev, addr, (0 - csum) << 8);
- } else {
- puts("\nplease defined 'ethaddr'\n");
- }
- } else if (strcmp(argv[2], "dump") == 0) {
- uchar addr = 0, endaddr, csum; ushort data;
-
- puts("Dump of CS8900 config device: ");
- cs8900_e2prom_read(dev, addr, &data);
- if ((data & 0xE000) == 0xA000) {
- endaddr = (data & 0x00FF) / 2;
- csum = cs8900_chksum(data);
- for (addr = 1; addr <= endaddr; addr++) {
- cs8900_e2prom_read(dev, addr, &data);
- printf("\n0x%2.2X: 0x%4.4X", addr, data);
- csum += cs8900_chksum(data);
- }
- printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
- } else {
- puts("no valid config found");
- }
- puts("\n");
- }
-
- return 0;
- }
-#endif
-
- return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-
-U_BOOT_CMD(
- vcma9, 6, 1, do_vcma9,
- "VCMA9 specific commands",
- "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
- "vcma9 info - displays board information"
-);
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for MPL VCMA9 by
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- * (C) Copyright 2002, 2003, 2004, 2005
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-
-/* register definitions */
-
-#define PLD_BASE 0x28000000
-#define MISC_REG 0x103
-#define SDRAM_REG 0x106
-#define BWSCON 0x48000000
-#define CLKBASE 0x4C000000
-#define LOCKTIME 0x0
-#define MPLLCON 0x4
-#define UPLLCON 0x8
-#define GPIOBASE 0x56000000
-#define GSTATUS1 0xB0
-#define FASTCPU 0x02
-
-/* some parameters for the board */
-/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-/* BANKSIZE */
-#define BURST_EN (0x1<<7)
-
-/* BANK0CON 200 */
-#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
-#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
-#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
-#define B0_Tcoh_200 0x0 /* 0clk */
-#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
-#define B0_Tacp_200 0x0 /* page mode is not used */
-#define B0_PMC_200 0x0 /* page mode disabled */
-
-/* BANK0CON 250 */
-#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
-#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
-#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
-#define B0_Tcoh_250 0x0 /* 0clk */
-#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
-#define B0_Tacp_250 0x0 /* page mode is not used */
-#define B0_PMC_250 0x0 /* page mode disabled */
-
-/* BANK0CON 266 */
-#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
-#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
-#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
-#define B0_Tcoh_266 0x0 /* 0clk */
-#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
-#define B0_Tacp_266 0x0 /* page mode is not used */
-#define B0_PMC_266 0x0 /* page mode disabled */
-
-/* BANK1CON 200 */
-#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
-#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
-#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
-#define B1_Tcoh_200 0x0 /* 0clk */
-#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
-#define B1_Tacp_200 0x0 /* page mode is not used */
-#define B1_PMC_200 0x0 /* page mode disabled */
-
-/* BANK1CON 250 */
-#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
-#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
-#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
-#define B1_Tcoh_250 0x0 /* 0clk */
-#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
-#define B1_Tacp_250 0x0 /* page mode is not used */
-#define B1_PMC_250 0x0 /* page mode disabled */
-
-/* BANK1CON 266 */
-#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
-#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
-#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
-#define B1_Tcoh_266 0x0 /* 0clk */
-#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
-#define B1_Tacp_266 0x0 /* page mode is not used */
-#define B1_PMC_266 0x0 /* page mode disabled */
-
-/* BANK2CON 200 + 250 + 266 */
-#define B2_Tacs 0x3 /* 4clk */
-#define B2_Tcos 0x3 /* 4clk */
-#define B2_Tacc 0x7 /* 14clk */
-#define B2_Tcoh 0x3 /* 4clk */
-#define B2_Tcah 0x3 /* 4clk */
-#define B2_Tacp 0x0 /* page mode is not used */
-#define B2_PMC 0x0 /* page mode disabled */
-
-/* BANK3CON 200 + 250 + 266 */
-#define B3_Tacs 0x3 /* 4clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x3 /* 4clk */
-#define B3_Tcah 0x3 /* 4clk */
-#define B3_Tacp 0x0 /* page mode is not used */
-#define B3_PMC 0x0 /* page mode disabled */
-
-/* BANK4CON 200 */
-#define B4_Tacs_200 0x1 /* 1clk */
-#define B4_Tcos_200 0x3 /* 4clk */
-#define B4_Tacc_200 0x7 /* 14clk */
-#define B4_Tcoh_200 0x3 /* 4clk */
-#define B4_Tcah_200 0x2 /* 2clk */
-#define B4_Tacp_200 0x0 /* page mode is not used */
-#define B4_PMC_200 0x0 /* page mode disabled */
-
-/* BANK4CON 250 */
-#define B4_Tacs_250 0x1 /* 1clk */
-#define B4_Tcos_250 0x3 /* 4clk */
-#define B4_Tacc_250 0x7 /* 14clk */
-#define B4_Tcoh_250 0x3 /* 4clk */
-#define B4_Tcah_250 0x2 /* 2clk */
-#define B4_Tacp_250 0x0 /* page mode is not used */
-#define B4_PMC_250 0x0 /* page mode disabled */
-
-/* BANK4CON 266 */
-#define B4_Tacs_266 0x1 /* 1clk */
-#define B4_Tcos_266 0x3 /* 4clk */
-#define B4_Tacc_266 0x7 /* 14clk */
-#define B4_Tcoh_266 0x3 /* 4clk */
-#define B4_Tcah_266 0x2 /* 2clk */
-#define B4_Tacp_266 0x0 /* page mode is not used */
-#define B4_PMC_266 0x0 /* page mode disabled */
-
-/* BANK5CON 200 */
-#define B5_Tacs_200 0x0 /* 0clk */
-#define B5_Tcos_200 0x3 /* 4clk */
-#define B5_Tacc_200 0x4 /* 6clk */
-#define B5_Tcoh_200 0x3 /* 4clk */
-#define B5_Tcah_200 0x1 /* 1clk */
-#define B5_Tacp_200 0x0 /* page mode is not used */
-#define B5_PMC_200 0x0 /* page mode disabled */
-
-/* BANK5CON 250 */
-#define B5_Tacs_250 0x0 /* 0clk */
-#define B5_Tcos_250 0x3 /* 4clk */
-#define B5_Tacc_250 0x5 /* 8clk */
-#define B5_Tcoh_250 0x3 /* 4clk */
-#define B5_Tcah_250 0x1 /* 1clk */
-#define B5_Tacp_250 0x0 /* page mode is not used */
-#define B5_PMC_250 0x0 /* page mode disabled */
-
-/* BANK5CON 266 */
-#define B5_Tacs_266 0x0 /* 0clk */
-#define B5_Tcos_266 0x3 /* 4clk */
-#define B5_Tacc_266 0x5 /* 8clk */
-#define B5_Tcoh_266 0x3 /* 4clk */
-#define B5_Tcah_266 0x1 /* 1clk */
-#define B5_Tacp_266 0x0 /* page mode is not used */
-#define B5_PMC_266 0x0 /* page mode disabled */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd_200 0x0 /* 2clk */
-#define B6_Trcd_250 0x1 /* 3clk */
-#define B6_Trcd_266 0x1 /* 3clk */
-#define B6_SCAN 0x2 /* 10bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd_200 0x0 /* 2clk */
-#define B7_Trcd_250 0x1 /* 3clk */
-#define B7_Trcd_266 0x1 /* 3clk */
-#define B7_SCAN 0x2 /* 10bit */
-
-/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp_200 0x0 /* 2clk */
-#define Trp_250 0x1 /* 3clk */
-#define Trp_266 0x1 /* 3clk */
-#define Tsrc_200 0x1 /* 5clk */
-#define Tsrc_250 0x2 /* 6clk */
-#define Tsrc_266 0x3 /* 7clk */
-
-/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
-#define REFCNT_200 489
-/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
-#define REFCNT_250 99
-/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
-#define REFCNT_266 0
-/**************************************/
-
-.globl lowlevel_init
-lowlevel_init:
- /* use r0 to relocate DATA read/write to flash rather than memory ! */
- ldr r0, =CONFIG_SYS_TEXT_BASE
- ldr r13, =BWSCON
-
- /* enable minimal access to PLD */
- ldr r1, [r13] /* load default BWSCON */
- orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
- str r1, [r13] /* set BWSCON */
- ldr r1, =0x7FF0 /* select slowest timing */
- str r1, [r13, #0x18] /* set BANKCON5 */
-
- ldr r1, =PLD_BASE
- ldr r2, =SETUPDATA
- ldrb r1, [r1, #MISC_REG]
- sub r2, r2, r0
- tst r1, #FASTCPU /* FASTCPU available ? */
- addeq r2, r2, #SETUPENTRY_SIZE
-
- /* memory control configuration */
- /* r2 = pointer into timing table */
- /* r13 = pointer to MEM controller regs (starting with BWSCON) */
- add r3, r2, #CSDATA_OFFSET
- add r4, r3, #CSDATAENTRY_SIZE
-0:
- ldr r1, [r3], #4
- str r1, [r13], #4
- cmp r3, r4
- bne 0b
-
- /* PLD access is now possible */
- /* r3 = SDRAMDATA */
- /* r13 = pointer to MEM controller regs */
- ldr r1, =PLD_BASE
- mov r4, #SDRAMENTRY_SIZE
- ldrb r1, [r1, #SDRAM_REG]
- /* calculate start and end point */
- mla r3, r4, r1, r3
- add r4, r3, r4
-0:
- ldr r1, [r3], #4
- str r1, [r13], #4
- cmp r3, r4
- bne 0b
-
- /* setup MPLL registers */
- ldr r1, =CLKBASE
- ldr r4, =0xFFFFFF
- add r3, r2, #4 /* r3 points to PLL values */
- str r4, [r1, #LOCKTIME]
- ldmia r3, {r4,r5}
- str r5, [r1, #UPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subs r3, r3, #1
- bne 0b
-
- str r4, [r1, #MPLLCON] /* writing PLL register */
- /* !! order seems to be important !! */
- /* a little delay */
- ldr r3, =0x4000
-0:
- subs r3, r3, #1
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
- ((bws1) << 4) + \
- ((bws2) << 8) + \
- ((bws3) << 12) + \
- ((bws4) << 16) + \
- ((bws5) << 20) + \
- ((bws6) << 24) + \
- ((bws7) << 28)
-
-#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
- ((tacs) << 13) + \
- ((tcos) << 11) + \
- ((tacc) << 8) + \
- ((tcoh) << 6) + \
- ((tcah) << 4) + \
- ((tacp) << 2) + \
- (pmc)
-
-#define MK_BANKCON_SDRAM(trcd, scan) \
- ((0x03) << 15) + \
- ((trcd) << 2) + \
- (scan)
-
-#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
- ((enable) << 23) + \
- ((trefmd) << 22) + \
- ((trp) << 20) + \
- ((tsrc) << 18) + \
- (cnt)
-
-SETUPDATA:
- .word 0x32410002
- /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
- .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
- /* PLL values for USB clock */
- .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
-
- /* timing for 250 MHz*/
-0:
- .equiv CSDATA_OFFSET, (. - SETUPDATA)
- .word MK_BWSCON(DW16, \
- DW32, \
- DW32, \
- DW16 + WAIT + UBLB, \
- DW8 + UBLB, \
- DW32, \
- DW32)
-
- .word MK_BANKCON(B0_Tacs_250, \
- B0_Tcos_250, \
- B0_Tacc_250, \
- B0_Tcoh_250, \
- B0_Tcah_250, \
- B0_Tacp_250, \
- B0_PMC_250)
-
- .word MK_BANKCON(B1_Tacs_250, \
- B1_Tcos_250, \
- B1_Tacc_250, \
- B1_Tcoh_250, \
- B1_Tcah_250, \
- B1_Tacp_250, \
- B1_PMC_250)
-
- .word MK_BANKCON(B2_Tacs, \
- B2_Tcos, \
- B2_Tacc, \
- B2_Tcoh, \
- B2_Tcah, \
- B2_Tacp, \
- B2_PMC)
-
- .word MK_BANKCON(B3_Tacs, \
- B3_Tcos, \
- B3_Tacc, \
- B3_Tcoh, \
- B3_Tcah, \
- B3_Tacp, \
- B3_PMC)
-
- .word MK_BANKCON(B4_Tacs_250, \
- B4_Tcos_250, \
- B4_Tacc_250, \
- B4_Tcoh_250, \
- B4_Tcah_250, \
- B4_Tacp_250, \
- B4_PMC_250)
-
- .word MK_BANKCON(B5_Tacs_250, \
- B5_Tcos_250, \
- B5_Tacc_250, \
- B5_Tcoh_250, \
- B5_Tcah_250, \
- B5_Tacp_250, \
- B5_PMC_250)
-
- .equiv CSDATAENTRY_SIZE, (. - 0b)
- /* 4Mx8x4 */
-0:
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
- .equiv SDRAMENTRY_SIZE, (. - 0b)
-
- /* 8Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 2Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 4Mx8x2 */
- .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- .equiv SETUPENTRY_SIZE, (. - SETUPDATA)
-
- .word 0x32410000
- /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
- .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
- /* PLL values for USB clock */
- .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
-
- /* timing for 200 MHz and default*/
- .word MK_BWSCON(DW16, \
- DW32, \
- DW32, \
- DW16 + WAIT + UBLB, \
- DW8 + UBLB, \
- DW32, \
- DW32)
-
- .word MK_BANKCON(B0_Tacs_200, \
- B0_Tcos_200, \
- B0_Tacc_200, \
- B0_Tcoh_200, \
- B0_Tcah_200, \
- B0_Tacp_200, \
- B0_PMC_200)
-
- .word MK_BANKCON(B1_Tacs_200, \
- B1_Tcos_200, \
- B1_Tacc_200, \
- B1_Tcoh_200, \
- B1_Tcah_200, \
- B1_Tacp_200, \
- B1_PMC_200)
-
- .word MK_BANKCON(B2_Tacs, \
- B2_Tcos, \
- B2_Tacc, \
- B2_Tcoh, \
- B2_Tcah, \
- B2_Tacp, \
- B2_PMC)
-
- .word MK_BANKCON(B3_Tacs, \
- B3_Tcos, \
- B3_Tacc, \
- B3_Tcoh, \
- B3_Tcah, \
- B3_Tacp, \
- B3_PMC)
-
- .word MK_BANKCON(B4_Tacs_200, \
- B4_Tcos_200, \
- B4_Tacc_200, \
- B4_Tcoh_200, \
- B4_Tcah_200, \
- B4_Tacp_200, \
- B4_PMC_200)
-
- .word MK_BANKCON(B5_Tacs_200, \
- B5_Tcos_200, \
- B5_Tacc_200, \
- B5_Tcoh_200, \
- B5_Tcah_200, \
- B5_Tacp_200, \
- B5_PMC_200)
-
- /* 4Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 8Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 2Mx8x4 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- /* 4Mx8x2 */
- .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
- .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
- .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
- .word 0x32 + BURST_EN
- .word 0x30
- .word 0x30
-
- .equiv SETUPDATA_SIZE, (. - SETUPDATA)
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002, 2010
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#include "vcma9.h"
-#include "../common/common_util.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- /* set up the I/O ports */
- writel(0x007FFFFF, &gpio->gpacon);
- writel(0x002AAAAA, &gpio->gpbcon);
- writel(0x000002BF, &gpio->gpbup);
- writel(0xAAAAAAAA, &gpio->gpccon);
- writel(0x0000FFFF, &gpio->gpcup);
- writel(0xAAAAAAAA, &gpio->gpdcon);
- writel(0x0000FFFF, &gpio->gpdup);
- writel(0xAAAAAAAA, &gpio->gpecon);
- writel(0x000037F7, &gpio->gpeup);
- writel(0x00000000, &gpio->gpfcon);
- writel(0x00000000, &gpio->gpfup);
- writel(0xFFEAFF5A, &gpio->gpgcon);
- writel(0x0000F0DC, &gpio->gpgup);
- writel(0x0028AAAA, &gpio->gphcon);
- writel(0x00000656, &gpio->gphup);
-
- /* setup correct IRQ modes for NIC (rising edge mode) */
- writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2);
-
- /* select USB port 2 to be host or device (setup as host for now) */
- writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x30000100;
-
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-
-/*
- * Get some Board/PLD Info
- */
-
-static u8 get_pld_reg(enum vcma9_pld_regs reg)
-{
- return readb(VCMA9_PLD_BASE + reg);
-}
-
-static u8 get_pld_version(void)
-{
- return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
-}
-
-static u8 get_pld_revision(void)
-{
- return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
-}
-
-static uchar get_board_pcb(void)
-{
- return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
-}
-
-static u8 get_nr_chips(void)
-{
- switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
- case 0: return 4;
- case 1: return 1;
- case 2: return 2;
- default: return 0;
- }
-}
-
-static ulong get_chip_size(void)
-{
- switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
- case 0: return 16 * (1024*1024);
- case 1: return 32 * (1024*1024);
- case 2: return 8 * (1024*1024);
- case 3: return 8 * (1024*1024);
- default: return 0;
- }
-}
-
-static const char *get_chip_geom(void)
-{
- switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
- case 0: return "4Mx8x4";
- case 1: return "8Mx8x4";
- case 2: return "2Mx8x4";
- case 3: return "4Mx8x2";
- default: return "unknown";
- }
-}
-
-static void vcma9_show_info(char *board_name, char *serial)
-{
- printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
- board_name, serial,
- get_board_pcb(), get_pld_version(), get_pld_revision());
- printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_chip_size() * get_nr_chips();
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
- char s[50];
- int i;
- backup_t *b = (backup_t *) s;
-
- i = getenv_f("serial#", s, 32);
- if ((i < 0) || strncmp (s, "VCMA9", 5)) {
- get_backup_values (b);
- if (strncmp (b->signature, "MPL\0", 4) != 0) {
- puts ("### No HW ID - assuming VCMA9");
- } else {
- b->serial_name[5] = 0;
- vcma9_show_info(b->serial_name, &b->serial_name[6]);
- }
- } else {
- s[5] = 0;
- vcma9_show_info(s, &s[6]);
- }
-
- return 0;
-}
-
-int board_late_init(void)
-{
- /*
- * check if environment is healthy, otherwise restore values
- * from shadow copy
- */
- check_env();
- return 0;
-}
-
-void vcma9_print_info(void)
-{
- char *s = getenv("serial#");
-
- if (!s) {
- puts ("### No HW ID - assuming VCMA9");
- } else {
- s[5] = 0;
- vcma9_show_info(s, &s[6]);
- }
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F400BB flash.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002, 2003
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for VCMA9
- *****************************************************************************/
-
-#include <asm/arch/s3c24x0_cpu.h>
-
-extern void vcma9_print_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag,
- int argc, char *const argv[]);
-
-/* VCMA9 PLD registers */
-enum vcma9_pld_regs {
- VCMA9_PLD_ID,
- VCMA9_PLD_NIC,
- VCMA9_PLD_CAN,
- VCMA9_PLD_MISC,
- VCMA9_PLD_GPCD,
- VCMA9_PLD_BOARD,
- VCMA9_PLD_SDRAM
-};
-
-#define VCMA9_PLD_BASE (0x2C000100)
# SPDX-License-Identifier: GPL-2.0+
obj-y := mpr2.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: MPR2\n");
return 0;
}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
# SPDX-License-Identifier: GPL-2.0+
obj-y := ms7720se.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define LED_BASE 0xB0800000
int checkboard(void)
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
outw(value & 0xFF, LED_BASE);
# SPDX-License-Identifier: GPL-2.0+
obj-y := ms7722se.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define LED_BASE 0xB0800000
int checkboard(void)
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
writew(value & 0xFF, LED_BASE);
#
obj-y := ms7750se.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <common.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
return 0;
}
-int dram_init (void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
int board_late_init(void)
{
return 0;
# SPDX-License-Identifier: GPL-2.0+
obj-y := migo_r.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas MigoR\n");
return 0;
}
-int dram_init (void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state (unsigned short value)
{
}
#
obj-y := ap325rxa.o cpld-ap325rxa.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* PRI control register */
#define PRPRICR5 0xFF800048 /* LMB */
#define PRPRICR5_D 0x2a
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
# SPDX-License-Identifier: GPL-2.0+
obj-y := ecovec.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
static void debug_led(u8 led)
{
/* PDGR[0-4] is debug LED */
# SPDX-License-Identifier: GPL-2.0+
obj-y := r0p7734.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <netdev.h>
#include <i2c.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define MODEMR (0xFFCC0020)
#define MODEMR_MASK (0x6)
#define MODEMR_533MHZ (0x2)
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
-
#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
#
obj-y := r2dplus.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/pci.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Solutions R2D Plus\n");
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
int board_late_init(void)
{
return 0;
# SPDX-License-Identifier: GPL-2.0+
obj-y := r7780mp.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <netdev.h>
#include "r7780mp.h"
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
#if defined(CONFIG_R7780MP)
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
# SPDX-License-Identifier: GPL-2.0+
obj-y := rsk7203.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Technology RSK7203\n");
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
# SPDX-License-Identifier: GPL-2.0+
obj-y := rsk7264.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Technology RSK7264\n");
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
# SPDX-License-Identifier: GPL-2.0+
obj-y := rsk7269.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas RSK7269\n");
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7752evb.o spi-boot.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
-
int board_mmc_init(bd_t *bis)
{
struct gpio_regs *gpio = GPIO_BASE;
+++ /dev/null
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2012
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- *(.spiboot1.text)
- *(.spiboot2.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (__init_end = .);
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7753evb.o spi-boot.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
- return 0;
-}
-
int board_mmc_init(bd_t *bis)
{
struct gpio_regs *gpio = GPIO_BASE;
+++ /dev/null
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2012
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- *(.spiboot1.text)
- *(.spiboot2.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (__init_end = .);
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7757lcr.o spi-boot.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- printf(" Physical address\n");
- printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
- SH7757LCR_SDRAM_PHYS_TOP,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
- printf(" 0x%08x - 0x%08x : No Access Area\n",
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
- printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
- SH7757LCR_SDRAM_DVC_SIZE - 1);
- printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
- SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
-
- return 0;
-}
-
int board_mmc_init(bd_t *bis)
{
return mmcif_mmc_init();
+++ /dev/null
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2011
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- *(.spiboot1.text)
- *(.spiboot2.text)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (__init_end = .);
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
#
obj-y := sh7763rdp.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/io.h>
#include <asm/processor.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define CPU_CMDREG 0xB1000006
#define PDCR 0xffef0006
#define PECR 0xffef0008
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
void led_set_state(unsigned short value)
{
}
# SPDX-License-Identifier: GPL-2.0+
obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
#include <asm/pci.h>
#include <netdev.h>
-DECLARE_GLOBAL_DATA_PTR;
-
int checkboard(void)
{
puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
return 0;
}
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
static struct pci_controller hose;
void pci_init_board(void)
{
+++ /dev/null
-if TARGET_SMDK2410
-
-config SYS_BOARD
- default "smdk2410"
-
-config SYS_VENDOR
- default "samsung"
-
-config SYS_SOC
- default "s3c24x0"
-
-config SYS_CONFIG_NAME
- default "smdk2410"
-
-endif
+++ /dev/null
-SMDK2410 BOARD
-M: David Müller <d.mueller@elsoft.ch>
-S: Maintained
-F: board/samsung/smdk2410/
-F: include/configs/smdk2410.h
-F: configs/smdk2410_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := smdk2410.o
-obj-y += lowlevel_init.o
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <config.h>
-
-/* some parameters for the board */
-
-/*
- *
- * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
- *
- * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
- *
- */
-
-#define BWSCON 0x48000000
-
-/* BWSCON */
-#define DW8 (0x0)
-#define DW16 (0x1)
-#define DW32 (0x2)
-#define WAIT (0x1<<2)
-#define UBLB (0x1<<3)
-
-#define B1_BWSCON (DW32)
-#define B2_BWSCON (DW16)
-#define B3_BWSCON (DW16 + WAIT + UBLB)
-#define B4_BWSCON (DW16)
-#define B5_BWSCON (DW16)
-#define B6_BWSCON (DW32)
-#define B7_BWSCON (DW32)
-
-/* BANK0CON */
-#define B0_Tacs 0x0 /* 0clk */
-#define B0_Tcos 0x0 /* 0clk */
-#define B0_Tacc 0x7 /* 14clk */
-#define B0_Tcoh 0x0 /* 0clk */
-#define B0_Tah 0x0 /* 0clk */
-#define B0_Tacp 0x0
-#define B0_PMC 0x0 /* normal */
-
-/* BANK1CON */
-#define B1_Tacs 0x0 /* 0clk */
-#define B1_Tcos 0x0 /* 0clk */
-#define B1_Tacc 0x7 /* 14clk */
-#define B1_Tcoh 0x0 /* 0clk */
-#define B1_Tah 0x0 /* 0clk */
-#define B1_Tacp 0x0
-#define B1_PMC 0x0
-
-#define B2_Tacs 0x0
-#define B2_Tcos 0x0
-#define B2_Tacc 0x7
-#define B2_Tcoh 0x0
-#define B2_Tah 0x0
-#define B2_Tacp 0x0
-#define B2_PMC 0x0
-
-#define B3_Tacs 0x0 /* 0clk */
-#define B3_Tcos 0x3 /* 4clk */
-#define B3_Tacc 0x7 /* 14clk */
-#define B3_Tcoh 0x1 /* 1clk */
-#define B3_Tah 0x0 /* 0clk */
-#define B3_Tacp 0x3 /* 6clk */
-#define B3_PMC 0x0 /* normal */
-
-#define B4_Tacs 0x0 /* 0clk */
-#define B4_Tcos 0x0 /* 0clk */
-#define B4_Tacc 0x7 /* 14clk */
-#define B4_Tcoh 0x0 /* 0clk */
-#define B4_Tah 0x0 /* 0clk */
-#define B4_Tacp 0x0
-#define B4_PMC 0x0 /* normal */
-
-#define B5_Tacs 0x0 /* 0clk */
-#define B5_Tcos 0x0 /* 0clk */
-#define B5_Tacc 0x7 /* 14clk */
-#define B5_Tcoh 0x0 /* 0clk */
-#define B5_Tah 0x0 /* 0clk */
-#define B5_Tacp 0x0
-#define B5_PMC 0x0 /* normal */
-
-#define B6_MT 0x3 /* SDRAM */
-#define B6_Trcd 0x1
-#define B6_SCAN 0x1 /* 9bit */
-
-#define B7_MT 0x3 /* SDRAM */
-#define B7_Trcd 0x1 /* 3clk */
-#define B7_SCAN 0x1 /* 9bit */
-
-/* REFRESH parameter */
-#define REFEN 0x1 /* Refresh enable */
-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
-#define Trp 0x0 /* 2clk */
-#define Trc 0x3 /* 7clk */
-#define Tchr 0x2 /* 3clk */
-#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
-/**************************************/
-
-.globl lowlevel_init
-lowlevel_init:
- /* memory control configuration */
- /* make r0 relative the current location so that it */
- /* reads SMRDATA out of FLASH rather than memory ! */
- ldr r0, =SMRDATA
- ldr r1, =CONFIG_SYS_TEXT_BASE
- sub r0, r0, r1
- ldr r1, =BWSCON /* Bus Width Status Controller */
- add r2, r0, #13*4
-0:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r2, r0
- bne 0b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-/* the literal pools origin */
-
-SMRDATA:
- .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
- .word 0x32
- .word 0x30
- .word 0x30
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002, 2010
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FCLK_SPEED 1
-
-#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV 0xC3
-#define M_PDIV 0x4
-#define M_SDIV 0x1
-#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */
-#define M_MDIV 0xA1
-#define M_PDIV 0x3
-#define M_SDIV 0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if (USB_CLOCK == 0)
-#define U_M_MDIV 0xA1
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x1
-#elif (USB_CLOCK == 1)
-#define U_M_MDIV 0x48
-#define U_M_PDIV 0x3
-#define U_M_SDIV 0x2
-#endif
-
-static inline void pll_delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
- struct s3c24x0_clock_power * const clk_power =
- s3c24x0_get_base_clock_power();
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
- /* to reduce PLL lock time, adjust the LOCKTIME register */
- writel(0xFFFFFF, &clk_power->locktime);
-
- /* configure MPLL */
- writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
- &clk_power->mpllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(4000);
-
- /* configure UPLL */
- writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
- &clk_power->upllcon);
-
- /* some delay between MPLL and UPLL */
- pll_delay(8000);
-
- /* set up the I/O ports */
- writel(0x007FFFFF, &gpio->gpacon);
- writel(0x00044555, &gpio->gpbcon);
- writel(0x000007FF, &gpio->gpbup);
- writel(0xAAAAAAAA, &gpio->gpccon);
- writel(0x0000FFFF, &gpio->gpcup);
- writel(0xAAAAAAAA, &gpio->gpdcon);
- writel(0x0000FFFF, &gpio->gpdup);
- writel(0xAAAAAAAA, &gpio->gpecon);
- writel(0x0000FFFF, &gpio->gpeup);
- writel(0x000055AA, &gpio->gpfcon);
- writel(0x000000FF, &gpio->gpfup);
- writel(0xFF95FFBA, &gpio->gpgcon);
- writel(0x0000FFFF, &gpio->gpgup);
- writel(0x002AFAAA, &gpio->gphcon);
- writel(0x000007FF, &gpio->gphup);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of SMDK2410-Board */
- gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x30000100;
-
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29LV800BB flash.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
-}
--- /dev/null
+if TARGET_SAMTEC_VINING_2000
+
+config SYS_BOARD
+ default "vining_2000"
+
+config SYS_VENDOR
+ default "samtec"
+
+config SYS_CONFIG_NAME
+ default "vining_2000"
+
+endif
--- /dev/null
+VINING_2000 BOARD
+M: Ingo Schroeck <open-source@samtec.de>
+S: Maintained
+F: board/samtec/vining_2000/
+F: include/configs/vining_2000.h
+F: configs/vining_2000_defconfig
--- /dev/null
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vining_2000.o
--- /dev/null
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+
+/* Control */
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000028
+DATA 4 0x020e0314 0x00000028
+DATA 4 0x020e0614 0x00000028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00210022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4142013a
+DATA 4 0x021b0840 0x012e0123
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x43474949
+DATA 4 0x021b0850 0x38383c38
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333040
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x926e8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x02008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x15108030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b001c 0x00000000
--- /dev/null
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Author: Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <pwm.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_PKE)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
+ MUX_MODE_SION,
+ /* LAN8720 PHY Reset */
+ MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_led_pads[] = {
+ MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
+ MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
+ MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#define PHY_RESET IMX_GPIO_NR(5, 9)
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+ unsigned char eth1addr[6];
+
+ /* just to get secound mac address */
+ imx_get_mac_from_fuse(1, eth1addr);
+ if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
+ eth_setenv_enetaddr("eth1addr", eth1addr);
+
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+ /*
+ * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
+ * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
+ * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1],
+ IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
+ IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ goto eth_fail;
+
+ /* reset phy */
+ gpio_direction_output(PHY_RESET, 0);
+ mdelay(16);
+ gpio_set_value(PHY_RESET, 1);
+ mdelay(1);
+
+ ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
+ IMX_FEC_BASE);
+ if (ret)
+ goto eth_fail;
+
+ return ret;
+
+eth_fail:
+ printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
+ gpio_set_value(PHY_RESET, 0);
+ return ret;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+ .gp = IMX_GPIO_NR(1, 0),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+ .gp = IMX_GPIO_NR(1, 1),
+ },
+};
+
+static struct pmic *pfuze_init(unsigned char i2cbus)
+{
+ struct pmic *p;
+ int ret;
+ u32 reg;
+
+ ret = power_pfuze100_init(i2cbus);
+ if (ret)
+ return NULL;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return NULL;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return p;
+}
+
+static int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id;
+ int ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+ id = id & 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf("Not supported, id=%d\n", id);
+ return -EINVAL;
+ }
+
+ ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+ if (ret < 0) {
+ printf("Set SW1AB mode error!\n");
+ return ret;
+ }
+
+ for (i = 0; i < switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+ if (ret < 0) {
+ printf("Set switch 0x%x mode error!\n",
+ offset + i * SWITCH_SIZE);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+
+ p = pfuze_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_iomux_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+#endif
+
+#ifdef CONFIG_PWM_IMX
+static int set_pwm_leds(void)
+{
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
+ ARRAY_SIZE(pwm_led_pads));
+ /* enable backlight PWM 2, green LED */
+ ret = pwm_init(1, 0, 0);
+ if (ret)
+ goto error;
+ /* duty cycle 200ns, period: 8000ns */
+ ret = pwm_config(1, 200, 8000);
+ if (ret)
+ goto error;
+ ret = pwm_enable(1);
+ if (ret)
+ goto error;
+
+ /* enable backlight PWM 1, blue LED */
+ ret = pwm_init(0, 0, 0);
+ if (ret)
+ goto error;
+ /* duty cycle 200ns, period: 8000ns */
+ ret = pwm_config(0, 200, 8000);
+ if (ret)
+ goto error;
+ ret = pwm_enable(0);
+ if (ret)
+ goto error;
+
+ /* enable backlight PWM 6, red LED */
+ ret = pwm_init(5, 0, 0);
+ if (ret)
+ goto error;
+ /* duty cycle 200ns, period: 8000ns */
+ ret = pwm_config(5, 200, 8000);
+ if (ret)
+ goto error;
+ ret = pwm_enable(5);
+
+error:
+ return ret;
+}
+#else
+static int set_pwm_leds(void)
+{
+ return 0;
+}
+#endif
+
+#define ADCx_HC0 0x00
+#define ADCx_HS 0x08
+#define ADCx_HS_C0 BIT(0)
+#define ADCx_R0 0x0c
+#define ADCx_CFG 0x14
+#define ADCx_CFG_SWMODE 0x308
+#define ADCx_GC 0x18
+#define ADCx_GC_CAL BIT(7)
+
+static int read_adc(u32 *val)
+{
+ int ret;
+ void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
+
+ /* use software mode */
+ writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
+
+ /* start auto calibration */
+ setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
+ ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+ if (ret)
+ goto adc_exit;
+
+ /* start conversion */
+ writel(0, b + ADCx_HC0);
+
+ /* wait for conversion */
+ ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+ if (ret)
+ goto adc_exit;
+
+ /* read result */
+ *val = readl(b + ADCx_R0);
+
+adc_exit:
+ if (ret)
+ printf("ADC failure (ret=%i)\n", ret);
+ unmap_physmem(b, MAP_NOCACHE);
+ return ret;
+}
+
+#define VAL_UPPER 2498
+#define VAL_LOWER 1550
+
+static int set_pin_state(void)
+{
+ u32 val;
+ int ret;
+
+ ret = read_adc(&val);
+ if (ret)
+ return ret;
+
+ if (val >= VAL_UPPER)
+ setenv("pin_state", "connected");
+ else if (val < VAL_UPPER && val > VAL_LOWER)
+ setenv("pin_state", "open");
+ else
+ setenv("pin_state", "button");
+
+ return ret;
+}
+
+int board_late_init(void)
+{
+ int ret;
+
+ ret = set_pwm_leds();
+ if (ret)
+ return ret;
+
+ ret = set_pin_state();
+
+ return ret;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ setup_iomux_usb();
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC4_BASE_ADDR, 0, 8},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == USDHC4_BASE_ADDR)
+ return 1;
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ return !gpio_get_value(USDHC2_CD_GPIO);
+
+ return -EINVAL;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC4
+ * mmc1 USDHC2
+ */
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ if (ret) {
+ printf("Warning: failed to initialize USDHC4\n");
+ return ret;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+ if (ret) {
+ printf("Warning: failed to initialize USDHC2\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: VIN|ING 2000\n");
+
+ return 0;
+}
# SPDX-License-Identifier: GPL-2.0+
obj-y := shmin.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
return 0;
}
-int dram_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
int board_eth_init(bd_t *bis)
{
return ne2k_register();
}
#endif /* CONFIG_VIDEO_IPUV3 */
+static int ar8035_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8035_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
--- /dev/null
+if TARGET_TS4600
+
+config SYS_BOARD
+ default "ts4600"
+
+config SYS_VENDOR
+ default "technologic"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "ts4600"
+
+endif
--- /dev/null
+TS4600 BOARD
+M: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+S: Maintained
+F: board/technologic/ts4600/
+F: include/configs/ts4600.h
+F: configs/ts4600_defconfig
--- /dev/null
+#
+# (C) Copyright 2016 Savoir-faire Linux
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := ts4600.o
+else
+obj-y := iomux.o
+endif
--- /dev/null
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ * Kris Bahnsen <kris@embeddedarm.com>
+ * Mark Featherston <mark@embeddedarm.com>
+ * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ * Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+ /* MMC0 slot power enable */
+ MX28_PAD_PWM3__GPIO_3_28 |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+};
+
+#define HW_DRAM_CTL29 (0x74 >> 2)
+#define CS_MAP 0xf
+#define COLUMN_SIZE 0x2
+#define ADDR_PINS 0x1
+#define APREBIT 0xa
+
+#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
+ ADDR_PINS << 8 | APREBIT)
+
+#define HW_DRAM_CTL39 (0x9c >> 2)
+#define TFAW 0xb
+#define TDLL 0xc8
+
+#define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL)
+
+#define HW_DRAM_CTL41 (0xa4 >> 2)
+#define TPDEX 0x2
+#define TRCD_INT 0x4
+#define TRC 0xd
+
+#define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC)
+
+#define HW_DRAM_CTL42 (0xa8 >> 2)
+#define TRAS_MAX 0x36a6
+#define TRAS_MIN 0xa
+
+#define HW_DRAM_CTL42_CONFIG (TRAS_MAX << 8 | TRAS_MIN)
+
+#define HW_DRAM_CTL43 (0xac >> 2)
+#define TRP 0x4
+#define TRFC 0x27
+#define TREF 0x2a0
+
+#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+ dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
+ dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
+ dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
+ dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
--- /dev/null
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ * Kris Bahnsen <kris@embeddedarm.com>
+ * Mark Featherston <mark@embeddedarm.com>
+ * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ * Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clocks at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int ts4600_mmc_cd(int id)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28);
+
+ /* Power-on SD */
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1);
+ udelay(1000);
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+ /* SD card */
+ ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd);
+ if(ret != 0) {
+ printf("SD controller initialized with %d\n", ret);
+ }
+
+ return ret;
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: TS4600\n");
+
+ return 0;
+}
if (board_is_bbg1())
name = "BBG1";
set_board_info_env(name);
+
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
#endif
#if !defined(CONFIG_SPL_BUILD)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_info_env(NULL);
+
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
#endif
return 0;
}
#include "mux_data.h"
#define board_is_x15() board_ti_is("BBRDX15_")
+#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
+ (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
#define board_is_am572x_evm() board_ti_is("AM572PM_")
+#define board_is_am572x_evm_reva3() \
+ (board_ti_is("AM572PM_") && \
+ (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
#define board_is_am572x_idk() board_ti_is("AM572IDK")
+#define board_is_am571x_idk() board_ti_is("AM571IDK")
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
.is_ma_present = 0x1
};
+static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80640100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
- *dmm_lisa_regs = &beagle_x15_lisa_regs;
+ if (board_is_am571x_idk())
+ *dmm_lisa_regs = &am571x_idk_lisa_regs;
+ else
+ *dmm_lisa_regs = &beagle_x15_lisa_regs;
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
}
struct vcores_data beagle_x15_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
};
struct vcores_data am572x_idk_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+int get_voltrail_opp(int rail_offset)
+{
+ int opp;
+
+ switch (rail_offset) {
+ case VOLT_MPU:
+ opp = DRA7_MPU_OPP;
+ break;
+ case VOLT_CORE:
+ opp = DRA7_CORE_OPP;
+ break;
+ case VOLT_GPU:
+ opp = DRA7_GPU_OPP;
+ break;
+ case VOLT_EVE:
+ opp = DRA7_DSPEVE_OPP;
+ break;
+ case VOLT_IVA:
+ opp = DRA7_IVA_OPP;
+ break;
+ default:
+ opp = OPP_NOM;
+ }
+
+ return opp;
+}
+
+
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
bname = "AM572x EVM";
else if (board_is_am572x_idk())
bname = "AM572x IDK";
+ else if (board_is_am571x_idk())
+ bname = "AM571x IDK";
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
if (rc)
goto invalid_eeprom;
- if (board_is_x15())
- name = "beagle_x15";
- else if (board_is_am572x_evm())
- name = "am57xx_evm";
- else if (board_is_am572x_idk())
+ if (board_is_x15()) {
+ if (board_is_x15_revb1())
+ name = "beagle_x15_revb1";
+ else
+ name = "beagle_x15";
+ } else if (board_is_am572x_evm()) {
+ if (board_is_am572x_evm_reva3())
+ name = "am57xx_evm_reva3";
+ else
+ name = "am57xx_evm";
+ } else if (board_is_am572x_idk()) {
name = "am572x_idk";
- else
+ } else if (board_is_am571x_idk()) {
+ name = "am571x_idk";
+ } else {
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
+ }
invalid_eeprom:
set_board_info_env(name);
* This is the POWERHOLD-in-Low behavior.
*/
palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
+
return 0;
}
const struct pad_conf_entry *pconf;
const struct iodelay_cfg_entry *iod;
int pconf_sz, iod_sz;
+ int ret;
if (board_is_am572x_idk()) {
pconf = core_padconf_array_essential_am572x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
iod = iodelay_cfg_array_am572x_idk;
iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+ } else if (board_is_am571x_idk()) {
+ pconf = core_padconf_array_essential_am571x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
+ iod = iodelay_cfg_array_am571x_idk;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
} else {
/* Common for X15/GPEVM */
pconf = core_padconf_array_essential_x15;
pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
- iod = iodelay_cfg_array_x15;
- iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
+ /* There never was an SR1.0 X15.. So.. */
+ if (omap_revision() == DRA752_ES1_1) {
+ iod = iodelay_cfg_array_x15_sr1_1;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
+ } else {
+ /* Since full production should switch to SR2.0 */
+ iod = iodelay_cfg_array_x15_sr2_0;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
+ }
+ }
+
+ /* Setup I/O isolation */
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Do the muxing here */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+
+ /* Now do the weird minor deltas that should be safe */
+ if (board_is_x15() || board_is_am572x_evm()) {
+ if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
+ pconf = core_padconf_array_delta_x15_sr2_0;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
+ } else {
+ pconf = core_padconf_array_delta_x15_sr1_1;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
+ }
+ do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
}
- __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
+ /* Setup IOdelay configuration */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
+err:
+ /* Closeup.. remove isolation */
+ __recalibrate_iodelay_end(ret);
}
#endif
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
- /* The phy address for the AM572x IDK are different than x15 */
- if (board_is_am572x_idk()) {
+ /* The phy address for the AM57xx IDK are different than x15 */
+ if (board_is_am572x_idk() || board_is_am571x_idk()) {
cpsw_data.slave_data[0].phy_addr = 0;
cpsw_data.slave_data[1].phy_addr = 1;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
+ if (board_is_x15()) {
+ if (board_is_x15_revb1()) {
+ if (!strcmp(name, "am57xx-beagle-x15-revb1"))
+ return 0;
+ } else if (!strcmp(name, "am57xx-beagle-x15")) {
+ return 0;
+ }
+ } else if (board_is_am572x_evm() &&
+ !strcmp(name, "am57xx-beagle-x15")) {
return 0;
- else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
+ } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
return 0;
- else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
+ } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
return 0;
- else
- return -1;
+ }
+
+ return -1;
}
#endif
{
secure_boot_verify_image(p_image, p_size);
}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+ secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential_x15[] = {
- {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
- {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
- {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
- {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
- {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
- {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
- {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
- {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
- {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
- {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
- {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
- {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
- {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
- {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
- {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
- {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
+ {GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
+ {GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
+ {GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
+ {GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
+ {GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
+ {GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
+ {GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
+ {GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
+ {GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
+ {GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
+ {GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
+ {GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
+ {GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
+ {GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
+ {GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
+ {GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
- {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */
+ {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_cs3.vin3a_clk0 */
{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
- {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
+ {VIN1B_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1b_clk1.gpio2_31 */
{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
{VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
- {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */
{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */
- {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
+ {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
- {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
{VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */
- {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
+ {VIN2A_D3, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
{VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */
- {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
+ {VIN2A_D5, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
- {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
+ {VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
{VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
- {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
- {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
{VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
{VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */
{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */
{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */
- {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
{GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
{GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
- {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
+ {XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
- {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */
{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.i2c5_scl */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */
- {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */
- {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */
- {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP1_AXR8, (M14 | PIN_INPUT)}, /* mcasp1_axr8.gpio5_10 */
+ {MCASP1_AXR9, (M14 | PIN_INPUT)}, /* mcasp1_axr9.gpio5_11 */
+ {MCASP1_AXR10, (M14 | PIN_INPUT)}, /* mcasp1_axr10.gpio5_12 */
+ {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr11.gpio4_17 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */
- {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */
+ {MCASP2_FSX, (M0 | PIN_INPUT)}, /* mcasp2_fsx.mcasp2_fsx */
{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
{MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */
{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */
{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */
- {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */
- {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */
+ {MCASP2_AXR2, (M0 | PIN_INPUT)}, /* mcasp2_axr2.mcasp2_axr2 */
+ {MCASP2_AXR3, (M0 | PIN_INPUT)}, /* mcasp2_axr3.mcasp2_axr3 */
{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */
{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */
{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */
{MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */
{MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */
{MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */
- {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
+ {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */
+ {MCASP4_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
{MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */
- {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
- {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */
- {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
+ {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
+ {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */
+ {MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
- {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
+ {MMC1_CLK, (M0 | PIN_OUTPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */
- {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
- {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */
- {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */
- {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */
- {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */
- {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */
- {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */
- {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
+ {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
+ {GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {MMC3_CLK, (M0 | PIN_OUTPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
+ {MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_cmd.mmc3_cmd */
+ {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat0.mmc3_dat0 */
+ {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */
+ {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */
+ {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */
+ {MMC3_DAT4, (M1 | PIN_OUTPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
{MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */
{MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */
- {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
+ {MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
- {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
- {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */
{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */
{SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */
- {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
+ {SPI2_CS0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_cs0.gpio7_17 */
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
{DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
- {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */
- {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */
- {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */
- {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
- {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */
- {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */
- {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */
- {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */
- {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
- {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
- {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
+ {UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */
+ {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */
+ {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */
+ {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT_PULLDOWN)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
+ {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
+ {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
+ {VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */
};
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
- {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
- {GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
- {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
- {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
- {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
- {GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
- {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
- {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
- {GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
- {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
- {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
- {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
- {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
+ {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
+ {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
+ {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
+ {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
+ {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
+ {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
+ {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
+ {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
+ {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
+ {MCASP1_FSX, (M11 | PIN_INPUT)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
+ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
+ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
+ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
+ {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
+ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
+ {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
+ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
+ {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
+ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_OUTPUT)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_OUTPUT)}, /* spi2_cs0.spi2_cs0 */
+ {UART1_RXD, (M14 | PIN_OUTPUT)}, /* uart1_rxd.gpio7_22 */
+ {UART1_TXD, (M14 | PIN_OUTPUT)}, /* uart1_txd.gpio7_23 */
+ {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
+ {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
+ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
+ {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a0.vin1b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a1.vin1b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a2.vin1b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a3.vin1b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a4.vin1b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a5.vin1b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a6.vin1b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a7.vin1b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a8.vin1b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a9.vin1b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a10.vin1b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a11.vin1b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a12.vin1b_fld1 */
{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN) | MANUAL_MODE}, /* gpmc_a17.qspi1_d1 */
{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
- {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
- {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
- {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
- {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
- {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
- {VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d13.gpio3_17 */
- {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
- {VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d15.gpio3_19 */
- {VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d17.gpio3_21 */
- {VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
- {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
- {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
- {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
- {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
- {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {GPMC_CS3, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.gpio2_21 */
+ {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */
+ {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
+ {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
+ {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
+ {GPMC_BEN0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpio2_26 */
+ {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */
+ {GPMC_WAIT0, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
- {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.ecap1 */
- {VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.gpio4_4 */
- {VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.gpio4_5 */
- {VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mi1_col */
+ {VIN2A_D4, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.pr1_mii1_txd1 */
+ {VIN2A_D5, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_mii1_txd0 */
{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
- {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii_mii1_txen */
- {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii_mii1_txd3 */
- {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii_mii1_txd2 */
+ {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii1_txen */
+ {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii1_txd3 */
+ {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii1_txd2 */
{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
- {VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
- {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
- {UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.pr1_mii0_rxdv */
- {UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.rp1_mii_mr0_clk */
+ {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */
{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
- {GPIO6_15, (M0 | PIN_OUTPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
- {GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6)_16 */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */
{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
- {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.i6_19 */
- {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */
{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */
{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */
{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */
{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */
{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */
+ {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */
+ {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */
+ {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */
{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */
{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */
{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */
{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */
- {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */
+ {MCASP4_AXR1, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.spi3_cs0 */
{MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
- {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
- {MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.pr2_pru1_gpo3 */
- {MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.pr2_pru1_gpo4 */
+ {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MCASP5_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.Driveroff */
+ {MCASP5_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.Driveroff */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */
{GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
{GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
- {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs0.gpio7_10 */
{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
- {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
- {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
- {UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rxd.gpio7_22 */
- {UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio7_23 */
- {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
- {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
- {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
+ {SPI2_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_INPUT_SLEW)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT_SLEW)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
+ {UART1_RXD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
+ {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
+ {UART1_RTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rtsn.gpio7_25 */
+ {UART2_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_txd.uart2_txd */
+ {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP3, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_OUTPUT)}, /* rtc_porz.rtc_porz */
{TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
{TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
{0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
{0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
{0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
{0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
{0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
{0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
{0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
{0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
{0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
};
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
+ {0x0114, 2519, 702}, /* CFG_GPMC_A0_IN */
+ {0x0120, 2435, 411}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2379, 755}, /* CFG_GPMC_A11_IN */
+ {0x0198, 2384, 778}, /* CFG_GPMC_A1_IN */
+ {0x0204, 2499, 1127}, /* CFG_GPMC_A2_IN */
+ {0x0210, 2455, 1181}, /* CFG_GPMC_A3_IN */
+ {0x021C, 2486, 1039}, /* CFG_GPMC_A4_IN */
+ {0x0228, 2456, 938}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2463, 573}, /* CFG_GPMC_A6_IN */
+ {0x0240, 2608, 783}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2430, 656}, /* CFG_GPMC_A8_IN */
+ {0x0258, 2465, 850}, /* CFG_GPMC_A9_IN */
+ {0x0264, 2316, 301}, /* CFG_GPMC_AD0_IN */
+ {0x0270, 2324, 406}, /* CFG_GPMC_AD10_IN */
+ {0x027C, 2278, 352}, /* CFG_GPMC_AD11_IN */
+ {0x0288, 2297, 160}, /* CFG_GPMC_AD12_IN */
+ {0x0294, 2278, 108}, /* CFG_GPMC_AD13_IN */
+ {0x02A0, 2035, 0}, /* CFG_GPMC_AD14_IN */
+ {0x02AC, 2279, 378}, /* CFG_GPMC_AD15_IN */
+ {0x02B8, 2440, 70}, /* CFG_GPMC_AD1_IN */
+ {0x02C4, 2404, 446}, /* CFG_GPMC_AD2_IN */
+ {0x02D0, 2343, 212}, /* CFG_GPMC_AD3_IN */
+ {0x02DC, 2355, 322}, /* CFG_GPMC_AD4_IN */
+ {0x02E8, 2337, 192}, /* CFG_GPMC_AD5_IN */
+ {0x02F4, 2270, 314}, /* CFG_GPMC_AD6_IN */
+ {0x0300, 2339, 259}, /* CFG_GPMC_AD7_IN */
+ {0x030C, 2308, 577}, /* CFG_GPMC_AD8_IN */
+ {0x0318, 2334, 166}, /* CFG_GPMC_AD9_IN */
+ {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
+ {0x0678, 0, 386}, /* CFG_MMC3_CLK_IN */
+ {0x0680, 605, 0}, /* CFG_MMC3_CLK_OUT */
+ {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
+ {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
+ {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
+ {0x0690, 171, 0}, /* CFG_MMC3_DAT0_IN */
+ {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
+ {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
+ {0x069C, 221, 0}, /* CFG_MMC3_DAT1_IN */
+ {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
+ {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
+ {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
+ {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
+ {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
+ {0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */
+ {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
+ {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
+ {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
+};
+
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
- {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
- {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
- {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
- {0x0138, 2605, 45}, /* CFG_GPMC_A12_IN */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
- {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
- {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
- {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
- {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
- {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
- {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
- {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
- {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
- {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
- {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
- {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
- {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
- {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */
+ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 1783, 1178}, /* CFG_GPMC_A11_IN */
+ {0x0138, 1903, 853}, /* CFG_GPMC_A12_IN */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
+ {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0198, 1652, 891}, /* CFG_GPMC_A1_IN */
+ {0x0204, 1888, 1212}, /* CFG_GPMC_A2_IN */
+ {0x0210, 1839, 1274}, /* CFG_GPMC_A3_IN */
+ {0x021C, 1868, 1113}, /* CFG_GPMC_A4_IN */
+ {0x0228, 1757, 1079}, /* CFG_GPMC_A5_IN */
+ {0x0234, 1800, 670}, /* CFG_GPMC_A6_IN */
+ {0x0240, 1967, 898}, /* CFG_GPMC_A7_IN */
+ {0x024C, 1731, 959}, /* CFG_GPMC_A8_IN */
+ {0x0258, 1766, 1150}, /* CFG_GPMC_A9_IN */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */
+ {0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */
+ {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 90, 70}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 70, 70}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 180, 70}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 35, 70}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 180, 70}, /* CFG_RGMII0_TXD3_OUT */
{0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */
{0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */
{0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */
{0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */
{0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
{0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
{0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
{0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
{0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
{0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
{0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
+ {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */
};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2062, 2277}, /* CFG_GPMC_A14_IN */
+ {0x015C, 1960, 2289}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2058, 2386}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2062, 2350}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
+};
+
#endif
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
+#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0))
#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
}
struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
};
struct vcores_data dra722_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+struct vcores_data dra718_volts = {
+ /*
+ * In the case of dra71x GPU MPU and CORE
+ * are all powered up by BUCK0 of LP873X PMIC
+ */
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = LP873X_REG_ADDR_BUCK0,
+ .mpu.pmic = &lp8733,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = LP873X_REG_ADDR_BUCK0,
+ .core.pmic = &lp8733,
+
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = LP873X_REG_ADDR_BUCK0,
+ .gpu.pmic = &lp8733,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ /*
+ * The DSPEVE and IVA rails are grouped on DRA71x-evm
+ * and are powered by BUCK1 of LP873X PMIC
+ */
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = LP873X_REG_ADDR_BUCK1,
+ .eve.pmic = &lp8733,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = LP873X_REG_ADDR_BUCK1,
+ .iva.pmic = &lp8733,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+int get_voltrail_opp(int rail_offset)
+{
+ int opp;
+
+ /*
+ * DRA71x supports only OPP_NOM.
+ */
+ if (board_is_dra71x_evm())
+ return OPP_NOM;
+
+ switch (rail_offset) {
+ case VOLT_MPU:
+ opp = DRA7_MPU_OPP;
+ break;
+ case VOLT_CORE:
+ opp = DRA7_CORE_OPP;
+ break;
+ case VOLT_GPU:
+ opp = DRA7_GPU_OPP;
+ break;
+ case VOLT_EVE:
+ opp = DRA7_DSPEVE_OPP;
+ break;
+ case VOLT_IVA:
+ opp = DRA7_IVA_OPP;
+ break;
+ default:
+ opp = OPP_NOM;
+ }
+
+ return opp;
+}
+
/**
* @brief board_init
*
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
+ else if (board_is_dra71x_evm())
+ name = "dra71x";
else
name = "dra72x";
} else {
set_board_info_env(name);
+ /*
+ * Default FIT boot on HS devices. Non FIT images are not allowed
+ * on HS devices.
+ */
+ if (get_device_type() == HS_DEVICE)
+ setenv("boot_fit", "1");
+
omap_die_id_serial();
#endif
return 0;
bname = "DRA74x EVM";
} else if (board_is_dra72x_evm()) {
bname = "DRA72x EVM";
+ } else if (board_is_dra71x_evm()) {
+ bname = "DRA71x EVM";
} else {
/* If EEPROM is not populated */
if (is_dra72x())
*omap_vcores = &dra752_volts;
} else if (board_is_dra72x_evm()) {
*omap_vcores = &dra722_volts;
+ } else if (board_is_dra71x_evm()) {
+ *omap_vcores = &dra718_volts;
} else {
/* If EEPROM is not populated */
if (is_dra72x())
case DRA722_ES2_0:
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
- if (board_is_dra72x_revc_or_later()) {
+ if (board_is_dra71x_evm()) {
+ pads = dra71x_core_padconf_array;
+ npads = ARRAY_SIZE(dra71x_core_padconf_array);
+ iodelay = dra71_iodelay_cfg_array;
+ niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
+ } else if (board_is_dra72x_revc_or_later()) {
delta_pads = dra72x_rgmii_padconf_array_revc;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
int board_fit_config_name_match(const char *name)
{
if (is_dra72x()) {
- if (board_is_dra72x_revc_or_later()) {
+ if (board_is_dra71x_evm()) {
+ if (!strcmp(name, "dra71-evm"))
+ return 0;
+ }else if(board_is_dra72x_revc_or_later()) {
if (!strcmp(name, "dra72-evm-revc"))
return 0;
} else if (!strcmp(name, "dra72-evm")) {
{
secure_boot_verify_image(p_image, p_size);
}
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+ secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
#endif
const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
{VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
- {RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
};
+const struct pad_conf_entry dra71x_core_padconf_array[] = {
+ {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
+ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
+ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
+ {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
+ {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
+ {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
+ {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
+ {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
+ {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
+ {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
+ {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
+ {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
+ {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
+ {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
+ {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
+ {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
+ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
+ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
+ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
+ {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
+ {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
+ {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
+ {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
+ {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
+ {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
+ {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
+ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
+ {GPMC_A11, (M14 | PIN_INPUT)}, /* gpmc_a11.gpio2_1 */
+ {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
+ {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
+ {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
+ {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
+ {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
+ {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
+ {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
+ {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
+ {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
+ {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
+ {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
+ {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
+ {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
+ {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
+ {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
+ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
+ {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+ {MCASP1_ACLKX, (M14 | PIN_INPUT)}, /* mcasp1_aclkx.gpio7_31 */
+ {MCASP1_FSX, (M14 | 0x000d0000)}, /* mcasp1_fsx.gpio7_30 */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
+ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
+ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
+ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
+ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
+ {SPI1_CS1, (M14 | PIN_INPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
+ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
+ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
+ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
+ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
+ {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
+ {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
+ {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
+ {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
+ {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
+ {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
+ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
+ {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
+};
+
const struct pad_conf_entry early_padconf[] = {
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
{0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
{0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
{0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
};
+const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
+ {0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
+ {0x0A50, 2031, 0}, /* CFG_VIN2A_D10_IN */
+ {0x0A5C, 1702, 0}, /* CFG_VIN2A_D11_IN */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
+ {0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
+ {0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
+ {0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
+ {0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
+ {0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
+ {0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
+ {0x0B4C, 1224, 618}, /* CFG_VIN2A_D8_IN */
+ {0x0B58, 1373, 509}, /* CFG_VIN2A_D9_IN */
+ {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
+ {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
+};
#endif
const struct pad_conf_entry dra74x_core_padconf_array[] = {
--- /dev/null
+if TARGET_UDOO_NEO
+
+config SYS_VENDOR
+ default "udoo"
+
+config SYS_BOARD
+ default "neo"
+
+config SYS_CONFIG_NAME
+ default "udoo_neo"
+
+endif
--- /dev/null
+UDOO NEO BOARD
+M: Breno Lima <breno.lima@nxp.com>
+M: Francesco Montefoschi <francesco.montefoschi@udoo.org>
+S: Maintained
+F: board/udoo/neo/
+F: include/configs/udoo_neo.h
+F: configs/udoo_neo_defconfig
--- /dev/null
+# (C) Copyright 2015 UDOO Team
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := neo.o
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) Jasbir Matharu
+ * Copyright (C) UDOO Team
+ *
+ * Author: Breno Lima <breno.lima@nxp.com>
+ * Author: Francesco Montefoschi <francesco.monte@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <linux/sizes.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ UDOO_NEO_TYPE_BASIC,
+ UDOO_NEO_TYPE_BASIC_KS,
+ UDOO_NEO_TYPE_FULL,
+ UDOO_NEO_TYPE_EXTENDED,
+};
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm)
+
+#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
+ MUX_MODE_SION)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* CD pin */
+ MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Power */
+ MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const board_recognition_pads[] = {
+ /*Connected to R184*/
+ MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
+ /*Connected to R185*/
+ MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ /* Configured for WLAN */
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_b_pad = {
+ MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+ MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /*
+ * Because kernel set WDOG_B mux before pad with the commone pinctrl
+ * framwork now and wdog reset will be triggered once set WDOG_B mux
+ * with default pad setting, we set pad setting here to workaround this.
+ * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+ * as GPIO mux firstly here to workaround it.
+ */
+ imx_iomux_v3_setup_pad(wdog_b_pad);
+
+ /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+ ARRAY_SIZE(peri_3v3_pads));
+
+ /* Active high for ncp692 */
+ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+ return 0;
+}
+
+static int get_board_value(void)
+{
+ int r184, r185;
+
+ imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
+ ARRAY_SIZE(board_recognition_pads));
+
+ gpio_direction_input(IMX_GPIO_NR(4, 13));
+ gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+ r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
+ r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
+
+ /*
+ * Machine selection -
+ * Machine r184, r185
+ * ---------------------------------
+ * Basic 0 0
+ * Basic Ks 0 1
+ * Full 1 0
+ * Extended 1 1
+ */
+
+ return (r184 << 1) + r185;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers\
+ (%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning:\
+ failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+#else
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+ u32 port;
+
+ val = readl(&src_regs->sbmr1);
+
+ if ((val & 0xc0) != 0x40) {
+ printf("Not boot from USDHC!\n");
+ return -EINVAL;
+ }
+
+ port = (val >> 11) & 0x3;
+ printf("port %d\n", port);
+ switch (port) {
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+ break;
+ }
+
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+
+char *board_string(void)
+{
+ switch (get_board_value()) {
+ case UDOO_NEO_TYPE_BASIC:
+ return "BASIC";
+ case UDOO_NEO_TYPE_BASIC_KS:
+ return "BASICKS";
+ case UDOO_NEO_TYPE_FULL:
+ return "FULL";
+ case UDOO_NEO_TYPE_EXTENDED:
+ return "EXTENDED";
+ }
+ return "UNDEFINED";
+}
+
+int checkboard(void)
+{
+ printf("Board: UDOO Neo %s\n", board_string());
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", board_string());
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#include <libfdt.h>
+#include <asm/arch/mx6-ddr.h>
+
+static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_dqm2 = 0x00000028,
+ .dram_dqm3 = 0x00000028,
+ .dram_ras = 0x00000020,
+ .dram_cas = 0x00000020,
+ .dram_odt0 = 0x00000020,
+ .dram_odt1 = 0x00000020,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_sdqs2 = 0x00000028,
+ .dram_sdqs3 = 0x00000028,
+ .dram_reset = 0x00000020,
+};
+
+static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000020,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_ctlds = 0x00000020,
+ .grp_ddr_type = 0x000c0000,
+ .grp_b2ds = 0x00000028,
+ .grp_b3ds = 0x00000028,
+};
+
+static const struct mx6_mmdc_calibration neo_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x000E000B,
+ .p0_mpwldectrl1 = 0x000E0010,
+ .p0_mpdgctrl0 = 0x41600158,
+ .p0_mpdgctrl1 = 0x01500140,
+ .p0_mprddlctl = 0x3A383E3E,
+ .p0_mpwrdlctl = 0x3A383C38,
+};
+
+static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x001E0022,
+ .p0_mpwldectrl1 = 0x001C0019,
+ .p0_mpdgctrl0 = 0x41540150,
+ .p0_mpdgctrl1 = 0x01440138,
+ .p0_mprddlctl = 0x403E4644,
+ .p0_mpwrdlctl = 0x3C3A4038,
+};
+
+/* MT41K256M16 */
+static struct mx6_ddr3_cfg neo_mem_ddr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* MT41K128M16 */
+static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+ writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+ int board = get_board_value();
+
+ struct mx6_ddr_sysinfo sysinfo = {
+ .dsize = 1, /* width of data bus: 1 = 32 bits */
+ .cs_density = 24,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 2,
+ .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+ mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
+ &neo_basic_mem_ddr);
+ else
+ mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+#endif
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#if defined(CONFIG_VIDEO_IPUV3)
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
if (is_mx6dq())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+#endif
return 0;
}
obj-y := zynqmp.o
-hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
$(hw-platform-y)/psu_init_gpl.o)
for testing that EFI is working at a basic level, and for bringing
up EFI support on a new architecture.
+config CMD_BOOTMENU
+ bool "bootmenu"
+ select MENU
+ help
+ Add an ANSI terminal boot menu command.
+
config CMD_ELF
bool "bootelf, bootvx"
default y
help
Boot image via network using DHCP/TFTP protocol
+config CMD_PXE
+ bool "pxe"
+ select MENU
+ help
+ Boot image via network using PXE protocol
+
config CMD_NFS
bool "nfs"
default y
help
Show AMBA Plug-n-Play information on startup.
+config CMD_BKOPS_ENABLE
+ bool "mmc bkops enable"
+ depends on CMD_MMC
+ default n
+ help
+ Enable command for setting manual background operations handshake
+ on a eMMC device. The feature is optionally available on eMMC devices
+ conforming to standard >= 4.41.
+
config CMD_BLOCK_CACHE
bool "blkcache - control and stats for block cache"
depends on BLOCK_CACHE
DECLARE_GLOBAL_DATA_PTR;
+/**
+ * Decode a flash region parameter
+ *
+ * @param argc Number of params remaining
+ * @param argv List of remaining parameters
+ * @return flash region (EC_FLASH_REGION_...) or -1 on error
+ */
+static int cros_ec_decode_region(int argc, char * const argv[])
+{
+ if (argc > 0) {
+ if (0 == strcmp(*argv, "rw"))
+ return EC_FLASH_REGION_RW;
+ else if (0 == strcmp(*argv, "ro"))
+ return EC_FLASH_REGION_RO;
+
+ debug("%s: Invalid region '%s'\n", __func__, *argv);
+ } else {
+ debug("%s: Missing region parameter\n", __func__);
+ }
+
+ return -1;
+}
+
/**
* Perform a flash read or write command
*
return 1;
}
working_fdt = newaddr;
+#ifdef CONFIG_OF_SYSTEM_SETUP
+ /* Call the board-specific fixup routine */
+ } else if (strncmp(argv[1], "sys", 3) == 0) {
+ int err = ft_system_setup(working_fdt, gd->bd);
+ if (err) {
+ printf("Failed to add system information to FDT: %s\n",
+ fdt_strerror(err));
+ return CMD_RET_FAILURE;
+ }
+#endif
/*
* Make a new node
*/
return CMD_RET_FAILURE;
}
}
-#endif
-#ifdef CONFIG_OF_SYSTEM_SETUP
- /* Call the board-specific fixup routine */
- else if (strncmp(argv[1], "sys", 3) == 0) {
- int err = ft_system_setup(working_fdt, gd->bd);
-
- if (err) {
- printf("Failed to add system information to FDT: %s\n",
- fdt_strerror(err));
- return CMD_RET_FAILURE;
- }
- }
#endif
/* Create a chosen node */
else if (strncmp(argv[1], "cho", 3) == 0) {
static int extract_range(char *input, int *plo, int *phi)
{
char *end;
- *plo = simple_strtol(input, &end, 0);
+ *plo = simple_strtol(input, &end, 16);
if (end == input)
return -1;
if ((*end == '-') && *(++end))
- *phi = simple_strtol(end, NULL, 0);
+ *phi = simple_strtol(end, NULL, 16);
else if (*end == '\0')
*phi = *plo;
else
printf("Reading from bus %s\n", bus->name);
for (addr = addrlo; addr <= addrhi; addr++) {
- printf("PHY at address %d:\n", addr);
+ printf("PHY at address %x:\n", addr);
for (devad = devadlo; devad <= devadhi; devad++) {
for (reg = reglo; reg <= reghi; reg++) {
return ret;
}
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+static int do_mmc_bkops_enable(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int dev;
+ struct mmc *mmc;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ dev = simple_strtoul(argv[1], NULL, 10);
+
+ mmc = init_mmc_device(dev, false);
+ if (!mmc)
+ return CMD_RET_FAILURE;
+
+ if (IS_SD(mmc)) {
+ puts("BKOPS_EN only exists on eMMC\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return mmc_set_bkops_enable(mmc);
+}
+#endif
+
static cmd_tbl_t cmd_mmc[] = {
U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
U_BOOT_CMD_MKENT(rpmb, CONFIG_SYS_MAXARGS, 1, do_mmcrpmb, "", ""),
#endif
U_BOOT_CMD_MKENT(setdsr, 2, 0, do_mmc_setdsr, "", ""),
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+ U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""),
+#endif
};
static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
"mmc rpmb counter - read the value of the write counter\n"
#endif
"mmc setdsr <value> - set DSR register value\n"
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+ "mmc bkops-enable <dev> - enable background operations handshake on device\n"
+ " WARNING: This is a write-once setting.\n"
+#endif
);
/* Old command kept for compatibility. Same as 'mmc info' */
/*
* scsi boot command intepreter. Derived from diskboot
*/
-int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_scsiboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
return common_diskboot(cmdtp, "scsi", argc, argv);
}
/*
* scsi command intepreter
*/
-int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+static int do_scsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
+ int ret;
+
switch (argc) {
case 0:
case 1:
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nReset SCSI\n");
scsi_bus_reset();
- scsi_scan(1);
- return 0;
+ ret = scsi_scan(1);
+ if (ret)
+ return CMD_RET_FAILURE;
+ return ret;
}
if (strncmp(argv[1], "inf", 3) == 0) {
blk_list_devices(IF_TYPE_SCSI);
return 0;
}
if (strncmp(argv[1], "scan", 4) == 0) {
- scsi_scan(1);
- return 0;
+ ret = scsi_scan(1);
+ if (ret)
+ return CMD_RET_FAILURE;
+ return ret;
}
if (strncmp(argv[1], "part", 4) == 0) {
if (blk_list_part(IF_TYPE_SCSI))
static int do_tpmtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *c;
+ int i;
printf("argc = %d, argv = ", argc);
- do {
- int i = 0;
- for (i = 0; i < argc; i++)
- printf(" %s", argv[i]);
- printf("\n------\n");
- } while (0);
+ for (i = 0; i < argc; i++)
+ printf(" %s", argv[i]);
+
+ printf("\n------\n");
+
argc--;
argv++;
c = find_cmd_tbl(argv[0], cmd_cros_tpm_sub,
menu "Console"
+config MENU
+ bool
+ help
+ This is the library functionality to provide a text-based menu of
+ choices for the user to make choices with.
+
config CONSOLE_RECORD
bool "Console recording"
help
#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) || \
defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
-#elif defined(CONFIG_NDS32)
+#elif defined(CONFIG_NDS32) || defined(CONFIG_SH)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
#elif defined(CONFIG_SYS_MONITOR_BASE)
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
return 0;
}
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
+#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+ defined(CONFIG_SH)
static int setup_board_part1(void)
{
bd_t *bd = gd->bd;
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
- defined(CONFIG_SPARC)
+ defined(CONFIG_SH) || defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
#ifdef CONFIG_SYS_ALLOC_DPRAM
#if defined(CONFIG_MPC83xx)
prt_83xx_rsr,
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH)
checkcpu,
#endif
print_cpuinfo, /* display cpu info (and speed) */
announce_dram_init,
/* TODO: unify all these dram functions? */
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \
- defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
+ defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \
+ defined(CONFIG_SH)
dram_init, /* configure available RAM banks */
#endif
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
reserve_stacks,
setup_dram_config,
show_dram_config,
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
+#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
+ defined(CONFIG_SH)
setup_board_part1,
#endif
#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
return 0;
}
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
static int initr_trap(void)
{
/*
#ifdef CONFIG_NEEDS_MANUAL_RELOC
initr_manual_reloc_cmdtable,
#endif
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
initr_trap,
#endif
#ifdef CONFIG_ADDR_MAP
do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
}
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
/*
* fdt_pack_reg - pack address and size array into the "reg"-suitable stream
*/
}
return 0;
}
+#endif
int fdt_fixup_memory(void *blob, u64 start, u64 size)
{
printf("ERROR: /chosen node create failed\n");
goto err;
}
-#ifdef CONFIG_ARCH_FIXUP_FDT
if (arch_fixup_fdt(blob) < 0) {
printf("ERROR: arch-specific fdt fixup failed\n");
goto err;
}
-#endif
if (IMAGE_OF_BOARD_SETUP) {
fdt_ret = ft_board_setup(blob, gd->bd);
if (fdt_ret) {
static int fit_image_select(const void *fit, int rd_noffset, int verify)
{
-#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
- const void *data;
- size_t size;
- int ret;
-#endif
-
fit_image_print(fit, rd_noffset, " ");
if (verify) {
puts("OK\n");
}
-#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
- ret = fit_image_get_data(fit, rd_noffset, &data, &size);
- if (ret)
- return ret;
-
- /* perform any post-processing on the image data */
- board_fit_image_post_process((void **)&data, &size);
-
- /*
- * update U-Boot's understanding of the "data" property start address
- * and size according to the performed post-processing
- */
- ret = fdt_setprop((void *)fit, rd_noffset, FIT_DATA_PROP, data, size);
- if (ret)
- return ret;
-#endif
-
return 0;
}
bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
return -ENOENT;
}
+
+#if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
+ /* perform any post-processing on the image data */
+ board_fit_image_post_process((void **)&buf, &size);
+#endif
+
len = (ulong)size;
/* verify that image data is a proper FDT blob */
{ IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" },
{ IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
{ IH_TYPE_FPGA, "fpga", "FPGA Image" },
+ { IH_TYPE_TEE, "tee", "Trusted Execution Environment Image",},
{ -1, "", "", },
};
}
#endif
+static void fit_loadable_process(uint8_t img_type,
+ ulong img_data,
+ ulong img_len)
+{
+ int i;
+ const unsigned int count =
+ ll_entry_count(struct fit_loadable_tbl, fit_loadable);
+ struct fit_loadable_tbl *fit_loadable_handler =
+ ll_entry_start(struct fit_loadable_tbl, fit_loadable);
+ /* For each loadable handler */
+ for (i = 0; i < count; i++, fit_loadable_handler++)
+ /* matching this type */
+ if (fit_loadable_handler->type == img_type)
+ /* call that handler with this image data */
+ fit_loadable_handler->handler(img_data, img_len);
+}
+
int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong * const ld_len)
{
int conf_noffset;
int fit_img_result;
const char *uname;
+ uint8_t img_type;
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
/* Something went wrong! */
return fit_img_result;
}
+
+ fit_img_result = fit_image_get_node(buf, uname);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+ fit_img_result = fit_image_get_type(buf,
+ fit_img_result,
+ &img_type);
+ if (fit_img_result < 0) {
+ /* Something went wrong! */
+ return fit_img_result;
+ }
+
+ fit_loadable_process(img_type, img_data, img_len);
}
break;
default:
struct phy_device *phydev = bus->phymap[i];
if (phydev) {
- printf("%d - %s", i, phydev->drv->name);
+ printf("%x - %s", i, phydev->drv->name);
if (phydev->dev)
printf(" <--> %s\n", phydev->dev->name);
}
#endif
-void scsi_setup_read_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+static void scsi_setup_read_ext(ccb *pccb, lbaint_t start,
+ unsigned short blocks)
{
pccb->cmd[0] = SCSI_READ10;
pccb->cmd[1] = pccb->lun << 5;
pccb->cmd[7], pccb->cmd[8]);
}
-void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks)
+static void scsi_setup_write_ext(ccb *pccb, lbaint_t start,
+ unsigned short blocks)
{
pccb->cmd[0] = SCSI_WRITE10;
pccb->cmd[1] = pccb->lun << 5;
pccb->cmd[7], pccb->cmd[8]);
}
-void scsi_setup_read6(ccb *pccb, lbaint_t start, unsigned short blocks)
-{
- pccb->cmd[0] = SCSI_READ6;
- pccb->cmd[1] = pccb->lun << 5 | ((unsigned char)(start >> 16) & 0x1f);
- pccb->cmd[2] = (unsigned char)(start >> 8) & 0xff;
- pccb->cmd[3] = (unsigned char)start & 0xff;
- pccb->cmd[4] = (unsigned char)blocks & 0xff;
- pccb->cmd[5] = 0;
- pccb->cmdlen = 6;
- pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
- debug("scsi_setup_read6: cmd: %02X %02X startblk %02X%02X blccnt %02X\n",
- pccb->cmd[0], pccb->cmd[1],
- pccb->cmd[2], pccb->cmd[3], pccb->cmd[4]);
-}
-
-
-void scsi_setup_inquiry(ccb *pccb)
+static void scsi_setup_inquiry(ccb *pccb)
{
pccb->cmd[0] = SCSI_INQUIRY;
pccb->cmd[1] = pccb->lun << 5;
#ifdef CONFIG_BLK
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
- int device = block_dev->devnum;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks = 0;
ccb *pccb = (ccb *)&tempccb;
- device &= 0xff;
/* Setup device */
- pccb->target = scsi_dev_desc[device].target;
- pccb->lun = scsi_dev_desc[device].lun;
+ pccb->target = block_dev->target;
+ pccb->lun = block_dev->lun;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
debug("\nscsi_read: dev %d startblk " LBAF
", blccnt " LBAF " buffer %lx\n",
- device, start, blks, (unsigned long)buffer);
+ block_dev->devnum, start, blks, (unsigned long)buffer);
do {
pccb->pdata = (unsigned char *)buf_addr;
#ifdef CONFIG_SYS_64BIT_LBA
if (start > SCSI_LBA48_READ) {
unsigned long blocks;
blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK);
- pccb->datalen = scsi_dev_desc[device].blksz * blocks;
+ pccb->datalen = block_dev->blksz * blocks;
scsi_setup_read16(pccb, start, blocks);
start += blocks;
blks -= blocks;
} else
#endif
if (blks > SCSI_MAX_READ_BLK) {
- pccb->datalen = scsi_dev_desc[device].blksz *
+ pccb->datalen = block_dev->blksz *
SCSI_MAX_READ_BLK;
smallblks = SCSI_MAX_READ_BLK;
scsi_setup_read_ext(pccb, start, smallblks);
start += SCSI_MAX_READ_BLK;
blks -= SCSI_MAX_READ_BLK;
} else {
- pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ pccb->datalen = block_dev->blksz * blks;
smallblks = (unsigned short)blks;
scsi_setup_read_ext(pccb, start, smallblks);
start += blks;
#ifdef CONFIG_BLK
struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
#endif
- int device = block_dev->devnum;
lbaint_t start, blks;
uintptr_t buf_addr;
unsigned short smallblks;
ccb *pccb = (ccb *)&tempccb;
- device &= 0xff;
-
/* Setup device */
- pccb->target = scsi_dev_desc[device].target;
- pccb->lun = scsi_dev_desc[device].lun;
+ pccb->target = block_dev->target;
+ pccb->lun = block_dev->lun;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n",
- __func__, device, start, blks, (unsigned long)buffer);
+ __func__, block_dev->devnum, start, blks, (unsigned long)buffer);
do {
pccb->pdata = (unsigned char *)buf_addr;
if (blks > SCSI_MAX_WRITE_BLK) {
- pccb->datalen = (scsi_dev_desc[device].blksz *
+ pccb->datalen = (block_dev->blksz *
SCSI_MAX_WRITE_BLK);
smallblks = SCSI_MAX_WRITE_BLK;
scsi_setup_write_ext(pccb, start, smallblks);
start += SCSI_MAX_WRITE_BLK;
blks -= SCSI_MAX_WRITE_BLK;
} else {
- pccb->datalen = scsi_dev_desc[device].blksz * blks;
+ pccb->datalen = block_dev->blksz * blks;
smallblks = (unsigned short)blks;
scsi_setup_write_ext(pccb, start, smallblks);
start += blks;
return blkcnt;
}
-int scsi_get_disk_count(void)
-{
- return scsi_max_devs;
-}
-
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
void scsi_init(void)
{
/* copy src to dest, skipping leading and trailing blanks
* and null terminate the string
*/
-void scsi_ident_cpy(unsigned char *dest, unsigned char *src, unsigned int len)
+static void scsi_ident_cpy(unsigned char *dest, unsigned char *src,
+ unsigned int len)
{
int start, end;
*dest = '\0';
}
-
-/* Trim trailing blanks, and NUL-terminate string
- */
-void scsi_trim_trail(unsigned char *str, unsigned int len)
-{
- unsigned char *p = str + len - 1;
-
- while (len-- > 0) {
- *p-- = '\0';
- if (*p != ' ')
- return;
- }
-}
-
-int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz)
+static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity,
+ unsigned long *blksz)
{
*capacity = 0;
/*
* Some setup (fill-in) routines
*/
-void scsi_setup_test_unit_ready(ccb *pccb)
+static void scsi_setup_test_unit_ready(ccb *pccb)
{
pccb->cmd[0] = SCSI_TST_U_RDY;
pccb->cmd[1] = pccb->lun << 5;
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
}
-/*
- * (re)-scan the scsi bus and reports scsi device info
- * to the user if mode = 1
+/**
+ * scsi_init_dev_desc_priv - initialize only SCSI specific blk_desc properties
+ *
+ * @dev_desc: Block device description pointer
+ */
+static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc)
+{
+ dev_desc->target = 0xff;
+ dev_desc->lun = 0xff;
+ dev_desc->log2blksz =
+ LOG2_INVALID(typeof(dev_desc->log2blksz));
+ dev_desc->type = DEV_TYPE_UNKNOWN;
+ dev_desc->vendor[0] = 0;
+ dev_desc->product[0] = 0;
+ dev_desc->revision[0] = 0;
+ dev_desc->removable = false;
+#ifndef CONFIG_BLK
+ dev_desc->block_read = scsi_read;
+ dev_desc->block_write = scsi_write;
+#endif
+}
+
+/**
+ * scsi_init_dev_desc - initialize all SCSI specific blk_desc properties
+ *
+ * @dev_desc: Block device description pointer
+ * @devnum: Device number
+ */
+static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum)
+{
+ dev_desc->lba = 0;
+ dev_desc->blksz = 0;
+ dev_desc->if_type = IF_TYPE_SCSI;
+ dev_desc->devnum = devnum;
+ dev_desc->part_type = PART_TYPE_UNKNOWN;
+
+ scsi_init_dev_desc_priv(dev_desc);
+}
+
+/**
+ * scsi_detect_dev - Detect scsi device
+ *
+ * @target: target id
+ * @dev_desc: block device description
+ *
+ * The scsi_detect_dev detects and fills a dev_desc structure when the device is
+ * detected. The LUN number is taken from the struct blk_desc *dev_desc.
+ *
+ * Return: 0 on success, error value otherwise
*/
-void scsi_scan(int mode)
+static int scsi_detect_dev(int target, struct blk_desc *dev_desc)
{
- unsigned char i, perq, modi, lun;
+ unsigned char perq, modi;
lbaint_t capacity;
unsigned long blksz;
ccb *pccb = (ccb *)&tempccb;
+ pccb->target = target;
+ pccb->lun = dev_desc->lun;
+ pccb->pdata = (unsigned char *)&tempbuff;
+ pccb->datalen = 512;
+ scsi_setup_inquiry(pccb);
+ if (scsi_exec(pccb) != true) {
+ if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
+ /*
+ * selection timeout => assuming no
+ * device present
+ */
+ debug("Selection timeout ID %d\n",
+ pccb->target);
+ return -ETIMEDOUT;
+ }
+ scsi_print_error(pccb);
+ return -ENODEV;
+ }
+ perq = tempbuff[0];
+ modi = tempbuff[1];
+ if ((perq & 0x1f) == 0x1f)
+ return -ENODEV; /* skip unknown devices */
+ if ((modi & 0x80) == 0x80) /* drive is removable */
+ dev_desc->removable = true;
+ /* get info for this device */
+ scsi_ident_cpy((unsigned char *)dev_desc->vendor,
+ &tempbuff[8], 8);
+ scsi_ident_cpy((unsigned char *)dev_desc->product,
+ &tempbuff[16], 16);
+ scsi_ident_cpy((unsigned char *)dev_desc->revision,
+ &tempbuff[32], 4);
+ dev_desc->target = pccb->target;
+ dev_desc->lun = pccb->lun;
+
+ pccb->datalen = 0;
+ scsi_setup_test_unit_ready(pccb);
+ if (scsi_exec(pccb) != true) {
+ if (dev_desc->removable) {
+ dev_desc->type = perq;
+ goto removable;
+ }
+ scsi_print_error(pccb);
+ return -EINVAL;
+ }
+ if (scsi_read_capacity(pccb, &capacity, &blksz)) {
+ scsi_print_error(pccb);
+ return -EINVAL;
+ }
+ dev_desc->lba = capacity;
+ dev_desc->blksz = blksz;
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
+ dev_desc->type = perq;
+ part_init(&dev_desc[0]);
+removable:
+ return 0;
+}
+
+/*
+ * (re)-scan the scsi bus and reports scsi device info
+ * to the user if mode = 1
+ */
+int scsi_scan(int mode)
+{
+ unsigned char i, lun;
+ int ret;
+
if (mode == 1)
printf("scanning bus for devices...\n");
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++) {
- scsi_dev_desc[i].target = 0xff;
- scsi_dev_desc[i].lun = 0xff;
- scsi_dev_desc[i].lba = 0;
- scsi_dev_desc[i].blksz = 0;
- scsi_dev_desc[i].log2blksz =
- LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
- scsi_dev_desc[i].type = DEV_TYPE_UNKNOWN;
- scsi_dev_desc[i].vendor[0] = 0;
- scsi_dev_desc[i].product[0] = 0;
- scsi_dev_desc[i].revision[0] = 0;
- scsi_dev_desc[i].removable = false;
- scsi_dev_desc[i].if_type = IF_TYPE_SCSI;
- scsi_dev_desc[i].devnum = i;
- scsi_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
-#ifndef CONFIG_BLK
- scsi_dev_desc[i].block_read = scsi_read;
- scsi_dev_desc[i].block_write = scsi_write;
-#endif
- }
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_DEVICE; i++)
+ scsi_init_dev_desc(&scsi_dev_desc[i], i);
+
scsi_max_devs = 0;
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
- pccb->target = i;
for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
- pccb->lun = lun;
- pccb->pdata = (unsigned char *)&tempbuff;
- pccb->datalen = 512;
- scsi_setup_inquiry(pccb);
- if (scsi_exec(pccb) != true) {
- if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
- /*
- * selection timeout => assuming no
- * device present
- */
- debug("Selection timeout ID %d\n",
- pccb->target);
- continue;
- }
- scsi_print_error(pccb);
- continue;
- }
- perq = tempbuff[0];
- modi = tempbuff[1];
- if ((perq & 0x1f) == 0x1f)
- continue; /* skip unknown devices */
- if ((modi & 0x80) == 0x80) /* drive is removable */
- scsi_dev_desc[scsi_max_devs].removable = true;
- /* get info for this device */
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc
- [scsi_max_devs].vendor[0],
- &tempbuff[8], 8);
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc
- [scsi_max_devs].product[0],
- &tempbuff[16], 16);
- scsi_ident_cpy((unsigned char *)&scsi_dev_desc
- [scsi_max_devs].revision[0],
- &tempbuff[32], 4);
- scsi_dev_desc[scsi_max_devs].target = pccb->target;
- scsi_dev_desc[scsi_max_devs].lun = pccb->lun;
-
- pccb->datalen = 0;
- scsi_setup_test_unit_ready(pccb);
- if (scsi_exec(pccb) != true) {
- if (scsi_dev_desc[scsi_max_devs].removable) {
- scsi_dev_desc[scsi_max_devs].type =
- perq;
- goto removable;
- }
- scsi_print_error(pccb);
- continue;
- }
- if (scsi_read_capacity(pccb, &capacity, &blksz)) {
- scsi_print_error(pccb);
+ scsi_dev_desc[scsi_max_devs].lun = lun;
+ ret = scsi_detect_dev(i, &scsi_dev_desc[scsi_max_devs]);
+ if (ret)
continue;
- }
- scsi_dev_desc[scsi_max_devs].lba = capacity;
- scsi_dev_desc[scsi_max_devs].blksz = blksz;
- scsi_dev_desc[scsi_max_devs].log2blksz =
- LOG2(scsi_dev_desc[scsi_max_devs].blksz);
- scsi_dev_desc[scsi_max_devs].type = perq;
- part_init(&scsi_dev_desc[scsi_max_devs]);
-removable:
+
if (mode == 1) {
- printf(" Device %d: ", scsi_max_devs);
+ printf(" Device %d: ", 0);
dev_print(&scsi_dev_desc[scsi_max_devs]);
} /* if mode */
scsi_max_devs++;
#ifndef CONFIG_SPL_BUILD
setenv_ulong("scsidevs", scsi_max_devs);
#endif
+ return 0;
}
#ifdef CONFIG_BLK
ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16);
new_gd = (gd_t *)ptr;
memcpy(new_gd, (void *)gd, sizeof(gd_t));
+#if CONFIG_IS_ENABLED(DM)
+ dm_fixup_for_gd_move(new_gd);
+#endif
#if !defined(CONFIG_ARM)
gd = new_gd;
#endif
}
#endif
-static int spl_mmc_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
+int spl_mmc_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
struct mmc *mmc = NULL;
u32 boot_mode;
if (part == 7)
part = 0;
- err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+ if (CONFIG_IS_ENABLED(MMC_TINY))
+ err = mmc_switch_part(mmc, part);
+ else
+ err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("spl: mmc partition switch failed\n");
return err;
break;
- case MMCSD_MODE_UNDEFINED:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
default:
puts("spl: mmc: wrong boot mode\n");
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_VCMA9=y
-CONFIG_IDENT_STRING="\n(c) 2003 - 2011 by MPL AG Switzerland, MEV-10080-001 unstable"
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="VCMA9 # "
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_UBI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
# CONFIG_BLK is not set
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_NOR=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_NOR_BOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_SPI_BOOT=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_SPI_FLASH=y
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_GADGET_SUPPORT=y
-CONFIG_SPL_USBETH_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
# CONFIG_AUTOBOOT is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_AM43XX=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_ISW_ENTRY_ADDR=0x40302ae0
+CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_DM_ETH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_MMC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Apalis T30 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_TARGET_ARNDALE=y
CONFIG_IDENT_STRING=" for ARNDALE"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ARNDALE # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SOUND=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra30 (Beaver) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra30 (Cardhu) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri T20 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri T30 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DM_ETH=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
+CONFIG_PMIC_LP873X=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_DM_REGULATOR_LP873X=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_DM_ETH=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_PMIC_LP873X=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_DM_REGULATOR_LP873X=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_ARCH_SNAPDRAGON=y
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C"
CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c"
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="dragonboard410c => "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_PM8916_GPIO=y
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DUOVERO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="duovero # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_TARGET_FLEA3=y
CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING="hikey"
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OMAP34XX=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP34XX=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
CONFIG_BOOTDELAY=10
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
CONFIG_BOOTDELAY=10
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_IDENT_STRING=" LS-XHL"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_USB_KEYBOARD=y
+# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
+CONFIG_SPI_FLASH=y
+CONFIG_CMD_SF=y
+CONFIG_SPI_FLASH_EON=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
CONFIG_AUTOBOOT_KEYED=y
+CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SAVEENV is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_ARCH_EXYNOS5=y
CONFIG_IDENT_STRING=" for ODROID-XU3"
CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ODROID-XU3 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_PANDORA=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Pandora # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP4_PANDA=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP4_SDP4430=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_OMAPL138_LCDK=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_TARGET_PEACH_PI=y
CONFIG_IDENT_STRING=" for Peach-Pi"
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Peach-Pi # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_TARGET_PEACH_PIT=y
CONFIG_IDENT_STRING=" for Peach-Pit"
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Peach-Pit # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="dask # "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_RARP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_BLK is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Plutux) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
+CONFIG_NETDEVICES=y
+CONFIG_RTL8139=y
CONFIG_PCI=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI_2=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b"
-CONFIG_OF_EMBED=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
CONFIG_TARGET_RPI_3_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
-CONFIG_OF_EMBED=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
CONFIG_TARGET_RPI_3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
-CONFIG_OF_EMBED=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARCH_BCM283X=y
CONFIG_TARGET_RPI=y
CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b"
-CONFIG_OF_EMBED=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_LCD=y
CONFIG_PHYS_TO_BUS=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_S32V234EVB=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_LIBFDT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_MMC=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CDP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_NETCONSOLE=y
CONFIG_MMC=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
CONFIG_CMD_RARP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CDP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_SMDK2410=y
-CONFIG_BOOTDELAY=5
-# CONFIG_SYS_STDIO_DEREGISTER is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="SMDK2410 # "
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_UBI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
CONFIG_TARGET_SMDK5250=y
CONFIG_IDENT_STRING=" for SMDK5250"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SMDK5250 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SPI_FLASH=y
CONFIG_TARGET_SMDK5420=y
CONFIG_IDENT_STRING=" for SMDK5420"
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SMDK5420 # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SPI_FLASH=y
CONFIG_TARGET_SNOW=y
CONFIG_IDENT_STRING=" for snow"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="snow # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_TARGET_SPRING=y
CONFIG_IDENT_STRING=" for spring"
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="spring # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_SOUND=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_LDO=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (TrimSlice) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_TS4600=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_UDOO_NEO=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_DHCP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_TARGET_USBARMORY=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra124 (Venice2) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_VEXPRESS64_JUNO=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="VExpress64# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA15_TC2=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA5X2=y
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_VEXPRESS_CA9X4=y
+CONFIG_DISTRO_DEFAULTS=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_SAMTEC_VINING_2000=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg"
+CONFIG_BOOTDELAY=0
+CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PCI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Tegra20 (Whistler) # "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
# CONFIG_DM_MMC_OPS is not set
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm019 dc5"
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_SPL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_SPL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
Almost all of the serial drivers have been converted as at January 2016. These
ones remain:
- mcfuart.c
serial_bfin.c
serial_pxa.c
- serial_s3c24x0.c
The deadline for this work was the end of January 2016. If no one steps
forward to convert these, at some point there may come a patch to remove them!
(component image node of a "fpga type").
- loadables : Unit name containing a list of additional binaries to be
loaded at their given locations. "loadables" is a comma-separated list
- of strings. U-Boot will load each binary at its given start-address.
+ of strings. U-Boot will load each binary at its given start-address and
+ may optionaly invoke additional post-processing steps on this binary based
+ on its component image node type.
The FDT blob is required to properly boot FDT based kernel, so the minimal
configuration for 2.6 FDT kernel is (kernel, fdt) pair.
if (ret)
return ret;
+ *descp = desc;
+ return 0;
} else if (desc->devnum > devnum) {
found_more = true;
}
#endif
}
+fdt_addr_t dev_get_addr_size_index(struct udevice *dev, int index,
+ fdt_size_t *size)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ /*
+ * Only get the size in this first call. We'll get the addr in the
+ * next call to the exisiting dev_get_xxx function which handles
+ * all config options.
+ */
+ fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ "reg", index, size, false);
+
+ /*
+ * Get the base address via the existing function which handles
+ * all Kconfig cases
+ */
+ return dev_get_addr_index(dev, index);
+#else
+ return FDT_ADDR_T_NONE;
+#endif
+}
+
fdt_addr_t dev_get_addr_name(struct udevice *dev, const char *name)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
return gd->dm_root;
}
+void dm_fixup_for_gd_move(struct global_data *new_gd)
+{
+ /* The sentinel node has moved, so update things that point to it */
+ new_gd->uclass_root.next->prev = &new_gd->uclass_root;
+ new_gd->uclass_root.prev->next = &new_gd->uclass_root;
+}
+
fdt_addr_t dm_get_translation_offset(void)
{
struct udevice *root = dm_root();
return 0;
}
-int cros_ec_decode_region(int argc, char * const argv[])
-{
- if (argc > 0) {
- if (0 == strcmp(*argv, "rw"))
- return EC_FLASH_REGION_RW;
- else if (0 == strcmp(*argv, "ro"))
- return EC_FLASH_REGION_RO;
-
- debug("%s: Invalid region '%s'\n", __func__, *argv);
- } else {
- debug("%s: Missing region parameter\n", __func__);
- }
-
- return -1;
-}
-
int cros_ec_decode_ec_flash(const void *blob, int node,
struct fdt_cros_ec *config)
{
option will be removed as soon as all DM_MMC drivers use it, as it
will the only supported behaviour.
+config SPL_MMC_TINY
+ bool "Tiny MMC framework in SPL"
+ help
+ Enable MMC framework tinification support. This option is useful if
+ if your SPL is extremely size constrained. Heed the warning, enable
+ this option if and only if you know exactly what you are doing, if
+ you are reading this help text, you most likely have no idea :-)
+
+ The MMC framework is reduced to bare minimum to be useful. No malloc
+ support is needed for the MMC framework operation with this option
+ enabled. The framework supports exactly one MMC device and exactly
+ one MMC driver. The MMC driver can be adjusted to avoid any malloc
+ operations too, which can remove the need for malloc support in SPL
+ and thus further reduce footprint.
+
config MSM_SDHCI
bool "Qualcomm SDHCI controller"
depends on DM_MMC && BLK && DM_MMC_OPS
SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
};
+#if CONFIG_IS_ENABLED(MMC_TINY)
+static struct mmc mmc_static;
+struct mmc *find_mmc_device(int dev_num)
+{
+ return &mmc_static;
+}
+
+void mmc_do_preinit(void)
+{
+ struct mmc *m = &mmc_static;
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ mmc_set_preinit(m, 1);
+#endif
+ if (m->preinit)
+ mmc_start_init(m);
+}
+
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
+{
+ return &mmc->block_dev;
+}
+#endif
+
#ifndef CONFIG_DM_MMC_OPS
__weak int board_mmc_getwp(struct mmc *mmc)
{
if (!mmc)
return 0;
- err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+ if (CONFIG_IS_ENABLED(MMC_TINY))
+ err = mmc_switch_part(mmc, block_dev->hwpart);
+ else
+ err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
+
if (err < 0)
return 0;
int mmc_init(struct mmc *mmc)
{
int err = 0;
- unsigned start;
+ __maybe_unused unsigned start;
#ifdef CONFIG_DM_MMC
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
initialized = 1;
#ifndef CONFIG_BLK
+#if !CONFIG_IS_ENABLED(MMC_TINY)
mmc_list_init();
+#endif
#endif
ret = mmc_probe(bis);
if (ret)
mmc_do_preinit();
return 0;
}
+
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+int mmc_set_bkops_enable(struct mmc *mmc)
+{
+ int err;
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+
+ err = mmc_send_ext_csd(mmc, ext_csd);
+ if (err) {
+ puts("Could not get ext_csd register values\n");
+ return err;
+ }
+
+ if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
+ puts("Background operations not supported on device\n");
+ return -EMEDIUMTYPE;
+ }
+
+ if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
+ puts("Background operations already enabled\n");
+ return 0;
+ }
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
+ if (err) {
+ puts("Failed to enable manual background operations\n");
+ return err;
+ }
+
+ puts("Enabled manual background operations\n");
+
+ return 0;
+}
+#endif
static struct list_head mmc_devices;
static int cur_dev_num = -1;
+#if !CONFIG_IS_ENABLED(MMC_TINY)
struct mmc *find_mmc_device(int dev_num)
{
struct mmc *m;
mmc_start_init(m);
}
}
+#endif
void mmc_list_init(void)
{
void print_mmc_devices(char separator) { }
#endif
+#if CONFIG_IS_ENABLED(MMC_TINY)
+static struct mmc mmc_static = {
+ .dsr_imp = 0,
+ .dsr = 0xffffffff,
+ .block_dev = {
+ .if_type = IF_TYPE_MMC,
+ .removable = 1,
+ .devnum = 0,
+ .block_read = mmc_bread,
+ .block_write = mmc_bwrite,
+ .block_erase = mmc_berase,
+ .part_type = 0,
+ },
+};
+
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
+{
+ struct mmc *mmc = &mmc_static;
+
+ mmc->cfg = cfg;
+ mmc->priv = priv;
+
+ return mmc;
+}
+
+void mmc_destroy(struct mmc *mmc)
+{
+}
+#else
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
{
struct blk_desc *bdesc;
/* only freeing memory for now */
free(mmc);
}
+#endif
static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
{
}
#endif
-#if defined(CONFIG_OMAP44XX)
-static void omap4_vmmc_pbias_config(struct mmc *mmc)
-{
- u32 value = 0;
-
- value = readl((*ctrl)->control_pbiaslite);
- value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
- writel(value, (*ctrl)->control_pbiaslite);
- value = readl((*ctrl)->control_pbiaslite);
- value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
- writel(value, (*ctrl)->control_pbiaslite);
-}
-#endif
-
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
-static void omap5_pbias_config(struct mmc *mmc)
-{
- u32 value = 0;
-
- value = readl((*ctrl)->control_pbias);
- value &= ~SDCARD_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
- udelay(10); /* wait 10 us */
- value &= ~SDCARD_BIAS_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
-
- palmas_mmc1_poweron_ldo();
-
- value = readl((*ctrl)->control_pbias);
- value |= SDCARD_BIAS_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
- udelay(150); /* wait 150 us */
- value |= SDCARD_PWRDNZ;
- writel(value, (*ctrl)->control_pbias);
- udelay(150); /* wait 150 us */
-}
-#endif
-
static unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
&prcm_base->iclken1_core);
#endif
-#if defined(CONFIG_OMAP44XX)
+#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
/* PBIAS config needed for MMC1 only */
if (mmc->block_dev.devnum == 0)
- omap4_vmmc_pbias_config(mmc);
-#endif
-#if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
- if (mmc->block_dev.devnum == 0)
- omap5_pbias_config(mmc);
+ vmmc_pbias_config(LDO_VOLT_3V0);
#endif
return 0;
writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}
-
static int omap_hsmmc_init_setup(struct mmc *mmc)
{
struct hsmmc *mmc_base;
case 1:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
- defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
- defined(CONFIG_AM33XX) || \
+ defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
defined(CONFIG_HSMMC2_8BIT)
/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
#ifdef OMAP_HSMMC3_BASE
case 2:
priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
-#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT)
+#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
/* Enable 8-bit interface for eMMC on DRA7XX */
host_caps_val |= MMC_MODE_8BIT;
#endif
/* Get device id */
dev_id = pinmux_decode_periph_id(blob, node);
- if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
+ if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
debug("MMC: Can't get device id\n");
return -EINVAL;
}
cmd = FLASH_CMD_PROTECT_SET;
else
cmd = FLASH_CMD_PROTECT_CLEAR;
- flash_write_cmd(info, sector, 0,
- FLASH_CMD_PROTECT);
+
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
flash_write_cmd(info, sector, 0, cmd);
/* re-enable interrupts if necessary */
if (flag)
#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
nand->options |= NAND_NO_SUBPAGE_WRITE;
#endif
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ nand->options |= NAND_BUSWIDTH_16;
+#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
- /* IGB is cool */
- if (hw->mac_type == e1000_igb)
- return;
switch (hw->mac_type) {
+ case e1000_igb: /* IGB is cool */
+ return;
case e1000_82571:
case e1000_82572:
/* Clear PHY TX compatible mode bits */
static struct rtl8169_private *tpc;
-static const u16 rtl8169_intr_mask =
- SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
- TxOK | RxErr | RxOK;
static const unsigned int rtl8169_rx_config =
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
- printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
+ printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
#define SH7751_PCI_IO_BASE 0xFE240000
#define SH7751_PCI_IO_SIZE 0x00040000
-#define SH7751_CS3_BASE_ADDR 0x0C000000
-#define SH7751_P2CS3_BASE_ADDR 0xAC000000
-
#define SH7751_PCIPAR (vu_long *)0xFE2001C0
#define SH7751_PCIPDR (vu_long *)0xFE200220
/* Set up target memory mappings (for external DMA access) */
/* Map both P0 and P2 range to Area 3 RAM for ease of use */
- p4_out((64 - 1) << 20, SH7751_PCILSR0);
- p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
+ p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
+ p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
+ p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
+
p4_out(0, SH7751_PCILSR1);
p4_out(0, SH7751_PCILAR1);
- p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
p4_out(0xd0000000, SH7751_PCICONF6);
/* Map memory window to same address on PCI bus */
p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
/* Map IO window to same address on PCI bus */
- p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
+ p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
/* set BREQEN */
p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
#define rb_pin_pu_tx BIT(18)
#define rb_pin_tx_idle BIT(19)
#define rf_gen_rx_sel_shift 22
-#define rf_gen_rx_select (0xFF << rf_gen_rx_sel_shift)
+#define rf_gen_rx_select (0x0F << rf_gen_rx_sel_shift)
#define rf_gen_tx_sel_shift 26
-#define rf_gen_tx_select (0xFF << rf_gen_tx_sel_shift)
+#define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
#define rb_phy_rx_init BIT(30)
#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28)
#endif
}
-int palmas_mmc1_poweron_ldo(void)
+#if defined(CONFIG_OMAP54XX)
+int lp873x_mmc1_poweron_ldo(uint voltage)
+{
+ if (palmas_i2c_write_u8(LP873X_LDO1_ADDR, LP873X_LDO1_VOLTAGE,
+ voltage)) {
+ printf("lp873x: could not set LDO1 voltage.\n");
+ return 1;
+ }
+ /* TURN ON LDO1 */
+ if (palmas_i2c_write_u8(LP873X_LDO1_ADDR, LP873X_LDO1_CTRL,
+ LP873X_LDO_CTRL_EN | LP873X_LDO_CTRL_RDIS_EN)) {
+ printf("lp873x: could not turn on LDO1.\n");
+ return 1;
+ }
+ return 0;
+
+}
+#endif
+
+int palmas_mmc1_poweron_ldo(uint voltage)
{
u8 val = 0;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
/*
* Currently valid for the dra7xx_evm board:
* Set TPS659038 LDO1 to 3.0 V
#include <div64.h>
#include <asm/arch/imx-regs.h>
-/* pwm_id from 0..3 */
+/* pwm_id from 0..7 */
struct pwm_regs *pwm_id_to_reg(int pwm_id)
{
switch (pwm_id) {
return (struct pwm_regs *)PWM3_BASE_ADDR;
case 3:
return (struct pwm_regs *)PWM4_BASE_ADDR;
+#ifdef CONFIG_MX6SX
+ case 4:
+ return (struct pwm_regs *)PWM5_BASE_ADDR;
+ case 5:
+ return (struct pwm_regs *)PWM6_BASE_ADDR;
+ case 6:
+ return (struct pwm_regs *)PWM7_BASE_ADDR;
+ case 7:
+ return (struct pwm_regs *)PWM8_BASE_ADDR;
+#endif
default:
printf("unknown pwm_id: %d\n", pwm_id);
break;
drivers to perform the actual functions. See rtc.h for a
description of the API.
+config RTC_PCF2127
+ bool "Enable PCF2127 driver"
+ depends on DM_RTC
+ help
+ Enable pcf2127 driver which provides rtc get and set function
+
endmenu
obj-$(CONFIG_RTC_MX27) += mx27rtc.o
obj-$(CONFIG_RTC_MXS) += mxsrtc.o
obj-$(CONFIG_RTC_PCF8563) += pcf8563.o
+obj-$(CONFIG_RTC_PCF2127) += pcf2127.o
obj-$(CONFIG_RTC_PL031) += pl031.o
obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
--- /dev/null
+/*
+ * Copyright (C) 2016 by NXP Semiconductors Inc.
+ * Date & Time support for PCF2127 RTC
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <i2c.h>
+#include <rtc.h>
+
+#define PCF2127_REG_CTRL1 (0x00)
+#define PCF2127_REG_CTRL2 (0x01)
+#define PCF2127_REG_CTRL3 (0x02)
+#define PCF2127_REG_SC (0x03) /* datetime */
+#define PCF2127_REG_MN (0x04)
+#define PCF2127_REG_HR (0x05)
+#define PCF2127_REG_DM (0x06)
+#define PCF2127_REG_DW (0x07)
+#define PCF2127_REG_MO (0x08)
+#define PCF2127_REG_YR (0x09)
+
+static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ uchar buf[8];
+ int i = 0;
+
+ /* start register address */
+ buf[i++] = PCF2127_REG_SC;
+
+ /* hours, minutes and seconds */
+ buf[i++] = bin2bcd(tm->tm_sec);
+ buf[i++] = bin2bcd(tm->tm_min);
+ buf[i++] = bin2bcd(tm->tm_hour);
+ buf[i++] = bin2bcd(tm->tm_mday);
+ buf[i++] = tm->tm_wday & 0x07;
+
+ /* month, 1 - 12 */
+ buf[i++] = bin2bcd(tm->tm_mon + 1);
+
+ /* year */
+ buf[i++] = bin2bcd(tm->tm_year % 100);
+
+ /* write register's data */
+ if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
+ return -1;
+
+ return 0;
+}
+
+static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ int rel = 0;
+ uchar buf[10] = { PCF2127_REG_CTRL1 };
+
+ if (dm_i2c_write(dev, PCF2127_REG_CTRL1, buf, 1) < 0)
+ return -1;
+ if (dm_i2c_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf)) < 0)
+ return -1;
+
+ if (buf[PCF2127_REG_CTRL3] & 0x04)
+ puts("### Warning: RTC Low Voltage - date/time not reliable\n");
+
+ tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
+ tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
+ tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F);
+ tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
+ tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1;
+ tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]) + 1900;
+ if (tm->tm_year < 1970)
+ tm->tm_year += 100; /* assume we are in 1970...2069 */
+ tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return rel;
+}
+
+static int pcf2127_rtc_reset(struct udevice *dev)
+{
+ /*Doing nothing here*/
+ return 0;
+}
+
+static const struct rtc_ops pcf2127_rtc_ops = {
+ .get = pcf2127_rtc_get,
+ .set = pcf2127_rtc_set,
+ .reset = pcf2127_rtc_reset,
+};
+
+static const struct udevice_id pcf2127_rtc_ids[] = {
+ { .compatible = "pcf2127-rtc" },
+ { }
+};
+
+U_BOOT_DRIVER(rtc_pcf2127) = {
+ .name = "rtc-pcf2127",
+ .id = UCLASS_RTC,
+ .of_match = pcf2127_rtc_ids,
+ .ops = &pcf2127_rtc_ops,
+};
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
endif
-obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SERIAL1
-#define UART_NR S3C24X0_UART0
-
-#elif defined(CONFIG_SERIAL2)
-#define UART_NR S3C24X0_UART1
-
-#elif defined(CONFIG_SERIAL3)
-#define UART_NR S3C24X0_UART2
-
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-
-#include <asm/io.h>
-#include <serial.h>
-
-/* Multi serial device functions */
-#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \
- int s3serial##port##_init(void) \
- { \
- return serial_init_dev(port); \
- } \
- void s3serial##port##_setbrg(void) \
- { \
- serial_setbrg_dev(port); \
- } \
- int s3serial##port##_getc(void) \
- { \
- return serial_getc_dev(port); \
- } \
- int s3serial##port##_tstc(void) \
- { \
- return serial_tstc_dev(port); \
- } \
- void s3serial##port##_putc(const char c) \
- { \
- serial_putc_dev(port, c); \
- } \
- void s3serial##port##_puts(const char *s) \
- { \
- serial_puts_dev(port, s); \
- }
-
-#define INIT_S3C_SERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = s3serial##port##_init, \
- .stop = NULL, \
- .setbrg = s3serial##port##_setbrg, \
- .getc = s3serial##port##_getc, \
- .tstc = s3serial##port##_tstc, \
- .putc = s3serial##port##_putc, \
- .puts = s3serial##port##_puts, \
-}
-
-static void _serial_setbrg(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- unsigned int reg = 0;
- int i;
-
- /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
- reg = get_PCLK() / (16 * gd->baudrate) - 1;
-
- writel(reg, &uart->ubrdiv);
- for (i = 0; i < 100; i++)
- /* Delay */ ;
-}
-
-static inline void serial_setbrg_dev(unsigned int dev_index)
-{
- _serial_setbrg(dev_index);
-}
-
-/* Initialise the serial port. The settings are always 8 data bits, no parity,
- * 1 stop bit, no start bits.
- */
-static int serial_init_dev(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- /* FIFO enable, Tx/Rx FIFO clear */
- writel(0x07, &uart->ufcon);
- writel(0x0, &uart->umcon);
-
- /* Normal,No parity,1 stop,8 bit */
- writel(0x3, &uart->ulcon);
- /*
- * tx=level,rx=edge,disable timeout int.,enable rx error int.,
- * normal,interrupt or polling
- */
- writel(0x245, &uart->ucon);
-
- _serial_setbrg(dev_index);
-
- return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int _serial_getc(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- while (!(readl(&uart->utrstat) & 0x1))
- /* wait for character to arrive */ ;
-
- return readb(&uart->urxh) & 0xff;
-}
-
-static inline int serial_getc_dev(unsigned int dev_index)
-{
- return _serial_getc(dev_index);
-}
-
-/*
- * Output a single byte to the serial port.
- */
-static void _serial_putc(const char c, const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-
- while (!(readl(&uart->utrstat) & 0x2))
- /* wait for room in the tx FIFO */ ;
-
- writeb(c, &uart->utxh);
-}
-
-static inline void serial_putc_dev(unsigned int dev_index, const char c)
-{
- _serial_putc(c, dev_index);
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int _serial_tstc(const int dev_index)
-{
- struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
-
- return readl(&uart->utrstat) & 0x1;
-}
-
-static inline int serial_tstc_dev(unsigned int dev_index)
-{
- return _serial_tstc(dev_index);
-}
-
-static void _serial_puts(const char *s, const int dev_index)
-{
- while (*s) {
- _serial_putc(*s++, dev_index);
- }
-}
-
-static inline void serial_puts_dev(int dev_index, const char *s)
-{
- _serial_puts(s, dev_index);
-}
-
-DECLARE_S3C_SERIAL_FUNCTIONS(0);
-struct serial_device s3c24xx_serial0_device =
-INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0");
-DECLARE_S3C_SERIAL_FUNCTIONS(1);
-struct serial_device s3c24xx_serial1_device =
-INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1");
-DECLARE_S3C_SERIAL_FUNCTIONS(2);
-struct serial_device s3c24xx_serial2_device =
-INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2");
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if defined(CONFIG_SERIAL1)
- return &s3c24xx_serial0_device;
-#elif defined(CONFIG_SERIAL2)
- return &s3c24xx_serial1_device;
-#elif defined(CONFIG_SERIAL3)
- return &s3c24xx_serial2_device;
-#else
-#error "CONFIG_SERIAL? missing."
-#endif
-}
-
-void s3c24xx_serial_initialize(void)
-{
- serial_register(&s3c24xx_serial0_device);
- serial_register(&s3c24xx_serial1_device);
- serial_register(&s3c24xx_serial2_device);
-}
priv->base = (struct ti_qspi_regs *)QSPI_BASE;
priv->mode = mode;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
priv->fclk = QSPI_DRA7XX_FCLK;
#define PREFIX "lpc_tpm: "
+enum i2c_chip_type {
+ SLB9635,
+ AT97SC3204,
+};
+
+static const char * const chip_name[] = {
+ [SLB9635] = "Infineon SLB9635 TT 1.2",
+ [AT97SC3204] = "Atmel AT97SC3204",
+};
+
+static const u32 chip_didvid[] = {
+ [SLB9635] = 0xb15d1,
+ [AT97SC3204] = 0x32041114,
+};
+
struct tpm_locality {
u32 access;
u8 padding0[4];
static int tpm_tis_lpc_probe(struct udevice *dev)
{
struct tpm_tis_lpc_priv *priv = dev_get_priv(dev);
- u32 vid, did;
fdt_addr_t addr;
u32 didvid;
+ ulong chip_type = dev_get_driver_data(dev);
addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
priv->regs = map_sysmem(addr, 0);
didvid = tpm_read_word(priv, &priv->regs[0].did_vid);
- vid = didvid & 0xffff;
- did = (didvid >> 16) & 0xffff;
- if (vid != 0x15d1 || did != 0xb) {
+ if (didvid != chip_didvid[chip_type]) {
+ u32 vid, did;
+ vid = didvid & 0xffff;
+ did = (didvid >> 16) & 0xffff;
debug("Invalid vendor/device ID %04x/%04x\n", vid, did);
- return -ENOSYS;
+ return -ENODEV;
}
- debug("Found TPM %s by %s\n", "SLB9635 TT 1.2", "Infineon");
+ debug("Found TPM: %s\n", chip_name[chip_type]);
return 0;
}
static int tpm_tis_get_desc(struct udevice *dev, char *buf, int size)
{
+ ulong chip_type = dev_get_driver_data(dev);
+
if (size < 50)
return -ENOSPC;
- return snprintf(buf, size, "1.2 TPM (vendor %s, chip %s)",
- "Infineon", "SLB9635 TT 1.2");
+ return snprintf(buf, size, "1.2 TPM (%s)",
+ chip_name[chip_type]);
}
};
static const struct udevice_id tpm_tis_lpc_ids[] = {
- { .compatible = "infineon,slb9635lpc" },
+ { .compatible = "infineon,slb9635lpc", .data = SLB9635 },
+ { .compatible = "atmel,at97sc3204", .data = AT97SC3204 },
{ }
};
val = readl(phy->usb2_phy_power);
if (on) {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
if (phy->index == 1)
val &= ~OMAP_CTRL_USB2_PHY_PD;
else
AM437X_CTRL_USB2_OTGSESSEND_EN);
#endif
} else {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#if defined(CONFIG_DRA7XX)
if (phy->index == 1)
val |= OMAP_CTRL_USB2_PHY_PD;
else
} else if (tp->version == RTL_VER_04) {
r8153_pre_ram_code(tp, 0x7001);
- for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
- ocp_write_word(tp, MCU_TYPE_PLA,
- r8153_ram_code_bc[i],
- r8153_ram_code_bc[i+1]);
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_bc[i],
+ r8153_ram_code_bc[i+1]);
r8153_post_ram_code(tp);
#include "gadget_chips.h"
#include "rndis.h"
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
#define USB_NET_NAME "usb_ether"
#define atomic_read
/* Based on linux 2.6.27 version */
#define DRIVER_VERSION "May Day 2005"
-static const char shortname[] = "ether";
static const char driver_desc[] = DRIVER_DESC;
#define RX_EXTRA 20 /* guard against rx overflows */
struct usb_gadget *gadget;
struct usb_request *req; /* for control responses */
struct usb_request *stat_req; /* for cdc & rndis status */
+#ifdef CONFIG_DM_USB
+ struct udevice *usb_udev;
+#endif
u8 config;
struct usb_ep *in_ep, *out_ep, *status_ep;
*/
/*-------------------------------------------------------------------------*/
-static struct eth_dev l_ethdev;
-static struct eth_device l_netdev;
-static struct usb_gadget_driver eth_driver;
+struct ether_priv {
+ struct eth_dev ethdev;
+ struct eth_device netdev;
+ struct usb_gadget_driver eth_driver;
+};
+
+struct ether_priv eth_priv;
+struct ether_priv *l_priv = ð_priv;
/*-------------------------------------------------------------------------*/
event->bNotificationType, value);
if (event->bNotificationType ==
USB_CDC_NOTIFY_SPEED_CHANGE) {
- l_ethdev.network_started = 1;
+ dev->network_started = 1;
printf("USB network up!\n");
}
}
* that network is working. So we signalize it
* here.
*/
- l_ethdev.network_started = 1;
+ dev->network_started = 1;
debug("USB network up!\n");
goto done_set_intf;
}
debug("rndis control ack complete --> %d, %d/%d\n",
req->status, req->actual, req->length);
- if (!l_ethdev.network_started) {
+ if (!dev->network_started) {
if (rndis_get_state(dev->rndis_config)
== RNDIS_DATA_INITIALIZED) {
- l_ethdev.network_started = 1;
+ dev->network_started = 1;
printf("USB RNDIS network up!\n");
}
}
static int rndis_control_ack(struct eth_device *net)
{
- struct eth_dev *dev = &l_ethdev;
+ struct ether_priv *priv = (struct ether_priv *)net->priv;
+ struct eth_dev *dev = &priv->ethdev;
int length;
struct usb_request *resp = dev->stat_req;
static int eth_bind(struct usb_gadget *gadget)
{
- struct eth_dev *dev = &l_ethdev;
+ struct eth_dev *dev = &l_priv->ethdev;
u8 cdc = 1, zlp = 1, rndis = 1;
struct usb_ep *in_ep, *out_ep, *status_ep = NULL;
int status = -ENOMEM;
/* network device setup */
- dev->net = &l_netdev;
+ dev->net = &l_priv->netdev;
dev->cdc = cdc;
dev->zlp = zlp;
/*-------------------------------------------------------------------------*/
-static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
+#ifdef CONFIG_DM_USB
+int dm_usb_init(struct eth_dev *e_dev)
{
- struct eth_dev *dev = &l_ethdev;
+ struct udevice *dev = NULL;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_USB_DEV_GENERIC, &dev);
+ if (!dev || ret) {
+ error("No USB device found\n");
+ return -ENODEV;
+ }
+
+ e_dev->usb_udev = dev;
+
+ return ret;
+}
+#endif
+
+static int _usb_eth_init(struct ether_priv *priv)
+{
+ struct eth_dev *dev = &priv->ethdev;
struct usb_gadget *gadget;
unsigned long ts;
unsigned long timeout = USB_CONNECT_TIMEOUT;
- if (!netdev) {
- error("received NULL ptr");
- goto fail;
+#ifdef CONFIG_DM_USB
+ if (dm_usb_init(dev)) {
+ error("USB ether not found\n");
+ return -ENODEV;
}
-
+#else
board_usb_init(0, USB_INIT_DEVICE);
+#endif
/* Configure default mac-addresses for the USB ethernet device */
#ifdef CONFIG_USBNET_DEV_ADDR
goto fail;
}
- if (usb_gadget_register_driver(ð_driver) < 0)
+ priv->eth_driver.speed = DEVSPEED;
+ priv->eth_driver.bind = eth_bind;
+ priv->eth_driver.unbind = eth_unbind;
+ priv->eth_driver.setup = eth_setup;
+ priv->eth_driver.reset = eth_disconnect;
+ priv->eth_driver.disconnect = eth_disconnect;
+ priv->eth_driver.suspend = eth_suspend;
+ priv->eth_driver.resume = eth_resume;
+ if (usb_gadget_register_driver(&priv->eth_driver) < 0)
goto fail;
dev->network_started = 0;
timeout = simple_strtoul(getenv("cdc_connect_timeout"),
NULL, 10) * CONFIG_SYS_HZ;
ts = get_timer(0);
- while (!l_ethdev.network_started) {
+ while (!dev->network_started) {
/* Handle control-c and timeouts */
if (ctrlc() || (get_timer(ts) > timeout)) {
error("The remote end did not respond in time.");
return -1;
}
-static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
+static int _usb_eth_send(struct ether_priv *priv, void *packet, int length)
{
int retval;
void *rndis_pkt = NULL;
- struct eth_dev *dev = &l_ethdev;
+ struct eth_dev *dev = &priv->ethdev;
struct usb_request *req = dev->tx_req;
unsigned long ts;
unsigned long timeout = USB_CONNECT_TIMEOUT;
return -ENOMEM;
}
-static int usb_eth_recv(struct eth_device *netdev)
+static int _usb_eth_recv(struct ether_priv *priv)
{
- struct eth_dev *dev = &l_ethdev;
-
usb_gadget_handle_interrupts(0);
- if (packet_received) {
- debug("%s: packet received\n", __func__);
- if (dev->rx_req) {
- net_process_received_packet(net_rx_packets[0],
- dev->rx_req->length);
- packet_received = 0;
-
- rx_submit(dev, dev->rx_req, 0);
- } else
- error("dev->rx_req invalid");
- }
return 0;
}
-void usb_eth_halt(struct eth_device *netdev)
+void _usb_eth_halt(struct ether_priv *priv)
{
- struct eth_dev *dev = &l_ethdev;
-
- if (!netdev) {
- error("received NULL ptr");
- return;
- }
+ struct eth_dev *dev = &priv->ethdev;
/* If the gadget not registered, simple return */
if (!dev->gadget)
dev->network_started = 0;
}
- usb_gadget_unregister_driver(ð_driver);
+ usb_gadget_unregister_driver(&priv->eth_driver);
+#ifdef CONFIG_DM_USB
+ device_remove(dev->usb_udev);
+#else
board_usb_cleanup(0, USB_INIT_DEVICE);
+#endif
+}
+
+static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
+
+ return _usb_eth_init(priv);
}
-static struct usb_gadget_driver eth_driver = {
- .speed = DEVSPEED,
+static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
- .bind = eth_bind,
- .unbind = eth_unbind,
+ return _usb_eth_send(priv, packet, length);
+}
- .setup = eth_setup,
- .reset = eth_disconnect,
- .disconnect = eth_disconnect,
+static int usb_eth_recv(struct eth_device *netdev)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
+ struct eth_dev *dev = &priv->ethdev;
+ int ret;
+
+ ret = _usb_eth_recv(priv);
+ if (ret) {
+ error("error packet receive\n");
+ return ret;
+ }
- .suspend = eth_suspend,
- .resume = eth_resume,
-};
+ if (!packet_received)
+ return 0;
+
+ if (dev->rx_req) {
+ net_process_received_packet(net_rx_packets[0],
+ dev->rx_req->length);
+ } else {
+ error("dev->rx_req invalid");
+ }
+ packet_received = 0;
+ rx_submit(dev, dev->rx_req, 0);
+
+ return 0;
+}
+
+void usb_eth_halt(struct eth_device *netdev)
+{
+ struct ether_priv *priv = (struct ether_priv *)netdev->priv;
+
+ _usb_eth_halt(priv);
+}
int usb_eth_initialize(bd_t *bi)
{
- struct eth_device *netdev = &l_netdev;
+ struct eth_device *netdev = &l_priv->netdev;
strlcpy(netdev->name, USB_NET_NAME, sizeof(netdev->name));
netdev->send = usb_eth_send;
netdev->recv = usb_eth_recv;
netdev->halt = usb_eth_halt;
+ netdev->priv = l_priv;
#ifdef CONFIG_MCAST_TFTP
#error not supported
help
Enables the MUSB USB dual-role controller in gadget mode.
+config USB_MUSB_TI
+ bool "Enable TI OTG USB controller"
+ depends on DM_USB
+ default n
+ help
+ Say y here to enable support for the dual role high
+ speed USB controller based on the Mentor Graphics
+ silicon IP.
+
if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_PIC32
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
+obj-$(CONFIG_USB_MUSB_TI) += ti-musb.o
ccflags-y := $(call cc-option,-Wno-unused-variable) \
$(call cc-option,-Wno-unused-but-set-variable) \
if (ret == IRQ_HANDLED || epintr || usbintr) {
/* clear level interrupt */
if (data->clear_irq)
- data->clear_irq();
+ data->clear_irq(data->dev);
/* write EOI */
musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
}
/* Reset the musb */
if (data->reset)
- data->reset();
+ data->reset(data->dev);
/* Reset the controller */
musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
msleep(5);
/* clear level interrupt */
if (data->clear_irq)
- data->clear_irq();
+ data->clear_irq(data->dev);
return 0;
}
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
#ifndef __UBOOT__
usb_put_phy(musb->xceiv);
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
clk_disable(glue->phy_clk);
clk_disable(glue->clk);
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
ret = clk_enable(glue->phy_clk);
if (ret) {
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
musb->isr = dsps_interrupt;
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
#ifndef __UBOOT__
/* NOP driver needs change if supporting dual instance */
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(0);
+ data->set_phy_power(data->dev, 0);
return 0;
}
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
- data->set_phy_power(1);
+ data->set_phy_power(data->dev, 1);
return 0;
}
--- /dev/null
+/*
+ * MISC driver for TI MUSB Glue.
+ *
+ * (C) Copyright 2016
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+#include <linux/usb/otg.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+#include <asm/io.h>
+#include <asm/omap_musb.h>
+#include "musb_uboot.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_USB
+
+/* USB 2.0 PHY Control */
+#define CM_PHY_PWRDN (1 << 0)
+#define CM_PHY_OTG_PWRDN (1 << 1)
+#define OTGVDET_EN (1 << 19)
+#define OTGSESSENDEN (1 << 20)
+
+#define AM335X_USB1_CTRL 0x8
+
+struct ti_musb_platdata {
+ void *base;
+ void *ctrl_mod_base;
+ struct musb_hdrc_platform_data plat;
+ struct musb_hdrc_config musb_config;
+ struct omap_musb_board_data otg_board_data;
+};
+
+static int ti_musb_get_usb_index(int node)
+{
+ const void *fdt = gd->fdt_blob;
+ int i = 0;
+ char path[64];
+ const char *alias_path;
+ char alias[16];
+
+ fdt_get_path(fdt, node, path, sizeof(path));
+
+ do {
+ snprintf(alias, sizeof(alias), "usb%d", i);
+ alias_path = fdt_get_alias(fdt, alias);
+ if (alias_path == NULL) {
+ debug("USB index not found\n");
+ return -ENOENT;
+ }
+
+ if (!strcmp(path, alias_path))
+ return i;
+
+ i++;
+ } while (alias_path);
+
+ return -ENOENT;
+}
+
+static void ti_musb_set_phy_power(struct udevice *dev, u8 on)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+
+ if (on) {
+ clrsetbits_le32(platdata->ctrl_mod_base,
+ CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
+ OTGVDET_EN | OTGSESSENDEN);
+ } else {
+ clrsetbits_le32(platdata->ctrl_mod_base, 0,
+ CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
+ }
+}
+
+static int ti_musb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+ int phys;
+ int ctrl_mod;
+ int usb_index;
+
+ platdata->base = (void *)dev_get_addr_index(dev, 1);
+
+ phys = fdtdec_lookup_phandle(fdt, node, "phys");
+ ctrl_mod = fdtdec_lookup_phandle(fdt, phys, "ti,ctrl_mod");
+ platdata->ctrl_mod_base = (void *)fdtdec_get_addr(fdt, ctrl_mod, "reg");
+ usb_index = ti_musb_get_usb_index(node);
+ switch (usb_index) {
+ case 1:
+ platdata->ctrl_mod_base += AM335X_USB1_CTRL;
+ case 0:
+ default:
+ break;
+ }
+
+ platdata->musb_config.multipoint = fdtdec_get_int(fdt, node,
+ "mentor,multipoint",
+ -1);
+ if (platdata->musb_config.multipoint < 0) {
+ error("MUSB multipoint DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->musb_config.dyn_fifo = 1;
+
+ platdata->musb_config.num_eps = fdtdec_get_int(fdt, node,
+ "mentor,num-eps", -1);
+ if (platdata->musb_config.num_eps < 0) {
+ error("MUSB num-eps DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->musb_config.ram_bits = fdtdec_get_int(fdt, node,
+ "mentor,ram-bits", -1);
+ if (platdata->musb_config.ram_bits < 0) {
+ error("MUSB ram-bits DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->otg_board_data.set_phy_power = ti_musb_set_phy_power;
+ platdata->otg_board_data.dev = dev;
+ platdata->plat.config = &platdata->musb_config;
+
+ platdata->plat.power = fdtdec_get_int(fdt, node, "mentor,power", -1);
+ if (platdata->plat.power < 0) {
+ error("MUSB mentor,power DT entry missing\n");
+ return -ENOENT;
+ }
+
+ platdata->plat.platform_ops = &musb_dsps_ops;
+ platdata->plat.board_data = &platdata->otg_board_data;
+
+ return 0;
+}
+
+static int ti_musb_host_probe(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ struct omap_musb_board_data *otg_board_data;
+ int ret;
+
+ priv->desc_before_addr = true;
+
+ otg_board_data = &platdata->otg_board_data;
+
+ host->host = musb_init_controller(&platdata->plat,
+ (struct device *)otg_board_data,
+ platdata->base);
+ if (!host->host)
+ return -EIO;
+
+ ret = musb_lowlevel_init(host);
+
+ return ret;
+}
+
+static int ti_musb_host_remove(struct udevice *dev)
+{
+ struct musb_host_data *host = dev_get_priv(dev);
+
+ musb_stop(host->host);
+
+ return 0;
+}
+
+static int ti_musb_host_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ti_musb_platdata *platdata = dev_get_platdata(dev);
+ const void *fdt = gd->fdt_blob;
+ int node = dev->of_offset;
+ int ret;
+
+ ret = ti_musb_ofdata_to_platdata(dev);
+ if (ret) {
+ error("platdata dt parse error\n");
+ return ret;
+ }
+
+ platdata->plat.mode = MUSB_HOST;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ti_musb_host) = {
+ .name = "ti-musb-host",
+ .id = UCLASS_USB,
+ .ofdata_to_platdata = ti_musb_host_ofdata_to_platdata,
+ .probe = ti_musb_host_probe,
+ .remove = ti_musb_host_remove,
+ .ops = &musb_usb_ops,
+ .platdata_auto_alloc_size = sizeof(struct ti_musb_platdata),
+ .priv_auto_alloc_size = sizeof(struct musb_host_data),
+};
+
+static int ti_musb_wrapper_bind(struct udevice *parent)
+{
+ const void *fdt = gd->fdt_blob;
+ int node;
+ int ret;
+
+ for (node = fdt_first_subnode(fdt, parent->of_offset); node > 0;
+ node = fdt_next_subnode(fdt, node)) {
+ struct udevice *dev;
+ const char *name = fdt_get_name(fdt, node, NULL);
+ enum usb_dr_mode dr_mode;
+ struct driver *drv;
+
+ if (strncmp(name, "usb@", 4))
+ continue;
+
+ dr_mode = usb_get_dr_mode(node);
+ switch (dr_mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ /* Bind MUSB device */
+ break;
+ case USB_DR_MODE_HOST:
+ /* Bind MUSB host */
+ ret = device_bind_driver_to_node(parent, "ti-musb-host",
+ name, node, &dev);
+ if (ret) {
+ error("musb - not able to bind usb host node\n");
+ return ret;
+ }
+ break;
+ default:
+ break;
+ };
+ }
+ return 0;
+}
+
+static const struct udevice_id ti_musb_ids[] = {
+ { .compatible = "ti,am33xx-usb" },
+ { }
+};
+
+U_BOOT_DRIVER(ti_musb_wrapper) = {
+ .name = "ti-musb-wrapper",
+ .id = UCLASS_MISC,
+ .of_match = ti_musb_ids,
+ .bind = ti_musb_wrapper_bind,
+};
+
+#endif /* CONFIG_DM_USB */
ret = os_dirent_ls(dirname, &head);
if (ret)
- return ret;
+ goto out;
for (node = head; node; node = node->next) {
printf("%s %10lu %s\n", os_dirent_get_typename(node->type),
node->size, node->name);
}
+out:
os_dirent_free(head);
- return 0;
+ return ret;
}
int sandbox_fs_exists(const char *filename)
# include <sys/endian.h> /* htole32 and friends */
#elif defined(__OpenBSD__)
# include <endian.h>
+# define __BYTE_ORDER BYTE_ORDER
+# define __LITTLE_ENDIAN LITTLE_ENDIAN
+# define __BIG_ENDIAN BIG_ENDIAN
#endif
#include <time.h>
# define uswap_64(x) _uswap_64(x, )
#endif
-#if defined(__OpenBSD__)
-#define cpu_to_le16(x) htole16(x)
-#define cpu_to_le32(x) htole32(x)
-#define cpu_to_le64(x) htole64(x)
-#define le16_to_cpu(x) letoh16(x)
-#define le32_to_cpu(x) letoh32(x)
-#define le64_to_cpu(x) letoh64(x)
-#define cpu_to_be16(x) htobe16(x)
-#define cpu_to_be32(x) htobe32(x)
-#define cpu_to_be64(x) htobe64(x)
-#define be16_to_cpu(x) betoh16(x)
-#define be32_to_cpu(x) betoh32(x)
-#define be64_to_cpu(x) betoh64(x)
-#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#if __BYTE_ORDER == __LITTLE_ENDIAN
# define cpu_to_le16(x) (x)
# define cpu_to_le32(x) (x)
# define cpu_to_le64(x) (x)
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_CMD_PXE
-
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
-#define CONFIG_MENU
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_ISO_PARTITION
#ifndef CONFIG_CMDLINE
#undef CONFIG_CMDLINE_EDITING
#undef CONFIG_SYS_LONGHELP
-#undef CONFIG_MENU
#endif
#endif /* __CONFIG_FALLBACKS_H */
#ifndef __MIGO_R_H
#define __MIGO_R_H
-#undef DEBUG
#define CONFIG_CPU_SH7722 1
#define CONFIG_MIGO_R 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
+++ /dev/null
-/*
- * (C) Copyright 2002, 2003
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Configuation settings for the MPL VCMA9 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define MACH_TYPE_MPL_VCMA9 227
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_THUMB_BUILD
-
-#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
-#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
-#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
-#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
-/* input clock of PLL (VCMA9 has 12MHz input clock) */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_NAND
-
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * I2C stuff:
- * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
- * address 0x50 with 16bit addressing
- */
-#define CONFIG_SYS_I2C
-
-/* we use the built-in I2C controller */
-#define CONFIG_SYS_I2C_S3C24X0
-#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-/* use EEPROM for environment vars */
-#define CONFIG_ENV_IS_IN_EEPROM 1
-/* environment starts at offset 0 */
-#define CONFIG_ENV_OFFSET 0x000
-/* 2KB should be more than enough */
-#define CONFIG_ENV_SIZE 0x800
-
-#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-/* 64 bytes page write mode on 24C256 */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * Hardware drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x20000300
-#define CONFIG_CS8900_BUS16
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
-
-/* USB support (currently only works with D-cache off) */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_OHCI_S3C24XX
-#define CONFIG_DOS_PARTITION
-
-/* Enable needed helper functions */
-
-/* RTC */
-#define CONFIG_RTC_S3C24X0
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.0.110
-#define CONFIG_SERVERIP 10.0.0.1
-
-#if defined(CONFIG_CMD_KGDB)
-/* speed to run kgdb serial port */
-#define CONFIG_KGDB_BAUDRATE 115200
-#endif
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
-
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_SYS_LOAD_ADDR 0x30800000
-
-/* we configure PWM Timer 4 to 1ms 1000Hz */
-
-/* support additional compression methods */
-#define CONFIG_BZIP2
-#define CONFIG_LZO
-#define CONFIG_LZMA
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/* FLASH and environment organization */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT (19)
-
-/*
- * Size of malloc() pool
- * BZIP2 / LZO / LZMA need a lot of RAM
- */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-/* NAND configuration */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_S3C2410
-#define CONFIG_SYS_S3C2410_NAND_HWECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x4E000000
-#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
-#define CONFIG_S3C24XX_TACLS 1
-#define CONFIG_S3C24XX_TWRPH0 5
-#define CONFIG_S3C24XX_TWRPH1 3
-#endif
-
-#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-
-/* File system */
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_JFFS2
-#define CONFIG_YAFFS2
-#define CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#endif /* __CONFIG_H */
#define __CONFIG_AM335X_EVM_H
#include <configs/ti_am335x_common.h>
+#include <environment/ti/dfu.h>
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run init_console; " \
"run envboot; " \
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
- "boot_fdt=try\0" \
+ DEFAULT_FIT_TI_ARGS \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcloados=run args_mmc; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "run envboot; " \
- "if run loadimage; then " \
- "run mmcloados;" \
- "fi;" \
- "fi;\0" \
"spiboot=echo Booting from spi ...; " \
"run spiargs; " \
"sf probe ${spibusno}:0; " \
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
+#undef CONFIG_DM_USB
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-#ifdef CONFIG_NAND
-#define DFU_ALT_INFO_NAND \
- "dfu_alt_info_nand=" \
- "SPL part 0 1;" \
- "SPL.backup1 part 0 2;" \
- "SPL.backup2 part 0 3;" \
- "SPL.backup3 part 0 4;" \
- "u-boot part 0 5;" \
- "u-boot-spl-os part 0 6;" \
- "kernel part 0 8;" \
- "rootfs part 0 9\0"
-#else
-#define DFU_ALT_INFO_NAND ""
-#endif
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0xD80000;" \
- "fdt ram 0x80F80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
#define DFUARGS \
"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
DFU_ALT_INFO_MMC \
#undef CONFIG_CMD_EXT4_WRITE
#undef CONFIG_CMD_MMC_SPI
#undef CONFIG_CMD_SPI
-#undef CONFIG_CMD_PXE
#define CONFIG_CMD_CACHE
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#include <environment/ti/dfu.h>
#include <asm/arch/omap.h>
/* NS16550 Configuration */
#ifndef CONFIG_SPL_BUILD
/* USB Device Firmware Update support */
-
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
- "dfu_alt_info_emmc=" \
- "MLO raw 0x100 0x100 mmcpart 0;" \
- "u-boot.img raw 0x300 0x1000 mmcpart 0\0"
-
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-
-#define DFU_ALT_INFO_QSPI \
- "dfu_alt_info_qspi=" \
- "u-boot.bin raw 0x0 0x080000;" \
- "u-boot.backup raw 0x080000 0x080000;" \
- "u-boot-spl-os raw 0x100000 0x010000;" \
- "u-boot-env raw 0x110000 0x010000;" \
- "u-boot-env.backup raw 0x120000 0x010000;" \
- "kernel raw 0x130000 0x800000\0"
-
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_QSPI
+ DFU_ALT_INFO_QSPI_XIP
#else
#define DFUARGS
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"root=${ramroot} " \
"rootfstype=${ramrootfstype}\0" \
"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
- "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "setenv devnum ${mmcdev}; " \
- "setenv devtype mmc; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${devnum};" \
- "if run loadimage; then " \
- "run loadfdt; " \
- "echo Booting from mmc${mmcdev} ...; " \
- "run args_mmc; " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
- "fi;\0" \
"usbboot=" \
"setenv devnum ${usbdev}; " \
"setenv devtype usb; " \
DFUARGS \
#define CONFIG_BOOTCOMMAND \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run envboot;" \
"run mmcboot;" \
#ifndef __CONFIG_AM57XX_EVM_H
#define __CONFIG_AM57XX_EVM_H
-#define CONFIG_AM57XX
+#include <environment/ti/dfu.h>
+
+#define CONFIG_DRA7XX
#ifdef CONFIG_SPL_BUILD
#define CONFIG_IODELAY_RECALIBRATION
"name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
+#define DFUARGS \
+ "dfu_bufsiz=0x10000\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_RAM \
+
#include <configs/ti_omap5_common.h>
/* Enhance our eMMC support / experience. */
#ifndef __AP325RXA_H
#define __AP325RXA_H
-#undef DEBUG
#define CONFIG_CPU_SH7723 1
#define CONFIG_AP325RXA 1
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTARGS "console=ttySC2,38400"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9118 */
#ifndef __AP_SH4A_4A_H
#define __AP_SH4A_4A_H
-#undef DEBUG
#define CONFIG_CPU_SH7734 1
#define CONFIG_AP_SH4A_4A 1
#define CONFIG_400MHZ_MODE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC4,115200"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Ether */
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE 0x60000000
#define CONFIG_DA850_LOWLEVEL
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \
"${setupargs} ${vidargs}; echo Booting from NAND...; " \
- "ubi part ubi && ubifsmount ubi0:rootfs && " \
- "ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
- "ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+ "ubi part ubi && " \
+ "ubi read ${kernel_addr_r} kernel && " \
+ "ubi read ${fdt_addr_r} dtb && " \
"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#ifdef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_ARCH_CPU_INIT
#ifndef __CONFIG_DRA7XX_EVM_H
#define __CONFIG_DRA7XX_EVM_H
+#include <environment/ti/dfu.h>
+
#define CONFIG_DRA7XX
#define CONFIG_BOARD_EARLY_INIT_F
"name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
- "dfu_alt_info_emmc=" \
- "rawemmc raw 0 3751936;" \
- "boot part 1 1;" \
- "rootfs part 1 2;" \
- "MLO fat 1 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 1 1;" \
- "spl-os-image fat 1 1;" \
- "u-boot.img fat 1 1;" \
- "uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-
-#define DFU_ALT_INFO_QSPI \
- "dfu_alt_info_qspi=" \
- "MLO raw 0x0 0x040000;" \
- "u-boot.img raw 0x040000 0x0100000;" \
- "u-boot-spl-os raw 0x140000 0x080000;" \
- "u-boot-env raw 0x1C0000 0x010000;" \
- "u-boot-env.backup raw 0x1D0000 0x010000;" \
- "kernel raw 0x1E0000 0x800000\0"
-
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
#undef CONFIG_CMD_BOOTD
#ifdef CONFIG_SPL_DFU_SUPPORT
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_RAM
* 0x1800_0000 MFI 16bit
*/
-#undef DEBUG
#define CONFIG_CPU_SH7724 1
#define CONFIG_BOARD_LATE_INIT 1
#define CONFIG_ECOVEC 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* I2C */
/* Command definition */
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_BOARD_NAME EL6Q
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +40000;" \
- "erase ${uboot_addr} +40000;" \
+ "update=protect off ${uboot_addr} +80000;" \
+ "erase ${uboot_addr} +80000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
"upd=if run load;then echo Updating u-boot;if run update;" \
"then echo U-Boot updated;" \
#define CONFIG_FS_EXT4
/* Command line configuration */
-#define CONFIG_MENU
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_ENV
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_STACK 0x0091FFB8
+/*
+ * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO 0x11000
/* NAND support */
#if defined(CONFIG_SPL_NAND_SUPPORT)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
/*
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
-#define CONFIG_SYS_DA850_PLL_INIT
-#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
/* Command line configuration */
#define CONFIG_CMD_ENV
-#define CONFIG_MENU
-#define CONFIG_CMD_PXE
/* MMC */
#define CONFIG_MMC
#define CONFIG_CPU_SH7720 1
#define CONFIG_MPR2 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/* U-Boot internals */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
#define CONFIG_BOOTFILE "/boot/zImage"
#define CONFIG_LOADADDR 0x8E000000
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
#define CONFIG_MS7750SE 1
#define __LITTLE_ENDIAN__ 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Command line configuration.
*/
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
+/* MXC SPI driver support */
+#define CONFIG_MXC_SPI
+
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
* to support nand, since emmc has pin conflicts with nand
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_CMD_BOOTMENU /* ANSI terminal Boot Menu */
#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */
#ifdef ONENAND_SUPPORT
"run attachboot;" \
"echo"
-#define CONFIG_MENU
#define CONFIG_MENU_SHOW
/*
#ifndef __CONFIG_OMAP5_EVM_H
#define __CONFIG_OMAP5_EVM_H
+#include <environment/ti/dfu.h>
+
#ifndef CONFIG_SPL_BUILD
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
#endif
-#define DFU_ALT_INFO_MMC \
- "dfu_alt_info_mmc=" \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1\0"
-
-#define DFU_ALT_INFO_EMMC \
- "dfu_alt_info_emmc=" \
- "rawemmc raw 0 3751936;" \
- "boot part 1 1;" \
- "rootfs part 1 2;" \
- "MLO fat 1 1;" \
- "MLO.raw raw 0x100 0x100;" \
- "u-boot.img.raw raw 0x300 0x400;" \
- "spl-os-args.raw raw 0x80 0x80;" \
- "spl-os-image.raw raw 0x900 0x2000;" \
- "spl-os-args fat 1 1;" \
- "spl-os-image fat 1 1;" \
- "u-boot.img fat 1 1;" \
- "uEnv.txt fat 1 1\0"
-
-#define DFU_ALT_INFO_RAM \
- "dfu_alt_info_ram=" \
- "kernel ram 0x80200000 0x4000000;" \
- "fdt ram 0x80f80000 0x80000;" \
- "ramdisk ram 0x81000000 0x4000000\0"
-
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+ DV_DDR_PHY_EXT_STRBEN | \
+ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (4 << DV_DDR_SDCR_CL_SHIFT) | \
+ (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
+ (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
+ (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
+ (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
+ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
+ (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
+ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
+#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+
/*
* Serial Driver info
*/
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_BUSWIDTH_16_BIT
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_CLE_MASK 0x10
-#define CONFIG_SYS_ALE_MASK 0x8
+#define CONFIG_SYS_NAND_MASK_CLE 0x10
+#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200 /*0x60000*/
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
+ CONFIG_SYS_NAND_U_BOOT_SIZE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
#endif
#ifdef CONFIG_SYS_USE_NOR
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
-#define CONFIG_BOOTCOMMAND "if mmc rescan; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan; then " \
+ "run mmcboot; " \
+ "else " \
+ "run spiboot; " \
+ "fi"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdtaddr=0xc0600000\0" \
+ "fdtfile=da850-lcdk.dtb\0" \
+ "fdtboot=bootm 0xc0700000 - ${fdtaddr};\0" \
+ "mmcboot=" \
+ "if fatload mmc 0 0xc0600000 boot.scr; then " \
+ "source 0xc0600000; " \
+ "else " \
+ "fatload mmc 0 0xc0700000 uImage; " \
+ "fatload mmc 0 ${fdtaddr} ${fdtfile}; " \
+ "run fdtboot; " \
+ "fi;\0" \
+ "spiboot=" \
+ "sf probe 0; " \
+ "sf read 0xc0700000 0x80000 0x220000; " \
+ "bootm 0xc0700000;\0"
/*
* U-Boot commands
#ifndef __R0P7734_H
#define __R0P7734_H
-#undef DEBUG
#define CONFIG_CPU_SH7734 1
#define CONFIG_R0P7734 1
#define CONFIG_400MHZ_MODE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC3,115200"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Ether */
#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
#define CONFIG_CPU_SH7751 1
#define CONFIG_CPU_SH_TYPE_R 1
#define CONFIG_R2DPLUS 1
#define __LITTLE_ENDIAN__ 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Command line configuration.
*/
#define CONFIG_ENV_OVERWRITE 1
/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
-#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
+#define CONFIG_SYS_SDRAM_BASE 0x8C000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000
-#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
+#define CONFIG_SYS_TEXT_BASE 0x8FE00000
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SH4_PCI
#define CONFIG_SH7751_PCI
#define CONFIG_PCI_SCAN_SHOW 1
-#define __io
#define __mem_pci
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
-#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
-#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
+#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
#endif /* __CONFIG_H */
#ifndef __R7780RP_H
#define __R7780RP_H
-#undef DEBUG
#define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1
#define CONFIG_SYS_R7780MP_OLD_FLASH 1
#define __LITTLE_ENDIAN__ 1
+#define CONFIG_DISPLAY_BOARDINFO
+
/*
* Command line configuration.
*/
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_PCI_SCAN_SHOW 1
-#define __io
#define __mem_pci
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
#ifndef __RSK7203_H
#define __RSK7203_H
-#undef DEBUG
#define CONFIG_CPU_SH7203 1
#define CONFIG_RSK7203 1
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#ifndef __RSK7264_H
#define __RSK7264_H
-#undef DEBUG
#define CONFIG_CPU_SH7264 1
#define CONFIG_RSK7264 1
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC3,115200"
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#ifndef __RSK7269_H
#define __RSK7269_H
-#undef DEBUG
#define CONFIG_CPU_SH7269 1
#define CONFIG_RSK7269 1
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC7,115200"
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
/* #define CONFIG_CMD_EXT2 EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_DOS_PARTITION
#if 0
/* Ethernet config */
#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
-#define CONFIG_CMD_DHCP
-
#define CONFIG_LOADADDR 0xC307FFC0
#define CONFIG_BOOTARGS "console=ttyLF0 root=/dev/ram rw"
#if 0
/* Configure PXE */
-#define CONFIG_CMD_PXE
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
#endif
#ifndef __SH7752EVB_H
#define __SH7752EVB_H
-#undef DEBUG
#define CONFIG_CPU_SH7752 1
#define CONFIG_SH7752EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
-#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds"
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#ifndef __SH7753EVB_H
#define __SH7753EVB_H
-#undef DEBUG
#define CONFIG_CPU_SH7753 1
#define CONFIG_SH7753EVB 1
#define CONFIG_SYS_TEXT_BASE 0x5ff80000
-#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7753evb/u-boot.lds"
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#ifndef __SH7757LCR_H
#define __SH7757LCR_H
-#undef DEBUG
#define CONFIG_CPU_SH7757 1
#define CONFIG_SH7757LCR 1
#define CONFIG_SH7757LCR_DDR_ECC 1
#define CONFIG_SYS_TEXT_BASE 0x8ef80000
-#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SCIF */
#ifndef __SH7785LCR_H
#define __SH7785LCR_H
-#undef DEBUG
#define CONFIG_CPU_SH7785 1
#define CONFIG_SH7785LCR 1
"bootdevice=0:1\0" \
"usbload=usb reset;usbboot;usb stop;bootm\0"
+#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
* you should set undef.
*/
#undef CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_DISPLAY_BOARDINFO
/* system */
#define SHMIN_SDRAM_BASE (0x8C000000)
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Configuation settings for the SAMSUNG SMDK2410 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */
-#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
-#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
-
-#define CONFIG_SYS_TEXT_BASE 0x0
-
-#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-
-/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Hardware drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x19000300
-#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
-
-/************************************************************
- * USB support (currently only works with D-cache off)
- ************************************************************/
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_OHCI_S3C24XX
-#define CONFIG_DOS_PARTITION
-
-/************************************************************
- * RTC
- ************************************************************/
-#define CONFIG_RTC_S3C24X0
-
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_REGINFO
-
-#define CONFIG_CMDLINE_EDITING
-
-/* autoboot */
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 10.0.0.110
-#define CONFIG_SERVERIP 10.0.0.1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x30800000
-
-/* support additional compression methods */
-#define CONFIG_BZIP2
-#define CONFIG_LZO
-#define CONFIG_LZMA
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT (19)
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SIZE 0x10000
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Size of malloc() pool
- * BZIP2 / LZO / LZMA need a lot of RAM
- */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-/*
- * NAND configuration
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_S3C2410
-#define CONFIG_SYS_S3C2410_NAND_HWECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x4E000000
-#endif
-
-/*
- * File system
- */
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_YAFFS2
-#define CONFIG_RBTREE
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#endif /* __CONFIG_H */
#define CONFIG_BAUDRATE 115200
-/* Command line configuration */
-#define CONFIG_MENU
-
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
"ramdisk_addr_r=0x88080000\0" \
"scriptaddr=0x80000000\0" \
"pxefile_addr_r=0x80100000\0" \
- "bootm_size=0x10000000\0"
+ "bootm_size=0x10000000\0" \
+ "boot_fdt=try\0"
#define DEFAULT_MMC_TI_ARGS \
"mmcdev=0\0" \
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
+ "loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"envboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"fi;" \
"fi;" \
"fi;\0" \
+ "mmcloados=run args_mmc; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "mmcboot=mmc dev ${mmcdev}; " \
+ "setenv devnum ${mmcdev}; " \
+ "setenv devtype mmc; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadimage; then " \
+ "if test ${boot_fit} -eq 1; then " \
+ "run loadfit; " \
+ "else " \
+ "run mmcloados;" \
+ "fi;" \
+ "fi;" \
+ "fi;\0" \
+
+#define DEFAULT_FIT_TI_ARGS \
+ "boot_fit=0\0" \
+ "fit_loadaddr=0x88000000\0" \
+ "fit_bootfile=fitImage.itb\0" \
+ "update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}\0" \
+ "args_fit=setenv bootargs console=${console} \0" \
+ "loadfit=run args_fit; bootm ${loadaddr}:kernel@1 " \
+ "${loadaddr}:ramdisk@1 ${loadaddr}:${fdtfile};\0" \
/*
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
#define CONFIG_SYS_MAXARGS 64
/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_CBSIZE 1024
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run envboot; " \
"run distro_bootcmd"
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"console=ttyO2,115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"vram=16M\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run args_mmc; " \
- "if run loadimage; then " \
- "run loadfdt; " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;\0" \
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
"run args_mmc; " \
"bootm ${loadaddr}\0" \
"setenv fdtfile omap4-duovero-parlor.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
BOOTENV
/*
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"console=" CONSOLEDEV ",115200n8\0" \
"fdtfile=undefined\0" \
"bootpart=0:2\0" \
"partitions=" PARTS_DEFAULT "\0" \
"optargs=\0" \
"dofastboot=0\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadimage; then " \
- "run loadfdt; " \
- "echo Booting from mmc${mmcdev} ...; " \
- "run args_mmc; " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi;" \
- "fi;\0" \
"findfdt="\
"if test $board_name = omap5_uevm; then " \
"setenv fdtfile omap5-uevm.dtb; fi; " \
"setenv fdtfile dra72-evm-revc.dtb; fi;" \
"if test $board_name = dra72x; then " \
"setenv fdtfile dra72-evm.dtb; fi;" \
+ "if test $board_name = dra71x; then " \
+ "setenv fdtfile dra71-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = beagle_x15_revb1; then " \
+ "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
"if test $board_name = am572x_idk; then " \
"setenv fdtfile am572x-idk.dtb; fi;" \
"if test $board_name = am57xx_evm; then " \
"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = am57xx_evm_reva3; then " \
+ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+ "if test $board_name = am571x_idk; then " \
+ "setenv fdtfile am571x-idk.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
DFUARGS \
NETARGS \
"echo Booting into fastboot ...; " \
"fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
"fi;" \
+ "if test ${boot_fit} -eq 1; then " \
+ "run update_to_fit;" \
+ "fi;" \
"run findfdt; " \
"run envboot; " \
"run mmcboot;" \
--- /dev/null
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Derived from MX28EVK code by
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ * Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the TS4600 Board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIGS_TS4600_H__
+#define __CONFIGS_TS4600_H__
+
+/* System configurations */
+#define CONFIG_MX28 /* i.MX28 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
+#define CONFIG_DOS_PARTITION
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+/* Boot Linux */
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_addr=0x41000000\0" \
+ "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \
+ "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \
+ "bootscript=echo Running bootscript from mmc...; " \
+ "setenv mmcdev 0; " \
+ "setenv mmcpart 2; " \
+ "run loadbootscript && source ${loadaddr}; \0" \
+ "sdboot=echo Booting from SD card ...; " \
+ "setenv mmcdev 0; " \
+ "setenv mmcpart 2; " \
+ "setenv root /dev/mmcblk0p3; " \
+ "run loadkernel && run loadfdt; \0" \
+ "startbootsequence=run bootscript || run sdboot \0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc rescan; " \
+ "run startbootsequence; " \
+ "setenv cmdline_append console=ttyAMA0,115200; " \
+ "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \
+ "bootz ${loadaddr} - ${fdt_addr}; "
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_TS4600_H__ */
--- /dev/null
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright Jasbir Matharu
+ * Copyright 2015 UDOO Team
+ *
+ * Configuration settings for the UDOO NEO board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_UART
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+/* Command definition */
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/
+
+/* Linux only */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc0,115200\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=undefined\0" \
+ "fdt_addr=0x83000000\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcrootfstype=ext4\0" \
+ "mmcautodetect=no\0" \
+ "findfdt="\
+ "if test $board_name = BASIC; then " \
+ "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
+ "if test $board_name = BASICKS; then " \
+ "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
+ "if test $board_name = FULL; then " \
+ "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \
+ "if test $board_name = EXTENDED; then " \
+ "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \
+ "if test $fdt_file = UNDEFINED; then " \
+ "echo WARNING: Could not determine dtb to use; fi; \0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+ "ramdisk_addr_r=0x83000000\0" \
+ "ramdiskaddr=0x83000000\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#endif /* __CONFIG_H */
#define CONFIG_PL011_CLOCK 24000000
#endif
-/* Command line configuration */
-#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#define CONFIG_DOS_PARTITION
--- /dev/null
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Configuration settings for the Samtec VIN|ING 2000 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6)
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_IS_IN_MMC
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */
+/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
+#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
+#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#endif
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
#endif
#define CONFIG_AUTO_COMPLETE
-/* PXE */
-#define CONFIG_CMD_PXE
-#define CONFIG_MENU
-
#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_XHCI_ZYNQMP
#ifdef CONFIG_USB_EHCI_ZYNQ
# define CONFIG_EHCI_IS_TDI
-# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
*/
int cros_ec_calc_checksum(const uint8_t *data, int size);
-/**
- * Decode a flash region parameter
- *
- * @param argc Number of params remaining
- * @param argv List of remaining parameters
- * @return flash region (EC_FLASH_REGION_...) or -1 on error
- */
-int cros_ec_decode_region(int argc, char * const argv[]);
-
int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t offset,
uint32_t size);
*/
fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
+/**
+ * dev_get_addr_size_index() - Get the indexed reg property of a device
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ * @size: Pointer to size varible - this function returns the size
+ * specified in the 'reg' property here
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_size_index(struct udevice *dev, int index,
+ fdt_size_t *size);
+
/**
* dev_get_addr_name() - Get the reg property of a device, indexed by name
*
*/
struct udevice *dm_root(void);
+struct global_data;
+/**
+ * dm_fixup_for_gd_move() - Handle global_data moving to a new place
+ *
+ * The uclass list is part of global_data. Due to the way lists work, moving
+ * the list will cause it to become invalid. This function fixes that up so
+ * that the uclass list will work correctly.
+ */
+void dm_fixup_for_gd_move(struct global_data *new_gd);
+
/**
* dm_scan_platdata() - Scan all platform data and bind drivers
*
--- /dev/null
+/*
+ * This header provides constants for DRA7 ATL (Audio Tracking Logic)
+ *
+ * The constants defined in this header are used in dts files
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
+#define _DT_BINDINGS_CLK_DRA7_ATL_H
+
+#define DRA7_ATL_WS_MCASP1_FSR 0
+#define DRA7_ATL_WS_MCASP1_FSX 1
+#define DRA7_ATL_WS_MCASP2_FSR 2
+#define DRA7_ATL_WS_MCASP2_FSX 3
+#define DRA7_ATL_WS_MCASP3_FSX 4
+#define DRA7_ATL_WS_MCASP4_FSX 5
+#define DRA7_ATL_WS_MCASP5_FSX 6
+#define DRA7_ATL_WS_MCASP6_FSX 7
+#define DRA7_ATL_WS_MCASP7_FSX 8
+#define DRA7_ATL_WS_MCASP8_FSX 9
+#define DRA7_ATL_WS_MCASP8_AHCLKX 10
+#define DRA7_ATL_WS_XREF_CLK3 11
+#define DRA7_ATL_WS_XREF_CLK0 12
+#define DRA7_ATL_WS_XREF_CLK1 13
+#define DRA7_ATL_WS_XREF_CLK2 14
+#define DRA7_ATL_WS_OSC1_X1 15
+
+#endif
#define MUX_MODE14 0xe
#define MUX_MODE15 0xf
+/* Certain pins need virtual mode, but note: they may glitch */
+#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
+#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
+#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
+#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
+#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
+#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
+#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
+#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
+#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
+#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
+#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
+#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
+#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
+#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
+#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
+#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
+
+#define MODE_SELECT (1 << 8)
+
#define PULL_ENA (0 << 16)
#define PULL_DIS (1 << 16)
#define PULL_UP (1 << 17)
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
+
#endif
--- /dev/null
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for DFU on TI boards.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+ "dfu_alt_info_emmc=" \
+ "rawemmc raw 0 3751936;" \
+ "boot part 1 1;" \
+ "rootfs part 1 2;" \
+ "MLO fat 1 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x1000;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 1 1;" \
+ "spl-os-image fat 1 1;" \
+ "u-boot.img fat 1 1;" \
+ "uEnv.txt fat 1 1\0"
+
+#ifdef CONFIG_NAND
+#define DFU_ALT_INFO_NAND \
+ "dfu_alt_info_nand=" \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0x4000000;" \
+ "fdt ram 0x80f80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFU_ALT_INFO_QSPI_XIP \
+ "dfu_alt_info_qspi=" \
+ "u-boot.bin raw 0x0 0x080000;" \
+ "u-boot.backup raw 0x080000 0x080000;" \
+ "u-boot-spl-os raw 0x100000 0x010000;" \
+ "u-boot-env raw 0x110000 0x010000;" \
+ "u-boot-env.backup raw 0x120000 0x010000;" \
+ "kernel raw 0x130000 0x800000\0"
+
+#define DFU_ALT_INFO_QSPI \
+ "dfu_alt_info_qspi=" \
+ "MLO raw 0x0 0x040000;" \
+ "u-boot.img raw 0x040000 0x0100000;" \
+ "u-boot-spl-os raw 0x140000 0x080000;" \
+ "u-boot-env raw 0x1C0000 0x010000;" \
+ "u-boot-env.backup raw 0x1D0000 0x010000;" \
+ "kernel raw 0x1E0000 0x800000\0"
* property will be left untouched.
* @return 0 if ok, or -1 or -FDT_ERR_... on error
*/
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+#else
+static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[],
+ int banks)
+{
+ return 0;
+}
+#endif
void fdt_fixup_ethernet(void *fdt);
int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */
IH_TYPE_FPGA, /* FPGA Image */
IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */
+ IH_TYPE_TEE, /* Trusted Execution Environment OS Image */
IH_TYPE_COUNT, /* Number of image types */
};
void board_fit_image_post_process(void **p_image, size_t *p_size);
#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
+/**
+ * Mapping of image types to function handlers to be invoked on the associated
+ * loaded images
+ *
+ * @type: Type of image, I.E. IH_TYPE_*
+ * @handler: Function to call on loaded image
+ */
+struct fit_loadable_tbl {
+ int type;
+ /**
+ * handler() - Process a loaded image
+ *
+ * @data: Pointer to start of loaded image data
+ * @size: Size of loaded image data
+ */
+ void (*handler)(ulong data, size_t size);
+};
+
+/*
+ * Define a FIT loadable image type handler
+ *
+ * _type is a valid uimage_type ID as defined in the "Image Type" enum above
+ * _handler is the handler function to call after this image type is loaded
+ */
+#define U_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \
+ ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) = { \
+ .type = _type, \
+ .handler = _handler, \
+ }
+
#endif /* __IMAGE_H__ */
#ifndef _ASM_ARCH_XHCI_OMAP_H_
#define _ASM_ARCH_XHCI_OMAP_H_
-#ifdef CONFIG_DRA7XX
+#ifdef CONFIG_TARGET_DRA7XX_EVM
#define OMAP_XHCI_BASE 0x488d0000
#define OMAP_OCP1_SCP_BASE 0x4A081000
#define OMAP_OTG_WRAPPER_BASE 0x488c0000
-#elif defined CONFIG_AM57XX
+#elif defined CONFIG_TARGET_AM57XX_EVM
#define OMAP_XHCI_BASE 0x48890000
#define OMAP_OCP1_SCP_BASE 0x4A084c00
#define OMAP_OTG_WRAPPER_BASE 0x48880000
#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
+#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
#define EXT_CSD_WR_REL_PARAM 166 /* R */
#define EXT_CSD_WR_REL_SET 167 /* R/W */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
+#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
/*
* EXT_CSD field definitions
* @return 0 if there is no MMC device, else the number of devices
*/
int get_mmc_num(void);
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
enum mmc_hwpart_conf_mode mode);
unsigned short cnt, unsigned char *key);
int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
unsigned short cnt, unsigned char *key);
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+int mmc_set_bkops_enable(struct mmc *mmc);
+#endif
+
/**
* Start device initialization and return immediately; it does not block on
* polling OCR (operation condition register) status. Then you should call
#define LDO1_CTRL 0x50
#define LDO1_VOLTAGE 0x51
+/* LDO1 control/voltage for LP873x */
+#define LP873X_LDO1_ADDR 0x60
+#define LP873X_LDO1_CTRL 0x9
+#define LP873X_LDO1_VOLTAGE 0xa
+#define LP873X_LDO_VOLT_3V0 0x19
+#define LP873X_LDO_VOLT_1V8 0xa
+#define LP873X_LDO_CTRL_EN (0x1 << 0)
+#define LP873X_LDO_CTRL_EN_PINCTRL (0x1 << 1)
+#define LP873X_LDO_CTRL_RDIS_EN (0x1 << 2)
+
/* LDO2 control/voltage */
#define LDO2_CTRL 0x52
#define LDO2_VOLTAGE 0x53
}
void palmas_init_settings(void);
-int palmas_mmc1_poweron_ldo(void);
+int palmas_mmc1_poweron_ldo(uint voltage);
+int lp873x_mmc1_poweron_ldo(uint voltage);
int twl603x_mmc1_set_ldo9(u8 vsel);
int twl603x_audio_power(u8 on);
int twl603x_enable_bb_charge(u8 bb_fields);
* functions residing inside cmd_scsi.c
*/
void scsi_init(void);
-void scsi_scan(int mode);
-
-/** @return the number of scsi disks */
-int scsi_get_disk_count(void);
+int scsi_scan(int mode);
#define SCSI_IDENTIFY 0xC0 /* not used */
*/
int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr);
+int spl_mmc_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev);
+
#endif
--- /dev/null
+/*
+ * OP-TEE related definitions
+ *
+ * (C) Copyright 2016 Linaro Limited
+ * Andrew F. Davis <andrew.davis@linaro.org>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef _OPTEE_H
+#define _OPTEE_H
+
+#define OPTEE_MAGIC 0x4554504f
+#define OPTEE_VERSION 1
+#define OPTEE_ARCH_ARM32 0
+#define OPTEE_ARCH_ARM64 1
+
+struct optee_header {
+ uint32_t magic;
+ uint8_t version;
+ uint8_t arch;
+ uint16_t flags;
+ uint32_t init_size;
+ uint32_t init_load_addr_hi;
+ uint32_t init_load_addr_lo;
+ uint32_t init_mem_usage;
+ uint32_t paged_size;
+};
+
+#endif /* _OPTEE_H */
hi = (temp64>>32) & 0xffffffff;
lo = temp64 & 0xffffffff;
- post_log("Memory (date line) error at %08x, "
+ post_log("Memory (data line) error at %08x, "
"wrote %08x%08x, read %08x%08x !\n",
pmem, pathi, patlo, hi, lo);
ret = -1;
CONFIG_AM335X_USB1_MODE
CONFIG_AM33XX
CONFIG_AM437X_USB2PHY2_HOST
-CONFIG_AM57XX
CONFIG_AMBAPP_IOAREA
CONFIG_AMCC_DEF_ENV
CONFIG_AMCC_DEF_ENV_NOR_UPD
CONFIG_ARCH_RPC
CONFIG_ARCH_S3C2440
CONFIG_ARCH_SHARK
-CONFIG_ARCH_SMDK2410
CONFIG_ARCH_TEGRA
CONFIG_ARCH_USE_BUILTIN_BSWAP
CONFIG_ARCH_VERSATILE_PB
CONFIG_CMD_BMODE
CONFIG_CMD_BMP
CONFIG_CMD_BOOTLDR
-CONFIG_CMD_BOOTMENU
CONFIG_CMD_BSP
CONFIG_CMD_CBFS
CONFIG_CMD_CHIP_CONFIG
CONFIG_MEM_INIT_VALUE
CONFIG_MEM_REMAP
CONFIG_MEM_SIZE
-CONFIG_MENU
CONFIG_MENUKEY
CONFIG_MENUPROMPT
CONFIG_MENU_SHOW
CONFIG_S3C2410_NAND_HWECC
CONFIG_S3C2440
CONFIG_S3C24X0
-CONFIG_S3C24X0_SERIAL
CONFIG_S3C24XX_CUSTOM_NAND_TIMING
CONFIG_S3C24XX_TACLS
CONFIG_S3C24XX_TWRPH0
CONFIG_SMC_GCTL_VAL
CONFIG_SMC_USE_32_BIT
CONFIG_SMC_USE_IOFUNCS
-CONFIG_SMDK2410
CONFIG_SMDK5420
CONFIG_SMDKC100
CONFIG_SMDKV310
CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_AHB_BASE
-CONFIG_SYS_ALE_MASK
CONFIG_SYS_ALLOC_DPRAM
CONFIG_SYS_ALT_BOOT
CONFIG_SYS_ALT_FLASH
CONFIG_SYS_CF_SIZE
CONFIG_SYS_CH7301_I2C
CONFIG_SYS_CKEN
-CONFIG_SYS_CLE_MASK
CONFIG_SYS_CLK
CONFIG_SYS_CLKDIV_CPU
CONFIG_SYS_CLKDIV_HSB
CONFIG_SYS_DA850_DDR2_SDRCR
CONFIG_SYS_DA850_DDR2_SDTIMR
CONFIG_SYS_DA850_DDR2_SDTIMR2
-CONFIG_SYS_DA850_DDR_INIT
CONFIG_SYS_DA850_PLL0_PLLDIV1
CONFIG_SYS_DA850_PLL0_PLLDIV2
CONFIG_SYS_DA850_PLL0_PLLDIV3
CONFIG_SYS_DA850_PLL1_PLLDIV3
CONFIG_SYS_DA850_PLL1_PLLM
CONFIG_SYS_DA850_PLL1_POSTDIV
-CONFIG_SYS_DA850_PLL_INIT
CONFIG_SYS_DA850_SYSCFG_SUSPSRC
CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0
CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
CONFIG_SYS_NAND_BOOT
CONFIG_SYS_NAND_BR_PRELIM
CONFIG_SYS_NAND_BUSWIDTH_16
-CONFIG_SYS_NAND_BUSWIDTH_16_BIT
CONFIG_SYS_NAND_CE
CONFIG_SYS_NAND_CLE
CONFIG_SYS_NAND_CS
CONFIG_V38B
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
-CONFIG_VCMA9
CONFIG_VCO_HZ
CONFIG_VCO_MULT
CONFIG_VCT_NOR
SOURCE_DATE_EPOCH=0 ./tools/buildman/buildman -I -P tegra
+Checking configuration
+======================
+
+A common requirement when converting CONFIG options to Kconfig is to check
+that the effective configuration has not changed due to the conversion.
+Buildman supports this with the -K option, used after a build. This shows
+differences in effective configuration between one commit and the next.
+
+For example:
+
+ $ buildman -b kc4 -sK
+ ...
+ 43: Convert CONFIG_SPL_USBETH_SUPPORT to Kconfig
+ arm:
+ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
+ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ am335x_evm_usbspl :
+ + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ + u-boot-spl.cfg: CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1
+ + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC_SUPPORT=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET_SUPPORT=1
+ 44: Convert CONFIG_SPL_USB_HOST_SUPPORT to Kconfig
+ ...
+
+This shows that commit 44 enabled three new options for the board
+am335x_evm_usbspl which were not enabled in commit 43. There is also a
+summary for 'arm' showing all the changes detected for that architecture.
+In this case there is only one board with changes, so 'arm' output is the
+same as 'am335x_evm_usbspl'/
+
+The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg
+files which are produced by a build. If all you want is to check the
+configuration you can in fact avoid doing a full build, using -D. This tells
+buildman to configuration U-Boot and create the .cfg files, but not actually
+build the source. This is 5-10 times faster than doing a full build.
+
+By default buildman considers the follow two configuration methods
+equivalent:
+
+ #define CONFIG_SOME_OPTION
+
+ CONFIG_SOME_OPTION=y
+
+The former would appear in a header filer and the latter in a defconfig
+file. The achieve this, buildman considers 'y' to be '1' in configuration
+variables. This avoids lots of useless output when converting a CONFIG
+option to Kconfig. To disable this behaviour, use --squash-config-y.
+
+
Other options
=============
# Translate a commit subject into a valid filename
trans_valid_chars = string.maketrans("/: ", "---")
-CONFIG_FILENAMES = [
+BASE_CONFIG_FILENAMES = [
+ 'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'
+]
+
+EXTRA_CONFIG_FILENAMES = [
'.config', '.config-spl', '.config-tpl',
'autoconf.mk', 'autoconf-spl.mk', 'autoconf-tpl.mk',
'autoconf.h', 'autoconf-spl.h','autoconf-tpl.h',
- 'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg'
]
class Config:
"""Holds information about configuration settings for a board."""
- def __init__(self, target):
+ def __init__(self, config_filename, target):
self.target = target
self.config = {}
- for fname in CONFIG_FILENAMES:
+ for fname in config_filename:
self.config[fname] = {}
def Add(self, fname, key, value):
def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs,
gnu_make='make', checkout=True, show_unknown=True, step=1,
no_subdirs=False, full_path=False, verbose_build=False,
- incremental=False, per_board_out_dir=False):
+ incremental=False, per_board_out_dir=False,
+ config_only=False, squash_config_y=False):
"""Create a new Builder object
Args:
mrproper when configuring
per_board_out_dir: Build in a separate persistent directory per
board rather than a thread-specific directory
+ config_only: Only configure each build, don't build it
+ squash_config_y: Convert CONFIG options with the value 'y' to '1'
"""
self.toolchains = toolchains
self.base_dir = base_dir
self.no_subdirs = no_subdirs
self.full_path = full_path
self.verbose_build = verbose_build
+ self.config_only = config_only
+ self.squash_config_y = squash_config_y
+ self.config_filenames = BASE_CONFIG_FILENAMES
+ if not self.squash_config_y:
+ self.config_filenames += EXTRA_CONFIG_FILENAMES
self.col = terminal.Color()
name += target
Print(line + name, newline=False)
- length = 14 + len(name)
+ length = 16 + len(name)
self.ClearLine(length)
def _GetOutputDir(self, commit_upto):
key, value = values
else:
key = values[0]
- value = ''
+ value = '1' if self.squash_config_y else ''
if not key.startswith('CONFIG_'):
continue
elif not line or line[0] in ['#', '*', '/']:
continue
else:
key, value = line.split('=', 1)
+ if self.squash_config_y and value == 'y':
+ value = '1'
config[key] = value
return config
if read_config:
output_dir = self.GetBuildDir(commit_upto, target)
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
fname = os.path.join(output_dir, name)
config[name] = self._ProcessConfig(fname)
line, board)
last_was_warning = is_warning
last_func = None
- tconfig = Config(board.target)
- for fname in CONFIG_FILENAMES:
+ tconfig = Config(self.config_filenames, board.target)
+ for fname in self.config_filenames:
if outcome.config:
for key, value in outcome.config[fname].iteritems():
tconfig.Add(fname, key, value)
arch_config_plus[arch] = {}
arch_config_minus[arch] = {}
arch_config_change[arch] = {}
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
arch_config_plus[arch][name] = {}
arch_config_minus[arch][name] = {}
arch_config_change[arch][name] = {}
tbase = self._base_config[target]
tconfig = config[target]
lines = []
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
if not tconfig.config[name]:
continue
config_plus = {}
all_plus = {}
all_minus = {}
all_change = {}
- for name in CONFIG_FILENAMES:
+ for name in self.config_filenames:
all_plus.update(arch_config_plus[arch][name])
all_minus.update(arch_config_minus[arch][name])
all_change.update(arch_config_change[arch][name])
return self.builder.do_make(commit, brd, stage, cwd, *args,
**kwargs)
- def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build,
- force_build_failures):
+ def RunCommit(self, commit_upto, brd, work_dir, do_config, config_only,
+ force_build, force_build_failures):
"""Build a particular commit.
If the build is already done, and we are not forcing a build, we skip
brd: Board object to build
work_dir: Directory to which the source will be checked out
do_config: True to run a make <board>_defconfig on the source
+ config_only: Only configure the source, do not build it
force_build: Force a build even if one was previously done
force_build_failures: Force a bulid if the previous result showed
failure
config_out += result.combined
do_config = False # No need to configure next time
if result.return_code == 0:
+ if config_only:
+ args.append('cfg')
result = self.Make(commit, brd, 'build', cwd, *args,
env=env)
result.stderr = result.stderr.replace(src_dir + '/', '')
force_build = False
for commit_upto in range(0, len(job.commits), job.step):
result, request_config = self.RunCommit(commit_upto, brd,
- work_dir, do_config,
+ work_dir, do_config, self.builder.config_only,
force_build or self.builder.force_build,
self.builder.force_build_failures)
failed = result.return_code or result.stderr
# with a reconfig.
if self.builder.force_config_on_failure:
result, request_config = self.RunCommit(commit_upto,
- brd, work_dir, True, True, False)
+ brd, work_dir, True, False, True, False)
did_config = True
if not self.builder.force_reconfig:
do_config = request_config
else:
# Just build the currently checked-out build
result, request_config = self.RunCommit(None, brd, work_dir, True,
- True, self.builder.force_build_failures)
+ self.builder.config_only, True,
+ self.builder.force_build_failures)
result.commit_upto = 0
self._WriteResult(result, job.keep_outputs)
self.builder.out_queue.put(result)
parser.add_option('-d', '--detail', dest='show_detail',
action='store_true', default=False,
help='Show detailed information for each board in summary')
+ parser.add_option('-D', '--config-only', action='store_true', default=False,
+ help="Don't build, just configure each commit")
parser.add_option('-e', '--show_errors', action='store_true',
default=False, help='Show errors and warnings')
parser.add_option('-f', '--force-build', dest='force_build',
default=False, help='Keep all build output files (e.g. binaries)')
parser.add_option('-K', '--show-config', action='store_true',
default=False, help='Show configuration changes in summary (both board config files and Kconfig)')
+ parser.add_option('--preserve-config-y', action='store_true',
+ default=False, help="Don't convert y to 1 in configs")
parser.add_option('-l', '--list-error-boards', action='store_true',
default=False, help='Show a list of boards next to each error/warning')
parser.add_option('--list-tool-chains', action='store_true', default=False,
no_subdirs=options.no_subdirs, full_path=options.full_path,
verbose_build=options.verbose_build,
incremental=options.incremental,
- per_board_out_dir=options.per_board_out_dir,)
+ per_board_out_dir=options.per_board_out_dir,
+ config_only=options.config_only,
+ squash_config_y=not options.preserve_config_y)
builder.force_config_on_failure = not options.quick
if make_func:
builder.do_make = make_func
d = (struct dcd_v2_cmd *)(((char *)d) + len);
len = (char *)d - (char *)&dcd_v2->header;
-
dcd_v2->header.tag = DCD_HEADER_TAG;
dcd_v2->header.length = cpu_to_be16(len);
dcd_v2->header.version = DCD_VERSION;
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
(imximage_csf_size != UNDEFINED)) {
+ uint16_t dcdlen;
+ int offs;
+
+ dcdlen = hdr_v2->data.dcd_table.header.length;
+ offs = (char *)&hdr_v2->data.dcd_table
+ - (char *)hdr_v2;
+
printf("HAB Blocks: %08x %08x %08x\n",
(uint32_t)fhdr_v2->self, 0,
hdr_v2->boot_data.size - imximage_ivt_offset -
imximage_csf_size);
+ printf("DCD Blocks: 00910000 %08x %08x\n",
+ offs, be16_to_cpu(dcdlen));
}
} else {
imx_header_v2_t *next_hdr_v2;
IMAGE_CFG_BINARY,
IMAGE_CFG_PAYLOAD,
IMAGE_CFG_DATA,
+ IMAGE_CFG_BAUDRATE,
+ IMAGE_CFG_DEBUG,
} type;
union {
unsigned int version;
unsigned int nandeccmode;
unsigned int nandpagesz;
struct ext_hdr_v0_reg regdata;
+ unsigned int baudrate;
+ unsigned int debug;
};
};
return csum;
}
+static uint8_t baudrate_to_option(unsigned int baudrate)
+{
+ switch (baudrate) {
+ case 2400:
+ return MAIN_HDR_V1_OPT_BAUD_2400;
+ case 4800:
+ return MAIN_HDR_V1_OPT_BAUD_4800;
+ case 9600:
+ return MAIN_HDR_V1_OPT_BAUD_9600;
+ case 19200:
+ return MAIN_HDR_V1_OPT_BAUD_19200;
+ case 38400:
+ return MAIN_HDR_V1_OPT_BAUD_38400;
+ case 57600:
+ return MAIN_HDR_V1_OPT_BAUD_57600;
+ case 115200:
+ return MAIN_HDR_V1_OPT_BAUD_115200;
+ default:
+ return MAIN_HDR_V1_OPT_BAUD_DEFAULT;
+ }
+}
+
static void *image_create_v0(size_t *imagesz, struct image_tool_params *params,
int payloadsz)
{
e = image_find_option(IMAGE_CFG_NAND_BADBLK_LOCATION);
if (e)
main_hdr->nandbadblklocation = e->nandbadblklocation;
+ e = image_find_option(IMAGE_CFG_BAUDRATE);
+ if (e)
+ main_hdr->options = baudrate_to_option(e->baudrate);
+ e = image_find_option(IMAGE_CFG_DEBUG);
+ if (e)
+ main_hdr->flags = e->debug ? 0x1 : 0;
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
el->type = IMAGE_CFG_DATA;
el->regdata.raddr = strtoul(value1, NULL, 16);
el->regdata.rdata = strtoul(value2, NULL, 16);
+ } else if (!strcmp(keyword, "BAUDRATE")) {
+ char *value = strtok_r(NULL, deliminiters, &saveptr);
+ el->type = IMAGE_CFG_BAUDRATE;
+ el->baudrate = strtoul(value, NULL, 10);
+ } else if (!strcmp(keyword, "DEBUG")) {
+ char *value = strtok_r(NULL, deliminiters, &saveptr);
+ el->type = IMAGE_CFG_DEBUG;
+ el->debug = strtoul(value, NULL, 10);
} else {
fprintf(stderr, "Ignoring unknown line '%s'\n", line);
}
/* Structure of the main header, version 1 (Armada 370, Armada XP) */
struct main_hdr_v1 {
uint8_t blockid; /* 0 */
- uint8_t reserved1; /* 1 */
+ uint8_t flags; /* 1 */
uint16_t reserved2; /* 2-3 */
uint32_t blocksize; /* 4-7 */
uint8_t version; /* 8 */
uint32_t srcaddr; /* C-F */
uint32_t destaddr; /* 10-13 */
uint32_t execaddr; /* 14-17 */
- uint8_t reserved3; /* 18 */
+ uint8_t options; /* 18 */
uint8_t nandblocksize; /* 19 */
uint8_t nandbadblklocation; /* 1A */
uint8_t reserved4; /* 1B */
uint8_t checksum; /* 1F */
};
+/*
+ * Main header options
+ */
+#define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
+#define MAIN_HDR_V1_OPT_BAUD_2400 0x1
+#define MAIN_HDR_V1_OPT_BAUD_4800 0x2
+#define MAIN_HDR_V1_OPT_BAUD_9600 0x3
+#define MAIN_HDR_V1_OPT_BAUD_19200 0x4
+#define MAIN_HDR_V1_OPT_BAUD_38400 0x5
+#define MAIN_HDR_V1_OPT_BAUD_57600 0x6
+#define MAIN_HDR_V1_OPT_BAUD_115200 0x7
+
/*
* Header for the optional headers, version 1 (Armada 370, Armada XP)
*/
projects / u-boot / commitdiff