]> git.sur5r.net Git - u-boot/commitdiff
Add support for CS2 dataflash for Atmel-SPI.
authorRemy Bohmer <linux@bohmer.net>
Wed, 28 Oct 2009 21:13:37 +0000 (22:13 +0100)
committerWolfgang Denk <wd@denx.de>
Mon, 23 Nov 2009 22:43:37 +0000 (23:43 +0100)
The only missing chipselect line support is CS2, and I need it on
CS2...

Signed-off-by: Remy Bohmer <linux@bohmer.net>
drivers/spi/atmel_dataflash_spi.c

index 614965c36746995d963a184a10c57dca87fa786c..3a648e619027f7fb0399f54078f9fc6e00756e26 100644 (file)
@@ -30,7 +30,8 @@
 #include <dataflash.h>
 
 #define AT91_SPI_PCS0_DATAFLASH_CARD   0xE     /* Chip Select 0: NPCS0%1110 */
-#define AT91_SPI_PCS1_DATAFLASH_CARD   0xD     /* Chip Select 0: NPCS0%1101 */
+#define AT91_SPI_PCS1_DATAFLASH_CARD   0xD     /* Chip Select 1: NPCS1%1101 */
+#define AT91_SPI_PCS2_DATAFLASH_CARD   0xB     /* Chip Select 2: NPCS2%1011 */
 #define AT91_SPI_PCS3_DATAFLASH_CARD   0x7     /* Chip Select 3: NPCS3%0111 */
 
 void AT91F_SpiInit(void)
@@ -57,7 +58,14 @@ void AT91F_SpiInit(void)
               ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
               AT91_BASE_SPI + AT91_SPI_CSR(1));
 #endif
-
+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
+       /* Configure CS2 */
+       writel(AT91_SPI_NCPHA |
+              (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+              (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+              ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
+              AT91_BASE_SPI + AT91_SPI_CSR(2));
+#endif
 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
        /* Configure CS3 */
        writel(AT91_SPI_NCPHA |
@@ -99,6 +107,12 @@ void AT91F_SpiEnable(int cs)
                writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
                       AT91_BASE_SPI + AT91_SPI_MR);
                break;
+       case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
+               mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+               mode &= 0xFFF0FFFF;
+               writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+                      AT91_BASE_SPI + AT91_SPI_MR);
+               break;
        case 3:
                mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
                mode &= 0xFFF0FFFF;