help
Additional size of malloc() pool before relocation.
+config FSP_USE_UPD
+ bool
+ depends on HAVE_FSP
+ default y
+ help
+ Most FSPs use UPD data region for some FSP customization. But there
+ are still some FSPs that might not even have UPD. For such FSPs,
+ override this to n in their platform Kconfig files.
+
config ENABLE_MRC_CACHE
bool "Enable MRC cache"
depends on !EFI && !SYS_COREBOOT
};
/**
- * Override the FSP's UPD.
+ * Override the FSP's configuration data.
* If the device tree does not specify an integer setting, use the default
* provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
*/
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
+ struct upd_region *fsp_upd = &config->fsp_upd;
struct memory_down_data *mem;
const void *blob = gd->fdt_blob;
int node;
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
+
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMM_TSEG
- select HAVE_INTEL_ME
select X86_RAMTEST
config SMM_TSEG_SIZE
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/sipi.h>
+#include <asm/fw_cfg.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
#include <linux/linkage.h>
DECLARE_GLOBAL_DATA_PTR;
}
}
-static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
+static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
{
struct udevice *dev;
enable_lapic();
apic_id = lapicid();
- ret = find_cpu_by_apid_id(apic_id, &dev);
+ ret = find_cpu_by_apic_id(apic_id, &dev);
if (ret) {
debug("Unknown CPU apic_id %x\n", apic_id);
goto done;
return msr_count;
}
-static int load_sipi_vector(atomic_t **ap_countp)
+static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
{
struct sipi_params_16bit *params16;
struct sipi_params *params;
params->idt_ptr = (uint32_t)x86_get_idt();
params->stack_size = CONFIG_AP_STACK_SIZE;
- size = params->stack_size * CONFIG_MAX_CPUS;
+ size = params->stack_size * num_cpus;
stack = memalign(size, 4096);
if (!stack)
return -ENOMEM;
lapic_setup();
apic_id = lapicid();
- ret = find_cpu_by_apid_id(apic_id, devp);
+ ret = find_cpu_by_apic_id(apic_id, devp);
if (ret) {
printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
return ret;
return 0;
}
+#ifdef CONFIG_QEMU
+static int qemu_cpu_fixup(void)
+{
+ int ret;
+ int cpu_num;
+ int cpu_online;
+ struct udevice *dev, *pdev;
+ struct cpu_platdata *plat;
+ char *cpu;
+
+ /* first we need to find '/cpus' */
+ for (device_find_first_child(dm_root(), &pdev);
+ pdev;
+ device_find_next_child(&pdev)) {
+ if (!strcmp(pdev->name, "cpus"))
+ break;
+ }
+ if (!pdev) {
+ printf("unable to find cpus device\n");
+ return -ENODEV;
+ }
+
+ /* calculate cpus that are already bound */
+ cpu_num = 0;
+ for (uclass_find_first_device(UCLASS_CPU, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ cpu_num++;
+ }
+
+ /* get actual cpu number */
+ cpu_online = qemu_fwcfg_online_cpus();
+ if (cpu_online < 0) {
+ printf("unable to get online cpu number: %d\n", cpu_online);
+ return cpu_online;
+ }
+
+ /* bind addtional cpus */
+ dev = NULL;
+ for (; cpu_num < cpu_online; cpu_num++) {
+ /*
+ * allocate device name here as device_bind_driver() does
+ * not copy device name, 8 bytes are enough for
+ * sizeof("cpu@") + 3 digits cpu number + '\0'
+ */
+ cpu = malloc(8);
+ if (!cpu) {
+ printf("unable to allocate device name\n");
+ return -ENOMEM;
+ }
+ sprintf(cpu, "cpu@%d", cpu_num);
+ ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev);
+ if (ret) {
+ printf("binding cpu@%d failed: %d\n", cpu_num, ret);
+ return ret;
+ }
+ plat = dev_get_parent_platdata(dev);
+ plat->cpu_id = cpu_num;
+ }
+ return 0;
+}
+#endif
+
int mp_init(struct mp_params *p)
{
int num_aps;
if (ret)
return ret;
+#ifdef CONFIG_QEMU
+ ret = qemu_cpu_fixup();
+ if (ret)
+ return ret;
+#endif
+
ret = init_bsp(&cpu);
if (ret) {
debug("Cannot init boot CPU: err=%d\n", ret);
mp_info.records = p->flight_plan;
/* Load the SIPI vector */
- ret = load_sipi_vector(&ap_count);
+ ret = load_sipi_vector(&ap_count, num_cpus);
if (ap_count == NULL)
return -1;
ifndef CONFIG_EFI_STUB
obj-y += car.o dram.o
endif
-obj-y += qemu.o
+obj-y += cpu.o fw_cfg.o qemu.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
--- /dev/null
+/*
+ * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu.h>
+#include <asm/fw_cfg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
+static int cpu_qemu_get_count(struct udevice *dev)
+{
+ return qemu_fwcfg_online_cpus();
+}
+
+static const struct cpu_ops cpu_qemu_ops = {
+ .get_desc = cpu_qemu_get_desc,
+ .get_count = cpu_qemu_get_count,
+};
+
+static const struct udevice_id cpu_qemu_ids[] = {
+ { .compatible = "cpu-qemu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_qemu_drv) = {
+ .name = "cpu_qemu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_qemu_ids,
+ .ops = &cpu_qemu_ops,
+};
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/fw_cfg.h>
+
+static bool fwcfg_present;
+static bool fwcfg_dma_present;
+
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+ uint32_t size, void *address)
+{
+ uint32_t i = 0;
+ uint8_t *data = address;
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ outw(entry, FW_CONTROL_PORT);
+ while (size--)
+ data[i++] = inb(FW_DATA_PORT);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+ uint32_t size, void *address)
+{
+ struct fw_cfg_dma_access dma;
+
+ dma.length = cpu_to_be32(size);
+ dma.address = cpu_to_be64((uintptr_t)address);
+ dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+ /*
+ * writting FW_CFG_INVALID will cause read operation to resume at
+ * last offset, otherwise read will start at offset 0
+ */
+ if (entry != FW_CFG_INVALID)
+ dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+ barrier();
+
+ debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
+ address, size, be32_to_cpu(dma.control));
+
+ outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
+
+ while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
+ __asm__ __volatile__ ("pause");
+}
+
+static bool qemu_fwcfg_present(void)
+{
+ uint32_t qemu;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+ return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
+}
+
+static bool qemu_fwcfg_dma_present(void)
+{
+ uint8_t dma_enabled;
+
+ qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+ if (dma_enabled & FW_CFG_DMA_ENABLED)
+ return true;
+
+ return false;
+}
+
+static void qemu_fwcfg_read_entry(uint16_t entry,
+ uint32_t length, void *address)
+{
+ if (fwcfg_dma_present)
+ qemu_fwcfg_read_entry_dma(entry, length, address);
+ else
+ qemu_fwcfg_read_entry_pio(entry, length, address);
+}
+
+int qemu_fwcfg_online_cpus(void)
+{
+ uint16_t nb_cpus;
+
+ if (!fwcfg_present)
+ return -ENODEV;
+
+ qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+ return le16_to_cpu(nb_cpus);
+}
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+ char *data_addr;
+ uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+ if (setup_size == 0 || kernel_size == 0) {
+ printf("warning: no kernel available\n");
+ return -1;
+ }
+
+ data_addr = load_addr;
+ qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+ le32_to_cpu(setup_size), data_addr);
+ data_addr += le32_to_cpu(setup_size);
+
+ qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+ le32_to_cpu(kernel_size), data_addr);
+ data_addr += le32_to_cpu(kernel_size);
+
+ data_addr = initrd_addr;
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+ if (initrd_size == 0) {
+ printf("warning: no initrd available\n");
+ } else {
+ qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+ le32_to_cpu(initrd_size), data_addr);
+ data_addr += le32_to_cpu(initrd_size);
+ }
+
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+ if (cmdline_size) {
+ qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+ le32_to_cpu(cmdline_size), data_addr);
+ /*
+ * if kernel cmdline only contains '\0', (e.g. no -append
+ * when invoking qemu), do not update bootargs
+ */
+ if (*data_addr != '\0') {
+ if (setenv("bootargs", data_addr) < 0)
+ printf("warning: unable to change bootargs\n");
+ }
+ }
+
+ printf("loading kernel to address %p size %x", load_addr,
+ le32_to_cpu(kernel_size));
+ if (initrd_size)
+ printf(" initrd %p size %x\n",
+ initrd_addr,
+ le32_to_cpu(initrd_size));
+ else
+ printf("\n");
+
+ return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+ int i;
+ uint32_t count;
+ struct fw_cfg_files *files;
+
+ qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+ if (!count)
+ return 0;
+
+ count = be32_to_cpu(count);
+ files = malloc(count * sizeof(struct fw_cfg_file));
+ if (!files)
+ return -ENOMEM;
+
+ files->count = count;
+ qemu_fwcfg_read_entry(FW_CFG_INVALID,
+ count * sizeof(struct fw_cfg_file),
+ files->files);
+
+ for (i = 0; i < files->count; i++)
+ printf("%-56s\n", files->files[i].name);
+ free(files);
+ return 0;
+}
+
+void qemu_fwcfg_init(void)
+{
+ fwcfg_present = qemu_fwcfg_present();
+ if (fwcfg_present)
+ fwcfg_dma_present = qemu_fwcfg_dma_present();
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (qemu_fwcfg_list_firmware() < 0)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int ret = qemu_fwcfg_online_cpus();
+ if (ret < 0) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+ return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ char *env;
+ void *load_addr;
+ void *initrd_addr;
+
+ env = getenv("loadaddr");
+ load_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+ (void *)CONFIG_LOADADDR;
+
+ env = getenv("ramdiskaddr");
+ initrd_addr = env ?
+ (void *)simple_strtoul(env, NULL, 16) :
+ (void *)CONFIG_RAMDISK_ADDR;
+
+ if (argc == 2) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ } else if (argc == 1) {
+ load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+ }
+
+ return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+ U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+ U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+ U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ cmd_tbl_t *fwcfg_cmd;
+
+ if (!fwcfg_present) {
+ printf("QEMU fw_cfg interface not found\n");
+ return CMD_RET_USAGE;
+ }
+
+ fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+ ARRAY_SIZE(fwcfg_commands));
+ argc -= 2;
+ argv += 2;
+ if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+ return CMD_RET_USAGE;
+
+ ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+ return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+ qfw, 4, 1, do_qemu_fw,
+ "QEMU firmware interface",
+ "<command>\n"
+ " - list : print firmware(s) currently loaded\n"
+ " - cpus : print online cpu number\n"
+ " - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/qemu.h>
+#include <asm/fw_cfg.h>
static bool i440fx;
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
}
+
+ qemu_fwcfg_init();
}
int arch_cpu_init(void)
#include <common.h>
#include <asm/fsp/fsp_support.h>
-void update_fsp_upd(struct upd_region *fsp_upd)
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf)
{
- /* Override any UPD setting if required */
-
- /* Uncomment the line below to enable DEBUG message */
- /* fsp_upd->serial_dbgport_type = 1; */
+ /* Initialize runtime buffer for fsp_init() */
+ rt_buf->common.stack_top = config->common.stack_top - 32;
+ rt_buf->common.boot_mode = config->common.boot_mode;
+ rt_buf->common.upd_data = &config->fsp_upd;
- /* Examples on how to initialize the pointers in UPD region */
- /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */
+ /* Override any UPD setting if required */
}
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x8>;
+intel,date-code = <0x5182011>;
+intel,processor-signature = <0x306a2>;
+intel,checksum = <0xa0e51feb>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x08000000 0x11201805 0xa2060300
+ 0xeb1fe5a0 0x01000000 0x12000000 0xd01f0000
+ 0x00200000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x08000000
+ 0x00000000 0x00000000 0x17051120 0xd1070000
+ 0x01000000 0xa2060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x5665ff94 0x179da7cf 0x1e819fb2 0xb0c24e8e
+ 0x5cb7beb5 0x43af9a6c 0xcb0b4ccc 0x195d8712
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x72873db0 0x0f41a6d6 0x609f17c3
+ 0x1b1349d0 0xe1950c52 0xdbc8e4fc 0xebc212b5
+ 0x77697371 0x7b156982 0xe71e5ccf 0x78bd638c
+ 0x1b196322 0x8b7ebfbf 0xc2e2588f 0xf139b826
+ 0x98ac3169 0xaa9131b0 0x2d7563f8 0xa1300b39
+ 0x5bd4675f 0x25a4b079 0xe006afb1 0x2bd60828
+ 0x453a0abb 0x3b944679 0x33fd63fd 0xd26ff3c9
+ 0x23c0a581 0xf3beb03a 0xc07109cb 0x2e4c27d9
+ 0xc857a22e 0x470c5b1d 0x5b990a43 0x9f6999e6
+ 0xb5d88f30 0x48c6a95c 0x3756bdc5 0xdc7011d2
+ 0x705d8ef2 0xa657f56c 0xa0b168a4 0x219a3d73
+ 0xb761630a 0x3fa1fb9a 0xe82b74c6 0x037911be
+ 0x5104f10d 0xb4b9e04c 0x4db05893 0x86feb635
+ 0x7391fed4 0x5a690081 0x05797a02 0xce30465e
+ 0x989cdec2 0xa478a8c8 0xa406b02b 0x4ac6e170
+ 0x54ceef3f 0xbbe5e10f 0x7e60e8e1 0x32a015cf
+ 0xaf6491a8 0xef6c1c39 0x38d54b81 0xbca9aa3f
+ 0x7be47871 0x1af28407 0x07fde04d 0x56d82648
+ 0x9f91a24f 0xa71eb768 0x263f176d 0x324196dd
+ 0xa31a37a9 0x3f14178c 0xb3fbb89e 0x18d29b03
+ 0x95c2e349 0xbf559bbe 0xa011c68a 0x0be59ecf
+ 0x644217f4 0x330a8356 0x89f5956e 0xb7103120
+ 0x7d0d2203 0x9d40fc96 0xa9279679 0x81d22306
+ 0x1bc7b5fa 0x679e3a28 0x511a7129 0x81a006a4
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+ 0x22efe24d 0x215fd043 0x833f7214 0xf4603491
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+ 0x47f0bf5e 0x2724a54a 0xaf9e8b13 0xdefa0851
+ 0x4642ee69 0xd1c53770 0x96ae6df2 0xcdec381d
+ 0x66cda20a 0x3118ab96 0xb976b2b7 0x26edfc39
+ 0x55935013 0x9fad6ed7 0x45828ac9 0x226cff75
+ 0x0fed2634 0xa1d814ba 0x072b1f47 0x8fffb2ce
+ 0xa09a6843 0x530673e4 0x4859b9bf 0x8187a24a
+ 0xe27981e0 0xe8f391d9 0x32589e20 0x37da379e
+ 0xad59afdb 0x183cd4d3 0xf7469108 0xbc628572
+ 0x7551944c 0xfee39d3a 0xde1cd9ea 0x7ef53855
+ 0x5d2b7e29 0xa62cdacf 0x1adb5a78 0xa40b54f7
+ 0x9668c5e1 0x191e0c4c 0x93a121eb 0x09531f1f
+ 0x96ba49f4 0x2d1e896c 0xba78f90a 0xece1583e
+ 0x6c15bc44 0xcf8f520a 0x9a9e83ad 0x9b6b6c7c
+ 0xbff862a2 0xf17c48ed 0xcc40b386 0x75379aa0
+ 0x6fcc78f9 0x5ee6d91d 0x60e2881b 0xc5a50f2b
+ 0xb0e21c76 0x77293b3f 0x4dc3c125 0x71e5e326
+ 0x752180b6 0xf6966af7 0x96b13f47 0x842f1470
+ 0xd3cebc0a 0x23931ca2 0x9fa82e41 0x1569625a
+ 0xab11f0fd 0x0dabfc2f 0x4f499d06 0xdf2f551f
+ 0x1d59c866 0x228b7c5a 0xcb5c338c 0xf779d337
+ 0x5661e179 0x57ee6674 0x92c67b12 0x2ab20094
+ 0x86443609 0x96c11603 0x52150c42 0xbe7a1a0c
+ 0x417323c5 0x8f535a20 0x0ee45abc 0xd831b3ab
+ 0x4b56c35e 0xadfca903 0xdb953e87 0x06c100be
+ 0xccd4e5a1 0x84b1eb7a 0x740cce47 0x61e9a67f
+ 0x873b3e77 0x7dbb260e 0x2837cadc 0x2f253b42
+ 0x7afe427a 0xe8ec3710 0x5900dbbc 0x2174e514
+ 0x84ea376a 0xdd3e79a3 0xa567abf1 0xdff5891f
+ 0x4b88082f 0x70d28e4e 0xb265f970 0x8fa57c8c
+ 0x6fb84267 0x1ffed689 0xc8dfaf03 0x593d6750
+ 0x5c96ee39 0x0199636c 0x415fb6c2 0x77ab0c5a
+ 0x7f3d0014 0xb51ef843 0xdcc02ceb 0x75cf2a1a
+ 0x675e057e 0x6fd4b8e0 0xc35c810a 0x0263e828
+ 0xb3b38e6a 0xeb6f1904 0x38e0e3d5 0xe56c97cb
+ 0xb9ab05fe 0x7d00aae0 0xc3e2f290 0xd17b0539
+ 0xab6b0d3c 0x01949b89 0xbde6d45a 0x3ea48534
+ 0x2585b3ae 0x20eaec0a 0x12165161 0x81eb9e23
+ 0xbf087042 0x769a37d3 0xbee94e4b 0xd82d0346
+ 0x95284516 0x9cdd530b 0x610188a3 0xe1cb1a84
+ 0x201023e8 0xa2b51aa1 0x5f793de7 0x7822f6b7
+ 0x3415fd61 0x80d0dbd2 0xeaa0b1d0 0x0647a151
+ 0x37a04153 0x64dd9b5b 0xbea43949 0x7ffc6b1d
+ 0x3ec171d9 0x16399842 0x0d539e5b 0x168772af
+ 0x50528a24 0x1ba46948 0x4d1c7622 0x7eabb87b
+ 0xe1f28f53 0xedfe9f50 0x0882e6f4 0x0b0e858c
+ 0x53202809 0xdd40481c 0x98f9548c 0xd305e7f4
+ 0xaa3a3b82 0xf5dfbd5a 0x7f3f0103 0x68d7e48a
+ 0xf9cbe6ec 0x0aaa6ce6 0x983430db 0xa93473f0
+ 0xab4a9fe8 0x5967af5f 0x2e4a1aad 0x0eb753b9
+ 0x5252c78f 0x20cc9e56 0x6d7d06b4 0x01ed2c54
+ 0x7458f014 0xc472083b 0x5ebc4b2d 0x11938115
+ 0x5609a0d3 0xcfccc47c 0x44c7215c 0xf87411c1
+ 0x22a92265 0xd2b00607 0x033ba680 0xb4ed58ed
+ 0xc58e4a87 0x60836e06 0x9eaff4fc 0xa0528e78
+ 0xfd20b0d3 0x02356e10 0xa047e404 0xa9283593
+ 0x54cdff7d 0x3eb1403e 0x9f4a7f56 0x670a19e4
+ 0x497d4c90 0x7d4b5b52 0x240ad44f 0xa8d2f730
+ 0xae53e947 0x566c963f 0x109b6ca8 0x27dd1a3f
+ 0x2c1c5ef0 0x796228e6 0x24220a88 0x008e2bcb
+ 0x74d45ba5 0xce0484fb 0x8160be45 0xdc3b4bb5
+ 0xc1cc6e3d 0x1f692d98 0xd4387a6d 0x6efc2aab
+ 0xdcad07eb 0x95be0966 0x58b6c364 0xc23613b5
+ 0xe911e2c4 0xd323a52d 0xba9a0937 0x026db7a6
+ 0xdcb5253e 0xc4d75876 0xfe7c5882 0x70cb8faa
+ 0x8fd4396f 0x71f19b8a 0x5c6d8137 0xaf3c55e2
+ 0xe4fa5eaf 0xb489bc28 0xe4059d20 0x7f776f27
+ 0x418d7e67 0x0560dd23 0xddc8a9f2 0x5d24cfc9
+ 0x9e0e807d 0x1baeba2b 0xd4085729 0x95604427
+ 0xa1b82a01 0x9ebf78b3 0x7da9a0bb 0xebad0bcc
+ 0x876ac5f0 0x50f5e56d 0x35bd1ac5 0x33ce5e78
+ 0xd0796806 0x28523eb0 0xe0e25542 0xd89e9c2f
+ 0xf6aa4a94 0xd9843f54 0xde1c58f0 0xa43b7439
+ 0x438c402a 0xb29e8468 0x2d8b8b39 0x3ac583c5
+ 0xad2624a0 0x2e57fd2d 0xbf4fd6b8 0x8f86a6ad
+ 0xee7b10ce 0xd6a0ff5c 0x796cc316 0xe9592c97
+ 0x78fb0448 0xeb7142a7 0xc23de330 0x510681d9
+ 0x34034a90 0x535cc5d7 0xbaafd38c 0x5d11e611
+ 0x58c99b2c 0x2eb95f00 0x8db62076 0xf49d8396
+ 0xae6f906e 0x7ac672ff 0xc82f6f2f 0xe04071c7
+ 0xc60fb70b 0x2d0065b4 0xc7dc4d8e 0xe5386450
+ 0x45de7648 0x4d9d9ed5 0x1ea63c26 0x7e65c525
+ 0x5a3aa43d 0x68d8ad03 0x125edc7f 0xe444712f
+ 0x04f20274 0x8e892ae5 0x790c0141 0x3589a296
+ 0x6615472c 0x923399e6 0xb796db99 0x36b70376
+ 0xfa59ef8e 0x580ed43f 0x770c41c8 0x0760ac46
+ 0x76755f0a 0x55272e71 0x64778d44 0xcc8e527a
+ 0x0863f548 0x2b42f2c5 0x20756bcb 0xf1753f6a
+ 0xaab7bc8d 0x8d58c65a 0xc2292ed5 0x92f5f173
+ 0x0ff9fbe6 0x805f2512 0x617a5b90 0x92532577
+ 0x152d0a3b 0x51c6273a 0xb467eb12 0x973aa5fc
+ 0xffd5fe17 0x9def8fb4 0xe5f9ee6f 0x3050215b
+ 0xa6c512c4 0x95fc2825 0x56b9c86a 0x296ff9f7
+ 0xd5bbd16f 0xfdd6408f 0xcab0ce03 0xa3a37242
+ 0x6fbc45d8 0x528f4f44 0x195c3aa5 0x3df1ddfe
+ 0xd705871a 0x6d525fdb 0xf2f0177b 0xe856b5f9
+ 0x5a62fb0e 0xa10c6b11 0x76c4de6a 0x620929d3
+ 0xc74465cd 0x70d6eb66 0xc789cff7 0x9b40ec8c
+ 0xf8d44b90 0x89467100 0xbf5de474 0xd93ffb76
+ 0xa77e0fd6 0x9a6dedf2 0x7a4b5bff 0x4353cc95
+ 0x19ad6141 0xe93efcc1 0x63716258 0x5dcb90e0
+ 0x216ed316 0x38e053f7 0xb2d11a29 0x401fb696
+ 0x0f60ff0a 0x59c96ce3 0x41ae78bf 0x11293802
+ 0xe2140131 0x06b3aaed 0x945a8a4d 0xbdc051cc
+ 0x12a396f8 0x86c84c40 0x2398465d 0x90831319
+ 0x4d8b474e 0x31edf74a 0x68605ffb 0xdbd5aab4
+ 0x03a20ef4 0xcb578309 0x55cf8de4 0xeb63cc3e
+ 0x77b6e657 0x9064c204 0x7e508ca7 0x51f9cc07
+ 0x2034a87f 0x9e8d6363 0x2347348b 0xb33811f8
+ 0x61059c50 0x6644040c 0xbb47186a 0x0b39b8a5
+ 0x719a5cb0 0xf6039950 0x890dc3a5 0xb2c3e909
+ 0x843ba28a 0xeeb824c6 0x0b0fd3c8 0xa0ae5b58
+ 0x5fc0fbad 0x869e0f43 0x8157a6ce 0x012ff9e2
+ 0x7aa0588e 0xcea70c7e 0xdbeb31a2 0x1cdc813c
+ 0x58772a19 0xd6ef8b39 0x211d0c2b 0x521336f3
+ 0x0748e0d6 0x31180d54 0x17f2e391 0x7b200851
+ 0x12a76efa 0x93584a83 0x59a26d00 0xf443aff8
+ 0x3a6c1c64 0xab949fb1 0x54bb06a5 0x818d1d12
+ 0xc69783c8 0x6effa0a8 0xd61c0c05 0xd76d617a
+ 0xf89c3b36 0xbbf2c9e4 0xefd5e16a 0xf239e70b
+ 0xe124dcf9 0x0ce35a7e 0x4e5de898 0xe898bb85
+ 0x0eda9543 0x189bb85e 0x3237d51e 0xa81afba4
+ 0x50e5417c 0xadfe8513 0xd00a97c3 0x7942e79c
+ 0x45a3f95d 0x38c92d7f 0x66b0fa65 0x88f34b2e
+ 0x945e83de 0x6fd718fa 0x09988ebc 0x185afb1a
+ 0xa4bc09ab 0x763ee195 0xd565b562 0x513d30cc
+ 0x4eca27db 0xab95cb61 0x797f0ba2 0xd1d17c13
+ 0x7fbdcbc0 0xf2680538 0x8b7d8039 0x545a92be
+ 0xf7e5dc0b 0x17ff40cb 0x91b1aaf5 0xa65cfaec
+ 0xe4b88f59 0x5d4a3d52 0xf649b8a7 0xe2d5240a
+ 0x5e4090d8 0xe8ceb64c 0x5e7604a0 0x87e50b84
+ 0x78baa4b7 0x8a134528 0xc130aa24 0xbadf6b92
+ 0x3996d321 0x13d44664 0x6c30618f 0x9546bc58
+ 0x440b2d80 0x4ab82baf 0xe605672c 0xda1e84c7
+ 0x0436c4e8 0xf1726cd4 0x380df7f4 0x76cff6ea
+ 0xec52b439 0xbd0acfa6 0x4a66c6c1 0xee77b3c8
+ 0x305e5ad1 0xe3df7a5f 0x6d3ca452 0xe2f0bb6a
+ 0x20aca9dc 0xff5f2785 0xaf1d85e8 0xd4c55653
+ 0x52bb24e1 0x54d928ac 0x07cd70ee 0x39274492
+ 0xf7baebc4 0x65071bbc 0xb73a6304 0x2a18402c
+ 0x04e85d51 0x0eb01c76 0x6f73e255 0xd392e3ab
+ 0x31ab0616 0x9ab8ba65 0xab2a2eb9 0x34934a78
+ 0xf8561348 0x2f6642b1 0x30261a32 0xb2a6c09a
+ 0x4a420e88 0x33557453 0x19bda003 0xaf4e76ba
+ 0xed9dc685 0x604c61a9 0x9725b972 0x329201c2
+ 0xa9b4b087 0x5e06c74d 0x9628fdb1 0xe6dc0d04
+ 0xb18577fa 0xa989c3cc 0x5b299fb7 0x36aaa3cb
+ 0x6b39a761 0x25bdf05f 0x7b7c71ba 0x8265ae16
+ 0x403fe456 0x96ec45f1 0x087b5470 0x217e734d
+ 0xe65c9541 0x688d43f3 0x5bcec90f 0x80e971c0
+ 0x62f76d35 0x5f9030d0 0xacefa05f 0x64ac9810
+ 0xd6667793 0x35f8565f 0xf7247bcb 0xc34e0feb
+ 0xcae60e22 0x728fffe8 0xcf6a16ce 0x8d4fac73
+ 0x8ad230fc 0x987257c0 0x8c7a1da5 0xa7dbda8d
+ 0x3c09c385 0x647f2867 0xf0b3b5dc 0x781eb0e9
+ 0x6244d05d 0x337bd6a2 0x77dd9e28 0xc48c5512
+ 0x883e4cfe 0x66ad74fd 0x1f659c37 0xd65bfb11
+ 0xb2389cda 0xdfdd6141 0x28888c3d 0x2e76ac3f
+ 0x7b21a7f9 0x5ceb1f5b 0x97f62545 0xaefe190f
+ 0x16fd077d 0xd558d127 0x1fe8a8a7 0xaab0dc71
+ 0x8ea4576c 0x17a8b8ef 0x7476364f 0x229b0ca9
+ 0x236b1e56 0x5c1bd152 0x20002652 0x8c0805cd
+ 0x4c122c4d 0x6cbd72db 0xa9d9d258 0x4817fa88
+ 0xc805adb3 0x227416db 0xd58adbb5 0x11cdd037
+ 0xc06e6c92 0x1c548525 0x8cbfab9f 0xa4b1c180
+ 0xffab2b24 0x186068bb 0x8983f63b 0x982997b0
+ 0x5abc10e6 0xdfd139c5 0x11c9b6e9 0x86cdfc81
+ 0x4f8010c7 0x1e1646b6 0x9d66a0d2 0x37c4239d
+ 0x8066847b 0xaadad61e 0x3eaf7caf 0x957e015c
+ 0x4d78bfc3 0x15c3fe27 0x6c2d2fc5 0x84af2a8b
+ 0x59a66a0b 0x3e13f346 0xe9874a62 0xa7446843
+ 0xdecfe92c 0x120cf098 0x1d188cb6 0xa4938e5f
+ 0x9023d7e1 0x8bbdb7db 0xaf452ce8 0x6854d9e8
+ 0x0604f218 0xd39c3237 0x3754ebaf 0x4ae59d90
+ 0x3913e367 0x99b1902a 0x78c06ff6 0xc177a4a5
+ 0x218159ad 0x01ec7cd6 0x5a6bda31 0x9a753f92
+ 0xecad36d9 0xa2216cdb 0x4fc8328e 0x879ac7be
+ 0x23f3f907 0x5b59fad8 0x122a1644 0x16e63209
+ 0xcfc827a1 0xfe332476 0x2b72bb15 0xd478caf1
+ 0x21deb5e0 0x3c1a561e 0xb59be4e8 0x4598f63e
+ 0x20194b01 0xb4d76ed5 0xb58e06d8 0xb1219a36
+ 0xdefe3946 0x0731248f 0xcfa09f93 0xe420d6e6
+ 0x8a0518ba 0x013d8f80 0xd32a05ed 0x7d9d8209
+ 0x548cb1d4 0x69457a2c 0x668a0a70 0x8cc2b661
+ 0xb72d4ad3 0x19b388c7 0xb844dd6f 0x4dc39493
+ 0x7e96565c 0x53959236 0x1dd4a349 0xe50914a5
+ 0x319844c0 0xddbb2abd 0x2f126ba4 0xa46c6d63
+ 0xd6829c4d 0x8f178677 0x8ae6291d 0xb5660702
+ >;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9082011>;
+intel,processor-signature = <0x306a4>;
+intel,checksum = <0x7e23e5af>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200809 0xa4060300
+ 0xafe5237e 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x07091120 0xd1080000
+ 0x01000000 0xa4060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x9539a0b3 0xc7bb991d 0x308f0f1a 0xb1ba077d
+ 0x8bd7260b 0xd710ad0c 0xf82ee64b 0xe6f11ce1
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0x71f0ab19 0x85635e57 0xfecdeb36
+ 0x7c93f457 0x13e3fb92 0xa512551d 0x6ac10509
+ 0x423fe38d 0x778481b6 0xff413c23 0x534d1d6c
+ 0xade61b9c 0x8cc43e62 0x0a8e5091 0x47382579
+ 0x8ee1d885 0x370915dc 0x8d8274f9 0xff11ba81
+ 0xb0919d7d 0xac434821 0x46d13494 0xe7fcc12e
+ 0x37876ec1 0x67a67b02 0x8d80b952 0xa2bdb26e
+ 0xf19c0c77 0x7b1f5296 0x544fbc2f 0xa8a3b1de
+ 0x8285fcfb 0xcab6dcc3 0x2a63f8de 0xab28edcf
+ 0x86e0e1cf 0xc21e5137 0x04616818 0x3172cc2e
+ 0x4a472e10 0xea8d7f3d 0x7e225494 0x7df2be43
+ 0x8a86b11c 0xf6894a26 0x81b6df9a 0x967c4076
+ 0x8c3e7b47 0xf81709e7 0x8bc622d9 0x4ed8aeae
+ 0x7cc696b5 0x45fb131d 0x77f322fb 0x4801173e
+ 0x056db13d 0x9a64fc3a 0x1508afa7 0xbb357cd3
+ 0xb863aa72 0xe57b932d 0x30892535 0x56a5e167
+ 0x842d402f 0x3113bd4c 0x04016ae3 0x7d81c983
+ 0xdeb79060 0x950e14e6 0xab7833c9 0x297e8abe
+ 0x49252831 0x489acc6f 0x9ed63fab 0x3166416d
+ 0x97319343 0x28ad40d7 0x3fbb9b52 0x203c7460
+ 0xe03bf6a8 0xbe288f65 0x8183b5d7 0x3752814b
+ 0x57405958 0xb4b3ab8d 0x235ba207 0x20bf3240
+ 0x9ea6da77 0xb8f77bf6 0x83d7ce90 0x5575d3de
+ 0x21f46a2d 0xaba56e91 0xb5657416 0x6ed3bce3
+ 0x1cf28b50 0x7e3f8573 0x76ed8028 0x8c785c22
+ 0x5a0fec15 0xbec7ac15 0x3763a0c6 0xd0fcfcdb
+ 0x39581ba2 0x386e0e74 0x4336b4a8 0x4bcc5176
+ 0x314b2da1 0x2ec76c38 0x2a517be5 0x17ce6f78
+ 0x7f124d6b 0xc68ce86a 0xac7d29f3 0x7ea7cbd0
+ 0x053169e4 0x4c0d5e6c 0xe39aa81a 0x083a39bd
+ 0x6d71ce68 0x7c50cc9b 0x10aa72b9 0xdd11c952
+ 0x43bea88d 0x9c1ddab6 0x41b013af 0x1e98de66
+ 0x554b92a3 0x86bac233 0x50fae8f6 0x358742c8
+ 0xa80c50d9 0xdfe9302d 0xc9b4c715 0xdb4b1c66
+ 0x78b7d75b 0xadde8aa8 0x59c09d74 0xa46b87d0
+ 0x548cc5b2 0xf9b8b729 0xa738e8c3 0x1c5a00e1
+ 0xd9c2d59a 0x8d1cc5de 0x05bae2e5 0x0ecdfd2e
+ 0xab3a984e 0xcf53db57 0x3ebc3c88 0x6b60e477
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+ 0x54de129a 0x793b2e40 0x78d5e95c 0x6f433a46
+ 0x49264de9 0xe155bf0e 0x3bd4788b 0x7b9291ec
+ 0xf80b3c50 0x5ada3b87 0xd1a7b055 0x4cb0eb44
+ 0x4f712378 0x36bc14b4 0x7bd0b6b9 0x62920554
+ 0x780ea525 0x1c74f629 0xe1431d38 0x4ea1ff33
+ 0xba9ad4ab 0x6b8113fe 0x0022a139 0x835303e0
+ 0xfa39cff6 0xe45918a5 0x844484a2 0x55b42e18
+ 0xf14cd964 0xb65c5efa 0xd04e9cbb 0xcba8edf6
+ 0x2dd6a76e 0x1d5da1ec 0x9329bd8b 0x527d6e4c
+ 0x956956fa 0xeaba1ade 0x9125ddfd 0xd6f09a18
+ 0x4d2db260 0x8c8b9e8d 0xca95ab0a 0x5bbe0573
+ 0x7310a64b 0x4d5c4c73 0x0a2f0b12 0xaf9bf6c7
+ 0xc9687aa8 0xe5a2a604 0x54ec3dbe 0xf4256cc1
+ 0x405fc417 0xa19ca399 0x93531bda 0x595298c7
+ 0xa28dfa52 0x7385a266 0x027dc36c 0xcdb82903
+ 0x5ce4b82c 0x98977244 0x0d4cf474 0x99236465
+ 0xb67a8672 0x1e1fee2b 0x38a75771 0xfb017ac3
+ 0xc04889d4 0x93753894 0xa9603439 0xb37a2ca7
+ 0x8491a2b3 0xdf1cad03 0x6717cc79 0x9f8bacae
+ 0xa053641e 0x8383fb3b 0x0229b112 0xf9d2a0f0
+ 0xb578ff0e 0x79a48f10 0x33a2f133 0x8d9a77ae
+ 0xd931bc20 0x6629f839 0xeb0e4ada 0x2b8c1290
+ 0x2c3aee9b 0x324eef42 0x13b50a02 0x059aa872
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+ 0xf7a92001 0x9bb5dec8 0x49b44f85 0xa3f93611
+ 0xf2d51bfd 0xf8e42618 0x03d9a8dd 0x34526d3b
+ 0xa3b9112a 0x385ff261 0xae991c2f 0xdd990afb
+ 0xf10471f1 0x842b7feb 0xc959bba6 0x51db24ca
+ 0x7af01558 0x1abc2242 0x8adea69a 0x77140ced
+ 0xd7fa451f 0x46c48f08 0xf19545c7 0xc571c2a0
+ 0xd24188c2 0x2da3f8c2 0x035b1847 0xcfbccf6c
+ 0xe4e6123e 0x56967bb0 0xb0187725 0x1e98dd1f
+ 0x2c5f8b17 0x42ad6c44 0x7dc0cdaf 0xbdbc7762
+ 0xf926a4fb 0xac0b9ea6 0x7108af88 0x335f4e85
+ 0x174ff319 0x08263330 0x9ab6c830 0x2dca63a5
+ 0x479bf730 0xc8187fd6 0x97daf5aa 0x66f9147c
+ 0x448b62b1 0x9db3dfaa 0x4c0abeec 0x3eb5e03b
+ 0x726606d9 0xe2c3faf8 0x8bf2f174 0x6395c1fb
+ 0x1e84bf32 0xfb452586 0xee550d69 0x40858cdd
+ 0xf454cd26 0xefb81d50 0x3c879cfc 0x41a58812
+ 0x30338aea 0x42288f92 0x4a4980a6 0x40556e1f
+ 0x3d14bcdb 0xd6509d13 0x494d8e13 0x05ae949d
+ 0x1d8528cb 0x40c73cb9 0x24e60bba 0xbdd52ae9
+ 0x4aa0fc29 0x5f01792b 0xd0d13875 0x7c3553dd
+ 0x41a52955 0x0325f0f0 0x49ba411c 0x05d30bd1
+ 0x2af8ea4b 0xf91e6a39 0x17054898 0x33516ff4
+ 0xc62cf75c 0x301a0459 0xc18857e3 0x78f05585
+ 0x07eee4db 0x014c9d2d 0x5e67a82e 0x9babf458
+ 0xb7ada3a8 0xb4c978ea 0x0ac14e64 0x6c47ff91
+ 0x9900eea4 0x1ba7c285 0x51c7f0e4 0x64d8f725
+ 0x0f0cdc9c 0x69cd6c3a 0x37589cc1 0xe9bcd133
+ 0x23b39134 0x205ba564 0xc00dbffb 0xf01c3680
+ 0xada1dfc4 0x3494c547 0x34f95b08 0xfaff44b5
+ 0x8a2b6e4a 0x579f3f04 0x7cedfc17 0x41ef4344
+ 0xe786cd57 0x5ddfbc7b 0xecd5c628 0xfe55a66e
+ 0xa68bcf08 0xd69384d9 0x9cfe6968 0xa98b01b1
+ 0xf569ba00 0xdbb51d1c 0x3df4a346 0xf913cbfc
+ 0x8b156a28 0xf95684bc 0x5bc070cd 0xf6b27548
+ 0xe7f9c2ae 0x9233351d 0xa9ba9381 0x632c9197
+ 0x6dbd7022 0x67b448df 0xbb62f843 0x6a712209
+ 0x03867759 0xd7baeeb4 0x5104c12a 0x11f9e0c8
+ 0x9fae9186 0x46c17ca4 0x33b16593 0x20308078
+ 0xdfebe428 0xac27d933 0x59cff948 0x60eae57f
+ 0xec308135 0x2a2b3da3 0x47c74c7e 0x24dd1bac
+ 0x11f67090 0xd2b37df5 0x2367170b 0x08b3ce06
+ 0xfeef940d 0x46cd6519 0x6685cee3 0x23244876
+ 0x5929c779 0xf8fd52b5 0x7520251b 0xbe64ea34
+ 0x594ba72e 0x8a522818 0x3a563759 0x448dfe58
+ 0x28b8193a 0x8b898a6d 0x26b1864f 0x94b9a512
+ 0x58c57299 0x326b3c96 0x3073f0c2 0x5c9623f5
+ 0x69e2d14d 0x06c69b27 0xbae70a29 0x77120eff
+ 0xbd57a135 0x3182e024 0xc48ce0fc 0x889476f2
+ 0x9c5c428e 0x18243a48 0xf226e200 0xa434bc0a
+ 0xc31975ba 0x7a7ff48c 0x6e459a3b 0x171057cc
+ 0x7e4cacae 0x6e2d9566 0x4a253a89 0xb26b3cab
+ 0x342ba69c 0x03c13ba4 0xce667e63 0x32250c84
+ 0xb15f105a 0x436c5c66 0xdbfd79b1 0x090ca274
+ 0xa3f5ece3 0x4b3b4650 0xa41a96b2 0xe527bc5d
+ 0xada0de6d 0x87e5a944 0x5d99e654 0x3cc3d95c
+ 0x67c2e1fe 0xa05b8205 0x5fe902ef 0xcef05b37
+ 0x1081e4f5 0xe381012c 0xd4953b82 0xacb344b4
+ 0x278b5104 0x9e8f6f53 0x539cc1cd 0x55a16099
+ 0x235f5ac5 0xcaed439c 0xad386728 0x5d2656fd
+ 0x50e1622b 0x76422754 0x88c2a109 0x6c5faaa8
+ 0x413faaa4 0x8e64eca2 0x1c900d41 0xab89b33c
+ 0xec9e418a 0xcd7d4db8 0x65a17ab1 0xbf52c694
+ 0xeecff735 0xa540d8c3 0xaa45a930 0xc0070502
+ 0x18f8e76c 0x0d0958bc 0xf5c2aa4d 0x1deb8b87
+ 0xb06edbcb 0x50228379 0x600947b3 0x99f01bc6
+ 0x9290adf1 0x3353fa5f 0x5256cbef 0x19c196fb
+ 0x822b7e48 0x5400d0c3 0x12fe150f 0x5ada541a
+ 0x410eea57 0xc34b0ac3 0x3a7ea361 0x3dfdbc15
+ 0x3d2ae574 0xd3f41956 0x79bcebc8 0x85681660
+ 0x27855dc6 0xe61bd8a2 0x47eee402 0x7e6e74c9
+ 0x0e1fd6bf 0x6ff32cb5 0x40da8747 0x85e02a6b
+ 0x9f7d9a5c 0xaa512efd 0xc6673d19 0x8218c318
+ 0x0fde8712 0x612ec9c8 0xbd40745c 0x2daf88a0
+ 0xad6e44c6 0x2e087d9e 0x1652702a 0x4fd9afe1
+ 0xabe830ef 0x08dd3913 0xce99af5e 0x2ad29258
+ 0x2d2bb1fc 0x4cd05f07 0x86c1d313 0xc121df89
+ 0xdc34b9d7 0xcf66a60b 0xf4be35c7 0xaea67507
+ 0x0905d5b2 0x6e6aec02 0xa4ed411f 0xeaada4ec
+ 0xf548fe2b 0x4a2e9a7f 0x8884168d 0x7b3cd8f9
+ 0xe380c72e 0x6332531d 0x96228e28 0x0d019478
+ 0x38b0bba7 0x3b35de12 0xbd8cf061 0xc40be0db
+ 0x308f624f 0x014dce9c 0xdc9d4c1c 0xe7cf4845
+ 0xd3c3cb56 0xd273eca6 0xd4574a88 0x47df611f
+ 0xeea7b70e 0xdc4b81b8 0x1f3adf2e 0x695634c6
+ 0x249ef15f 0x7b2b6dfa 0xa39a7367 0xf3cc99dc
+ 0xe0743236 0x6e00ecef 0x4bc24c6b 0x557ca804
+ 0xbe759d03 0x0eb2c5c4 0x366a6da4 0xa40acf07
+ 0xcaaa7952 0x63dd5b89 0x6f09f54d 0xc598a3b8
+ 0x818270a9 0xe85e2b53 0x6d437ced 0x3301c4ff
+ 0x8950ff23 0x88e3303d 0xf3b7c745 0xd823996d
+ 0x2a4caebc 0xa1eb7e2c 0x960fa785 0xa5d9192d
+ 0xb771a75f 0x6c17bda4 0xa4c62290 0x01f559c4
+ 0x5b6bcb90 0xbdf4e260 0x37d24146 0xe9f7c113
+ 0x224c8d1e 0x944f0d14 0xb7a446db 0x470e1bd8
+ 0x5b4553b1 0x9713ed1f 0x3bb0621f 0x5d13ccd2
+ 0xd1512876 0x92172e03 0x80d4f34e 0xfd03a89e
+ 0x82de677a 0xe72e0a3b 0x593b0502 0x7825be45
+ 0xa765c6c7 0xddef9369 0xd449c6a6 0xe4440203
+ 0x8be34a5c 0x22617938 0x6eaacd0b 0xd0b47183
+ 0xd39589f4 0x3159c597 0x76a0a4ec 0xf434b1c5
+ 0xf3a26de7 0xe9b69e3c 0xceb232f8 0x7bc91c43
+ 0x225cfa3a 0xdbabb166 0x04d4782f 0xd573884a
+ 0x351f5f88 0x4acda1e6 0x2cb93b68 0xed4b0663
+ 0x1dd147b0 0x4b64aa81 0x9baaddd3 0xdb305d03
+ 0xe44403aa 0xd52140b8 0x442e2197 0xfb8f8aa2
+ 0xa1d2b054 0x30ac7b0e 0x535ff138 0xa34c29fb
+ 0x4dcff8e5 0x4d4b5af7 0x75846d8b 0x29060275
+ 0x154f0dbc 0xf506c696 0x18706d08 0xbe1cddfe
+ 0xc972edf3 0x070f4aae 0xe5055290 0x12ff9063
+ 0xe4b81a09 0x11ad8348 0x184faea6 0xfe9b3674
+ 0xd8a68c8c 0x28366da2 0xd0729297 0x8c07e77b
+ 0xe85cb507 0x54d582d1 0x0e10aa56 0x5f79aff3
+ 0xb5c2f58c 0x0976ca59 0xd43bed61 0x9e76951d
+ 0x4bc2542e 0x7a1870fc 0x2cd01266 0xcc717daa
+ 0x045e2757 0xa5b943c8 0xbbb21e51 0xa19b070c
+ 0x985e3e58 0xb0f22523 0x1dfac693 0xe2491946
+ 0x649791b6 0x54d4f8fc 0x2920c0c0 0x45af983c
+ 0xd400878f 0xbf94ce47 0x00dacb15 0x8f79afc0
+ 0x96d4d1f6 0xdacc4fee 0x3eac2a87 0x89f808a3
+ 0xa8963eb3 0x3bfbf9fc 0x16970a5b 0xdc925ecb
+ 0xfa5e4920 0x219ffbea 0xfb442d8f 0x32a5d657
+ 0x7db7483a 0xfb330167 0xe75f7f87 0xea1de0e1
+ 0x764b080a 0xed1eab80 0x6b75f59a 0x8dceba7f
+ 0x735a7fce 0x68128837 0x7243057b 0x4da7a027
+ 0xc1c502ca 0xa5f2bcc4 0xf2c6209c 0xb675c45d
+ 0xa5aef423 0x362b5df4 0x7840609c 0x714209ea
+ 0x3919be09 0xc67c360b 0x6ffe8d84 0x3dcc0e10
+ 0x558ec8dd 0xa2285d7b 0x9eb86078 0xb4685e77
+ 0x3840ab30 0x2ac2fdb1 0xc6b795c0 0x834c15c0
+ 0xaa0ff942 0x74fdc7e3 0x87ab3565 0xa9d3f71c
+ 0x53ad4955 0xad5191de 0x3e30a79e 0xee227702
+ 0x5910cbaa 0xce926dbc 0x629937d9 0x271e98ea
+ 0x29ac6f12 0x09248669 0x74d8fbb5 0x435a83c3
+ 0x93dd39a3 0x7bcab8ab 0xf86858ac 0x403823a8
+ 0xd9fb5669 0xddfdc2b6 0x9b7e771a 0xf7a6a574
+ 0x1bdc0062 0x54c621be 0x45a49ac5 0xf4b5c38c
+ 0xe7916b1f 0x4ea7f121 0xd5457986 0x6bb57a6f
+ 0x1bc4d42b 0x2ab0ee84 0x5b8e508e 0x6adf0b60
+ 0x1c39dc48 0x25d58fce 0x54327b32 0x93718903
+ 0x991e452b 0x627cc0d3 0x15233871 0xf921f79a
+ 0xea6475d1 0x9b155143 0x5914ee94 0xbbeb43cf
+ 0xbd590426 0x8aaaa0c4 0x50b174a1 0x51aa1955
+ 0xea349dfc 0x005a2de4 0x4603a63a 0x971af0b8
+ 0xbcd89a17 0x1d49e631 0x63d3a40c 0x63b0f1eb
+ 0x975757fe 0x706e086e 0x161d0cad 0x5b5f4fe0
+ 0x4a82f4de 0x34800a89 0xdcfeeb96 0xae9c0bb8
+ 0xa6422c15 0x8ee1b10d 0xa454ec0b 0x1a51e7eb
+ 0xd2767564 0x8541c726 0x7e0a8cb8 0xbd6f58ef
+ 0x7325c5fd 0x5f8b8144 0xb18853e2 0xd6ac3e90
+ 0xeccfdfaa 0x8bed8778 0x7d65f220 0x86502ddb
+ 0x272d7bbd 0x9546beb4 0x2fdbc971 0x8f86c26d
+ 0x317131ee 0x06a2d84b 0xcfaeb274 0xbdc64496
+ 0x842eee16 0xc5596e5e 0x3fc8d83e 0x60ce3e3d
+ 0x233ff26f 0x8e7eea69 0x3dfb8b62 0x0bd1271f
+ 0x3276add3 0xdce0f322 0x272f2fed 0x310b01b9
+ 0xec13dbff 0x44ecef5f 0x716a95b1 0x8e2ed760
+ 0xfc1cdbf3 0x363ab021 0x529c749c 0xb8361787
+ 0xb576b8dd 0x05ba72be 0xbd94ddca 0x995823cd
+ 0x4bf10e99 0x6350d475 0x6fab0d5d 0xa3fb7ef0
+ 0xa755d719 0xefeb5c22 0x8369b60e 0xa190b7b2
+ 0xf1ca5eba 0x406fbd8f 0x0b858d59 0x9f4f3a99
+ 0x600706c0 0x8efb77fd 0x8ebd23fe 0xa82b4e93
+ 0x44d50e4f 0x92a2b5a1 0xde8229a0 0xa9128ba4
+ 0x6dc829bb 0x5d63bac1 0x8948d416 0xbb85eebc
+ 0x4b280f18 0x6156e24b 0x5271526e 0x3a550970
+ 0x7212c942 0x09040eba 0x0c199ae0 0x3f41b3f9
+ 0x8d439401 0x83319b2d 0xf3deffb4 0xfd813e2a
+ 0xa8ac6a50 0x72858022 0x5650a6ea 0x8b9e18a3
+ 0x7dc2d48e 0xabf0c35c 0xe9d93f5c 0x228412d4
+ 0xa7b07016 0x0babb01b 0x36faa524 0x3157fe90
+ 0x4cf0fd08 0x1272a76a 0x8e701e54 0xd1ed3067
+ 0xe92bc6ac 0xea2fcc5d 0xdae1a6c7 0x4ec3465f
+ 0x97556141 0xda282893 0x2bdf77f3 0x458abb7b
+ 0x8c98d27e 0x9f2ddc8e 0x4bf66134 0x7ef33d1d
+ 0xe7bfef39 0xa9b37d3e 0x2272b785 0x41bc32d3
+ 0x16790e7a 0xfcd172a9 0x4dcbdb4f 0xadc6cea4
+ 0xe72aab79 0xd3a530cd 0x153171ea 0x60d6122e
+ 0x1b00ebde 0x366861f2 0x6781fc14 0xe6d6189c
+ 0x3b9beebb 0x5c239e07 0x51999573 0x5b900c94
+ 0x52a14fae 0xc7c0bdfb 0x5bebb646 0xaaebca2f
+ 0x360c6d2f 0xc8b43453 0x16ae683d 0x11248d2a
+ 0x08fa3017 0x2bfc636f 0x7360ae91 0x793ad23c
+ 0x7d2bc4bc 0x2d505664 0xee449c94 0xbd0beb6a
+ 0xa9b818e7 0x251354ca 0x119825e5 0xae8b8d2c
+ 0xeea15a2f 0x8b3c47ad 0x2af74ac7 0xaedb8156
+ 0x9b96ee47 0x05034a2f 0x752f8722 0x0f1ee372
+ 0xff55b4b5 0xd12d4ead 0x554c31c4 0xc167849a
+ 0x118d9c61 0x9825a5b5 0xd1941592 0xa21440d6
+ 0x0c8fa874 0xd23ff93c 0xf592f75b 0x6d171131
+ 0xe1cc848b 0xe73fe5cf 0x38677f4a 0xddbbd004
+ 0x6af79754 0xa666b38e 0xf5afba55 0x036b1f0b
+ 0xd55860f2 0x1efdbe6f 0xafc557a4 0x3b24c27d
+ 0x68f319ef 0xf863285e 0x80e88563 0xbe2af6a4
+ 0x81360909 0xcfbaac9a 0xa0a07505 0x8c653634
+ 0xf630bc25 0xdea1640f 0x51445022 0x8bd02194
+ 0x593185c9 0xc23f98f1 0x06b6d384 0x432278ed
+ 0x9c422519 0x0664dc91 0x733e7075 0x9e05a4c2
+ 0x1b014110 0xc4787233 0x4aad488b 0x756f0d47
+ 0x9e29a6df 0xabde4b5d 0x23727bdb 0xf1e3a05d
+ 0xa1f22c40 0x2d290090 0x62d3b212 0xcc247195
+ 0xcd5c84a1 0xf277c61f 0x4f9f213a 0xa69e7391
+ 0xf09f4162 0x44771471 0x6be202f9 0xf27e05bd
+ 0xef27ffc6 0xb94d8b95 0xcc124e11 0x6d22e955
+ 0x8c572ef0 0xc59727f0 0xa68aa858 0x034de5f4
+ 0x242700ae 0xcad4225a 0xb5e792ea 0xf791ab32
+ 0x8f75a863 0xd078bb02 0xec889a62 0xbae59fa8
+ 0xd0e96b37 0x7127e3a9 0x69283a7c 0x7fe26fca
+ 0x3b33f97f 0xef3bfad2 0x0a33c011 0x060e0e58
+ 0x27de1402 0x55f0b8c9 0xf48de31c 0xacbc1c7e
+ 0x228459e6 0x9119a04c 0xeae173ef 0x50347a6c
+ 0x6da1ae72 0xcea1256b 0xc328fe6a 0x85a48b53
+ 0xd8bdb49b 0x857cd611 0x2218a975 0x4893fbe3
+ 0xbd0b7590 0xdc35b430 0x0b37d8a4 0xc1938a77
+ 0x78423be3 0xbb14bb91 0x0c900fe5 0x82037d1e
+ 0x1fc0a8c5 0x5b83cd7a 0xf1a7ff8d 0x36cb83e6
+ >;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x7>;
+intel,date-code = <0x9092011>;
+intel,processor-signature = <0x306a5>;
+intel,checksum = <0x8e38731>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x07000000 0x11200909 0xa5060300
+ 0x3187e308 0x01000000 0x12000000 0xd0230000
+ 0x00240000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x07000000
+ 0x00000000 0x00000000 0x08091120 0x71080000
+ 0x01000000 0xa5060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x27649db1 0x904b6445 0x6acff7e8 0xc4ac0631
+ 0x6830ec45 0x3aece98d 0x97bf40c8 0x83b8fef0
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
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+ 0xb3ceb634 0x26c2d231 0x1e509d45 0xb010dc16
+ 0xbaed93e6 0xffd995a5 0x2274c579 0x081c20f5
+ 0x0e890545 0x9bf20a67 0x534d1668 0xbe0d8a9e
+ 0xe6a3b6a6 0xa19826e8 0x8c369600 0x9b00d171
+ 0xdec22ff7 0x0de50b44 0x4ca2d735 0xe9142307
+ 0xb2d75e8f 0x74018651 0x8a93b3dc 0x679f8926
+ 0xf216f6dc 0xaebc58e5 0x820b6760 0x6e49feb6
+ 0x3ad58a8f 0x62ab576e 0x31829e46 0xb1a2bd35
+ 0xd3db9735 0x248c8e9a 0x8db52fa6 0x8b65b2de
+ 0xebfee08e 0x0d2bdaa1 0xb3d9a282 0xde361f30
+ 0xc121c45c 0x12cdcb27 0x8d7ab875 0xcefac8dc
+ 0x573f8424 0x783fb263 0xbc2d8f2f 0x04f05791
+ 0xa880912a 0x22042163 0xb7891d1d 0x27a3b82a
+ 0x70e35ee9 0xb0b74dc8 0x72b51ef4 0xc074941c
+ 0xeb765569 0x8fba1f5b 0x044aaefa 0xc0db48d0
+ 0x31bed72a 0x7f5ad220 0x132e1da0 0x4cc7e7b5
+ 0x145a80c6 0x39367173 0x0689d163 0x96822f9a
+ >;
--- /dev/null
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ * * Neither the name of Intel Corporation nor the names of its contributors may
+ * be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x10>;
+intel,date-code = <0x2202012>;
+intel,processor-signature = <0x306a8>;
+intel,checksum = <0xe44a4ef2>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x12>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+ 0x01000000 0x10000000 0x12202002 0xa8060300
+ 0xf24e4ae4 0x01000000 0x12000000 0xd0270000
+ 0x00280000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0xa1000000 0x01000200 0x10000000
+ 0x00000000 0x00000000 0x17021220 0xe1090000
+ 0x01000000 0xa8060300 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000
+ 0x493d401b 0x64106cf1 0x0ffc7f0f 0x9b4b97f6
+ 0xb8fab9c2 0x46353316 0x0247d91b 0x3c36c361
+ 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
+ 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
+ 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
+ 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
+ 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
+ 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
+ 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
+ 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
+ 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
+ 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
+ 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
+ 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
+ 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
+ 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
+ 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
+ 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
+ 0x11000000 0xe5ffd18e 0x9c10c032 0xef097758
+ 0x5b44fb3b 0xabbc6973 0xb040312f 0x6267ab0a
+ 0x35ef3655 0x694c0da7 0x6eaf94db 0x293feb5f
+ 0x225a62bf 0x550edd27 0x8e4da670 0x9afcd29b
+ 0x62ad52f1 0xddcdc6fb 0x059e156b 0x9472a491
+ 0x20d8e6fb 0x7041822d 0x5af9c518 0x7e6c342f
+ 0xb113a311 0xdec46650 0x91c8a91c 0x157cde4d
+ 0xec563d5d 0x92470d0e 0x373c488c 0xf18a8f84
+ 0x757fa8ad 0xf8959ce7 0x95e1e3c9 0x47347f30
+ 0xfbd6e4a3 0x18c2f2e2 0xb6c6eb68 0xd2a81838
+ 0xa44964bb 0x36893d55 0x0b411d47 0x5addcf15
+ 0x47584269 0x972c08b3 0x0935b300 0xec7d36a7
+ 0x1c373823 0x487626be 0xacfecd64 0x6688c83c
+ 0xb96f01f9 0x2b6c9719 0x97e955da 0xc4f3b25a
+ 0xfcf12050 0x961bc5be 0x53ebb1e4 0xdc7deaa3
+ 0x3b86819a 0x7c498a21 0x129bc1b6 0x2aa5c324
+ 0x6fb58020 0x0c8e24a8 0xb7c1f0cf 0x37287581
+ 0xf417e311 0x5fd7b8cb 0xe615c56a 0x6a6c6aa7
+ 0x46c97d63 0xcc71adee 0x239b7483 0xea6750f7
+ 0x17bae7c2 0xbf4de5e1 0x6c37a1e0 0x314fc762
+ 0x68bffc94 0x4069875c 0x60d3a593 0x3a923495
+ 0x70f7a899 0xc959db6f 0xfd440374 0x0be4f668
+ 0xc15b74e9 0x9eb15fc7 0x04dc5939 0x1c2d0faf
+ 0x8ca378c9 0x15aaae90 0x2c53e471 0x2ada3977
+ 0x750d6d3b 0xd3e27cdd 0xf63ece4c 0xcbbf9463
+ 0xf0b26aad 0xacc9dc7e 0xcb2131eb 0xc2da14bc
+ 0x01b57719 0x901319e9 0x86b16d25 0x89fe5e27
+ 0xfa3135cd 0x51ebcf8e 0x91b36807 0x6efb87a1
+ 0xbe05489f 0x0461f6c7 0x4f1ddb59 0x007a7e35
+ 0xdde5c360 0xf137a520 0x153d9512 0xebe49940
+ 0xb81727b3 0xdff04ada 0x504811d5 0x6192a2a1
+ 0x418ad287 0x44278f0f 0xc8d70fcc 0x5d5953ca
+ 0xeca4ae03 0xb507f886 0x90a6726b 0xec2c60b6
+ 0xfe003923 0x8cd52bb2 0x87397bbb 0xec98c514
+ 0x28501352 0xd5518d70 0xf3258a19 0x15e4e0f4
+ 0xae272618 0x164ece6f 0x19b5449c 0x2717cf2a
+ 0xffee98cf 0xf18d6c04 0xffb6f744 0x5ed2cb50
+ 0x9421a65a 0x76150be7 0x9689d9eb 0xe6ce395b
+ 0xa5857737 0xe51b5a0f 0x5cc95766 0x365a6f04
+ 0xee8a6d1b 0x219da3e7 0x81004946 0xce4f00f9
+ 0x852eebd0 0x3a39b164 0x96863ddd 0x43b46d69
+ 0x064e138b 0x2ac312a3 0xe7eac082 0xb958803f
+ 0x3138940e 0x4c1d5d99 0x49e9ed02 0xeb3a904e
+ 0x14c2ce82 0x8449493e 0x3cdd6dbf 0xdddb592e
+ 0xaae39fca 0x163c6e65 0xee5a0e52 0xae8c2f8c
+ 0x07fd1416 0x406bd0dc 0x52811c06 0x18316363
+ 0xf954d2eb 0xa8ec83dc 0xe24996e9 0xc92af45f
+ 0x5a73f1d0 0xf5b9948f 0xa6960f5f 0xef3d1266
+ 0x97ac2b43 0x20ce72fe 0x0d774f96 0x29653967
+ 0xca765fe6 0x470ded7f 0x42a9b87e 0x3c9cfb36
+ 0xcd9354db 0x0f2fa889 0xb35e5c71 0xc3da1e0d
+ 0x85f9bfd0 0x1afc94a1 0xf05524d4 0x2b2138ef
+ 0x3c77b905 0x55d26a06 0xcc3a045d 0xad05a556
+ 0xef80f5b7 0x3ca6e8de 0xc40df9e4 0xdc5bdd8a
+ 0xdee9349d 0x258ecbc9 0xa29faf0e 0xf41daab4
+ 0x47af938b 0x6a6a1cf1 0x7a3d2f4a 0x11ede796
+ 0x61f25722 0x6864a35e 0xb4d96fae 0xcdc6a722
+ 0xce64615d 0xef56b252 0x0b89020b 0x2a1ac24c
+ 0x582c3283 0x124f274e 0xf6a58fdc 0x847c262d
+ 0x31517f9b 0x8cd34984 0xc60f7204 0xa94875c1
+ 0x12abf4e6 0xfbdd2b29 0xdb51a1c1 0xb10f9ec9
+ 0xc52b5d3c 0xfa5f75c4 0xb63c6fef 0x8ccd4fe0
+ 0x74b6cc11 0x013babd9 0x0bc30209 0xb1597dcf
+ 0xbda5ac76 0x0371d13a 0x67252505 0xf3081369
+ 0x0d7a4e53 0x25f89a9f 0xd0d9e53f 0xa25d897d
+ 0x822f83e0 0x3008eae6 0x428d3320 0x9890d235
+ 0xfec38910 0x56c87e21 0x7f7f594b 0xdf46866a
+ 0x34a34b40 0x0987267e 0xb47033d1 0x331f5d40
+ 0x935a4ec5 0xab480f95 0x1803d8e7 0x00e2e693
+ 0xab18b053 0x1cf706dd 0x7dda5849 0xb422e2e3
+ 0xba5fd0f3 0x3aee2ce1 0x33b21147 0x5fdec0d7
+ 0xd509d289 0x61187bf4 0xf7687684 0x48edbc90
+ 0x519dcd0b 0x77f026eb 0xc52eb470 0x1d4dd497
+ 0x2fa69c9c 0x8fcfef0d 0x1ed8a0b3 0x9312d199
+ 0x596b55be 0xc8c68e56 0x6aa8dc28 0x3100ec70
+ 0x737bfff7 0x40e51f14 0x695baf1f 0xad786740
+ 0x6278b108 0xcd066fb0 0x74f9d22c 0x9dd7d6f6
+ 0xc9d8d081 0xb82f32ae 0x797beeed 0xa34ce8dd
+ 0xd57ad56e 0xa4bec19f 0xe2cc7268 0xd2b85f64
+ 0x4faf835d 0xda6f3933 0x28397cd3 0x010b5a17
+ 0x6d904bfb 0x26fc2b26 0xdc7b440c 0x4e985f16
+ 0x92fb8abe 0xab8d7b77 0xb906004f 0xb0bdac98
+ 0xee64230b 0xe768ebf6 0x3c96a534 0x4e2aa084
+ 0x5f4c5c4a 0x7bff964e 0x4b4fdde3 0xfc36550b
+ 0xe90220be 0x0056c3d4 0x65599751 0x00c71265
+ 0x83011ea4 0x5bd8113f 0x616bc4ab 0xcdbbfdab
+ 0x187abde6 0xcb0b2059 0x24244c94 0xa05cac8b
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+ 0x1c256625 0x841f4379 0x782edb54 0x6a70674d
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+ 0xc045ffb0 0xd94e8bbf 0xf7ff3edc 0xb1d3aab5
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+ 0xc355e1f5 0xdabc3f4b 0x3a3925e8 0xffc15e96
+ 0xd37cf717 0xbd580830 0x9527f96c 0x91b1119b
+ 0x527baf62 0xdcd8cb14 0xceff6ef8 0x7a64b27d
+ 0xc2bced42 0x62693867 0x171d7869 0x82a502af
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+ 0x4277692e 0x8bd2a7e8 0x2ced9478 0xd6d0958f
+ 0x1f11c590 0x64eea64e 0xfd0d9181 0xfe337731
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+ 0x6e6f5cf0 0x99ed610b 0x1c9c6591 0xb5b9e932
+ 0x1881f045 0x4a07d22c 0x2534671a 0xf98db0e6
+ 0x3eecedcc 0x03d88a38 0x473f8803 0x0e964e29
+ 0xe7865109 0x067ce3a2 0xb67ea547 0xc9478d11
+ 0x77824680 0xe44e870b 0x26409f76 0xf56325e4
+ 0x83850a25 0x5778bde0 0xeccc9cbe 0x2b2a510c
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+ 0xc63259df 0x6138534e 0xb365098e 0x9063c5e5
+ 0x45457621 0x80a16d60 0xd8ace6a1 0xaf8e5612
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+ 0xfa4642cf 0xe995b648 0x678dfc40 0xd4ee70c9
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+ 0x3185cd83 0x17fd5de8 0x0eb47a60 0x8b390214
+ 0x813d2606 0xa98680cf 0xe1320b2c 0xb1cff298
+ 0x55954a20 0x2832306f 0x022e5c5a 0x248ace30
+ 0x12fdb8ef 0xa1ccd483 0x46722ba6 0x383957a3
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+ 0x79a559b9 0x297a6cfc 0x9b80d725 0x231980df
+ 0x5aba4182 0x6b8930ed 0xfad6b3bf 0x03b99393
+ 0x2ce7b19b 0xd12071f4 0x4c2d0204 0x54833fe9
+ 0x1c8d0433 0xb32e9724 0x02a273bf 0xc52a9d5a
+ 0x62aa1fa6 0x68ca34ad 0x1ac94c91 0x1794e58d
+ 0xa74691ef 0x0e22c1d3 0x66be923f 0x6f6f2c45
+ 0x15ce79a4 0x3b8c9c40 0xa11ff2f9 0xb18f0e8a
+ 0x1e0763e8 0xab472e97 0xd011b9c7 0x7f4cd77e
+ 0x60291b08 0xfc4746db 0x1101cb2f 0x7127e03e
+ 0x39dd8454 0x9e18e09b 0x449c71ba 0xc1106522
+ 0xee38c53b 0x8e30f2a1 0x30a5c398 0xbde9c623
+ 0x49ff1078 0x36360091 0x2b797c99 0x553ff25a
+ 0x063174e2 0xcd5fb064 0xbaf1c003 0xbbbba060
+ 0x9e7bd54a 0xe3bb944c 0xa7586ca4 0x4586a706
+ 0x5bd43e12 0x9139b258 0x5962b23e 0xb20799b8
+ 0x23ef9a21 0xb505a156 0xed51d1ae 0x82dced20
+ 0xfed14015 0xe50de153 0xcb1de201 0x20407156
+ 0x6e6c8c9f 0x4e33f0f7 0xb61006ea 0x81bcca2d
+ 0x8fd94695 0x576fe5c7 0x074ff2db 0xd707ccf4
+ 0x581503ca 0xfcc1c71b 0xcfc21805 0xcb8251a8
+ 0x69361b9a 0x14ec2bbe 0x2df3d3f6 0xa5e66081
+ 0xc5c70b23 0x5dfa028b 0x22338ffa 0x1932168a
+ 0x11a0ed71 0xf676d717 0x823b48d7 0xe02bc37e
+ 0xfc624cac 0x03795ade 0x845ff149 0x5b657ed4
+ 0xbe434a2e 0x8a77afde 0x3615b39d 0xba7200d9
+ 0x674e4541 0x12f91c65 0x694cb6ab 0x22e78146
+ 0x8f574161 0x58f35068 0xce5b6f43 0xd1f0f21e
+ 0x1be73d35 0x7b2dd03f 0x39bf4987 0xd9a00a8b
+ 0xa1285004 0x64b6871e 0xee7377af 0x51d239c8
+ 0x54521a4e 0xcb661f19 0xf26dc3a8 0x8772cda3
+ 0x2c827fa9 0x16f8f76f 0x1de27a89 0xf8b4a070
+ 0xab4243b4 0x2c910203 0x1fc663ad 0xe310c2a3
+ 0x9476000d 0x11e66913 0x346d42a8 0xa513fd81
+ 0xfc260d0f 0x54c7995a 0x228585bc 0xefc0dbb0
+ 0xb9999ca4 0x7dfc9ec2 0x1556bde4 0x2749b83f
+ 0x753da831 0x5d415b40 0x763debe4 0x94a2d4df
+ 0xcc560707 0x08a3de8d 0x7d9f0997 0xe3ff555e
+ 0xa8d05131 0xc75a1e9c 0xd696df91 0x633551a7
+ 0x7ead2980 0x6c8b10b9 0x2b97f758 0xa785048f
+ 0x744ba0dc 0xd350342d 0x6dbdccaa 0x10a5e224
+ 0x0963176d 0x71a4325c 0xa9bfeca5 0x73c90b16
+ 0x5f486277 0xc897525a 0x57a8234d 0x78a73eeb
+ 0x2640604e 0x1598efd9 0x135cb408 0x486bd6d3
+ 0xef98ab1b 0x0ce2744c 0x6a690e5d 0xa65e3af1
+ 0x5263f69d 0x10feb14e 0xd857d93a 0x94d52946
+ 0x52162f56 0xe72a0b7d 0x3e7d7b23 0xdff4b663
+ 0xcbad0105 0x4886da29 0x7d5521d0 0xa37ad7b6
+ 0xe4e79a68 0x4c6cc715 0xbb746a87 0x0a222aa2
+ 0xcff26451 0xe5b51d1a 0xd786658d 0x0edc8ddc
+ 0x95a91b59 0x2b7b0dd7 0xc4003ca8 0xa90e574b
+ 0xf6d1b6c5 0x0880fcaa 0xda31fd31 0x5e2c3099
+ 0x9e9cf801 0x069347b4 0x66215bcc 0x8698d9cc
+ 0x5d53b7ce 0x3b0a3025 0x1765a598 0xba1f4f29
+ 0xa6017b4a 0x1db6bb22 0xd9b63caf 0x531e2601
+ 0x24fa819b 0x8ab091a2 0xbbc3b96a 0x6d4e061d
+ 0x5f7b1d3a 0x13fc2925 0x564b9a06 0x2b0d7a90
+ 0x933a10c7 0x8aa5e38a 0x9b79b254 0x9444c3c2
+ 0xd737212d 0xb13f74df 0x7193f8c1 0xa95f42de
+ 0x6c5a39de 0xf1263eb0 0x57c322ea 0x829cf7e7
+ 0xf8c58a2e 0x2408ad3a 0xe05fa2b7 0xf61c2132
+ 0x47bcb102 0x167f4eb3 0x6a9ca49a 0x03c76439
+ 0x69fa64cc 0xd715eab1 0x26b9ff58 0x65a0d362
+ 0x168ed37e 0x1c4f3752 0xd4e7d4de 0x26e7865d
+ 0xfbd25786 0x347be5c6 0xb610ff32 0xdae6720f
+ 0xa01ff608 0x4a093466 0x7dce182b 0x5eb3cc1e
+ 0xadd542b4 0xfff308b2 0x9deaf2fb 0xd6fa9bac
+ 0x7f1729b9 0x54ae192c 0x85e8e337 0x840f4bfc
+ 0x566993d1 0x2cf2af63 0xf86cbf7b 0xa78e4aa1
+ 0x11806adc 0x06070f3d 0xa833c724 0x3ffef088
+ 0x78febf93 0x2cf6ae38 0x8c4d8867 0x485a2845
+ 0x003a5def 0xe8d1b155 0xcb675ca8 0xcf4fec75
+ 0xb7fe3198 0xf5da0890 0x9f1599b4 0xb952a34e
+ 0x7f1bc151 0x362e7bbb 0x063507a0 0x99c65de4
+ 0xd5130eb3 0x8613ee0b 0xfd6a8987 0x01c85a32
+ 0xed25a8ce 0x3e81114d 0x3f96d0be 0xfa892912
+ 0xb8ab3d94 0x7f10a909 0xe20ebd7e 0x30e900b7
+ 0x05b0d117 0x423ee599 0xd09dacd3 0xd385eb38
+ 0xa0839eee 0x4f29f80c 0x7f253d6e 0xbc757a72
+ 0x326c615c 0x43e0c8e2 0x21771593 0xa71e6072
+ 0xf355b109 0xf2852219 0x9a6ab7b6 0x9b1c39ad
+ 0x2edb942f 0x51234e78 0xbbe44b02 0x9078446a
+ 0x1ff97b31 0xb2967297 0x5f1267ac 0xf8ccd029
+ 0x846ccba2 0x3a2a8297 0xf60c1eae 0xd8b7a467
+ 0x517e2f1f 0xe0087865 0x2a952fa4 0x75963d8d
+ 0x1bb14788 0x1375edb3 0x941303f7 0x6738a9c9
+ 0xe3c99502 0x5f42b5ec 0xb53339d3 0x65896cac
+ 0x8d992623 0x8b09fdc1 0x47e71464 0xc09733fb
+ 0xfa8cfbfe 0x898ba57d 0xe74ca247 0x4fc21f9f
+ 0xc880e39a 0x973ab5b7 0x78628ad6 0x8a6fe2a0
+ 0x92a5a189 0x7a6ff475 0x7db81d10 0x81deea09
+ 0xa4ff44fd 0x056e383e 0x7cd47b4c 0x2182a401
+ 0xd0c4ce01 0xeb313665 0x8bbb4e07 0xbb4d4a64
+ 0x15fe41cb 0x53a267ce 0x8ee4ae7c 0x01678630
+ 0xda477daf 0x7ee74db4 0xf6e9228b 0x06c57aef
+ 0x5b9c8e80 0x1e05611b 0x26682707 0x7111591a
+ 0x7646cb3b 0x20f2d117 0x4dae44a9 0x395871da
+ 0x54e6172c 0x4ab90f71 0x65209536 0xb3b57c85
+ 0x11d10b0b 0xc9e50256 0x47521f5a 0x4416012f
+ 0x6d8042b6 0x454542fa 0x77f0fea3 0xce983a27
+ 0x40f74a4e 0xabc2d476 0xcd6a647d 0xca633336
+ 0xeb7fa467 0x4b14425f 0xd7abae15 0xb9652306
+ 0x990b3a98 0x03e6f53a 0xa5f3ec3c 0xb40c953f
+ 0x5cd8470a 0xbf93da01 0x89a52e28 0x5984bd42
+ 0xe9d93e95 0xa3b67bbf 0x099ff7cf 0x07b80086
+ 0x20cdf1cb 0xcfbbdb2e 0xeb0da53d 0x33b82f36
+ 0x28fb9aca 0x013bb5b7 0xcfbfefea 0x7f4400d1
+ 0xd3ad108f 0xe32556f3 0xa9e77e41 0x92955338
+ 0x3d102663 0x63bde93f 0xbbb464c4 0xcc1ff27f
+ 0x7968d83b 0xca32b52d 0x1d4102ff 0x84cfd695
+ 0x8303a6d3 0xc6f8ba69 0xdd78d4ef 0x98b195af
+ 0x50f92a15 0x2066c503 0x61281597 0x5d0197b7
+ 0x59e6f0be 0x02423dd6 0x9b4d27af 0xb2a0755d
+ 0x72f2eb4e 0xdb5aa819 0xddb42e82 0x9688712a
+ 0xb430e384 0x6484e439 0x44f68d17 0x195c6382
+ 0xddee2db1 0xd9af2e18 0x7fbd30d6 0x2ac223db
+ 0x0d3bd809 0xec982530 0x1a41d13f 0xef2849a8
+ 0x9c233021 0xc074a29c 0xe7b8f28f 0xd0adf47f
+ 0x23cdf70d 0x6795e85d 0x1168d6ea 0x3c8bb4c7
+ 0xad1d00c9 0xf3eeb5d0 0x2f950982 0x9fbbde57
+ 0xdc733a93 0xb23e2beb 0x7dbb34af 0xf1323cff
+ 0xf6c9a9bc 0xf69900a6 0x9447ab0b 0xf03e55fa
+ 0x2816479b 0x487e507e 0x494087fb 0x0601d1ef
+ 0x27c86510 0x6a14691a 0xb78886de 0xe89e8c84
+ 0xf2cd073c 0x09144b70 0xa82227a5 0x82f88828
+ 0x71f7e10a 0x6c2b46b6 0xf813fe7d 0xf76d2602
+ 0x044d5543 0x9e1b6a76 0x967ad7b5 0xe803b0a7
+ 0x01e03dd9 0x6d5c94d8 0x112357c8 0x8e0bfe12
+ 0xcc8c7461 0xfbc1c562 0x9838886c 0xa16c46a7
+ 0x020631ad 0x70fb29ff 0x5f5f1795 0x07a762e8
+ 0x3467aa2b 0xd396d1d7 0xa12aaf4c 0xd3c13b6b
+ 0xf158d7dd 0x17b1317a 0xd847a91d 0x7612ab8e
+ >;
cpu@0 {
device_type = "cpu";
- compatible = "cpu-x86";
+ compatible = "cpu-qemu";
reg = <0>;
intel,apic-id = <0>;
};
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cpu-x86";
- reg = <1>;
- intel,apic-id = <1>;
- };
};
tsc-timer {
cpu@0 {
device_type = "cpu";
- compatible = "cpu-x86";
+ compatible = "cpu-qemu";
reg = <0>;
intel,apic-id = <0>;
};
-
- cpu@1 {
- device_type = "cpu";
- compatible = "cpu-x86";
- reg = <1>;
- intel,apic-id = <1>;
- };
};
tsc-timer {
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
#define GPIO_ROUT 0xb8
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */
+#define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */
#define LPC_EN 0x82 /* LPC IF Enables Register */
#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
+#define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */
+#define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */
+#define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */
+#define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */
+#define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */
+#define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */
+#define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */
+#define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */
/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: Intel
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+ struct fsp_cfg_common common;
+ struct upd_region fsp_upd;
+};
+
+struct fspinit_rtbuf {
+ struct common_buf common; /* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
#include <linux/linkage.h>
+/*
+ * FSP common configuration structure.
+ * This needs to be included in the platform-specific struct fsp_config_data.
+ */
+struct fsp_cfg_common {
+ struct fsp_header *fsp_hdr;
+ u32 stack_top;
+ u32 boot_mode;
+};
+
/*
* FspInit continuation function prototype.
* Control will be returned to this callback function after FspInit API call.
* Stack top pointer used by the bootloader. The new stack frame will be
* set up at this location after FspInit API call.
*/
- u32 *stack_top;
+ u32 stack_top;
u32 boot_mode; /* Current system boot mode */
void *upd_data; /* User platform configuraiton data region */
u32 reserved[7]; /* Reserved */
+++ /dev/null
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: Intel
- */
-
-#ifndef __FSP_PLATFORM_H__
-#define __FSP_PLATFORM_H__
-
-struct fspinit_rtbuf {
- struct common_buf common; /* FSP common runtime data structure */
-};
-
-#endif
#include "fsp_ffs.h"
#include "fsp_api.h"
#include "fsp_hob.h"
-#include "fsp_platform.h"
#include "fsp_infoheader.h"
#include "fsp_bootmode.h"
#include <asm/arch/fsp/fsp_vpd.h>
-
-struct shared_data {
- struct fsp_header *fsp_hdr;
- u32 *stack_top;
- struct upd_region fsp_upd;
-};
+#include <asm/arch/fsp/fsp_configs.h>
#define FSP_LOWMEM_BASE 0x100000UL
#define FSP_HIGHMEM_BASE 0x100000000ULL
/**
* FSP Continuation function
*
- * @shared_data: Shared data base before stack migration
* @status: Always 0
* @hob_list: HOB list pointer
*
* @retval: Never returns
*/
-void fsp_continue(struct shared_data *shared_data, u32 status,
- void *hob_list);
+void fsp_continue(u32 status, void *hob_list);
/**
* Find FSP header offset in FSP image
void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
/**
- * This function overrides the default configurations in the UPD data region.
+ * This function overrides the default configurations of FSP.
*
- * @fsp_upd: A pointer to the upd_region data strcture
+ * @config: A pointer to the FSP configuration data structure
+ * @rt_buf: A pointer to the FSP runtime buffer data structure
*
* @return: None
*/
-void update_fsp_upd(struct upd_region *fsp_upd);
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf);
/**
* fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
--- /dev/null
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#define FW_CONTROL_PORT 0x510
+#define FW_DATA_PORT 0x511
+#define FW_DMA_PORT_LOW 0x514
+#define FW_DMA_PORT_HIGH 0x518
+
+enum qemu_fwcfg_items {
+ FW_CFG_SIGNATURE = 0x00,
+ FW_CFG_ID = 0x01,
+ FW_CFG_UUID = 0x02,
+ FW_CFG_RAM_SIZE = 0x03,
+ FW_CFG_NOGRAPHIC = 0x04,
+ FW_CFG_NB_CPUS = 0x05,
+ FW_CFG_MACHINE_ID = 0x06,
+ FW_CFG_KERNEL_ADDR = 0x07,
+ FW_CFG_KERNEL_SIZE = 0x08,
+ FW_CFG_KERNEL_CMDLINE = 0x09,
+ FW_CFG_INITRD_ADDR = 0x0a,
+ FW_CFG_INITRD_SIZE = 0x0b,
+ FW_CFG_BOOT_DEVICE = 0x0c,
+ FW_CFG_NUMA = 0x0d,
+ FW_CFG_BOOT_MENU = 0x0e,
+ FW_CFG_MAX_CPUS = 0x0f,
+ FW_CFG_KERNEL_ENTRY = 0x10,
+ FW_CFG_KERNEL_DATA = 0x11,
+ FW_CFG_INITRD_DATA = 0x12,
+ FW_CFG_CMDLINE_ADDR = 0x13,
+ FW_CFG_CMDLINE_SIZE = 0x14,
+ FW_CFG_CMDLINE_DATA = 0x15,
+ FW_CFG_SETUP_ADDR = 0x16,
+ FW_CFG_SETUP_SIZE = 0x17,
+ FW_CFG_SETUP_DATA = 0x18,
+ FW_CFG_FILE_DIR = 0x19,
+ FW_CFG_FILE_FIRST = 0x20,
+ FW_CFG_WRITE_CHANNEL = 0x4000,
+ FW_CFG_ARCH_LOCAL = 0x8000,
+ FW_CFG_INVALID = 0xffff,
+};
+
+#define FW_CFG_FILE_SLOTS 0x10
+#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH 56
+
+#define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR (1 << 0)
+#define FW_CFG_DMA_READ (1 << 1)
+#define FW_CFG_DMA_SKIP (1 << 2)
+#define FW_CFG_DMA_SELECT (1 << 3)
+
+#define FW_CFG_DMA_ENABLED (1 << 1)
+
+struct fw_cfg_file {
+ __be32 size;
+ __be16 select;
+ __be16 reserved;
+ char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_cfg_files {
+ __be32 count;
+ struct fw_cfg_file files[];
+};
+
+struct fw_cfg_dma_access {
+ __be32 control;
+ __be32 length;
+ __be64 address;
+};
+
+/**
+ * Initialize QEMU fw_cfg interface
+ */
+void qemu_fwcfg_init(void);
+
+/**
+ * Get system cpu number
+ *
+ * @return: cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+#endif
printf("---|----------|-----------|------|-");
printf("------------------------------------------\n");
while (!end_of_hob(hdr)) {
- printf("%-2d | %08x | ", i, (unsigned int)hdr);
+ printf("%02x | %08x | ", i, (unsigned int)hdr);
type = hdr->type;
if (type == HOB_TYPE_UNUSED)
desc = "*Unused*";
desc = hob_type[type];
else
desc = "*Invalid*";
- printf("%-9s | %-4d | ", desc, hdr->len);
+ printf("%-9s | %04x | ", desc, hdr->len);
if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC ||
type == HOB_TYPE_GUID_EXT) {
return (struct fsp_header *)fsp;
}
-void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
+void fsp_continue(u32 status, void *hob_list)
{
- u32 stack_len;
- u32 stack_base;
- u32 stack_top;
-
post_code(POST_MRC);
assert(status == 0);
- /* Get the migrated stack in normal memory */
- stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
- assert(stack_base != 0);
- stack_top = stack_base + stack_len - sizeof(u32);
-
- /*
- * Old stack base is stored at the very end of the stack top,
- * use it to calculate the migrated shared data base
- */
- shared_data = (struct shared_data *)(stack_base +
- ((u32)shared_data - *(u32 *)stack_top));
-
/* The boot loader main function entry */
fsp_init_done(hob_list);
}
void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
{
- struct shared_data shared_data;
+ struct fsp_config_data config_data;
fsp_init_f init;
struct fsp_init_params params;
struct fspinit_rtbuf rt_buf;
- struct vpd_region *fsp_vpd;
struct fsp_header *fsp_hdr;
struct fsp_init_params *params_ptr;
+#ifdef CONFIG_FSP_USE_UPD
+ struct vpd_region *fsp_vpd;
struct upd_region *fsp_upd;
+#endif
#ifdef CONFIG_DEBUG_UART
setup_early_uart();
panic("Invalid FSP header");
}
- fsp_upd = &shared_data.fsp_upd;
- memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
-
- /* Reserve a gap in stack top */
- rt_buf.common.stack_top = (u32 *)stack_top - 32;
- rt_buf.common.boot_mode = boot_mode;
- rt_buf.common.upd_data = fsp_upd;
+ config_data.common.fsp_hdr = fsp_hdr;
+ config_data.common.stack_top = stack_top;
+ config_data.common.boot_mode = boot_mode;
+#ifdef CONFIG_FSP_USE_UPD
/* Get VPD region start */
fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
fsp_hdr->cfg_region_off);
/* Verify the VPD data region is valid */
assert(fsp_vpd->sign == VPD_IMAGE_ID);
+ fsp_upd = &config_data.fsp_upd;
+
/* Copy default data from Flash */
memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
sizeof(struct upd_region));
/* Verify the UPD data region is valid */
assert(fsp_upd->terminator == UPD_TERMINATOR);
+#endif
- /* Override any UPD setting if required */
- update_fsp_upd(fsp_upd);
+ memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
+
+ /* Override any configuration if required */
+ update_fsp_configs(&config_data, &rt_buf);
memset(¶ms, 0, sizeof(struct fsp_init_params));
params.nvs_buf = nvs_buf;
init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
params_ptr = ¶ms;
- shared_data.fsp_hdr = fsp_hdr;
- shared_data.stack_top = (u32 *)stack_top;
-
post_code(POST_PRE_MRC);
/* Load GDT for FSP */
setup_fsp_gdt();
/*
- * Use ASM code to ensure the register value in EAX & ECX
- * will be passed into BlContinuationFunc
+ * Use ASM code to ensure the register value in EAX & EDX
+ * will be passed into fsp_continue
*/
asm volatile (
"pushl %0;"
"call *%%eax;"
".global asm_continuation;"
"asm_continuation:;"
- "movl %%ebx, %%eax;" /* shared_data */
- "movl 4(%%esp), %%edx;" /* status */
- "movl 8(%%esp), %%ecx;" /* hob_list */
+ "movl 4(%%esp), %%eax;" /* status */
+ "movl 8(%%esp), %%edx;" /* hob_list */
"jmp fsp_continue;"
- : : "m"(params_ptr), "a"(init), "b"(&shared_data)
+ : : "m"(params_ptr), "a"(init)
);
/*
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_INTEL_ME
select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR
If you want to check both consoles, use '-serial stdio'.
Multicore is also supported by QEMU via '-smp n' where n is the number of cores
-to instantiate. Currently the default U-Boot built for QEMU supports 2 cores.
-In order to support more cores, you need add additional cpu nodes in the device
-tree and change CONFIG_MAX_CPUS accordingly.
+to instantiate. Note, the maximum supported CPU number in QEMU is 255.
+
+The fw_cfg interface in QEMU also provides information about kernel data, initrd,
+command-line arguments and more. U-Boot supports directly accessing these informtion
+from fw_cfg interface, this saves the time of loading them from hard disk or
+network again, through emulated devices. To use it , simply providing them in
+QEMU command line:
+
+$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
+ -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
+
+Note: -initrd and -smp are both optional
+
+Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+
+ => qfw
+qfw - QEMU firmware interface
+
+Usage:
+qfw <command>
+ - list : print firmware(s) currently loaded
+ - cpus : print online cpu number
+ - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
+
+=> qfw load
+loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
+
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
+can be used to boot the kernel:
+
+=> zboot 02000000 - 04000000 1b1ab50
CPU Microcode
-------------
#define CONFIG_HOSTNAME x86
#define CONFIG_BOOTFILE "bzImage"
#define CONFIG_LOADADDR 0x1000000
+#define CONFIG_RAMDISK_ADDR 0x4000000
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"othbootargs=acpi=off\0" \
- "ramdiskaddr=0x2000000\0" \
+ "ramdiskaddr=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
#define CONFIG_RAMBOOTCOMMAND \
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
+ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
COMPAT_COUNT,
};
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
+ COMPAT(COMPAT_INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
name = os.path.splitext(name)[0]
data = []
with open(fname) as fd:
+ license_start = False
+ license_end = False
for line in fd:
line = line.rstrip()
+ if len(line) >= 2:
+ if line[0] == '/' and line[1] == '*':
+ license_start = True
+ continue
+ if line[0] == '*' and line[1] == '/':
+ license_end = True
+ continue
+ if license_start and not license_end:
+ # Ignore blank line
+ if len(line) > 0:
+ license_text.append(line)
+ continue
# Omit anything after the last comma
words = line.split(',')[:-1]
data += [word + ',' for word in words]
projects / u-boot / commitdiff