endmenu # Boot images
+source "api/Kconfig"
+
source "common/Kconfig"
source "cmd/Kconfig"
source "lib/Kconfig"
source "test/Kconfig"
+
+source "scripts/Kconfig"
# Build targets only - this includes vmlinux, arch specific targets, clean
# targets and others. In general all targets except *config targets.
+# Additional helpers built in scripts/
+# Carefully list dependencies so we do not try to build scripts twice
+# in parallel
+PHONY += scripts
+scripts: scripts_basic include/config/auto.conf
+ $(Q)$(MAKE) $(build)=$(@)
+
ifeq ($(dot-config),1)
# Read in config
-include include/config/auto.conf
cfg: u-boot.cfg
+quiet_cmd_cfgcheck = CFGCHK $2
+cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
+ $(srctree)/scripts/config_whitelist.txt $(srctree)
+
all: $(ALL-y)
ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
@echo "===================== WARNING ======================"
@# Check that this build does not use CONFIG options that we do not
@# know about unless they are in Kconfig. All the existing CONFIG
@# options are whitelisted, so new ones should not be added.
- $(srctree)/scripts/check-config.sh u-boot.cfg \
- $(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2
+ $(call cmd,cfgcheck,u-boot.cfg)
PHONY += dtbs
dtbs: dts/dt.dtb
$(call if_changed,objcopy)
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
- $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
+ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
$(filter-out FORCE,$^) -o $@
-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
- $(if $(CONFIG_HAVE_REFCODE),refcode.bin)
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
+ $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
+ $(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE
$(call if_changed,binman)
OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
$(foreach d, spl tpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h include/license.h \
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
boot* u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
$(Q)$(MAKE) $(build)=scripts build_docproc
$(Q)$(MAKE) $(build)=doc/DocBook $@
-# Dummies...
-PHONY += prepare scripts
-prepare: ;
-scripts: ;
-
endif #ifeq ($(config-targets),1)
endif #ifeq ($(mixed-targets),1)
can be displayed via the splashscreen support or the
bmp command.
-- Do compressing for memory range:
- CONFIG_CMD_ZIP
-
- If this option is set, it would use zlib deflate method
- to compress the specified memory at its best effort.
-
- Compression support:
CONFIG_GZIP
--- /dev/null
+menu "API"
+
+config API
+ bool "Enable U-Boot API"
+ default n
+ help
+ This option enables the U-Boot API. See api/README for more information.
+
+endmenu
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
-dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
- k2l-evm.dtb \
- k2e-evm.dtb \
- k2g-evm.dtb
+dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
+ keystone-k2l-evm.dtb \
+ keystone-k2e-evm.dtb \
+ keystone-k2g-evm.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
+++ /dev/null
-/*
- * Copyright 2014 Texas Instruments, Inc.
- *
- * Keystone 2 Edison SoC specific device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-clocks {
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkpass>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3a>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- clkusb1: clkusb1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "usb1";
- reg = <0x02350004 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkhyperlink0: clkhyperlink0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-0";
- reg = <0x02350030 0xb00>, <0x02350014 0x400>;
- reg-names = "control", "domain";
- domain-id = <5>;
- };
-
- clkpcie1: clkpcie1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie1";
- reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkxge: clkxge {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "xge";
- reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-};
+++ /dev/null
-/*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
- * Keystone 2 Edison EVM device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "k2e.dtsi"
-
-/ {
- compatible = "ti,k2e-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Edison EVM";
-
- soc {
-
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-sys";
- };
-
- refclkpass: refclkpass {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-pass";
- };
-
- refclkddr3a: refclkddr3a {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3a";
- };
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x1FE80000>;
- };
- };
- };
-};
-
-&spi0 {
- status = "okay";
- nor_flash: n25q128a11@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "spi-flash";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "ok";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
+++ /dev/null
-/*
- * Device Tree Source for Keystone 2 Edison Netcp driver
- *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0 0x10000>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <528 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <544 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <896 128>;
- qalloc-by-id;
- };
- };
- };
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000
- 0x23a80000 0x23a90000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x24186000 0x100>,
- <0x24187000 0x2a0>,
- <0x24188000 0xb60>,
- <0x24186100 0x80>,
- <0x24189000 0x1000>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@24000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x24000000 0x1000000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>,
- <&dma_gbe 8>,
- <&dma_gbe 0>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 { /* ETHSS */
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-9";
- reg = <0x200000 0x900>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <896>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- port-4 {
- slave-port = <4>;
- link-interface = <2>;
- };
- port-5 {
- slave-port = <5>;
- link-interface = <2>;
- };
- port-6 {
- slave-port = <6>;
- link-interface = <2>;
- };
- port-7 {
- slave-port = <7>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <528>;
- tx-completion-queue = <530>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <529>;
- tx-completion-queue = <531>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 00];
- netcp-gbe = <&gbe1>;
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
- * Keystone 2 Edison soc device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- soc {
- /include/ "k2e-clocks.dtsi"
-
- usb: usb@2680000 {
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- dwc3@2690000 {
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- usb1_phy: usb_phy@2620750 {
- compatible = "ti,keystone-usbphy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2620750 24>;
- status = "disabled";
- };
-
- usb1: usb@25000000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x25000000 0x10000>;
- clocks = <&clkusb1>;
- clock-names = "usb";
- interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
-
- dwc3@25010000 {
- compatible = "synopsys,dwc3";
- reg = <0x25010000 0x70000>;
- interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
- usb-phy = <&usb1_phy>, <&usb1_phy>;
- };
- };
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- pcie1: pcie@21020000 {
- compatible = "ti,keystone-pcie","snps,dw-pcie";
- clocks = <&clkpcie1>;
- clock-names = "pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
- ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
- 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
-
- status = "disabled";
- device_type = "pci";
- num-lanes = <2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
- <0 0 0 2 &pcie_intc1 1>, /* INT B */
- <0 0 0 3 &pcie_intc1 2>, /* INT C */
- <0 0 0 4 &pcie_intc1 3>; /* INT D */
-
- pcie_msi_intc1: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
- };
-
- pcie_intc1: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- mdio: mdio@24200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x24200f00 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "k2e-netcp.dtsi"
- };
-};
+++ /dev/null
-/*
- * Copyright 2014 Texas Instruments, Inc.
- *
- * Keystone 2 Galileo EVM device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include "k2g.dtsi"
-
-/ {
- compatible = "ti,k2g-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Galileo EVM";
-
- chosen {
- stdout-path = &uart0;
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- phy-mode = "rgmii-id";
- };
-};
-
-&gbe0 {
- phy-handle = <ðphy0>;
-};
-
-&spi1 {
- status = "okay";
-
- spi_nor: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-flash";
- spi-max-frequency = <50000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&qspi {
- status = "okay";
-
- flash0: m25p80@0 {
- compatible = "s25fl512s","spi-flash";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- tshsl-ns = <392>;
- tsd2d-ns = <392>;
- tchsh-ns = <100>;
- tslch-ns = <100>;
- block-size = <18>;
-
-
- partition@0 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001C0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.file-system";
- reg = <0x009C0000 0x3640000>;
- };
- };
-};
-
-&mmc0 {
- status = "okay";
-};
-
-&mmc1 {
- status = "okay";
-};
+++ /dev/null
-/*
- * Device Tree Source for Keystone 2 Galileo Netcp driver
- *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-qmss: qmss@4020000 {
- compatible = "ti,keystone-navigator-qmss-l";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
- clock-names = "nss_vclk";
- ranges;
- queue-range = <0 0x80>;
- linkram0 = <0x4020000 0x7ff>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x80>;
- reg = <0x4100000 0x800>,
- <0x4040000 0x100>,
- <0x4080000 0x800>,
- <0x40c0000 0x800>;
- reg-names = "peek", "config",
- "region", "push";
- };
-
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <77 8>;
- interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
- 0 311 0xf04 0 312 0xf04 0 313 0xf04
- 0 314 0xf04 0 315 0xf04>;
- qalloc-by-id;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <112 8>;
- };
- netcp-tx {
- qrange = <5 8>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <1023 128>; /* num_desc desc_size */
- link-index = <0x400>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
- clock-names = "nss_vclk";
- ranges;
- ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x4010000 0x100>,
- <0x4011000 0x2a0>, /* 21 Tx channels */
- <0x4012000 0x400>, /* 32 Rx channels */
- <0x4010100 0x80>,
- <0x4013000 0x400>; /* 32 Rx flows */
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-
-};
-
-gbe_subsys: subsys@4200000 {
- compatible = "syscon";
- reg = <0x4200000 0x100>;
-};
-
-netcp: netcp@4000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
- clock-names = "ethss_clk";
-
- /* NetCP address range */
- ranges = <0 0x4000000 0x1000000>;
-
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>;
- ti,navigator-dma-names = "netrx0", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 {
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-2";
- syscon-subsys = <&gbe_subsys>;
- reg = <0x200100 0xe00>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <5>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <5>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <512 12>;
- tx-pool = <511 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <77>;
- tx-completion-queue = <78>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2014 Texas Instruments, Inc.
- *
- * Keystone 2 Galileo soc device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
-/ {
- model = "Texas Instruments Keystone 2 SoC";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- spi3 = &spi3;
- spi4 = &qspi;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- gic: interrupt-controller {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x0 0x02561000 0x0 0x1000>,
- <0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
- <0x0 0x02566000 0x0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,keystone","simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- uart0: serial@02530c00 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02530c00 0x100>;
- clock-names = "uart";
- interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
- };
-
- mdio: mdio@4200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
- clock-names = "fck";
- reg = <0x04200f00 0x100>;
- status = "disabled";
- bus_freq = <2500000>;
- };
-
- qspi: qspi@2940000 {
- compatible = "cadence,qspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x02940000 0x1000>,
- <0x24000000 0x4000000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
- num-cs = <4>;
- fifo-depth = <256>;
- sram-size = <256>;
- status = "disabled";
- };
-
- #include "k2g-netcp.dtsi"
-
- pmmc: pmmc@2900000 {
- compatible = "ti,power-processor";
- reg = <0x02900000 0x40000>;
- ti,lpsc_module = <1>;
- };
-
- spi0: spi@21805400 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805400 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@21805800 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805800 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@21805c00 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805C00 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi3: spi@21806000 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21806000 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mmc0: mmc@23000000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x23000000 0x400>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
- bus-width = <4>;
- ti,needs-special-reset;
- no-1-8-v;
- max-frequency = <96000000>;
- status = "disabled";
- };
-
- mmc1: mmc@23100000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x23100000 0x400>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
- bus-width = <8>;
- ti,needs-special-reset;
- ti,non-removable;
- max-frequency = <96000000>;
- status = "disabled";
- clock-names = "fck";
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
- * Keystone 2 Kepler/Hawking SoC clock nodes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-clocks {
- armpllclk: armpllclk@2620370 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkarm>;
- clock-output-names = "arm-pll-clk";
- reg = <0x02620370 4>;
- reg-names = "control";
- };
-
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkpass>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3a>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- ddr3bpllclk: ddr3bpllclk@2620368 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3b>;
- clock-output-names = "ddr-3b-pll-clk";
- reg = <0x02620368 4>;
- reg-names = "control";
- };
-
- clktsip: clktsip {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "tsip";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clksrio: clksrio {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1rstiso13>;
- clock-output-names = "srio";
- reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
- reg-names = "control", "domain";
- domain-id = <4>;
- };
-
- clkhyperlink0: clkhyperlink0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-0";
- reg = <0x02350030 0xb00>, <0x02350014 0x400>;
- reg-names = "control", "domain";
- domain-id = <5>;
- };
-
- clkgem1: clkgem1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem1";
- reg = <0x02350040 0xb00>, <0x02350024 0x400>;
- reg-names = "control", "domain";
- domain-id = <9>;
- };
-
- clkgem2: clkgem2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem2";
- reg = <0x02350044 0xb00>, <0x02350028 0x400>;
- reg-names = "control", "domain";
- domain-id = <10>;
- };
-
- clkgem3: clkgem3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem3";
- reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
- reg-names = "control", "domain";
- domain-id = <11>;
- };
-
- clkgem4: clkgem4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem4";
- reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
- reg-names = "control", "domain";
- domain-id = <12>;
- };
-
- clkgem5: clkgem5 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem5";
- reg = <0x02350050 0xb00>, <0x02350034 0x400>;
- reg-names = "control", "domain";
- domain-id = <13>;
- };
-
- clkgem6: clkgem6 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem6";
- reg = <0x02350054 0xb00>, <0x02350038 0x400>;
- reg-names = "control", "domain";
- domain-id = <14>;
- };
-
- clkgem7: clkgem7 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem7";
- reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
- reg-names = "control", "domain";
- domain-id = <15>;
- };
-
- clkddr31: clkddr31 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "ddr3-1";
- reg = <0x02350060 0xb00>, <0x02350040 0x400>;
- reg-names = "control", "domain";
- domain-id = <16>;
- };
-
- clktac: clktac {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tac";
- reg = <0x02350064 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac01: clkrac01 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac-01";
- reg = <0x02350068 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac23: clkrac23 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac-23";
- reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkfftc0: clkfftc0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-0";
- reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkfftc1: clkfftc1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-1";
- reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkfftc2: clkfftc2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-2";
- reg = <0x02350078 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc3: clkfftc3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-3";
- reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc4: clkfftc4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-4";
- reg = <0x02350080 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc5: clkfftc5 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-5";
- reg = <0x02350084 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkaif: clkaif {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "aif";
- reg = <0x02350088 0xb00>, <0x02350054 0x400>;
- reg-names = "control", "domain";
- domain-id = <21>;
- };
-
- clktcp3d0: clktcp3d0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-0";
- reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d1: clktcp3d1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-1";
- reg = <0x02350090 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d2: clktcp3d2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-2";
- reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clktcp3d3: clktcp3d3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-3";
- reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clkvcp0: clkvcp0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-0";
- reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp1: clkvcp1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-1";
- reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp2: clkvcp2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-2";
- reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp3: clkvcp3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-3";
- reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp4: clkvcp4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-4";
- reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp5: clkvcp5 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-5";
- reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp6: clkvcp6 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-6";
- reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp7: clkvcp7 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-7";
- reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkbcp: clkbcp {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "bcp";
- reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
- reg-names = "control", "domain";
- domain-id = <26>;
- };
-
- clkdxb: clkdxb {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dxb";
- reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
- reg-names = "control", "domain";
- domain-id = <27>;
- };
-
- clkhyperlink1: clkhyperlink1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-1";
- reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
- reg-names = "control", "domain";
- domain-id = <28>;
- };
-
- clkxge: clkxge {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "xge";
- reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-};
+++ /dev/null
-/*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
- * Keystone 2 Kepler/Hawking EVM device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "k2hk.dtsi"
-
-/ {
- compatible = "ti,k2hk-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
-
- soc {
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-sys";
- };
-
- refclkpass: refclkpass {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-pass";
- };
-
- refclkarm: refclkarm {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "refclk-arm";
- };
-
- refclkddr3a: refclkddr3a {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3a";
- };
-
- refclkddr3b: refclkddr3b {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3b";
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- debug1_1 {
- label = "keystone:green:debug1";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
- };
-
- debug1_2 {
- label = "keystone:red:debug1";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
- };
-
- debug2 {
- label = "keystone:blue:debug2";
- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
- };
-
- debug3 {
- label = "keystone:blue:debug3";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x1fe80000>;
- };
- };
- };
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&spi0 {
- status = "okay";
- nor_flash: n25q128a11@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "spi-flash";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "ok";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
+++ /dev/null
-/*
- * Device Tree Source for Keystone 2 Hawking Netcp driver
- *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x4000>;
- linkram0 = <0x100000 0x8000>;
- linkram1 = <0x0 0x10000>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
-
- qmgr1 {
- managed-queues = <0x2000 0x2000>;
- reg = <0x2a60000 0x20000>,
- <0x2a06400 0x400>,
- <0x2a04000 0x1000>,
- <0x2a05000 0x1000>,
- <0x23aa0000 0x20000>,
- <0x2aa0000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <8704 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <8720 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <640 9>;
- qalloc-by-id;
- };
- netcpx-tx {
- qrange = <8752 8>;
- qalloc-by-id;
- };
- };
- };
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000
- 0x23aa0000 0x23ab0000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x2004000 0x100>,
- <0x2004400 0x120>,
- <0x2004800 0x300>,
- <0x2004c00 0x120>,
- <0x2005000 0x400>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@2000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x2000000 0x100000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 22>,
- <&dma_gbe 23>,
- <&dma_gbe 8>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
- gbe@90000 { /* ETHSS */
- #address-cells = <1>;
- #size-cells = <1>;
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe";
- reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
- /* enable-ale; */
- tx-queue = <648>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <8704>;
- tx-completion-queue = <8706>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <8705>;
- tx-completion-queue = <8707>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 6f];
- netcp-gbe = <&gbe1>;
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
- * Keystone 2 Kepler/Hawking soc specific device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- soc {
- /include/ "k2hk-clocks.dtsi"
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
-
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
-
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
-
- dspgpio4: keystone_dsp_gpio@2620250 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x250>;
- };
-
- dspgpio5: keystone_dsp_gpio@2620254 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x254>;
- };
-
- dspgpio6: keystone_dsp_gpio@2620258 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x258>;
- };
-
- dspgpio7: keystone_dsp_gpio@262025c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x25c>;
- };
-
- mdio: mdio@02090300 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x02090300 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "k2hk-netcp.dtsi"
- };
-};
+++ /dev/null
-/*
- * Copyright 2013-2014 Texas Instruments, Inc.
- *
- * Keystone 2 lamarr SoC clock nodes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-clocks {
- armpllclk: armpllclk@2620370 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "arm-pll-clk";
- reg = <0x02620370 4>;
- reg-names = "control";
- };
-
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- clkdfeiqnsys: clkdfeiqnsys {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "dfe";
- reg-names = "control", "domain";
- reg = <0x02350004 0xb00>, <0x02350000 0x400>;
- domain-id = <0>;
- };
-
- clkpcie1: clkpcie1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie";
- reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <4>;
- };
-
- clkgem1: clkgem1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem1";
- reg = <0x02350040 0xb00>, <0x02350024 0x400>;
- reg-names = "control", "domain";
- domain-id = <9>;
- };
-
- clkgem2: clkgem2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem2";
- reg = <0x02350044 0xb00>, <0x02350028 0x400>;
- reg-names = "control", "domain";
- domain-id = <10>;
- };
-
- clkgem3: clkgem3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem3";
- reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
- reg-names = "control", "domain";
- domain-id = <11>;
- };
-
- clktac: clktac {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tac";
- reg = <0x02350064 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac: clkrac {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac";
- reg = <0x02350068 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkdfepd0: clkdfepd0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dfe-pd0";
- reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkfftc0: clkfftc0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-0";
- reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkosr: clkosr {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "osr";
- reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <21>;
- };
-
- clktcp3d0: clktcp3d0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-0";
- reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d1: clktcp3d1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-1";
- reg = <0x02350094 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clkvcp0: clkvcp0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-0";
- reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp1: clkvcp1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-1";
- reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp2: clkvcp2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-2";
- reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp3: clkvcp3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-3";
- reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkbcp: clkbcp {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "bcp";
- reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
- reg-names = "control", "domain";
- domain-id = <26>;
- };
-
- clkdfepd1: clkdfepd1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dfe-pd1";
- reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <27>;
- };
-
- clkfftc1: clkfftc1 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-1";
- reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
- reg-names = "control", "domain";
- domain-id = <28>;
- };
-
- clkiqnail: clkiqnail {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "iqn-ail";
- reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-
- clkuart2: clkuart2 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart2";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart3: clkuart3 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart3";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-};
+++ /dev/null
-/*
- * Copyright 2014 Texas Instruments, Inc.
- *
- * Keystone 2 Lamarr EVM device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "k2l.dtsi"
-
-/ {
- compatible = "ti,k2l-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Lamarr EVM";
-
- soc {
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-sys";
- };
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x7FE80000>;
- };
- };
- };
-};
-
-&spi0 {
- status ="okay";
- nor_flash: n25q128a11@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "spi-flash";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "ok";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
+++ /dev/null
-/*
- * Device Tree Source for Keystone 2 Lamarr Netcp driver
- *
- * Copyright 2015 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <528 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <544 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <896 128>;
- qalloc-by-id;
- };
- };
- };
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x26186000 0x100>,
- <0x26187000 0x2a0>,
- <0x26188000 0xb60>,
- <0x26186100 0x80>,
- <0x26189000 0x1000>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@26000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x26000000 0x1000000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>,
- <&dma_gbe 8>,
- <&dma_gbe 0>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 { /* ETHSS */
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-5";
- reg = <0x200000 0x900>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <896>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <528>;
- tx-completion-queue = <530>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <529>;
- tx-completion-queue = <531>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 7f];
- netcp-gbe = <&gbe1>;
- };
- };
-};
+++ /dev/null
-/*
- * Copyright 2014 Texas Instruments, Inc.
- *
- * Keystone 2 Lamarr SoC specific device tree
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
- };
-
- soc {
- /include/ "k2l-clocks.dtsi"
-
- uart2: serial@02348400 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02348400 0x100>;
- clocks = <&clkuart2>;
- interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
- };
-
- uart3: serial@02348800 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02348800 0x100>;
- clocks = <&clkuart3>;
- interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
- };
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
-
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
-
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
-
- mdio: mdio@26200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x26200f00 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "k2l-netcp.dtsi"
- };
-};
-
-&spi0 {
- ti,davinci-spi-num-cs = <5>;
-};
-
-&spi1 {
- ti,davinci-spi-num-cs = <3>;
-};
-
-&spi2 {
- ti,davinci-spi-num-cs = <5>;
- /* Pin muxed. Enabled and configured by Bootloader */
- status = "disabled";
-};
--- /dev/null
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Edison SoC specific device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clocks {
+ mainpllclk: mainpllclk@2310110 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,main-pll-clock";
+ clocks = <&refclksys>;
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
+ };
+
+ papllclk: papllclk@2620358 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclkpass>;
+ clock-output-names = "papllclk";
+ reg = <0x02620358 4>;
+ reg-names = "control";
+ };
+
+ ddr3apllclk: ddr3apllclk@2620360 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclkddr3a>;
+ clock-output-names = "ddr-3a-pll-clk";
+ reg = <0x02620360 4>;
+ reg-names = "control";
+ };
+
+ clkusb1: clkusb1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk16>;
+ clock-output-names = "usb1";
+ reg = <0x02350004 0xb00>, <0x02350000 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <0>;
+ };
+
+ clkhyperlink0: clkhyperlink0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk12>;
+ clock-output-names = "hyperlink-0";
+ reg = <0x02350030 0xb00>, <0x02350014 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <5>;
+ };
+
+ clkpcie1: clkpcie1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk12>;
+ clock-output-names = "pcie1";
+ reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <18>;
+ };
+
+ clkxge: clkxge {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "xge";
+ reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <29>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Edison EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "keystone.dtsi"
+#include "keystone-k2e.dtsi"
+
+/ {
+ compatible = "ti,k2e-evm","ti,keystone";
+ model = "Texas Instruments Keystone 2 Edison EVM";
+
+ soc {
+
+ clocks {
+ refclksys: refclksys {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "refclk-sys";
+ };
+
+ refclkpass: refclkpass {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "refclk-pass";
+ };
+
+ refclkddr3a: refclkddr3a {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "refclk-ddr3a";
+ };
+ };
+ };
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&i2c0 {
+ dtt@50 {
+ compatible = "at,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&aemif {
+ cs0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-ranges;
+ ranges;
+
+ ti,cs-chipselect = <0>;
+ /* all timings in nanoseconds */
+ ti,cs-min-turnaround-ns = <12>;
+ ti,cs-read-hold-ns = <6>;
+ ti,cs-read-strobe-ns = <23>;
+ ti,cs-read-setup-ns = <9>;
+ ti,cs-write-hold-ns = <8>;
+ ti,cs-write-strobe-ns = <23>;
+ ti,cs-write-setup-ns = <8>;
+
+ nand@0,0 {
+ compatible = "ti,keystone-nand","ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0 0x4000000
+ 1 0 0x0000100>;
+
+ ti,davinci-chipselect = <0>;
+ ti,davinci-mask-ale = <0x2000>;
+ ti,davinci-mask-cle = <0x4000>;
+ ti,davinci-mask-chipsel = <0>;
+ nand-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ nand-on-flash-bbt;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "params";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "ubifs";
+ reg = <0x180000 0x1FE80000>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+ nor_flash: n25q128a11@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "Micron,n25q128a11", "spi-flash";
+ spi-max-frequency = <54000000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "misc";
+ reg = <0x80000 0xf80000>;
+ };
+ };
+};
+
+&mdio {
+ status = "ok";
+ ethphy0: ethernet-phy@0 {
+ compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for Keystone 2 Edison Netcp driver
+ *
+ * Copyright 2015 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+qmss: qmss@2a40000 {
+ compatible = "ti,keystone-navigator-qmss";
+ dma-coherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&chipclk13>;
+ ranges;
+ queue-range = <0 0x2000>;
+ linkram0 = <0x100000 0x4000>;
+ linkram1 = <0 0x10000>;
+
+ qmgrs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ qmgr0 {
+ managed-queues = <0 0x2000>;
+ reg = <0x2a40000 0x20000>,
+ <0x2a06000 0x400>,
+ <0x2a02000 0x1000>,
+ <0x2a03000 0x1000>,
+ <0x23a80000 0x20000>,
+ <0x2a80000 0x20000>;
+ reg-names = "peek", "status", "config",
+ "region", "push", "pop";
+ };
+ };
+ queue-pools {
+ qpend {
+ qpend-0 {
+ qrange = <658 8>;
+ interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
+ };
+ qpend-1 {
+ qrange = <528 16>;
+ interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
+ 0 51 0xf04 0 52 0xf04 0 53 0xf04
+ 0 54 0xf04 0 55 0xf04 0 56 0xf04
+ 0 57 0xf04 0 58 0xf04 0 59 0xf04
+ 0 60 0xf04 0 61 0xf04 0 62 0xf04
+ 0 63 0xf04>;
+ qalloc-by-id;
+ };
+ qpend-2 {
+ qrange = <544 16>;
+ interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
+ 0 59 0xf04 0 68 0xf04 0 69 0xf04
+ 0 70 0xf04 0 71 0xf04 0 72 0xf04
+ 0 73 0xf04 0 74 0xf04 0 75 0xf04
+ 0 76 0xf04 0 77 0xf04 0 78 0xf04
+ 0 79 0xf04>;
+ };
+ };
+ general-purpose {
+ gp-0 {
+ qrange = <4000 64>;
+ };
+ netcp-tx {
+ qrange = <896 128>;
+ qalloc-by-id;
+ };
+ };
+ };
+ descriptor-regions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ region-12 {
+ id = <12>;
+ region-spec = <8192 128>; /* num_desc desc_size */
+ link-index = <0x4000>;
+ };
+ };
+}; /* qmss */
+
+knav_dmas: knav_dmas@0 {
+ compatible = "ti,keystone-navigator-dma";
+ clocks = <&papllclk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,navigator-cloud-address = <0x23a80000 0x23a90000
+ 0x23a80000 0x23a90000>;
+
+ dma_gbe: dma_gbe@0 {
+ reg = <0x24186000 0x100>,
+ <0x24187000 0x2a0>,
+ <0x24188000 0xb60>,
+ <0x24186100 0x80>,
+ <0x24189000 0x1000>;
+ reg-names = "global", "txchan", "rxchan",
+ "txsched", "rxflow";
+ };
+};
+
+netcp: netcp@24000000 {
+ reg = <0x2620110 0x8>;
+ reg-names = "efuse";
+ compatible = "ti,netcp-1.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* NetCP address range */
+ ranges = <0 0x24000000 0x1000000>;
+
+ clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
+ dma-coherent;
+
+ ti,navigator-dmas = <&dma_gbe 0>,
+ <&dma_gbe 8>,
+ <&dma_gbe 0>;
+ ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
+
+ netcp-devices {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ gbe@200000 { /* ETHSS */
+ label = "netcp-gbe";
+ compatible = "ti,netcp-gbe-9";
+ reg = <0x200000 0x900>, <0x220000 0x20000>;
+ /* enable-ale; */
+ tx-queue = <896>;
+ tx-channel = "nettx";
+
+ interfaces {
+ gbe0: interface-0 {
+ slave-port = <0>;
+ link-interface = <1>;
+ phy-handle = <ðphy0>;
+ };
+ gbe1: interface-1 {
+ slave-port = <1>;
+ link-interface = <1>;
+ phy-handle = <ðphy1>;
+ };
+ };
+
+ secondary-slave-ports {
+ port-2 {
+ slave-port = <2>;
+ link-interface = <2>;
+ };
+ port-3 {
+ slave-port = <3>;
+ link-interface = <2>;
+ };
+ port-4 {
+ slave-port = <4>;
+ link-interface = <2>;
+ };
+ port-5 {
+ slave-port = <5>;
+ link-interface = <2>;
+ };
+ port-6 {
+ slave-port = <6>;
+ link-interface = <2>;
+ };
+ port-7 {
+ slave-port = <7>;
+ link-interface = <2>;
+ };
+ };
+ };
+ };
+
+ netcp-interfaces {
+ interface-0 {
+ rx-channel = "netrx0";
+ rx-pool = <1024 12>;
+ tx-pool = <1024 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <528>;
+ tx-completion-queue = <530>;
+ efuse-mac = <1>;
+ netcp-gbe = <&gbe0>;
+
+ };
+ interface-1 {
+ rx-channel = "netrx1";
+ rx-pool = <1024 12>;
+ tx-pool = <1024 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <529>;
+ tx-completion-queue = <531>;
+ efuse-mac = <0>;
+ local-mac-address = [02 18 31 7e 3e 00];
+ netcp-gbe = <&gbe1>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Edison soc device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gic>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ soc {
+ /include/ "keystone-k2e-clocks.dtsi"
+
+ usb: usb@2680000 {
+ interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
+ dwc3@2690000 {
+ interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ usb1_phy: usb_phy@2620750 {
+ compatible = "ti,keystone-usbphy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2620750 24>;
+ status = "disabled";
+ };
+
+ usb1: usb@25000000 {
+ compatible = "ti,keystone-dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x25000000 0x10000>;
+ clocks = <&clkusb1>;
+ clock-names = "usb";
+ interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
+ ranges;
+ dma-coherent;
+ dma-ranges;
+ status = "disabled";
+
+ dwc3@25010000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x25010000 0x70000>;
+ interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
+ usb-phy = <&usb1_phy>, <&usb1_phy>;
+ };
+ };
+
+ dspgpio0: keystone_dsp_gpio@02620240 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
+
+ pcie1: pcie@21020000 {
+ compatible = "ti,keystone-pcie","snps,dw-pcie";
+ clocks = <&clkpcie1>;
+ clock-names = "pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
+ ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
+ 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
+
+ status = "disabled";
+ device_type = "pci";
+ num-lanes = <2>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
+ <0 0 0 2 &pcie_intc1 1>, /* INT B */
+ <0 0 0 3 &pcie_intc1 2>, /* INT C */
+ <0 0 0 4 &pcie_intc1 3>; /* INT D */
+
+ pcie_msi_intc1: msi-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pcie_intc1: legacy-interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ mdio: mdio@24200f00 {
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x24200f00 0x100>;
+ status = "disabled";
+ clocks = <&clkcpgmac>;
+ clock-names = "fck";
+ bus_freq = <2500000>;
+ };
+ /include/ "keystone-k2e-netcp.dtsi"
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Device Tree Source for K2G EVM
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+ compatible = "ti,k2g-evm","ti,keystone";
+ model = "Texas Instruments K2G General Purpose EVM";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&mdio {
+ status = "okay";
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ phy-mode = "rgmii-id";
+ };
+};
+
+&gbe0 {
+ phy-handle = <ðphy0>;
+};
+
+&spi1 {
+ status = "okay";
+
+ spi_nor: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "misc";
+ reg = <0x80000 0xf80000>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: m25p80@0 {
+ compatible = "s25fl512s","spi-flash";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <96000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ tshsl-ns = <392>;
+ tsd2d-ns = <392>;
+ tchsh-ns = <100>;
+ tslch-ns = <100>;
+ block-size = <18>;
+
+
+ partition@0 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00000000 0x00100000>;
+ };
+ partition@1 {
+ label = "QSPI.u-boot-env";
+ reg = <0x00100000 0x00040000>;
+ };
+ partition@2 {
+ label = "QSPI.skern";
+ reg = <0x00140000 0x0040000>;
+ };
+ partition@3 {
+ label = "QSPI.pmmc-firmware";
+ reg = <0x00180000 0x0040000>;
+ };
+ partition@4 {
+ label = "QSPI.kernel";
+ reg = <0x001C0000 0x0800000>;
+ };
+ partition@5 {
+ label = "QSPI.file-system";
+ reg = <0x009C0000 0x3640000>;
+ };
+ };
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&mmc1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source for K2G Netcp driver
+ *
+ * Copyright 2015 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+qmss: qmss@4020000 {
+ compatible = "ti,keystone-navigator-qmss-l";
+ dma-coherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
+ /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
+ clock-names = "nss_vclk";
+ ranges;
+ queue-range = <0 0x80>;
+ linkram0 = <0x4020000 0x7ff>;
+
+ qmgrs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ qmgr0 {
+ managed-queues = <0 0x80>;
+ reg = <0x4100000 0x800>,
+ <0x4040000 0x100>,
+ <0x4080000 0x800>,
+ <0x40c0000 0x800>;
+ reg-names = "peek", "config",
+ "region", "push";
+ };
+
+ };
+ queue-pools {
+ qpend {
+ qpend-0 {
+ qrange = <77 8>;
+ interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
+ 0 311 0xf04 0 312 0xf04 0 313 0xf04
+ 0 314 0xf04 0 315 0xf04>;
+ qalloc-by-id;
+ };
+ };
+ general-purpose {
+ gp-0 {
+ qrange = <112 8>;
+ };
+ netcp-tx {
+ qrange = <5 8>;
+ qalloc-by-id;
+ };
+ };
+ };
+
+ descriptor-regions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ region-12 {
+ id = <12>;
+ region-spec = <1023 128>; /* num_desc desc_size */
+ link-index = <0x400>;
+ };
+ };
+}; /* qmss */
+
+knav_dmas: knav_dmas@0 {
+ compatible = "ti,keystone-navigator-dma";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
+ /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
+ clock-names = "nss_vclk";
+ ranges;
+ ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>;
+
+ dma_gbe: dma_gbe@0 {
+ reg = <0x4010000 0x100>,
+ <0x4011000 0x2a0>, /* 21 Tx channels */
+ <0x4012000 0x400>, /* 32 Rx channels */
+ <0x4010100 0x80>,
+ <0x4013000 0x400>; /* 32 Rx flows */
+ reg-names = "global", "txchan", "rxchan",
+ "txsched", "rxflow";
+ };
+
+};
+
+gbe_subsys: subsys@4200000 {
+ compatible = "syscon";
+ reg = <0x4200000 0x100>;
+};
+
+netcp: netcp@4000000 {
+ reg = <0x2620110 0x8>;
+ reg-names = "efuse";
+ compatible = "ti,netcp-1.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
+ /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
+ clock-names = "ethss_clk";
+
+ /* NetCP address range */
+ ranges = <0 0x4000000 0x1000000>;
+
+ dma-coherent;
+
+ ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>;
+ ti,navigator-dma-names = "netrx0", "nettx";
+
+ netcp-devices {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ gbe@200000 {
+ label = "netcp-gbe";
+ compatible = "ti,netcp-gbe-2";
+ syscon-subsys = <&gbe_subsys>;
+ reg = <0x200100 0xe00>, <0x220000 0x20000>;
+ /* enable-ale; */
+ tx-queue = <5>;
+ tx-channel = "nettx";
+
+ interfaces {
+ gbe0: interface-0 {
+ slave-port = <0>;
+ link-interface = <5>;
+ };
+ };
+ };
+ };
+
+ netcp-interfaces {
+ interface-0 {
+ rx-channel = "netrx0";
+ rx-pool = <512 12>;
+ tx-pool = <511 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <77>;
+ tx-completion-queue = <78>;
+ efuse-mac = <1>;
+ netcp-gbe = <&gbe0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Device Tree Source for K2G SOC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+ model = "Texas Instruments K2G SoC";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gic>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ gic: interrupt-controller {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x02561000 0x0 0x1000>,
+ <0x0 0x02562000 0x0 0x2000>,
+ <0x0 0x02564000 0x0 0x1000>,
+ <0x0 0x02566000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ti,keystone","simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ uart0: serial@02530c00 {
+ compatible = "ns16550a";
+ current-speed = <115200>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ reg = <0x02530c00 0x100>;
+ clock-names = "uart";
+ interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ mdio: mdio@4200f00 {
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
+ /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
+ clock-names = "fck";
+ reg = <0x04200f00 0x100>;
+ status = "disabled";
+ bus_freq = <2500000>;
+ };
+
+ qspi: qspi@2940000 {
+ compatible = "cadence,qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x02940000 0x1000>,
+ <0x24000000 0x4000000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+ num-cs = <4>;
+ fifo-depth = <256>;
+ sram-size = <256>;
+ status = "disabled";
+ };
+
+ #include "keystone-k2g-netcp.dtsi"
+
+ pmmc: pmmc@2900000 {
+ compatible = "ti,power-processor";
+ reg = <0x02900000 0x40000>;
+ ti,lpsc_module = <1>;
+ };
+
+ spi0: spi@21805400 {
+ compatible = "ti,keystone-spi", "ti,dm6441-spi";
+ reg = <0x21805400 0x200>;
+ num-cs = <4>;
+ ti,davinci-spi-intr-line = <0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@21805800 {
+ compatible = "ti,keystone-spi", "ti,dm6441-spi";
+ reg = <0x21805800 0x200>;
+ num-cs = <4>;
+ ti,davinci-spi-intr-line = <0>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@21805c00 {
+ compatible = "ti,keystone-spi", "ti,dm6441-spi";
+ reg = <0x21805C00 0x200>;
+ num-cs = <4>;
+ ti,davinci-spi-intr-line = <0>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@21806000 {
+ compatible = "ti,keystone-spi", "ti,dm6441-spi";
+ reg = <0x21806000 0x200>;
+ num-cs = <4>;
+ ti,davinci-spi-intr-line = <0>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@23000000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x23000000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
+ bus-width = <4>;
+ ti,needs-special-reset;
+ no-1-8-v;
+ max-frequency = <96000000>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@23100000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x23100000 0x400>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
+ bus-width = <8>;
+ ti,needs-special-reset;
+ ti,non-removable;
+ max-frequency = <96000000>;
+ status = "disabled";
+ clock-names = "fck";
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking SoC clock nodes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clocks {
+ armpllclk: armpllclk@2620370 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclkarm>;
+ clock-output-names = "arm-pll-clk";
+ reg = <0x02620370 4>;
+ reg-names = "control";
+ };
+
+ mainpllclk: mainpllclk@2310110 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,main-pll-clock";
+ clocks = <&refclksys>;
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
+ };
+
+ papllclk: papllclk@2620358 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclkpass>;
+ clock-output-names = "papllclk";
+ reg = <0x02620358 4>;
+ reg-names = "control";
+ };
+
+ ddr3apllclk: ddr3apllclk@2620360 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclkddr3a>;
+ clock-output-names = "ddr-3a-pll-clk";
+ reg = <0x02620360 4>;
+ reg-names = "control";
+ };
+
+ ddr3bpllclk: ddr3bpllclk@2620368 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclkddr3b>;
+ clock-output-names = "ddr-3b-pll-clk";
+ reg = <0x02620368 4>;
+ reg-names = "control";
+ };
+
+ clktsip: clktsip {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk16>;
+ clock-output-names = "tsip";
+ reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <0>;
+ };
+
+ clksrio: clksrio {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1rstiso13>;
+ clock-output-names = "srio";
+ reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <4>;
+ };
+
+ clkhyperlink0: clkhyperlink0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk12>;
+ clock-output-names = "hyperlink-0";
+ reg = <0x02350030 0xb00>, <0x02350014 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <5>;
+ };
+
+ clkgem1: clkgem1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem1";
+ reg = <0x02350040 0xb00>, <0x02350024 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <9>;
+ };
+
+ clkgem2: clkgem2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem2";
+ reg = <0x02350044 0xb00>, <0x02350028 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <10>;
+ };
+
+ clkgem3: clkgem3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem3";
+ reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <11>;
+ };
+
+ clkgem4: clkgem4 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem4";
+ reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <12>;
+ };
+
+ clkgem5: clkgem5 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem5";
+ reg = <0x02350050 0xb00>, <0x02350034 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <13>;
+ };
+
+ clkgem6: clkgem6 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem6";
+ reg = <0x02350054 0xb00>, <0x02350038 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <14>;
+ };
+
+ clkgem7: clkgem7 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem7";
+ reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <15>;
+ };
+
+ clkddr31: clkddr31 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "ddr3-1";
+ reg = <0x02350060 0xb00>, <0x02350040 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <16>;
+ };
+
+ clktac: clktac {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tac";
+ reg = <0x02350064 0xb00>, <0x02350044 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <17>;
+ };
+
+ clkrac01: clkrac01 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "rac-01";
+ reg = <0x02350068 0xb00>, <0x02350044 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <17>;
+ };
+
+ clkrac23: clkrac23 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "rac-23";
+ reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <18>;
+ };
+
+ clkfftc0: clkfftc0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-0";
+ reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <19>;
+ };
+
+ clkfftc1: clkfftc1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-1";
+ reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <19>;
+ };
+
+ clkfftc2: clkfftc2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-2";
+ reg = <0x02350078 0xb00>, <0x02350050 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <20>;
+ };
+
+ clkfftc3: clkfftc3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-3";
+ reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <20>;
+ };
+
+ clkfftc4: clkfftc4 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-4";
+ reg = <0x02350080 0xb00>, <0x02350050 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <20>;
+ };
+
+ clkfftc5: clkfftc5 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-5";
+ reg = <0x02350084 0xb00>, <0x02350050 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <20>;
+ };
+
+ clkaif: clkaif {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "aif";
+ reg = <0x02350088 0xb00>, <0x02350054 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <21>;
+ };
+
+ clktcp3d0: clktcp3d0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tcp3d-0";
+ reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <22>;
+ };
+
+ clktcp3d1: clktcp3d1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tcp3d-1";
+ reg = <0x02350090 0xb00>, <0x02350058 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <22>;
+ };
+
+ clktcp3d2: clktcp3d2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tcp3d-2";
+ reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <23>;
+ };
+
+ clktcp3d3: clktcp3d3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tcp3d-3";
+ reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <23>;
+ };
+
+ clkvcp0: clkvcp0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-0";
+ reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp1: clkvcp1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-1";
+ reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp2: clkvcp2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-2";
+ reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp3: clkvcp3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-3";
+ reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp4: clkvcp4 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-4";
+ reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <25>;
+ };
+
+ clkvcp5: clkvcp5 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-5";
+ reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <25>;
+ };
+
+ clkvcp6: clkvcp6 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-6";
+ reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <25>;
+ };
+
+ clkvcp7: clkvcp7 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-7";
+ reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <25>;
+ };
+
+ clkbcp: clkbcp {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "bcp";
+ reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <26>;
+ };
+
+ clkdxb: clkdxb {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "dxb";
+ reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <27>;
+ };
+
+ clkhyperlink1: clkhyperlink1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk12>;
+ clock-output-names = "hyperlink-1";
+ reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <28>;
+ };
+
+ clkxge: clkxge {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "xge";
+ reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <29>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "keystone.dtsi"
+#include "keystone-k2hk.dtsi"
+
+/ {
+ compatible = "ti,k2hk-evm","ti,keystone";
+ model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
+
+ soc {
+ clocks {
+ refclksys: refclksys {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <122880000>;
+ clock-output-names = "refclk-sys";
+ };
+
+ refclkpass: refclkpass {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <122880000>;
+ clock-output-names = "refclk-pass";
+ };
+
+ refclkarm: refclkarm {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "refclk-arm";
+ };
+
+ refclkddr3a: refclkddr3a {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "refclk-ddr3a";
+ };
+
+ refclkddr3b: refclkddr3b {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "refclk-ddr3b";
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ debug1_1 {
+ label = "keystone:green:debug1";
+ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
+ };
+
+ debug1_2 {
+ label = "keystone:red:debug1";
+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
+ };
+
+ debug2 {
+ label = "keystone:blue:debug2";
+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
+ };
+
+ debug3 {
+ label = "keystone:blue:debug3";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
+ };
+ };
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&aemif {
+ cs0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-ranges;
+ ranges;
+
+ ti,cs-chipselect = <0>;
+ /* all timings in nanoseconds */
+ ti,cs-min-turnaround-ns = <12>;
+ ti,cs-read-hold-ns = <6>;
+ ti,cs-read-strobe-ns = <23>;
+ ti,cs-read-setup-ns = <9>;
+ ti,cs-write-hold-ns = <8>;
+ ti,cs-write-strobe-ns = <23>;
+ ti,cs-write-setup-ns = <8>;
+
+ nand@0,0 {
+ compatible = "ti,keystone-nand","ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0 0x4000000
+ 1 0 0x0000100>;
+
+ ti,davinci-chipselect = <0>;
+ ti,davinci-mask-ale = <0x2000>;
+ ti,davinci-mask-cle = <0x4000>;
+ ti,davinci-mask-chipsel = <0>;
+ nand-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ nand-on-flash-bbt;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "params";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "ubifs";
+ reg = <0x180000 0x1fe80000>;
+ };
+ };
+ };
+};
+
+&i2c0 {
+ dtt@50 {
+ compatible = "at,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ nor_flash: n25q128a11@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "Micron,n25q128a11", "spi-flash";
+ spi-max-frequency = <54000000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "misc";
+ reg = <0x80000 0xf80000>;
+ };
+ };
+};
+
+&mdio {
+ status = "ok";
+ ethphy0: ethernet-phy@0 {
+ compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for Keystone 2 Hawking Netcp driver
+ *
+ * Copyright 2015 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+qmss: qmss@2a40000 {
+ compatible = "ti,keystone-navigator-qmss";
+ dma-coherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&chipclk13>;
+ ranges;
+ queue-range = <0 0x4000>;
+ linkram0 = <0x100000 0x8000>;
+ linkram1 = <0x0 0x10000>;
+
+ qmgrs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ qmgr0 {
+ managed-queues = <0 0x2000>;
+ reg = <0x2a40000 0x20000>,
+ <0x2a06000 0x400>,
+ <0x2a02000 0x1000>,
+ <0x2a03000 0x1000>,
+ <0x23a80000 0x20000>,
+ <0x2a80000 0x20000>;
+ reg-names = "peek", "status", "config",
+ "region", "push", "pop";
+ };
+
+ qmgr1 {
+ managed-queues = <0x2000 0x2000>;
+ reg = <0x2a60000 0x20000>,
+ <0x2a06400 0x400>,
+ <0x2a04000 0x1000>,
+ <0x2a05000 0x1000>,
+ <0x23aa0000 0x20000>,
+ <0x2aa0000 0x20000>;
+ reg-names = "peek", "status", "config",
+ "region", "push", "pop";
+ };
+ };
+ queue-pools {
+ qpend {
+ qpend-0 {
+ qrange = <658 8>;
+ interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
+ };
+ qpend-1 {
+ qrange = <8704 16>;
+ interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
+ 0 51 0xf04 0 52 0xf04 0 53 0xf04
+ 0 54 0xf04 0 55 0xf04 0 56 0xf04
+ 0 57 0xf04 0 58 0xf04 0 59 0xf04
+ 0 60 0xf04 0 61 0xf04 0 62 0xf04
+ 0 63 0xf04>;
+ qalloc-by-id;
+ };
+ qpend-2 {
+ qrange = <8720 16>;
+ interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
+ 0 59 0xf04 0 68 0xf04 0 69 0xf04
+ 0 70 0xf04 0 71 0xf04 0 72 0xf04
+ 0 73 0xf04 0 74 0xf04 0 75 0xf04
+ 0 76 0xf04 0 77 0xf04 0 78 0xf04
+ 0 79 0xf04>;
+ };
+ };
+ general-purpose {
+ gp-0 {
+ qrange = <4000 64>;
+ };
+ netcp-tx {
+ qrange = <640 9>;
+ qalloc-by-id;
+ };
+ netcpx-tx {
+ qrange = <8752 8>;
+ qalloc-by-id;
+ };
+ };
+ };
+ descriptor-regions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ region-12 {
+ id = <12>;
+ region-spec = <8192 128>; /* num_desc desc_size */
+ link-index = <0x4000>;
+ };
+ };
+}; /* qmss */
+
+knav_dmas: knav_dmas@0 {
+ compatible = "ti,keystone-navigator-dma";
+ clocks = <&papllclk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,navigator-cloud-address = <0x23a80000 0x23a90000
+ 0x23aa0000 0x23ab0000>;
+
+ dma_gbe: dma_gbe@0 {
+ reg = <0x2004000 0x100>,
+ <0x2004400 0x120>,
+ <0x2004800 0x300>,
+ <0x2004c00 0x120>,
+ <0x2005000 0x400>;
+ reg-names = "global", "txchan", "rxchan",
+ "txsched", "rxflow";
+ };
+};
+
+netcp: netcp@2000000 {
+ reg = <0x2620110 0x8>;
+ reg-names = "efuse";
+ compatible = "ti,netcp-1.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* NetCP address range */
+ ranges = <0 0x2000000 0x100000>;
+
+ clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
+ dma-coherent;
+
+ ti,navigator-dmas = <&dma_gbe 22>,
+ <&dma_gbe 23>,
+ <&dma_gbe 8>;
+ ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
+
+ netcp-devices {
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gbe@90000 { /* ETHSS */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "netcp-gbe";
+ compatible = "ti,netcp-gbe";
+ reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
+ /* enable-ale; */
+ tx-queue = <648>;
+ tx-channel = "nettx";
+
+ interfaces {
+ gbe0: interface-0 {
+ slave-port = <0>;
+ link-interface = <1>;
+ phy-handle = <ðphy0>;
+ };
+ gbe1: interface-1 {
+ slave-port = <1>;
+ link-interface = <1>;
+ phy-handle = <ðphy1>;
+ };
+ };
+
+ secondary-slave-ports {
+ port-2 {
+ slave-port = <2>;
+ link-interface = <2>;
+ };
+ port-3 {
+ slave-port = <3>;
+ link-interface = <2>;
+ };
+ };
+ };
+ };
+
+ netcp-interfaces {
+ interface-0 {
+ rx-channel = "netrx0";
+ rx-pool = <1024 12>;
+ tx-pool = <1024 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <8704>;
+ tx-completion-queue = <8706>;
+ efuse-mac = <1>;
+ netcp-gbe = <&gbe0>;
+
+ };
+ interface-1 {
+ rx-channel = "netrx1";
+ rx-pool = <1024 12>;
+ tx-pool = <1024 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <8705>;
+ tx-completion-queue = <8707>;
+ efuse-mac = <0>;
+ local-mac-address = [02 18 31 7e 3e 6f];
+ netcp-gbe = <&gbe1>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Kepler/Hawking soc specific device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gic>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ soc {
+ /include/ "keystone-k2hk-clocks.dtsi"
+
+ dspgpio0: keystone_dsp_gpio@02620240 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
+
+ dspgpio1: keystone_dsp_gpio@2620244 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x244>;
+ };
+
+ dspgpio2: keystone_dsp_gpio@2620248 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x248>;
+ };
+
+ dspgpio3: keystone_dsp_gpio@262024c {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x24c>;
+ };
+
+ dspgpio4: keystone_dsp_gpio@2620250 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x250>;
+ };
+
+ dspgpio5: keystone_dsp_gpio@2620254 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x254>;
+ };
+
+ dspgpio6: keystone_dsp_gpio@2620258 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x258>;
+ };
+
+ dspgpio7: keystone_dsp_gpio@262025c {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x25c>;
+ };
+
+ mdio: mdio@02090300 {
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x02090300 0x100>;
+ status = "disabled";
+ clocks = <&clkcpgmac>;
+ clock-names = "fck";
+ bus_freq = <2500000>;
+ };
+ /include/ "keystone-k2hk-netcp.dtsi"
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013-2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 lamarr SoC clock nodes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+clocks {
+ armpllclk: armpllclk@2620370 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclksys>;
+ clock-output-names = "arm-pll-clk";
+ reg = <0x02620370 4>;
+ reg-names = "control";
+ };
+
+ mainpllclk: mainpllclk@2310110 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,main-pll-clock";
+ clocks = <&refclksys>;
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
+ };
+
+ papllclk: papllclk@2620358 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclksys>;
+ clock-output-names = "papllclk";
+ reg = <0x02620358 4>;
+ reg-names = "control";
+ };
+
+ ddr3apllclk: ddr3apllclk@2620360 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,pll-clock";
+ clocks = <&refclksys>;
+ clock-output-names = "ddr-3a-pll-clk";
+ reg = <0x02620360 4>;
+ reg-names = "control";
+ };
+
+ clkdfeiqnsys: clkdfeiqnsys {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk12>;
+ clock-output-names = "dfe";
+ reg-names = "control", "domain";
+ reg = <0x02350004 0xb00>, <0x02350000 0x400>;
+ domain-id = <0>;
+ };
+
+ clkpcie1: clkpcie1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk12>;
+ clock-output-names = "pcie";
+ reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <4>;
+ };
+
+ clkgem1: clkgem1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem1";
+ reg = <0x02350040 0xb00>, <0x02350024 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <9>;
+ };
+
+ clkgem2: clkgem2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem2";
+ reg = <0x02350044 0xb00>, <0x02350028 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <10>;
+ };
+
+ clkgem3: clkgem3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk1>;
+ clock-output-names = "gem3";
+ reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <11>;
+ };
+
+ clktac: clktac {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tac";
+ reg = <0x02350064 0xb00>, <0x02350044 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <17>;
+ };
+
+ clkrac: clkrac {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "rac";
+ reg = <0x02350068 0xb00>, <0x02350044 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <17>;
+ };
+
+ clkdfepd0: clkdfepd0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "dfe-pd0";
+ reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <18>;
+ };
+
+ clkfftc0: clkfftc0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-0";
+ reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <19>;
+ };
+
+ clkosr: clkosr {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "osr";
+ reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <21>;
+ };
+
+ clktcp3d0: clktcp3d0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tcp3d-0";
+ reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <22>;
+ };
+
+ clktcp3d1: clktcp3d1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "tcp3d-1";
+ reg = <0x02350094 0xb00>, <0x02350058 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <23>;
+ };
+
+ clkvcp0: clkvcp0 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-0";
+ reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp1: clkvcp1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-1";
+ reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp2: clkvcp2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-2";
+ reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkvcp3: clkvcp3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "vcp-3";
+ reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <24>;
+ };
+
+ clkbcp: clkbcp {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "bcp";
+ reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <26>;
+ };
+
+ clkdfepd1: clkdfepd1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "dfe-pd1";
+ reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <27>;
+ };
+
+ clkfftc1: clkfftc1 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "fftc-1";
+ reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <28>;
+ };
+
+ clkiqnail: clkiqnail {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&chipclk13>;
+ clock-output-names = "iqn-ail";
+ reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <29>;
+ };
+
+ clkuart2: clkuart2 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&clkmodrst0>;
+ clock-output-names = "uart2";
+ reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <0>;
+ };
+
+ clkuart3: clkuart3 {
+ #clock-cells = <0>;
+ compatible = "ti,keystone,psc-clock";
+ clocks = <&clkmodrst0>;
+ clock-output-names = "uart3";
+ reg = <0x02350000 0xb00>, <0x02350000 0x400>;
+ reg-names = "control", "domain";
+ domain-id = <0>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Lamarr EVM device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "keystone.dtsi"
+#include "keystone-k2l.dtsi"
+
+/ {
+ compatible = "ti,k2l-evm","ti,keystone";
+ model = "Texas Instruments Keystone 2 Lamarr EVM";
+
+ soc {
+ clocks {
+ refclksys: refclksys {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <122880000>;
+ clock-output-names = "refclk-sys";
+ };
+ };
+ };
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&i2c0 {
+ dtt@50 {
+ compatible = "at,24c1024";
+ reg = <0x50>;
+ };
+};
+
+&aemif {
+ cs0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-ranges;
+ ranges;
+
+ ti,cs-chipselect = <0>;
+ /* all timings in nanoseconds */
+ ti,cs-min-turnaround-ns = <12>;
+ ti,cs-read-hold-ns = <6>;
+ ti,cs-read-strobe-ns = <23>;
+ ti,cs-read-setup-ns = <9>;
+ ti,cs-write-hold-ns = <8>;
+ ti,cs-write-strobe-ns = <23>;
+ ti,cs-write-setup-ns = <8>;
+
+ nand@0,0 {
+ compatible = "ti,keystone-nand","ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0 0x4000000
+ 1 0 0x0000100>;
+
+ ti,davinci-chipselect = <0>;
+ ti,davinci-mask-ale = <0x2000>;
+ ti,davinci-mask-cle = <0x4000>;
+ ti,davinci-mask-chipsel = <0>;
+ nand-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ nand-on-flash-bbt;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "params";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "ubifs";
+ reg = <0x180000 0x7FE80000>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ status ="okay";
+ nor_flash: n25q128a11@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "Micron,n25q128a11", "spi-flash";
+ spi-max-frequency = <54000000>;
+ m25p,fast-read;
+ reg = <0>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@1 {
+ label = "misc";
+ reg = <0x80000 0xf80000>;
+ };
+ };
+};
+
+&mdio {
+ status = "ok";
+ ethphy0: ethernet-phy@0 {
+ compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
--- /dev/null
+/*
+ * Device Tree Source for Keystone 2 Lamarr Netcp driver
+ *
+ * Copyright 2015 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+qmss: qmss@2a40000 {
+ compatible = "ti,keystone-navigator-qmss";
+ dma-coherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&chipclk13>;
+ ranges;
+ queue-range = <0 0x2000>;
+ linkram0 = <0x100000 0x4000>;
+ linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
+
+ qmgrs {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ qmgr0 {
+ managed-queues = <0 0x2000>;
+ reg = <0x2a40000 0x20000>,
+ <0x2a06000 0x400>,
+ <0x2a02000 0x1000>,
+ <0x2a03000 0x1000>,
+ <0x23a80000 0x20000>,
+ <0x2a80000 0x20000>;
+ reg-names = "peek", "status", "config",
+ "region", "push", "pop";
+ };
+ };
+ queue-pools {
+ qpend {
+ qpend-0 {
+ qrange = <658 8>;
+ interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
+ };
+ qpend-1 {
+ qrange = <528 16>;
+ interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
+ 0 51 0xf04 0 52 0xf04 0 53 0xf04
+ 0 54 0xf04 0 55 0xf04 0 56 0xf04
+ 0 57 0xf04 0 58 0xf04 0 59 0xf04
+ 0 60 0xf04 0 61 0xf04 0 62 0xf04
+ 0 63 0xf04>;
+ qalloc-by-id;
+ };
+ qpend-2 {
+ qrange = <544 16>;
+ interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
+ 0 59 0xf04 0 68 0xf04 0 69 0xf04
+ 0 70 0xf04 0 71 0xf04 0 72 0xf04
+ 0 73 0xf04 0 74 0xf04 0 75 0xf04
+ 0 76 0xf04 0 77 0xf04 0 78 0xf04
+ 0 79 0xf04>;
+ };
+ };
+ general-purpose {
+ gp-0 {
+ qrange = <4000 64>;
+ };
+ netcp-tx {
+ qrange = <896 128>;
+ qalloc-by-id;
+ };
+ };
+ };
+ descriptor-regions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ region-12 {
+ id = <12>;
+ region-spec = <8192 128>; /* num_desc desc_size */
+ link-index = <0x4000>;
+ };
+ };
+}; /* qmss */
+
+knav_dmas: knav_dmas@0 {
+ compatible = "ti,keystone-navigator-dma";
+ clocks = <&papllclk>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,navigator-cloud-address = <0x23a80000 0x23a90000>;
+
+ dma_gbe: dma_gbe@0 {
+ reg = <0x26186000 0x100>,
+ <0x26187000 0x2a0>,
+ <0x26188000 0xb60>,
+ <0x26186100 0x80>,
+ <0x26189000 0x1000>;
+ reg-names = "global", "txchan", "rxchan",
+ "txsched", "rxflow";
+ };
+};
+
+netcp: netcp@26000000 {
+ reg = <0x2620110 0x8>;
+ reg-names = "efuse";
+ compatible = "ti,netcp-1.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* NetCP address range */
+ ranges = <0 0x26000000 0x1000000>;
+
+ clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
+ dma-coherent;
+
+ ti,navigator-dmas = <&dma_gbe 0>,
+ <&dma_gbe 8>,
+ <&dma_gbe 0>;
+ ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
+
+ netcp-devices {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ gbe@200000 { /* ETHSS */
+ label = "netcp-gbe";
+ compatible = "ti,netcp-gbe-5";
+ reg = <0x200000 0x900>, <0x220000 0x20000>;
+ /* enable-ale; */
+ tx-queue = <896>;
+ tx-channel = "nettx";
+
+ interfaces {
+ gbe0: interface-0 {
+ slave-port = <0>;
+ link-interface = <1>;
+ phy-handle = <ðphy0>;
+ };
+ gbe1: interface-1 {
+ slave-port = <1>;
+ link-interface = <1>;
+ phy-handle = <ðphy1>;
+ };
+ };
+
+ secondary-slave-ports {
+ port-2 {
+ slave-port = <2>;
+ link-interface = <2>;
+ };
+ port-3 {
+ slave-port = <3>;
+ link-interface = <2>;
+ };
+ };
+ };
+ };
+
+ netcp-interfaces {
+ interface-0 {
+ rx-channel = "netrx0";
+ rx-pool = <1024 12>;
+ tx-pool = <1024 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <528>;
+ tx-completion-queue = <530>;
+ efuse-mac = <1>;
+ netcp-gbe = <&gbe0>;
+
+ };
+ interface-1 {
+ rx-channel = "netrx1";
+ rx-pool = <1024 12>;
+ tx-pool = <1024 12>;
+ rx-queue-depth = <128 128 0 0>;
+ rx-buffer-size = <1518 4096 0 0>;
+ rx-queue = <529>;
+ tx-completion-queue = <531>;
+ efuse-mac = <0>;
+ local-mac-address = [02 18 31 7e 3e 7f];
+ netcp-gbe = <&gbe1>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 Lamarr SoC specific device tree
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gic>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ /include/ "keystone-k2l-clocks.dtsi"
+
+ uart2: serial@02348400 {
+ compatible = "ns16550a";
+ current-speed = <115200>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ reg = <0x02348400 0x100>;
+ clocks = <&clkuart2>;
+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ uart3: serial@02348800 {
+ compatible = "ns16550a";
+ current-speed = <115200>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ reg = <0x02348800 0x100>;
+ clocks = <&clkuart3>;
+ interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ dspgpio0: keystone_dsp_gpio@02620240 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x240>;
+ };
+
+ dspgpio1: keystone_dsp_gpio@2620244 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x244>;
+ };
+
+ dspgpio2: keystone_dsp_gpio@2620248 {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x248>;
+ };
+
+ dspgpio3: keystone_dsp_gpio@262024c {
+ compatible = "ti,keystone-dsp-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&devctrl 0x24c>;
+ };
+
+ mdio: mdio@26200f00 {
+ compatible = "ti,keystone_mdio", "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x26200f00 0x100>;
+ status = "disabled";
+ clocks = <&clkcpgmac>;
+ clock-names = "fck";
+ bus_freq = <2500000>;
+ };
+ /include/ "keystone-k2l-netcp.dtsi"
+ };
+};
+
+&spi0 {
+ ti,davinci-spi-num-cs = <5>;
+};
+
+&spi1 {
+ ti,davinci-spi-num-cs = <3>;
+};
+
+&spi2 {
+ ti,davinci-spi-num-cs = <5>;
+ /* Pin muxed. Enabled and configured by Bootloader */
+ status = "disabled";
+};
*/
ldr x0, =__bss_start /* this is auto-relocated! */
ldr x1, =__bss_end /* this is auto-relocated! */
- mov x2, #0
clear_loop:
- str x2, [x0]
- add x0, x0, #8
+ str xzr, [x0], #8
cmp x0, x1
b.lo clear_loop
b 0f
1: mrs x0, sctlr_el1
0: tbz w0, #2, 5f /* skip flushing cache if disabled */
- tbz w0, #12, 4f /* invalide i-cache is enabled */
+ tbz w0, #12, 4f /* skip invalidating i-cache if disabled */
ic iallu /* i-cache invalidate all */
isb sy
4: ldp x0, x1, [sp, #16]
priv->regs = regmap_get_range(map, 0);
priv->phy = regmap_get_range(map, 1);
- priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
if (!priv->clock_rate) {
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_sdram_params *params = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
/* Rk3288 supports dual-channel, set default channel num to 2 */
config ARCH_UNIPHIER_64BIT
bool
select ARM64
+ select CMD_UNZIP
select SPL_SEPARATE_BSS if SPL
select ARMV8_MULTIENTRY if SPL
select ARMV8_SPIN_TABLE if SPL
static int altera_nios2_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
gd->cpu_clk = fdtdec_get_int(blob, node,
"clock-frequency", 0);
stringarray = "one";
};
+ spl-test4 {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test.2";
+ };
+
square {
compatible = "demo-shape";
colour = "blue";
config SYS_ARCH
default "x86"
+choice
+ prompt "Run U-Boot in 32/64-bit mode"
+ default X86_RUN_32BIT
+ help
+ U-Boot can be built as a 32-bit binary which runs in 32-bit mode
+ even on 64-bit machines. In this case SPL is not used, and U-Boot
+ runs directly from the reset vector (via 16-bit start-up).
+
+ Alternatively it can be run as a 64-bit binary, thus requiring a
+ 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
+ start-up) then jumps to U-Boot in 64-bit mode.
+
+ For now, 32-bit mode is recommended, as 64-bit is still
+ experimental and is missing a lot of features.
+
+config X86_RUN_32BIT
+ bool "32-bit"
+ help
+ Build U-Boot as a 32-bit binary with no SPL. This is the currently
+ supported normal setup. U-Boot will stay in 32-bit mode even on
+ 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
+ to 64-bit just before starting the kernel. Only the bottom 4GB of
+ memory can be accessed through normal means, although
+ arch_phys_memset() can be used for basic access to other memory.
+
+config X86_RUN_64BIT
+ bool "64-bit"
+ select X86_64
+ select SUPPORT_SPL
+ select SPL
+ select SPL_SEPARATE_BSS
+ help
+ Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
+ experimental and many features are missing. U-Boot SPL starts up,
+ runs through the 16-bit and 32-bit init, then switches to 64-bit
+ mode and jumps to U-Boot proper.
+
+endchoice
+
+config X86_64
+ bool
+
+config SPL_X86_64
+ bool
+ depends on SPL
+
choice
prompt "Mainboard vendor"
default VENDOR_EMULATION
bool
default n
+# The following options control where the 16-bit and 32-bit init lies
+# If SPL is enabled then it normally holds this init code, and U-Boot proper
+# is normally a 64-bit build.
+#
+# The 16-bit init refers to the reset vector and the small amount of code to
+# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
+# or missing altogether if U-Boot is started from EFI or coreboot.
+#
+# The 32-bit init refers to processor init, running binary blobs including
+# FSP, setting up interrupts and anything else that needs to be done in
+# 32-bit code. It is normally in the same place as 16-bit init if that is
+# enabled (i.e. they are both in SPL, or both in U-Boot proper).
+config X86_16BIT_INIT
+ bool
+ depends on X86_RESET_VECTOR
+ default y if X86_RESET_VECTOR && !SPL
+ help
+ This is enabled when 16-bit init is in U-Boot proper
+
+config SPL_X86_16BIT_INIT
+ bool
+ depends on X86_RESET_VECTOR
+ default y if X86_RESET_VECTOR && SPL
+ help
+ This is enabled when 16-bit init is in SPL
+
+config X86_32BIT_INIT
+ bool
+ depends on X86_RESET_VECTOR
+ default y if X86_RESET_VECTOR && !SPL
+ help
+ This is enabled when 32-bit init is in U-Boot proper
+
+config SPL_X86_32BIT_INIT
+ bool
+ depends on X86_RESET_VECTOR
+ default y if X86_RESET_VECTOR && SPL
+ help
+ This is enabled when 32-bit init is in SPL
+
config RESET_SEG_START
hex
depends on X86_RESET_VECTOR
depends on X86_RESET_VECTOR
default 0xfffff800
+config X86_LOAD_FROM_32_BIT
+ bool "Boot from a 32-bit program"
+ help
+ Define this to boot U-Boot from a 32-bit program which sets
+ the GDT differently. This can be used to boot directly from
+ any stage of coreboot, for example, bypassing the normal
+ payload-loading feature.
+
config BOARD_ROMSIZE_KB_512
bool
config BOARD_ROMSIZE_KB_1024
#
ifeq ($(CONFIG_EFI_APP),)
+ifdef CONFIG_$(SPL_)X86_64
+head-y := arch/x86/cpu/start64.o
+else
head-y := arch/x86/cpu/start.o
endif
-ifeq ($(CONFIG_SPL_BUILD),y)
-head-y += arch/x86/cpu/start16.o
-head-y += arch/x86/cpu/resetvec.o
endif
+head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
+head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
+
libs-y += arch/x86/cpu/
libs-y += arch/x86/lib/
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+
+ifdef CONFIG_SPL_BUILD
+IS_32BIT := y
+else
+ifndef CONFIG_X86_64
+IS_32BIT := y
+endif
+endif
+
+ifeq ($(IS_32BIT),y)
PLATFORM_CPPFLAGS += -march=i386 -m32
+else
+PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common
+endif
PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
-PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions -m elf_i386
+PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions
+PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)
LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \
-j .rel -j .rela -j .reloc
+ifeq ($(IS_32BIT),y)
CFLAGS_NON_EFI := -mregparm=3
+endif
CFLAGS_EFI := -fpic -fshort-wchar
ifeq ($(CONFIG_EFI_STUB_64BIT),)
PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI)
PLATFORM_LDFLAGS += --emit-relocs
-LDFLAGS_FINAL += --gc-sections -pie
+LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie)
+
+endif
+ifdef CONFIG_X86_64
+ifndef CONFIG_SPL_BUILD
+PLATFORM_CPPFLAGS += -D__x86_64__
+else
+PLATFORM_CPPFLAGS += -D__I386__
+endif
+else
+PLATFORM_CPPFLAGS += -D__I386__
endif
ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
# SPDX-License-Identifier: GPL-2.0+
#
+ifeq ($(CONFIG_$(SPL_)X86_64),y)
+extra-y = start64.o
+else
extra-y = start.o
-obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o
+endif
+extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
+obj-y += cpu.o cpu_x86.o
+
+ifndef CONFIG_$(SPL_)X86_64
AFLAGS_REMOVE_call32.o := -mregparm=3 \
$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
AFLAGS_call32.o := -fpic -fshort-wchar
extra-y += call32.o
+endif
obj-y += intel_common/
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
-obj-y += irq.o lapic.o ioapic.o
+obj-y += lapic.o ioapic.o
+obj-y += irq.o
+ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
+endif
obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
+ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += sipi_vector.o
+endif
obj-y += turbo.o
+
+ifeq ($(CONFIG_$(SPL_)X86_64),y)
+obj-y += x86_64/
+else
+obj-y += i386/
+endif
/* Set the slow ramp rate */
msr.hi &= ~(0x3 << (53 - 32));
/* Configure the C-state exit ramp rate */
- ramp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,slow-ramp",
- -1);
+ ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,slow-ramp", -1);
if (ramp != -1) {
/* Configured slow ramp rate */
msr.hi |= ((ramp & 0x3) << (53 - 32));
}
/* Set MIN_VID (31:24) to allow CPU to have full control */
msr.lo &= ~0xff000000;
- min_vid = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,min-vid",
- 0);
+ min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,min-vid", 0);
msr.lo |= (min_vid & 0xff) << 24;
msr_write(MSR_VR_MISC_CONFIG, msr);
int tcc_offset;
msr_t msr;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,tcc-offset", 0);
/* Set TCC activaiton offset if supported */
debug("Set power %s after power failure.\n", state);
/* GPE setup based on device tree configuration */
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"intel,gpe0-en", enable, ARRAY_SIZE(enable));
if (ret)
return -EINVAL;
enable_all_gpe(enable[0], enable[1], enable[2], enable[3]);
/* SMI setup based on device tree configuration */
- enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,alt-gp-smi-enable", 0));
return 0;
int node;
debug("%s: starting\n", __func__);
- for (node = fdt_first_subnode(blob, dev->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
int phandle = fdt_get_phandle(blob, node);
int count = 0;
int node;
- for (node = fdt_first_subnode(blob, dev->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
int len, i;
{
struct sata_platdata *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
plat->port0_gen3_tx = fdtdec_get_int(blob, node,
+++ /dev/null
-/*
- * (C) Copyright 2014 Google, Inc
- * Copyright (C) 1991, 1992, 1993 Linus Torvalds
- *
- * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/global_data.h>
-#include <asm/msr-index.h>
-#include <asm/processor-flags.h>
-
-.code32
-.globl cpu_call64
-cpu_call64:
- /*
- * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
- *
- * eax - pgtable
- * edx - setup_base
- * ecx - target
- */
- cli
- push %ecx /* arg2 = target */
- push %edx /* arg1 = setup_base */
- mov %eax, %ebx
-
- /* Load new GDT with the 64bit segments using 32bit descriptor */
- leal gdt, %eax
- movl %eax, gdt+2
- lgdt gdt
-
- /* Enable PAE mode */
- movl $(X86_CR4_PAE), %eax
- movl %eax, %cr4
-
- /* Enable the boot page tables */
- leal (%ebx), %eax
- movl %eax, %cr3
-
- /* Enable Long mode in EFER (Extended Feature Enable Register) */
- movl $MSR_EFER, %ecx
- rdmsr
- btsl $_EFER_LME, %eax
- wrmsr
-
- /* After gdt is loaded */
- xorl %eax, %eax
- lldt %ax
- movl $0x20, %eax
- ltr %ax
-
- /*
- * Setup for the jump to 64bit mode
- *
- * When the jump is performed we will be in long mode but
- * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
- * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
- * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
- * We place all of the values on our mini stack so lret can
- * used to perform that far jump. See the gdt below.
- */
- pop %esi /* setup_base */
-
- pushl $0x10
- leal lret_target, %eax
- pushl %eax
-
- /* Enter paged protected Mode, activating Long Mode */
- movl $(X86_CR0_PG | X86_CR0_PE), %eax
- movl %eax, %cr0
-
- /* Jump from 32bit compatibility mode into 64bit mode. */
- lret
-
-code64:
-lret_target:
- pop %eax /* target */
- mov %eax, %eax /* Clear bits 63:32 */
- jmp *%eax /* Jump to the 64-bit target */
-
- .data
-gdt:
- .word gdt_end - gdt - 1
- .long gdt /* Fixed up by code above */
- .word 0
- .quad 0x0000000000000000 /* NULL descriptor */
- .quad 0x00af9a000000ffff /* __KERNEL_CS */
- .quad 0x00cf92000000ffff /* __KERNEL_DS */
- .quad 0x0080890000000000 /* TS descriptor */
- .quad 0x0000000000000000 /* TS continued */
-gdt_end:
CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -D__I386__
-
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START)
LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE)
LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC)
LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)"
+
+ifdef CONFIG_X86_64
+ifndef CONFIG_SPL_BUILD
+LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds
+endif
+endif
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Constructor for a conventional segment GDT (or LDT) entry
- * This is a macro so it can be used in initialisers
- */
-#define GDT_ENTRY(flags, base, limit) \
- ((((base) & 0xff000000ULL) << (56-24)) | \
- (((flags) & 0x0000f0ffULL) << 40) | \
- (((limit) & 0x000f0000ULL) << (48-16)) | \
- (((base) & 0x00ffffffULL) << 16) | \
- (((limit) & 0x0000ffffULL)))
-
-struct gdt_ptr {
- u16 len;
- u32 ptr;
-} __packed;
-
-struct cpu_device_id {
- unsigned vendor;
- unsigned device;
-};
-
-struct cpuinfo_x86 {
- uint8_t x86; /* CPU family */
- uint8_t x86_vendor; /* CPU vendor */
- uint8_t x86_model;
- uint8_t x86_mask;
-};
-
-/*
- * List of cpu vendor strings along with their normalized
- * id values.
- */
-static const struct {
- int vendor;
- const char *name;
-} x86_vendors[] = {
- { X86_VENDOR_INTEL, "GenuineIntel", },
- { X86_VENDOR_CYRIX, "CyrixInstead", },
- { X86_VENDOR_AMD, "AuthenticAMD", },
- { X86_VENDOR_UMC, "UMC UMC UMC ", },
- { X86_VENDOR_NEXGEN, "NexGenDriven", },
- { X86_VENDOR_CENTAUR, "CentaurHauls", },
- { X86_VENDOR_RISE, "RiseRiseRise", },
- { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
- { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
- { X86_VENDOR_NSC, "Geode by NSC", },
- { X86_VENDOR_SIS, "SiS SiS SiS ", },
-};
-
static const char *const x86_vendor_name[] = {
[X86_VENDOR_INTEL] = "Intel",
[X86_VENDOR_CYRIX] = "Cyrix",
[X86_VENDOR_SIS] = "SiS",
};
-static void load_ds(u32 segment)
-{
- asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_es(u32 segment)
-{
- asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_fs(u32 segment)
-{
- asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_gs(u32 segment)
-{
- asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_ss(u32 segment)
-{
- asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_gdt(const u64 *boot_gdt, u16 num_entries)
-{
- struct gdt_ptr gdt;
-
- gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
- gdt.ptr = (ulong)boot_gdt;
-
- asm volatile("lgdtl %0\n" : : "m" (gdt));
-}
-
-void arch_setup_gd(gd_t *new_gd)
-{
- u64 *gdt_addr;
-
- gdt_addr = new_gd->arch.gdt;
-
- /*
- * CS: code, read/execute, 4 GB, base 0
- *
- * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
- */
- gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
- gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
-
- /* DS: data, read/write, 4 GB, base 0 */
- gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
-
- /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
- new_gd->arch.gd_addr = new_gd;
- gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
- (ulong)&new_gd->arch.gd_addr, 0xfffff);
-
- /* 16-bit CS: code, read/execute, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
-
- /* 16-bit DS: data, read/write, 64 kB, base 0 */
- gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
-
- gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
- gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
-
- load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
- load_ds(X86_GDT_ENTRY_32BIT_DS);
- load_es(X86_GDT_ENTRY_32BIT_DS);
- load_gs(X86_GDT_ENTRY_32BIT_DS);
- load_ss(X86_GDT_ENTRY_32BIT_DS);
- load_fs(X86_GDT_ENTRY_32BIT_FS);
-}
-
-#ifdef CONFIG_HAVE_FSP
-/*
- * Setup FSP execution environment GDT
- *
- * Per Intel FSP external architecture specification, before calling any FSP
- * APIs, we need make sure the system is in flat 32-bit mode and both the code
- * and data selectors should have full 4GB access range. Here we reuse the one
- * we used in arch/x86/cpu/start16.S, and reload the segement registers.
- */
-void setup_fsp_gdt(void)
-{
- load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
- load_ds(X86_GDT_ENTRY_32BIT_DS);
- load_ss(X86_GDT_ENTRY_32BIT_DS);
- load_es(X86_GDT_ENTRY_32BIT_DS);
- load_fs(X86_GDT_ENTRY_32BIT_DS);
- load_gs(X86_GDT_ENTRY_32BIT_DS);
-}
-#endif
-
int __weak x86_cleanup_before_linux(void)
{
#ifdef CONFIG_BOOTSTAGE_STASH
return 0;
}
-/*
- * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
- * by the fact that they preserve the flags across the division of 5/2.
- * PII and PPro exhibit this behavior too, but they have cpuid available.
- */
-
-/*
- * Perform the Cyrix 5/2 test. A Cyrix won't change
- * the flags, while other 486 chips will.
- */
-static inline int test_cyrix_52div(void)
-{
- unsigned int test;
-
- __asm__ __volatile__(
- "sahf\n\t" /* clear flags (%eax = 0x0005) */
- "div %b2\n\t" /* divide 5 by 2 */
- "lahf" /* store flags into %ah */
- : "=a" (test)
- : "0" (5), "q" (2)
- : "cc");
-
- /* AH is 0x02 on Cyrix after the divide.. */
- return (unsigned char) (test >> 8) == 0x02;
-}
-
-/*
- * Detect a NexGen CPU running without BIOS hypercode new enough
- * to have CPUID. (Thanks to Herbert Oppmann)
- */
-
-static int deep_magic_nexgen_probe(void)
-{
- int ret;
-
- __asm__ __volatile__ (
- " movw $0x5555, %%ax\n"
- " xorw %%dx,%%dx\n"
- " movw $2, %%cx\n"
- " divw %%cx\n"
- " movl $0, %%eax\n"
- " jnz 1f\n"
- " movl $1, %%eax\n"
- "1:\n"
- : "=a" (ret) : : "cx", "dx");
- return ret;
-}
-
-static bool has_cpuid(void)
-{
- return flag_is_changeable_p(X86_EFLAGS_ID);
-}
-
-static bool has_mtrr(void)
-{
- return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
-}
-
-static int build_vendor_name(char *vendor_name)
-{
- struct cpuid_result result;
- result = cpuid(0x00000000);
- unsigned int *name_as_ints = (unsigned int *)vendor_name;
-
- name_as_ints[0] = result.ebx;
- name_as_ints[1] = result.edx;
- name_as_ints[2] = result.ecx;
-
- return result.eax;
-}
-
-static void identify_cpu(struct cpu_device_id *cpu)
-{
- char vendor_name[16];
- int i;
-
- vendor_name[0] = '\0'; /* Unset */
- cpu->device = 0; /* fix gcc 4.4.4 warning */
-
- /* Find the id and vendor_name */
- if (!has_cpuid()) {
- /* Its a 486 if we can modify the AC flag */
- if (flag_is_changeable_p(X86_EFLAGS_AC))
- cpu->device = 0x00000400; /* 486 */
- else
- cpu->device = 0x00000300; /* 386 */
- if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
- memcpy(vendor_name, "CyrixInstead", 13);
- /* If we ever care we can enable cpuid here */
- }
- /* Detect NexGen with old hypercode */
- else if (deep_magic_nexgen_probe())
- memcpy(vendor_name, "NexGenDriven", 13);
- }
- if (has_cpuid()) {
- int cpuid_level;
-
- cpuid_level = build_vendor_name(vendor_name);
- vendor_name[12] = '\0';
-
- /* Intel-defined flags: level 0x00000001 */
- if (cpuid_level >= 0x00000001) {
- cpu->device = cpuid_eax(0x00000001);
- } else {
- /* Have CPUID level 0 only unheard of */
- cpu->device = 0x00000400;
- }
- }
- cpu->vendor = X86_VENDOR_UNKNOWN;
- for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
- if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
- cpu->vendor = x86_vendors[i].vendor;
- break;
- }
- }
-}
-
-static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
-{
- c->x86 = (tfms >> 8) & 0xf;
- c->x86_model = (tfms >> 4) & 0xf;
- c->x86_mask = tfms & 0xf;
- if (c->x86 == 0xf)
- c->x86 += (tfms >> 20) & 0xff;
- if (c->x86 >= 0x6)
- c->x86_model += ((tfms >> 16) & 0xF) << 4;
-}
-
-u32 cpu_get_family_model(void)
-{
- return gd->arch.x86_device & 0x0fff0ff0;
-}
-
-u32 cpu_get_stepping(void)
-{
- return gd->arch.x86_mask;
-}
-
-int x86_cpu_init_f(void)
-{
- const u32 em_rst = ~X86_CR0_EM;
- const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
-
- if (ll_boot_init()) {
- /* initialize FPU, reset EM, set MP and NE */
- asm ("fninit\n" \
- "movl %%cr0, %%eax\n" \
- "andl %0, %%eax\n" \
- "orl %1, %%eax\n" \
- "movl %%eax, %%cr0\n" \
- : : "i" (em_rst), "i" (mp_ne_set) : "eax");
- }
-
- /* identify CPU via cpuid and store the decoded info into gd->arch */
- if (has_cpuid()) {
- struct cpu_device_id cpu;
- struct cpuinfo_x86 c;
-
- identify_cpu(&cpu);
- get_fms(&c, cpu.device);
- gd->arch.x86 = c.x86;
- gd->arch.x86_vendor = cpu.vendor;
- gd->arch.x86_model = c.x86_model;
- gd->arch.x86_mask = c.x86_mask;
- gd->arch.x86_device = cpu.device;
-
- gd->arch.has_mtrr = has_mtrr();
- }
- /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
- gd->pci_ram_top = 0x80000000U;
-
- /* Configure fixed range MTRRs for some legacy regions */
- if (gd->arch.has_mtrr) {
- u64 mtrr_cap;
-
- mtrr_cap = native_read_msr(MTRR_CAP_MSR);
- if (mtrr_cap & MTRR_CAP_FIX) {
- /* Mark the VGA RAM area as uncacheable */
- native_write_msr(MTRR_FIX_16K_A0000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
- MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
-
- /*
- * Mark the PCI ROM area as cacheable to improve ROM
- * execution performance.
- */
- native_write_msr(MTRR_FIX_4K_C0000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
- native_write_msr(MTRR_FIX_4K_C8000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
- native_write_msr(MTRR_FIX_4K_D0000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
- native_write_msr(MTRR_FIX_4K_D8000_MSR,
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
- MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
-
- /* Enable the fixed range MTRRs */
- msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
- }
- }
-
-#ifdef CONFIG_I8254_TIMER
- /* Set up the i8254 timer if required */
- i8254_init();
-#endif
-
- return 0;
-}
-
-void x86_enable_caches(void)
-{
- unsigned long cr0;
-
- cr0 = read_cr0();
- cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
- write_cr0(cr0);
- wbinvd();
-}
-void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
-
-void x86_disable_caches(void)
-{
- unsigned long cr0;
-
- cr0 = read_cr0();
- cr0 |= X86_CR0_NW | X86_CR0_CD;
- wbinvd();
- write_cr0(cr0);
- wbinvd();
-}
-void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
-
int x86_init_cache(void)
{
enable_caches();
outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
}
-int dcache_status(void)
-{
- return !(read_cr0() & X86_CR0_CD);
-}
-
/* Define these functions to allow ehch-hcd to function */
void flush_dcache_range(unsigned long start, unsigned long stop)
{
return 1;
}
-void cpu_enable_paging_pae(ulong cr3)
-{
- __asm__ __volatile__(
- /* Load the page table address */
- "movl %0, %%cr3\n"
- /* Enable pae */
- "movl %%cr4, %%eax\n"
- "orl $0x00000020, %%eax\n"
- "movl %%eax, %%cr4\n"
- /* Enable paging */
- "movl %%cr0, %%eax\n"
- "orl $0x80000000, %%eax\n"
- "movl %%eax, %%cr0\n"
- :
- : "r" (cr3)
- : "eax");
-}
-
-void cpu_disable_paging_pae(void)
-{
- /* Turn off paging */
- __asm__ __volatile__ (
- /* Disable paging */
- "movl %%cr0, %%eax\n"
- "andl $0x7fffffff, %%eax\n"
- "movl %%eax, %%cr0\n"
- /* Disable pae */
- "movl %%cr4, %%eax\n"
- "andl $0xffffffdf, %%eax\n"
- "movl %%eax, %%cr4\n"
- :
- :
- : "eax");
-}
-
-static bool can_detect_long_mode(void)
-{
- return cpuid_eax(0x80000000) > 0x80000000UL;
-}
-
-static bool has_long_mode(void)
-{
- return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
-}
-
-int cpu_has_64bit(void)
-{
- return has_cpuid() && can_detect_long_mode() &&
- has_long_mode();
-}
-
const char *cpu_vendor_name(int vendor)
{
const char *name;
return 0;
}
-#define PAGETABLE_SIZE (6 * 4096)
-
-/**
- * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
- *
- * @pgtable: Pointer to a 24iKB block of memory
- */
-static void build_pagetable(uint32_t *pgtable)
-{
- uint i;
-
- memset(pgtable, '\0', PAGETABLE_SIZE);
-
- /* Level 4 needs a single entry */
- pgtable[0] = (ulong)&pgtable[1024] + 7;
-
- /* Level 3 has one 64-bit entry for each GiB of memory */
- for (i = 0; i < 4; i++)
- pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
-
- /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
- for (i = 0; i < 2048; i++)
- pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
-}
-
-int cpu_jump_to_64bit(ulong setup_base, ulong target)
-{
- uint32_t *pgtable;
-
- pgtable = memalign(4096, PAGETABLE_SIZE);
- if (!pgtable)
- return -ENOMEM;
-
- build_pagetable(pgtable);
- cpu_call64((ulong)pgtable, setup_base, target);
- free(pgtable);
-
- return -EFAULT;
-}
-
void show_boot_progress(int val)
{
outb(val, POST_PORT);
}
#endif
-#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
- return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
- MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
- /* Wait for APs to finish initialization before proceeding */
- MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int x86_mp_init(void)
-{
- struct mp_params mp_params;
-
- mp_params.parallel_microcode_load = 0,
- mp_params.flight_plan = &mp_steps[0];
- mp_params.num_records = ARRAY_SIZE(mp_steps);
- mp_params.microcode_pointer = 0;
-
- if (mp_init(&mp_params)) {
- printf("Warning: MP init failure\n");
- return -EIO;
- }
-
- return 0;
-}
-#endif
-
static int x86_init_cpus(void)
{
#ifdef CONFIG_SMP
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpuid_result res;
- plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,apic-id", -1);
plat->family = gd->arch.x86;
res = cpuid(1);
--- /dev/null
+#
+# (C) Copyright 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+obj-y += call64.o
+obj-y += cpu.o
+obj-y += interrupt.o
+obj-y += setjmp.o
--- /dev/null
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Copyright (C) 1991, 1992, 1993 Linus Torvalds
+ *
+ * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor-flags.h>
+
+.code32
+.globl cpu_call64
+cpu_call64:
+ /*
+ * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
+ *
+ * eax - pgtable
+ * edx - setup_base
+ * ecx - target
+ */
+ cli
+ push %ecx /* arg2 = target */
+ push %edx /* arg1 = setup_base */
+ mov %eax, %ebx
+
+ /* Load new GDT with the 64bit segments using 32bit descriptor */
+ leal gdt, %eax
+ movl %eax, gdt+2
+ lgdt gdt
+
+ /* Enable PAE mode */
+ movl $(X86_CR4_PAE), %eax
+ movl %eax, %cr4
+
+ /* Enable the boot page tables */
+ leal (%ebx), %eax
+ movl %eax, %cr3
+
+ /* Enable Long mode in EFER (Extended Feature Enable Register) */
+ movl $MSR_EFER, %ecx
+ rdmsr
+ btsl $_EFER_LME, %eax
+ wrmsr
+
+ /* After gdt is loaded */
+ xorl %eax, %eax
+ lldt %ax
+ movl $0x20, %eax
+ ltr %ax
+
+ /*
+ * Setup for the jump to 64bit mode
+ *
+ * When the jump is performed we will be in long mode but
+ * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
+ * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
+ * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
+ * We place all of the values on our mini stack so lret can
+ * used to perform that far jump. See the gdt below.
+ */
+ pop %esi /* setup_base */
+
+ pushl $0x10
+ leal lret_target, %eax
+ pushl %eax
+
+ /* Enter paged protected Mode, activating Long Mode */
+ movl $(X86_CR0_PG | X86_CR0_PE), %eax
+ movl %eax, %cr0
+
+ /* Jump from 32bit compatibility mode into 64bit mode. */
+ lret
+
+code64:
+lret_target:
+ pop %eax /* target */
+ mov %eax, %eax /* Clear bits 63:32 */
+ jmp *%eax /* Jump to the 64-bit target */
+
+ .data
+ .align 16
+ .globl gdt64
+gdt64:
+gdt:
+ .word gdt_end - gdt - 1
+ .long gdt /* Fixed up by code above */
+ .word 0
+ .quad 0x0000000000000000 /* NULL descriptor */
+ .quad 0x00af9a000000ffff /* __KERNEL_CS */
+ .quad 0x00cf92000000ffff /* __KERNEL_DS */
+ .quad 0x0080890000000000 /* TS descriptor */
+ .quad 0x0000000000000000 /* TS continued */
+gdt_end:
--- /dev/null
+/*
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/lib/cpu.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/control_regs.h>
+#include <asm/cpu.h>
+#include <asm/mp.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/processor-flags.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Constructor for a conventional segment GDT (or LDT) entry
+ * This is a macro so it can be used in initialisers
+ */
+#define GDT_ENTRY(flags, base, limit) \
+ ((((base) & 0xff000000ULL) << (56-24)) | \
+ (((flags) & 0x0000f0ffULL) << 40) | \
+ (((limit) & 0x000f0000ULL) << (48-16)) | \
+ (((base) & 0x00ffffffULL) << 16) | \
+ (((limit) & 0x0000ffffULL)))
+
+struct gdt_ptr {
+ u16 len;
+ u32 ptr;
+} __packed;
+
+struct cpu_device_id {
+ unsigned vendor;
+ unsigned device;
+};
+
+struct cpuinfo_x86 {
+ uint8_t x86; /* CPU family */
+ uint8_t x86_vendor; /* CPU vendor */
+ uint8_t x86_model;
+ uint8_t x86_mask;
+};
+
+/*
+ * List of cpu vendor strings along with their normalized
+ * id values.
+ */
+static const struct {
+ int vendor;
+ const char *name;
+} x86_vendors[] = {
+ { X86_VENDOR_INTEL, "GenuineIntel", },
+ { X86_VENDOR_CYRIX, "CyrixInstead", },
+ { X86_VENDOR_AMD, "AuthenticAMD", },
+ { X86_VENDOR_UMC, "UMC UMC UMC ", },
+ { X86_VENDOR_NEXGEN, "NexGenDriven", },
+ { X86_VENDOR_CENTAUR, "CentaurHauls", },
+ { X86_VENDOR_RISE, "RiseRiseRise", },
+ { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
+ { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
+ { X86_VENDOR_NSC, "Geode by NSC", },
+ { X86_VENDOR_SIS, "SiS SiS SiS ", },
+};
+
+static void load_ds(u32 segment)
+{
+ asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_es(u32 segment)
+{
+ asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_fs(u32 segment)
+{
+ asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_gs(u32 segment)
+{
+ asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_ss(u32 segment)
+{
+ asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_gdt(const u64 *boot_gdt, u16 num_entries)
+{
+ struct gdt_ptr gdt;
+
+ gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
+ gdt.ptr = (ulong)boot_gdt;
+
+ asm volatile("lgdtl %0\n" : : "m" (gdt));
+}
+
+void arch_setup_gd(gd_t *new_gd)
+{
+ u64 *gdt_addr;
+
+ gdt_addr = new_gd->arch.gdt;
+
+ /*
+ * CS: code, read/execute, 4 GB, base 0
+ *
+ * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
+ */
+ gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
+ gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
+
+ /* DS: data, read/write, 4 GB, base 0 */
+ gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
+
+ /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
+ new_gd->arch.gd_addr = new_gd;
+ gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
+ (ulong)&new_gd->arch.gd_addr, 0xfffff);
+
+ /* 16-bit CS: code, read/execute, 64 kB, base 0 */
+ gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
+
+ /* 16-bit DS: data, read/write, 64 kB, base 0 */
+ gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
+
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
+ gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
+
+ load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
+ load_ds(X86_GDT_ENTRY_32BIT_DS);
+ load_es(X86_GDT_ENTRY_32BIT_DS);
+ load_gs(X86_GDT_ENTRY_32BIT_DS);
+ load_ss(X86_GDT_ENTRY_32BIT_DS);
+ load_fs(X86_GDT_ENTRY_32BIT_FS);
+}
+
+#ifdef CONFIG_HAVE_FSP
+/*
+ * Setup FSP execution environment GDT
+ *
+ * Per Intel FSP external architecture specification, before calling any FSP
+ * APIs, we need make sure the system is in flat 32-bit mode and both the code
+ * and data selectors should have full 4GB access range. Here we reuse the one
+ * we used in arch/x86/cpu/start16.S, and reload the segement registers.
+ */
+void setup_fsp_gdt(void)
+{
+ load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
+ load_ds(X86_GDT_ENTRY_32BIT_DS);
+ load_ss(X86_GDT_ENTRY_32BIT_DS);
+ load_es(X86_GDT_ENTRY_32BIT_DS);
+ load_fs(X86_GDT_ENTRY_32BIT_DS);
+ load_gs(X86_GDT_ENTRY_32BIT_DS);
+}
+#endif
+
+/*
+ * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
+ * by the fact that they preserve the flags across the division of 5/2.
+ * PII and PPro exhibit this behavior too, but they have cpuid available.
+ */
+
+/*
+ * Perform the Cyrix 5/2 test. A Cyrix won't change
+ * the flags, while other 486 chips will.
+ */
+static inline int test_cyrix_52div(void)
+{
+ unsigned int test;
+
+ __asm__ __volatile__(
+ "sahf\n\t" /* clear flags (%eax = 0x0005) */
+ "div %b2\n\t" /* divide 5 by 2 */
+ "lahf" /* store flags into %ah */
+ : "=a" (test)
+ : "0" (5), "q" (2)
+ : "cc");
+
+ /* AH is 0x02 on Cyrix after the divide.. */
+ return (unsigned char) (test >> 8) == 0x02;
+}
+
+/*
+ * Detect a NexGen CPU running without BIOS hypercode new enough
+ * to have CPUID. (Thanks to Herbert Oppmann)
+ */
+static int deep_magic_nexgen_probe(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ " movw $0x5555, %%ax\n"
+ " xorw %%dx,%%dx\n"
+ " movw $2, %%cx\n"
+ " divw %%cx\n"
+ " movl $0, %%eax\n"
+ " jnz 1f\n"
+ " movl $1, %%eax\n"
+ "1:\n"
+ : "=a" (ret) : : "cx", "dx");
+ return ret;
+}
+
+static bool has_cpuid(void)
+{
+ return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static bool has_mtrr(void)
+{
+ return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
+}
+
+static int build_vendor_name(char *vendor_name)
+{
+ struct cpuid_result result;
+ result = cpuid(0x00000000);
+ unsigned int *name_as_ints = (unsigned int *)vendor_name;
+
+ name_as_ints[0] = result.ebx;
+ name_as_ints[1] = result.edx;
+ name_as_ints[2] = result.ecx;
+
+ return result.eax;
+}
+
+static void identify_cpu(struct cpu_device_id *cpu)
+{
+ char vendor_name[16];
+ int i;
+
+ vendor_name[0] = '\0'; /* Unset */
+ cpu->device = 0; /* fix gcc 4.4.4 warning */
+
+ /* Find the id and vendor_name */
+ if (!has_cpuid()) {
+ /* Its a 486 if we can modify the AC flag */
+ if (flag_is_changeable_p(X86_EFLAGS_AC))
+ cpu->device = 0x00000400; /* 486 */
+ else
+ cpu->device = 0x00000300; /* 386 */
+ if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
+ memcpy(vendor_name, "CyrixInstead", 13);
+ /* If we ever care we can enable cpuid here */
+ }
+ /* Detect NexGen with old hypercode */
+ else if (deep_magic_nexgen_probe())
+ memcpy(vendor_name, "NexGenDriven", 13);
+ }
+ if (has_cpuid()) {
+ int cpuid_level;
+
+ cpuid_level = build_vendor_name(vendor_name);
+ vendor_name[12] = '\0';
+
+ /* Intel-defined flags: level 0x00000001 */
+ if (cpuid_level >= 0x00000001) {
+ cpu->device = cpuid_eax(0x00000001);
+ } else {
+ /* Have CPUID level 0 only unheard of */
+ cpu->device = 0x00000400;
+ }
+ }
+ cpu->vendor = X86_VENDOR_UNKNOWN;
+ for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
+ if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
+ cpu->vendor = x86_vendors[i].vendor;
+ break;
+ }
+ }
+}
+
+static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
+{
+ c->x86 = (tfms >> 8) & 0xf;
+ c->x86_model = (tfms >> 4) & 0xf;
+ c->x86_mask = tfms & 0xf;
+ if (c->x86 == 0xf)
+ c->x86 += (tfms >> 20) & 0xff;
+ if (c->x86 >= 0x6)
+ c->x86_model += ((tfms >> 16) & 0xF) << 4;
+}
+
+u32 cpu_get_family_model(void)
+{
+ return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+ return gd->arch.x86_mask;
+}
+
+int x86_cpu_init_f(void)
+{
+ const u32 em_rst = ~X86_CR0_EM;
+ const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
+ if (ll_boot_init()) {
+ /* initialize FPU, reset EM, set MP and NE */
+ asm ("fninit\n" \
+ "movl %%cr0, %%eax\n" \
+ "andl %0, %%eax\n" \
+ "orl %1, %%eax\n" \
+ "movl %%eax, %%cr0\n" \
+ : : "i" (em_rst), "i" (mp_ne_set) : "eax");
+ }
+
+ /* identify CPU via cpuid and store the decoded info into gd->arch */
+ if (has_cpuid()) {
+ struct cpu_device_id cpu;
+ struct cpuinfo_x86 c;
+
+ identify_cpu(&cpu);
+ get_fms(&c, cpu.device);
+ gd->arch.x86 = c.x86;
+ gd->arch.x86_vendor = cpu.vendor;
+ gd->arch.x86_model = c.x86_model;
+ gd->arch.x86_mask = c.x86_mask;
+ gd->arch.x86_device = cpu.device;
+
+ gd->arch.has_mtrr = has_mtrr();
+ }
+ /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+ gd->pci_ram_top = 0x80000000U;
+
+ /* Configure fixed range MTRRs for some legacy regions */
+ if (gd->arch.has_mtrr) {
+ u64 mtrr_cap;
+
+ mtrr_cap = native_read_msr(MTRR_CAP_MSR);
+ if (mtrr_cap & MTRR_CAP_FIX) {
+ /* Mark the VGA RAM area as uncacheable */
+ native_write_msr(MTRR_FIX_16K_A0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+ /*
+ * Mark the PCI ROM area as cacheable to improve ROM
+ * execution performance.
+ */
+ native_write_msr(MTRR_FIX_4K_C0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_C8000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_D0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_D8000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+ /* Enable the fixed range MTRRs */
+ msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
+ }
+ }
+
+#ifdef CONFIG_I8254_TIMER
+ /* Set up the i8254 timer if required */
+ i8254_init();
+#endif
+
+ return 0;
+}
+
+void x86_enable_caches(void)
+{
+ unsigned long cr0;
+
+ cr0 = read_cr0();
+ cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
+ write_cr0(cr0);
+ wbinvd();
+}
+void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
+
+void x86_disable_caches(void)
+{
+ unsigned long cr0;
+
+ cr0 = read_cr0();
+ cr0 |= X86_CR0_NW | X86_CR0_CD;
+ wbinvd();
+ write_cr0(cr0);
+ wbinvd();
+}
+void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
+
+int dcache_status(void)
+{
+ return !(read_cr0() & X86_CR0_CD);
+}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+ __asm__ __volatile__(
+ /* Load the page table address */
+ "movl %0, %%cr3\n"
+ /* Enable pae */
+ "movl %%cr4, %%eax\n"
+ "orl $0x00000020, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ /* Enable paging */
+ "movl %%cr0, %%eax\n"
+ "orl $0x80000000, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ :
+ : "r" (cr3)
+ : "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+ /* Turn off paging */
+ __asm__ __volatile__ (
+ /* Disable paging */
+ "movl %%cr0, %%eax\n"
+ "andl $0x7fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ /* Disable pae */
+ "movl %%cr4, %%eax\n"
+ "andl $0xffffffdf, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ :
+ :
+ : "eax");
+}
+
+static bool can_detect_long_mode(void)
+{
+ return cpuid_eax(0x80000000) > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+ return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
+
+#define PAGETABLE_SIZE (6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+ uint i;
+
+ memset(pgtable, '\0', PAGETABLE_SIZE);
+
+ /* Level 4 needs a single entry */
+ pgtable[0] = (ulong)&pgtable[1024] + 7;
+
+ /* Level 3 has one 64-bit entry for each GiB of memory */
+ for (i = 0; i < 4; i++)
+ pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
+
+ /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+ for (i = 0; i < 2048; i++)
+ pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+ uint32_t *pgtable;
+
+ pgtable = memalign(4096, PAGETABLE_SIZE);
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+ cpu_call64((ulong)pgtable, setup_base, target);
+ free(pgtable);
+
+ return -EFAULT;
+}
+
+/*
+ * Jump from SPL to U-Boot
+ *
+ * This function is work-in-progress with many issues to resolve.
+ *
+ * It works by setting up several regions:
+ * ptr - a place to put the code that jumps into 64-bit mode
+ * gdt - a place to put the global descriptor table
+ * pgtable - a place to put the page tables
+ *
+ * The cpu_call64() code is copied from ROM and then manually patched so that
+ * it has the correct GDT address in RAM. U-Boot is copied from ROM into
+ * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
+ * which changes to 64-bit mode and starts U-Boot.
+ */
+int cpu_jump_to_64bit_uboot(ulong target)
+{
+ typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
+ uint32_t *pgtable;
+ func_t func;
+
+ /* TODO(sjg@chromium.org): Find a better place for this */
+ pgtable = (uint32_t *)0x1000000;
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+
+ /* TODO(sjg@chromium.org): Find a better place for this */
+ char *ptr = (char *)0x3000000;
+ char *gdt = (char *)0x3100000;
+
+ extern char gdt64[];
+
+ memcpy(ptr, cpu_call64, 0x1000);
+ memcpy(gdt, gdt64, 0x100);
+
+ /*
+ * TODO(sjg@chromium.org): This manually inserts the pointers into
+ * the code. Tidy this up to avoid this.
+ */
+ func = (func_t)ptr;
+ ulong ofs = (ulong)cpu_call64 - (ulong)ptr;
+ *(ulong *)(ptr + 7) = (ulong)gdt;
+ *(ulong *)(ptr + 0xc) = (ulong)gdt + 2;
+ *(ulong *)(ptr + 0x13) = (ulong)gdt;
+ *(ulong *)(ptr + 0x117 - 0xd4) -= ofs;
+
+ /*
+ * Copy U-Boot from ROM
+ * TODO(sjg@chromium.org): Figure out a way to get the text base
+ * correctly here, and in the device-tree binman definition.
+ *
+ * Also consider using FIT so we get the correct image length and
+ * parameters.
+ */
+ memcpy((char *)target, (char *)0xfff00000, 0x100000);
+
+ /* Jump to U-Boot */
+ func((ulong)pgtable, 0, (ulong)target);
+
+ return -EFAULT;
+}
+
+#ifdef CONFIG_SMP
+static int enable_smis(struct udevice *cpu, void *unused)
+{
+ return 0;
+}
+
+static struct mp_flight_record mp_steps[] = {
+ MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
+ /* Wait for APs to finish initialization before proceeding */
+ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
+};
+
+int x86_mp_init(void)
+{
+ struct mp_params mp_params;
+
+ mp_params.parallel_microcode_load = 0,
+ mp_params.flight_plan = &mp_steps[0];
+ mp_params.num_records = ARRAY_SIZE(mp_steps);
+ mp_params.microcode_pointer = 0;
+
+ if (mp_init(&mp_params)) {
+ printf("Warning: MP init failure\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * Portions of this file are derived from the Linux kernel source
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/control_regs.h>
+#include <asm/i8259.h>
+#include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/processor-flags.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DECLARE_INTERRUPT(x) \
+ ".globl irq_"#x"\n" \
+ ".hidden irq_"#x"\n" \
+ ".type irq_"#x", @function\n" \
+ "irq_"#x":\n" \
+ "pushl $"#x"\n" \
+ "jmp irq_common_entry\n"
+
+static char *exceptions[] = {
+ "Divide Error",
+ "Debug",
+ "NMI Interrupt",
+ "Breakpoint",
+ "Overflow",
+ "BOUND Range Exceeded",
+ "Invalid Opcode (Undefined Opcode)",
+ "Device Not Avaiable (No Math Coprocessor)",
+ "Double Fault",
+ "Coprocessor Segment Overrun",
+ "Invalid TSS",
+ "Segment Not Present",
+ "Stack Segment Fault",
+ "General Protection",
+ "Page Fault",
+ "Reserved",
+ "x87 FPU Floating-Point Error",
+ "Alignment Check",
+ "Machine Check",
+ "SIMD Floating-Point Exception",
+ "Virtualization Exception",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved",
+ "Reserved"
+};
+
+static void dump_regs(struct irq_regs *regs)
+{
+ unsigned long cs, eip, eflags;
+ unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
+ unsigned long d0, d1, d2, d3, d6, d7;
+ unsigned long sp;
+
+ /*
+ * Some exceptions cause an error code to be saved on the current stack
+ * after the EIP value. We should extract CS/EIP/EFLAGS from different
+ * position on the stack based on the exception number.
+ */
+ switch (regs->irq_id) {
+ case EXC_DF:
+ case EXC_TS:
+ case EXC_NP:
+ case EXC_SS:
+ case EXC_GP:
+ case EXC_PF:
+ case EXC_AC:
+ cs = regs->context.ctx2.xcs;
+ eip = regs->context.ctx2.eip;
+ eflags = regs->context.ctx2.eflags;
+ /* We should fix up the ESP due to error code */
+ regs->esp += 4;
+ break;
+ default:
+ cs = regs->context.ctx1.xcs;
+ eip = regs->context.ctx1.eip;
+ eflags = regs->context.ctx1.eflags;
+ break;
+ }
+
+ printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
+ (u16)cs, eip, eflags);
+ if (gd->flags & GD_FLG_RELOC)
+ printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
+
+ printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
+ regs->eax, regs->ebx, regs->ecx, regs->edx);
+ printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
+ regs->esi, regs->edi, regs->ebp, regs->esp);
+ printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
+ (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
+ (u16)regs->xgs, (u16)regs->xss);
+
+ cr0 = read_cr0();
+ cr2 = read_cr2();
+ cr3 = read_cr3();
+ cr4 = read_cr4();
+
+ printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
+ cr0, cr2, cr3, cr4);
+
+ d0 = get_debugreg(0);
+ d1 = get_debugreg(1);
+ d2 = get_debugreg(2);
+ d3 = get_debugreg(3);
+
+ printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
+ d0, d1, d2, d3);
+
+ d6 = get_debugreg(6);
+ d7 = get_debugreg(7);
+ printf("DR6: %08lx DR7: %08lx\n",
+ d6, d7);
+
+ printf("Stack:\n");
+ sp = regs->esp;
+
+ sp += 64;
+
+ while (sp > (regs->esp - 16)) {
+ if (sp == regs->esp)
+ printf("--->");
+ else
+ printf(" ");
+ printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
+ sp -= 4;
+ }
+}
+
+static void do_exception(struct irq_regs *regs)
+{
+ printf("%s\n", exceptions[regs->irq_id]);
+ dump_regs(regs);
+ hang();
+}
+
+struct idt_entry {
+ u16 base_low;
+ u16 selector;
+ u8 res;
+ u8 access;
+ u16 base_high;
+} __packed;
+
+struct desc_ptr {
+ unsigned short size;
+ unsigned long address;
+} __packed;
+
+struct idt_entry idt[256] __aligned(16);
+
+struct desc_ptr idt_ptr;
+
+static inline void load_idt(const struct desc_ptr *dtr)
+{
+ asm volatile("cs lidt %0" : : "m" (*dtr));
+}
+
+void set_vector(u8 intnum, void *routine)
+{
+ idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
+ idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
+}
+
+/*
+ * Ideally these would be defined static to avoid a checkpatch warning, but
+ * the compiler cannot see them in the inline asm and complains that they
+ * aren't defined
+ */
+void irq_0(void);
+void irq_1(void);
+
+int cpu_init_interrupts(void)
+{
+ int i;
+
+ int irq_entry_size = irq_1 - irq_0;
+ void *irq_entry = (void *)irq_0;
+
+ /* Setup the IDT */
+ for (i = 0; i < 256; i++) {
+ idt[i].access = 0x8e;
+ idt[i].res = 0;
+ idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
+ set_vector(i, irq_entry);
+ irq_entry += irq_entry_size;
+ }
+
+ idt_ptr.size = 256 * 8 - 1;
+ idt_ptr.address = (unsigned long) idt;
+
+ load_idt(&idt_ptr);
+
+ return 0;
+}
+
+void *x86_get_idt(void)
+{
+ return &idt_ptr;
+}
+
+void __do_irq(int irq)
+{
+ printf("Unhandled IRQ : %d\n", irq);
+}
+void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
+
+void enable_interrupts(void)
+{
+ asm("sti\n");
+}
+
+int disable_interrupts(void)
+{
+ long flags;
+
+#if CONFIG_IS_ENABLED(X86_64)
+ asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
+#else
+ asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
+#endif
+ return flags & X86_EFLAGS_IF;
+}
+
+int interrupt_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ /* Try to set up the interrupt router, but don't require one */
+ ret = uclass_first_device_err(UCLASS_IRQ, &dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+
+ /*
+ * When running as an EFI application we are not in control of
+ * interrupts and should leave them alone.
+ */
+#ifndef CONFIG_EFI_APP
+ /* Just in case... */
+ disable_interrupts();
+
+#ifdef CONFIG_I8259_PIC
+ /* Initialize the master/slave i8259 pic */
+ i8259_init();
+#endif
+
+ lapic_setup();
+
+ /* Initialize core interrupt and exception functionality of CPU */
+ cpu_init_interrupts();
+
+ /*
+ * It is now safe to enable interrupts.
+ *
+ * TODO(sjg@chromium.org): But we don't handle these correctly when
+ * booted from EFI.
+ */
+ if (ll_boot_init())
+ enable_interrupts();
+#endif
+
+ return 0;
+}
+
+/* IRQ Low-Level Service Routine */
+void irq_llsr(struct irq_regs *regs)
+{
+ /*
+ * For detailed description of each exception, refer to:
+ * Intel® 64 and IA-32 Architectures Software Developer's Manual
+ * Volume 1: Basic Architecture
+ * Order Number: 253665-029US, November 2008
+ * Table 6-1. Exceptions and Interrupts
+ */
+ if (regs->irq_id < 32) {
+ /* Architecture defined exception */
+ do_exception(regs);
+ } else {
+ /* Hardware or User IRQ */
+ do_irq(regs->irq_id);
+ }
+}
+
+/*
+ * OK - This looks really horrible, but it serves a purpose - It helps create
+ * fully relocatable code.
+ * - The call to irq_llsr will be a relative jump
+ * - The IRQ entries will be guaranteed to be in order
+ * Interrupt entries are now very small (a push and a jump) but they are
+ * now slower (all registers pushed on stack which provides complete
+ * crash dumps in the low level handlers
+ *
+ * Interrupt Entry Point:
+ * - Interrupt has caused eflags, CS and EIP to be pushed
+ * - Interrupt Vector Handler has pushed orig_eax
+ * - pt_regs.esp needs to be adjusted by 40 bytes:
+ * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
+ * 4 bytes pushed by vector handler (irq_id)
+ * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
+ * NOTE: Only longs are pushed on/popped off the stack!
+ */
+asm(".globl irq_common_entry\n" \
+ ".hidden irq_common_entry\n" \
+ ".type irq_common_entry, @function\n" \
+ "irq_common_entry:\n" \
+ "cld\n" \
+ "pushl %ss\n" \
+ "pushl %gs\n" \
+ "pushl %fs\n" \
+ "pushl %es\n" \
+ "pushl %ds\n" \
+ "pushl %eax\n" \
+ "movl %esp, %eax\n" \
+ "addl $40, %eax\n" \
+ "pushl %eax\n" \
+ "pushl %ebp\n" \
+ "pushl %edi\n" \
+ "pushl %esi\n" \
+ "pushl %edx\n" \
+ "pushl %ecx\n" \
+ "pushl %ebx\n" \
+ "mov %esp, %eax\n" \
+ "call irq_llsr\n" \
+ "popl %ebx\n" \
+ "popl %ecx\n" \
+ "popl %edx\n" \
+ "popl %esi\n" \
+ "popl %edi\n" \
+ "popl %ebp\n" \
+ "popl %eax\n" \
+ "popl %eax\n" \
+ "popl %ds\n" \
+ "popl %es\n" \
+ "popl %fs\n" \
+ "popl %gs\n" \
+ "popl %ss\n" \
+ "add $4, %esp\n" \
+ "iret\n" \
+ DECLARE_INTERRUPT(0) \
+ DECLARE_INTERRUPT(1) \
+ DECLARE_INTERRUPT(2) \
+ DECLARE_INTERRUPT(3) \
+ DECLARE_INTERRUPT(4) \
+ DECLARE_INTERRUPT(5) \
+ DECLARE_INTERRUPT(6) \
+ DECLARE_INTERRUPT(7) \
+ DECLARE_INTERRUPT(8) \
+ DECLARE_INTERRUPT(9) \
+ DECLARE_INTERRUPT(10) \
+ DECLARE_INTERRUPT(11) \
+ DECLARE_INTERRUPT(12) \
+ DECLARE_INTERRUPT(13) \
+ DECLARE_INTERRUPT(14) \
+ DECLARE_INTERRUPT(15) \
+ DECLARE_INTERRUPT(16) \
+ DECLARE_INTERRUPT(17) \
+ DECLARE_INTERRUPT(18) \
+ DECLARE_INTERRUPT(19) \
+ DECLARE_INTERRUPT(20) \
+ DECLARE_INTERRUPT(21) \
+ DECLARE_INTERRUPT(22) \
+ DECLARE_INTERRUPT(23) \
+ DECLARE_INTERRUPT(24) \
+ DECLARE_INTERRUPT(25) \
+ DECLARE_INTERRUPT(26) \
+ DECLARE_INTERRUPT(27) \
+ DECLARE_INTERRUPT(28) \
+ DECLARE_INTERRUPT(29) \
+ DECLARE_INTERRUPT(30) \
+ DECLARE_INTERRUPT(31) \
+ DECLARE_INTERRUPT(32) \
+ DECLARE_INTERRUPT(33) \
+ DECLARE_INTERRUPT(34) \
+ DECLARE_INTERRUPT(35) \
+ DECLARE_INTERRUPT(36) \
+ DECLARE_INTERRUPT(37) \
+ DECLARE_INTERRUPT(38) \
+ DECLARE_INTERRUPT(39) \
+ DECLARE_INTERRUPT(40) \
+ DECLARE_INTERRUPT(41) \
+ DECLARE_INTERRUPT(42) \
+ DECLARE_INTERRUPT(43) \
+ DECLARE_INTERRUPT(44) \
+ DECLARE_INTERRUPT(45) \
+ DECLARE_INTERRUPT(46) \
+ DECLARE_INTERRUPT(47) \
+ DECLARE_INTERRUPT(48) \
+ DECLARE_INTERRUPT(49) \
+ DECLARE_INTERRUPT(50) \
+ DECLARE_INTERRUPT(51) \
+ DECLARE_INTERRUPT(52) \
+ DECLARE_INTERRUPT(53) \
+ DECLARE_INTERRUPT(54) \
+ DECLARE_INTERRUPT(55) \
+ DECLARE_INTERRUPT(56) \
+ DECLARE_INTERRUPT(57) \
+ DECLARE_INTERRUPT(58) \
+ DECLARE_INTERRUPT(59) \
+ DECLARE_INTERRUPT(60) \
+ DECLARE_INTERRUPT(61) \
+ DECLARE_INTERRUPT(62) \
+ DECLARE_INTERRUPT(63) \
+ DECLARE_INTERRUPT(64) \
+ DECLARE_INTERRUPT(65) \
+ DECLARE_INTERRUPT(66) \
+ DECLARE_INTERRUPT(67) \
+ DECLARE_INTERRUPT(68) \
+ DECLARE_INTERRUPT(69) \
+ DECLARE_INTERRUPT(70) \
+ DECLARE_INTERRUPT(71) \
+ DECLARE_INTERRUPT(72) \
+ DECLARE_INTERRUPT(73) \
+ DECLARE_INTERRUPT(74) \
+ DECLARE_INTERRUPT(75) \
+ DECLARE_INTERRUPT(76) \
+ DECLARE_INTERRUPT(77) \
+ DECLARE_INTERRUPT(78) \
+ DECLARE_INTERRUPT(79) \
+ DECLARE_INTERRUPT(80) \
+ DECLARE_INTERRUPT(81) \
+ DECLARE_INTERRUPT(82) \
+ DECLARE_INTERRUPT(83) \
+ DECLARE_INTERRUPT(84) \
+ DECLARE_INTERRUPT(85) \
+ DECLARE_INTERRUPT(86) \
+ DECLARE_INTERRUPT(87) \
+ DECLARE_INTERRUPT(88) \
+ DECLARE_INTERRUPT(89) \
+ DECLARE_INTERRUPT(90) \
+ DECLARE_INTERRUPT(91) \
+ DECLARE_INTERRUPT(92) \
+ DECLARE_INTERRUPT(93) \
+ DECLARE_INTERRUPT(94) \
+ DECLARE_INTERRUPT(95) \
+ DECLARE_INTERRUPT(97) \
+ DECLARE_INTERRUPT(96) \
+ DECLARE_INTERRUPT(98) \
+ DECLARE_INTERRUPT(99) \
+ DECLARE_INTERRUPT(100) \
+ DECLARE_INTERRUPT(101) \
+ DECLARE_INTERRUPT(102) \
+ DECLARE_INTERRUPT(103) \
+ DECLARE_INTERRUPT(104) \
+ DECLARE_INTERRUPT(105) \
+ DECLARE_INTERRUPT(106) \
+ DECLARE_INTERRUPT(107) \
+ DECLARE_INTERRUPT(108) \
+ DECLARE_INTERRUPT(109) \
+ DECLARE_INTERRUPT(110) \
+ DECLARE_INTERRUPT(111) \
+ DECLARE_INTERRUPT(112) \
+ DECLARE_INTERRUPT(113) \
+ DECLARE_INTERRUPT(114) \
+ DECLARE_INTERRUPT(115) \
+ DECLARE_INTERRUPT(116) \
+ DECLARE_INTERRUPT(117) \
+ DECLARE_INTERRUPT(118) \
+ DECLARE_INTERRUPT(119) \
+ DECLARE_INTERRUPT(120) \
+ DECLARE_INTERRUPT(121) \
+ DECLARE_INTERRUPT(122) \
+ DECLARE_INTERRUPT(123) \
+ DECLARE_INTERRUPT(124) \
+ DECLARE_INTERRUPT(125) \
+ DECLARE_INTERRUPT(126) \
+ DECLARE_INTERRUPT(127) \
+ DECLARE_INTERRUPT(128) \
+ DECLARE_INTERRUPT(129) \
+ DECLARE_INTERRUPT(130) \
+ DECLARE_INTERRUPT(131) \
+ DECLARE_INTERRUPT(132) \
+ DECLARE_INTERRUPT(133) \
+ DECLARE_INTERRUPT(134) \
+ DECLARE_INTERRUPT(135) \
+ DECLARE_INTERRUPT(136) \
+ DECLARE_INTERRUPT(137) \
+ DECLARE_INTERRUPT(138) \
+ DECLARE_INTERRUPT(139) \
+ DECLARE_INTERRUPT(140) \
+ DECLARE_INTERRUPT(141) \
+ DECLARE_INTERRUPT(142) \
+ DECLARE_INTERRUPT(143) \
+ DECLARE_INTERRUPT(144) \
+ DECLARE_INTERRUPT(145) \
+ DECLARE_INTERRUPT(146) \
+ DECLARE_INTERRUPT(147) \
+ DECLARE_INTERRUPT(148) \
+ DECLARE_INTERRUPT(149) \
+ DECLARE_INTERRUPT(150) \
+ DECLARE_INTERRUPT(151) \
+ DECLARE_INTERRUPT(152) \
+ DECLARE_INTERRUPT(153) \
+ DECLARE_INTERRUPT(154) \
+ DECLARE_INTERRUPT(155) \
+ DECLARE_INTERRUPT(156) \
+ DECLARE_INTERRUPT(157) \
+ DECLARE_INTERRUPT(158) \
+ DECLARE_INTERRUPT(159) \
+ DECLARE_INTERRUPT(160) \
+ DECLARE_INTERRUPT(161) \
+ DECLARE_INTERRUPT(162) \
+ DECLARE_INTERRUPT(163) \
+ DECLARE_INTERRUPT(164) \
+ DECLARE_INTERRUPT(165) \
+ DECLARE_INTERRUPT(166) \
+ DECLARE_INTERRUPT(167) \
+ DECLARE_INTERRUPT(168) \
+ DECLARE_INTERRUPT(169) \
+ DECLARE_INTERRUPT(170) \
+ DECLARE_INTERRUPT(171) \
+ DECLARE_INTERRUPT(172) \
+ DECLARE_INTERRUPT(173) \
+ DECLARE_INTERRUPT(174) \
+ DECLARE_INTERRUPT(175) \
+ DECLARE_INTERRUPT(176) \
+ DECLARE_INTERRUPT(177) \
+ DECLARE_INTERRUPT(178) \
+ DECLARE_INTERRUPT(179) \
+ DECLARE_INTERRUPT(180) \
+ DECLARE_INTERRUPT(181) \
+ DECLARE_INTERRUPT(182) \
+ DECLARE_INTERRUPT(183) \
+ DECLARE_INTERRUPT(184) \
+ DECLARE_INTERRUPT(185) \
+ DECLARE_INTERRUPT(186) \
+ DECLARE_INTERRUPT(187) \
+ DECLARE_INTERRUPT(188) \
+ DECLARE_INTERRUPT(189) \
+ DECLARE_INTERRUPT(190) \
+ DECLARE_INTERRUPT(191) \
+ DECLARE_INTERRUPT(192) \
+ DECLARE_INTERRUPT(193) \
+ DECLARE_INTERRUPT(194) \
+ DECLARE_INTERRUPT(195) \
+ DECLARE_INTERRUPT(196) \
+ DECLARE_INTERRUPT(197) \
+ DECLARE_INTERRUPT(198) \
+ DECLARE_INTERRUPT(199) \
+ DECLARE_INTERRUPT(200) \
+ DECLARE_INTERRUPT(201) \
+ DECLARE_INTERRUPT(202) \
+ DECLARE_INTERRUPT(203) \
+ DECLARE_INTERRUPT(204) \
+ DECLARE_INTERRUPT(205) \
+ DECLARE_INTERRUPT(206) \
+ DECLARE_INTERRUPT(207) \
+ DECLARE_INTERRUPT(208) \
+ DECLARE_INTERRUPT(209) \
+ DECLARE_INTERRUPT(210) \
+ DECLARE_INTERRUPT(211) \
+ DECLARE_INTERRUPT(212) \
+ DECLARE_INTERRUPT(213) \
+ DECLARE_INTERRUPT(214) \
+ DECLARE_INTERRUPT(215) \
+ DECLARE_INTERRUPT(216) \
+ DECLARE_INTERRUPT(217) \
+ DECLARE_INTERRUPT(218) \
+ DECLARE_INTERRUPT(219) \
+ DECLARE_INTERRUPT(220) \
+ DECLARE_INTERRUPT(221) \
+ DECLARE_INTERRUPT(222) \
+ DECLARE_INTERRUPT(223) \
+ DECLARE_INTERRUPT(224) \
+ DECLARE_INTERRUPT(225) \
+ DECLARE_INTERRUPT(226) \
+ DECLARE_INTERRUPT(227) \
+ DECLARE_INTERRUPT(228) \
+ DECLARE_INTERRUPT(229) \
+ DECLARE_INTERRUPT(230) \
+ DECLARE_INTERRUPT(231) \
+ DECLARE_INTERRUPT(232) \
+ DECLARE_INTERRUPT(233) \
+ DECLARE_INTERRUPT(234) \
+ DECLARE_INTERRUPT(235) \
+ DECLARE_INTERRUPT(236) \
+ DECLARE_INTERRUPT(237) \
+ DECLARE_INTERRUPT(238) \
+ DECLARE_INTERRUPT(239) \
+ DECLARE_INTERRUPT(240) \
+ DECLARE_INTERRUPT(241) \
+ DECLARE_INTERRUPT(242) \
+ DECLARE_INTERRUPT(243) \
+ DECLARE_INTERRUPT(244) \
+ DECLARE_INTERRUPT(245) \
+ DECLARE_INTERRUPT(246) \
+ DECLARE_INTERRUPT(247) \
+ DECLARE_INTERRUPT(248) \
+ DECLARE_INTERRUPT(249) \
+ DECLARE_INTERRUPT(250) \
+ DECLARE_INTERRUPT(251) \
+ DECLARE_INTERRUPT(252) \
+ DECLARE_INTERRUPT(253) \
+ DECLARE_INTERRUPT(254) \
+ DECLARE_INTERRUPT(255));
--- /dev/null
+/*
+ * Written by H. Peter Anvin <hpa@zytor.com>
+ * Brought in from Linux v4.4 and modified for U-Boot
+ * From Linux arch/um/sys-i386/setjmp.S
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#define _REGPARM
+
+/*
+ * The jmp_buf is assumed to contain the following, in order:
+ * %ebx
+ * %esp
+ * %ebp
+ * %esi
+ * %edi
+ * <return address>
+ */
+
+ .text
+ .align 4
+ .globl setjmp
+ .type setjmp, @function
+setjmp:
+#ifdef _REGPARM
+ movl %eax, %edx
+#else
+ movl 4(%esp), %edx
+#endif
+ popl %ecx /* Return address, and adjust the stack */
+ xorl %eax, %eax /* Return value */
+ movl %ebx, (%edx)
+ movl %esp, 4(%edx) /* Post-return %esp! */
+ pushl %ecx /* Make the call/return stack happy */
+ movl %ebp, 8(%edx)
+ movl %esi, 12(%edx)
+ movl %edi, 16(%edx)
+ movl %ecx, 20(%edx) /* Return address */
+ ret
+
+ /* Provide function size if needed */
+ .size setjmp, .-setjmp
+
+ .align 4
+ .globl longjmp
+ .type longjmp, @function
+longjmp:
+#ifdef _REGPARM
+ xchgl %eax, %edx
+#else
+ movl 4(%esp), %edx /* jmp_ptr address */
+#endif
+ movl (%edx), %ebx
+ movl 4(%edx), %esp
+ movl 8(%edx), %ebp
+ movl 12(%edx), %esi
+ movl 16(%edx), %edi
+ jmp *20(%edx)
+
+ .size longjmp, .-longjmp
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_HAVE_MRC) += car.o
+ifdef CONFIG_HAVE_MRC
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o
+endif
obj-y += cpu.o
obj-y += lpc.o
-obj-$(CONFIG_HAVE_MRC) += me_status.o
ifndef CONFIG_TARGET_EFI
obj-y += microcode.o
endif
obj-y += pch.o
-obj-$(CONFIG_HAVE_MRC) += report_platform.o
-obj-$(CONFIG_HAVE_MRC) += mrc.o
int count;
int i;
- count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+ count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
"intel,gen-dec", (u32 *)values,
sizeof(values) / sizeof(u32));
if (count < 0)
spd_index = dm_gpio_get_values_as_int(desc, ret);
debug("spd index %d\n", spd_index);
- node = fdt_first_subnode(blob, dev->of_offset);
+ node = fdt_first_subnode(blob, dev_of_offset(dev));
if (node < 0)
return -EINVAL;
for (spd_node = fdt_first_subnode(blob, node);
+++ /dev/null
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * Portions of this file are derived from the Linux kernel source
- * Copyright (C) 1991, 1992 Linus Torvalds
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/cache.h>
-#include <asm/control_regs.h>
-#include <asm/i8259.h>
-#include <asm/interrupt.h>
-#include <asm/io.h>
-#include <asm/lapic.h>
-#include <asm/msr.h>
-#include <asm/processor-flags.h>
-#include <asm/processor.h>
-#include <asm/u-boot-x86.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DECLARE_INTERRUPT(x) \
- ".globl irq_"#x"\n" \
- ".hidden irq_"#x"\n" \
- ".type irq_"#x", @function\n" \
- "irq_"#x":\n" \
- "pushl $"#x"\n" \
- "jmp irq_common_entry\n"
-
-static char *exceptions[] = {
- "Divide Error",
- "Debug",
- "NMI Interrupt",
- "Breakpoint",
- "Overflow",
- "BOUND Range Exceeded",
- "Invalid Opcode (Undefined Opcode)",
- "Device Not Avaiable (No Math Coprocessor)",
- "Double Fault",
- "Coprocessor Segment Overrun",
- "Invalid TSS",
- "Segment Not Present",
- "Stack Segment Fault",
- "General Protection",
- "Page Fault",
- "Reserved",
- "x87 FPU Floating-Point Error",
- "Alignment Check",
- "Machine Check",
- "SIMD Floating-Point Exception",
- "Virtualization Exception",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved",
- "Reserved"
-};
-
-static void dump_regs(struct irq_regs *regs)
-{
- unsigned long cs, eip, eflags;
- unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
- unsigned long d0, d1, d2, d3, d6, d7;
- unsigned long sp;
-
- /*
- * Some exceptions cause an error code to be saved on the current stack
- * after the EIP value. We should extract CS/EIP/EFLAGS from different
- * position on the stack based on the exception number.
- */
- switch (regs->irq_id) {
- case EXC_DF:
- case EXC_TS:
- case EXC_NP:
- case EXC_SS:
- case EXC_GP:
- case EXC_PF:
- case EXC_AC:
- cs = regs->context.ctx2.xcs;
- eip = regs->context.ctx2.eip;
- eflags = regs->context.ctx2.eflags;
- /* We should fix up the ESP due to error code */
- regs->esp += 4;
- break;
- default:
- cs = regs->context.ctx1.xcs;
- eip = regs->context.ctx1.eip;
- eflags = regs->context.ctx1.eflags;
- break;
- }
-
- printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
- (u16)cs, eip, eflags);
- if (gd->flags & GD_FLG_RELOC)
- printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
-
- printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
- regs->eax, regs->ebx, regs->ecx, regs->edx);
- printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
- regs->esi, regs->edi, regs->ebp, regs->esp);
- printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
- (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
- (u16)regs->xgs, (u16)regs->xss);
-
- cr0 = read_cr0();
- cr2 = read_cr2();
- cr3 = read_cr3();
- cr4 = read_cr4();
-
- printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
- cr0, cr2, cr3, cr4);
-
- d0 = get_debugreg(0);
- d1 = get_debugreg(1);
- d2 = get_debugreg(2);
- d3 = get_debugreg(3);
-
- printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
- d0, d1, d2, d3);
-
- d6 = get_debugreg(6);
- d7 = get_debugreg(7);
- printf("DR6: %08lx DR7: %08lx\n",
- d6, d7);
-
- printf("Stack:\n");
- sp = regs->esp;
-
- sp += 64;
-
- while (sp > (regs->esp - 16)) {
- if (sp == regs->esp)
- printf("--->");
- else
- printf(" ");
- printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
- sp -= 4;
- }
-}
-
-static void do_exception(struct irq_regs *regs)
-{
- printf("%s\n", exceptions[regs->irq_id]);
- dump_regs(regs);
- hang();
-}
-
-struct idt_entry {
- u16 base_low;
- u16 selector;
- u8 res;
- u8 access;
- u16 base_high;
-} __packed;
-
-struct desc_ptr {
- unsigned short size;
- unsigned long address;
-} __packed;
-
-struct idt_entry idt[256] __aligned(16);
-
-struct desc_ptr idt_ptr;
-
-static inline void load_idt(const struct desc_ptr *dtr)
-{
- asm volatile("cs lidt %0" : : "m" (*dtr));
-}
-
-void set_vector(u8 intnum, void *routine)
-{
- idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
- idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
-}
-
-/*
- * Ideally these would be defined static to avoid a checkpatch warning, but
- * the compiler cannot see them in the inline asm and complains that they
- * aren't defined
- */
-void irq_0(void);
-void irq_1(void);
-
-int cpu_init_interrupts(void)
-{
- int i;
-
- int irq_entry_size = irq_1 - irq_0;
- void *irq_entry = (void *)irq_0;
-
- /* Setup the IDT */
- for (i = 0; i < 256; i++) {
- idt[i].access = 0x8e;
- idt[i].res = 0;
- idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
- set_vector(i, irq_entry);
- irq_entry += irq_entry_size;
- }
-
- idt_ptr.size = 256 * 8 - 1;
- idt_ptr.address = (unsigned long) idt;
-
- load_idt(&idt_ptr);
-
- return 0;
-}
-
-void *x86_get_idt(void)
-{
- return &idt_ptr;
-}
-
-void __do_irq(int irq)
-{
- printf("Unhandled IRQ : %d\n", irq);
-}
-void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
-
-void enable_interrupts(void)
-{
- asm("sti\n");
-}
-
-int disable_interrupts(void)
-{
- long flags;
-
-#ifdef CONFIG_X86_64
- asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
-#else
- asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
-#endif
- return flags & X86_EFLAGS_IF;
-}
-
-int interrupt_init(void)
-{
- struct udevice *dev;
- int ret;
-
- /* Try to set up the interrupt router, but don't require one */
- ret = uclass_first_device_err(UCLASS_IRQ, &dev);
- if (ret && ret != -ENODEV)
- return ret;
-
- /*
- * When running as an EFI application we are not in control of
- * interrupts and should leave them alone.
- */
-#ifndef CONFIG_EFI_APP
- /* Just in case... */
- disable_interrupts();
-
-#ifdef CONFIG_I8259_PIC
- /* Initialize the master/slave i8259 pic */
- i8259_init();
-#endif
-
- lapic_setup();
-
- /* Initialize core interrupt and exception functionality of CPU */
- cpu_init_interrupts();
-
- /*
- * It is now safe to enable interrupts.
- *
- * TODO(sjg@chromium.org): But we don't handle these correctly when
- * booted from EFI.
- */
- if (ll_boot_init())
- enable_interrupts();
-#endif
-
- return 0;
-}
-
-/* IRQ Low-Level Service Routine */
-void irq_llsr(struct irq_regs *regs)
-{
- /*
- * For detailed description of each exception, refer to:
- * Intel® 64 and IA-32 Architectures Software Developer's Manual
- * Volume 1: Basic Architecture
- * Order Number: 253665-029US, November 2008
- * Table 6-1. Exceptions and Interrupts
- */
- if (regs->irq_id < 32) {
- /* Architecture defined exception */
- do_exception(regs);
- } else {
- /* Hardware or User IRQ */
- do_irq(regs->irq_id);
- }
-}
-
-/*
- * OK - This looks really horrible, but it serves a purpose - It helps create
- * fully relocatable code.
- * - The call to irq_llsr will be a relative jump
- * - The IRQ entries will be guaranteed to be in order
- * Interrupt entries are now very small (a push and a jump) but they are
- * now slower (all registers pushed on stack which provides complete
- * crash dumps in the low level handlers
- *
- * Interrupt Entry Point:
- * - Interrupt has caused eflags, CS and EIP to be pushed
- * - Interrupt Vector Handler has pushed orig_eax
- * - pt_regs.esp needs to be adjusted by 40 bytes:
- * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
- * 4 bytes pushed by vector handler (irq_id)
- * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
- * NOTE: Only longs are pushed on/popped off the stack!
- */
-asm(".globl irq_common_entry\n" \
- ".hidden irq_common_entry\n" \
- ".type irq_common_entry, @function\n" \
- "irq_common_entry:\n" \
- "cld\n" \
- "pushl %ss\n" \
- "pushl %gs\n" \
- "pushl %fs\n" \
- "pushl %es\n" \
- "pushl %ds\n" \
- "pushl %eax\n" \
- "movl %esp, %eax\n" \
- "addl $40, %eax\n" \
- "pushl %eax\n" \
- "pushl %ebp\n" \
- "pushl %edi\n" \
- "pushl %esi\n" \
- "pushl %edx\n" \
- "pushl %ecx\n" \
- "pushl %ebx\n" \
- "mov %esp, %eax\n" \
- "call irq_llsr\n" \
- "popl %ebx\n" \
- "popl %ecx\n" \
- "popl %edx\n" \
- "popl %esi\n" \
- "popl %edi\n" \
- "popl %ebp\n" \
- "popl %eax\n" \
- "popl %eax\n" \
- "popl %ds\n" \
- "popl %es\n" \
- "popl %fs\n" \
- "popl %gs\n" \
- "popl %ss\n" \
- "add $4, %esp\n" \
- "iret\n" \
- DECLARE_INTERRUPT(0) \
- DECLARE_INTERRUPT(1) \
- DECLARE_INTERRUPT(2) \
- DECLARE_INTERRUPT(3) \
- DECLARE_INTERRUPT(4) \
- DECLARE_INTERRUPT(5) \
- DECLARE_INTERRUPT(6) \
- DECLARE_INTERRUPT(7) \
- DECLARE_INTERRUPT(8) \
- DECLARE_INTERRUPT(9) \
- DECLARE_INTERRUPT(10) \
- DECLARE_INTERRUPT(11) \
- DECLARE_INTERRUPT(12) \
- DECLARE_INTERRUPT(13) \
- DECLARE_INTERRUPT(14) \
- DECLARE_INTERRUPT(15) \
- DECLARE_INTERRUPT(16) \
- DECLARE_INTERRUPT(17) \
- DECLARE_INTERRUPT(18) \
- DECLARE_INTERRUPT(19) \
- DECLARE_INTERRUPT(20) \
- DECLARE_INTERRUPT(21) \
- DECLARE_INTERRUPT(22) \
- DECLARE_INTERRUPT(23) \
- DECLARE_INTERRUPT(24) \
- DECLARE_INTERRUPT(25) \
- DECLARE_INTERRUPT(26) \
- DECLARE_INTERRUPT(27) \
- DECLARE_INTERRUPT(28) \
- DECLARE_INTERRUPT(29) \
- DECLARE_INTERRUPT(30) \
- DECLARE_INTERRUPT(31) \
- DECLARE_INTERRUPT(32) \
- DECLARE_INTERRUPT(33) \
- DECLARE_INTERRUPT(34) \
- DECLARE_INTERRUPT(35) \
- DECLARE_INTERRUPT(36) \
- DECLARE_INTERRUPT(37) \
- DECLARE_INTERRUPT(38) \
- DECLARE_INTERRUPT(39) \
- DECLARE_INTERRUPT(40) \
- DECLARE_INTERRUPT(41) \
- DECLARE_INTERRUPT(42) \
- DECLARE_INTERRUPT(43) \
- DECLARE_INTERRUPT(44) \
- DECLARE_INTERRUPT(45) \
- DECLARE_INTERRUPT(46) \
- DECLARE_INTERRUPT(47) \
- DECLARE_INTERRUPT(48) \
- DECLARE_INTERRUPT(49) \
- DECLARE_INTERRUPT(50) \
- DECLARE_INTERRUPT(51) \
- DECLARE_INTERRUPT(52) \
- DECLARE_INTERRUPT(53) \
- DECLARE_INTERRUPT(54) \
- DECLARE_INTERRUPT(55) \
- DECLARE_INTERRUPT(56) \
- DECLARE_INTERRUPT(57) \
- DECLARE_INTERRUPT(58) \
- DECLARE_INTERRUPT(59) \
- DECLARE_INTERRUPT(60) \
- DECLARE_INTERRUPT(61) \
- DECLARE_INTERRUPT(62) \
- DECLARE_INTERRUPT(63) \
- DECLARE_INTERRUPT(64) \
- DECLARE_INTERRUPT(65) \
- DECLARE_INTERRUPT(66) \
- DECLARE_INTERRUPT(67) \
- DECLARE_INTERRUPT(68) \
- DECLARE_INTERRUPT(69) \
- DECLARE_INTERRUPT(70) \
- DECLARE_INTERRUPT(71) \
- DECLARE_INTERRUPT(72) \
- DECLARE_INTERRUPT(73) \
- DECLARE_INTERRUPT(74) \
- DECLARE_INTERRUPT(75) \
- DECLARE_INTERRUPT(76) \
- DECLARE_INTERRUPT(77) \
- DECLARE_INTERRUPT(78) \
- DECLARE_INTERRUPT(79) \
- DECLARE_INTERRUPT(80) \
- DECLARE_INTERRUPT(81) \
- DECLARE_INTERRUPT(82) \
- DECLARE_INTERRUPT(83) \
- DECLARE_INTERRUPT(84) \
- DECLARE_INTERRUPT(85) \
- DECLARE_INTERRUPT(86) \
- DECLARE_INTERRUPT(87) \
- DECLARE_INTERRUPT(88) \
- DECLARE_INTERRUPT(89) \
- DECLARE_INTERRUPT(90) \
- DECLARE_INTERRUPT(91) \
- DECLARE_INTERRUPT(92) \
- DECLARE_INTERRUPT(93) \
- DECLARE_INTERRUPT(94) \
- DECLARE_INTERRUPT(95) \
- DECLARE_INTERRUPT(97) \
- DECLARE_INTERRUPT(96) \
- DECLARE_INTERRUPT(98) \
- DECLARE_INTERRUPT(99) \
- DECLARE_INTERRUPT(100) \
- DECLARE_INTERRUPT(101) \
- DECLARE_INTERRUPT(102) \
- DECLARE_INTERRUPT(103) \
- DECLARE_INTERRUPT(104) \
- DECLARE_INTERRUPT(105) \
- DECLARE_INTERRUPT(106) \
- DECLARE_INTERRUPT(107) \
- DECLARE_INTERRUPT(108) \
- DECLARE_INTERRUPT(109) \
- DECLARE_INTERRUPT(110) \
- DECLARE_INTERRUPT(111) \
- DECLARE_INTERRUPT(112) \
- DECLARE_INTERRUPT(113) \
- DECLARE_INTERRUPT(114) \
- DECLARE_INTERRUPT(115) \
- DECLARE_INTERRUPT(116) \
- DECLARE_INTERRUPT(117) \
- DECLARE_INTERRUPT(118) \
- DECLARE_INTERRUPT(119) \
- DECLARE_INTERRUPT(120) \
- DECLARE_INTERRUPT(121) \
- DECLARE_INTERRUPT(122) \
- DECLARE_INTERRUPT(123) \
- DECLARE_INTERRUPT(124) \
- DECLARE_INTERRUPT(125) \
- DECLARE_INTERRUPT(126) \
- DECLARE_INTERRUPT(127) \
- DECLARE_INTERRUPT(128) \
- DECLARE_INTERRUPT(129) \
- DECLARE_INTERRUPT(130) \
- DECLARE_INTERRUPT(131) \
- DECLARE_INTERRUPT(132) \
- DECLARE_INTERRUPT(133) \
- DECLARE_INTERRUPT(134) \
- DECLARE_INTERRUPT(135) \
- DECLARE_INTERRUPT(136) \
- DECLARE_INTERRUPT(137) \
- DECLARE_INTERRUPT(138) \
- DECLARE_INTERRUPT(139) \
- DECLARE_INTERRUPT(140) \
- DECLARE_INTERRUPT(141) \
- DECLARE_INTERRUPT(142) \
- DECLARE_INTERRUPT(143) \
- DECLARE_INTERRUPT(144) \
- DECLARE_INTERRUPT(145) \
- DECLARE_INTERRUPT(146) \
- DECLARE_INTERRUPT(147) \
- DECLARE_INTERRUPT(148) \
- DECLARE_INTERRUPT(149) \
- DECLARE_INTERRUPT(150) \
- DECLARE_INTERRUPT(151) \
- DECLARE_INTERRUPT(152) \
- DECLARE_INTERRUPT(153) \
- DECLARE_INTERRUPT(154) \
- DECLARE_INTERRUPT(155) \
- DECLARE_INTERRUPT(156) \
- DECLARE_INTERRUPT(157) \
- DECLARE_INTERRUPT(158) \
- DECLARE_INTERRUPT(159) \
- DECLARE_INTERRUPT(160) \
- DECLARE_INTERRUPT(161) \
- DECLARE_INTERRUPT(162) \
- DECLARE_INTERRUPT(163) \
- DECLARE_INTERRUPT(164) \
- DECLARE_INTERRUPT(165) \
- DECLARE_INTERRUPT(166) \
- DECLARE_INTERRUPT(167) \
- DECLARE_INTERRUPT(168) \
- DECLARE_INTERRUPT(169) \
- DECLARE_INTERRUPT(170) \
- DECLARE_INTERRUPT(171) \
- DECLARE_INTERRUPT(172) \
- DECLARE_INTERRUPT(173) \
- DECLARE_INTERRUPT(174) \
- DECLARE_INTERRUPT(175) \
- DECLARE_INTERRUPT(176) \
- DECLARE_INTERRUPT(177) \
- DECLARE_INTERRUPT(178) \
- DECLARE_INTERRUPT(179) \
- DECLARE_INTERRUPT(180) \
- DECLARE_INTERRUPT(181) \
- DECLARE_INTERRUPT(182) \
- DECLARE_INTERRUPT(183) \
- DECLARE_INTERRUPT(184) \
- DECLARE_INTERRUPT(185) \
- DECLARE_INTERRUPT(186) \
- DECLARE_INTERRUPT(187) \
- DECLARE_INTERRUPT(188) \
- DECLARE_INTERRUPT(189) \
- DECLARE_INTERRUPT(190) \
- DECLARE_INTERRUPT(191) \
- DECLARE_INTERRUPT(192) \
- DECLARE_INTERRUPT(193) \
- DECLARE_INTERRUPT(194) \
- DECLARE_INTERRUPT(195) \
- DECLARE_INTERRUPT(196) \
- DECLARE_INTERRUPT(197) \
- DECLARE_INTERRUPT(198) \
- DECLARE_INTERRUPT(199) \
- DECLARE_INTERRUPT(200) \
- DECLARE_INTERRUPT(201) \
- DECLARE_INTERRUPT(202) \
- DECLARE_INTERRUPT(203) \
- DECLARE_INTERRUPT(204) \
- DECLARE_INTERRUPT(205) \
- DECLARE_INTERRUPT(206) \
- DECLARE_INTERRUPT(207) \
- DECLARE_INTERRUPT(208) \
- DECLARE_INTERRUPT(209) \
- DECLARE_INTERRUPT(210) \
- DECLARE_INTERRUPT(211) \
- DECLARE_INTERRUPT(212) \
- DECLARE_INTERRUPT(213) \
- DECLARE_INTERRUPT(214) \
- DECLARE_INTERRUPT(215) \
- DECLARE_INTERRUPT(216) \
- DECLARE_INTERRUPT(217) \
- DECLARE_INTERRUPT(218) \
- DECLARE_INTERRUPT(219) \
- DECLARE_INTERRUPT(220) \
- DECLARE_INTERRUPT(221) \
- DECLARE_INTERRUPT(222) \
- DECLARE_INTERRUPT(223) \
- DECLARE_INTERRUPT(224) \
- DECLARE_INTERRUPT(225) \
- DECLARE_INTERRUPT(226) \
- DECLARE_INTERRUPT(227) \
- DECLARE_INTERRUPT(228) \
- DECLARE_INTERRUPT(229) \
- DECLARE_INTERRUPT(230) \
- DECLARE_INTERRUPT(231) \
- DECLARE_INTERRUPT(232) \
- DECLARE_INTERRUPT(233) \
- DECLARE_INTERRUPT(234) \
- DECLARE_INTERRUPT(235) \
- DECLARE_INTERRUPT(236) \
- DECLARE_INTERRUPT(237) \
- DECLARE_INTERRUPT(238) \
- DECLARE_INTERRUPT(239) \
- DECLARE_INTERRUPT(240) \
- DECLARE_INTERRUPT(241) \
- DECLARE_INTERRUPT(242) \
- DECLARE_INTERRUPT(243) \
- DECLARE_INTERRUPT(244) \
- DECLARE_INTERRUPT(245) \
- DECLARE_INTERRUPT(246) \
- DECLARE_INTERRUPT(247) \
- DECLARE_INTERRUPT(248) \
- DECLARE_INTERRUPT(249) \
- DECLARE_INTERRUPT(250) \
- DECLARE_INTERRUPT(251) \
- DECLARE_INTERRUPT(252) \
- DECLARE_INTERRUPT(253) \
- DECLARE_INTERRUPT(254) \
- DECLARE_INTERRUPT(255));
DECLARE_GLOBAL_DATA_PTR;
-static struct irq_routing_table *pirq_routing_table;
-
bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
{
struct irq_router *priv = dev_get_priv(dev);
if (priv->config == PIRQ_VIA_PCI)
dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
else
- pirq = readb(priv->ibase + LINK_N2V(link, base));
+ pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base));
pirq &= 0xf;
if (priv->config == PIRQ_VIA_PCI)
dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
else
- writeb(irq, priv->ibase + LINK_N2V(link, base));
+ writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base));
}
static struct irq_info *check_dup_entry(struct irq_info *slot_base,
int i;
int ret;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
/* extract the bdf from fdt_pci_addr */
priv->bdf = dm_pci_get_bdf(dev->parent);
/* Fix up the table checksum */
rt->checksum = table_compute_checksum(rt, rt->size);
- pirq_routing_table = rt;
+ gd->arch.pirq_routing_table = rt;
return 0;
}
if (priv->config == PIRQ_VIA_PCI)
dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
else
- writel(0, priv->ibase + priv->actl_addr);
+ writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
}
}
return ret;
}
/* Route PIRQ */
- pirq_route_irqs(dev, pirq_routing_table->slots,
- get_irq_slot_count(pirq_routing_table));
+ pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
+ get_irq_slot_count(gd->arch.pirq_routing_table));
if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
irq_enable_sci(dev);
return irq_router_common_init(dev);
}
-u32 write_pirq_routing_table(u32 addr)
+ulong write_pirq_routing_table(ulong addr)
{
- if (!pirq_routing_table)
+ if (!gd->arch.pirq_routing_table)
return addr;
- return copy_pirq_routing_table(addr, pirq_routing_table);
+ return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
}
static const struct udevice_id irq_router_ids[] = {
ifdef CONFIG_HAVE_FSP
obj-y += fsp_configs.o ivybridge.o
else
-obj-y += cpu.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o
obj-y += early_me.o
obj-y += lpc.o
obj-y += model_206ax.o
obj-y += northbridge.o
+ifndef CONFIG_SPL_BUILD
obj-y += sata.o
-obj-y += sdram.o
+endif
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o
+ifndef CONFIG_$(SPL_)X86_32BIT_INIT
+obj-y += sdram_nop.o
+endif
endif
obj-y += bd82x6x.o
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define GPIO_BASE 0x48
#define BIOS_CTRL 0xdc
/* Enable SPD ROMs and DDR-III DRAM */
ret = uclass_first_device_err(UCLASS_I2C, &dev);
- if (ret)
+ if (ret) {
+ debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
return ret;
+ }
/* Prepare USB controller early in S3 resume */
if (boot_mode == PEI_BOOT_RESUME) {
#include <asm/pci.h>
#include <asm/arch/pch.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
{
uint8_t route[8], *ptr;
- if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
"intel,pirq-routing", route, sizeof(route)))
return -EINVAL;
ptr = route;
u32 reg;
int gpi;
- if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
"intel,gpi-routing", route, sizeof(route)))
return -EINVAL;
static int pch_power_options(struct udevice *pch)
{
const void *blob = gd->fdt_blob;
- int node = pch->of_offset;
+ int node = dev_of_offset(pch);
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
#include <asm/turbo.h>
#include <asm/arch/model_206ax.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static void enable_vmx(void)
{
struct cpuid_result regs;
int tcc_offset;
msr_t msr;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
- 0);
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "tcc-offset", 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
#include <asm/arch/model_206ax.h>
#include <asm/arch/sandybridge.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int bridge_silicon_revision(struct udevice *dev)
{
struct cpuid_result result;
{
unsigned int port_map, speed_support, port_tx;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *mode;
u32 reg32;
u16 reg16;
mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
if (!mode || !strcmp(mode, "ahci")) {
- u32 abar;
+ ulong abar;
debug("SATA: Controller in AHCI mode\n");
/* Initialize AHCI memory-mapped space */
abar = dm_pci_read_bar32(dev, 5);
- debug("ABAR: %08X\n", abar);
+ debug("ABAR: %08lx\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = readl(abar + 0x00);
reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
static void bd82x6x_sata_enable(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
unsigned port_map;
const char *mode;
u16 map = 0;
int ret;
ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
- if (ret)
+ if (ret) {
+ debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
return ret;
+ }
memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
/* We need the pinctrl set up early */
ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
- if (ret)
+ if (ret) {
+ debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret);
return ret;
+ }
ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
- if (ret)
+ if (ret) {
+ debug("%s: Could not get northbridge (ret=%d)\n", __func__,
+ ret);
return ret;
+ }
ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
- if (ret)
+ if (ret) {
+ debug("%s: Could not get ME (ret=%d)\n", __func__, ret);
return ret;
+ }
ret = copy_spd(dev, pei_data);
- if (ret)
+ if (ret) {
+ debug("%s: Could not get SPD (ret=%d)\n", __func__, ret);
return ret;
+ }
pei_data->boot_mode = gd->arch.pei_boot_mode;
debug("Boot mode %d\n", gd->arch.pei_boot_mode);
debug("mrc_input %p\n", pei_data->mrc_input);
/* Wait for ME to be ready */
ret = intel_early_me_init(me_dev);
- if (ret)
+ if (ret) {
+ debug("%s: Could not init ME (ret=%d)\n", __func__, ret);
return ret;
+ }
ret = intel_early_me_uma_size(me_dev);
- if (ret < 0)
+ if (ret < 0) {
+ debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret);
return ret;
+ }
ret = mrc_common_init(dev, pei_data, false);
- if (ret)
+ if (ret) {
+ debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret);
return ret;
+ }
ret = sdram_find(dev);
- if (ret)
+ if (ret) {
+ debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret);
return ret;
+ }
gd->ram_size = gd->arch.meminfo.total_32bit_memory;
debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = 1ULL << 31;
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
* seq num in the uclass_resolve_seq() during device_probe(). To avoid
* this, set req_seq to the reg number in the device tree in advance.
*/
- cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
+ cpu->req_seq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(cpu), "reg",
+ -1);
plat->ucode_version = microcode_read_rev();
plat->device_id = gd->arch.x86_device;
#include <common.h>
#include <asm/e820.h>
+DECLARE_GLOBAL_DATA_PTR;
+
unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
{
entries[0].addr = 0;
static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
{
/* the DMA address register is big endian */
- outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+ outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
__asm__ __volatile__ ("pause");
#endif
}
+#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
return x86_cpu_init_f();
}
+#endif
-#ifndef CONFIG_EFI_STUB
+#if !CONFIG_IS_ENABLED(EFI_STUB) && \
+ !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT)
int print_cpuinfo(void)
{
post_code(POST_CPU_INFO);
+++ /dev/null
-/*
- * Written by H. Peter Anvin <hpa@zytor.com>
- * Brought in from Linux v4.4 and modified for U-Boot
- * From Linux arch/um/sys-i386/setjmp.S
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#define _REGPARM
-
-/*
- * The jmp_buf is assumed to contain the following, in order:
- * %ebx
- * %esp
- * %ebp
- * %esi
- * %edi
- * <return address>
- */
-
- .text
- .align 4
- .globl setjmp
- .type setjmp, @function
-setjmp:
-#ifdef _REGPARM
- movl %eax, %edx
-#else
- movl 4(%esp), %edx
-#endif
- popl %ecx /* Return address, and adjust the stack */
- xorl %eax, %eax /* Return value */
- movl %ebx, (%edx)
- movl %esp, 4(%edx) /* Post-return %esp! */
- pushl %ecx /* Make the call/return stack happy */
- movl %ebp, 8(%edx)
- movl %esi, 12(%edx)
- movl %edi, 16(%edx)
- movl %ecx, 20(%edx) /* Return address */
- ret
-
- /* Provide function size if needed */
- .size setjmp, .-setjmp
-
- .align 4
- .globl longjmp
- .type longjmp, @function
-longjmp:
-#ifdef _REGPARM
- xchgl %eax, %edx
-#else
- movl 4(%esp), %edx /* jmp_ptr address */
-#endif
- movl (%edx), %ebx
- movl 4(%edx), %esp
- movl 8(%edx), %ebp
- movl 12(%edx), %esi
- movl 16(%edx), %edi
- jmp *20(%edx)
-
- .size longjmp, .-longjmp
#include <generated/generic-asm-offsets.h>
#include <generated/asm-offsets.h>
-/*
- * Define this to boot U-Boot from a 32-bit program which sets the GDT
- * differently. This can be used to boot directly from any stage of coreboot,
- * for example, bypassing the normal payload-loading feature.
- * This is only useful for development.
- */
-#undef LOAD_FROM_32_BIT
-
.section .text
.code32
.globl _start
/* Save table pointer */
movl %ecx, %esi
-#ifdef LOAD_FROM_32_BIT
+#ifdef CONFIG_X86_LOAD_FROM_32_BIT
lgdt gdt_ptr2
#endif
/* entry addr */
.long CONFIG_SYS_TEXT_BASE
-#ifdef LOAD_FROM_32_BIT
+#ifdef CONFIG_X86_LOAD_FROM_32_BIT
/*
* The following Global Descriptor Table is just enough to get us into
* 'Flat Protected Mode' - It will be discarded as soon as the final
--- /dev/null
+/*
+ * 64-bit x86 Startup Code
+ *
+ * (C) Copyright 216 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.section .text
+.code64
+.globl _start
+.type _start, @function
+_start:
+ /* Set up memory using the existing stack */
+ mov %rsp, %rdi
+ call board_init_f_alloc_reserve
+ mov %rax, %rsp
+
+ call board_init_f_init_reserve
+
+ call board_init_f
+ call board_init_f_r
+
+ /* Should not return here */
+ jmp .
#include <asm/processor.h>
#include <asm/turbo.h>
+DECLARE_GLOBAL_DATA_PTR;
+
#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
static inline int get_global_turbo_state(void)
{
{
}
#else
-static int g_turbo_state = TURBO_UNKNOWN;
-
static inline int get_global_turbo_state(void)
{
- return g_turbo_state;
+ return gd->arch.turbo_state;
}
static inline void set_global_turbo_state(int state)
{
- g_turbo_state = state;
+ gd->arch.turbo_state = state;
}
#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64")
+OUTPUT_ARCH(i386:x86-64)
+ENTRY(_start)
+
+SECTIONS
+{
+#ifndef CONFIG_CMDLINE
+ /DISCARD/ : { *(.u_boot_list_2_cmd_*) }
+#endif
+
+ . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
+ __text_start = .;
+ .text : { *(.text*); }
+
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = ALIGN(4);
+ .hash : { *(.hash*) }
+
+ . = ALIGN(4);
+ .got : { *(.got*) }
+
+ . = ALIGN(4);
+ __data_end = .;
+ __init_end = .;
+
+ . = ALIGN(4);
+ .dynsym : { *(.dynsym*) }
+
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rela.dyn : {
+ *(.rela*)
+ }
+ __rel_dyn_end = .;
+ . = ALIGN(4);
+
+ .dynamic : { *(.dynamic) }
+
+ . = ALIGN(4);
+ _end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ *(COM*)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+#ifndef CONFIG_CMDLINE
+ /DISCARD/ : { *(.u_boot_list_2_cmd_*) }
+#endif
+
+ . = CONFIG_SPL_TEXT_BASE; /* Location of bootcode in flash */
+ __text_start = .;
+ .text : { *(.text*); }
+
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = ALIGN(4);
+ __data_end = .;
+ __init_end = .;
+
+ _image_binary_end = .;
+
+ . = 0x120000;
+ .bss (OVERLAY) : {
+ __bss_start = .;
+ *(.bss*)
+ *(COM*)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+ __bss_size = __bss_end - __bss_start;
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+
+#ifdef CONFIG_SPL_X86_16BIT_INIT
+ /*
+ * The following expressions place the 16-bit Real-Mode code and
+ * Reset Vector at the end of the Flash ROM
+ */
+ . = START_16 - RESET_SEG_START;
+ .start16 : AT (START_16) {
+ KEEP(*(.start16));
+ }
+
+ . = RESET_VEC_LOC - RESET_SEG_START;
+ .resetvec : AT (RESET_VEC_LOC) {
+ KEEP(*(.resetvec));
+ }
+#endif
+
+}
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
-#ifdef CONFIG_X86_RESET_VECTOR
+#ifdef CONFIG_X86_16BIT_INIT
/*
* The following expressions place the 16-bit Real-Mode code and
* Reset Vector at the end of the Flash ROM
--- /dev/null
+#
+# (C) Copyright 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+obj-y += cpu.o interrupts.o setjmp.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Global declaration of gd */
+struct global_data *global_data_ptr;
+
+void arch_setup_gd(gd_t *new_gd)
+{
+ global_data_ptr = new_gd;
+
+ /*
+ * TODO(sjg@chromium.org): For some reason U-Boot does not boot
+ * without this line. It fails to start up U-Boot proper and instead
+ * restarts SPL. Need to figure out why:
+ *
+ * U-Boot SPL 2017.01
+ *
+ * U-Boot SPL 2017.01
+ * CPU: Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz
+ * Trying to boot from SPIJumping to 64-bit U-Boot: Note many
+ * features are missing
+ *
+ * U-Boot SPL 2017.01
+ */
+#ifdef CONFIG_DEBUG_UART
+ printch(' ');
+#endif
+}
+
+int cpu_has_64bit(void)
+{
+ return true;
+}
+
+void enable_caches(void)
+{
+ /* Not implemented */
+}
+
+void disable_caches(void)
+{
+ /* Not implemented */
+}
+
+int dcache_status(void)
+{
+ return true;
+}
+
+int x86_mp_init(void)
+{
+ /* Not implemented */
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor-flags.h>
+
+void enable_interrupts(void)
+{
+ asm("sti\n");
+}
+
+int disable_interrupts(void)
+{
+ long flags;
+
+ asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
+
+ return flags & X86_EFLAGS_IF;
+}
+
+int interrupt_init(void)
+{
+ /* Nothing to do - this was already done in SPL */
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/setjmp.h>
+
+int setjmp(struct jmp_buf_data *jmp_buf)
+{
+ printf("WARNING: setjmp() is not supported\n");
+
+ return 0;
+}
+
+void longjmp(struct jmp_buf_data *jmp_buf, int val)
+{
+ printf("WARNING: longjmp() is not supported\n");
+}
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <0>;
intel,apic-id = <0>;
+ u-boot,dm-pre-reloc;
};
cpu@1 {
compatible = "intel,core-gen3";
reg = <1>;
intel,apic-id = <1>;
+ u-boot,dm-pre-reloc;
};
cpu@2 {
compatible = "intel,core-gen3";
reg = <2>;
intel,apic-id = <2>;
+ u-boot,dm-pre-reloc;
};
cpu@3 {
compatible = "intel,core-gen3";
reg = <3>;
intel,apic-id = <3>;
+ u-boot,dm-pre-reloc;
};
};
northbridge@0,0 {
reg = <0x00000000 0 0 0 0>;
+ u-boot,dm-pre-reloc;
compatible = "intel,bd82x6x-northbridge";
board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
<&gpio_b 11 0>, <&gpio_a 10 0>;
- u-boot,dm-pre-reloc;
spd {
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
+ u-boot,dm-pre-reloc;
reg = <0>;
data = [92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
00 00 00 00 00 00 00 00];
};
samsung_4Gb_1600_1.35v_x16 {
+ u-boot,dm-pre-reloc;
reg = <1>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
+ u-boot,dm-pre-reloc;
reg = <0>;
compatible = "winbond,w25q64",
"spi-flash";
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
+ u-boot,dm-pre-reloc;
};
};
};
};
microcode {
+ u-boot,dm-pre-reloc;
update@0 {
+ u-boot,dm-pre-reloc;
#include "microcode/m12306a9_0000001b.dtsi"
};
};
#ifdef CONFIG_ROM_SIZE
/ {
binman {
+#ifdef CONFIG_SPL
+ u-boot-spl-with-ucode-ptr {
+ optional-ucode;
+ };
+#else
u-boot-with-ucode-ptr {
optional-ucode;
};
+#endif
};
};
#endif
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
compatible = "cpu-qemu";
+ u-boot,dm-pre-reloc;
reg = <0>;
intel,apic-id = <0>;
};
pch@1,0 {
reg = <0x00000800 0 0 0 0>;
compatible = "intel,pch7";
+ u-boot,dm-pre-reloc;
irq-router {
compatible = "intel,irq-router";
+ u-boot,dm-pre-reloc;
intel,pirq-config = "pci";
intel,pirq-link = <0x60 4>;
intel,pirq-mask = <0x0e40>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
cpu@0 {
device_type = "cpu";
compatible = "cpu-qemu";
+ u-boot,dm-pre-reloc;
reg = <0>;
intel,apic-id = <0>;
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
+ u-boot,dm-pre-reloc;
irq-router {
compatible = "intel,irq-router";
+ u-boot,dm-pre-reloc;
intel,pirq-config = "pci";
intel,actl-8bit;
intel,actl-addr = <0x44>;
/ {
serial: serial {
+ u-boot,dm-pre-reloc;
compatible = "ns16550";
reg = <0x3f8 8>;
reg-shift = <0>;
intel-me {
};
#endif
+#ifdef CONFIG_SPL
+ u-boot-spl-with-ucode-ptr {
+ pos = <CONFIG_SPL_TEXT_BASE>;
+ };
+
+ u-boot-dtb-with-ucode2 {
+ type = "u-boot-dtb-with-ucode";
+ };
+ u-boot {
+ pos = <0xfff00000>;
+ };
+#else
u-boot-with-ucode-ptr {
pos = <CONFIG_SYS_TEXT_BASE>;
};
+#endif
u-boot-dtb-with-ucode {
};
u-boot-ucode {
pos = <CONFIG_X86_REFCODE_ADDR>;
};
#endif
+#ifdef CONFIG_SPL
+ x86-start16-spl {
+ pos = <CONFIG_SYS_X86_START16>;
+ };
+#else
x86-start16 {
pos = <CONFIG_SYS_X86_START16>;
};
+#endif
};
};
#endif
u8 cpu, u16 flags, u8 lint);
u32 acpi_fill_madt(u32 current);
void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
-u32 write_acpi_tables(u32 start);
+ulong write_acpi_tables(ulong start);
X86_SUBARCH_PC = 0,
X86_SUBARCH_LGUEST,
X86_SUBARCH_XEN,
- X86_SUBARCH_MRST,
+ X86_SUBARCH_INTEL_MID,
+ X86_SUBARCH_CE4100,
X86_NR_SUBARCHS,
};
#endif /* _ASM_X86_BOOTPARAM_H */
static __inline__ __u32 ___arch__swab32(__u32 x)
{
-#ifdef CONFIG_X86_BSWAP
__asm__("bswap %0" : "=r" (x) : "0" (x));
-#else
- __asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */
- "rorl $16,%0\n\t" /* swap words */
- "xchgb %b0,%h0" /* swap higher bytes */
- :"=q" (x)
- : "0" (x));
-#endif
+
return x;
}
+#define _constant_swab16(x) ((__u16)( \
+ (((__u16)(x) & (__u16)0x00ffU) << 8) | \
+ (((__u16)(x) & (__u16)0xff00U) >> 8)))
+
static __inline__ __u16 ___arch__swab16(__u16 x)
{
+#if CONFIG_IS_ENABLED(X86_64)
+ return _constant_swab16(x);
+#else
__asm__("xchgb %b0,%h0" /* swap bytes */ \
: "=q" (x) \
: "0" (x)); \
return x;
+#endif
}
#define __arch__swab32(x) ___arch__swab32(x)
return edx;
}
+#if !CONFIG_IS_ENABLED(X86_64)
+
/* Standard macro to see if a specific flag is changeable */
static inline int flag_is_changeable_p(uint32_t flag)
{
: "ir" (flag));
return ((f1^f2) & flag) != 0;
}
+#endif
static inline void mfence(void)
{
*/
int cpu_jump_to_64bit(ulong setup_base, ulong target);
+/**
+ * cpu_jump_to_64bit_uboot() - special function to jump from SPL to U-Boot
+ *
+ * This handles calling from 32-bit SPL to 64-bit U-Boot.
+ *
+ * @target: Address of U-Boot in RAM
+ */
+int cpu_jump_to_64bit_uboot(ulong target);
+
/**
* cpu_get_family_model() - Get the family and model for the CPU
*
*/
static inline const struct hob_header *get_next_hob(const struct hob_header *hdr)
{
- return (const struct hob_header *)((u32)hdr + hdr->len);
+ return (const struct hob_header *)((uintptr_t)hdr + hdr->len);
}
/**
*/
static inline void *get_guid_hob_data(const struct hob_header *hdr)
{
- return (void *)((u32)hdr + sizeof(struct hob_guid));
+ return (void *)((uintptr_t)hdr + sizeof(struct hob_guid));
}
/**
char *mrc_output;
unsigned int mrc_output_len;
ulong table; /* Table pointer from previous loader */
+ int turbo_state; /* Current turbo state */
+ struct irq_routing_table *pirq_routing_table;
#ifdef CONFIG_SEABIOS
u32 high_table_ptr;
u32 high_table_limit;
#include <asm-generic/global_data.h>
#ifndef __ASSEMBLY__
-# ifdef CONFIG_EFI_APP
+# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
+/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
#define gd global_data_ptr
#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr
{
gd_t *gd_ptr;
+#if CONFIG_IS_ENABLED(X86_64)
+ asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
+#else
asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
+#endif
return gd_ptr;
}
/* Probes the CPU device */
int mp_init_cpu(struct udevice *cpu, void *unused);
+/* Set up additional CPUs */
+int x86_mp_init(void);
+
#endif /* _X86_MP_H_ */
* @mc: configuration table header address
* @return: configuration table end address
*/
-static inline u32 mp_next_mpc_entry(struct mp_config_table *mc)
+static inline ulong mp_next_mpc_entry(struct mp_config_table *mc)
{
- return (u32)mc + mc->mpc_length;
+ return (ulong)mc + mc->mpc_length;
}
/**
* @mc: configuration table header address
* @return: configuration table end address
*/
-static inline u32 mp_next_mpe_entry(struct mp_config_table *mc)
+static inline ulong mp_next_mpe_entry(struct mp_config_table *mc)
{
- return (u32)mc + mc->mpc_length + mc->mpe_length;
+ return (ulong)mc + mc->mpc_length + mc->mpe_length;
}
/**
* @addr: start address to write MP table
* @return: end address of MP table
*/
-u32 write_mp_table(u32 addr);
+ulong write_mp_table(ulong addr);
#endif /* __ASM_MPSPEC_H */
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
+#if CONFIG_IS_ENABLED(X86_64)
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+#else
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
+#endif
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
* @base: Address to write table to
* @return address to use for the next table
*/
-u32 write_sfi_table(u32 base);
+ulong write_sfi_table(ulong base);
#endif /*_LINUX_SFI_H */
--- /dev/null
+/*
+ * Copyright (C) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file is required for SPL to build, but is empty.
+ */
* @start: start address to write PIRQ routing table
* @return: end address of PIRQ routing table
*/
-u32 write_pirq_routing_table(u32 start);
+ulong write_pirq_routing_table(ulong start);
#endif /* _X86_TABLES_H_ */
typedef __UINT64_TYPE__ u64;
#endif
+#if CONFIG_IS_ENABLED(X86_64)
+#define BITS_PER_LONG 64
+#else
#define BITS_PER_LONG 32
+#endif
+
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_X86_64
obj-y += bios.o
obj-y += bios_asm.o
obj-y += bios_interrupts.o
+endif
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+endif
obj-y += cmd_boot.o
obj-$(CONFIG_SEABIOS) += coreboot_table.o
obj-$(CONFIG_EFI) += efi/
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
endif
obj-y += tables.o
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
+endif
obj-$(CONFIG_HAVE_FSP) += fsp/
+obj-$(CONFIG_SPL_BUILD) += spl.o
extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a
$(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
$(call if_changed,objcopy)
+ifeq ($(CONFIG_$(SPL_)X86_64),)
obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o
+endif
ifneq ($(CONFIG_EFI_STUB),)
endif
ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
+ifeq ($(CONFIG_$(SPL_)X86_64),)
extra-y += $(EFI_CRT0) $(EFI_RELOC)
endif
+endif
* QEMU's version of write_acpi_tables is defined in
* arch/x86/cpu/qemu/acpi_table.c
*/
-u32 write_acpi_tables(u32 start)
+ulong write_acpi_tables(ulong start)
{
u32 current;
struct acpi_rsdp *rsdp;
/* Align ACPI tables to 16 byte */
current = ALIGN(current, 16);
- debug("ACPI: Writing ACPI tables at %x\n", start);
+ debug("ACPI: Writing ACPI tables at %lx\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (struct acpi_rsdp *)current;
for (i = 0; i < 256; i++) {
idts[i].cs = 0;
idts[i].offset = 0x1000 + (i * __idt_handler_size);
- write_idt_stub((void *)((u32)idts[i].offset), i);
+ write_idt_stub((void *)((ulong)idts[i].offset), i);
}
/*
mode_info->video_mode = (1 << 14) | vesa_mode;
vbe_get_mode_info(mode_info);
- framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr;
+ framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr;
debug("VBE: resolution: %dx%d@%d\n",
le16_to_cpu(mode_info->vesa.x_resolution),
le16_to_cpu(mode_info->vesa.y_resolution),
puts("Cannot boot 64-bit kernel on 32-bit machine\n");
return -EFAULT;
}
+ /* At present 64-bit U-Boot does not support booting a
+ * kernel.
+ * TODO(sjg@chromium.org): Support booting both 32-bit and
+ * 64-bit kernels from 64-bit U-Boot.
+ */
+#if !CONFIG_IS_ENABLED(X86_64)
return cpu_jump_to_64bit(setup_base, load_address);
+#endif
} else {
/*
* Set %ebx, %ebp, and %edi to 0, %esi to point to the
int init_cache_f_r(void)
{
-#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP)
+#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP)
int ret;
ret = mtrr_commit(false);
#include <common.h>
#include <asm/interrupt.h>
+#if !CONFIG_IS_ENABLED(X86_64)
+
struct irq_action {
interrupt_handler_t *handler;
void *arg;
}
}
}
+#endif
#if defined(CONFIG_CMD_IRQ)
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+#if !CONFIG_IS_ENABLED(X86_64)
int irq;
printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
irq_handlers[irq].count);
}
}
+#endif
return 0;
}
struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
{
- u32 mc;
+ ulong mc;
memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
- mf->mpf_physptr = (u32)mf + sizeof(struct mp_floating_table);
+ mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
mf->mpf_length = 1;
mf->mpf_spec = MPSPEC_V14;
mf->mpf_checksum = 0;
mf->mpf_feature5 = 0;
mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);
- mc = (u32)mf + sizeof(struct mp_floating_table);
+ mc = (ulong)mf + sizeof(struct mp_floating_table);
return (struct mp_config_table *)mc;
}
u32 mptable_finalize(struct mp_config_table *mc)
{
- u32 end;
+ ulong end;
mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
mc->mpe_length);
mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
end = mp_next_mpe_entry(mc);
- debug("Write the MP table at: %x - %x\n", (u32)mc, end);
+ debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);
return end;
}
}
/* Get I/O interrupt information from device tree */
- cell = fdt_getprop(blob, dev->of_offset, "intel,pirq-routing", &len);
+ cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
+ &len);
if (!cell)
return -ENOENT;
bus_isa, 0, MP_APIC_ALL, 1);
}
-u32 write_mp_table(u32 addr)
+ulong write_mp_table(ulong addr)
{
struct mp_config_table *mc;
int ioapic_id, ioapic_ver;
int bus_isa = 0xff;
int ret;
- u32 end;
+ ulong end;
/* 16 byte align the table address */
addr = ALIGN(addr, 16);
/* if iobase is present, let's configure the pad */
if (iobase != -1) {
- int iobase_addr;
+ ulong iobase_addr;
/*
* The offset for the same pin for the IOBASE and GPIOBASE are
return -EINVAL;
}
- for (pin_node = fdt_first_subnode(gd->fdt_blob, dev->of_offset);
+ for (pin_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
pin_node > 0;
pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
/* Configure the pin */
#include <asm/pci.h>
#include <asm/pirq_routing.h>
-static bool irq_already_routed[16];
-
-static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap)
+static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap,
+ bool irq_already_routed[])
{
int i, link;
u8 irq = 0;
{
unsigned char irq_slot[MAX_INTX_ENTRIES];
unsigned char pirq[CONFIG_MAX_PIRQ_LINKS];
+ bool irq_already_routed[16];
int i, intx;
memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS);
+ memset(irq_already_routed, '\0', sizeof(irq_already_routed));
/* Set PCI IRQs */
for (i = 0; i < num; i++) {
/* yet not routed */
if (!pirq[link]) {
- irq = pirq_get_next_free_irq(dev, pirq, bitmap);
+ irq = pirq_get_next_free_irq(dev, pirq, bitmap,
+ irq_already_routed);
pirq[link] = irq;
} else {
irq = pirq[link];
addr = ALIGN(addr, 16);
debug("Copying Interrupt Routing Table to 0x%x\n", addr);
- memcpy((void *)addr, rt, rt->size);
+ memcpy((void *)(uintptr_t)addr, rt, rt->size);
/*
* We do the sanity check here against the copied table after memcpy,
* as something might go wrong after the memcpy, which is normally
* due to the F segment decode is not turned on to systeam RAM.
*/
- rom_rt = (struct irq_routing_table *)addr;
+ rom_rt = (struct irq_routing_table *)(uintptr_t)addr;
if (rom_rt->signature != PIRQ_SIGNATURE ||
rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) {
printf("Interrupt Routing Table not valid\n");
int copy_uboot_to_ram(void)
{
- size_t len = (size_t)&__data_end - (size_t)&__text_start;
+ size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
int clear_bss(void)
{
ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
- size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+ size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
return 0;
}
-/*
- * This function has more error checking than you might expect. Please see
- * the commit message for more informaiton.
- */
-int do_elf_reloc_fixups(void)
+#if CONFIG_IS_ENABLED(X86_64)
+static void do_elf_reloc_fixups64(unsigned int text_base, uintptr_t size,
+ Elf64_Rela *re_src, Elf64_Rela *re_end)
{
- Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
- Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
+ Elf64_Addr *offset_ptr_rom, *last_offset = NULL;
+ Elf64_Addr *offset_ptr_ram;
- Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
- Elf32_Addr *offset_ptr_ram;
- unsigned int text_base = 0;
+ do {
+ /* Get the location from the relocation entry */
+ offset_ptr_rom = (Elf64_Addr *)(uintptr_t)re_src->r_offset;
- /* The size of the region of u-boot that runs out of RAM. */
- uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+ /* Check that the location of the relocation is in .text */
+ if (offset_ptr_rom >= (Elf64_Addr *)(uintptr_t)text_base &&
+ offset_ptr_rom > last_offset) {
+ /* Switch to the in-RAM version */
+ offset_ptr_ram = (Elf64_Addr *)((ulong)offset_ptr_rom +
+ gd->reloc_off);
- if (gd->flags & GD_FLG_SKIP_RELOC)
- return 0;
- if (re_src == re_end)
- panic("No relocation data");
+ /* Check that the target points into .text */
+ if (*offset_ptr_ram >= text_base &&
+ *offset_ptr_ram <= text_base + size) {
+ *offset_ptr_ram = gd->reloc_off +
+ re_src->r_addend;
+ } else {
+ debug(" %p: %lx: rom reloc %lx, ram %p, value %lx, limit %"
+ PRIXPTR "\n",
+ re_src, (ulong)re_src->r_info,
+ (ulong)re_src->r_offset, offset_ptr_ram,
+ (ulong)*offset_ptr_ram, text_base + size);
+ }
+ } else {
+ debug(" %p: %lx: rom reloc %lx, last %p\n", re_src,
+ (ulong)re_src->r_info, (ulong)re_src->r_offset,
+ last_offset);
+ }
+ last_offset = offset_ptr_rom;
-#ifdef CONFIG_SYS_TEXT_BASE
- text_base = CONFIG_SYS_TEXT_BASE;
+ } while (++re_src < re_end);
+}
#else
- panic("No CONFIG_SYS_TEXT_BASE");
-#endif
+static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,
+ Elf32_Rel *re_src, Elf32_Rel *re_end)
+{
+ Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+ Elf32_Addr *offset_ptr_ram;
+
do {
/* Get the location from the relocation entry */
- offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+ offset_ptr_rom = (Elf32_Addr *)(uintptr_t)re_src->r_offset;
/* Check that the location of the relocation is in .text */
- if (offset_ptr_rom >= (Elf32_Addr *)text_base &&
+ if (offset_ptr_rom >= (Elf32_Addr *)(uintptr_t)text_base &&
offset_ptr_rom > last_offset) {
/* Switch to the in-RAM version */
last_offset = offset_ptr_rom;
} while (++re_src < re_end);
+}
+#endif
+
+/*
+ * This function has more error checking than you might expect. Please see
+ * this commit message for more information:
+ * 62f7970a x86: Add error checking to x86 relocation code
+ */
+int do_elf_reloc_fixups(void)
+{
+ void *re_src = (void *)(&__rel_dyn_start);
+ void *re_end = (void *)(&__rel_dyn_end);
+ uint text_base;
+
+ /* The size of the region of u-boot that runs out of RAM. */
+ uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ return 0;
+ if (re_src == re_end)
+ panic("No relocation data");
+
+#ifdef CONFIG_SYS_TEXT_BASE
+ text_base = CONFIG_SYS_TEXT_BASE;
+#else
+ panic("No CONFIG_SYS_TEXT_BASE");
+#endif
+#if CONFIG_IS_ENABLED(X86_64)
+ do_elf_reloc_fixups64(text_base, size, re_src, re_end);
+#else
+ do_elf_reloc_fixups32(text_base, size, re_src, re_end);
+#endif
return 0;
}
tab->table[tab->count] = tab->entry_start;
tab->entry_start += sizeof(struct sfi_table_header);
- return (void *)tab->entry_start;
+ return (void *)(uintptr_t)tab->entry_start;
}
static void finish_table(struct table_info *tab, const char *sig, void *entry)
{
struct sfi_table_header *hdr;
- hdr = (struct sfi_table_header *)(tab->base + tab->ptr);
+ hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr);
strcpy(hdr->sig, sig);
hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start);
hdr->rev = 1;
return 0;
}
-u32 write_sfi_table(u32 base)
+ulong write_sfi_table(ulong base)
{
struct table_info table;
--- /dev/null
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+#include <asm/cpu.h>
+#include <asm/init_helpers.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm-generic/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int arch_cpu_init_dm(void)
+{
+ return 0;
+}
+
+static int x86_spl_init(void)
+{
+ /*
+ * TODO(sjg@chromium.org): We use this area of RAM for the stack
+ * and global_data in SPL. Once U-Boot starts up and releocates it
+ * is not needed. We could make this a CONFIG option or perhaps
+ * place it immediately below CONFIG_SYS_TEXT_BASE.
+ */
+ char *ptr = (char *)0x110000;
+ int ret;
+
+ debug("%s starting\n", __func__);
+ ret = spl_init();
+ if (ret) {
+ debug("%s: spl_init() failed\n", __func__);
+ return ret;
+ }
+ preloader_console_init();
+
+ ret = arch_cpu_init();
+ if (ret) {
+ debug("%s: arch_cpu_init() failed\n", __func__);
+ return ret;
+ }
+ ret = arch_cpu_init_dm();
+ if (ret) {
+ debug("%s: arch_cpu_init_dm() failed\n", __func__);
+ return ret;
+ }
+ ret = print_cpuinfo();
+ if (ret) {
+ debug("%s: print_cpuinfo() failed\n", __func__);
+ return ret;
+ }
+ ret = dram_init();
+ if (ret) {
+ debug("%s: dram_init() failed\n", __func__);
+ return ret;
+ }
+ memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
+
+ /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
+ ret = interrupt_init();
+ if (ret) {
+ debug("%s: interrupt_init() failed\n", __func__);
+ return ret;
+ }
+
+ /*
+ * The stack grows down from ptr. Put the global data at ptr. This
+ * will only be used for SPL. Once SPL loads U-Boot proper it will
+ * set up its own stack.
+ */
+ gd->new_gd = (struct global_data *)ptr;
+ memcpy(gd->new_gd, gd, sizeof(*gd));
+ arch_setup_gd(gd->new_gd);
+ gd->start_addr_sp = (ulong)ptr;
+
+ /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
+ ret = mtrr_add_request(MTRR_TYPE_WRBACK,
+ (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
+ CONFIG_XIP_ROM_SIZE);
+ if (ret) {
+ debug("%s: SPI cache setup failed\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong flags)
+{
+ int ret;
+
+ ret = x86_spl_init();
+ if (ret) {
+ debug("Error %d\n", ret);
+ hang();
+ }
+
+ /* Uninit CAR and jump to board_init_f_r() */
+ board_init_f_r_trampoline(gd->start_addr_sp);
+}
+
+void board_init_f_r(void)
+{
+ init_cache_f_r();
+ gd->flags &= ~GD_FLG_SERIAL_READY;
+ debug("cache status %d\n", dcache_status());
+ board_init_r(gd, 0);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_BOARD;
+}
+
+int spl_start_uboot(void)
+{
+ return 0;
+}
+
+void spl_board_announce_boot_device(void)
+{
+ printf("SPI flash");
+}
+
+static int spl_board_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ spl_image->size = CONFIG_SYS_MONITOR_LEN;
+ spl_image->entry_point = CONFIG_SYS_TEXT_BASE;
+ spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+ spl_image->os = IH_OS_U_BOOT;
+ spl_image->name = "U-Boot";
+
+ debug("Loading to %lx\n", spl_image->load_addr);
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+
+int spl_spi_load_image(void)
+{
+ return -EPERM;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ int ret;
+
+ printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
+ ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
+ debug("ret=%d\n", ret);
+ while (1)
+ ;
+}
#include <asm/acpi_table.h>
#include <asm/coreboot_tables.h>
-#ifdef CONFIG_GENERATE_SMBIOS_TABLE
-static u32 write_smbios_table_wrapper(u32 addr)
-{
- return write_smbios_table(addr);
-}
-#endif
-
/**
* Function prototype to write a specific configuration table
*
* @addr: start address to write the table
* @return: end address of the table
*/
-typedef u32 (*table_write)(u32 addr);
+typedef ulong (*table_write)(ulong addr);
static table_write table_write_funcs[] = {
#ifdef CONFIG_GENERATE_PIRQ_TABLE
write_acpi_tables,
#endif
#ifdef CONFIG_GENERATE_SMBIOS_TABLE
- write_smbios_table_wrapper,
+ write_smbios_table,
#endif
};
* A very old kernel MUST have its real-mode code
* loaded at 0x90000
*/
- if ((u32)setup_base != 0x90000) {
+ if ((ulong)setup_base != 0x90000) {
/* Copy the real-mode kernel */
memmove((void *)0x90000, setup_base, setup_size);
supported by U-Boot. They are via QEMU '-M pc', an i440FX/PIIX
chipset platform and '-M q35', a Q35/ICH9 chipset platform.
+config TARGET_QEMU_X86_64
+ bool "QEMU x86 64-bit"
+ help
+ This is the QEMU emulated x86 64-bit board. With this config
+ U-Boot is built as a 64-bit binary. This allows testing while
+ this feature is being completed.
+
endchoice
source "board/emulation/qemu-x86/Kconfig"
-if TARGET_QEMU_X86
+if TARGET_QEMU_X86 || TARGET_QEMU_X86_64
config SYS_BOARD
default "qemu-x86"
default "qemu-x86"
config SYS_TEXT_BASE
- default 0xfff00000 if !EFI_STUB
- default 0x01110000 if EFI_STUB
+ default 0xfff00000 if !EFI_STUB && !SUPPORT_SPL
+ default 0x01110000 if EFI_STUB || SUPPORT_SPL
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
F: configs/qemu-x86_defconfig
F: configs/qemu-x86_efi_payload32_defconfig
F: configs/qemu-x86_efi_payload64_defconfig
+
+QEMU X86 64-bit BOARD
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/emulation/qemu-x86/
+F: include/configs/qemu-x86.h
+F: configs/qemu-x86_64_defconfig
and it provides a 2560x1700 high resolution touch-enabled LCD
display.
+config TARGET_CHROMEBOOK_LINK64
+ bool "Chromebook link 64-bit"
+ help
+ This is the Chromebook Pixel released in 2013. With this config
+ U-Boot is built as a 64-bit binary. This allows testing while this
+ feature is being completed.
+
config TARGET_CHROMEBOX_PANTHER
bool "Chromebox panther (not available)"
select n
-if TARGET_CHROMEBOOK_LINK
+if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
config SYS_BOARD
default "chromebook_link"
default "chromebook_link"
config SYS_TEXT_BASE
- default 0xfff00000
+ default 0xfff00000 if !SUPPORT_SPL
+ default 0x10000000 if SUPPORT_SPL
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
F: board/google/chromebook_link/
F: include/configs/chromebook_link.h
F: configs/chromebook_link_defconfig
+
+CHROMEBOOK LINK 64-bit BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_link/
+F: include/configs/chromebook_link.h
+F: configs/chromebook_link64_defconfig
.wldqsen = 25,
};
- ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
- pcm052_phy_settings, 1, 2);
+ const int row_diff = 2;
#elif defined(CONFIG_TARGET_BK4R1)
.wldqsen = 25,
};
- ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
- pcm052_phy_settings, 1, 1);
+ const int row_diff = 1;
#else /* Unknown PCM052 variant */
imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+ ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
+ pcm052_phy_settings, 1, row_diff);
+
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
/* Try to request gpios needed to start usb host on dragonboard */
if (!dm_gpio_is_valid(&hub_reset)) {
- node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+ node = fdt_subnode_offset(gd->fdt_blob,
+ dev_of_offset(pmic_gpio),
"usb_hub_reset_pm");
if (node < 0) {
printf("Failed to find usb_hub_reset_pm dt node.\n");
}
if (!dm_gpio_is_valid(&usb_sel)) {
- node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+ node = fdt_subnode_offset(gd->fdt_blob,
+ dev_of_offset(pmic_gpio),
"usb_sw_sel_pm");
if (node < 0) {
printf("Failed to find usb_sw_sel_pm dt node.\n");
return 0;
}
- node = fdt_subnode_offset(gd->fdt_blob, pon->of_offset, "key_vol_down");
+ node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+ "key_vol_down");
if (node < 0) {
printf("Failed to find key_vol_down node. Check device tree\n");
return 0;
--- /dev/null
+config_data.gz
+config_data_gz.h
+config_data_size.h
+license_data.gz
+license_data_gz.h
+license_data_size.h
help
Print board info
+config CMD_CONFIG
+ bool "config"
+ select BUILD_BIN2C
+ default SANDBOX
+ help
+ Print ".config" contents.
+
+ If this option is enabled, the ".config" file contents are embedded
+ in the U-Boot image and can be printed on the console by the "config"
+ command. This provides information of which options are enabled on
+ the running U-Boot.
+
config CMD_CONSOLE
bool "coninfo"
default y
config CMD_LICENSE
bool "license"
+ select BUILD_BIN2C
help
Print GPL license text
help
Display memory information.
+config CMD_UNZIP
+ bool "unzip"
+ help
+ Uncompress a zip-compressed memory region.
+
+config CMD_ZIP
+ bool "zip"
+ help
+ Compress a memory region with zlib deflate method.
+
endmenu
menu "Device access commands"
obj-$(CONFIG_CMD_CACHE) += cache.o
obj-$(CONFIG_CMD_CBFS) += cbfs.o
obj-$(CONFIG_CMD_CLK) += clk.o
+obj-$(CONFIG_CMD_CONFIG) += config.o
obj-$(CONFIG_CMD_CONSOLE) += console.o
obj-$(CONFIG_CMD_CPLBINFO) += cplbinfo.o
obj-$(CONFIG_CMD_CPU) += cpu.o
obj-y += nvedit.o
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
+
+filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
+
+filechk_data_size = \
+ (echo "static const size_t data_size = "; \
+ cat $< | wc -c; echo ";")
+
+# "config" command
+$(obj)/config.o: $(obj)/config_data_gz.h $(obj)/config_data_size.h
+
+targets += config_data.gz
+$(obj)/config_data.gz: $(KCONFIG_CONFIG) FORCE
+ $(call if_changed,gzip)
+
+targets += config_data_gz.h
+$(obj)/config_data_gz.h: $(obj)/config_data.gz FORCE
+ $(call filechk,data_gz)
+
+targets += config_data_size.h
+$(obj)/config_data_size.h: $(KCONFIG_CONFIG) FORCE
+ $(call filechk,data_size)
+
+# "license" command
+$(obj)/license.o: $(obj)/license_data_gz.h $(obj)/license_data_size.h
+
+targets += license_data.gz
+$(obj)/license_data.gz: $(srctree)/Licenses/gpl-2.0.txt FORCE
+ $(call if_changed,gzip)
+
+targets += license_data_gz.h
+$(obj)/license_data_gz.h: $(obj)/license_data.gz FORCE
+ $(call filechk,data_gz)
+
+targets += license_data_size.h
+$(obj)/license_data_size.h: $(srctree)/Licenses/gpl-2.0.txt FORCE
+ $(call filechk,data_size)
return -ENOMEM;
}
- ret = nand_read_skip_bad(mtd, off, &len, imgdata);
+ ret = nand_read_skip_bad(mtd, off, &len, NULL, mtd->size, imgdata);
if (ret < 0 && ret != -EUCLEAN) {
free(imgdata);
return ret;
return -ENOMEM;
}
- ret = nand_read_skip_bad(mtd, off, &len, imgdata);
+ ret = nand_read_skip_bad(mtd, off, &len, NULL, mtd->size, imgdata);
if (ret < 0 && ret != -EUCLEAN) {
free(imgdata);
return ret;
--- /dev/null
+/*
+ * Copyright (C) 2017 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+
+#include "config_data_gz.h"
+#include "config_data_size.h"
+
+static int do_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *dst;
+ unsigned long len = data_size;
+ int ret = CMD_RET_SUCCESS;
+
+ dst = malloc(data_size + 1);
+ if (!dst)
+ return CMD_RET_FAILURE;
+
+ ret = gunzip(dst, data_size, (unsigned char *)data_gz, &len);
+ if (ret) {
+ printf("failed to uncompress .config data\n");
+ ret = CMD_RET_FAILURE;
+ goto free;
+ }
+
+ dst[data_size] = 0;
+ puts(dst);
+
+free:
+ free(dst);
+
+ return ret;
+}
+
+U_BOOT_CMD(
+ config, 1, 1, do_config,
+ "print .config",
+ ""
+);
*/
#include <common.h>
-
-/* Licenses/gpl-2.0.txt is currently 18092 bytes in size */
-#define LICENSE_MAX 20480
-
#include <command.h>
#include <malloc.h>
-#include <license.h>
-int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#include "license_data_gz.h"
+#include "license_data_size.h"
+
+static int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *dst = malloc(LICENSE_MAX);
- unsigned long len = LICENSE_MAX;
+ char *dst;
+ unsigned long len = data_size;
+ int ret = CMD_RET_SUCCESS;
+ dst = malloc(data_size + 1);
if (!dst)
- return -1;
+ return CMD_RET_FAILURE;
- if (gunzip(dst, LICENSE_MAX, license_gzip, &len) != 0) {
+ ret = gunzip(dst, data_size, (unsigned char *)data_gz, &len);
+ if (ret) {
printf("Error uncompressing license text\n");
- free(dst);
- return -1;
+ ret = CMD_RET_FAILURE;
+ goto free;
}
+
+ dst[data_size] = 0;
puts(dst);
+
+free:
free(dst);
- return 0;
+ return ret;
}
U_BOOT_CMD(
}
/* ARM calls relocate_code from its crt0.S */
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
+ !CONFIG_IS_ENABLED(X86_64)
static int jump_to_copy(void)
{
return 0;
}
-static init_fnc_t init_sequence_f[] = {
+static const init_fnc_t init_sequence_f[] = {
#ifdef CONFIG_SANDBOX
setup_ram_buf,
#endif
setup_reloc,
#if defined(CONFIG_X86) || defined(CONFIG_ARC)
copy_uboot_to_ram,
- clear_bss,
do_elf_reloc_fixups,
+ clear_bss,
#endif
#if defined(CONFIG_XTENSA)
clear_bss,
#endif
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
+ !CONFIG_IS_ENABLED(X86_64)
jump_to_copy,
#endif
NULL,
hang();
#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
- !defined(CONFIG_EFI_APP)
+ !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
/* NOTREACHED - jump_to_copy() does not return */
hang();
#endif
* NOTE: At present only x86 uses this route, but it is intended that
* all archs will move to this when generic relocation is implemented.
*/
-static init_fnc_t init_sequence_f_r[] = {
+static const init_fnc_t init_sequence_f_r[] = {
+#if !CONFIG_IS_ENABLED(X86_64)
init_cache_f_r,
+#endif
NULL,
};
*
* TODO: perhaps reset the watchdog in the initcall function after each call?
*/
-init_fnc_t init_sequence_r[] = {
+static init_fnc_t init_sequence_r[] = {
initr_trace,
initr_reloc,
/* TODO: could x86/PPC have this also perhaps? */
void board_init_r(gd_t *new_gd, ulong dest_addr)
{
+ /*
+ * Set up the new global data pointer. So far only x86 does this
+ * here.
+ * TODO(sjg@chromium.org): Consider doing this for all archs, or
+ * dropping the new_gd parameter.
+ */
+#if CONFIG_IS_ENABLED(X86_64)
+ arch_setup_gd(new_gd);
+#endif
+
#ifdef CONFIG_NEEDS_MANUAL_RELOC
int i;
#endif
case env_op_create:
case env_op_overwrite:
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
if (iomux_doenv(console, value))
return 1;
#else
/* Try assigning specified device */
if (console_assign(console, value) < 0)
return 1;
-#endif /* CONFIG_CONSOLE_MUX */
+#endif
return 0;
case env_op_delete:
U_BOOT_ENV_CALLBACK(silent, on_silent);
#endif
-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
+#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
/*
* if overwrite_console returns 1, the stdin, stderr and stdout
* are switched to the serial port, else the settings in the
#define OVERWRITE_CONSOLE 0
#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
+#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
static int console_setfile(int file, struct stdio_dev * dev)
{
return error;
}
-#if defined(CONFIG_CONSOLE_MUX)
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
/** Console I/O multiplexing *******************************************/
static struct stdio_dev *tstcdev;
{
console_setfile(file, dev);
}
-#endif /* defined(CONFIG_CONSOLE_MUX) */
+#endif /* CONIFIG_IS_ENABLED(CONSOLE_MUX) */
/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/
int fgetc(int file)
{
if (file < MAX_FILES) {
-#if defined(CONFIG_CONSOLE_MUX)
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
/*
* Effectively poll for input wherever it may be available.
*/
}
}
-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
+#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
/* Called after the relocation - use desired console functions */
int console_init_r(void)
{
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
int i;
#endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
int iomux_err = 0;
#endif
inputdev = search_device(DEV_FLAGS_INPUT, stdinname);
outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname);
errdev = search_device(DEV_FLAGS_OUTPUT, stderrname);
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
iomux_err = iomux_doenv(stdin, stdinname);
iomux_err += iomux_doenv(stdout, stdoutname);
iomux_err += iomux_doenv(stderr, stderrname);
console_doenv(stdin, inputdev);
}
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
done:
#endif
return 0;
}
-#else /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
+#else /* !CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
/* Called after the relocation - use desired console functions */
int console_init_r(void)
if (outputdev != NULL) {
console_setfile(stdout, outputdev);
console_setfile(stderr, outputdev);
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
console_devices[stdout][0] = outputdev;
console_devices[stderr][0] = outputdev;
#endif
/* Initializes input console */
if (inputdev != NULL) {
console_setfile(stdin, inputdev);
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
console_devices[stdin][0] = inputdev;
#endif
}
return 0;
}
-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
+#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
#include <dm/device-internal.h>
#ifndef CONFIG_ENV_SPI_BUS
-# define CONFIG_ENV_SPI_BUS 0
+# define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#endif
#ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS 0
+# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#endif
#ifndef CONFIG_ENV_SPI_MAX_HZ
-# define CONFIG_ENV_SPI_MAX_HZ 1000000
+# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
#ifndef CONFIG_ENV_SPI_MODE
-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
+# define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#endif
#ifdef CONFIG_ENV_OFFSET_REDUND
{
struct node_info *ni = node_info;
struct mtd_device *dev;
- char *parts;
int i, idx;
int noff;
- parts = getenv("mtdparts");
- if (!parts)
- return;
-
if (mtdparts_init() != 0)
return;
#include <serial.h>
#include <malloc.h>
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
void iomux_printdevs(const int console)
{
int i;
free(cons_set);
return 0;
}
-#endif /* CONFIG_CONSOLE_MUX */
+#endif /* CONSOLE_MUX */
SHA256 variant is supported: SHA512 and others are not currently
supported in U-Boot.
+config SPL_CPU_SUPPORT
+ bool "Support CPU drivers"
+ depends on SPL
+ help
+ Enable this to support CPU drivers in SPL. These drivers can set
+ up CPUs and provide information about them such as the model and
+ name. This can be useful in SPL since setting up the CPUs earlier
+ may improve boot performance. Enable this option to build the
+ drivers in drivers/cpu as part of an SPL build.
+
config SPL_CRYPTO_SUPPORT
bool "Support crypto drivers"
depends on SPL
endif # SPL_OS_BOOT
+config SPL_PCI_SUPPORT
+ bool "Support PCI drivers"
+ depends on SPL
+ help
+ Enable support for PCI in SPL. For platforms that need PCI to boot,
+ or must perform some init using PCI in SPL, this provides the
+ necessary driver support. This enables the drivers in drivers/pci
+ as part of an SPL build.
+
+config SPL_PCH_SUPPORT
+ bool "Support PCH drivers"
+ depends on SPL
+ help
+ Enable support for PCH (Platform Controller Hub) devices in SPL.
+ These are used to set up GPIOs and the SPI peripheral early in
+ boot. This enables the drivers in drivers/pch as part of an SPL
+ build.
+
config SPL_POST_MEM_SUPPORT
bool "Support POST drivers"
depends on SPL
be already in memory when SPL takes over, e.g. loaded by the boot
ROM.
+config SPL_RTC_SUPPORT
+ bool "Support RTC drivers"
+ depends on SPL
+ help
+ Enable RTC (Real-time Clock) support in SPL. This includes support
+ for reading and setting the time. Some RTC devices also have some
+ non-volatile (battery-backed) memory which is accessible if
+ needed. This enables the drivers in drivers/rtc as part of an SPL
+ build.
+
config SPL_SATA_SUPPORT
bool "Support loading from SATA"
depends on SPL
enable SPI drivers that are needed for other purposes also, such
as a SPI PMIC.
+config SPL_TIMER_SUPPORT
+ bool "Support timer drivers"
+ depends on SPL
+ help
+ Enable support for timer drivers in SPL. These can be used to get
+ a timer value when in SPL, or perhaps for implementing a delay
+ function. This enables the drivers in drivers/timer as part of an
+ SPL build.
+
config SPL_USB_HOST_SUPPORT
bool "Support USB host drivers"
depends on SPL
/* Load u-boot, mkimage header is 64 bytes. */
err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
(void *)header);
- if (err)
+ if (err) {
+ debug("%s: Failed to read from SPI flash (err=%d)\n",
+ __func__, err);
return err;
+ }
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
return error;
stdinname = getenv("stdin");
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
error = iomux_doenv(stdin, stdinname);
if (error)
return error;
data = usb_kbd_dev->privptr;
if (stdio_deregister_dev(dev, force) != 0)
return 1;
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
if (iomux_doenv(stdin, getenv("stdin")) != 0)
return 1;
#endif
ret = -EPERM;
goto err;
}
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
if (iomux_doenv(stdin, getenv("stdin"))) {
ret = -ENOLINK;
goto err;
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_API=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
--- /dev/null
+CONFIG_X86=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_X86_RUN_64BIT=y
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
+CONFIG_TARGET_CHROMEBOOK_LINK64=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_PCI_SUPPORT=y
+CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_TIMER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_INTEL=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_IVYBRIDGE_IGD=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_TPM=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_X86=y
-CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_VENDOR_GOOGLE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
CONFIG_DM_VIDEO=y
+CONFIG_USB_KEYBOARD=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEFAULT_DEVICE_TREE="k2e-evm"
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm"
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEFAULT_DEVICE_TREE="k2l-evm"
+CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
+CONFIG_API=y
--- /dev/null
+CONFIG_X86=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_MAX_CPUS=2
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_X86_RUN_64BIT=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
+CONFIG_TARGET_QEMU_X86_64=y
+CONFIG_SMP=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_PCI_SUPPORT=y
+CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_TIMER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_QFW=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CPU=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_111=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_GPT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_NAND=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
printf("%s: calloc failed!\n", __func__);
return -1;
}
+
+ /* Read MBR to backup boot code if it exists */
+ if (blk_dread(dev_desc, 0, 1, p_mbr) != 1) {
+ error("** Can't read from device %d **\n", dev_desc->devnum);
+ return -1;
+ }
+
/* Append signature */
p_mbr->signature = MSDOS_MBR_SIGNATURE;
p_mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
g. If the driver provides an ofdata_to_platdata() method, then this is
called to convert the device tree data into platform data. This should
- do various calls like fdtdec_get_int(gd->fdt_blob, dev->of_offset, ...)
+ do various calls like fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), ...)
to access the node and store the resulting information into dev->platdata.
After this point, the device works the same way whether it was bound
using a device tree node or U_BOOT_DEVICE() structure. In either case,
/* Decode the device tree data */
struct mmc_platdata *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
#endif
{
struct exynos_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
plat->periph_id = pinmux_decode_periph_id(blob, node);
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
+obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
+obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/
+obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/
+obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/
obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
static int adc_vdd_platdata_set(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
- int ret, offset = dev->of_offset;
+ int ret, offset = dev_of_offset(dev);
const void *fdt = gd->fdt_blob;
char *prop;
static int adc_vss_platdata_set(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
- int ret, offset = dev->of_offset;
+ int ret, offset = dev_of_offset(dev);
const void *fdt = gd->fdt_blob;
char *prop;
const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
& SCU_MPLL_POST_MASK;
- return (clkin * ((num + 1) / (denum + 1))) / post_div;
+ return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
/*
const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
& SCU_HPLL_POST_MASK;
- return (clkin * ((num + 1) / (denum + 1))) / post_div;
+ return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
static ulong ast2500_get_clkin(struct ast2500_scu *scu)
u32 num_parents;
num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
- dev_get_parent(dev)->of_offset,
- "clocks", cells,
- GENERATED_SOURCE_MAX);
+ dev_of_offset(dev_get_parent(dev)), "clocks", cells,
+ GENERATED_SOURCE_MAX);
if (!num_parents)
return -1;
int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
{
const void *fdt = gd->fdt_blob;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
return -EINVAL;
}
- periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
+ periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
+ -1);
if (periph < 0)
return -EINVAL;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(clk);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"clocks", "#clock-cells", 0, index,
&args);
if (ret) {
debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"clock-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
to_clk_fixed_rate(dev)->fixed_rate =
- fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
#endif
for (i = REF1CLK; i <= REF5CLK; i++) {
snprintf(propname, sizeof(propname),
"microchip,refo%d-frequency", i - REF1CLK + 1);
- rate = fdtdec_get_int(blob, dev->of_offset, propname, 0);
+ rate = fdtdec_get_int(blob, dev_of_offset(dev), propname, 0);
if (rate)
pic32_set_refclk(priv, i, pll_hz, rate, ROCLK_SRC_SPLL);
}
fdt_addr_t addr;
fdt_size_t size;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
goto fail;
}
- if (drv->ofdata_to_platdata && dev->of_offset >= 0) {
+ if (drv->ofdata_to_platdata && dev_of_offset(dev) >= 0) {
ret = drv->ofdata_to_platdata(dev);
if (ret)
goto fail;
*devp = NULL;
list_for_each_entry(dev, &parent->child_head, sibling_node) {
- if (dev->of_offset == of_offset) {
+ if (dev_of_offset(dev) == of_offset) {
*devp = dev;
return 0;
}
{
struct udevice *dev, *found;
- if (parent->of_offset == of_offset)
+ if (dev_of_offset(parent) == of_offset)
return parent;
list_for_each_entry(dev, &parent->child_head, sibling_node) {
int len = 0;
int na, ns;
- na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ na = fdt_address_cells(gd->fdt_blob,
+ dev_of_offset(dev->parent));
if (na < 1) {
debug("bad #address-cells\n");
return FDT_ADDR_T_NONE;
}
- ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (ns < 0) {
debug("bad #size-cells\n");
return FDT_ADDR_T_NONE;
}
- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+ reg = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &len);
if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
debug("Req index out of range\n");
return FDT_ADDR_T_NONE;
* bus setups.
*/
addr = fdt_translate_address((void *)gd->fdt_blob,
- dev->of_offset, reg);
+ dev_of_offset(dev), reg);
} else {
/*
* Use the "simple" translate function for less complex
* bus setups.
*/
addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev->parent->of_offset,
- dev->of_offset, "reg",
- index, NULL, false);
+ dev_of_offset(dev->parent), dev_of_offset(dev),
+ "reg", index, NULL, false);
if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
if (device_get_uclass_id(dev->parent) ==
UCLASS_SIMPLE_BUS)
* next call to the exisiting dev_get_xxx function which handles
* all config options.
*/
- fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev_of_offset(dev),
"reg", index, size, false);
/*
#if CONFIG_IS_ENABLED(OF_CONTROL)
int index;
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"reg-names", name);
if (index < 0)
return index;
{
const void *fdt = gd->fdt_blob;
- return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+ return !fdt_node_check_compatible(fdt, dev_of_offset(dev), compat);
}
bool of_machine_is_compatible(const char *compat)
int parent;
int len;
- parent = dev->parent->of_offset;
+ parent = dev_of_offset(dev->parent);
addr_len = fdt_address_cells(blob, parent);
size_len = fdt_size_cells(blob, parent);
both_len = addr_len + size_len;
- cell = fdt_getprop(blob, dev->of_offset, "reg", &len);
+ cell = fdt_getprop(blob, dev_of_offset(dev), "reg", &len);
len /= sizeof(*cell);
count = len / both_len;
if (!cell || !count)
int dm_scan_fdt_dev(struct udevice *dev)
{
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev_of_offset(dev),
gd->flags & GD_FLG_RELOC ? false : true);
}
static int simple_bus_post_bind(struct udevice *dev)
{
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ return 0;
+#else
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "ranges",
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "ranges",
cell, ARRAY_SIZE(cell));
if (!ret) {
struct simple_bus_plat *plat = dev_get_uclass_platdata(dev);
}
return dm_scan_fdt_dev(dev);
+#endif
}
UCLASS_DRIVER(simple_bus) = {
return ret;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
- if (dev->of_offset == node) {
+ if (dev_of_offset(dev) == node) {
*devp = dev;
return 0;
}
int ret;
*devp = NULL;
- find_phandle = fdtdec_get_int(gd->fdt_blob, parent->of_offset, name,
+ find_phandle = fdtdec_get_int(gd->fdt_blob, dev_of_offset(parent), name,
-1);
if (find_phandle <= 0)
return -ENOENT;
return ret;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
- uint phandle = fdt_get_phandle(gd->fdt_blob, dev->of_offset);
+ uint phandle;
+
+ phandle = fdt_get_phandle(gd->fdt_blob, dev_of_offset(dev));
if (phandle == find_phandle) {
*devp = dev;
return ret;
/* Parse the data that only we need */
- pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"character", '@');
return 0;
int demo_parse_dt(struct udevice *dev)
{
struct dm_demo_pdata *pdata = dev_get_platdata(dev);
- int dn = dev->of_offset;
+ int dn = dev_of_offset(dev);
pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0);
pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL);
char *str, name[32];
int ret;
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
snprintf(name, sizeof(name), "%s_", dev->name);
str = strdup(name);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct altera_pio_regs),
MAP_NOCACHE);
- plat->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"altr,gpio-bank-width", 32);
- plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
return 0;
static int atmel_pio4_bind(struct udevice *dev)
{
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev_of_offset(dev), false);
}
static int atmel_pio4_probe(struct udevice *dev)
pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
nbanks = pioctrl_data->nbanks;
- uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
+ NULL);
uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
return 0;
/**
* config_pin - configure a pin's mux attributes
- * @cfg: pin confguration
+ * @cfg: pin configuration
*
* Configures a pin's mode (alternate function or GPIO), its pull up status,
* and its sleep mode based on the specified configuration. The @cfg is
if (plat)
return 0;
- base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+ base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
}
- for (node = fdt_first_subnode(blob, dev->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
if (!fdtdec_get_bool(blob, node, "gpio-controller"))
if (ret)
goto err;
- subdev->of_offset = node;
+ dev_set_of_offset(subdev, node);
bank++;
}
* calls in gpio_request_by_name(), but we can do this until
* gpio_request_by_name_nodev() can be dropped.
*/
- return gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset,
+ return gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
list_name, index, desc, flags);
}
* calls in gpio_request_by_name(), but we can do this until
* gpio_request_list_by_name_nodev() can be dropped.
*/
- return gpio_request_list_by_name_nodev(gd->fdt_blob, dev->of_offset,
+ return gpio_request_list_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
list_name, desc, max_count,
flags);
}
{
int ret;
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
list_name, "#gpio-cells", 0, -1,
NULL);
if (ret) {
if (ret)
return ret;
- bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (bank == -1) {
debug("%s: Invalid bank number %d\n", __func__, bank);
return -EINVAL;
}
plat->bank = bank;
plat->base_addr = gpiobase;
- plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"bank-name", NULL);
return 0;
if (ret)
return ret;
- offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (offset == -1) {
debug("%s: Invalid register offset %d\n", __func__, offset);
return -EINVAL;
}
plat->offset = offset;
plat->base_addr = gpiobase + offset;
- plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"bank-name", NULL);
return 0;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- if (dev->of_offset == -1) {
+ if (dev_of_offset(dev) == -1) {
/* Tell the uclass how many GPIOs we have */
uc_priv->gpio_count = LPC32XX_GPIOS;
}
fdt_addr_t addr;
fdt_size_t size;
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
- "reg", 0, &size, false);
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+ dev_of_offset(dev), "reg", 0, &size, false);
plat->addr = addr;
plat->size = size;
- plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "ngpios", 32);
+ plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "ngpios", 32);
return 0;
}
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gpio-count", 0);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "soc";
return -ENOMEM;
plat->base = base_addr;
- plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ plat->port_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL);
dev->platdata = plat;
return 0;
return -ENODEV;
}
- addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
if (addr == 0)
return -ENODEV;
int n_latch;
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gpio-count", 16);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (!uc_priv->bank_name)
uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
- dev->of_offset, NULL);
+ dev_of_offset(dev), NULL);
- n_latch = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ n_latch = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"lines-initial-states", 0);
plat->out = ~n_latch;
char *end;
int bank;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gpio-count", 0);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "pm8916";
return 0;
base = (struct s5p_gpio_bank *)dev_get_addr(parent);
- for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
+ for (node = fdt_first_subnode(blob, dev_of_offset(parent)), bank = base;
node > 0;
node = fdt_next_subnode(blob, node), bank++) {
struct exynos_gpio_platdata *plat;
if (ret)
return ret;
- dev->of_offset = node;
+ dev_set_of_offset(dev, node);
reg = dev_get_addr(dev);
if (reg != FDT_ADDR_T_NONE)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"num-gpios", 0);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
return 0;
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- if (dev->of_offset == -1) {
+ if (dev_of_offset(dev) == -1) {
/* Tell the uclass how many GPIOs we have */
uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT;
}
plat->bank_name, plat, -1, &dev);
if (ret)
return ret;
- dev->of_offset = parent->of_offset;
+ dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
-1, &dev);
if (ret)
return ret;
- dev->of_offset = parent->of_offset;
+ dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
*/
- if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
+ if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
+ &len))
return -EINVAL;
bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)dev_get_addr(parent);
plat->port_name, plat, -1, &dev);
if (ret)
return ret;
- dev->of_offset = parent->of_offset;
+ dev_set_of_offset(dev, dev_of_offset(parent));
}
}
plat->base = base_addr;
plat->chip = dev->req_seq;
- plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ plat->port_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL);
dev->platdata = plat;
return 0;
{
const void *blob = gd->fdt_blob;
struct at91_i2c_bus *bus = dev_get_priv(dev);
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
bus->regs = (struct at91_i2c_regs *)dev_get_addr(dev);
bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev);
{
struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus",
0);
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
int node;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
struct fsl_i2c_dev *dev = dev_get_priv(bus);
fdt_addr_t addr;
fdt_size_t size;
+ int node = dev_of_offset(bus);
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset,
- "reg", 0, &size, false);
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, node, "reg", 0,
+ &size, false);
dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
if (!dev->base)
return -ENOMEM;
- dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
- "cell-index", -1);
- dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->index = fdtdec_get_int(gd->fdt_blob, node, "cell-index", -1);
+ dev->slaveadd = fdtdec_get_int(gd->fdt_blob, node,
"u-boot,i2c-slave-addr", 0x7f);
- dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
- "clock-frequency", 400000);
+ dev->speed = fdtdec_get_int(gd->fdt_blob, node, "clock-frequency",
+ 400000);
dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
{
struct i2c_gpio_bus *bus = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = gpio_request_list_by_name(dev, "gpios", bus->gpios,
#if CONFIG_IS_ENABLED(OF_CONTROL)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
- i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 100000);
return dm_i2c_set_bus_speed(dev, i2c->speed_hz);
#if CONFIG_IS_ENABLED(OF_CONTROL)
struct dm_i2c_chip *plat = dev_get_parent_platdata(dev);
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
- return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
+ return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev_of_offset(dev),
+ plat);
#else
return 0;
#endif
{
struct i2c_arbitrator_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
debug("%s: %s\n", __func__, dev->name);
struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
int channel;
- channel = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ channel = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (channel < 0)
return -EINVAL;
plat->channel = channel;
* There is no compatible string in the sub-nodes, so we must manually
* bind these
*/
- for (offset = fdt_first_subnode(blob, mux->of_offset);
+ for (offset = fdt_first_subnode(blob, dev_of_offset(mux));
offset > 0;
offset = fdt_next_subnode(blob, offset)) {
struct udevice *dev;
{
struct pca954x_priv *priv = dev_get_priv(dev);
- priv->addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ priv->addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
if (!priv->addr) {
debug("MUX not found\n");
return -ENODEV;
if (!dev->base)
return -ENOMEM;
- dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"cell-index", -1);
- dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"u-boot,i2c-slave-addr", 0x0);
- dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->speed = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"clock-frequency", 100000);
return 0;
}
{
struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
const void *fdt = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
fdt_addr_t addr;
int ret, ret2;
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
int node;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
{
struct tegra186_bpmp_i2c *priv = dev_get_priv(dev);
- priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"nvidia,bpmp-bus-id", U32_MAX);
if (priv->bpmp_bus_id == U32_MAX) {
debug("%s: could not parse nvidia,bpmp-bus-id\n", __func__);
struct stdio_dev *sdev = &uc_priv->sdev;
struct input_config *input = &uc_priv->input;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
if (cros_ec_keyb_decode_fdt(blob, node, priv))
struct input_config *input = &uc_priv->input;
int ret;
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"intel,duplicate-por"))
priv->quirks |= QUIRK_DUP_POR;
struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
struct stdio_dev *sdev = &uc_priv->sdev;
struct input_config *input = &uc_priv->input;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
priv->kbc = (struct kbc_tegra *)dev_get_addr(dev);
int node;
int ret;
- for (node = fdt_first_subnode(blob, parent->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(parent));
node > 0;
node = fdt_next_subnode(blob, node)) {
struct led_uclass_plat *uc_plat;
debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"mboxes", "#mbox-cells", 0,
index, &args);
if (ret) {
debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"mbox-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
{
struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
char id[MSG_BYTES];
cdev->dev = dev;
#define debug_trace(fmt, b...)
#endif
+/**
+ * Request format for protocol v3
+ * byte 0 0xda (EC_COMMAND_PROTOCOL_3)
+ * byte 1-8 struct ec_host_request
+ * byte 10- response data
+ */
+struct ec_host_request_i2c {
+ /* Always 0xda to backward compatible with v2 struct */
+ uint8_t command_protocol;
+ struct ec_host_request ec_request;
+} __packed;
+
+/*
+ * Response format for protocol v3
+ * byte 0 result code
+ * byte 1 packet_length
+ * byte 2-9 struct ec_host_response
+ * byte 10- response data
+ */
+struct ec_host_response_i2c {
+ uint8_t result;
+ uint8_t packet_length;
+ struct ec_host_response ec_response;
+} __packed;
+
+static int cros_ec_i2c_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+ struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+ struct ec_host_request_i2c *ec_request_i2c =
+ (struct ec_host_request_i2c *)dev->dout;
+ struct ec_host_response_i2c *ec_response_i2c =
+ (struct ec_host_response_i2c *)dev->din;
+ struct i2c_msg i2c_msg[2];
+ int ret;
+
+ i2c_msg[0].addr = chip->chip_addr;
+ i2c_msg[0].flags = 0;
+ i2c_msg[1].addr = chip->chip_addr;
+ i2c_msg[1].flags = I2C_M_RD;
+
+ /* one extra byte, to indicate v3 */
+ i2c_msg[0].len = out_bytes + 1;
+ i2c_msg[0].buf = dev->dout;
+
+ /* stitch on EC_COMMAND_PROTOCOL_3 */
+ memmove(&ec_request_i2c->ec_request, dev->dout, out_bytes);
+ ec_request_i2c->command_protocol = EC_COMMAND_PROTOCOL_3;
+
+ /* two extra bytes for v3 */
+ i2c_msg[1].len = in_bytes + 2;
+ i2c_msg[1].buf = dev->din;
+
+ ret = dm_i2c_xfer(udev, &i2c_msg[0], 2);
+ if (ret) {
+ printf("%s: Could not execute transfer: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* When we send a v3 request to v2 ec, ec won't recognize the 0xda
+ * (EC_COMMAND_PROTOCOL_3) and will return with status
+ * EC_RES_INVALID_COMMAND with zero data length
+ *
+ * In case of invalid command for v3 protocol the data length
+ * will be at least sizeof(struct ec_host_response)
+ */
+ if (ec_response_i2c->result == EC_RES_INVALID_COMMAND &&
+ ec_response_i2c->packet_length == 0)
+ return -EPROTONOSUPPORT;
+
+ if (ec_response_i2c->packet_length < sizeof(struct ec_host_response)) {
+ printf("%s: response of %u bytes too short; not a full hdr\n",
+ __func__, ec_response_i2c->packet_length);
+ return -EBADMSG;
+ }
+
+
+ /* drop result and packet_len */
+ memmove(dev->din, &ec_response_i2c->ec_response, in_bytes);
+
+ return in_bytes;
+}
+
static int cros_ec_i2c_command(struct udevice *udev, uint8_t cmd,
int cmd_version, const uint8_t *dout,
int dout_len, uint8_t **dinp, int din_len)
{
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(udev);
+ struct i2c_msg i2c_msg[2];
/* version8, cmd8, arglen8, out8[dout_len], csum8 */
int out_bytes = dout_len + 4;
/* response8, arglen8, in8[din_len], checksum8 */
assert(dout_len >= 0);
assert(dinp);
+ i2c_msg[0].addr = chip->chip_addr;
+ i2c_msg[0].len = out_bytes;
+ i2c_msg[0].buf = dev->dout;
+ i2c_msg[0].flags = 0;
+
/*
* Copy command and data into output buffer so we can do a single I2C
* burst transaction.
*ptr++ = (uint8_t)
cros_ec_calc_checksum(dev->dout, dout_len + 3);
+ i2c_msg[1].addr = chip->chip_addr;
+ i2c_msg[1].len = in_bytes;
+ i2c_msg[1].buf = in_ptr;
+ i2c_msg[1].flags = I2C_M_RD;
+
/* Send output data */
cros_ec_dump_data("out", -1, dev->dout, out_bytes);
- ret = dm_i2c_write(udev, 0, dev->dout, out_bytes);
+
+ ret = dm_i2c_xfer(udev, &i2c_msg[0], 2);
if (ret) {
- debug("%s: Cannot complete I2C write to %s\n", __func__,
+ debug("%s: Could not execute transfer to %s\n", __func__,
udev->name);
ret = -1;
}
- if (!ret) {
- ret = dm_i2c_read(udev, 0, in_ptr, in_bytes);
- if (ret) {
- debug("%s: Cannot complete I2C read from %s\n",
- __func__, udev->name);
- ret = -1;
- }
- }
-
if (*in_ptr != EC_RES_SUCCESS) {
debug("%s: Received bad result code %d\n", __func__, *in_ptr);
return -(int)*in_ptr;
static struct dm_cros_ec_ops cros_ec_ops = {
.command = cros_ec_i2c_command,
+ .packet = cros_ec_i2c_packet,
};
static const struct udevice_id cros_ec_ids[] = {
int err;
memcpy(ec, &s_state, sizeof(*ec));
- err = cros_ec_decode_ec_flash(blob, dev->of_offset, &ec->ec_config);
+ err = cros_ec_decode_ec_flash(blob, dev_of_offset(dev), &ec->ec_config);
if (err)
return err;
keyb_dev;
device_find_next_child(&keyb_dev)) {
if (device_get_uclass_id(keyb_dev) == UCLASS_KEYBOARD) {
- node = keyb_dev->of_offset;
+ node = dev_of_offset(keyb_dev);
break;
}
}
{
struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
- plat->size = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->size = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"sandbox,size", 32);
- plat->filename = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->filename = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"sandbox,filename", NULL);
if (!plat->filename) {
debug("%s: No filename for device '%s'\n", __func__,
* be ignored.
* @return: 0 on success, or negative value on failure
*/
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
+static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr)
{
uint32_t size, align;
struct fw_file *file;
}
/* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
+ulong write_acpi_tables(ulong addr)
{
int i, ret = 0;
struct fw_file *file;
debug("%s(dev=%p)\n", __func__, dev);
ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
- dev->of_offset, &child);
+ dev_of_offset(dev), &child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra186_reset",
- "tegra186_reset", dev->of_offset,
+ "tegra186_reset", dev_of_offset(dev),
&child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
"tegra186_power_domain",
- dev->of_offset, &child);
+ dev_of_offset(dev), &child);
if (ret)
return ret;
struct fdtdec_phandle_args args;
fdt_addr_t reg;
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"shmem", NULL, 0, index, &args);
if (ret < 0) {
error("fdtdec_parse_phandle_with_args() failed: %d\n", ret);
debug("%s(dev=%p)\n", __func__, dev);
ret = device_bind_driver_to_node(dev, "tegra_car_clk", "tegra_car_clk",
- dev->of_offset, &child);
+ dev_of_offset(dev), &child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra_car_reset",
- "tegra_car_reset", dev->of_offset,
+ "tegra_car_reset", dev_of_offset(dev),
&child);
if (ret)
return ret;
host->ioaddr = (void *)dev_get_addr(dev);
host->quirks = 0;
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
struct dwmci_host *host = &priv->host;
int err;
- err = exynos_dwmci_get_config(gd->fdt_blob, dev->of_offset, host);
+ err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
if (err)
return err;
err = do_dwmci_init(host);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
fdt_addr_t addr;
unsigned int val;
int ret;
static int msm_sdc_clk_init(struct udevice *dev)
{
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
- "clock-frequency", 400000);
+ int node = dev_of_offset(dev);
+ uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
+ 400000);
uint clkd[2]; /* clk_id and clk_no */
int clk_offset;
struct udevice *clk_dev;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
- 2);
+ ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
if (ret)
return ret;
struct udevice *parent = dev->parent;
struct msm_sdhc *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
+ int node = dev_of_offset(dev);
host->name = strdup(dev->name);
host->ioaddr = (void *)dev_get_addr(dev);
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "bus-width", 4);
- host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
+ host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- parent->of_offset,
- dev->of_offset,
- "reg", 1, NULL,
- false);
+ dev_of_offset(parent), node, "reg", 1, NULL, false);
if (priv->base == (void *)FDT_ADDR_T_NONE ||
host->ioaddr == (void *)FDT_ADDR_T_NONE)
return -EINVAL;
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mmc_config *cfg;
int val;
fdt_size_t size;
int ret;
- addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
host->ioaddr = ioremap(addr, size);
host->name = dev->name;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
host->ops = &pic32_sdhci_ops;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", f_min_max, 2);
if (ret) {
printf("sdhci: clock-freq-min-max not found\n");
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
- host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
/* use non-removeable as sdcard and emmc as judgement */
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "non-removable"))
host->dev_index = 0;
else
host->dev_index = 1;
- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
if (priv->fifo_depth < 0)
return -EINVAL;
- priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
- if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2))
return -EINVAL;
#endif
struct clk clk;
- max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", 0);
ret = clk_get_by_index(dev, 0, &clk);
if (!ret) {
struct sdhci_host *host = dev_get_priv(dev);
int ret;
- ret = sdhci_get_config(gd->fdt_blob, dev->of_offset, host);
+ ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
if (ret)
return ret;
return -EINVAL;
}
- fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
if (fifo_depth < 0) {
printf("DWMMC: Can't get FIFO depth\n");
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
- host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
host->clksel = socfpga_dwmci_clksel;
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
- priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"drvsel", 3);
- priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"smplsel", 0);
host->priv = priv;
priv->cfg.name = "Tegra SD/MMC";
priv->cfg.ops = &tegra_mmc_ops;
- bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width",
- 1);
+ bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 1);
priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
priv->cfg.host_caps = 0;
plat->cfg.name = dev->name;
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
- switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
+ switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
+ 1)) {
case 8:
plat->cfg.host_caps |= MMC_MODE_8BIT;
break;
return -EINVAL;
}
- if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable",
+ if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
NULL))
priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
armada_3700_soc_pad_voltage_set(host);
host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
- switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
+ switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
+ 1)) {
case 8:
host->host_caps |= MMC_MODE_8BIT;
break;
if (of_device_is_compatible(dev, "marvell,armada-3700-sdhci"))
priv->pad_ctrl_reg = (void *)dev_get_addr_index(dev, 1);
- name = fdt_getprop(gd->fdt_blob, dev->of_offset, "marvell,pad-type",
+ name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);
if (name) {
if (0 == strncmp(name, "sd", 2)) {
{
struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
void *base;
static int cfi_flash_probe(struct udevice *dev)
{
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const fdt32_t *cell;
phys_addr_t addr;
int parent, addrc, sizec;
static int pic32_flash_probe(struct udevice *dev)
{
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
unsigned long addr, size;
{
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
pdata->filename = fdt_getprop(blob, node, "sandbox,filename", NULL);
pdata->device_name = fdt_getprop(blob, node, "compatible", NULL);
debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ",
__func__, busnum, cs);
ret = sandbox_sf_bind_emul(state, busnum, cs, bus,
- slave->of_offset, slave->name);
+ dev_of_offset(slave), slave->name);
if (ret) {
debug("failed (err=%d)\n", ret);
return ret;
#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
fdt_size_t size;
- int node = flash->dev->of_offset;
+ int node = dev_of_offset(flash->dev);
addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
{
int offset;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy");
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
if (offset <= 0) {
debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
return -EINVAL;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct altera_tse_priv *priv = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
void *base, *desc_mem = NULL;
const char *phy_mode;
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
int slave, u8 *mac_addr)
{
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u32 macid_lsb;
u32 macid_msb;
fdt32_t gmii = 0;
u8 *mac_addr)
{
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u32 macid_lo;
u32 macid_hi;
fdt32_t gmii = 0;
if (of_device_is_compatible(dev, "ti,dm816-emac"))
return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
- if (of_machine_is_compatible("ti,am4372"))
+ if (of_machine_is_compatible("ti,am43"))
return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
if (of_machine_is_compatible("ti,dra7"))
#ifdef CONFIG_DM_ETH
if (slave->data->phy_of_handle)
- phydev->dev->of_offset = slave->data->phy_of_handle;
+ dev_set_of_offset(phydev->dev, slave->data->phy_of_handle);
#endif
priv->phydev = phydev;
const char *phy_mode;
const char *phy_sel_compat = NULL;
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int subnode;
int slave_index = 0;
int active_slave;
pdata->iobase = dev_get_addr(dev);
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
pdata->max_speed = 0;
- cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
+ cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
#ifdef CONFIG_DM_GPIO
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-active-low"))
reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
&priv->reset_gpio, reset_flags);
if (ret == 0) {
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-delays-us", dw_pdata->reset_delays, 3);
} else if (ret == -ENOENT) {
ret = 0;
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
- pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"tx-delay", 0x30);
- pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"rx-delay", 0x10);
return designware_eth_ofdata_to_platdata(dev);
struct ks2_eth_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
- int slave = dev->of_offset;
+ int slave = dev_of_offset(dev);
int interfaces;
int gbe;
int netcp_devices;
int netcp_devices;
int gbe;
- netcp_devices = fdt_subnode_offset(fdt, dev->of_offset,
+ netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
"netcp-devices");
gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
ks2_eth_bind_slaves(dev, gbe, &gbe_0);
- ks2_eth_parse_slave_interface(dev->of_offset, gbe_0, priv, pdata);
+ ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
pdata->iobase = dev_get_addr(dev);
#ifdef CONFIG_DM_ETH
const char *phy_mode;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
macb->phy_interface = phy_get_interface_by_name(phy_mode);
if (macb->phy_interface == -1) {
struct eth_pdata *pdata = dev_get_platdata(dev);
struct mvneta_port *pp = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mii_dev *bus;
unsigned long addr;
void *bd_space;
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
return err;
}
- return mvpp2_port_probe(dev, port, dev->of_offset, priv,
+ return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
&buffer_loc.first_rxq);
}
static int mvpp2_base_bind(struct udevice *parent)
{
const void *blob = gd->fdt_blob;
- int node = parent->of_offset;
+ int node = dev_of_offset(parent);
struct uclass_driver *drv;
struct udevice *dev;
struct eth_pdata *plat;
/* Create child device UCLASS_ETH and bind it */
device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
- dev->of_offset = subnode;
+ dev_set_of_offset(dev, subnode);
}
return 0;
return -EOPNOTSUPP;
for (i = 0; i < ofcfg->grpsz; i++) {
- val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
ofcfg->grp[i].name, -1);
offset = ofcfg->grp[i].off;
if (val[i] == -1) {
struct dp83867_private *dp83867 = phydev->priv;
struct udevice *dev = phydev->dev;
- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,rx-internal-delay", -1);
- dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,tx-internal-delay", -1);
- dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,fifo-depth", -1);
return 0;
u32 phytype;
debug("%s\n", __func__);
- phytype = fdtdec_get_int(gd->fdt_blob, phydev->dev->of_offset,
+ phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
"phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
int offset = 0;
int phy_addr = -1;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
/* get phy mode */
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
/* get phy addr */
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
/* phy reset gpio */
- gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset,
+ gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
"reset-gpios", 0,
&priv->rst_gpio, GPIOD_IS_OUT);
debug("eth_sandbox_raw: Start\n");
- interface = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ interface = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"host-raw-interface", NULL);
if (interface == NULL)
return -EINVAL;
debug("eth_sandbox: Start\n");
- fdtdec_get_byte_array(gd->fdt_blob, dev->of_offset, "fake-host-hwaddr",
- priv->fake_host_hwaddr, ARP_HLEN);
+ fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(dev),
+ "fake-host-hwaddr", priv->fake_host_hwaddr,
+ ARP_HLEN);
priv->recv_packet_buffer = net_rx_packets[0];
return 0;
}
const char *pin_name;
int drive, pull, i;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"pinctrl-0");
if (offset < 0) {
printf("WARNING: emac: cannot find pinctrl-0 node\n");
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
+ int node = dev_of_offset(dev);
int offset = 0;
pdata->iobase = dev_get_addr_name(dev, "emac");
priv->phyaddr = -1;
priv->use_internal_phy = false;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"phy");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
-1);
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
}
if (priv->variant == H3_EMAC) {
- if (fdt_getprop(gd->fdt_blob, dev->of_offset,
+ if (fdt_getprop(gd->fdt_blob, node,
"allwinner,use-internal-phy", NULL))
priv->use_internal_phy = true;
}
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->regs = (struct tsec *)pdata->iobase;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0) {
reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
return -ENOENT;
}
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"tbi-handle");
if (offset > 0) {
reg = fdtdec_get_int(gd->fdt_blob, offset, "reg",
priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
}
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"phy-connection-type", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct axidma_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct axi_regs *)pdata->iobase;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"axistream-connected");
if (offset <= 0) {
printf("%s: axistream is not found\n", __func__);
priv->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
- "phy-handle");
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
emaclite->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
- emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
- emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
priv->phydev->advertising = priv->phydev->supported;
if (priv->phy_of_handle > 0)
- priv->phydev->dev->of_offset = priv->phy_of_handle;
+ dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
return phy_config(priv->phydev);
}
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->emio = 0;
priv->phyaddr = -1;
- priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
- dev->of_offset, "phy-handle");
+ priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
+ "phy-handle");
if (priv->phy_of_handle > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
priv->phy_of_handle, "reg", -1);
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
priv->interface = pdata->phy_interface;
- priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
+ priv->emio = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,emio");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
/* For bridges, use the top-level PCI controller */
if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
- ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
- bus->of_offset);
+ ret = decode_regions(hose, gd->fdt_blob,
+ dev_of_offset(bus->parent),
+ dev_of_offset(bus));
if (ret) {
debug("%s: Cannot decode regions\n", __func__);
return ret;
struct fdt_pci_addr addr;
int ret;
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
/*
* just check the address.
*/
pplat = dev_get_parent_platdata(dev);
- ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_CONFIG, "reg", &addr);
if (ret) {
goto err;
#endif
} else {
-#ifdef CONFIG_X86
+#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT)
bios_set_interrupt_handler(0x15, int15_handler);
bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
INIT_LIST_HEAD(&pcie->ports);
- if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie))
+ if (tegra_pcie_parse_dt(gd->fdt_blob, dev_of_offset(dev), id, pcie))
return -EINVAL;
return 0;
{
struct ls_pcie *pcie = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u8 header_type;
u16 link_sta;
bool ep_mode;
DECLARE_GLOBAL_DATA_PTR;
int err;
- err = fdt_get_resource(gd->fdt_blob, dev->of_offset, "reg",
+ err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
0, ®_res);
if (err < 0) {
error("\"reg\" resource not found\n");
static int comphy_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
int subnode;
u32 cell[2];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
u32 cell[2];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
const void *fdt = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
unsigned int pinfunc, pinpud, pindrv;
unsigned long reg, value;
int node, gpio = -1, len;
int na, ns;
- na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (na < 1) {
debug("bad #address-cells\n");
return -EINVAL;
}
- ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (ns < 1) {
debug("bad #size-cells\n");
return -EINVAL;
}
- fdt_for_each_subnode(node, gd->fdt_blob, dev->of_offset) {
+ fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
gpio = node;
break;
int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
const void *blob = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
struct mvebu_pinctrl_priv *priv;
u32 pin_arr[MVEBU_MAX_PINS_PER_BANK];
u32 function;
struct udevice *config)
{
const void *blob = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
struct mvebu_pinctrl_priv *priv;
u32 func_arr[MVEBU_MAX_PINS_PER_BANK];
int pin, err;
int mvebu_pinctl_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mvebu_pinctrl_priv *priv;
priv = dev_get_priv(dev);
{
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
struct imx_pinctrl_soc_info *info = priv->info;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
const struct fdt_property *prop;
u32 *pin_data;
int npins, size, pin_size;
struct imx_pinctrl_soc_info *info)
{
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
- int node = dev->of_offset, ret;
+ int node = dev_of_offset(dev), ret;
struct fdtdec_phandle_args arg;
fdt_addr_t addr;
fdt_size_t size;
priv->dev = dev;
priv->info = info;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct atmel_pio4_port *bank_base;
const void *blob = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
u32 offset, func, bank, line;
u32 cells[MAX_PINMUX_ENTRIES];
u32 i, conf;
bool is_group, unsigned selector)
{
const void *fdt = gd->fdt_blob;
- int node_offset = config->of_offset;
+ int node_offset = dev_of_offset(config);
const char *propname;
const void *value;
int prop_offset, len, func_selector, param, ret;
struct udevice *config)
{
const void *fdt = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
const char *subnode_target_type = "pins";
bool is_group = false;
const char *name;
static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
{
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
char propname[32]; /* long enough */
const fdt32_t *list;
uint32_t phandle;
static int pinconfig_post_bind(struct udevice *dev)
{
const void *fdt = gd->fdt_blob;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
int ret;
u32 cell[2];
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
struct fdt_resource res;
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
u32 cell[60], *ptr;
debug("%s: %s %s\n", __func__, dev->name, config->name);
- ret = fdtdec_get_int_array_count(blob, config->of_offset,
+ ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
"rockchip,pins", cell,
ARRAY_SIZE(cell));
if (ret < 0) {
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
debug("%s(dev=%p, power_domain=%p)\n", __func__, dev, power_domain);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"power-domains",
"#power-domain-cells", 0, 0,
&args);
int regulators_node;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
debug("%s:%d Setting PMIC default registers\n", __func__, __LINE__);
- reg_defaults = fdtdec_locate_byte_array(gd->fdt_blob, emul->of_offset,
- "reg-defaults",
- SANDBOX_PMIC_REG_COUNT);
+ reg_defaults = fdtdec_locate_byte_array(gd->fdt_blob,
+ dev_of_offset(emul), "reg-defaults",
+ SANDBOX_PMIC_REG_COUNT);
if (!reg_defaults) {
error("Property \"reg-defaults\" not found for device: %s!",
int regulators_node;
const void *blob = gd->fdt_blob;
int children;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
regulators_node = fdt_subnode_offset(blob, node, "regulators");
const void *blob = gd->fdt_blob;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"voltage-regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
int pmic_node = -1, regulators_node;
const void *blob = gd->fdt_blob;
int children;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int subnode, len;
fdt_for_each_subnode(subnode, blob, node) {
int regulators_node;
const void *blob = gd->fdt_blob;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
int ret;
debug("%s for '%s' at node offset: %d\n", __func__, pmic->name,
- pmic->of_offset);
+ dev_of_offset(pmic));
for (node = fdt_first_subnode(blob, offset);
node > 0;
int regulators_node;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
const void *blob = gd->fdt_blob;
int children;
- node = fdt_subnode_offset(blob, dev->of_offset, "regulators");
+ node = fdt_subnode_offset(blob, dev_of_offset(dev), "regulators");
if (node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
dev->name);
static int sandbox_pmic_bind(struct udevice *dev)
{
- if (!pmic_bind_children(dev, dev->of_offset, pmic_children_info))
+ if (!pmic_bind_children(dev, dev_of_offset(dev), pmic_children_info))
error("%s:%d PMIC: %s - no child found!", __func__, __LINE__,
dev->name);
const void *blob = gd->fdt_blob;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
struct fixed_regulator_platdata *dev_pdata;
struct gpio_desc *gpio;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset, flags = GPIOD_IS_OUT;
+ int node = dev_of_offset(dev), flags = GPIOD_IS_OUT;
int ret;
dev_pdata = dev_get_platdata(dev);
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = fdtdec_get_uint(gd->fdt_blob,
- dev->of_offset,
+ dev_of_offset(dev),
"startup-delay-us", 0);
return 0;
struct gpio_regulator_platdata *dev_pdata;
struct gpio_desc *gpio;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret, count, i, j;
u32 states_array[8];
case 8:
case 9:
case 10:
- idx = dev->driver_data - 4;
+ idx = dev->driver_data - 3;
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
uc_pdata->volt_reg = palmas_smps_volt[type][idx];
break;
struct pwm_regulator_info *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
static int regulator_post_bind(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
const char *property = "regulator-name";
static int regulator_pre_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
uc_pdata = dev_get_uclass_platdata(dev);
if (!uc_pdata)
#ccflags-y += -DDEBUG
-obj-$(CONFIG_DM_PWM) += pwm-uclass.o
-obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
-obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
-ifdef CONFIG_DM_PWM
-obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
-obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
-endif
+obj-$(CONFIG_DM_PWM) += pwm-uclass.o
+
+obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
+obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
+obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
+obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
if (!dev->platdata) {
#if CONFIG_IS_ENABLED(OF_CONTROL)
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
bool tmp;
if (!blob) {
static int ti_of_to_priv(struct udevice *dev,
struct ti_powerproc_privdata *priv)
{
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
int tmp;
debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
reset_ctl);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"resets", "#reset-cells", 0,
index, &args);
if (ret) {
debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
reset_ctl);
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"reset-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct altera_uart_regs),
MAP_NOCACHE);
- plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
return 0;
int ret;
/* we prefer to use a memory-mapped register */
- ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
- dev->of_offset,
+ dev_of_offset(dev),
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
#endif
- plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"reg-offset", 0);
- plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"reg-shift", 0);
err = clk_get_by_index(dev, 0, &clk);
}
if (!plat->clock)
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
int i;
plat->colour = -1;
- colour = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ colour = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"sandbox,text-colour", NULL);
if (colour) {
for (i = 0; i < ARRAY_SIZE(ansi_colour); i++) {
DECLARE_GLOBAL_DATA_PTR;
plat->reg = (struct arc_serial_regs *)dev_get_addr(dev);
- plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
return 0;
return -EINVAL;
plat->base = addr;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
- plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
+ 1);
+ plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"skip-init");
plat->disabled = false;
return 0;
static int msm_uart_clk_init(struct udevice *dev)
{
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 115200);
uint clkd[2]; /* clk_id and clk_no */
int clk_offset;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
- 2);
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
+ clkd, 2);
if (ret)
return ret;
plat->reg = (struct mxc_uart *)addr;
- plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fsl,dte-mode");
return 0;
}
int ret;
/* get address */
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
return -EINVAL;
plat->base = addr;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
+ 1);
plat->type = dev_get_driver_data(dev);
- plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"skip-init");
return 0;
}
return -EINVAL;
plat->reg = (struct s5p_uart *)addr;
- plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"id", dev->seq);
return 0;
}
struct sh_serial_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
- plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+ plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
+ 1);
plat->type = dev_get_driver_data(dev);
return 0;
}
priv->membase = port;
- priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
tmp = readl(&port->lcr_mcr);
{
struct cadence_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int subnode;
u32 data[4];
int ret;
{
struct davinci_spi_slave *ds = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
ds->regs = dev_map_physmem(bus, sizeof(struct davinci_spi_regs));
if (!ds->regs) {
{
struct dw_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct dw_spi *)dev_get_addr(bus);
{
struct exynos_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct exynos_spi *)dev_get_addr(bus);
plat->periph_id = pinmux_decode_periph_id(blob, node);
fdt_addr_t addr;
struct fsl_dspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
struct fdt_resource res_regs, res_mem;
struct fsl_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int ret, flash_num = 0, subnode;
if (fdtdec_get_bool(blob, node, "big-endian"))
static int ich_spi_ofdata_to_platdata(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ int node = dev_of_offset(dev);
int ret;
- ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
- "intel,ich7-spi");
+ ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
if (ret == 0) {
plat->ich_version = ICHV_7;
} else {
- ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+ ret = fdt_node_check_compatible(gd->fdt_blob, node,
"intel,ich9-spi");
if (ret == 0)
plat->ich_version = ICHV_9;
* it should be used to read the input clock and the DT property
* can be removed.
*/
- plat->clock = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"clock-frequency", 160000);
- plat->frequency = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ plat->frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"spi-max-frequency", 40000);
return 0;
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct omap2_mcspi_platform_config* data =
(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
{
struct pic32_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
+ int node = dev_of_offset(bus);
struct udevice *clkdev;
fdt_addr_t addr;
fdt_size_t size;
int ret;
debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
- addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
if (!priv->regs)
return -EINVAL;
- dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
- "spi-max-frequency", 250000000);
+ dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
+ 250000000);
/* get clock rate */
ret = clk_get_by_index(bus, 0, &clkdev);
if (ret < 0) {
* of the ongoing transfer. To avoid this sort of error we will drive
* /CS manually by toggling cs-gpio pins.
*/
- ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
- "cs-gpios", 0,
+ ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "cs-gpios", 0,
&priv->cs_gpio, GPIOD_IS_OUT);
if (ret) {
printf("pic32-spi: error, cs-gpios not found\n");
struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int ret;
plat->base = dev_get_addr(bus);
{
struct soft_spi_platdata *plat = dev->platdata;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
{
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
- return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
+ return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev_of_offset(dev),
+ plat);
}
#endif
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
- spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ spi->max_hz = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"spi-max-frequency", 0);
#endif
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct fdt_resource res_regs, res_mem;
struct stm32_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int ret;
ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
fdt_addr_t addr;
void *mmap;
{
struct zynq_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
node, "reg");
{
struct zynq_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
{
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
int i;
priv->arb_chnl = dev_get_addr(dev);
priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- parent->of_offset,
- dev->of_offset,
- "reg", 1, NULL,
- false);
+ dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- parent->of_offset,
- dev->of_offset, "reg",
- 2, NULL, false);
+ dev_of_offset(parent), node, "reg", 2, NULL, false);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
* (see the U_BOOT_DEVICE() declaration below) should not do anything.
* If we are that device, return an error.
*/
- if (state->fdt_fname && dev->of_offset == -1)
+ if (state->fdt_fname && dev_of_offset(dev) == -1)
return -ENODEV;
switch (type) {
uc_priv->clock_rate = ret;
} else
uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
- dev->of_offset, "clock-frequency", 0);
+ dev_of_offset(dev), "clock-frequency", 0);
return 0;
}
struct sandbox_flash_plat *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- plat->pathname = fdt_getprop(blob, dev->of_offset, "sandbox,filepath",
- NULL);
+ plat->pathname = fdt_getprop(blob, dev_of_offset(dev),
+ "sandbox,filepath", NULL);
return 0;
}
{
struct sandbox_hub_platdata *plat = dev_get_parent_platdata(dev);
- plat->port = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ plat->port = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg",
+ -1);
return 0;
}
return -EINVAL;
priv->regs = (struct dwc2_core_regs *)addr;
- prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "disable-over-current",
- NULL);
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ "disable-over-current", NULL);
if (prop)
priv->oc_disable = true;
}
depth = 0;
- node = fdtdec_next_compatible_subnode(blob, dev->of_offset,
+ node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
if (node <= 0) {
debug("XHCI: Can't get device node for usb3-phy controller\n");
struct ehci_fsl_priv *priv = dev_get_priv(dev);
const void *prop;
- prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy_type",
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
NULL);
if (prop) {
priv->phy_type = (char *)prop;
void *__iomem addr = (void *__iomem)dev_get_addr(dev);
void *__iomem phy_ctrl, *__iomem phy_status;
const void *blob = gd->fdt_blob;
- int offset = dev->of_offset, phy_off;
+ int offset = dev_of_offset(dev), phy_off;
u32 val;
/*
struct usb_platdata *plat = dev_get_platdata(dev);
const char *mode;
- mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "dr_mode", NULL);
+ mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
if (mode) {
if (strcmp(mode, "peripheral") == 0)
plat->init_type = USB_INIT_DEVICE;
static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *phy, *mode;
config->reg = (struct usb_ctlr *)dev_get_addr(dev);
{
struct ehci_vf_priv_data *priv = dev_get_priv(dev);
const void *dt_blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *mode;
priv->portnr = dev->seq;
const void *blob = gd->fdt_blob;
int val;
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
/* We only support matching a few things */
- val = fdtdec_get_int(blob, dev->of_offset, "usb,device-class", -1);
+ val = fdtdec_get_int(blob, dev_of_offset(dev), "usb,device-class", -1);
if (val != -1) {
plat->id.match_flags |= USB_DEVICE_ID_MATCH_DEV_CLASS;
plat->id.bDeviceClass = val;
}
- val = fdtdec_get_int(blob, dev->of_offset, "usb,interface-class", -1);
+ val = fdtdec_get_int(blob, dev_of_offset(dev), "usb,interface-class",
+ -1);
if (val != -1) {
plat->id.match_flags |= USB_DEVICE_ID_MATCH_INT_CLASS;
plat->id.bInterfaceClass = val;
}
depth = 0;
- node = fdtdec_next_compatible_subnode(blob, dev->of_offset,
+ node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
if (node <= 0) {
debug("XHCI: Can't get device node for usb3-phy controller\n");
/* Set dwc3 usb2 phy config */
reg = readl(&dwc3_reg->g_usb2phycfg[0]);
- if (fdtdec_get_bool(blob, dev->of_offset,
+ if (fdtdec_get_bool(blob, dev_of_offset(dev),
"snps,dis-enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
- utmi_bits = fdtdec_get_int(blob, dev->of_offset,
+ utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev),
"snps,phyif-utmi-bits", -1);
if (utmi_bits == 16) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;
reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
}
- if (fdtdec_get_bool(blob, dev->of_offset,
+ if (fdtdec_get_bool(blob, dev_of_offset(dev),
"snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
- if (fdtdec_get_bool(blob, dev->of_offset,
+ if (fdtdec_get_bool(blob, dev_of_offset(dev),
"snps,dis-u2-susphy-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
struct musb_host_data *mdata = &pdata->mdata;
struct fdt_resource mc, glue;
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
void __iomem *mregs;
int ret;
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int phys;
int ctrl_mod;
int usb_index;
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = ti_musb_ofdata_to_platdata(dev);
int node;
int ret;
- for (node = fdt_first_subnode(fdt, parent->of_offset); node > 0;
+ for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
node = fdt_next_subnode(fdt, node)) {
struct udevice *dev;
const char *name = fdt_get_name(fdt, node, NULL);
struct display_timing *timing = &priv->timing;
const void *blob = gd->fdt_blob;
- if (fdtdec_decode_display_timing(blob, dev->of_offset,
+ if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
plat->timing_index, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
if (ret)
return ret;
- params = fdt_getprop(gd->fdt_blob, dev->of_offset, "parade,regs", &len);
+ params = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "parade,regs",
+ &len);
if (!params || len % 3) {
debug("%s: missing/invalid params=%p, len=%x\n", __func__,
params, len);
{
struct broadwell_igd_plat *plat = dev_get_platdata(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
{
struct exynos_dp_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- unsigned int node = dev->of_offset;
+ unsigned int node = dev_of_offset(dev);
fdt_addr_t addr;
addr = dev_get_addr(dev);
unsigned int offset;
unsigned int node;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
exynos_fimd_disable_sysmmu();
int exynos_fb_ofdata_to_platdata(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
- unsigned int node = dev->of_offset;
+ unsigned int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
fdt_addr_t addr;
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct gt_powermeter {
u16 reg;
u32 value;
static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u32 reg32, cycle_delay;
debug("GT Power Management Init (post VBIOS)\n");
mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
mtrr_commit(true);
- gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
+ gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
debug("GT bar %p\n", gtt_bar);
ret = gma_pm_init_pre_vbios(gtt_bar, rev);
if (ret)
return ret;
/* Post VBIOS init */
- gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
+ gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
if (ret)
return ret;
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int index, ret, count, len;
const u32 *cell;
int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
{
if (fdtdec_decode_display_timing
- (gd->fdt_blob, dev->of_offset, 0, timing)) {
+ (gd->fdt_blob, dev_of_offset(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
priv->regs = (void *)dev_get_addr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
* clock so it is currently not possible to use more than one display
* device simultaneously.
*/
- port = fdt_subnode_offset(blob, dev->of_offset, "port");
+ port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
if (port < 0)
return -EINVAL;
for (node = fdt_first_subnode(blob, port);
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct sandbox_sdl_plat *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret = 0;
plat->xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
struct display_timing *timing;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int panel_node;
int rgb;
int ret;
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int rgb;
rgb = fdt_subnode_offset(blob, node, "rgb");
return ret;
}
- dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev->of_offset,
+ dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
"reg");
- if (fdtdec_decode_display_timing(blob, dev->of_offset, 0, timing)) {
+ if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
/* Use the first display controller */
debug("%s\n", __func__);
- node = dc_dev->of_offset;
+ node = dev_of_offset(dc_dev);
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
tegra_dc_sor_enable_dc(disp_ctrl);
debug("%s\n", __func__);
/* Use the first display controller */
- node = dc_dev->of_offset;
+ node = dev_of_offset(dc_dev);
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
/* Sleep mode */
int node;
int ret;
- priv->base = (void *)fdtdec_get_addr(blob, dev->of_offset, "reg");
+ priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
if (node < 0) {
/bmp_logo.h
/bmp_logo_data.h
/config.h
-/license.h
#define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */
#define CONFIG_CMD_UBIFS /* UBIFS Support */
#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */
-#define CONFIG_CMD_UNZIP /* unzip from memory to memory */
#define CONFIG_CMD_ZFS /* ZFS Support */
#endif /* _CONFIG_CMD_ALL_H */
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
-#define CONFIG_API 1
-
#endif /* __CONFIG_H */
#ifdef CONFIG_USB_MUSB_HCD
-#define CONGIG_CMD_STORAGE
-
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#ifdef CONFIG_USB_MUSB_HOST
-#define CONGIG_CMD_STORAGE
-
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4)
-#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_BMP
#define CONFIG_BMP_24BMP
#define CONFIG_BMP_32BPP
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x003f8000
+#define CONFIG_SPL_FRAMEWORK
+
+#define CONFIG_SPL_TEXT_BASE 0xfffd0000
+
+#define BOOT_DEVICE_SPI 10
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#define BOOT_DEVICE_BOARD 11
+
#endif /* __CONFIG_H */
/*#define CONFIG_SUPPORT_EMMC_BOOT */
#define CONFIG_CMD_REGINFO /* Register dump */
#define CONFIG_CMD_TFTP
-#define CONFIG_CMD_UNZIP
/* Partition table support */
#define HAVE_BLOCK_DEVICE /* Needed for partition commands */
#define CONFIG_CMD_REISER
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_UNZIP
#endif
/* NAND flash */
#define CONFIG_FS_EXT4
/* Command line configuration */
-#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_ENV
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_NO_FLASH
-/*
- * Enable u-boot API for standalone programs.
- */
-#define CONFIG_API
-
/*
* Commands configuration
*/
#ifdef CONFIG_USB_MUSB_HCD
-#define CONGIG_CMD_STORAGE
-
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SPL_FRAMEWORK
+
+#define CONFIG_SPL_TEXT_BASE 0xfffd0000
+
+#define BOOT_DEVICE_SPI 10
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#define BOOT_DEVICE_BOARD 11
+
#endif /* __CONFIG_H */
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
-#define CONGIG_CMD_STORAGE
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
-#define CONFIG_SPL_STACK_SIZE (8 * 1024)
+#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
- CONFIG_SPL_STACK_SIZE - 4)
+ KEYSTONE_SPL_STACK_SIZE - 4)
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-#ifdef CONFIG_ARM64
-#define CONFIG_CMD_UNZIP
-#endif
-
/*-----------------------------------------------------------------------
* MMU and Cache Setting
*----------------------------------------------------------------------*/
#endif
/*#define CONFIG_MENU_SHOW*/
-#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_ENV
/* BOOTP options */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
-#define CONFIG_CMD_UNZIP
-
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_CLOCKS
/* Returns non-zero if the device is active (probed and not removed) */
#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED)
+static inline int dev_of_offset(const struct udevice *dev)
+{
+ return dev->of_offset;
+}
+
+static inline void dev_set_of_offset(struct udevice *dev, int of_offset)
+{
+ dev->of_offset = of_offset;
+}
+
/**
* struct udevice_id - Lists the compatible strings supported by a driver
* @compatible: Compatible string
* @handle: the structure's handle, a unique 16-bit number
* @return: size of the structure
*/
-typedef int (*smbios_write_type)(uintptr_t *addr, int handle);
+typedef int (*smbios_write_type)(ulong *addr, int handle);
/**
* write_smbios_table() - Write SMBIOS table
* @addr: start address to write SMBIOS table
* @return: end address of SMBIOS table
*/
-uintptr_t write_smbios_table(uintptr_t addr);
+ulong write_smbios_table(ulong addr);
#endif /* _SMBIOS_H_ */
return len + 1;
}
-static int smbios_write_type0(uintptr_t *current, int handle)
+static int smbios_write_type0(ulong *current, int handle)
{
struct smbios_type0 *t = (struct smbios_type0 *)*current;
int len = sizeof(struct smbios_type0);
return len;
}
-static int smbios_write_type1(uintptr_t *current, int handle)
+static int smbios_write_type1(ulong *current, int handle)
{
struct smbios_type1 *t = (struct smbios_type1 *)*current;
int len = sizeof(struct smbios_type1);
return len;
}
-static int smbios_write_type2(uintptr_t *current, int handle)
+static int smbios_write_type2(ulong *current, int handle)
{
struct smbios_type2 *t = (struct smbios_type2 *)*current;
int len = sizeof(struct smbios_type2);
return len;
}
-static int smbios_write_type3(uintptr_t *current, int handle)
+static int smbios_write_type3(ulong *current, int handle)
{
struct smbios_type3 *t = (struct smbios_type3 *)*current;
int len = sizeof(struct smbios_type3);
t->processor_version = smbios_add_string(t->eos, name);
}
-static int smbios_write_type4(uintptr_t *current, int handle)
+static int smbios_write_type4(ulong *current, int handle)
{
struct smbios_type4 *t = (struct smbios_type4 *)*current;
int len = sizeof(struct smbios_type4);
return len;
}
-static int smbios_write_type32(uintptr_t *current, int handle)
+static int smbios_write_type32(ulong *current, int handle)
{
struct smbios_type32 *t = (struct smbios_type32 *)*current;
int len = sizeof(struct smbios_type32);
return len;
}
-static int smbios_write_type127(uintptr_t *current, int handle)
+static int smbios_write_type127(ulong *current, int handle)
{
struct smbios_type127 *t = (struct smbios_type127 *)*current;
int len = sizeof(struct smbios_type127);
smbios_write_type127
};
-uintptr_t write_smbios_table(uintptr_t addr)
+ulong write_smbios_table(ulong addr)
{
struct smbios_entry *se;
- u32 tables;
+ ulong tables;
int len = 0;
int max_struct_size = 0;
int handle = 0;
/* 16 byte align the table address */
addr = ALIGN(addr, 16);
- se = (struct smbios_entry *)addr;
+ se = (struct smbios_entry *)(uintptr_t)addr;
memset(se, 0, sizeof(struct smbios_entry));
addr += sizeof(struct smbios_entry);
/* populate minimum required tables */
for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
- int tmp = smbios_write_funcs[i](&addr, handle++);
+ int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++);
max_struct_size = max(max_struct_size, tmp);
len += tmp;
}
#
# Generated files
#
+bin2c
docproc
--- /dev/null
+config BUILD_BIN2C
+ bool
# SPDX-License-Identifier: GPL-2.0
#
+hostprogs-$(CONFIG_BUILD_BIN2C) += bin2c
+
+always := $(hostprogs-y)
+
# The following hostprogs-y programs are only build on demand
hostprogs-y += docproc
SPL_BIN := u-boot-spl
endif
+ifdef CONFIG_SPL_BUILD
+SPL_ := SPL_
+else
+SPL_ :=
+endif
+
include $(srctree)/config.mk
include $(srctree)/arch/$(ARCH)/Makefile
ALL-y += boot.bin
endif
+ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
+
ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
cmd_copy = cp $< $@
ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy)
-$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \
+$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
+ $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \
$(obj)/$(SPL_BIN).dtb FORCE
$(call if_changed,cat)
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
-OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary
+OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \
+ $(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec)
$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE
$(call if_changed,objcopy)
+OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j .start16 -j .resetvec
+$(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
ifneq ($(CONFIG_SPL_TEXT_BASE),)
LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
--- /dev/null
+/*
+ * Unloved program to convert a binary on stdin to a C include on stdout
+ *
+ * Jan 1999 Matt Mackall <mpm@selenic.com>
+ *
+ * This software may be used and distributed according to the terms
+ * of the GNU General Public License, incorporated herein by reference.
+ */
+
+#include <stdio.h>
+
+int main(int argc, char *argv[])
+{
+ int ch, total = 0;
+
+ if (argc > 1)
+ printf("const char %s[] %s=\n",
+ argv[1], argc > 2 ? argv[2] : "");
+
+ do {
+ printf("\t\"");
+ while ((ch = getchar()) != EOF) {
+ total++;
+ printf("\\x%02x", ch);
+ if (total % 16 == 0)
+ break;
+ }
+ printf("\"\n");
+ } while (ch != EOF);
+
+ if (argc > 1)
+ printf("\t;\n\n#include <linux/types.h>\n\nconst size_t %s_size = %d;\n",
+ argv[1], total);
+
+ return 0;
+}
-e 's/^menuconfig \([A-Za-z0-9_]*\).*$/CONFIG_\1/p' |sort |uniq > ${ok}
comm -23 ${suspects} ${ok} >${new_adhoc}
if [ -s ${new_adhoc} ]; then
- echo "Error: You must add new CONFIG options using Kconfig"
- echo "The following new ad-hoc CONFIG options were detected:"
- cat ${new_adhoc}
- echo
- echo "Please add these via Kconfig instead. Find a suitable Kconfig"
- echo "file and add a 'config' or 'menuconfig' option."
+ echo >&2 "Error: You must add new CONFIG options using Kconfig"
+ echo >&2 "The following new ad-hoc CONFIG options were detected:"
+ cat >&2 ${new_adhoc}
+ echo >&2
+ echo >&2 "Please add these via Kconfig instead. Find a suitable Kconfig"
+ echo >&2 "file and add a 'config' or 'menuconfig' option."
# Don't delete the temporary files in case they are useful
exit 1
else
use strict;
use POSIX;
+use File::Basename;
+use Cwd 'abs_path';
my $P = $0;
$P =~ s@.*/@@g;
+my $D = dirname(abs_path($P));
my $V = '0.32';
my $max_line_length = 80;
my $ignore_perl_version = 0;
my $minimum_perl_version = 5.10.0;
+my $spelling_file = "$D/spelling.txt";
+my $codespell = 0;
+my $codespellfile = "/usr/share/codespell/dictionary.txt";
sub help {
my ($exitcode) = @_;
file. It's your fault if there's no backup or git
--ignore-perl-version override checking of perl version. expect
runtime errors.
+ --codespell Use the codespell dictionary for spelling/typos
+ (default:/usr/local/share/codespell/dictionary.txt)
+ --codespellfile Use this codespell dictionary
-h, --help, --version display this help and exit
When FILE is - read standard input.
'ignore-perl-version!' => \$ignore_perl_version,
'debug=s' => \%debug,
'test-only=s' => \$tst_only,
+ 'codespell!' => \$codespell,
+ 'codespellfile=s' => \$codespellfile,
'h|help' => \$help,
'version' => \$help
) or help(1);
)};
# memory.h: ARM has a custom one
+# Load common spelling mistakes and build regular expression list.
+my $misspellings;
+my %spelling_fix;
+
+if (open(my $spelling, '<', $spelling_file)) {
+ while (<$spelling>) {
+ my $line = $_;
+
+ $line =~ s/\s*\n?$//g;
+ $line =~ s/^\s*//g;
+
+ next if ($line =~ m/^\s*#/);
+ next if ($line =~ m/^\s*$/);
+
+ my ($suspect, $fix) = split(/\|\|/, $line);
+
+ $spelling_fix{$suspect} = $fix;
+ }
+ close($spelling);
+} else {
+ warn "No typos will be found - file '$spelling_file': $!\n";
+}
+
+if ($codespell) {
+ if (open(my $spelling, '<', $codespellfile)) {
+ while (<$spelling>) {
+ my $line = $_;
+
+ $line =~ s/\s*\n?$//g;
+ $line =~ s/^\s*//g;
+
+ next if ($line =~ m/^\s*#/);
+ next if ($line =~ m/^\s*$/);
+ next if ($line =~ m/, disabled/i);
+
+ $line =~ s/,.*$//;
+
+ my ($suspect, $fix) = split(/->/, $line);
+
+ $spelling_fix{$suspect} = $fix;
+ }
+ close($spelling);
+ } else {
+ warn "No codespell typos will be found - file '$codespellfile': $!\n";
+ }
+}
+
+$misspellings = join("|", sort keys %spelling_fix) if keys %spelling_fix;
+
+
sub build_types {
my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)";
my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)";
my @lines = ();
my @fixed = ();
my $vname;
+my $fixlinenr = -1;
+
for my $filename (@ARGV) {
my $FILE;
if ($file) {
"8-bit UTF-8 used in possible commit log\n" . $herecurr);
}
+# Check for various typo / spelling mistakes
+ if (defined($misspellings) &&
+ ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) {
+ while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\b|$|[^a-z@])/gi) {
+ my $typo = $1;
+ my $typo_fix = $spelling_fix{lc($typo)};
+ $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/);
+ $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/);
+ my $msg_type = \&WARN;
+ $msg_type = \&CHK if ($file);
+ if (&{$msg_type}("TYPO_SPELLING",
+ "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) &&
+ $fix) {
+ $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/;
+ }
+ }
+ }
+
# ignore non-hunk lines and lines being removed
next if (!$hunk_line || $line =~ /^-/);
CONFIG_APER_0_BASE
CONFIG_APER_1_BASE
CONFIG_APER_SIZE
-CONFIG_API
CONFIG_APUS_FAST_EXCEPT
CONFIG_AP_SH4A_4A
CONFIG_ARCH_ADPAG101P
*/
ut_asserteq(0, uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus));
ut_assertok(spi_cs_info(bus, cs, &info));
- of_offset = info.dev->of_offset;
+ of_offset = dev_of_offset(info.dev);
device_remove(info.dev);
device_unbind(info.dev);
{
struct dm_test_pdata *pdata = dev_get_platdata(dev);
- pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"ping-add", -1);
- pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+ pdata->base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
"ping-expect");
return 0;
* want to test the code that sets that up
* (testfdt_drv_probe()).
*/
- base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+ base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
"ping-expect");
debug("dev=%d, base=%d: %s\n", i, base,
- fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+ fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL));
ut_assert(!dm_check_operations(uts, dev, base,
dev_get_priv(dev)));
hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params
-hostprogs-$(CONFIG_CMD_LICENSE) += bin2header
hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo
hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo
HOSTCFLAGS_bmp_logo.o := -pedantic
endif # !LOGO_BMP
-# Generated gziped GPL-2.0 license text
-LICENSE_H = $(objtree)/include/license.h
-LICENSE-$(CONFIG_CMD_LICENSE) += $(LICENSE_H)
-
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
-D__KERNEL_STRICT_NAMES \
-D_GNU_SOURCE
-__build: $(LOGO-y) $(LICENSE-y)
+__build: $(LOGO-y)
$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@
$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP)
$(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@
-$(LICENSE_H): $(obj)/bin2header $(srctree)/Licenses/gpl-2.0.txt
- cat $(srctree)/Licenses/gpl-2.0.txt | gzip -9 -c | \
- $(obj)/bin2header license_gzip > $(LICENSE_H)
-
# Let clean descend into subdirs
subdir- += env
+++ /dev/null
-/* bin2header.c - program to convert binary file into a C structure
- * definition to be included in a header file.
- *
- * (C) Copyright 2008 by Harald Welte <laforge@openmoko.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <unistd.h>
-
-int main(int argc, char **argv)
-{
- if (argc < 2) {
- fprintf(stderr, "%s needs one argument: the structure name\n",
- argv[0]);
- exit(1);
- }
-
- printf("/* bin2header output - automatically generated */\n");
- printf("unsigned char %s[] = {\n", argv[1]);
-
- while (1) {
- int i, nread;
- unsigned char buf[10];
- nread = read(0, buf, sizeof(buf));
- if (nread <= 0)
- break;
-
- printf("\t");
- for (i = 0; i < nread - 1; i++)
- printf("0x%02x, ", buf[i]);
-
- printf("0x%02x,\n", buf[nread-1]);
- }
-
- printf("};\n");
-
- exit(0);
-}
process.
"""
def __init__(self, image, etype, node):
- Entry_blob.__init__(self, image, etype, node)
+ Entry_u_boot_with_ucode_ptr.__init__(self, image, etype, node)
self.elf_fname = 'spl/u-boot-spl'
def GetDefaultFilename(self):
self.data = ''
return True
+ # Handle microcode in SPL image as well
+ ucode_dest_entry = self.image.FindEntryType('u-boot-spl-with-ucode-ptr')
+ if ucode_dest_entry and not ucode_dest_entry.target_pos:
+ self.data = ''
+ return True
+
# Get the microcode from the device tree entry
fdt_entry = self.image.FindEntryType('u-boot-dtb-with-ucode')
if not fdt_entry or not fdt_entry.ucode_data:
with 'ball'.
It is convenient to use the -n option to see what will be built based on
-the subset given.
+the subset given. Use -v as well to get an actual list of boards.
Buildman does not store intermediate object files. It optionally copies
the binary output into a directory when a build is successful. Size
exclude: List of boards to exclude, regardless of 'args'
Returns:
- Dictionary which holds the number of boards which were selected
+ Dictionary which holds the list of boards which were selected
due to each argument, arranged by argument.
"""
result = {}
terms = self._BuildTerms(args)
- result['all'] = 0
+ result['all'] = []
for term in terms:
- result[str(term)] = 0
+ result[str(term)] = []
exclude_list = []
for expr in exclude:
if build_it:
board.build_it = True
if matching_term:
- result[matching_term] += 1
- result['all'] += 1
+ result[matching_term].append(board.target)
+ result['all'].append(board.target)
return result
Args:
series: Series object
why_selected: Dictionary where each key is a buildman argument
- provided by the user, and the value is the boards brought
- in by that argument. For example, 'arm' might bring in
- 400 boards, so in this case the key would be 'arm' and
+ provided by the user, and the value is the list of boards
+ brought in by that argument. For example, 'arm' might bring
+ in 400 boards, so in this case the key would be 'arm' and
the value would be a list of board names.
boards_selected: Dict of selected boards, key is target name,
value is Board object
print
for arg in why_selected:
if arg != 'all':
- print arg, ': %d boards' % why_selected[arg]
+ print arg, ': %d boards' % len(why_selected[arg])
+ if options.verbose:
+ print ' %s' % ' '.join(why_selected[arg])
print ('Total boards to build for each commit: %d\n' %
- why_selected['all'])
+ len(why_selected['all']))
def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
clean_dir=False):
options.git_dir, count, series=None, allow_overwrite=True)
else:
series = None
- options.verbose = True
- if not options.summary:
- options.show_errors = True
+ if not options.dry_run:
+ options.verbose = True
+ if not options.summary:
+ options.show_errors = True
# By default we have one thread per CPU. But if there are not enough jobs
# we can have fewer threads and use a high '-j' value for make.
str = name.replace('@', '_at_')
str = str.replace('-', '_')
str = str.replace(',', '_')
+ str = str.replace('.', '_')
str = str.replace('/', '__')
return str
msg_type = col.Color(col.RED, msg_type)
elif msg_type == 'check':
msg_type = col.Color(col.MAGENTA, msg_type)
- return '%s: %s,%d: %s' % (msg_type, fname, line, msg)
+ return '%s:%d: %s: %s\n' % (fname, line, msg_type, msg)
def CheckPatches(verbose, args):
'''Run the checkpatch.pl script on each patch'''
result.checks):
print("Internal error: some problems lost")
for item in result.problems:
- print(GetWarningMsg(col, item.get('type', '<unknown>'),
+ sys.stderr.write(
+ GetWarningMsg(col, item.get('type', '<unknown>'),
item.get('file', '<unknown>'),
item.get('line', 0), item.get('msg', 'message')))
print
if cover_fname:
cover_cc = gitutil.BuildEmailList(self.get('cover_cc', ''))
- print(cover_fname, ', '.join(set(cover_cc + all_ccs)), file=fd)
+ cc_list = ', '.join([x.decode('utf-8') for x in set(cover_cc + all_ccs)])
+ print(cover_fname, cc_list.encode('utf-8'), file=fd)
fd.close()
return fname
projects / u-boot / commitdiff