BUILDMAN="freescale -x powerpc,m68k,aarch64"
- env:
- JOB="Freescale AArch64"
- BUILDMAN="freescale -x powerpc,m68k,armv7,arm9,arm11"
+ BUILDMAN="freescale&aarch64"
- env:
- - JOB="i.MX (non-Freescale)"
- BUILDMAN="mx -x freescale"
+ - JOB="i.MX6 (non-Freescale)"
+ BUILDMAN="mx6 -x freescale"
+ - env:
+ - JOB="i.MX (non-Freescale, non-i.MX6)"
+ BUILDMAN="mx -x freescale,mx6"
- env:
- BUILDMAN="samsung"
- env:
bool "Support bcmnsp"
select CPU_V7
+config TARGET_BCMNS2
+ bool "Support Broadcom Northstar2"
+ select ARM64
+ help
+ Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
+ ARMv8 Cortex-A57 processors targeting a broad range of networking
+ applications
+
config ARCH_EXYNOS
bool "Samsung EXYNOS"
select DM
config AM43XX
bool "AM43XX SoC"
select ARCH_OMAP2
+ imply SPL_DM
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_OF_CONTROL
+ imply SPL_OF_TRANSLATE
+ imply SPL_SEPARATE_BSS
+ imply SPL_SYS_MALLOC_SIMPLE
imply SYS_THUMB_BUILD
help
Support for AM43xx SOC from Texas Instruments.
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
source "board/broadcom/bcmnsp/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "dra7.dtsi"
+ */
+
+/{
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+ u-boot,dm-pre-reloc;
+};
+
+&mac {
+ u-boot,dm-pre-reloc;
+};
+
+&davinci_mdio {
+ u-boot,dm-pre-reloc;
+};
+
+&cpsw_emac0 {
+ u-boot,dm-pre-reloc;
+};
+
+&phy_sel {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "dra7.dtsi"
+ */
+
+/{
+ ocp {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart3 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc2 {
+ u-boot,dm-pre-reloc;
+};
+
+&l4_cfg {
+ u-boot,dm-pre-reloc;
+};
+
+&scm {
+ u-boot,dm-pre-reloc;
+};
+
+&scm_conf {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+
+ m25p80@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
#define OMAP54XX_GPIO7_BASE 0x48051000
#define OMAP54XX_GPIO8_BASE 0x48053000
+
+/* Get the GPIO index from the given bank number and bank gpio */
+#define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio))
+
#endif /* _GPIO_OMAP5_H */
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
-#define OMAP_SRAM_SCRATCH_SPACE_END (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
+#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#endif
+#define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
/* Boot parameters */
#define DEVICE_DATA_OFFSET 0x18
config TARGET_K2G_EVM
bool "TI Keystone 2 Galileo EVM"
+ select BOARD_LATE_INIT
+ select TI_I2C_BOARD_DETECT
endchoice
bool "Support am43xx_evm"
select BOARD_LATE_INIT
select TI_I2C_BOARD_DETECT
+ imply DM_ETH
+ imply DM_I2C
+ imply DM_SPI
+ imply DM_SPI_FLASH
+ imply SPI_FLASH_BAR
imply SPL_ENV_SUPPORT
imply SPL_EXT_SUPPORT
imply SPL_FAT_SUPPORT
"2.0",
"2.1"};
+static char *cpu_revs_am43xx[] = {
+ "1.0",
+ "1.1",
+ "1.2"};
static char *dev_types[] = {
"TST",
int print_cpuinfo(void)
{
char *cpu_s, *sec_s, *rev_s;
+ char **cpu_rev_arr = cpu_revs;
switch (get_cpu_type()) {
case AM335X:
break;
case AM437X:
cpu_s = "AM437X";
+ cpu_rev_arr = cpu_revs_am43xx;
break;
default:
cpu_s = "Unknown CPU type";
}
if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
- rev_s = cpu_revs[get_cpu_rev()];
+ rev_s = cpu_rev_arr[get_cpu_rev()];
else
rev_s = "?";
*(.__end)
}
+ _image_binary_end = .;
+
.bss :
{
. = ALIGN(4);
--- /dev/null
+BCM958712K BOARD
+M: Jon Mason <jon.mason@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmns2/
+F: include/configs/bcm_northstar2.h
+F: configs/bcm958712k_defconfig
--- /dev/null
+if TARGET_BCMNS2
+
+config SYS_BOARD
+ default "bcmns2"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "ns2"
+
+config SYS_CONFIG_NAME
+ default "bcm_northstar2"
+
+endif
--- /dev/null
+#
+# Copyright 2016 Broadcom Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := northstar2.o
--- /dev/null
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region ns2_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0xff80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
U-Boot > tftp u-boot.ais
U-Boot > sf write c0700000 0 $filesize
+Flashing the images to NAND
+===========================
+The AIS image can be written to NAND using the u-boot "nand" commands.
+
+Example:
+
+OMAPL138_LCDK requires the AIS image to be written to the second block of
+the NAND flash.
+
+From the "nand info" command we see that the second block would start at
+offset 0x20000:
+
+ U-Boot > nand info
+ sector size 128 KiB (0x20000)
+ Page size 2048 b
+
+From the tftp command we see that we need to copy 0x74908 bytes from
+memory address 0xc0700000 (0x75000 if we align a page of 2048):
+
+ U-Boot > tftp u-boot.ais
+ Load address: 0xc0700000
+ Bytes transferred = 477448 (74908 hex)
+
+The commands to write the image from memory to NAND would be:
+
+ U-Boot > nand erase 0x20000 0x75000
+ U-Boot > nand write 0xc0700000 0x20000 0x75000
+
+Alternatively, MTD partitions may be defined. Using "mtdparts" to
+conveniently have a bootloader partition starting at the second block
+(offset 0x20000):
+
+ setenv mtdids nand0=davinci_nand.0
+ setenv mtdparts mtdparts=davinci_nand.0:128k(bootenv),2m(bootloader)
+
+In this case the commands would be simplified to:
+
+ U-Boot > tftp u-boot.ais
+ U-Boot > nand erase.part bootloader
+ U-Boot > nand write 0xc0700000 bootloader
+
Flashing the images to MMC
==========================
If the boot pins are set to boot from mmc, the RBL will try to load the
DECLARE_GLOBAL_DATA_PTR;
+#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
+/* Touch screen controller to identify the LCD */
+#define OSD_TS_FT_BUS_ADDRESS 0
+#define OSD_TS_FT_CHIP_ADDRESS 0x38
+#define OSD_TS_FT_REG_ID 0xA3
+/*
+ * Touchscreen IDs for various OSD panels
+ * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
+ */
+/* Used on newer osd101t2587 Panels */
+#define OSD_TS_FT_ID_5x46 0x54
+/* Used on older osd101t2045 Panels */
+#define OSD_TS_FT_ID_5606 0x08
+
#define SYSINFO_BOARD_NAME_MAX_LEN 45
#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
*ctrl = &dra7xx_ctrl;
}
+bool am571x_idk_needs_lcd(void)
+{
+ bool needs_lcd;
+
+ gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
+ if (gpio_get_value(GPIO_ETH_LCD))
+ needs_lcd = false;
+ else
+ needs_lcd = true;
+
+ gpio_free(GPIO_ETH_LCD);
+
+ return needs_lcd;
+}
+
int board_init(void)
{
gpmc_init();
return 0;
}
+void am57x_idk_lcd_detect(void)
+{
+ int r = -ENODEV;
+ char *idk_lcd = "no";
+ uint8_t buf = 0;
+
+ /* Only valid for IDKs */
+ if (board_is_x15() || board_is_am572x_evm())
+ return;
+
+ /* Only AM571x IDK has gpio control detect.. so check that */
+ if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
+ goto out;
+
+ r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
+ if (r) {
+ printf("%s: Failed to set bus address to %d: %d\n",
+ __func__, OSD_TS_FT_BUS_ADDRESS, r);
+ goto out;
+ }
+ r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
+ if (r) {
+ /* AM572x IDK has no explicit settings for optional LCD kit */
+ if (board_is_am571x_idk()) {
+ printf("%s: Touch screen detect failed: %d!\n",
+ __func__, r);
+ }
+ goto out;
+ }
+
+ /* Read FT ID */
+ r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
+ if (r) {
+ printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
+ __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
+ OSD_TS_FT_REG_ID, r);
+ goto out;
+ }
+
+ switch (buf) {
+ case OSD_TS_FT_ID_5606:
+ idk_lcd = "osd101t2045";
+ break;
+ case OSD_TS_FT_ID_5x46:
+ idk_lcd = "osd101t2587";
+ break;
+ default:
+ printf("%s: Unidentifed Touch screen ID 0x%02x\n",
+ __func__, buf);
+ /* we will let default be "no lcd" */
+ }
+out:
+ setenv("idk_lcd", idk_lcd);
+ return;
+}
+
int board_late_init(void)
{
setup_board_eeprom_env();
omap_die_id_serial();
+ am57x_idk_lcd_detect();
+
+#if !defined(CONFIG_SPL_BUILD)
+ board_ti_set_ethaddr(2);
+#endif
+
return 0;
}
do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
}
+ if (board_is_am571x_idk()) {
+ if (am571x_idk_needs_lcd()) {
+ pconf = core_padconf_array_vout_am571x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
+ } else {
+ pconf = core_padconf_array_icss1eth_am571x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
+ }
+ do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+ }
+
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
err:
{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */
- {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mi1_col */
- {VIN2A_D4, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.pr1_mii1_txd1 */
- {VIN2A_D5, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_mii1_txd0 */
- {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
- {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii1_txen */
- {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii1_txd3 */
- {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii1_txd2 */
{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
{VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */
{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
{VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
{GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
{GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
{GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
- {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)}, /* xref_clk1.pr2_mii1_crs */
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
{XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */
{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */
{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */
{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */
- {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
- {MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */
- {MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */
- {MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
- {MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */
- {MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */
- {MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
- {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr14.pr2_mii0_rxdv */
- {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
- {MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
- {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
{MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */
{MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */
{MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */
{MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */
- {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
- {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR2, (M11 | PIN_INPUT)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT)}, /* mcasp2_axr3.pr2_mii0_rxlink */
{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */
{MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */
{MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */
{MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */
- {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
- {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
- {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
- {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT)}, /* mcasp3_axr1.pr2_mii1_rxlink */
{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */
{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */
{MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
{MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */
- {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
- {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
- {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
- {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
- {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
- {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
- {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_OUTPUT)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_OUTPUT)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_OUTPUT)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_OUTPUT)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_OUTPUT)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat2.pr2_mii_mr1_clk */
{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
- {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
- {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
- {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
- {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {MMC3_DAT4, (M11 | PIN_INPUT)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT)}, /* mmc3_dat7.pr2_mii1_rxd0 */
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
{RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */
};
+const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
+ /* PR1 MII0 */
+ {VOUT1_D8, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.pr1_mii_mt0_clk */
+ {VOUT1_D9, (M13 | PIN_OUTPUT)}, /* vout1_d9.pr1_mii0_txd3 */
+ {VOUT1_D10, (M13 | PIN_OUTPUT)}, /* vout1_d10.pr1_mii0_txd2 */
+ {VOUT1_D11, (M13 | PIN_OUTPUT)}, /* vout1_d11.pr1_mii0_txen */
+ {VOUT1_D12, (M13 | PIN_OUTPUT)}, /* vout1_d12.pr1_mii0_txd1 */
+ {VOUT1_D13, (M13 | PIN_OUTPUT)}, /* vout1_d13.pr1_mii0_txd0 */
+ {VOUT1_D14, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.pr1_mii_mr0_clk */
+ {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */
+ {VOUT1_D16, (M12 | PIN_INPUT)}, /* vout1_d16.pr1_mii0_rxd3 */
+ {VOUT1_D17, (M12 | PIN_INPUT)}, /* vout1_d17.pr1_mii0_rxd2 */
+ {VOUT1_D18, (M12 | PIN_INPUT)}, /* vout1_d18.pr1_mii0_rxd1 */
+ {VOUT1_D19, (M12 | PIN_INPUT)}, /* vout1_d19.pr1_mii0_rxd0 */
+ {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */
+ {VOUT1_D21, (M12 | PIN_INPUT)}, /* vout1_d21.pr1_mii0_rxlink */
+ {VOUT1_D22, (M12 | PIN_INPUT)}, /* vout1_d22.pr1_mii0_col */
+ {VOUT1_D23, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d23.pr1_mii0_crs */
+
+ /* PR1 MII1 */
+ {VIN2A_D3, (M12 | PIN_INPUT)}, /* vin2a_d3.pr1_mi1_col */
+ {VIN2A_D4, (M13 | PIN_OUTPUT)}, /* vin2a_d4.pr1_mii1_txd1 */
+ {VIN2A_D5, (M13 | PIN_OUTPUT)}, /* vin2a_d5.pr1_mii1_txd0 */
+ {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
+ {VIN2A_D7, (M11 | PIN_OUTPUT)}, /* vin2a_d7.pr1_mii1_txen */
+ {VIN2A_D8, (M11 | PIN_OUTPUT)}, /* vin2a_d8.pr1_mii1_txd3 */
+ {VIN2A_D9, (M11 | PIN_OUTPUT)}, /* vin2a_d9.pr1_mii1_txd2 */
+ {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */
+ {VOUT1_D0, (M12 | PIN_INPUT)}, /* vout1_d0.pr1_mii1_rxlink */
+ {VOUT1_D1, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d1.pr1_mii1_crs */
+ {VOUT1_D2, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.pr1_mii_mr1_clk */
+ {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */
+ {VOUT1_D4, (M12 | PIN_INPUT)}, /* vout1_d4.pr1_mii1_rxd3 */
+ {VOUT1_D5, (M12 | PIN_INPUT)}, /* vout1_d5.pr1_mii1_rxd2 */
+ {VOUT1_D6, (M12 | PIN_INPUT)}, /* vout1_d6.pr1_mii1_rxd1 */
+ {VOUT1_D7, (M12 | PIN_INPUT)}, /* vout1_d7.pr1_mii1_rxd0 */
+};
+
+const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
+ {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
+ {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
+};
+
const struct pad_conf_entry early_padconf[] = {
{UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
help
Support for detection board information on Texas Instrument's
Evaluation Boards which have I2C based EEPROM detection
+
+config EEPROM_BUS_ADDRESS
+ int "Board EEPROM's I2C bus address"
+ range 0 8
+ default 0
+
+config EEPROM_CHIP_ADDRESS
+ hex "Board EEPROM's I2C chip address"
+ range 0 0xff
+ default 0x50
else
setenv("board_serial", unknown);
}
+
+static u64 mac_to_u64(u8 mac[6])
+{
+ int i;
+ u64 addr = 0;
+
+ for (i = 0; i < 6; i++) {
+ addr <<= 8;
+ addr |= mac[i];
+ }
+
+ return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+ mac[5] = addr;
+ mac[4] = addr >> 8;
+ mac[3] = addr >> 16;
+ mac[2] = addr >> 24;
+ mac[1] = addr >> 32;
+ mac[0] = addr >> 40;
+}
+
+void board_ti_set_ethaddr(int index)
+{
+ uint8_t mac_addr[6];
+ int i;
+ u64 mac1, mac2;
+ u8 mac_addr1[6], mac_addr2[6];
+ int num_macs;
+ /*
+ * Export any Ethernet MAC addresses from EEPROM.
+ * The 2 MAC addresses in EEPROM define the address range.
+ */
+ board_ti_get_eth_mac_addr(0, mac_addr1);
+ board_ti_get_eth_mac_addr(1, mac_addr2);
+
+ if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+ mac1 = mac_to_u64(mac_addr1);
+ mac2 = mac_to_u64(mac_addr2);
+
+ /* must contain an address range */
+ num_macs = mac2 - mac1 + 1;
+ if (num_macs <= 0)
+ return;
+
+ if (num_macs > 50) {
+ printf("%s: Too many MAC addresses: %d. Limiting to 50\n",
+ __func__, num_macs);
+ num_macs = 50;
+ }
+
+ for (i = 0; i < num_macs; i++) {
+ u64_to_mac(mac1 + i, mac_addr);
+ if (is_valid_ethaddr(mac_addr)) {
+ eth_setenv_enetaddr_by_index("eth", i + index,
+ mac_addr);
+ }
+ }
+ }
+}
};
#define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
- OMAP_SRAM_SCRATCH_BOARD_EEPROM_START)
+ TI_SRAM_SCRATCH_BOARD_EEPROM_START)
/**
* ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
*/
void set_board_info_env(char *name);
+/**
+ * board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first eth<index>addr environment variable to set
+ *
+ * EEPROM should be already read before calling this function.
+ * The EEPROM contains 2 MAC addresses which define the MAC address
+ * range (i.e. first and last MAC address).
+ * This function sets the ethaddr environment variable for all
+ * the available MAC addresses starting from eth<index>addr.
+ */
+void board_ti_set_ethaddr(int index);
+
#endif /* __BOARD_DETECT_H */
default "k2g_evm"
endif
+
+source "board/ti/common/Kconfig"
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
#include "mux-k2g.h"
+#include "../common/board_detect.h"
#define SYS_CLK 24000000
}
#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+ int rc;
+
+ rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (rc)
+ printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+ board_ti_set_ethaddr(1);
+#endif
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
int spl_init(void)
{
int ret;
+ bool setup_malloc = !(IS_ENABLED(CONFIG_SPL_STACK_R) &&
+ IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIMPLE));
if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) {
- ret = spl_common_init(
- !IS_ENABLED(CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN));
+ ret = spl_common_init(setup_malloc);
if (ret)
return ret;
}
CONFIG_ARM=y
CONFIG_AM43XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_ARM=y
CONFIG_AM43XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_AM43XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_AM57XX_EVM=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
+CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am572x-idk am571x-idk"
CONFIG_DM=y
+CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_FASTBOOT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS2=y
+CONFIG_IDENT_STRING=" Broadcom Northstar 2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=5
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="u-boot> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
+CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_FASTBOOT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm"
CONFIG_DM=y
+CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_SPL_OF_LIBFDT=y
common when EFI is the bootloader. Note 2TB partition limit;
see disk/part_efi.c
+config EFI_PARTITION_ENTRIES_OFF
+ int "Offset (in bytes) of the EFI partition entries"
+ depends on EFI_PARTITION
+ default 0
+ help
+ Specify an earliest location (in bytes) where the partition
+ entries may be located. This is meant to allow "punching a
+ hole into a device" to create a gap for an SPL, its payload
+ and the U-Boot environment.
+
+ If unsure, leave at 0 (which will locate the partition
+ entries at the first possible LBA following the GPT header).
+
config SPL_EFI_PARTITION
bool "Enable EFI GPT partition table for SPL"
depends on SPL && PARTITIONS
#include <asm/unaligned.h>
#include <common.h>
#include <command.h>
+#include <fdtdec.h>
#include <ide.h>
#include <inttypes.h>
#include <malloc.h>
#include <memalign.h>
#include <part_efi.h>
+#include <linux/compiler.h>
#include <linux/ctype.h>
DECLARE_GLOBAL_DATA_PTR;
if (blk_dwrite(dev_desc, 1, 1, gpt_h) != 1)
goto err;
- if (blk_dwrite(dev_desc, 2, pte_blk_cnt, gpt_e)
- != pte_blk_cnt)
+ if (blk_dwrite(dev_desc, le64_to_cpu(gpt_h->partition_entry_lba),
+ pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
prepare_backup_gpt_header(gpt_h);
return 0;
}
+static uint32_t partition_entries_offset(struct blk_desc *dev_desc)
+{
+ uint32_t offset_blks = 2;
+ int __maybe_unused config_offset;
+
+#if defined(CONFIG_EFI_PARTITION_ENTRIES_OFF)
+ /*
+ * Some architectures require their SPL loader at a fixed
+ * address within the first 16KB of the disk. To avoid an
+ * overlap with the partition entries of the EFI partition
+ * table, the first safe offset (in bytes, from the start of
+ * the disk) for the entries can be set in
+ * CONFIG_EFI_PARTITION_ENTRIES_OFF.
+ */
+ offset_blks =
+ PAD_TO_BLOCKSIZE(CONFIG_EFI_PARTITION_ENTRIES_OFF, dev_desc);
+#endif
+
+#if defined(CONFIG_OF_CONTROL)
+ /*
+ * Allow the offset of the first partition entires (in bytes
+ * from the start of the device) to be specified as a property
+ * of the device tree '/config' node.
+ */
+ config_offset = fdtdec_get_config_int(gd->fdt_blob,
+ "u-boot,efi-partition-entries-offset",
+ -EINVAL);
+ if (config_offset != -EINVAL)
+ offset_blks = PAD_TO_BLOCKSIZE(config_offset, dev_desc);
+#endif
+
+ debug("efi: partition entries offset (in blocks): %d\n", offset_blks);
+
+ /*
+ * The earliest LBA this can be at is LBA#2 (i.e. right behind
+ * the (protective) MBR and the GPT header.
+ */
+ if (offset_blks < 2)
+ offset_blks = 2;
+
+ return offset_blks;
+}
+
int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
char *str_guid, int parts_count)
{
gpt_h->header_size = cpu_to_le32(sizeof(gpt_header));
gpt_h->my_lba = cpu_to_le64(1);
gpt_h->alternate_lba = cpu_to_le64(dev_desc->lba - 1);
- gpt_h->first_usable_lba = cpu_to_le64(34);
gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
- gpt_h->partition_entry_lba = cpu_to_le64(2);
+ gpt_h->partition_entry_lba =
+ cpu_to_le64(partition_entries_offset(dev_desc));
+ gpt_h->first_usable_lba =
+ cpu_to_le64(le64_to_cpu(gpt_h->partition_entry_lba) + 32);
gpt_h->num_partition_entries = cpu_to_le32(GPT_ENTRY_NUMBERS);
gpt_h->sizeof_partition_entry = cpu_to_le32(sizeof(gpt_entry));
gpt_h->header_crc32 = 0;
$ make DEVICE_TREE=<dts-file-name>
-Configuration Options
----------------------
-
-A number of run-time configuration options are provided in the /config node
-of the control device tree. You can access these using fdtdec_get_config_int(),
-fdtdec_get_config_bool() and fdtdec_get_config_string().
-
-Available options are:
-
-silent-console
- If present and non-zero, the console is silenced by default on boot.
-
-no-keyboard
- Tells U-Boot not to expect an attached keyboard with a VGA console
-
-
Limitations
-----------
--- /dev/null
+The /config node (Configuration Options)
+----------------------------------------
+
+A number of run-time configuration options are provided in the /config node
+of the control device tree. You can access these using fdtdec_get_config_int(),
+fdtdec_get_config_bool() and fdtdec_get_config_string().
+
+Available options are:
+
+silent-console
+ If present and non-zero, the console is silenced by default on boot.
+
+no-keyboard
+ Tells U-Boot not to expect an attached keyboard with a VGA console
+
+u-boot,efi-partition-entries-offset
+ If present, this provides an offset (in bytes, from the start of a
+ device) that should be skipped over before the partition entries.
+ This is used by the EFI/GPT partition implementation when a device
+ is formatted.
+
+ This setting will override any values configured via Kconfig.
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_CLK 48000000
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#endif
/* I2C Configuration */
* DM support in SPL
*/
#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_TIMER
#endif
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* EEPROM */
-#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
-#define CONFIG_EEPROM_BUS_ADDRESS 0
-
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
-#endif
-
/* SPI SPL */
#define CONFIG_TI_EDMA3
#define CONFIG_SPL_SPI_LOAD
--- /dev/null
+/*
+ * Configuration for Broadcom NS2.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCM_NORTHSTAR2_H
+#define __BCM_NORTHSTAR2_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_HOSTNAME northstar2
+
+/* Physical Memory Map */
+#define V2M_BASE 0x80000000
+#define PHYS_SDRAM_1 V2M_BASE
+
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G)
+#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* define text_base for U-boot image */
+#define CONFIG_SYS_TEXT_BASE 0x85000000
+#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00)
+#define CONFIG_SYS_LOAD_ADDR 0x90000000
+#define CONFIG_SYS_MALLOC_LEN SZ_16M
+
+/* Serial Configuration */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 25000000
+#define CONFIG_SYS_NS16550_COM1 0x66100000
+#define CONFIG_SYS_NS16550_COM2 0x66110000
+#define CONFIG_SYS_NS16550_COM3 0x66120000
+#define CONFIG_SYS_NS16550_COM4 0x66130000
+#define CONFIG_CONS_INDEX 4
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_NOWHERE
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE SZ_1K
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* version string, parser, etc */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_SYS_LONGHELP
+
+#endif /* __BCM_NORTHSTAR2_H */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_QSPI_QUAD_SUPPORT
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_SPI
-#undef CONFIG_DM_SPI_FLASH
-#endif
-
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x040000 : QSPI.SPL (256KiB)
#endif
#endif /* NOR support */
-/* EEPROM */
-#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
-#define CONFIG_EEPROM_BUS_ADDRESS 0
-
#endif /* __CONFIG_DRA7XX_EVM_H */
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+/* SRAM scratch space entries */
+#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8
+
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
+
/* UART Configuration */
#define CONFIG_SYS_NS16550_MEM32
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
* Hardware drivers
*/
#define CONFIG_SYS_NS16550_CLK 48000000
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#if !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#endif
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
-#undef CONFIG_DM_ETH
#endif
#endif /* __CONFIG_TI_OMAP5_COMMON_H */
config RSA
bool "Use RSA Library"
- select RSA_FREESCALE_EXP if FSL_CAAM
+ select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP
help
RSA support. This enables the RSA algorithm used for FIT image
config RSA_FREESCALE_EXP
bool "Enable RSA Modular Exponentiation with FSL crypto accelerator"
- depends on DM && RSA && FSL_CAAM
+ depends on DM && RSA && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5
help
Enables driver for RSA modular exponentiation using Freescale cryptographic
accelerator - CAAM.
{
char buf[ARP_HLEN_ASCII + 1];
+ if (eth_getenv_enetaddr(name, (uchar *)buf))
+ return -EEXIST;
+
sprintf(buf, "%pM", enetaddr);
return setenv(name, buf);
# make O=sandbox sandbox_config
# make O=sandbox
# ./test/image/test-fit.py -u sandbox/u-boot
+#
+# Note: The above testing requires the Python development package, typically
+# called python-devel or something similar.
import doctest
from optparse import OptionParser
};
'''
-# This is the U-Boot script that is run for each test. First load the fit,
-# then do the 'bootm' command, then save out memory from the places where
+# This is the U-Boot script that is run for each test. First load the FIT,
+# then run the 'bootm' command, then save out memory from the places where
# we expect 'bootm' to write things. Then quit.
base_script = '''
sb load hostfs 0 %(fit_addr)x %(fit)s
>>> find_matching('first line:10\\nsecond_line:20', 'first line:')
'10'
- >>> find_matching('first line:10\\nsecond_line:20', 'second linex')
+ >>> find_matching('first line:10\\nsecond_line:20', 'second line')
Traceback (most recent call last):
...
ValueError: Test aborted
fail('Ramdisk loaded but should not be', stdout)
# Find out the offset in the FIT where U-Boot has found the FDT
- line = find_matching(stdout, 'Booting using the fdt blob at ')
+ line = find_matching(stdout, 'Booting using the FDT blob at ')
fit_offset = int(line, 16) - params['fit_addr']
fdt_magic = struct.pack('>L', 0xd00dfeed)
data = read_file(fit)
print '\nTests passed'
print 'Caveat: this is only a sanity check - test coverage is poor'
- # Remove the tempoerary directory unless we are asked to keep it
+ # Remove the temporary directory unless we are asked to keep it
if options.keep:
print "Output files are in '%s'" % base_dir
else:
libfdt:
tools/_libfdt.so: $(patsubst %.o,%.c,$(LIBFDT_OBJS)) tools/libfdt_wrap.c
- LDFLAGS="$(HOSTLDFLAGS)" python $(srctree)/lib/libfdt/setup.py \
+ LDFLAGS="$(HOSTLDFLAGS)" CFLAGS= python $(srctree)/lib/libfdt/setup.py \
"$(_hostc_flags)" $^
mv _libfdt.so $@
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