Merge git://git.denx.de/u-boot-sh

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7212fc5afa72c2bfeee8e5918af13b79d7c33edf..c930fa284600aabbe5931afcb7fd73a0aeae454a 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1185,6 +1185,7 @@ config ARCH_ROCKCHIP
        imply TPL_SYSRESET
        imply ADC
        imply SARADC_ROCKCHIP
+       imply SYS_NS16550
 
 config TARGET_THUNDERX_88XX
        bool "Support ThunderX 88xx"

diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
new file mode 100644 (file)
index 0000000..26f5707
--- /dev/null
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+&cru {
+       u-boot,dm-spl;
+};
+
+&pinctrl {
+       u-boot,dm-spl;
+};
+
+&uart2 {
+       status = "okay";
+       u-boot,dm-spl;
+};
+
+&timer3 {
+       compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+       u-boot,dm-spl;
+       clock-frequency = <24000000>;
+};

diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts
index 5f5b5e9a1f09b453ae8ea655b2339b526a527d27..0fc4f54af2d44ce0a398a2699537079fa34887cb 100644 (file)
--- a/arch/arm/dts/rk3188-radxarock.dts
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 #include <dt-bindings/input/input.h>
 #include "rk3188.dtsi"
+#include "rk3188-radxarock-u-boot.dtsi"
 
 / {
        model = "Radxa Rock";
@@ -356,11 +357,6 @@
        status = "okay";
 };
 
-&uart2 {
-       status = "okay";
-       u-boot,dm-spl;
-};
-
 &uart3 {
        status = "okay";
 };

diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index f4d438eb66e4a0c543e6fa3280479dc7b071e356..aeb5b80e144ac8ac906651601ef9df7d465478a1 100644 (file)
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -105,7 +105,6 @@
                compatible = "rockchip,rk3188-cru";
                reg = <0x20000000 0x1000>;
                rockchip,grf = <&grf>;
-               u-boot,dm-spl;
 
                #clock-cells = <1>;
                #reset-cells = <1>;
@@ -124,6 +123,12 @@
                };
        };
 
+       timer3: timer@2000e000 {
+               compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+               reg = <0x2000e000 0x20>;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
        usbphy: phy {
                compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
                rockchip,grf = <&grf>;
@@ -156,7 +161,6 @@
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
-               u-boot,dm-spl;
 
                gpio0: gpio0@2000a000 {
                        compatible = "rockchip,gpio-bank";

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0adaed43677ac686a70d9a6335b1e2631c3d36f8..007cb22a349e15d4b5fb5e5bf5ef4cd78320e678 100644 (file)
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
        imply SPL_SERIAL_SUPPORT
        imply TPL_SERIAL_SUPPORT
        select DEBUG_UART_BOARD_INIT
-       select SYS_NS16550
        help
          The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
          into a big and little cluster with 4 cores each) Cortex-A53 including

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index e1b0519b1f4c44538c8a9b5918a176d2a2650a88..096dbac25b2b0586c193fd770258d85b876deac0 100644 (file)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -40,8 +40,10 @@ endif
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
 
 ifndef CONFIG_ARM64
+ifndef CONFIG_ROCKCHIP_RK3188
 obj-y += rk_timer.o
 endif
+endif
 
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/

diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index 7c6dd576781a0d606e0c862efdbcbbd62945c126..9a404d1d32439c821c62df84c352a099440d1af5 100755 (executable)
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,8 +13,6 @@ import getopt
 
 # pip install pyelftools
 from elftools.elf.elffile import ELFFile
-from elftools.elf.sections import SymbolTableSection
-from elftools.elf.segments import Segment, InterpSegment, NoteSegment
 
 ELF_SEG_P_TYPE='p_type'
 ELF_SEG_P_PADDR='p_paddr'

diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 74771d3a0b04f33a08d2d4c46f20d115c589ec70..3ccc4f120547c89fb764e93f51e9592538a2a65e 100644 (file)
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -131,8 +131,6 @@ void board_init_f(ulong dummy)
                hang();
        }
 
-       rockchip_timer_init();
-
        ret = rockchip_get_clk(&dev);
        if (ret) {
                debug("CLK init failed: %d\n", ret);

diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
index 206abfafcd971249c8c1a511b693ffe0e260ce2f..d3d04465744b9a471a2246f3178e5c44b724ab18 100644 (file)
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -95,7 +95,7 @@ void board_init_f(ulong dummy)
 
        /* Disable the ddr secure region setting to make it non-secure */
        rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
        back_to_bootrom(BROM_BOOT_NEXTSTAGE);
 #endif
 }

diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index d8ab84b8e47e550a6c23858b9072900a33c7bbcf..d1728ef6395ca67d891dc8efdd012de1445f8fa1 100644 (file)
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -71,7 +71,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y

diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 5dabae5434a44e4bfdacbd4f2a419205660922bf..43d93f4637ad5ad74d4f9a7136c142254756cc0a 100644 (file)
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -72,7 +72,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y

diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index c54c00f4841cd97ccc2b940671fe8a3bfbb7f71b..706809ca53fb8d70f8b1e699ba808acbef32c93b 100644 (file)
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -71,7 +71,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y

diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index 5407cbaf22c467c8be02cf076fb6a152b5207f3d..796d0ec92e67110a50af9c8f174980d4b84412ad 100644 (file)
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -34,7 +34,6 @@ CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 549a16673a27543f06a0e3b221833f4084d38425..710b0b4e1a99afc8eab17d3a4eab88a849c9b333 100644 (file)
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -46,7 +46,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0x11030000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_GADGET=y

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index d625fb1c5fa27960805f02340e25ef988d728246..7695277daf350427d1b3b20688ba5a1fbb423ad8 100644 (file)
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index a52e37ac74513c977a8fb415dc9ea877a92deec3..78ae24b56b27fecf4e2d5c14c47ab317e72b6b9a 100644 (file)
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -44,7 +44,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0xFF130000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index b36f232dcb11172959d04eb0d24b27795bd305f3..08c0ab0e2753c450a13e6aeb4d352ab4a7c030db 100644 (file)
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_STACK_R=y
@@ -25,6 +26,8 @@ CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_SPL_OF_PLATDATA=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
@@ -56,7 +59,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index d1f7f777ed032e5bc31a4fc21e71a52ba32d864f..efdd583cf6e5b34786aeea37cc55a27eeb8880b8 100644 (file)
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0f254c0972382b9bbb04d63b140da2646b6ebe1b..b252d2746403e16cbaa1fb072945c50749ff8b00 100644 (file)
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 984c3f4ed6ea3374f510066c4ee05fa21f4b7b64..19c0b110401714f8dbc356de22e2e85bfe4f1829 100644 (file)
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -58,7 +58,6 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index af5b9cc6a4169e87be20b5178fc1e90132d61645..f44537c88f40d7dc4d8ceaa1edf69df09ce6cd6d 100644 (file)
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 66decf0653adb71b808dd7a862590f2d7bcaa506..d78b6d57b6b87a9fc315bff0258db1b35bff1013 100644 (file)
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 8343a4ab4d3785aba1d52243b556519c758b56ef..2670b4b75aef890af8add7d19bdf55ee4a5ee55c 100644 (file)
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 4324a82e7664db477668b9bf8ab9f27cce8f93dc..e6539a7da8d4569209ed574622c0579e1eb94cef 100644 (file)
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -80,10 +80,11 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ISL1208=y
 CONFIG_DEBUG_UART_BASE=0xFF180000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y

diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index a59599ebbccbb55a8491605fcc2409997aadc113..cd9a82197464f7ed87091355e95be54719512b11 100644 (file)
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index c4a236ccf63ebc8fd1793c68edb7e05f04a2c24e..08ca78d03b9bf1c68c30e67d9040de32da0e5028 100644 (file)
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -5,6 +5,9 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x60000000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3188=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_ROCK=y
 CONFIG_SPL_STACK_R_ADDR=0x60080000
@@ -47,7 +50,6 @@ CONFIG_RAM=y
 CONFIG_DEBUG_UART_BASE=0x20064000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_ROCKCHIP_USB2_PHY=y

diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index d5c705ae46258226a58bf7cdc5522ffd6aecb537..fb6bfa57ad7f917008020650cace9dadc371dc5f 100644 (file)
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -66,7 +66,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index bf1de5a56e7d8ac0487d5486cda0d105b99f9b3e..9e4e96a4f274fab47de829e0fc23a80298f86df2 100644 (file)
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y

diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 560222b96c4442afb11fd96518ee4667188db2a0..5e11318042dc21fad837133e641b4bc3e603cf75 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -317,11 +317,19 @@ static struct clk_ops rk3036_clk_ops = {
        .set_rate       = rk3036_clk_set_rate,
 };
 
-static int rk3036_clk_probe(struct udevice *dev)
+static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
 {
        struct rk3036_clk_priv *priv = dev_get_priv(dev);
 
        priv->cru = dev_read_addr_ptr(dev);
+
+       return 0;
+}
+
+static int rk3036_clk_probe(struct udevice *dev)
+{
+       struct rk3036_clk_priv *priv = dev_get_priv(dev);
+
        rkclk_init(priv->cru);
 
        return 0;
@@ -367,6 +375,7 @@ U_BOOT_DRIVER(rockchip_rk3036_cru) = {
        .id             = UCLASS_CLK,
        .of_match       = rk3036_clk_ids,
        .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
+       .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
        .ops            = &rk3036_clk_ops,
        .bind           = rk3036_clk_bind,
        .probe          = rk3036_clk_probe,

diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index 132d50dda3877c368494c4c1d2475dab30dcca42..7b479e79bb4928e2143ce766caa35aaee068432e 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -546,11 +546,19 @@ static struct clk_ops rk3128_clk_ops = {
        .set_rate       = rk3128_clk_set_rate,
 };
 
+static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
+{
+       struct rk3128_clk_priv *priv = dev_get_priv(dev);
+
+       priv->cru = dev_read_addr_ptr(dev);
+
+       return 0;
+}
+
 static int rk3128_clk_probe(struct udevice *dev)
 {
        struct rk3128_clk_priv *priv = dev_get_priv(dev);
 
-       priv->cru = (struct rk3128_cru *)dev_read_addr(dev);
        rkclk_init(priv->cru);
 
        return 0;
@@ -590,6 +598,7 @@ U_BOOT_DRIVER(rockchip_rk3128_cru) = {
        .id             = UCLASS_CLK,
        .of_match       = rk3128_clk_ids,
        .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
+       .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
        .ops            = &rk3128_clk_ops,
        .bind           = rk3128_clk_bind,
        .probe          = rk3128_clk_probe,

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 3a36d04096b03c6e58278a2308eb6c624b4aab8b..78ada2d2db4d126dfa424f5d426796e59319df66 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -893,12 +893,25 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par
        return -ENOENT;
 }
 
+static int rk3288_clk_enable(struct clk *clk)
+{
+       switch (clk->id) {
+       case HCLK_USBHOST0:
+       case HCLK_HSIC:
+               return 0;
+       }
+
+       debug("%s: unsupported clk %ld\n", __func__, clk->id);
+       return -ENOENT;
+}
+
 static struct clk_ops rk3288_clk_ops = {
        .get_rate       = rk3288_clk_get_rate,
        .set_rate       = rk3288_clk_set_rate,
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
        .set_parent     = rk3288_clk_set_parent,
 #endif
+       .enable = rk3288_clk_enable,
 };
 
 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)

diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 958fc78592648223de4636e6951cf63fa0312f4e..42341a856605841900e2c38f66661565d936eadb 100644 (file)
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -209,12 +209,19 @@ static void rkclk_init(struct rv1108_cru *cru)
        printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
 }
 
-static int rv1108_clk_probe(struct udevice *dev)
+static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
 {
        struct rv1108_clk_priv *priv = dev_get_priv(dev);
 
        priv->cru = dev_read_addr_ptr(dev);
 
+       return 0;
+}
+
+static int rv1108_clk_probe(struct udevice *dev)
+{
+       struct rv1108_clk_priv *priv = dev_get_priv(dev);
+
        rkclk_init(priv->cru);
 
        return 0;
@@ -260,6 +267,7 @@ U_BOOT_DRIVER(clk_rv1108) = {
        .id             = UCLASS_CLK,
        .of_match       = rv1108_clk_ids,
        .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
+       .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
        .ops            = &rv1108_clk_ops,
        .bind           = rv1108_clk_bind,
        .probe          = rv1108_clk_probe,

diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 07d14482d68c0fa6daaa996bb2e11d5a0a0ace9e..b847bc40c4ec937a771b6d8f3b778dd15f5cd334 100644 (file)
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -152,6 +152,8 @@ static const struct timer_ops rockchip_timer_ops = {
 };
 
 static const struct udevice_id rockchip_timer_ids[] = {
+       { .compatible = "rockchip,rk3188-timer" },
+       { .compatible = "rockchip,rk3288-timer" },
        { .compatible = "rockchip,rk3368-timer" },
        {}
 };

diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index d6bb9f6fb4af05d91755e77a3dc717dd33856ce1..2b0ac9ec5f43e62c8bb47679063bcd5b72538cf5 100644 (file)
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -10,8 +10,7 @@
 #define ROCKCHIP_DEVICE_SETTINGS \
                "stdin=serial,usbkbd\0" \
                "stdout=serial,vidconsole\0" \
-               "stderr=serial,vidconsole\0" \
-               "preboot=usb start\0"
+               "stderr=serial,vidconsole\0"
 
 #include <configs/rk3288_common.h>
 

diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f39a272e6d211c783183520a66c4f7f7acdb730a..c5ec864b1ed0e935cf6660583930f0adb08d1702 100644 (file)
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 #define CONFIG_SPL_STACK               0x10081fff

diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index bd8019c6a56a7ba715627286d83934c00ff496aa..c593f18fdbeb950a317b7497f44859767a93affc 100644 (file)
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -19,8 +19,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x200440a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 

diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 94f8cda8532009496489c721eea22cc94911440d..e07facd9c30609d7085536a4bf19fdf4e843810c 100644 (file)
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -17,11 +17,6 @@
 #define CONFIG_SYS_MALLOC_LEN          (32 << 20)
 #define CONFIG_SYS_CBSIZE              1024
 
-#define CONFIG_SYS_TIMER_RATE          (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE          0x2000e000 /* TIMER3 */
-#define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
 #define CONFIG_SYS_NS16550_MEM32
 
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM

diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 7f9c7fbfd5e8a3d610df08ccf799d235fa62b91a..0fb72214f4a8bd2880103b2aa702bb1bc6b7e278 100644 (file)
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -18,11 +18,10 @@
 #define CONFIG_SYS_TIMER_BASE          0x110c00a0 /* TIMER5 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
 #define CONFIG_SYS_INIT_SP_ADDR                0x60100000
 #define CONFIG_SYS_LOAD_ADDR           0x60800800
 #define CONFIG_SPL_STACK               0x10088000
-#define CONFIG_SPL_TEXT_BASE           0x10081004
+#define CONFIG_SPL_TEXT_BASE           0x10081000
 
 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE  (28 << 10)
 #define CONFIG_ROCKCHIP_CHIP_TAG       "RK32"

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 78595b86ec4855ff9c58dc193f0c96edf91127df..23dbfecf018cd0fc04d28089652e0fdd0b6e340a 100644 (file)
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -19,8 +19,6 @@
 #define        CONFIG_SYS_TIMER_BASE           0xff810020 /* TIMER7 */
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550_MEM32
-
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #endif
@@ -73,6 +71,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "fdt_high=0x0fffffff\0" \
        "initrd_high=0x0fffffff\0" \
+       "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
        "partitions=" PARTS_DEFAULT \
        ENV_MEM_LAYOUT_SETTINGS \
        ROCKCHIP_DEVICE_SETTINGS \

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 349c53c2898d53c365e6b6267d78b2533da7a542..cd204e97184fd006fba0ca86206a675d34625bfa 100644 (file)
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -18,9 +18,6 @@
 #define CONFIG_SYS_TIMER_BASE          0x10350020
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMER_BASE + 8)
 
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
 #define CONFIG_SYS_SDRAM_BASE          0x60000000
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_TEXT_BASE + 0x100000)