cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
$(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk
- $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
+ $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all
$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
+ $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all
cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
+ cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin
$(VERSION_FILE):
@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
PQ2FADS-ZU_66MHz_lowboot_config \
: unconfig
@mkdir -p $(obj)include
- @mkdir -p $(obj)board/mpc8260ads
+ @mkdir -p $(obj)board/freescale/mpc8260ads
$(if $(findstring PQ2FADS,$@), \
@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
$(if $(findstring VR,$@), \
@echo "#define CONFIG_8260_CLKIN 66000000" >> $(obj)include/config.h))
@[ -z "$(findstring lowboot_,$@)" ] || \
- { echo "TEXT_BASE = 0xFF800000" >$(obj)board/mpc8260ads/config.tmp ; \
+ { echo "TEXT_BASE = 0xFF800000" >$(obj)board/freescale/mpc8260ads/config.tmp ; \
$(XECHO) "... with lowboot configuration" ; \
}
- @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads
+ @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads freescale
MPC8266ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale
# PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash
PM825_config \
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 freescale
P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
$(obj)board/{integratorap,integratorcp}/u-boot.lds \
$(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds
@rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map}
- @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl.map}
+ @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
@rm -f $(obj)api_examples/demo $(VERSION_FILE)
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
#include <common.h>
#include <mpc8xx.h>
+#if defined(CONFIG_OF_LIBFDT)
+ #include <libfdt.h>
+#endif
/*
* SDRAM is single Samsung K4S643232F-T70 chip (8MB)
return 0;
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+}
+#endif
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
+COBJS := $(BOARD).o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-/*
- * ADI Blackfin 537 MAC Ethernet
- *
- * Copyright (c) 2005 Analog Device, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <command.h>
-#include <malloc.h>
-#include "ether_bf537.h"
-
-#include <asm/mach-common/bits/dma.h>
-#include <asm/mach-common/bits/emac.h>
-#include <asm/mach-common/bits/pll.h>
-
-#ifdef CONFIG_POST
-#include <post.h>
-#endif
-
-#undef DEBUG_ETHERNET
-
-#ifdef DEBUG_ETHERNET
-#define DEBUGF(fmt,args...) printf(fmt,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-#if defined(CONFIG_CMD_NET)
-
-#define RXBUF_BASE_ADDR 0xFF900000
-#define TXBUF_BASE_ADDR 0xFF800000
-#define TX_BUF_CNT 1
-
-#define TOUT_LOOP 1000000
-
-ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
-ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
-static u16 txIdx; /* index of the current RX buffer */
-static u16 rxIdx; /* index of the current TX buffer */
-
-u8 SrcAddr[6];
-u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
-
-/* DMAx_CONFIG values at DMA Restart */
-const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
-
-#if 0
- rxdmacfg.b_DMA_EN = 1; /* enabled */
- rxdmacfg.b_WNR = 1; /* write to memory */
- rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
- rxdmacfg.b_DMA2D = 0; /* N/A */
- rxdmacfg.b_RESTART= 0; /* N/A */
- rxdmacfg.b_DI_SEL = 0; /* N/A */
- rxdmacfg.b_DI_EN = 0; /* no interrupt */
- rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
- rxdmacfg.b_FLOW = 7; /* large desc flow */
-#endif
-
-const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
-
-#if 0
- txdmacfg.b_DMA_EN = 1; /* enabled */
- txdmacfg.b_WNR = 0; /* read from memory */
- txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
- txdmacfg.b_DMA2D = 0; /* N/A */
- txdmacfg.b_RESTART= 0; /* N/A */
- txdmacfg.b_DI_SEL = 0; /* N/A */
- txdmacfg.b_DI_EN = 0; /* no interrupt */
- txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
- txdmacfg.b_FLOW = 7; /* large desc flow */
-#endif
-
-ADI_ETHER_BUFFER *SetupRxBuffer(int no);
-ADI_ETHER_BUFFER *SetupTxBuffer(int no);
-
-static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
-static void bfin_EMAC_halt(struct eth_device *dev);
-static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
- int length);
-static int bfin_EMAC_recv(struct eth_device *dev);
-
-int bfin_EMAC_initialize(bd_t * bis)
-{
- struct eth_device *dev;
- dev = (struct eth_device *)malloc(sizeof(*dev));
- if (dev == NULL)
- hang();
-
- memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "BF537 ETHERNET");
-
- dev->iobase = 0;
- dev->priv = 0;
- dev->init = bfin_EMAC_init;
- dev->halt = bfin_EMAC_halt;
- dev->send = bfin_EMAC_send;
- dev->recv = bfin_EMAC_recv;
-
- eth_register(dev);
-
- return 1;
-}
-
-static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
- int length)
-{
- int i;
- int result = 0;
- unsigned int *buf;
- buf = (unsigned int *)packet;
-
- if (length <= 0) {
- printf("Ethernet: bad packet size: %d\n", length);
- goto out;
- }
-
- if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
- printf("Ethernet: tx DMA error\n");
- goto out;
- }
-
- for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
- if (i > TOUT_LOOP) {
- puts("Ethernet: tx time out\n");
- goto out;
- }
- }
- txbuf[txIdx]->FrmData->NoBytes = length;
- memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
- txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
- *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
- *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
- *pEMAC_OPMODE |= TE;
-
- for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
- if (i > TOUT_LOOP) {
- puts("Ethernet: tx error\n");
- goto out;
- }
- }
- result = txbuf[txIdx]->StatusWord;
- txbuf[txIdx]->StatusWord = 0;
- if ((txIdx + 1) >= TX_BUF_CNT)
- txIdx = 0;
- else
- txIdx++;
- out:
- DEBUGF("BFIN EMAC send: length = %d\n", length);
- return result;
-}
-
-static int bfin_EMAC_recv(struct eth_device *dev)
-{
- int length = 0;
-
- for (;;) {
- if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
- length = -1;
- break;
- }
- if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
- printf("Ethernet: rx dma overrun\n");
- break;
- }
- if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
- printf("Ethernet: rx error\n");
- break;
- }
- length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
- if (length <= 4) {
- printf("Ethernet: bad frame\n");
- break;
- }
- NetRxPackets[rxIdx] =
- (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
- NetReceive(NetRxPackets[rxIdx], length - 4);
- *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
- rxbuf[rxIdx]->StatusWord = 0x00000000;
- if ((rxIdx + 1) >= PKTBUFSRX)
- rxIdx = 0;
- else
- rxIdx++;
- }
-
- return length;
-}
-
-/**************************************************************
- *
- * Ethernet Initialization Routine
- *
- *************************************************************/
-
-static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
-{
- u32 opmode;
- int dat;
- int i;
- DEBUGF("Eth_init: ......\n");
-
- txIdx = 0;
- rxIdx = 0;
-
-/* Initialize System Register */
- if (SetupSystemRegs(&dat) < 0)
- return -1;
-
-/* Initialize EMAC address */
- SetupMacAddr(SrcAddr);
-
-/* Initialize TX and RX buffer */
- for (i = 0; i < PKTBUFSRX; i++) {
- rxbuf[i] = SetupRxBuffer(i);
- if (i > 0) {
- rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
- &(rxbuf[i]->Dma[0]);
- if (i == (PKTBUFSRX - 1))
- rxbuf[i]->Dma[1].NEXT_DESC_PTR =
- &(rxbuf[0]->Dma[0]);
- }
- }
- for (i = 0; i < TX_BUF_CNT; i++) {
- txbuf[i] = SetupTxBuffer(i);
- if (i > 0) {
- txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
- &(txbuf[i]->Dma[0]);
- if (i == (TX_BUF_CNT - 1))
- txbuf[i]->Dma[1].NEXT_DESC_PTR =
- &(txbuf[0]->Dma[0]);
- }
- }
-
- /* Set RX DMA */
- *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
- *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
-
- /* Wait MII done */
- PollMdcDone();
-
- /* We enable only RX here */
- /* ASTP : Enable Automatic Pad Stripping
- PR : Promiscuous Mode for test
- PSF : Receive frames with total length less than 64 bytes.
- FDMODE : Full Duplex Mode
- LB : Internal Loopback for test
- RE : Receiver Enable */
- if (dat == FDMODE)
- opmode = ASTP | FDMODE | PSF;
- else
- opmode = ASTP | PSF;
- opmode |= RE;
-#ifdef CONFIG_BFIN_MAC_RMII
- opmode |= TE | RMII;
-#endif
- /* Turn on the EMAC */
- *pEMAC_OPMODE = opmode;
- return 0;
-}
-
-static void bfin_EMAC_halt(struct eth_device *dev)
-{
- DEBUGF("Eth_halt: ......\n");
- /* Turn off the EMAC */
- *pEMAC_OPMODE = 0x00000000;
- /* Turn off the EMAC RX DMA */
- *pDMA1_CONFIG = 0x0000;
- *pDMA2_CONFIG = 0x0000;
-
-}
-
-void SetupMacAddr(u8 * MACaddr)
-{
- char *tmp, *end;
- int i;
- /* this depends on a little-endian machine */
- tmp = getenv("ethaddr");
- if (tmp) {
- for (i = 0; i < 6; i++) {
- MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end + 1 : end;
- }
-
-#ifndef CONFIG_NETCONSOLE
- printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
- MACaddr[0], MACaddr[1],
- MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
-#endif
- *pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
- MACaddr[2] << 16 | MACaddr[3] << 24;
- *pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
- }
-}
-
-void PollMdcDone(void)
-{
- /* poll the STABUSY bit */
- while (*pEMAC_STAADD & STABUSY) ;
-}
-
-void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
-{
- PollMdcDone();
-
- *pEMAC_STADAT = Data;
-
- *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
- STAOP | STAIE | STABUSY;
-}
-
-/*********************************************************************************
- * Read an off-chip register in a PHY through the MDC/MDIO port *
- *********************************************************************************/
-u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
-{
- u16 Data;
-
- PollMdcDone();
-
- *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
- STAIE | STABUSY;
-
- PollMdcDone();
-
- Data = (u16) * pEMAC_STADAT;
-
- PHYregs[RegAddr] = Data; /* save shadow copy */
-
- return Data;
-}
-
-void SoftResetPHY(void)
-{
- u16 phydat;
- /* set the reset bit */
- WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
- /* and clear it again */
- WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
- do {
- /* poll until reset is complete */
- phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
- } while ((phydat & PHY_RESET) != 0);
-}
-
-int SetupSystemRegs(int *opmode)
-{
- u16 sysctl, phydat;
- int count = 0;
- /* Enable PHY output */
- *pVR_CTL |= CLKBUFOE;
- /* MDC = 2.5 MHz */
- sysctl = SET_MDCDIV(24);
- /* Odd word alignment for Receive Frame DMA word */
- /* Configure checksum support and rcve frame word alignment */
- sysctl |= RXDWA | RXCKS;
- *pEMAC_SYSCTL = sysctl;
- /* auto negotiation on */
- /* full duplex */
- /* 100 Mbps */
- phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
- WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
- do {
- udelay(1000);
- phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
- if (count > 3000) {
- printf
- ("Link is down, please check your network connection\n");
- return -1;
- }
- count++;
- } while (!(phydat & 0x0004));
-
- phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
-
- if ((phydat & 0x0100) || (phydat & 0x0040))
- *opmode = FDMODE;
- else
- *opmode = 0;
-
- *pEMAC_MMC_CTL = RSTC | CROLL;
-
- /* Initialize the TX DMA channel registers */
- *pDMA2_X_COUNT = 0;
- *pDMA2_X_MODIFY = 4;
- *pDMA2_Y_COUNT = 0;
- *pDMA2_Y_MODIFY = 0;
-
- /* Initialize the RX DMA channel registers */
- *pDMA1_X_COUNT = 0;
- *pDMA1_X_MODIFY = 4;
- *pDMA1_Y_COUNT = 0;
- *pDMA1_Y_MODIFY = 0;
- return 0;
-}
-
-ADI_ETHER_BUFFER *SetupRxBuffer(int no)
-{
- ADI_ETHER_FRAME_BUFFER *frmbuf;
- ADI_ETHER_BUFFER *buf;
- int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
- int total_size = nobytes_buffer + RECV_BUFSIZE;
-
- buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
- frmbuf =
- (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
- nobytes_buffer);
-
- memset(buf, 0x00, nobytes_buffer);
- buf->FrmData = frmbuf;
- memset(frmbuf, 0xfe, RECV_BUFSIZE);
-
- /* set up first desc to point to receive frame buffer */
- buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
- buf->Dma[0].START_ADDR = (u32) buf->FrmData;
- buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
- buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
- buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
-
- /* set up second desc to point to status word */
- buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
- buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
- buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
- buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
- buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
- buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
-
- return buf;
-}
-
-ADI_ETHER_BUFFER *SetupTxBuffer(int no)
-{
- ADI_ETHER_FRAME_BUFFER *frmbuf;
- ADI_ETHER_BUFFER *buf;
- int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
- int total_size = nobytes_buffer + RECV_BUFSIZE;
-
- buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
- frmbuf =
- (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
- nobytes_buffer);
-
- memset(buf, 0x00, nobytes_buffer);
- buf->FrmData = frmbuf;
- memset(frmbuf, 0x00, RECV_BUFSIZE);
-
- /* set up first desc to point to receive frame buffer */
- buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
- buf->Dma[0].START_ADDR = (u32) buf->FrmData;
- buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
- buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
- buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
-
- /* set up second desc to point to status word */
- buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
- buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
- buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
- buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
- buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
- buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
- buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
- buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
-
- return buf;
-}
-
-#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
-int ether_post_test(int flags)
-{
- uchar buf[64];
- int i, value = 0;
- int length;
-
- printf("\n--------");
- bfin_EMAC_init(NULL, NULL);
- /* construct the package */
- buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
- buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
- buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
- buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
- buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
- buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
- buf[12] = 0x08; /* Type: ARP */
- buf[13] = 0x06;
- buf[14] = 0x00; /* Hardware type: Ethernet */
- buf[15] = 0x01;
- buf[16] = 0x08; /* Protocal type: IP */
- buf[17] = 0x00;
- buf[18] = 0x06; /* Hardware size */
- buf[19] = 0x04; /* Protocol size */
- buf[20] = 0x00; /* Opcode: request */
- buf[21] = 0x01;
-
- for (i = 0; i < 42; i++)
- buf[i + 22] = i;
- printf("--------Send 64 bytes......\n");
- bfin_EMAC_send(NULL, (volatile void *)buf, 64);
- for (i = 0; i < 100; i++) {
- udelay(10000);
- if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
- value = 1;
- break;
- }
- }
- if (value == 0) {
- printf("--------EMAC can't receive any data\n");
- eth_halt();
- return -1;
- }
- length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
- for (i = 0; i < length; i++) {
- if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
- printf("--------EMAC receive error data!\n");
- eth_halt();
- return -1;
- }
- }
- printf("--------receive %d bytes, matched\n", length);
- bfin_EMAC_halt(NULL);
- return 0;
-}
-#endif
-#endif
+++ /dev/null
-#define PHYADDR 0x01
-#define NO_PHY_REGS 0x20
-
-#define DEFAULT_PHY_PHYID1 0x0007
-#define DEFAULT_PHY_PHYID2 0xC0A3
-#define PHY_MODECTL 0x00
-#define PHY_MODESTAT 0x01
-#define PHY_PHYID1 0x02
-#define PHY_PHYID2 0x03
-#define PHY_ANAR 0x04
-#define PHY_ANLPAR 0x05
-#define PHY_ANER 0x06
-
-#define PHY_RESET 0x8000
-#define PHY_ANEG_EN 0x1000
-#define PHY_DUPLEX 0x0100
-#define PHY_SPD_SET 0x2000
-
-#define RECV_BUFSIZE (0x614)
-
-typedef volatile u32 reg32;
-typedef volatile u16 reg16;
-
-typedef struct ADI_DMA_CONFIG_REG {
- u16 b_DMA_EN:1; /* 0 Enabled */
- u16 b_WNR:1; /* 1 Direction */
- u16 b_WDSIZE:2; /* 2:3 Transfer word size */
- u16 b_DMA2D:1; /* 4 DMA mode */
- u16 b_RESTART:1; /* 5 Retain FIFO */
- u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
- u16 b_DI_EN:1; /* 7 Data interrupt enabled */
- u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
- u16 b_FLOW:3; /* 12:14Flow */
-} ADI_DMA_CONFIG_REG;
-
-typedef struct adi_ether_frame_buffer {
- u16 NoBytes; /* the no. of following bytes */
- u8 Dest[6]; /* destination MAC address */
- u8 Srce[6]; /* source MAC address */
- u16 LTfield; /* length/type field */
- u8 Data[0]; /* payload bytes */
-} ADI_ETHER_FRAME_BUFFER;
-/* 16 bytes/struct */
-
-typedef struct dma_descriptor {
- struct dma_descriptor *NEXT_DESC_PTR;
- u32 START_ADDR;
- ADI_DMA_CONFIG_REG CONFIG;
-} DMA_DESCRIPTOR;
-/* 10 bytes/struct in 12 bytes */
-
-typedef struct adi_ether_buffer {
- DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
- ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
- struct adi_ether_buffer *pNext; /* next buffer */
- struct adi_ether_buffer *pPrev; /* prev buffer */
- u16 IPHdrChksum; /* the IP header checksum */
- u16 IPPayloadChksum; /* the IP header and payload checksum */
- volatile u32 StatusWord; /* the frame status word */
-} ADI_ETHER_BUFFER;
-/* 40 bytes/struct in 44 bytes */
-
-void SetupMacAddr(u8 * MACaddr);
-
-void PollMdcDone(void);
-void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
-u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
-void SoftResetPHY(void);
-void DumpPHYRegs(void);
-
-int SetupSystemRegs(int *opmode);
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o tsi108_init.o
+SOBJS := asm_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+.PHONY: distclean
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2004-05; Tundra Semiconductor Corp.
+ *
+ * Added automatic detect of SDC settings
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ * Maintainer tie-fei.zang@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * FILENAME: asm_init.s
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Initialization code for the Tundra Tsi108 bridge chip
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/processor.h>
+
+#include <tsi108.h>
+
+/*
+ * Build Configuration Options
+ */
+
+/* #define DISABLE_PBM disables usage of PB Master */
+/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
+/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
+
+/*
+ * Hardcoded SDC settings
+ */
+
+#ifdef SDC_HARDCODED_INIT
+
+/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
+
+#define VAL_SD_REFRESH (0x61A)
+#define VAL_SD_TIMING (0x0308336b)
+#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
+#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
+#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
+#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
+
+#endif /* SDC_HARDCODED_INIT */
+
+/*
+ CPU Configuration:
+
+ CPU Address and Data Parity enables.
+
+#define CPU_AP
+#define CPU_DP
+*/
+
+/*
+ * Macros
+ * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
+ * expected to work correctly for the CSR space within 32KB range.
+ *
+ * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
+ * These macros are absolutely identical except their names. This difference
+ * is provided intentionally for better readable code.
+ */
+
+#define LOAD_PTR(reg,const32) \
+ addis reg,r0,const32@h; ori reg,reg,const32@l
+
+#define LOAD_U32(reg,const32) \
+ addis reg,r0,const32@h; ori reg,reg,const32@l
+
+/* LOADMEM initializes a register with the contents of a specified 32-bit
+ * memory location, usually a CSR value.
+ */
+
+#define LOAD_MEM(reg,addr32) \
+ addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
+
+#ifndef SDC_HARDCODED_INIT
+sdc_clk_sync:
+ /* MHz: 0,0,183,100,133,167,200,233 */
+ .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
+#endif
+
+/*
+ * board_asm_init() - early initialization function. Coded to be portable to
+ * dual-CPU configuration.
+ * Checks CPU number and performs board HW initialization if called for CPU0.
+ * Registers used: r3,r4,r5,r6,r19,r29
+ *
+ * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
+ * and the rest of the board. Current implementation demonstrates two
+ * possible ways to identify CPU number:
+ * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
+ * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
+ */
+
+ .globl board_asm_init
+board_asm_init:
+ mflr r19 /* Save LR to be able return later. */
+ bl icache_enable /* Enable icache to reduce reads from flash. */
+
+/* Initialize pointer to Tsi108 register space */
+
+ LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
+ ori r4,r29,TSI108_PB_REG_OFFSET
+
+/* Check Processor Version Number */
+
+ mfspr r3, PVR
+ rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
+
+ cmpli 0,0,r3,0x8000 /* MPC74xx */
+ bne cont_brd_init
+
+ /*
+ * For MPC744x/5x enable extended BATs[4-7]
+ * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
+ * to disable prefetch
+ */
+
+ mfspr r5, HID0
+ oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
+ ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
+ mtspr HID0, r5
+ isync
+ sync
+
+ /* Adding code to disable external interventions in MPX bus mode */
+ mfspr r3, 1014
+ oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
+ mtspr 1014, r3
+ isync
+ sync
+
+ /* Sri: code to enable FP unit */
+ mfmsr r3
+ ori r3, r3, 0x2000
+ mtmsr r3
+ isync
+ sync
+
+ /* def CONFIG_DUAL_CPU
+ * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
+ */
+#if(1)
+ mfspr r3,1014 /* read MSSCR0 */
+ rlwinm. r3,r3,27,31,31 /* get processor ID number */
+ mtspr SPRN_PIR,r3 /* Save CPU ID */
+ sync
+ bne init_done
+ b do_tsi108_init
+
+cont_brd_init:
+
+ /* An alternative method of checking the processor number (in addition
+ * to configuration using MSSCR0[ID] bit on MPC74xx).
+ * Good for IBM PPC750FX/GX.
+ */
+
+ lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
+ rlwinm. r3,r3,24,31,31 /* get processor ID number */
+ bne init_done
+#else
+
+cont_brd_init:
+
+#endif /* CONFIG_DUAL_CPU */
+
+ /* Initialize Tsi108 chip */
+
+do_tsi108_init:
+
+ /*
+ * Adjust HLP/Flash parameters. By default after reset the HLP port is
+ * set to support slow devices. Better performance can be achived when
+ * an optimal parameters are used for specific EPROM device.
+ * NOTE: This should be performed ASAP for the emulation platform
+ * because it has 5MHz HLP clocking.
+ */
+
+#ifdef CONFIG_TSI108EMU
+ ori r4,r29,TSI108_HLP_REG_OFFSET
+ LOAD_U32(r5,0x434422c0)
+ stw r5,0x08(r4) /* set HLP B0_CTRL0 */
+ sync
+ LOAD_U32(r5,0xd0012000)
+ stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
+ sync
+#endif
+
+ /* Initialize PB interface. */
+
+ ori r4,r29,TSI108_PB_REG_OFFSET
+
+#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
+ /* Relocate (if required) Tsi108 registers. Set new value for
+ * PB_REG_BAR:
+ * Note we are in the 32-bit address mode.
+ */
+ LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
+ stw r5,PB_REG_BAR(r4)
+ andis. r29,r5,0xFFFF
+ sync
+ ori r4,r29,TSI108_PB_REG_OFFSET
+#endif
+
+ /* Set PB Slave configuration register */
+
+ LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
+ lwz r3, PB_RSR(r4) /* get PB bus mode */
+ xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
+ rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
+ stw r5,PB_SCR(r4)
+ sync
+
+ /* Configure PB Arbiter */
+
+ lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
+ li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
+#ifdef DISABLE_PBM
+ ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
+#endif
+ andc r5,r5,r3 /* Clear the masked bit fields */
+ ori r5,r5,0x0001 /* Set pipeline depth */
+ stw r5,PB_ARB_CTRL(r4)
+
+#if (0) /* currently using the default settings for PBM after reset */
+ LOAD_U32(r5,0x) /* value for PB_MCR */
+ stw r5,PB_MCR(r4)
+ sync
+
+ LOAD_U32(r5,0x) /* value for PB_MCMD */
+ stw r5,PB_MCMD(r4)
+ sync
+#endif
+
+ /* Disable or enable PVT based on processor bus frequency
+ * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
+ * 2. See if the value is < or > 133mhz (18:16 = 100)
+ * 3. If > enable PVT
+ */
+
+ LOAD_U32(r3,0xC0002234)
+ lwz r3,0(r3)
+ rlwinm r3,r3,16,29,31
+
+ cmpi 0,0,r3,0x0004
+ bgt sdc_init
+
+#ifndef CONFIG_TSI108EMU
+ /* FIXME: Disable PB calibration control for any real Tsi108 board */
+ li r5,0x0101 /* disable calibration control */
+ stw r5,PB_PVT_CTRL2(r4)
+ sync
+#endif
+
+ /* Initialize SDRAM controller. */
+
+sdc_init:
+
+#ifndef SDC_HARDCODED_INIT
+ /* get SDC clock prior doing sdram controller autoconfig */
+ ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
+ lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
+ rlwinm r3,r3,12,29,31 /* r3 - SD clk */
+ lis r5,sdc_clk_sync@h
+ ori r5,r5,sdc_clk_sync@l
+ /* Sri: At this point check if r3 = 001. If yes,
+ * the memory frequency should be same as the
+ * MPX bus frequency
+ */
+ cmpi 0,0,r3,0x0001
+ bne get_nsec
+ lwz r6, CG_PWRUP_STATUS(r4)
+ rlwinm r6,r6,16,29,31
+ mr r3,r6
+
+get_nsec:
+ rlwinm r3,r3,2,0,31
+ lwzx r9,r5,r3 /* get SD clk rate in nSec */
+ /* ATTN: r9 will be used by SPD routine */
+#endif /* !SDC_HARDCODED_INIT */
+
+ ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
+
+ /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
+
+ LOAD_U32(r5,0x00)
+ stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
+#ifdef ENABLE_SDRAM_ECC
+ li r5, 0x01
+#endif /* ENABLE_SDRAM_ECC */
+ stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
+ sync
+
+#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
+
+ /* First read the CG_PWRUP_STATUS register to get the
+ * memory speed from bits 22,21,20
+ */
+
+ LOAD_U32(r3,0xC0002234)
+ lwz r3,0(r3)
+ rlwinm r3,r3,12,29,31
+
+ /* Now first check for 166, then 200, or default */
+
+ cmpi 0,0,r3,0x0005
+ bne check_for_200mhz
+
+ /* set values for 166 Mhz memory speed
+ * Set refresh rate and timing parameters
+ */
+ LOAD_U32(r5,0x00000515)
+ stw r5,SD_REFRESH(r4)
+ LOAD_U32(r5,0x03073368)
+ stw r5,SD_TIMING(r4)
+ sync
+
+ /* Initialize DIMM0 control and BAR registers */
+ LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D0_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D0_BAR)
+ stw r5,SD_D0_BAR(r4)
+ sync
+
+ /* Initialize DIMM1 control and BAR registers
+ * (same as dimm 0, next 512MB, disabled)
+ */
+ LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D1_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D1_BAR)
+ stw r5,SD_D1_BAR(r4)
+ sync
+
+ b sdc_init_done
+
+check_for_200mhz:
+
+ cmpi 0,0,r3,0x0006
+ bne set_default_values
+
+ /* set values for 200Mhz memory speed
+ * Set refresh rate and timing parameters
+ */
+ LOAD_U32(r5,0x0000061a)
+ stw r5,SD_REFRESH(r4)
+ LOAD_U32(r5,0x03083348)
+ stw r5,SD_TIMING(r4)
+ sync
+
+ /* Initialize DIMM0 control and BAR registers */
+ LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D0_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D0_BAR)
+ stw r5,SD_D0_BAR(r4)
+ sync
+
+ /* Initialize DIMM1 control and BAR registers
+ * (same as dimm 0, next 512MB, disabled)
+ */
+ LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D1_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D1_BAR)
+ stw r5,SD_D1_BAR(r4)
+ sync
+
+ b sdc_init_done
+
+set_default_values:
+
+ /* Set refresh rate and timing parameters */
+ LOAD_U32(r5,VAL_SD_REFRESH)
+ stw r5,SD_REFRESH(r4)
+ LOAD_U32(r5,VAL_SD_TIMING)
+ stw r5,SD_TIMING(r4)
+ sync
+
+ /* Initialize DIMM0 control and BAR registers */
+ LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D0_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D0_BAR)
+ stw r5,SD_D0_BAR(r4)
+ sync
+
+ /* Initialize DIMM1 control and BAR registers
+ * (same as dimm 0, next 512MB, disabled)
+ */
+ LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D1_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D1_BAR)
+ stw r5,SD_D1_BAR(r4)
+ sync
+#else /* !SDC_HARDCODED_INIT */
+ bl tsi108_sdram_spd /* automatically detect SDC settings */
+#endif /* SDC_HARDCODED_INIT */
+
+sdc_init_done:
+
+#ifdef DISABLE_PBM
+ LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
+#else
+ LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
+#endif /* DISABLE_PBM */
+
+#ifdef CONFIG_TSI108EMU
+ oris r5,r5,0x0010 /* set EMULATION_MODE bit */
+#endif
+
+ stw r5,SD_CTRL(r4)
+ eieio
+ sync
+
+ /* Enable SDRAM access */
+
+ oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
+ stw r5,SD_CTRL(r4)
+ sync
+
+wait_init_complete:
+ lwz r5,SD_STATUS(r4)
+ andi. r5,r5,0x0001
+ /* wait until SDRAM initialization is complete */
+ beq wait_init_complete
+
+ /* Map SDRAM into the processor bus address space */
+
+ ori r4,r29,TSI108_PB_REG_OFFSET
+
+ /* Setup BARs associated with direct path PB<->SDRAM */
+
+ /* PB_SDRAM_BAR1:
+ * provides a direct path to the main system memory (cacheable SDRAM)
+ */
+
+ /* BA=0,Size=512MB, ENable, No Addr.Translation */
+ LOAD_U32(r5, 0x00000011)
+ stw r5,PB_SDRAM_BAR1(r4)
+ sync
+
+ /* Make sure that PB_SDRAM_BAR1 decoder is set
+ * (to allow following immediate read from SDRAM)
+ */
+ lwz r5,PB_SDRAM_BAR1(r4)
+ sync
+
+ /* PB_SDRAM_BAR2:
+ * provides non-cacheable alias (via the direct path) to main
+ * system memory.
+ * Size = 512MB, ENable, Addr.Translation - ON,
+ * BA = 0x0_40000000, TA = 0x0_00000000
+ */
+
+ LOAD_U32(r5, 0x40010011)
+ stw r5,PB_SDRAM_BAR2(r4)
+ sync
+
+ /* Make sure that PB_SDRAM_BAR2 decoder is set
+ * (to allow following immediate read from SDRAM)
+ */
+ lwz r5,PB_SDRAM_BAR2(r4)
+ sync
+
+init_done:
+
+ /* All done. Restore LR and return. */
+ mtlr r19
+ blr
+
+#if (0)
+ /*
+ * init_cpu1
+ * This routine enables CPU1 on the dual-processor system.
+ * Now there is only one processor in the system
+ */
+
+ .global enable_cpu1
+enable_cpu1:
+
+ lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
+ addi r3,r3,Tsi108_Base@l
+ lwz r3,0(r3) /* R3 = CSR Base Addr */
+ ori r4,r3,TSI108_PB_REG_OFFSET
+ lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
+ ori r3,r3,0x0200 /* Set M1_EN bit */
+ stw r3,PB_ARB_CTRL(r4)
+
+ blr
+#endif
+
+ /*
+ * enable_EI
+ * Enable CPU core external interrupt
+ */
+
+ .global enable_EI
+enable_EI:
+ mfmsr r3
+ ori r3,r3,0x8000 /* set EE bit */
+ mtmsr r3
+ blr
+
+ /*
+ * disable_EI
+ * Disable CPU core external interrupt
+ */
+
+ .global disable_EI
+disable_EI:
+ mfmsr r3
+ li r4,-32768 /* aka "li r4,0x8000" */
+ andc r3,r3,r4 /* clear EE bit */
+ mtmsr r3
+ blr
+
+#ifdef ENABLE_SDRAM_ECC
+ /* enables SDRAM ECC */
+
+ .global enable_ECC
+enable_ECC:
+ ori r4,r29,TSI108_SD_REG_OFFSET
+ lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
+ ori r3,r3,0x0001 /* Set ECC_EN bit */
+ stw r3,SD_ECC_CTRL(r4)
+ blr
+
+ /*
+ * clear_ECC_err
+ * Clears all pending SDRAM ECC errors
+ * (normally after SDRAM scrubbing/initialization)
+ */
+
+ .global clear_ECC_err
+clear_ECC_err:
+ ori r4,r29,TSI108_SD_REG_OFFSET
+ ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
+ stw r3,SD_INT_STATUS(r4)
+ blr
+
+#endif /* ENABLE_SDRAM_ECC */
+
+#ifndef SDC_HARDCODED_INIT
+
+ /* SDRAM SPD Support */
+#define SD_I2C_CTRL1 (0x400)
+#define SD_I2C_CTRL2 (0x404)
+#define SD_I2C_RD_DATA (0x408)
+#define SD_I2C_WR_DATA (0x40C)
+
+ /*
+ * SDRAM SPD Support Macros
+ */
+
+#define SPD_DIMM0 (0x00000100)
+#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
+
+#define SPD_RDIMM (0x01)
+#define SPD_UDIMM (0x02)
+
+#define SPD_CAS_3 0x8
+#define SPD_CAS_4 0x10
+#define SPD_CAS_5 0x20
+
+#define ERR_NO_DIMM_FOUND (0xdb0)
+#define ERR_TRAS_FAIL (0xdb1)
+#define ERR_TRCD_FAIL (0xdb2)
+#define ERR_TRP_FAIL (0xdb3)
+#define ERR_TWR_FAIL (0xdb4)
+#define ERR_UNKNOWN_PART (0xdb5)
+#define ERR_NRANK_INVALID (0xdb6)
+#define ERR_DIMM_SIZE (0xdb7)
+#define ERR_ADDR_MODE (0xdb8)
+#define ERR_RFRSH_RATE (0xdb9)
+#define ERR_DIMM_TYPE (0xdba)
+#define ERR_CL_VALUE (0xdbb)
+#define ERR_TRFC_FAIL (0xdbc)
+
+/* READ_SPD requirements:
+ * byte - byte address in SPD device (0 - 255)
+ * r3 = will return data read from I2C Byte location
+ * r4 - unchanged (SDC base addr)
+ * r5 - clobbered in routine (I2C status)
+ * r10 - number of DDR slot where first SPD device is detected
+ */
+
+#define READ_SPD(byte_num) \
+ addis r3, 0, byte_num@l; \
+ or r3, r3, r10; \
+ ori r3, r3, 0x0A; \
+ stw r3, SD_I2C_CTRL1(r4); \
+ li r3, I2C_CNTRL2_START; \
+ stw r3, SD_I2C_CTRL2(r4); \
+ eieio; \
+ sync; \
+ li r3, 0x100; \
+1:; \
+ addic. r3, r3, -1; \
+ bne 1b; \
+2:; \
+ lwz r5, SD_I2C_CTRL2(r4); \
+ rlwinm. r3,r5,0,23,23; \
+ bne 2b; \
+ rlwinm. r3,r5,0,3,3; \
+ lwz r3,SD_I2C_RD_DATA(r4)
+
+#define SPD_MIN_RFRSH (0x80)
+#define SPD_MAX_RFRSH (0x85)
+
+refresh_rates: /* in nSec */
+ .long 15625 /* Normal (0x80) */
+ .long 3900 /* Reduced 0.25x (0x81) */
+ .long 7800 /* Reduced 0.5x (0x82) */
+ .long 31300 /* Extended 2x (0x83) */
+ .long 62500 /* Extended 4x (0x84) */
+ .long 125000 /* Extended 8x (0x85) */
+
+/*
+ * tsi108_sdram_spd
+ *
+ * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
+ * Uses registers: r4 - SDC base address (not changed)
+ * r9 - SDC clocking period in nSec
+ * Changes registers: r3,r5,r6,r7,r8,r10,r11
+ */
+
+tsi108_sdram_spd:
+
+ li r10,SPD_DIMM0
+ xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
+
+do_first_dimm:
+
+ /* Program Refresh Rate Register */
+
+ READ_SPD(12) /* get Refresh Rate */
+ beq check_next_slot
+ li r5, ERR_RFRSH_RATE
+ cmpi 0,0,r3,SPD_MIN_RFRSH
+ ble spd_fail
+ cmpi 0,0,r3,SPD_MAX_RFRSH
+ bgt spd_fail
+ addi r3,r3,-SPD_MIN_RFRSH
+ rlwinm r3,r3,2,0,31
+ lis r5,refresh_rates@h
+ ori r5,r5,refresh_rates@l
+ lwzx r5,r5,r3 /* get refresh rate in nSec */
+ divwu r5,r5,r9 /* calculate # of SDC clocks */
+ stw r5,SD_REFRESH(r4) /* Set refresh rate */
+ sync
+
+ /* Program SD Timing Register */
+
+ li r7, 0 /* clear r7 prior parameter collection */
+
+ READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
+ beq spd_read_fail
+ li r5, ERR_DIMM_TYPE
+ cmpi 0,0,r3,SPD_UDIMM
+ beq do_cl
+ cmpi 0,0,r3,SPD_RDIMM
+ bne spd_fail
+ oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
+
+do_cl:
+ READ_SPD(18) /* Get CAS Latency */
+ beq spd_read_fail
+ li r5,ERR_CL_VALUE
+ andi. r6,r3,SPD_CAS_3
+ beq cl_4
+ li r6,3
+ b set_cl
+cl_4:
+ andi. r6,r3,SPD_CAS_4
+ beq cl_5
+ li r6,4
+ b set_cl
+cl_5:
+ andi. r6,r3,SPD_CAS_5
+ beq spd_fail
+ li r6,5
+set_cl:
+ rlwimi r7,r6,24,5,7
+
+ READ_SPD(30) /* Get tRAS */
+ beq spd_read_fail
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_tras
+ addi r6,r6,1
+set_tras:
+ li r5,ERR_TRAS_FAIL
+ cmpi 0,0,r6,0x0F /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,16,12,15
+
+ READ_SPD(29) /* Get tRCD */
+ beq spd_read_fail
+ /* right shift tRCD by 2 bits as per DDR2 spec */
+ rlwinm r3,r3,30,2,31
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_trcd
+ addi r6,r6,1
+set_trcd:
+ li r5,ERR_TRCD_FAIL
+ cmpi 0,0,r6,0x07 /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,12,17,19
+
+ READ_SPD(27) /* Get tRP value */
+ beq spd_read_fail
+ rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_trp
+ addi r6,r6,1
+set_trp:
+ li r5,ERR_TRP_FAIL
+ cmpi 0,0,r6,0x07 /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,8,21,23
+
+ READ_SPD(36) /* Get tWR value */
+ beq spd_read_fail
+ rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_twr
+ addi r6,r6,1
+set_twr:
+ addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
+ li r5,ERR_TWR_FAIL
+ cmpi 0,0,r6,0x07 /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,5,24,26
+
+ READ_SPD(42) /* Get tRFC */
+ beq spd_read_fail
+ li r5, ERR_TRFC_FAIL
+ /* Tsi108 spec: tRFC=(tRFC + 1)/2 */
+ addi r3,r3,1
+ rlwinm. r3,r3,31,1,31 /* divide by 2 */
+ beq spd_fail
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_trfc
+ addi r6,r6,1
+set_trfc:
+ cmpi 0,0,r6,0x1F /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,0,27,31
+
+ stw r7,SD_TIMING(r4)
+ sync
+
+ /*
+ * The following two registers are set on per-DIMM basis.
+ * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
+ */
+
+do_each_dimm:
+
+ /* Program SDRAM DIMM Control Register */
+
+ li r7, 0 /* clear r7 prior parameter collection */
+
+ READ_SPD(13) /* Get Primary SDRAM Width */
+ beq spd_read_fail
+ cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
+ beq do_nbank
+ oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
+
+do_nbank:
+ READ_SPD(17) /* Get Number of banks on SDRAM device */
+ beq spd_read_fail
+ /* Grendel only distinguish betw. 4 or 8-bank memory parts */
+ li r5,ERR_UNKNOWN_PART /* non-supported memory part */
+ cmpi 0,0,r3,4
+ beq do_nrank
+ cmpi 0,0,r3,8
+ bne spd_fail
+ ori r7,r7,0x1000
+
+do_nrank:
+ READ_SPD(5) /* Get # of Ranks */
+ beq spd_read_fail
+ li r5,ERR_NRANK_INVALID
+ andi. r6,r3,0x7 /* Use bits [2..0] only */
+ beq do_addr_mode
+ cmpi 0,0,r6,1
+ bgt spd_fail
+ rlwimi r7,r6,8,23,23
+
+do_addr_mode:
+ READ_SPD(4) /* Get # of Column Addresses */
+ beq spd_read_fail
+ li r5, ERR_ADDR_MODE
+ andi. r3,r3,0x0f /* cut off reserved bits */
+ cmpi 0,0,r3,8
+ ble spd_fail
+ cmpi 0,0,r3,15
+ bgt spd_fail
+ addi r6,r3,-8 /* calculate ADDR_MODE parameter */
+ rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
+
+set_dimm_ctrl:
+#ifdef SDC_AUTOPRECH_EN
+ oris r7,r7,0x0001 /* set auto precharge EN bit */
+#endif
+ ori r7,r7,1 /* set ENABLE bit */
+ cmpi 0,0,r10,SPD_DIMM0
+ bne 1f
+ stw r7,SD_D0_CTRL(r4)
+ sync
+ b set_dimm_bar
+1:
+ stw r7,SD_D1_CTRL(r4)
+ sync
+
+
+ /* Program SDRAM DIMMx Base Address Register */
+
+set_dimm_bar:
+ READ_SPD(5) /* get # of Ranks */
+ beq spd_read_fail
+ andi. r7,r3,0x7
+ addi r7,r7,1
+ READ_SPD(31) /* Read DIMM rank density */
+ beq spd_read_fail
+ rlwinm r5,r3,27,29,31
+ rlwinm r6,r3,3,24,28
+ or r5,r6,r5 /* r5 = Normalized Rank Density byte */
+ lis r8, 0x0080 /* 128MB >> 4 */
+ mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
+ mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
+ neg r7,r8
+ rlwinm r7,r7,28,4,31
+ or r7,r7,r11 /* set ADDR field */
+ rlwinm r8,r8,12,20,31
+ add r11,r11,r8 /* set Base Addr for next DIMM */
+
+ cmpi 0,0,r10,SPD_DIMM0
+ bne set_dimm1_size
+ stw r7,SD_D0_BAR(r4)
+ sync
+ li r10,SPD_DIMM1
+ READ_SPD(0)
+ bne do_each_dimm
+ b spd_done
+
+set_dimm1_size:
+ stw r7,SD_D1_BAR(r4)
+ sync
+spd_done:
+ blr
+
+check_next_slot:
+ cmpi 0,0,r10,SPD_DIMM1
+ beq spd_read_fail
+ li r10,SPD_DIMM1
+ b do_first_dimm
+spd_read_fail:
+ ori r3,r0,0xdead
+ b err_hung
+spd_fail:
+ li r3,0x0bad
+ sync
+err_hung: /* hang here for debugging */
+ nop
+ nop
+ b err_hung
+
+#endif /* !SDC_HARDCODED_INIT */
--- /dev/null
+#
+# Copyright (c) 2005 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Flash address
+TEXT_BASE = 0xFF000000
+# RAM address
+#TEXT_BASE = 0x00400000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float
--- /dev/null
+/*
+ * (C) Copyright 2005 Freescale Semiconductor, Inc.
+ *
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the Tsi108 Emul Board by avb@Tundra
+ */
+
+/*
+ * board support/init functions for the
+ * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup (void *blob, bd_t *bd);
+#endif
+
+#undef DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+extern void tsi108_init_f (void);
+
+int display_mem_map (void);
+
+void after_reloc (ulong dest_addr)
+{
+ /*
+ * Jump to the main U-Boot board init code
+ */
+ board_init_r ((gd_t *) gd, dest_addr);
+ /* NOTREACHED */
+}
+
+/*
+ * Check Board Identity:
+ * report board type
+ */
+
+int checkboard (void)
+{
+ int l_type = 0;
+
+ printf ("BOARD: %s\n", CFG_BOARD_NAME);
+ return (l_type);
+}
+
+/*
+ * Read Processor ID:
+ *
+ * report calling processor number
+ */
+
+int read_pid (void)
+{
+ return 0; /* we are on single CPU platform for a while */
+}
+
+long int dram_size (int board_type)
+{
+ return 0x20000000; /* 256M bytes */
+}
+
+long int initdram (int board_type)
+{
+ return dram_size (board_type);
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup (void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup (blob, bd);
+
+ p = ft_get_prop (blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32 (bd->bi_memstart);
+ *p = cpu_to_be32 (bd->bi_memsize);
+ }
+}
+#endif
--- /dev/null
+/*****************************************************************************
+ * (C) Copyright 2003; Tundra Semiconductor Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ * FILENAME: tsi108_init.c
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Initialization code for the Tundra Tsi108 bridge chip
+ *---------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <tsi108.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void mpicInit (int verbose);
+
+/*
+ * Configuration Options
+ */
+
+typedef struct {
+ ulong upper;
+ ulong lower;
+} PB2OCN_LUT_ENTRY;
+
+PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
+ /* 0 - 7 */
+ {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
+
+ /* 8 - 15 */
+ {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
+
+ /* 16 - 23 */
+ {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
+ /* 24 - 31 */
+ {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
+
+ {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
+ {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
+ {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
+ {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
+};
+
+#ifdef CFG_CLK_SPREAD
+typedef struct {
+ ulong ctrl0;
+ ulong ctrl1;
+} PLL_CTRL_SET;
+
+/*
+ * Clock Generator SPLL0 initialization values
+ * PLL0 configuration table for various PB_CLKO freq.
+ * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
+ * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
+ */
+
+static PLL_CTRL_SET pll0_config[8] = {
+ {0x00000000, 0x00000000}, /* 0: bypass */
+ {0x00000000, 0x00000000}, /* 1: reserved */
+ {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
+ {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
+ {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
+ {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
+ {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
+ {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
+};
+#endif /* CFG_CLK_SPREAD */
+
+/*
+ * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
+ * (based on recommended Tsi108 reference clock 33MHz)
+ */
+static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
+
+/*
+ * get_board_bus_clk ()
+ *
+ * returns the bus clock in Hz.
+ */
+unsigned long get_board_bus_clk (void)
+{
+ ulong i;
+
+ /* Detect PB clock freq. */
+ i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+ i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
+
+ return pb_clk_sel[i] * 1000000;
+}
+
+/*
+ * board_early_init_f ()
+ *
+ * board-specific initialization executed from flash
+ */
+
+int board_early_init_f (void)
+{
+ ulong i;
+
+ gd->mem_clk = 0;
+ i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
+ CG_PWRUP_STATUS);
+ i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
+ switch (i) {
+ case 0: /* external clock */
+ printf ("Using external clock\n");
+ break;
+ case 1: /* system clock */
+ gd->mem_clk = gd->bus_clk;
+ break;
+ case 4: /* 133 MHz */
+ case 5: /* 166 MHz */
+ case 6: /* 200 MHz */
+ gd->mem_clk = pb_clk_sel[i] * 1000000;
+ break;
+ default:
+ printf ("Invalid DDR2 clock setting\n");
+ return -1;
+ }
+ printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
+ printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+ return 0;
+}
+
+/*
+ * board_early_init_r() - Tsi108 initialization function executed right after
+ * relocation. Contains code that cannot be executed from flash.
+ */
+
+int board_early_init_r (void)
+{
+ ulong temp, i;
+ ulong reg_val;
+ volatile ulong *reg_ptr;
+
+ reg_ptr =
+ (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
+ *reg_ptr++ = 0x00;
+ }
+
+ __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__ ("sync");
+
+ /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
+ 0x80000001);
+ __asm__ __volatile__ ("sync");
+
+ /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
+ * read from SDRAM)
+ */
+
+ temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
+ * processor bus address space. Immediately after reset LUT and address
+ * translation are disabled for this BAR. Now we have to initialize LUT
+ * and switch from the BOOT mode to the normal operation mode.
+ *
+ * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
+ * and covers 512MB of address space. To allow larger aperture we also
+ * have to relocate register window of Tsi108
+ *
+ * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
+ * mode.
+ *
+ * initialize pointer to LUT associated with PB_OCN_BAR1
+ */
+ reg_ptr =
+ (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = pb2ocn_lut1[i].lower;
+ *reg_ptr++ = pb2ocn_lut1[i].upper;
+ }
+
+ __asm__ __volatile__ ("sync");
+
+ /* Base addresses for CS0, CS1, CS2, CS3 */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
+ 0x00000000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
+ 0x00100000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
+ 0x00200000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
+ 0x00300000);
+ __asm__ __volatile__ ("sync");
+
+ /* Masks for HLP banks */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ /* Set CTRL0 values for banks */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
+ 0x7FFC44C2);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
+ 0x7FFC44C0);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
+ 0x7FFC44C0);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
+ 0x7FFC44C2);
+ __asm__ __volatile__ ("sync");
+
+ /* Set banks to latched mode, enabled, and other default settings */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
+ * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
+ */
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
+ 0xE0000011);
+ __asm__ __volatile__ ("sync");
+
+ /* Make sure that OCN_BAR2 decoder is set (to allow following
+ * immediate read from SDRAM)
+ */
+
+ temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * SRI: At this point we have enabled the HLP banks. That means we can
+ * now read from the NVRAM and initialize the environment variables.
+ * We will over-ride the env_init called in board_init_f
+ * This is really a work-around because, the HLP bank 1
+ * where NVRAM resides is not visible during board_init_f
+ * (lib_ppc/board.c)
+ * Alternatively, we could use the I2C EEPROM at start-up to configure
+ * and enable all HLP banks and not just HLP 0 as is being done for
+ * Taiga Rev. 2.
+ */
+
+ env_init ();
+
+#ifndef DISABLE_PBM
+
+ /*
+ * For IBM processors we have to set Address-Only commands generated
+ * by PBM that are different from ones set after reset.
+ */
+
+ temp = get_cpu_type ();
+
+ if ((CPU_750FX == temp) || (CPU_750GX == temp))
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
+ 0x00009955);
+#endif /* DISABLE_PBM */
+
+#ifdef CONFIG_PCI
+ /*
+ * Initialize PCI/X block
+ */
+
+ /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+ PCI_PFAB_BAR0_UPPER, 0);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
+ 0xFB000001);
+ __asm__ __volatile__ ("sync");
+
+ /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
+
+ temp = in32(CFG_TSI108_CSR_BASE +
+ TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
+
+ temp &= ~0xFF00; /* Clear the BUS_NUM field */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
+ temp);
+
+ /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
+ 0);
+ __asm__ __volatile__ ("sync");
+
+ /* This register is on the PCI side to interpret the address it receives
+ * and maps it as a IO address.
+ */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
+ 0xFA000001);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Map PCI/X Memory Space
+ *
+ * Transactions directed from OCM to PCI Memory Space are directed
+ * from PB to PCI
+ * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
+ * If address remapping is required the corresponding PCI_PFAB_MEM32
+ * and PCI_PFAB_PFMx register groups have to be configured.
+ *
+ * Map the path from the PCI/X bus into the system memory
+ *
+ * The memory mapped window assotiated with PCI P2O_BAR2 provides
+ * access to the system memory without address remapping.
+ * All system memory is opened for accesses initiated by PCI/X bus
+ * masters.
+ *
+ * Initialize LUT associated with PCI P2O_BAR2
+ *
+ * set pointer to LUT associated with PCI P2O_BAR2
+ */
+
+ reg_ptr =
+ (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
+
+#ifdef DISABLE_PBM
+
+ /* In case when PBM is disabled (no HW supported cache snoopng on PB)
+ * P2O_BAR2 is directly mapped into the system memory without address
+ * translation.
+ */
+
+ reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
+ *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
+ }
+
+ /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
+ reg_val = 0x00007500;
+#else
+
+ reg_val = 0x00000002; /* Destination port = PBM */
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
+/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
+ *reg_ptr++ = 0x40000000;
+/* offset = 16MB, address translation is enabled to allow byte swapping */
+ reg_val += 0x01000000;
+ }
+
+/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
+ reg_val = 0x00007100;
+#endif
+
+ __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+ reg_val);
+ __asm__ __volatile__ ("sync");
+
+ /* Set 64-bit PCI bus address for system memory
+ * ( 0 is the best choice for easy mapping)
+ */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
+ 0x00000000);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
+ 0x00000000);
+ __asm__ __volatile__ ("sync");
+
+#ifndef DISABLE_PBM
+ /*
+ * The memory mapped window assotiated with PCI P2O_BAR3 provides
+ * access to the system memory using SDRAM OCN port and address
+ * translation. This is alternative way to access SDRAM from PCI
+ * required for Tsi108 emulation testing.
+ * All system memory is opened for accesses initiated by
+ * PCI/X bus masters.
+ *
+ * Initialize LUT associated with PCI P2O_BAR3
+ *
+ * set pointer to LUT associated with PCI P2O_BAR3
+ */
+ reg_ptr =
+ (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
+
+ reg_val = 0x00000004; /* Destination port = SDC */
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
+
+/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
+ *reg_ptr++ = 0;
+
+/* offset = 16MB, address translation is enabled to allow byte swapping */
+ reg_val += 0x01000000;
+ }
+
+ __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__ ("sync");
+
+ /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
+
+ reg_val =
+ in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+ PCI_P2O_PAGE_SIZES);
+ reg_val &= ~0x00FF;
+ reg_val |= 0x0071;
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+ reg_val);
+ __asm__ __volatile__ ("sync");
+
+ /* Set 64-bit base PCI bus address for window (0x20000000) */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
+ 0x00000000);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
+ 0x20000000);
+ __asm__ __volatile__ ("sync");
+
+#endif /* !DISABLE_PBM */
+
+#ifdef ENABLE_PCI_CSR_BAR
+ /* open if required access to Tsi108 CSRs from the PCI/X bus */
+ /* enable BAR0 on the PCI/X bus */
+ reg_val = in32(CFG_TSI108_CSR_BASE +
+ TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
+ reg_val |= 0x02;
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
+ reg_val);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
+ 0x00000000);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
+ CFG_TSI108_CSR_BASE);
+ __asm__ __volatile__ ("sync");
+
+#endif
+
+ /*
+ * Finally enable PCI/X Bus Master and Memory Space access
+ */
+
+ reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
+ reg_val |= 0x06;
+ out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
+ __asm__ __volatile__ ("sync");
+
+#endif /* CONFIG_PCI */
+
+ /*
+ * Initialize MPIC outputs (interrupt pins):
+ * Interrupt routing on the Grendel Emul. Board:
+ * PB_INT[0] -> INT (CPU0)
+ * PB_INT[1] -> INT (CPU1)
+ * PB_INT[2] -> MCP (CPU0)
+ * PB_INT[3] -> MCP (CPU1)
+ * Set interrupt controller outputs as Level_Sensitive/Active_Low
+ */
+ out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Ensure that Machine Check exception is enabled
+ * We need it to support PCI Bus probing (configuration reads)
+ */
+
+ reg_val = mfmsr ();
+ mtmsr(reg_val | MSR_ME);
+
+ return 0;
+}
+
+/*
+ * Needed to print out L2 cache info
+ * used in the misc_init_r function
+ */
+
+unsigned long get_l2cr (void)
+{
+ unsigned long l2controlreg;
+ asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
+ return l2controlreg;
+}
+
+/*
+ * misc_init_r()
+ *
+ * various things to do after relocation
+ *
+ */
+
+int misc_init_r (void)
+{
+#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
+ ulong i;
+
+ /* Ensure that Spread-Spectrum is disabled */
+ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
+
+ /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
+ * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
+ */
+
+ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+ 0x002e0044); /* D = 0.25% */
+ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
+ 0x00000039); /* BWADJ */
+
+ /* Initialize PLL0: CG_PB_CLKO */
+ /* Detect PB clock freq. */
+ i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+ i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
+
+ out32 (CFG_TSI108_CSR_BASE +
+ TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
+ out32 (CFG_TSI108_CSR_BASE +
+ TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
+
+ /* Wait and set SSEN for both PLL0 and 1 */
+ udelay (1000);
+ out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+ 0x802e0044); /* D=0.25% */
+ out32 (CFG_TSI108_CSR_BASE +
+ TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
+ 0x80000000 | pll0_config[i].ctrl0);
+#endif /* CFG_CLK_SPREAD */
+
+#ifdef CFG_L2
+ l2cache_enable ();
+#endif
+ printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
+ printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+
+ /*
+ * All the information needed to print the cache details is avaiblable
+ * at this point i.e. above call to l2cache_enable is the very last
+ * thing done with regards to enabling diabling the cache.
+ * So this seems like a good place to print all this information
+ */
+
+ printf ("CACHE: ");
+ switch (get_cpu_type()) {
+ case CPU_7447A:
+ printf ("L1 Instruction cache - 32KB 8-way");
+ (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("L1 Data cache - 32KB 8-way");
+ (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("Unified L2 cache - 512KB 8-way");
+ (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("\n");
+ break;
+
+ case CPU_7448:
+ printf ("L1 Instruction cache - 32KB 8-way");
+ (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("L1 Data cache - 32KB 8-way");
+ (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("Unified L2 cache - 1MB 8-way");
+ (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/74xx_7xx/start.o (.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/* . = env_offset; */
+/* common/environment.o(.text) */
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Re-written to support multi-bank flash SIMMs.
+ * Added support for real protection and JFFS2.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT 0x89898989
+#define INTEL_ALT 0xB0B0B0B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x10101010
+#define INTEL_ERASE 0x20202020
+#define INTEL_CLEAR 0x50505050
+#define INTEL_LOCKBIT 0x60606060
+#define INTEL_PROTECT 0x01010101
+#define INTEL_STATUS 0x70707070
+#define INTEL_READID 0x90909090
+#define INTEL_CONFIRM 0xD0D0D0D0
+#define INTEL_RESET 0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x80808080
+#define INTEL_OK 0x80808080
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
+ * Up to 32MB of flash supported (up to 4 banks.)
+ * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
+ *
+ * The following code can not run from flash!
+ */
+unsigned long flash_init (void)
+{
+ ulong size = 0, sect_start, sect_size = 0, bank_size;
+ ushort sect_count = 0;
+ int i, j, nbanks;
+ vu_long *addr = (vu_long *)CFG_FLASH_BASE;
+ vu_long *bcsr = (vu_long *)CFG_BCSR;
+
+ switch (bcsr[2] & 0xF) {
+ case 0:
+ nbanks = 4;
+ break;
+ case 1:
+ nbanks = 2;
+ break;
+ case 2:
+ nbanks = 1;
+ break;
+ default: /* Unsupported configurations */
+ nbanks = CFG_MAX_FLASH_BANKS;
+ }
+
+ if (nbanks > CFG_MAX_FLASH_BANKS)
+ nbanks = CFG_MAX_FLASH_BANKS;
+
+ for (i = 0; i < nbanks; i++) {
+ *addr = INTEL_READID; /* Read Intelligent Identifier */
+ if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
+ switch (addr[1]) {
+ case SHARP_ID_28F016SCL:
+ case SHARP_ID_28F016SCZ:
+ flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ sect_count = 32;
+ sect_size = 0x40000;
+ break;
+ default:
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ sect_count = CFG_MAX_FLASH_SECT;
+ sect_size =
+ CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
+ }
+ }
+ else
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
+ addr[0], addr[1], (ulong)addr);
+ size = 0;
+ *addr = INTEL_RESET; /* Reset bank to Read Array mode */
+ break;
+ }
+ flash_info[i].sector_count = sect_count;
+ flash_info[i].size = bank_size = sect_size * sect_count;
+ size += bank_size;
+ sect_start = (ulong)addr;
+ for (j = 0; j < sect_count; j++) {
+ addr = (vu_long *)sect_start;
+ flash_info[i].start[j] = sect_start;
+ flash_info[i].protect[j] = (addr[2] == 0x01010101);
+ sect_start += sect_size;
+ }
+ *addr = INTEL_RESET; /* Reset bank to Read Array mode */
+ addr = (vu_long *)sect_start;
+ }
+
+ if (size == 0) { /* Unknown flash, fill with hard-coded values */
+ sect_start = CFG_FLASH_BASE;
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
+ flash_info[i].sector_count = sect_count;
+ for (j = 0; j < sect_count; j++) {
+ flash_info[i].start[j] = sect_start;
+ flash_info[i].protect[j] = 0;
+ sect_start += sect_size;
+ }
+ }
+ size = CFG_FLASH_SIZE;
+ }
+ else
+ for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].size = 0;
+ flash_info[i].sector_count = 0;
+ }
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Clear Status Register */
+ *addr = INTEL_CLEAR;
+ /* Single Block Erase Command */
+ *addr = INTEL_ERASE;
+ /* Confirm */
+ *addr = INTEL_CONFIRM;
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = INTEL_CONFIRM;
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = INTEL_RESET; /* reset bank */
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ if (*addr != INTEL_OK) {
+ printf("Block erase failed at %08X, CSR=%08X\n",
+ (uint)addr, (uint)*addr);
+ *addr = INTEL_RESET; /* reset bank */
+ return 1;
+ }
+
+ /* reset to read mode */
+ *addr = INTEL_RESET;
+ }
+ }
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ ulong start;
+ int rc = 0;
+ int flag;
+ vu_long *addr = (vu_long *)dest;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+
+ *addr = INTEL_CLEAR; /* Clear status register */
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = INTEL_PROGRAM;
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ printf("Write timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+ if (*addr != INTEL_OK) {
+ printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
+ rc = 1;
+ }
+
+ *addr = INTEL_RESET; /* Reset to read array mode */
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ rc = write_word(info, wp, data);
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ ulong start;
+ int i;
+ int rc = 0;
+ vu_long *addr = (vu_long *)(info->start[sector]);
+ int flag = disable_interrupts();
+
+ *addr = INTEL_CLEAR; /* Clear status register */
+ if (prot) { /* Set sector lock bit */
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ }
+ else { /* Clear sector lock bit */
+ *addr = INTEL_LOCKBIT; /* All sectors lock bits */
+ *addr = INTEL_CONFIRM; /* clear */
+ }
+
+ start = get_timer(0);
+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+ if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+ printf("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+
+ if (*addr != INTEL_OK) {
+ printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+ (uint)addr, (uint)*addr);
+ rc = 1;
+ }
+
+ if (!rc)
+ info->protect[sector] = prot;
+
+ /*
+ * Clear lock bit command clears all sectors lock bits, so
+ * we have to restore lock bits of protected sectors.
+ */
+ if (!prot)
+ for (i = 0; i < info->sector_count; i++)
+ if (info->protect[i]) {
+ addr = (vu_long *)(info->start[i]);
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ udelay(CFG_FLASH_LOCK_TOUT * 1000);
+ }
+
+ if (flag)
+ enable_interrupts();
+
+ *addr = INTEL_RESET; /* Reset to read array mode */
+
+ return rc;
+}
--- /dev/null
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * (C) Copyright 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
+ /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
+ /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
+ /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
+ /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
+ /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
+ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
+ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
+ /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
+ /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
+ /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
+ /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
+ /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
+ /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
+ /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
+ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
+ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
+ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
+ /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
+ /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
+ /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
+ /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+#if CONFIG_ADSTYPE == CFG_8272ADS
+ /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
+ /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
+#else
+ /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
+ /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
+ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+#if CONFIG_ADSTYPE == CFG_8272ADS
+ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
+#else
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+ /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
+ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+void reset_phy (void)
+{
+ vu_long *bcsr = (vu_long *)CFG_BCSR;
+
+ /* Reset the PHY */
+#if CFG_PHY_ADDR == 0
+ bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
+ udelay(2);
+ bcsr[1] |= FETH1_RST;
+#else
+ bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
+ udelay(2);
+ bcsr[3] |= FETH2_RST;
+#endif /* CFG_PHY_ADDR == 0 */
+ udelay(1000);
+#ifdef CONFIG_MII
+#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+ /*
+ * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
+ * Enable autonegotiation.
+ */
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#else
+ /*
+ * Ethernet PHY is configured (by means of configuration pins)
+ * to work at 10Mb/s only. We reconfigure it using MII
+ * to advertise all capabilities, including 100Mb/s, and
+ * restart autonegotiation.
+ */
+
+ /* Advertise all capabilities */
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
+
+ /* Do not bypass Rx/Tx (de)scrambler */
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
+
+ bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#endif /* CONFIG_MII */
+}
+
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+ unsigned long pci_int_stat;
+ unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
+int board_early_init_f (void)
+{
+ vu_long *bcsr = (vu_long *)CFG_BCSR;
+
+#ifdef CONFIG_PCI
+ volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
+
+ /* mask alll the PCI interrupts */
+ pci_ic->pci_int_mask |= 0xfff00000;
+#endif
+#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
+ bcsr[1] &= ~RS232EN_1;
+#endif
+#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
+ bcsr[1] &= ~RS232EN_2;
+#endif
+
+#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+ if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+ {
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+ immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+ immap->im_siu_conf.sc_siumcr =
+ (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+ | SIUMCR_LBPC01;
+ }
+#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
+
+ return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+ long int msize = 32;
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+ long int msize = 64;
+#else
+ long int msize = 16;
+#endif
+
+#ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ volatile uchar *ramaddr, c = 0xff;
+ uint or;
+ uint psdmr;
+ uint psrt;
+
+ int i;
+
+ immap->im_siu_conf.sc_ppc_acr = 0x00000002;
+ immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+ immap->im_siu_conf.sc_tescr1 = 0x00004000;
+
+ memctl->memc_mptpr = CFG_MPTPR;
+#ifdef CFG_LSDRAM_BASE
+ /*
+ Initialise local bus SDRAM only if the pins
+ are configured as local bus pins and not as PCI.
+ The configuration is determined by the HRCW.
+ */
+ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
+ memctl->memc_lsrt = CFG_LSRT;
+#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
+ memctl->memc_or3 = 0xFF803280;
+ memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
+#else /* CS4 */
+ memctl->memc_or4 = 0xFFC01480;
+ memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+ memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
+ ramaddr = (uchar *) CFG_LSDRAM_BASE;
+ *ramaddr = c;
+ memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+ memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+ *ramaddr = c;
+ memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+ }
+#endif /* CFG_LSDRAM_BASE */
+
+ /* Init 60x bus SDRAM */
+#ifdef CONFIG_SPD_EEPROM
+ {
+ spd_eeprom_t spd;
+ uint pbi, bsel, rowst, lsb, tmp;
+
+ i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
+
+ /* Bank-based interleaving is not supported for physical bank
+ sizes greater than 128MB which is encoded as 0x20 in SPD
+ */
+ pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
+ msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
+ or = ~(msize - 1) << 20; /* SDAM */
+ switch (spd.nbanks) { /* BPD */
+ case 2:
+ bsel = 1;
+ break;
+ case 4:
+ bsel = 2;
+ or |= 0x00002000;
+ break;
+ case 8:
+ bsel = 3;
+ or |= 0x00004000;
+ break;
+ }
+ lsb = 3; /* For 64-bit port, lsb is 3 bits */
+
+ if (pbi) { /* Bus partition depends on interleaving */
+ rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
+ or |= (rowst << 9); /* ROWST */
+ } else {
+ rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
+ or |= ((rowst * 2 - 12) << 9); /* ROWST */
+ }
+ or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
+
+ psdmr = (pbi << 31); /* PBI */
+ /* Bus multiplexing parameters */
+ tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
+ psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
+ psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
+
+ tmp = (31 - lsb - 10) - tmp;
+ /* Pin connected to SDA10 is (31 - lsb - 10).
+ rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
+ so (rowst + tmp) alternates with AP.
+ */
+ if (pbi) /* Table 10-7 */
+ psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
+ else
+ psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
+
+ /* SDRAM device-specific parameters */
+ tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
+ switch (tmp) { /* RFRC */
+ case 1:
+ case 2:
+ psdmr |= (1 << 15);
+ break;
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ psdmr |= ((tmp - 2) << 15);
+ break;
+ default:
+ psdmr |= (7 << 15);
+ }
+ psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
+ psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
+ /* BL=0 because for 64-bit SDRAM burst length must be 4 */
+ /* LDOTOPRE ??? */
+ for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
+ tmp >>= 1;
+ switch (i) { /* WRC */
+ case 0:
+ case 1:
+ psdmr |= (1 << 4);
+ break;
+ case 2:
+ case 3:
+ psdmr |= (i << 4);
+ break;
+ }
+ /* EAMUX=0 - no external address multiplexing */
+ /* BUFCMD=0 - no external buffers */
+ for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
+ tmp >>= 1;
+ psdmr |= i; /* CL */
+
+ switch (spd.refresh & 0x7F) {
+ case 1:
+ tmp = 3900;
+ break;
+ case 2:
+ tmp = 7800;
+ break;
+ case 3:
+ tmp = 31300;
+ break;
+ case 4:
+ tmp = 62500;
+ break;
+ case 5:
+ tmp = 125000;
+ break;
+ default:
+ tmp = 15625;
+ }
+ psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
+ ((memctl->memc_mptpr >> 8) + 1)) - 1;
+#ifdef SPD_DEBUG
+ printf ("\nDIMM type: %-18.18s\n", spd.mpart);
+ printf ("SPD size: %d\n", spd.info_size);
+ printf ("EEPROM size: %d\n", 1 << spd.chip_size);
+ printf ("Memory type: %d\n", spd.mem_type);
+ printf ("Row addr: %d\n", spd.nrow_addr);
+ printf ("Column addr: %d\n", spd.ncol_addr);
+ printf ("# of rows: %d\n", spd.nrows);
+ printf ("Row density: %d\n", spd.row_dens);
+ printf ("# of banks: %d\n", spd.nbanks);
+ printf ("Data width: %d\n",
+ 256 * spd.dataw_msb + spd.dataw_lsb);
+ printf ("Chip width: %d\n", spd.primw);
+ printf ("Refresh rate: %02X\n", spd.refresh);
+ printf ("CAS latencies: %02X\n", spd.cas_lat);
+ printf ("Write latencies: %02X\n", spd.write_lat);
+ printf ("tRP: %d\n", spd.trp);
+ printf ("tRCD: %d\n", spd.trcd);
+
+ printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
+#endif /* SPD_DEBUG */
+ }
+#else /* !CONFIG_SPD_EEPROM */
+ or = CFG_OR2;
+ psdmr = CFG_PSDMR;
+ psrt = CFG_PSRT;
+#endif /* CONFIG_SPD_EEPROM */
+ memctl->memc_psrt = psrt;
+ memctl->memc_or2 = or;
+ memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
+ ramaddr = (uchar *) CFG_SDRAM_BASE;
+ memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
+ *ramaddr = c;
+ memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
+ *ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+ /* return total 60x bus SDRAM size */
+ return (msize * 1024 * 1024);
+}
+
+int checkboard (void)
+{
+#if CONFIG_ADSTYPE == CFG_8260ADS
+ puts ("Board: Motorola MPC8260ADS\n");
+#elif CONFIG_ADSTYPE == CFG_8266ADS
+ puts ("Board: Motorola MPC8266ADS\n");
+#elif CONFIG_ADSTYPE == CFG_PQ2FADS
+ puts ("Board: Motorola PQ2FADS-ZU\n");
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+ puts ("Board: Motorola MPC8272ADS\n");
+#else
+ puts ("Board: unknown\n");
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc8250_init(&hose);
+}
+#endif
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8260ads board
+#
+
+TEXT_BASE = 0xfe000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifndef CONFIG_MPC8266ADS
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
+#endif
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+#ifndef CONFIG_MPC8266ADS
+ bcsr->bd_ctrl |= BD_CTRL_FLWE;
+#endif
+
+
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+#ifndef CONFIG_MPC8266ADS
+ /* Remap FLASH according to real size */
+ memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+ (memctl->memc_br1 & ~(BR_BA_MSK));
+#endif
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+
+ value = addr[0] & 0x00FF00FF;
+ switch (value) {
+ case MT_MANUFACT: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+ case (INTEL_ID_28F016S):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F160S3):
+ info->flash_id += FLASH_28F160S3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F320S3):
+ info->flash_id += FLASH_28F320S3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ sector_offset = 0x20000;
+ break; /* => 2x4 MB */
+
+ case SHARP_ID_28F016SCL:
+ case SHARP_ID_28F016SCZ:
+ info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ info->sector_count = 32;
+ info->size = 0x00800000;
+ sector_offset = 0x40000;
+ break; /* => 4x2 MB */
+
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+ while ((*addr & 0x80808080) != 0x80808080) {
+ if(*addr & 0x20202020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ }
+ }
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+ while (((csr = *addr) & 0x80808080) != 0x80808080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ /* Clear Status Register */
+ *addr = 0x50505050;
+
+ *addr = 0x60606060;
+ *addr = 0xd0d0d0d0;
+
+ start = get_timer (0);
+ while(*addr != 0x80808080){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ return 1;
+ }
+ }
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <i2c.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * PBI Page Based Interleaving
+ * PSDMR_PBI page based interleaving
+ * 0 bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ * (this can help with marginal board layouts)
+ * PSDMR_EAMUX adds a clock
+ * 0 no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ * PSDMR_BUFCMD adds a clock
+ * 0 no extra clock
+ */
+#define CONFIG_PBI 0
+#define PESSIMISTIC_SDRAM 0
+#define EAMUX 0 /* EST requires EAMUX */
+#define BUFCMD 0
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+typedef struct bscr_ {
+ unsigned long bcsr0;
+ unsigned long bcsr1;
+ unsigned long bcsr2;
+ unsigned long bcsr3;
+ unsigned long bcsr4;
+ unsigned long bcsr5;
+ unsigned long bcsr6;
+ unsigned long bcsr7;
+} bcsr_t;
+
+typedef struct pci_ic_s {
+ unsigned long pci_int_stat;
+ unsigned long pci_int_mask;
+} pci_ic_t;
+
+void reset_phy(void)
+{
+ volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
+
+ /* reset the FEC port */
+ bcsr->bcsr1 &= ~FETH_RST;
+ bcsr->bcsr1 |= FETH_RST;
+}
+
+
+int board_early_init_f (void)
+{
+ volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
+ volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT;
+
+ bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
+
+ /* mask all PCI interrupts */
+ pci_ic->pci_int_mask |= 0xfff00000;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts ("Board: Motorola MPC8266ADS\n");
+ return 0;
+}
+
+long int initdram(int board_type)
+{
+ /* Autoinit part stolen from board/sacsng/sacsng.c */
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ volatile uchar c = 0xff;
+ volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
+ uint psdmr = CFG_PSDMR;
+ int i;
+
+ uint psrt = 0x21; /* for no SPD */
+ uint chipselects = 1; /* for no SPD */
+ uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
+ uint or = CFG_OR2_PRELIM; /* for no SPD */
+ uint data_width;
+ uint rows;
+ uint banks;
+ uint cols;
+ uint caslatency;
+ uint width;
+ uint rowst;
+ uint sdam;
+ uint bsma;
+ uint sda10;
+ u_char spd_size;
+ u_char data;
+ u_char cksum;
+ int j;
+
+ /* Keep the compiler from complaining about potentially uninitialized vars */
+ data_width = rows = banks = cols = caslatency = 0;
+
+ /*
+ * Read the SDRAM SPD EEPROM via I2C.
+ */
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+ spd_size = data;
+ cksum = data;
+ for(j = 1; j < 64; j++)
+ { /* read only the checksummed bytes */
+ /* note: the I2C address autoincrements when alen == 0 */
+ i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+ /*printf("addr %d = 0x%02x\n", j, data);*/
+ if(j == 5) chipselects = data & 0x0F;
+ else if(j == 6) data_width = data;
+ else if(j == 7) data_width |= data << 8;
+ else if(j == 3) rows = data & 0x0F;
+ else if(j == 4) cols = data & 0x0F;
+ else if(j == 12)
+ {
+ /*
+ * Refresh rate: this assumes the prescaler is set to
+ * approximately 0.39uSec per tick and the target refresh period
+ * is about 85% of maximum.
+ */
+ switch(data & 0x7F)
+ {
+ default:
+ case 0: psrt = 0x21; /* 15.625uS */ break;
+ case 1: psrt = 0x07; /* 3.9uS */ break;
+ case 2: psrt = 0x0F; /* 7.8uS */ break;
+ case 3: psrt = 0x43; /* 31.3uS */ break;
+ case 4: psrt = 0x87; /* 62.5uS */ break;
+ case 5: psrt = 0xFF; /* 125uS */ break;
+ }
+ }
+ else if(j == 17) banks = data;
+ else if(j == 18)
+ {
+ caslatency = 3; /* default CL */
+# if(PESSIMISTIC_SDRAM)
+ if((data & 0x04) != 0) caslatency = 3;
+ else if((data & 0x02) != 0) caslatency = 2;
+ else if((data & 0x01) != 0) caslatency = 1;
+# else
+ if((data & 0x01) != 0) caslatency = 1;
+ else if((data & 0x02) != 0) caslatency = 2;
+ else if((data & 0x04) != 0) caslatency = 3;
+# endif
+ else
+ {
+ printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+ data);
+ }
+ }
+ else if(j == 63)
+ {
+ if(data != cksum)
+ {
+ printf ("WARNING: Configuration data checksum failure:"
+ " is 0x%02x, calculated 0x%02x\n",
+ data, cksum);
+ }
+ }
+ cksum += data;
+ }
+
+ /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+ if(caslatency < 2) {
+ printf("CL was %d, forcing to 2\n", caslatency);
+ caslatency = 2;
+ }
+ if(rows > 14) {
+ printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+ rows = 14;
+ }
+ if(cols > 11) {
+ printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+ cols = 11;
+ }
+
+ if((data_width != 64) && (data_width != 72))
+ {
+ printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+ data_width);
+ }
+ width = 3; /* 2^3 = 8 bytes = 64 bits wide */
+ /*
+ * Convert banks into log2(banks)
+ */
+ if (banks == 2) banks = 1;
+ else if(banks == 4) banks = 2;
+ else if(banks == 8) banks = 3;
+
+
+ sdram_size = 1 << (rows + cols + banks + width);
+ /* hack for high density memory (512MB per CS) */
+ /* !!!!! Will ONLY work with Page Based Interleave !!!!!
+ ( PSDMR[PBI] = 1 )
+ */
+ /* mamory actually has 11 column addresses, but the memory controller
+ doesn't really care.
+ the calculations that follow will however move the rows so that
+ they are muxed one bit off if you use 11 bit columns.
+ The solution is to tell the memory controller the correct size of the memory
+ but change the number of columns to 10 afterwards.
+ The 11th column addre will still be mucxed correctly onto the bus.
+
+ Also be aware that the MPC8266ADS board Rev B has not connected
+ Row addres 13 to anything.
+
+ The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
+ */
+ if (cols > 10)
+ cols = 10;
+
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+ rowst = 32 - (rows + banks + cols + width);
+#endif
+
+ or = ~(sdram_size - 1) | /* SDAM address mask */
+ ((banks-1) << 13) | /* banks per device */
+ (rowst << 9) | /* rowst */
+ ((rows - 9) << 6); /* numr */
+
+
+ /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
+
+ /*
+ * SDAM specifies the number of columns that are multiplexed
+ * (reference AN2165/D), defined to be (columns - 6) for page
+ * interleave, (columns - 8) for bank interleave.
+ *
+ * BSMA is 14 - max(rows, cols). The bank select lines come
+ * into play above the highest "address" line going into the
+ * the SDRAM.
+ */
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ sdam = cols - 8;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam + 2;
+#else
+ sdam = cols + banks - 8;
+ bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+ sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+ psdmr = (CONFIG_PBI |\
+ PSDMR_RFEN |\
+ PSDMR_RFRC_16_CLK |\
+ PSDMR_PRETOACT_8W |\
+ PSDMR_ACTTORW_8W |\
+ PSDMR_WRC_4C |\
+ PSDMR_EAMUX |\
+ PSDMR_BUFCMD) |\
+ caslatency |\
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
+ (sdam << 24) |\
+ (bsma << 21) |\
+ (sda10 << 18);
+#else
+ psdmr = (CONFIG_PBI |\
+ PSDMR_RFEN |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
+ PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
+ PSDMR_WRC_1C | /* 1 clock + 7nSec */
+ EAMUX |\
+ BUFCMD) |\
+ caslatency |\
+ ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
+ (sdam << 24) |\
+ (bsma << 21) |\
+ (sda10 << 18);
+#endif
+ /*printf("psdmr = 0x%08x\n", psdmr);*/
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * Quote from Micron MT48LC8M16A2 data sheet:
+ *
+ * "...the SDRAM requires a 100uS delay prior to issuing any
+ * command other than a COMMAND INHIBIT or NOP. Starting at some
+ * point during this 100uS period and continuing at least through
+ * the end of this period, COMMAND INHIBIT or NOP commands should
+ * be applied."
+ *
+ * "Once the 100uS delay has been satisfied with at least one COMMAND
+ * INHIBIT or NOP command having been applied, a /PRECHARGE command/
+ * should be applied. All banks must then be precharged, thereby
+ * placing the device in the all banks idle state."
+ *
+ * "Once in the idle state, /two/ AUTO REFRESH cycles must be
+ * performed. After the AUTO REFRESH cycles are complete, the
+ * SDRAM is ready for mode register programming."
+ *
+ * (/emphasis/ mine, gvb)
+ *
+ * The way I interpret this, Micron start up sequence is:
+ * 1. Issue a PRECHARGE-BANK command (initial precharge)
+ * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+ * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+ * 4. Issue a MODE-SET command to initialize the mode register
+ *
+ * --------
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ */
+
+ memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psrt = psrt;
+
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+ memctl->memc_or2 = or;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+
+ /*
+ * Do it a second time for the second set of chips if the DIMM has
+ * two chip selects (double sided).
+ */
+ if(chipselects > 1)
+ {
+ ramaddr += sdram_size;
+
+ memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+ memctl->memc_or3 = or;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+ for (i = 0; i < 8; i++)
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+ *ramaddr = c;
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+ *ramaddr = c;
+ }
+
+ /* print info */
+ printf("SDRAM configuration read from SPD\n");
+ printf("\tSize per side = %dMB\n", sdram_size >> 20);
+ printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
+ printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ printf(", Using Bank Based Interleave\n");
+#else
+ printf(", Using Page Based Interleave\n");
+#endif
+ printf("\tTotal size: ");
+
+ /* this delay only needed for original 16MB DIMM...
+ * Not needed for any other memory configuration */
+ if ((sdram_size * chipselects) == (16 *1024 *1024))
+ udelay (250000);
+ return (sdram_size * chipselects);
+ /*return (16 * 1024 * 1024);*/
+}
+
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc8250_init(&hose);
+}
+#endif
+++ /dev/null
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o tsi108_init.o
-SOBJS := asm_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-.PHONY: distclean
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude ($obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2004-05; Tundra Semiconductor Corp.
- *
- * Added automatic detect of SDC settings
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- * Maintainer tie-fei.zang@freescale.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * FILENAME: asm_init.s
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Initialization code for the Tundra Tsi108 bridge chip
- *
- */
-
-#include <config.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-#include <asm/processor.h>
-
-#include <tsi108.h>
-
-/*
- * Build Configuration Options
- */
-
-/* #define DISABLE_PBM disables usage of PB Master */
-/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
-/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
-
-/*
- * Hardcoded SDC settings
- */
-
-#ifdef SDC_HARDCODED_INIT
-
-/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
-
-#define VAL_SD_REFRESH (0x61A)
-#define VAL_SD_TIMING (0x0308336b)
-#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
-#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
-#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
-#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
-
-#endif /* SDC_HARDCODED_INIT */
-
-/*
- CPU Configuration:
-
- CPU Address and Data Parity enables.
-
-#define CPU_AP
-#define CPU_DP
-*/
-
-/*
- * Macros
- * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
- * expected to work correctly for the CSR space within 32KB range.
- *
- * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
- * These macros are absolutely identical except their names. This difference
- * is provided intentionally for better readable code.
- */
-
-#define LOAD_PTR(reg,const32) \
- addis reg,r0,const32@h; ori reg,reg,const32@l
-
-#define LOAD_U32(reg,const32) \
- addis reg,r0,const32@h; ori reg,reg,const32@l
-
-/* LOADMEM initializes a register with the contents of a specified 32-bit
- * memory location, usually a CSR value.
- */
-
-#define LOAD_MEM(reg,addr32) \
- addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
-
-#ifndef SDC_HARDCODED_INIT
-sdc_clk_sync:
- /* MHz: 0,0,183,100,133,167,200,233 */
- .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
-#endif
-
-/*
- * board_asm_init() - early initialization function. Coded to be portable to
- * dual-CPU configuration.
- * Checks CPU number and performs board HW initialization if called for CPU0.
- * Registers used: r3,r4,r5,r6,r19,r29
- *
- * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
- * and the rest of the board. Current implementation demonstrates two
- * possible ways to identify CPU number:
- * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
- * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
- */
-
- .globl board_asm_init
-board_asm_init:
- mflr r19 /* Save LR to be able return later. */
- bl icache_enable /* Enable icache to reduce reads from flash. */
-
-/* Initialize pointer to Tsi108 register space */
-
- LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
- ori r4,r29,TSI108_PB_REG_OFFSET
-
-/* Check Processor Version Number */
-
- mfspr r3, PVR
- rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
-
- cmpli 0,0,r3,0x8000 /* MPC74xx */
- bne cont_brd_init
-
- /*
- * For MPC744x/5x enable extended BATs[4-7]
- * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
- * to disable prefetch
- */
-
- mfspr r5, HID0
- oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
- ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
- mtspr HID0, r5
- isync
- sync
-
- /* Adding code to disable external interventions in MPX bus mode */
- mfspr r3, 1014
- oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
- mtspr 1014, r3
- isync
- sync
-
- /* Sri: code to enable FP unit */
- mfmsr r3
- ori r3, r3, 0x2000
- mtmsr r3
- isync
- sync
-
- /* def CONFIG_DUAL_CPU
- * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
- */
-#if(1)
- mfspr r3,1014 /* read MSSCR0 */
- rlwinm. r3,r3,27,31,31 /* get processor ID number */
- mtspr SPRN_PIR,r3 /* Save CPU ID */
- sync
- bne init_done
- b do_tsi108_init
-
-cont_brd_init:
-
- /* An alternative method of checking the processor number (in addition
- * to configuration using MSSCR0[ID] bit on MPC74xx).
- * Good for IBM PPC750FX/GX.
- */
-
- lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
- rlwinm. r3,r3,24,31,31 /* get processor ID number */
- bne init_done
-#else
-
-cont_brd_init:
-
-#endif /* CONFIG_DUAL_CPU */
-
- /* Initialize Tsi108 chip */
-
-do_tsi108_init:
-
- /*
- * Adjust HLP/Flash parameters. By default after reset the HLP port is
- * set to support slow devices. Better performance can be achived when
- * an optimal parameters are used for specific EPROM device.
- * NOTE: This should be performed ASAP for the emulation platform
- * because it has 5MHz HLP clocking.
- */
-
-#ifdef CONFIG_TSI108EMU
- ori r4,r29,TSI108_HLP_REG_OFFSET
- LOAD_U32(r5,0x434422c0)
- stw r5,0x08(r4) /* set HLP B0_CTRL0 */
- sync
- LOAD_U32(r5,0xd0012000)
- stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
- sync
-#endif
-
- /* Initialize PB interface. */
-
- ori r4,r29,TSI108_PB_REG_OFFSET
-
-#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
- /* Relocate (if required) Tsi108 registers. Set new value for
- * PB_REG_BAR:
- * Note we are in the 32-bit address mode.
- */
- LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
- stw r5,PB_REG_BAR(r4)
- andis. r29,r5,0xFFFF
- sync
- ori r4,r29,TSI108_PB_REG_OFFSET
-#endif
-
- /* Set PB Slave configuration register */
-
- LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
- lwz r3, PB_RSR(r4) /* get PB bus mode */
- xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
- rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
- stw r5,PB_SCR(r4)
- sync
-
- /* Configure PB Arbiter */
-
- lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
- li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
-#ifdef DISABLE_PBM
- ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
-#endif
- andc r5,r5,r3 /* Clear the masked bit fields */
- ori r5,r5,0x0001 /* Set pipeline depth */
- stw r5,PB_ARB_CTRL(r4)
-
-#if (0) /* currently using the default settings for PBM after reset */
- LOAD_U32(r5,0x) /* value for PB_MCR */
- stw r5,PB_MCR(r4)
- sync
-
- LOAD_U32(r5,0x) /* value for PB_MCMD */
- stw r5,PB_MCMD(r4)
- sync
-#endif
-
- /* Disable or enable PVT based on processor bus frequency
- * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
- * 2. See if the value is < or > 133mhz (18:16 = 100)
- * 3. If > enable PVT
- */
-
- LOAD_U32(r3,0xC0002234)
- lwz r3,0(r3)
- rlwinm r3,r3,16,29,31
-
- cmpi 0,0,r3,0x0004
- bgt sdc_init
-
-#ifndef CONFIG_TSI108EMU
- /* FIXME: Disable PB calibration control for any real Tsi108 board */
- li r5,0x0101 /* disable calibration control */
- stw r5,PB_PVT_CTRL2(r4)
- sync
-#endif
-
- /* Initialize SDRAM controller. */
-
-sdc_init:
-
-#ifndef SDC_HARDCODED_INIT
- /* get SDC clock prior doing sdram controller autoconfig */
- ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
- lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
- rlwinm r3,r3,12,29,31 /* r3 - SD clk */
- lis r5,sdc_clk_sync@h
- ori r5,r5,sdc_clk_sync@l
- /* Sri: At this point check if r3 = 001. If yes,
- * the memory frequency should be same as the
- * MPX bus frequency
- */
- cmpi 0,0,r3,0x0001
- bne get_nsec
- lwz r6, CG_PWRUP_STATUS(r4)
- rlwinm r6,r6,16,29,31
- mr r3,r6
-
-get_nsec:
- rlwinm r3,r3,2,0,31
- lwzx r9,r5,r3 /* get SD clk rate in nSec */
- /* ATTN: r9 will be used by SPD routine */
-#endif /* !SDC_HARDCODED_INIT */
-
- ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
-
- /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
-
- LOAD_U32(r5,0x00)
- stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
-#ifdef ENABLE_SDRAM_ECC
- li r5, 0x01
-#endif /* ENABLE_SDRAM_ECC */
- stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
- sync
-
-#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
-
- /* First read the CG_PWRUP_STATUS register to get the
- * memory speed from bits 22,21,20
- */
-
- LOAD_U32(r3,0xC0002234)
- lwz r3,0(r3)
- rlwinm r3,r3,12,29,31
-
- /* Now first check for 166, then 200, or default */
-
- cmpi 0,0,r3,0x0005
- bne check_for_200mhz
-
- /* set values for 166 Mhz memory speed
- * Set refresh rate and timing parameters
- */
- LOAD_U32(r5,0x00000515)
- stw r5,SD_REFRESH(r4)
- LOAD_U32(r5,0x03073368)
- stw r5,SD_TIMING(r4)
- sync
-
- /* Initialize DIMM0 control and BAR registers */
- LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D0_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D0_BAR)
- stw r5,SD_D0_BAR(r4)
- sync
-
- /* Initialize DIMM1 control and BAR registers
- * (same as dimm 0, next 512MB, disabled)
- */
- LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D1_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D1_BAR)
- stw r5,SD_D1_BAR(r4)
- sync
-
- b sdc_init_done
-
-check_for_200mhz:
-
- cmpi 0,0,r3,0x0006
- bne set_default_values
-
- /* set values for 200Mhz memory speed
- * Set refresh rate and timing parameters
- */
- LOAD_U32(r5,0x0000061a)
- stw r5,SD_REFRESH(r4)
- LOAD_U32(r5,0x03083348)
- stw r5,SD_TIMING(r4)
- sync
-
- /* Initialize DIMM0 control and BAR registers */
- LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D0_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D0_BAR)
- stw r5,SD_D0_BAR(r4)
- sync
-
- /* Initialize DIMM1 control and BAR registers
- * (same as dimm 0, next 512MB, disabled)
- */
- LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D1_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D1_BAR)
- stw r5,SD_D1_BAR(r4)
- sync
-
- b sdc_init_done
-
-set_default_values:
-
- /* Set refresh rate and timing parameters */
- LOAD_U32(r5,VAL_SD_REFRESH)
- stw r5,SD_REFRESH(r4)
- LOAD_U32(r5,VAL_SD_TIMING)
- stw r5,SD_TIMING(r4)
- sync
-
- /* Initialize DIMM0 control and BAR registers */
- LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D0_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D0_BAR)
- stw r5,SD_D0_BAR(r4)
- sync
-
- /* Initialize DIMM1 control and BAR registers
- * (same as dimm 0, next 512MB, disabled)
- */
- LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
-#ifdef SDC_AUTOPRECH_EN
- oris r5,r5,0x0001 /* set auto precharge EN bit */
-#endif
- stw r5,SD_D1_CTRL(r4)
- LOAD_U32(r5,VAL_SD_D1_BAR)
- stw r5,SD_D1_BAR(r4)
- sync
-#else /* !SDC_HARDCODED_INIT */
- bl tsi108_sdram_spd /* automatically detect SDC settings */
-#endif /* SDC_HARDCODED_INIT */
-
-sdc_init_done:
-
-#ifdef DISABLE_PBM
- LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
-#else
- LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
-#endif /* DISABLE_PBM */
-
-#ifdef CONFIG_TSI108EMU
- oris r5,r5,0x0010 /* set EMULATION_MODE bit */
-#endif
-
- stw r5,SD_CTRL(r4)
- eieio
- sync
-
- /* Enable SDRAM access */
-
- oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
- stw r5,SD_CTRL(r4)
- sync
-
-wait_init_complete:
- lwz r5,SD_STATUS(r4)
- andi. r5,r5,0x0001
- /* wait until SDRAM initialization is complete */
- beq wait_init_complete
-
- /* Map SDRAM into the processor bus address space */
-
- ori r4,r29,TSI108_PB_REG_OFFSET
-
- /* Setup BARs associated with direct path PB<->SDRAM */
-
- /* PB_SDRAM_BAR1:
- * provides a direct path to the main system memory (cacheable SDRAM)
- */
-
- /* BA=0,Size=512MB, ENable, No Addr.Translation */
- LOAD_U32(r5, 0x00000011)
- stw r5,PB_SDRAM_BAR1(r4)
- sync
-
- /* Make sure that PB_SDRAM_BAR1 decoder is set
- * (to allow following immediate read from SDRAM)
- */
- lwz r5,PB_SDRAM_BAR1(r4)
- sync
-
- /* PB_SDRAM_BAR2:
- * provides non-cacheable alias (via the direct path) to main
- * system memory.
- * Size = 512MB, ENable, Addr.Translation - ON,
- * BA = 0x0_40000000, TA = 0x0_00000000
- */
-
- LOAD_U32(r5, 0x40010011)
- stw r5,PB_SDRAM_BAR2(r4)
- sync
-
- /* Make sure that PB_SDRAM_BAR2 decoder is set
- * (to allow following immediate read from SDRAM)
- */
- lwz r5,PB_SDRAM_BAR2(r4)
- sync
-
-init_done:
-
- /* All done. Restore LR and return. */
- mtlr r19
- blr
-
-#if (0)
- /*
- * init_cpu1
- * This routine enables CPU1 on the dual-processor system.
- * Now there is only one processor in the system
- */
-
- .global enable_cpu1
-enable_cpu1:
-
- lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
- addi r3,r3,Tsi108_Base@l
- lwz r3,0(r3) /* R3 = CSR Base Addr */
- ori r4,r3,TSI108_PB_REG_OFFSET
- lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
- ori r3,r3,0x0200 /* Set M1_EN bit */
- stw r3,PB_ARB_CTRL(r4)
-
- blr
-#endif
-
- /*
- * enable_EI
- * Enable CPU core external interrupt
- */
-
- .global enable_EI
-enable_EI:
- mfmsr r3
- ori r3,r3,0x8000 /* set EE bit */
- mtmsr r3
- blr
-
- /*
- * disable_EI
- * Disable CPU core external interrupt
- */
-
- .global disable_EI
-disable_EI:
- mfmsr r3
- li r4,-32768 /* aka "li r4,0x8000" */
- andc r3,r3,r4 /* clear EE bit */
- mtmsr r3
- blr
-
-#ifdef ENABLE_SDRAM_ECC
- /* enables SDRAM ECC */
-
- .global enable_ECC
-enable_ECC:
- ori r4,r29,TSI108_SD_REG_OFFSET
- lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
- ori r3,r3,0x0001 /* Set ECC_EN bit */
- stw r3,SD_ECC_CTRL(r4)
- blr
-
- /*
- * clear_ECC_err
- * Clears all pending SDRAM ECC errors
- * (normally after SDRAM scrubbing/initialization)
- */
-
- .global clear_ECC_err
-clear_ECC_err:
- ori r4,r29,TSI108_SD_REG_OFFSET
- ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
- stw r3,SD_INT_STATUS(r4)
- blr
-
-#endif /* ENABLE_SDRAM_ECC */
-
-#ifndef SDC_HARDCODED_INIT
-
- /* SDRAM SPD Support */
-#define SD_I2C_CTRL1 (0x400)
-#define SD_I2C_CTRL2 (0x404)
-#define SD_I2C_RD_DATA (0x408)
-#define SD_I2C_WR_DATA (0x40C)
-
- /*
- * SDRAM SPD Support Macros
- */
-
-#define SPD_DIMM0 (0x00000100)
-#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
-
-#define SPD_RDIMM (0x01)
-#define SPD_UDIMM (0x02)
-
-#define SPD_CAS_3 0x8
-#define SPD_CAS_4 0x10
-#define SPD_CAS_5 0x20
-
-#define ERR_NO_DIMM_FOUND (0xdb0)
-#define ERR_TRAS_FAIL (0xdb1)
-#define ERR_TRCD_FAIL (0xdb2)
-#define ERR_TRP_FAIL (0xdb3)
-#define ERR_TWR_FAIL (0xdb4)
-#define ERR_UNKNOWN_PART (0xdb5)
-#define ERR_NRANK_INVALID (0xdb6)
-#define ERR_DIMM_SIZE (0xdb7)
-#define ERR_ADDR_MODE (0xdb8)
-#define ERR_RFRSH_RATE (0xdb9)
-#define ERR_DIMM_TYPE (0xdba)
-#define ERR_CL_VALUE (0xdbb)
-#define ERR_TRFC_FAIL (0xdbc)
-
-/* READ_SPD requirements:
- * byte - byte address in SPD device (0 - 255)
- * r3 = will return data read from I2C Byte location
- * r4 - unchanged (SDC base addr)
- * r5 - clobbered in routine (I2C status)
- * r10 - number of DDR slot where first SPD device is detected
- */
-
-#define READ_SPD(byte_num) \
- addis r3, 0, byte_num@l; \
- or r3, r3, r10; \
- ori r3, r3, 0x0A; \
- stw r3, SD_I2C_CTRL1(r4); \
- li r3, I2C_CNTRL2_START; \
- stw r3, SD_I2C_CTRL2(r4); \
- eieio; \
- sync; \
- li r3, 0x100; \
-1:; \
- addic. r3, r3, -1; \
- bne 1b; \
-2:; \
- lwz r5, SD_I2C_CTRL2(r4); \
- rlwinm. r3,r5,0,23,23; \
- bne 2b; \
- rlwinm. r3,r5,0,3,3; \
- lwz r3,SD_I2C_RD_DATA(r4)
-
-#define SPD_MIN_RFRSH (0x80)
-#define SPD_MAX_RFRSH (0x85)
-
-refresh_rates: /* in nSec */
- .long 15625 /* Normal (0x80) */
- .long 3900 /* Reduced 0.25x (0x81) */
- .long 7800 /* Reduced 0.5x (0x82) */
- .long 31300 /* Extended 2x (0x83) */
- .long 62500 /* Extended 4x (0x84) */
- .long 125000 /* Extended 8x (0x85) */
-
-/*
- * tsi108_sdram_spd
- *
- * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
- * Uses registers: r4 - SDC base address (not changed)
- * r9 - SDC clocking period in nSec
- * Changes registers: r3,r5,r6,r7,r8,r10,r11
- */
-
-tsi108_sdram_spd:
-
- li r10,SPD_DIMM0
- xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
-
-do_first_dimm:
-
- /* Program Refresh Rate Register */
-
- READ_SPD(12) /* get Refresh Rate */
- beq check_next_slot
- li r5, ERR_RFRSH_RATE
- cmpi 0,0,r3,SPD_MIN_RFRSH
- ble spd_fail
- cmpi 0,0,r3,SPD_MAX_RFRSH
- bgt spd_fail
- addi r3,r3,-SPD_MIN_RFRSH
- rlwinm r3,r3,2,0,31
- lis r5,refresh_rates@h
- ori r5,r5,refresh_rates@l
- lwzx r5,r5,r3 /* get refresh rate in nSec */
- divwu r5,r5,r9 /* calculate # of SDC clocks */
- stw r5,SD_REFRESH(r4) /* Set refresh rate */
- sync
-
- /* Program SD Timing Register */
-
- li r7, 0 /* clear r7 prior parameter collection */
-
- READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
- beq spd_read_fail
- li r5, ERR_DIMM_TYPE
- cmpi 0,0,r3,SPD_UDIMM
- beq do_cl
- cmpi 0,0,r3,SPD_RDIMM
- bne spd_fail
- oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
-
-do_cl:
- READ_SPD(18) /* Get CAS Latency */
- beq spd_read_fail
- li r5,ERR_CL_VALUE
- andi. r6,r3,SPD_CAS_3
- beq cl_4
- li r6,3
- b set_cl
-cl_4:
- andi. r6,r3,SPD_CAS_4
- beq cl_5
- li r6,4
- b set_cl
-cl_5:
- andi. r6,r3,SPD_CAS_5
- beq spd_fail
- li r6,5
-set_cl:
- rlwimi r7,r6,24,5,7
-
- READ_SPD(30) /* Get tRAS */
- beq spd_read_fail
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_tras
- addi r6,r6,1
-set_tras:
- li r5,ERR_TRAS_FAIL
- cmpi 0,0,r6,0x0F /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,16,12,15
-
- READ_SPD(29) /* Get tRCD */
- beq spd_read_fail
- /* right shift tRCD by 2 bits as per DDR2 spec */
- rlwinm r3,r3,30,2,31
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_trcd
- addi r6,r6,1
-set_trcd:
- li r5,ERR_TRCD_FAIL
- cmpi 0,0,r6,0x07 /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,12,17,19
-
- READ_SPD(27) /* Get tRP value */
- beq spd_read_fail
- rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_trp
- addi r6,r6,1
-set_trp:
- li r5,ERR_TRP_FAIL
- cmpi 0,0,r6,0x07 /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,8,21,23
-
- READ_SPD(36) /* Get tWR value */
- beq spd_read_fail
- rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_twr
- addi r6,r6,1
-set_twr:
- addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
- li r5,ERR_TWR_FAIL
- cmpi 0,0,r6,0x07 /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,5,24,26
-
- READ_SPD(42) /* Get tRFC */
- beq spd_read_fail
- li r5, ERR_TRFC_FAIL
- /* Tsi108 spec: tRFC=(tRFC + 1)/2 */
- addi r3,r3,1
- rlwinm. r3,r3,31,1,31 /* divide by 2 */
- beq spd_fail
- divwu r6,r3,r9
- mullw r8,r6,r9
- subf. r8,r8,r3
- beq set_trfc
- addi r6,r6,1
-set_trfc:
- cmpi 0,0,r6,0x1F /* max supported value */
- bgt spd_fail
- rlwimi r7,r6,0,27,31
-
- stw r7,SD_TIMING(r4)
- sync
-
- /*
- * The following two registers are set on per-DIMM basis.
- * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
- */
-
-do_each_dimm:
-
- /* Program SDRAM DIMM Control Register */
-
- li r7, 0 /* clear r7 prior parameter collection */
-
- READ_SPD(13) /* Get Primary SDRAM Width */
- beq spd_read_fail
- cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
- beq do_nbank
- oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
-
-do_nbank:
- READ_SPD(17) /* Get Number of banks on SDRAM device */
- beq spd_read_fail
- /* Grendel only distinguish betw. 4 or 8-bank memory parts */
- li r5,ERR_UNKNOWN_PART /* non-supported memory part */
- cmpi 0,0,r3,4
- beq do_nrank
- cmpi 0,0,r3,8
- bne spd_fail
- ori r7,r7,0x1000
-
-do_nrank:
- READ_SPD(5) /* Get # of Ranks */
- beq spd_read_fail
- li r5,ERR_NRANK_INVALID
- andi. r6,r3,0x7 /* Use bits [2..0] only */
- beq do_addr_mode
- cmpi 0,0,r6,1
- bgt spd_fail
- rlwimi r7,r6,8,23,23
-
-do_addr_mode:
- READ_SPD(4) /* Get # of Column Addresses */
- beq spd_read_fail
- li r5, ERR_ADDR_MODE
- andi. r3,r3,0x0f /* cut off reserved bits */
- cmpi 0,0,r3,8
- ble spd_fail
- cmpi 0,0,r3,15
- bgt spd_fail
- addi r6,r3,-8 /* calculate ADDR_MODE parameter */
- rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
-
-set_dimm_ctrl:
-#ifdef SDC_AUTOPRECH_EN
- oris r7,r7,0x0001 /* set auto precharge EN bit */
-#endif
- ori r7,r7,1 /* set ENABLE bit */
- cmpi 0,0,r10,SPD_DIMM0
- bne 1f
- stw r7,SD_D0_CTRL(r4)
- sync
- b set_dimm_bar
-1:
- stw r7,SD_D1_CTRL(r4)
- sync
-
-
- /* Program SDRAM DIMMx Base Address Register */
-
-set_dimm_bar:
- READ_SPD(5) /* get # of Ranks */
- beq spd_read_fail
- andi. r7,r3,0x7
- addi r7,r7,1
- READ_SPD(31) /* Read DIMM rank density */
- beq spd_read_fail
- rlwinm r5,r3,27,29,31
- rlwinm r6,r3,3,24,28
- or r5,r6,r5 /* r5 = Normalized Rank Density byte */
- lis r8, 0x0080 /* 128MB >> 4 */
- mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
- mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
- neg r7,r8
- rlwinm r7,r7,28,4,31
- or r7,r7,r11 /* set ADDR field */
- rlwinm r8,r8,12,20,31
- add r11,r11,r8 /* set Base Addr for next DIMM */
-
- cmpi 0,0,r10,SPD_DIMM0
- bne set_dimm1_size
- stw r7,SD_D0_BAR(r4)
- sync
- li r10,SPD_DIMM1
- READ_SPD(0)
- bne do_each_dimm
- b spd_done
-
-set_dimm1_size:
- stw r7,SD_D1_BAR(r4)
- sync
-spd_done:
- blr
-
-check_next_slot:
- cmpi 0,0,r10,SPD_DIMM1
- beq spd_read_fail
- li r10,SPD_DIMM1
- b do_first_dimm
-spd_read_fail:
- ori r3,r0,0xdead
- b err_hung
-spd_fail:
- li r3,0x0bad
- sync
-err_hung: /* hang here for debugging */
- nop
- nop
- b err_hung
-
-#endif /* !SDC_HARDCODED_INIT */
+++ /dev/null
-#
-# Copyright (c) 2005 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-# Flash address
-TEXT_BASE = 0xFF000000
-# RAM address
-#TEXT_BASE = 0x00400000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float
+++ /dev/null
-/*
- * (C) Copyright 2005 Freescale Semiconductor, Inc.
- *
- * Roy Zang <tie-fei.zang@freescale.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * modifications for the Tsi108 Emul Board by avb@Tundra
- */
-
-/*
- * board support/init functions for the
- * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
- */
-
-#include <common.h>
-#include <74xx_7xx.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup (void *blob, bd_t *bd);
-#endif
-
-#undef DEBUG
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-extern void tsi108_init_f (void);
-
-int display_mem_map (void);
-
-void after_reloc (ulong dest_addr)
-{
- /*
- * Jump to the main U-Boot board init code
- */
- board_init_r ((gd_t *) gd, dest_addr);
- /* NOTREACHED */
-}
-
-/*
- * Check Board Identity:
- * report board type
- */
-
-int checkboard (void)
-{
- int l_type = 0;
-
- printf ("BOARD: %s\n", CFG_BOARD_NAME);
- return (l_type);
-}
-
-/*
- * Read Processor ID:
- *
- * report calling processor number
- */
-
-int read_pid (void)
-{
- return 0; /* we are on single CPU platform for a while */
-}
-
-long int dram_size (int board_type)
-{
- return 0x20000000; /* 256M bytes */
-}
-
-long int initdram (int board_type)
-{
- return dram_size (board_type);
-}
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup (void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- ft_cpu_setup (blob, bd);
-
- p = ft_get_prop (blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32 (bd->bi_memstart);
- *p = cpu_to_be32 (bd->bi_memsize);
- }
-}
-#endif
+++ /dev/null
-/*****************************************************************************
- * (C) Copyright 2003; Tundra Semiconductor Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *****************************************************************************/
-
-/*----------------------------------------------------------------------------
- * FILENAME: tsi108_init.c
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Initialization code for the Tundra Tsi108 bridge chip
- *---------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <74xx_7xx.h>
-#include <config.h>
-#include <version.h>
-#include <asm/processor.h>
-#include <tsi108.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void mpicInit (int verbose);
-
-/*
- * Configuration Options
- */
-
-typedef struct {
- ulong upper;
- ulong lower;
-} PB2OCN_LUT_ENTRY;
-
-PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
- /* 0 - 7 */
- {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
-
- /* 8 - 15 */
- {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
-
- /* 16 - 23 */
- {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
- /* 24 - 31 */
- {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
- {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
-
- {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
- {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
- {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
- {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
-};
-
-#ifdef CFG_CLK_SPREAD
-typedef struct {
- ulong ctrl0;
- ulong ctrl1;
-} PLL_CTRL_SET;
-
-/*
- * Clock Generator SPLL0 initialization values
- * PLL0 configuration table for various PB_CLKO freq.
- * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
- * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
- */
-
-static PLL_CTRL_SET pll0_config[8] = {
- {0x00000000, 0x00000000}, /* 0: bypass */
- {0x00000000, 0x00000000}, /* 1: reserved */
- {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
- {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
- {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
- {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
- {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
- {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
-};
-#endif /* CFG_CLK_SPREAD */
-
-/*
- * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
- * (based on recommended Tsi108 reference clock 33MHz)
- */
-static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
-
-/*
- * get_board_bus_clk ()
- *
- * returns the bus clock in Hz.
- */
-unsigned long get_board_bus_clk (void)
-{
- ulong i;
-
- /* Detect PB clock freq. */
- i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
- i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
-
- return pb_clk_sel[i] * 1000000;
-}
-
-/*
- * board_early_init_f ()
- *
- * board-specific initialization executed from flash
- */
-
-int board_early_init_f (void)
-{
- ulong i;
-
- gd->mem_clk = 0;
- i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
- CG_PWRUP_STATUS);
- i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
- switch (i) {
- case 0: /* external clock */
- printf ("Using external clock\n");
- break;
- case 1: /* system clock */
- gd->mem_clk = gd->bus_clk;
- break;
- case 4: /* 133 MHz */
- case 5: /* 166 MHz */
- case 6: /* 200 MHz */
- gd->mem_clk = pb_clk_sel[i] * 1000000;
- break;
- default:
- printf ("Invalid DDR2 clock setting\n");
- return -1;
- }
- printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
- printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
- return 0;
-}
-
-/*
- * board_early_init_r() - Tsi108 initialization function executed right after
- * relocation. Contains code that cannot be executed from flash.
- */
-
-int board_early_init_r (void)
-{
- ulong temp, i;
- ulong reg_val;
- volatile ulong *reg_ptr;
-
- reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
- *reg_ptr++ = 0x00;
- }
-
- __asm__ __volatile__ ("eieio");
- __asm__ __volatile__ ("sync");
-
- /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
- 0x80000001);
- __asm__ __volatile__ ("sync");
-
- /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
- * read from SDRAM)
- */
-
- temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
- __asm__ __volatile__ ("sync");
-
- /*
- * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
- * processor bus address space. Immediately after reset LUT and address
- * translation are disabled for this BAR. Now we have to initialize LUT
- * and switch from the BOOT mode to the normal operation mode.
- *
- * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
- * and covers 512MB of address space. To allow larger aperture we also
- * have to relocate register window of Tsi108
- *
- * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
- * mode.
- *
- * initialize pointer to LUT associated with PB_OCN_BAR1
- */
- reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = pb2ocn_lut1[i].lower;
- *reg_ptr++ = pb2ocn_lut1[i].upper;
- }
-
- __asm__ __volatile__ ("sync");
-
- /* Base addresses for CS0, CS1, CS2, CS3 */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
- 0x00000000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
- 0x00100000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
- 0x00200000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
- 0x00300000);
- __asm__ __volatile__ ("sync");
-
- /* Masks for HLP banks */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
- 0xFFF00000);
- __asm__ __volatile__ ("sync");
-
- /* Set CTRL0 values for banks */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
- 0x7FFC44C2);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
- 0x7FFC44C0);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
- 0x7FFC44C0);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
- 0x7FFC44C2);
- __asm__ __volatile__ ("sync");
-
- /* Set banks to latched mode, enabled, and other default settings */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
- 0x7C0F2000);
- __asm__ __volatile__ ("sync");
-
- /*
- * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
- * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
- */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
- 0xE0000011);
- __asm__ __volatile__ ("sync");
-
- /* Make sure that OCN_BAR2 decoder is set (to allow following
- * immediate read from SDRAM)
- */
-
- temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
- __asm__ __volatile__ ("sync");
-
- /*
- * SRI: At this point we have enabled the HLP banks. That means we can
- * now read from the NVRAM and initialize the environment variables.
- * We will over-ride the env_init called in board_init_f
- * This is really a work-around because, the HLP bank 1
- * where NVRAM resides is not visible during board_init_f
- * (lib_ppc/board.c)
- * Alternatively, we could use the I2C EEPROM at start-up to configure
- * and enable all HLP banks and not just HLP 0 as is being done for
- * Taiga Rev. 2.
- */
-
- env_init ();
-
-#ifndef DISABLE_PBM
-
- /*
- * For IBM processors we have to set Address-Only commands generated
- * by PBM that are different from ones set after reset.
- */
-
- temp = get_cpu_type ();
-
- if ((CPU_750FX == temp) || (CPU_750GX == temp))
- out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
- 0x00009955);
-#endif /* DISABLE_PBM */
-
-#ifdef CONFIG_PCI
- /*
- * Initialize PCI/X block
- */
-
- /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
- PCI_PFAB_BAR0_UPPER, 0);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
- 0xFB000001);
- __asm__ __volatile__ ("sync");
-
- /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
-
- temp = in32(CFG_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
-
- temp &= ~0xFF00; /* Clear the BUS_NUM field */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
- temp);
-
- /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
- 0);
- __asm__ __volatile__ ("sync");
-
- /* This register is on the PCI side to interpret the address it receives
- * and maps it as a IO address.
- */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
- 0xFA000001);
- __asm__ __volatile__ ("sync");
-
- /*
- * Map PCI/X Memory Space
- *
- * Transactions directed from OCM to PCI Memory Space are directed
- * from PB to PCI
- * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
- * If address remapping is required the corresponding PCI_PFAB_MEM32
- * and PCI_PFAB_PFMx register groups have to be configured.
- *
- * Map the path from the PCI/X bus into the system memory
- *
- * The memory mapped window assotiated with PCI P2O_BAR2 provides
- * access to the system memory without address remapping.
- * All system memory is opened for accesses initiated by PCI/X bus
- * masters.
- *
- * Initialize LUT associated with PCI P2O_BAR2
- *
- * set pointer to LUT associated with PCI P2O_BAR2
- */
-
- reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
-
-#ifdef DISABLE_PBM
-
- /* In case when PBM is disabled (no HW supported cache snoopng on PB)
- * P2O_BAR2 is directly mapped into the system memory without address
- * translation.
- */
-
- reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
- *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
- }
-
- /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
- reg_val = 0x00007500;
-#else
-
- reg_val = 0x00000002; /* Destination port = PBM */
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
-/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
- *reg_ptr++ = 0x40000000;
-/* offset = 16MB, address translation is enabled to allow byte swapping */
- reg_val += 0x01000000;
- }
-
-/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
- reg_val = 0x00007100;
-#endif
-
- __asm__ __volatile__ ("eieio");
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
- reg_val);
- __asm__ __volatile__ ("sync");
-
- /* Set 64-bit PCI bus address for system memory
- * ( 0 is the best choice for easy mapping)
- */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
- 0x00000000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
- 0x00000000);
- __asm__ __volatile__ ("sync");
-
-#ifndef DISABLE_PBM
- /*
- * The memory mapped window assotiated with PCI P2O_BAR3 provides
- * access to the system memory using SDRAM OCN port and address
- * translation. This is alternative way to access SDRAM from PCI
- * required for Tsi108 emulation testing.
- * All system memory is opened for accesses initiated by
- * PCI/X bus masters.
- *
- * Initialize LUT associated with PCI P2O_BAR3
- *
- * set pointer to LUT associated with PCI P2O_BAR3
- */
- reg_ptr =
- (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
-
- reg_val = 0x00000004; /* Destination port = SDC */
-
- for (i = 0; i < 32; i++) {
- *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
-
-/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
- *reg_ptr++ = 0;
-
-/* offset = 16MB, address translation is enabled to allow byte swapping */
- reg_val += 0x01000000;
- }
-
- __asm__ __volatile__ ("eieio");
- __asm__ __volatile__ ("sync");
-
- /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
-
- reg_val =
- in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
- PCI_P2O_PAGE_SIZES);
- reg_val &= ~0x00FF;
- reg_val |= 0x0071;
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
- reg_val);
- __asm__ __volatile__ ("sync");
-
- /* Set 64-bit base PCI bus address for window (0x20000000) */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
- 0x00000000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
- 0x20000000);
- __asm__ __volatile__ ("sync");
-
-#endif /* !DISABLE_PBM */
-
-#ifdef ENABLE_PCI_CSR_BAR
- /* open if required access to Tsi108 CSRs from the PCI/X bus */
- /* enable BAR0 on the PCI/X bus */
- reg_val = in32(CFG_TSI108_CSR_BASE +
- TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
- reg_val |= 0x02;
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
- reg_val);
- __asm__ __volatile__ ("sync");
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
- 0x00000000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
- CFG_TSI108_CSR_BASE);
- __asm__ __volatile__ ("sync");
-
-#endif
-
- /*
- * Finally enable PCI/X Bus Master and Memory Space access
- */
-
- reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
- reg_val |= 0x06;
- out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
- __asm__ __volatile__ ("sync");
-
-#endif /* CONFIG_PCI */
-
- /*
- * Initialize MPIC outputs (interrupt pins):
- * Interrupt routing on the Grendel Emul. Board:
- * PB_INT[0] -> INT (CPU0)
- * PB_INT[1] -> INT (CPU1)
- * PB_INT[2] -> MCP (CPU0)
- * PB_INT[3] -> MCP (CPU1)
- * Set interrupt controller outputs as Level_Sensitive/Active_Low
- */
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
- out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
- __asm__ __volatile__ ("sync");
-
- /*
- * Ensure that Machine Check exception is enabled
- * We need it to support PCI Bus probing (configuration reads)
- */
-
- reg_val = mfmsr ();
- mtmsr(reg_val | MSR_ME);
-
- return 0;
-}
-
-/*
- * Needed to print out L2 cache info
- * used in the misc_init_r function
- */
-
-unsigned long get_l2cr (void)
-{
- unsigned long l2controlreg;
- asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
- return l2controlreg;
-}
-
-/*
- * misc_init_r()
- *
- * various things to do after relocation
- *
- */
-
-int misc_init_r (void)
-{
-#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
- ulong i;
-
- /* Ensure that Spread-Spectrum is disabled */
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
-
- /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
- * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
- */
-
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
- 0x002e0044); /* D = 0.25% */
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
- 0x00000039); /* BWADJ */
-
- /* Initialize PLL0: CG_PB_CLKO */
- /* Detect PB clock freq. */
- i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
- i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
-
- out32 (CFG_TSI108_CSR_BASE +
- TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
- out32 (CFG_TSI108_CSR_BASE +
- TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
-
- /* Wait and set SSEN for both PLL0 and 1 */
- udelay (1000);
- out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
- 0x802e0044); /* D=0.25% */
- out32 (CFG_TSI108_CSR_BASE +
- TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
- 0x80000000 | pll0_config[i].ctrl0);
-#endif /* CFG_CLK_SPREAD */
-
-#ifdef CFG_L2
- l2cache_enable ();
-#endif
- printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
- printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
-
- /*
- * All the information needed to print the cache details is avaiblable
- * at this point i.e. above call to l2cache_enable is the very last
- * thing done with regards to enabling diabling the cache.
- * So this seems like a good place to print all this information
- */
-
- printf ("CACHE: ");
- switch (get_cpu_type()) {
- case CPU_7447A:
- printf ("L1 Instruction cache - 32KB 8-way");
- (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("L1 Data cache - 32KB 8-way");
- (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("Unified L2 cache - 512KB 8-way");
- (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("\n");
- break;
-
- case CPU_7448:
- printf ("L1 Instruction cache - 32KB 8-way");
- (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("L1 Data cache - 32KB 8-way");
- (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- printf ("Unified L2 cache - 1MB 8-way");
- (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
- printf (" DISABLED\n");
- break;
- default:
- break;
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board.
- */
-
-OUTPUT_ARCH(powerpc)
-SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/74xx_7xx/start.o (.text)
-
-/* store the environment in a seperate sector in the boot flash */
-/* . = env_offset; */
-/* common/environment.o(.text) */
-
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
-#
-# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-## Standard: boot high
-TEXT_BASE = 0xFFF00000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * (C) Copyright 2003 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Re-written to support multi-bank flash SIMMs.
- * Added support for real protection and JFFS2.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x89898989
-#define INTEL_ALT 0xB0B0B0B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10101010
-#define INTEL_ERASE 0x20202020
-#define INTEL_CLEAR 0x50505050
-#define INTEL_LOCKBIT 0x60606060
-#define INTEL_PROTECT 0x01010101
-#define INTEL_STATUS 0x70707070
-#define INTEL_READID 0x90909090
-#define INTEL_CONFIRM 0xD0D0D0D0
-#define INTEL_RESET 0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80808080
-#define INTEL_OK 0x80808080
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
- * Up to 32MB of flash supported (up to 4 banks.)
- * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
- *
- * The following code can not run from flash!
- */
-unsigned long flash_init (void)
-{
- ulong size = 0, sect_start, sect_size = 0, bank_size;
- ushort sect_count = 0;
- int i, j, nbanks;
- vu_long *addr = (vu_long *)CFG_FLASH_BASE;
- vu_long *bcsr = (vu_long *)CFG_BCSR;
-
- switch (bcsr[2] & 0xF) {
- case 0:
- nbanks = 4;
- break;
- case 1:
- nbanks = 2;
- break;
- case 2:
- nbanks = 1;
- break;
- default: /* Unsupported configurations */
- nbanks = CFG_MAX_FLASH_BANKS;
- }
-
- if (nbanks > CFG_MAX_FLASH_BANKS)
- nbanks = CFG_MAX_FLASH_BANKS;
-
- for (i = 0; i < nbanks; i++) {
- *addr = INTEL_READID; /* Read Intelligent Identifier */
- if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
- switch (addr[1]) {
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- sect_count = 32;
- sect_size = 0x40000;
- break;
- default:
- flash_info[i].flash_id = FLASH_UNKNOWN;
- sect_count = CFG_MAX_FLASH_SECT;
- sect_size =
- CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
- }
- }
- else
- flash_info[i].flash_id = FLASH_UNKNOWN;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
- addr[0], addr[1], (ulong)addr);
- size = 0;
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- break;
- }
- flash_info[i].sector_count = sect_count;
- flash_info[i].size = bank_size = sect_size * sect_count;
- size += bank_size;
- sect_start = (ulong)addr;
- for (j = 0; j < sect_count; j++) {
- addr = (vu_long *)sect_start;
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = (addr[2] == 0x01010101);
- sect_start += sect_size;
- }
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- addr = (vu_long *)sect_start;
- }
-
- if (size == 0) { /* Unknown flash, fill with hard-coded values */
- sect_start = CFG_FLASH_BASE;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
- flash_info[i].sector_count = sect_count;
- for (j = 0; j < sect_count; j++) {
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = 0;
- sect_start += sect_size;
- }
- }
- size = CFG_FLASH_SIZE;
- }
- else
- for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = 0;
- flash_info[i].sector_count = 0;
- }
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Clear Status Register */
- *addr = INTEL_CLEAR;
- /* Single Block Erase Command */
- *addr = INTEL_ERASE;
- /* Confirm */
- *addr = INTEL_CONFIRM;
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = INTEL_CONFIRM;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Block erase failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
-
- /* reset to read mode */
- *addr = INTEL_RESET;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- ulong start;
- int rc = 0;
- int flag;
- vu_long *addr = (vu_long *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
-
- *addr = INTEL_CLEAR; /* Clear status register */
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = INTEL_PROGRAM;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- printf("Write timed out\n");
- rc = 1;
- break;
- }
- }
- if (*addr != INTEL_OK) {
- printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- rc = write_word(info, wp, data);
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- ulong start;
- int i;
- int rc = 0;
- vu_long *addr = (vu_long *)(info->start[sector]);
- int flag = disable_interrupts();
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- }
- else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer(0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- */
- if (!prot)
- for (i = 0; i < info->sector_count; i++)
- if (info->protect[i]) {
- addr = (vu_long *)(info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- udelay(CFG_FLASH_LOCK_TOUT * 1000);
- }
-
- if (flag)
- enable_interrupts();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
- /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
- /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CFG_8272ADS
- /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
- /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
-#else
- /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CFG_8272ADS
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
-#else
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-void reset_phy (void)
-{
- vu_long *bcsr = (vu_long *)CFG_BCSR;
-
- /* Reset the PHY */
-#if CFG_PHY_ADDR == 0
- bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
- udelay(2);
- bcsr[1] |= FETH1_RST;
-#else
- bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
- udelay(2);
- bcsr[3] |= FETH2_RST;
-#endif /* CFG_PHY_ADDR == 0 */
- udelay(1000);
-#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
- /*
- * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
- * Enable autonegotiation.
- */
- bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-#else
- /*
- * Ethernet PHY is configured (by means of configuration pins)
- * to work at 10Mb/s only. We reconfigure it using MII
- * to advertise all capabilities, including 100Mb/s, and
- * restart autonegotiation.
- */
-
- /* Advertise all capabilities */
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
-
- /* Do not bypass Rx/Tx (de)scrambler */
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
-
- bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
-#endif /* CONFIG_MII */
-}
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
- vu_long *bcsr = (vu_long *)CFG_BCSR;
-
-#ifdef CONFIG_PCI
- volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
-
- /* mask alll the PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
-#endif
-#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
- bcsr[1] &= ~RS232EN_1;
-#endif
-#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
- bcsr[1] &= ~RS232EN_2;
-#endif
-
-#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
- if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
- {
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
-
- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
- }
-#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
-
- return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-long int initdram (int board_type)
-{
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
- long int msize = 32;
-#elif CONFIG_ADSTYPE == CFG_8272ADS
- long int msize = 64;
-#else
- long int msize = 16;
-#endif
-
-#ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *ramaddr, c = 0xff;
- uint or;
- uint psdmr;
- uint psrt;
-
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000002;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CFG_MPTPR;
-#ifdef CFG_LSDRAM_BASE
- /*
- Initialise local bus SDRAM only if the pins
- are configured as local bus pins and not as PCI.
- The configuration is determined by the HRCW.
- */
- if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CFG_LSRT;
-#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
- memctl->memc_or3 = 0xFF803280;
- memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
-#else /* CS4 */
- memctl->memc_or4 = 0xFFC01480;
- memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
- memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
- ramaddr = (uchar *) CFG_LSDRAM_BASE;
- *ramaddr = c;
- memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
- *ramaddr = c;
- memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
- }
-#endif /* CFG_LSDRAM_BASE */
-
- /* Init 60x bus SDRAM */
-#ifdef CONFIG_SPD_EEPROM
- {
- spd_eeprom_t spd;
- uint pbi, bsel, rowst, lsb, tmp;
-
- i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
-
- /* Bank-based interleaving is not supported for physical bank
- sizes greater than 128MB which is encoded as 0x20 in SPD
- */
- pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
- msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
- or = ~(msize - 1) << 20; /* SDAM */
- switch (spd.nbanks) { /* BPD */
- case 2:
- bsel = 1;
- break;
- case 4:
- bsel = 2;
- or |= 0x00002000;
- break;
- case 8:
- bsel = 3;
- or |= 0x00004000;
- break;
- }
- lsb = 3; /* For 64-bit port, lsb is 3 bits */
-
- if (pbi) { /* Bus partition depends on interleaving */
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
- or |= (rowst << 9); /* ROWST */
- } else {
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
- or |= ((rowst * 2 - 12) << 9); /* ROWST */
- }
- or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
-
- psdmr = (pbi << 31); /* PBI */
- /* Bus multiplexing parameters */
- tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
- psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
- psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
-
- tmp = (31 - lsb - 10) - tmp;
- /* Pin connected to SDA10 is (31 - lsb - 10).
- rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
- so (rowst + tmp) alternates with AP.
- */
- if (pbi) /* Table 10-7 */
- psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
- else
- psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
-
- /* SDRAM device-specific parameters */
- tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
- switch (tmp) { /* RFRC */
- case 1:
- case 2:
- psdmr |= (1 << 15);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- psdmr |= ((tmp - 2) << 15);
- break;
- default:
- psdmr |= (7 << 15);
- }
- psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
- psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
- /* BL=0 because for 64-bit SDRAM burst length must be 4 */
- /* LDOTOPRE ??? */
- for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- switch (i) { /* WRC */
- case 0:
- case 1:
- psdmr |= (1 << 4);
- break;
- case 2:
- case 3:
- psdmr |= (i << 4);
- break;
- }
- /* EAMUX=0 - no external address multiplexing */
- /* BUFCMD=0 - no external buffers */
- for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- psdmr |= i; /* CL */
-
- switch (spd.refresh & 0x7F) {
- case 1:
- tmp = 3900;
- break;
- case 2:
- tmp = 7800;
- break;
- case 3:
- tmp = 31300;
- break;
- case 4:
- tmp = 62500;
- break;
- case 5:
- tmp = 125000;
- break;
- default:
- tmp = 15625;
- }
- psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
- ((memctl->memc_mptpr >> 8) + 1)) - 1;
-#ifdef SPD_DEBUG
- printf ("\nDIMM type: %-18.18s\n", spd.mpart);
- printf ("SPD size: %d\n", spd.info_size);
- printf ("EEPROM size: %d\n", 1 << spd.chip_size);
- printf ("Memory type: %d\n", spd.mem_type);
- printf ("Row addr: %d\n", spd.nrow_addr);
- printf ("Column addr: %d\n", spd.ncol_addr);
- printf ("# of rows: %d\n", spd.nrows);
- printf ("Row density: %d\n", spd.row_dens);
- printf ("# of banks: %d\n", spd.nbanks);
- printf ("Data width: %d\n",
- 256 * spd.dataw_msb + spd.dataw_lsb);
- printf ("Chip width: %d\n", spd.primw);
- printf ("Refresh rate: %02X\n", spd.refresh);
- printf ("CAS latencies: %02X\n", spd.cas_lat);
- printf ("Write latencies: %02X\n", spd.write_lat);
- printf ("tRP: %d\n", spd.trp);
- printf ("tRCD: %d\n", spd.trcd);
-
- printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
-#endif /* SPD_DEBUG */
- }
-#else /* !CONFIG_SPD_EEPROM */
- or = CFG_OR2;
- psdmr = CFG_PSDMR;
- psrt = CFG_PSRT;
-#endif /* CONFIG_SPD_EEPROM */
- memctl->memc_psrt = psrt;
- memctl->memc_or2 = or;
- memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
- ramaddr = (uchar *) CFG_SDRAM_BASE;
- memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
- *ramaddr = c;
-#endif /* CFG_RAMBOOT */
-
- /* return total 60x bus SDRAM size */
- return (msize * 1024 * 1024);
-}
-
-int checkboard (void)
-{
-#if CONFIG_ADSTYPE == CFG_8260ADS
- puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CFG_8266ADS
- puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CFG_PQ2FADS
- puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CFG_8272ADS
- puts ("Board: Motorola MPC8272ADS\n");
-#else
- puts ("Board: unknown\n");
-#endif
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# mpc8260ads board
-#
-
-TEXT_BASE = 0xfe000000
-
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef CFG_ENV_ADDR
-# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
-# endif
-# ifndef CFG_ENV_SIZE
-# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
-# endif
-# ifndef CFG_ENV_SECT_SIZE
-# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(vu_long * addr);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-#ifndef CONFIG_MPC8266ADS
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
-#endif
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
-#ifndef CONFIG_MPC8266ADS
- bcsr->bd_ctrl |= BD_CTRL_FLWE;
-#endif
-
-
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* set the default sector offset */
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
-#ifndef CONFIG_MPC8266ADS
- /* Remap FLASH according to real size */
- memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br1 & ~(BR_BA_MSK));
-#endif
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
- ulong sector_offset;
-
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
-
- value = addr[0] & 0x00FF00FF;
- switch (value) {
- case MT_MANUFACT: /* SHARP, MT or => Intel */
- case INTEL_ALT_MANU:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("unknown manufacturer: %x\n", (unsigned int)value);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case (INTEL_ID_28F016S):
- info->flash_id += FLASH_28F016SV;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F160S3):
- info->flash_id += FLASH_28F160S3;
- info->sector_count = 32;
- info->size = 0x00400000;
- sector_offset = 0x20000;
- break; /* => 2x2 MB */
-
- case (INTEL_ID_28F320S3):
- info->flash_id += FLASH_28F320S3;
- info->sector_count = 64;
- info->size = 0x00800000;
- sector_offset = 0x20000;
- break; /* => 2x4 MB */
-
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- info->sector_count = 32;
- info->size = 0x00800000;
- sector_offset = 0x40000;
- break; /* => 4x2 MB */
-
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += sector_offset;
- /* don't know how to check sector protection */
- info->protect[i] = 0;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
-
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Make Sure Block Lock Bit is not set. */
- if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
- return 1;
- }
-
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Reset Array */
- *addr = 0xffffffff;
- /* Clear Status Register */
- *addr = 0x50505050;
- /* Single Block Erase Command */
- *addr = 0x20202020;
- /* Confirm */
- *addr = 0xD0D0D0D0;
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
- while ((*addr & 0x80808080) != 0x80808080) {
- if(*addr & 0x20202020){
- printf("Error in Block Erase - Lock Bit may be set!\n");
- printf("Status Register = 0x%X\n", (uint)*addr);
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x10101010;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
- while (((csr = *addr) & 0x80808080) != 0x80808080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x40404040) {
- printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
-
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
- */
-
-static int clear_block_lock_bit(vu_long * addr)
-{
- ulong start, now;
-
- /* Reset Array */
- *addr = 0xffffffff;
- /* Clear Status Register */
- *addr = 0x50505050;
-
- *addr = 0x60606060;
- *addr = 0xd0d0d0d0;
-
- start = get_timer (0);
- while(*addr != 0x80808080){
- if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout on clearing Block Lock Bit\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- return 1;
- }
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <i2c.h>
-#include <mpc8260.h>
-#include <pci.h>
-
-/*
- * PBI Page Based Interleaving
- * PSDMR_PBI page based interleaving
- * 0 bank based interleaving
- * External Address Multiplexing (EAMUX) adds a clock to address cycles
- * (this can help with marginal board layouts)
- * PSDMR_EAMUX adds a clock
- * 0 no extra clock
- * Buffer Command (BUFCMD) adds a clock to command cycles.
- * PSDMR_BUFCMD adds a clock
- * 0 no extra clock
- */
-#define CONFIG_PBI 0
-#define PESSIMISTIC_SDRAM 0
-#define EAMUX 0 /* EST requires EAMUX */
-#define BUFCMD 0
-
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-typedef struct bscr_ {
- unsigned long bcsr0;
- unsigned long bcsr1;
- unsigned long bcsr2;
- unsigned long bcsr3;
- unsigned long bcsr4;
- unsigned long bcsr5;
- unsigned long bcsr6;
- unsigned long bcsr7;
-} bcsr_t;
-
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-} pci_ic_t;
-
-void reset_phy(void)
-{
- volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
-
- /* reset the FEC port */
- bcsr->bcsr1 &= ~FETH_RST;
- bcsr->bcsr1 |= FETH_RST;
-}
-
-
-int board_early_init_f (void)
-{
- volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
- volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT;
-
- bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
-
- /* mask all PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts ("Board: Motorola MPC8266ADS\n");
- return 0;
-}
-
-long int initdram(int board_type)
-{
- /* Autoinit part stolen from board/sacsng/sacsng.c */
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar c = 0xff;
- volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
- uint psdmr = CFG_PSDMR;
- int i;
-
- uint psrt = 0x21; /* for no SPD */
- uint chipselects = 1; /* for no SPD */
- uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */
- uint or = CFG_OR2_PRELIM; /* for no SPD */
- uint data_width;
- uint rows;
- uint banks;
- uint cols;
- uint caslatency;
- uint width;
- uint rowst;
- uint sdam;
- uint bsma;
- uint sda10;
- u_char spd_size;
- u_char data;
- u_char cksum;
- int j;
-
- /* Keep the compiler from complaining about potentially uninitialized vars */
- data_width = rows = banks = cols = caslatency = 0;
-
- /*
- * Read the SDRAM SPD EEPROM via I2C.
- */
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-
- i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
- spd_size = data;
- cksum = data;
- for(j = 1; j < 64; j++)
- { /* read only the checksummed bytes */
- /* note: the I2C address autoincrements when alen == 0 */
- i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
- /*printf("addr %d = 0x%02x\n", j, data);*/
- if(j == 5) chipselects = data & 0x0F;
- else if(j == 6) data_width = data;
- else if(j == 7) data_width |= data << 8;
- else if(j == 3) rows = data & 0x0F;
- else if(j == 4) cols = data & 0x0F;
- else if(j == 12)
- {
- /*
- * Refresh rate: this assumes the prescaler is set to
- * approximately 0.39uSec per tick and the target refresh period
- * is about 85% of maximum.
- */
- switch(data & 0x7F)
- {
- default:
- case 0: psrt = 0x21; /* 15.625uS */ break;
- case 1: psrt = 0x07; /* 3.9uS */ break;
- case 2: psrt = 0x0F; /* 7.8uS */ break;
- case 3: psrt = 0x43; /* 31.3uS */ break;
- case 4: psrt = 0x87; /* 62.5uS */ break;
- case 5: psrt = 0xFF; /* 125uS */ break;
- }
- }
- else if(j == 17) banks = data;
- else if(j == 18)
- {
- caslatency = 3; /* default CL */
-# if(PESSIMISTIC_SDRAM)
- if((data & 0x04) != 0) caslatency = 3;
- else if((data & 0x02) != 0) caslatency = 2;
- else if((data & 0x01) != 0) caslatency = 1;
-# else
- if((data & 0x01) != 0) caslatency = 1;
- else if((data & 0x02) != 0) caslatency = 2;
- else if((data & 0x04) != 0) caslatency = 3;
-# endif
- else
- {
- printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
- data);
- }
- }
- else if(j == 63)
- {
- if(data != cksum)
- {
- printf ("WARNING: Configuration data checksum failure:"
- " is 0x%02x, calculated 0x%02x\n",
- data, cksum);
- }
- }
- cksum += data;
- }
-
- /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
- if(caslatency < 2) {
- printf("CL was %d, forcing to 2\n", caslatency);
- caslatency = 2;
- }
- if(rows > 14) {
- printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
- rows = 14;
- }
- if(cols > 11) {
- printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
- cols = 11;
- }
-
- if((data_width != 64) && (data_width != 72))
- {
- printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
- data_width);
- }
- width = 3; /* 2^3 = 8 bytes = 64 bits wide */
- /*
- * Convert banks into log2(banks)
- */
- if (banks == 2) banks = 1;
- else if(banks == 4) banks = 2;
- else if(banks == 8) banks = 3;
-
-
- sdram_size = 1 << (rows + cols + banks + width);
- /* hack for high density memory (512MB per CS) */
- /* !!!!! Will ONLY work with Page Based Interleave !!!!!
- ( PSDMR[PBI] = 1 )
- */
- /* mamory actually has 11 column addresses, but the memory controller
- doesn't really care.
- the calculations that follow will however move the rows so that
- they are muxed one bit off if you use 11 bit columns.
- The solution is to tell the memory controller the correct size of the memory
- but change the number of columns to 10 afterwards.
- The 11th column addre will still be mucxed correctly onto the bus.
-
- Also be aware that the MPC8266ADS board Rev B has not connected
- Row addres 13 to anything.
-
- The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
- */
- if (cols > 10)
- cols = 10;
-
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- rowst = ((32 - 6) - (rows + cols + width)) * 2;
-#else
- rowst = 32 - (rows + banks + cols + width);
-#endif
-
- or = ~(sdram_size - 1) | /* SDAM address mask */
- ((banks-1) << 13) | /* banks per device */
- (rowst << 9) | /* rowst */
- ((rows - 9) << 6); /* numr */
-
-
- /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
-
- /*
- * SDAM specifies the number of columns that are multiplexed
- * (reference AN2165/D), defined to be (columns - 6) for page
- * interleave, (columns - 8) for bank interleave.
- *
- * BSMA is 14 - max(rows, cols). The bank select lines come
- * into play above the highest "address" line going into the
- * the SDRAM.
- */
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- sdam = cols - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam + 2;
-#else
- sdam = cols + banks - 8;
- bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
- sda10 = sdam;
-#endif
-#if(PESSIMISTIC_SDRAM)
- psdmr = (CONFIG_PBI |\
- PSDMR_RFEN |\
- PSDMR_RFRC_16_CLK |\
- PSDMR_PRETOACT_8W |\
- PSDMR_ACTTORW_8W |\
- PSDMR_WRC_4C |\
- PSDMR_EAMUX |\
- PSDMR_BUFCMD) |\
- caslatency |\
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
- (sdam << 24) |\
- (bsma << 21) |\
- (sda10 << 18);
-#else
- psdmr = (CONFIG_PBI |\
- PSDMR_RFEN |\
- PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
- PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
- PSDMR_WRC_1C | /* 1 clock + 7nSec */
- EAMUX |\
- BUFCMD) |\
- caslatency |\
- ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
- (sdam << 24) |\
- (bsma << 21) |\
- (sda10 << 18);
-#endif
- /*printf("psdmr = 0x%08x\n", psdmr);*/
-
- /*
- * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
- *
- * "At system reset, initialization software must set up the
- * programmable parameters in the memory controller banks registers
- * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
- * system software should execute the following initialization sequence
- * for each SDRAM device.
- *
- * 1. Issue a PRECHARGE-ALL-BANKS command
- * 2. Issue eight CBR REFRESH commands
- * 3. Issue a MODE-SET command to initialize the mode register
- *
- * Quote from Micron MT48LC8M16A2 data sheet:
- *
- * "...the SDRAM requires a 100uS delay prior to issuing any
- * command other than a COMMAND INHIBIT or NOP. Starting at some
- * point during this 100uS period and continuing at least through
- * the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied."
- *
- * "Once the 100uS delay has been satisfied with at least one COMMAND
- * INHIBIT or NOP command having been applied, a /PRECHARGE command/
- * should be applied. All banks must then be precharged, thereby
- * placing the device in the all banks idle state."
- *
- * "Once in the idle state, /two/ AUTO REFRESH cycles must be
- * performed. After the AUTO REFRESH cycles are complete, the
- * SDRAM is ready for mode register programming."
- *
- * (/emphasis/ mine, gvb)
- *
- * The way I interpret this, Micron start up sequence is:
- * 1. Issue a PRECHARGE-BANK command (initial precharge)
- * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
- * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
- * 4. Issue a MODE-SET command to initialize the mode register
- *
- * --------
- *
- * The initial commands are executed by setting P/LSDMR[OP] and
- * accessing the SDRAM with a single-byte transaction."
- *
- * The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
- */
-
- memctl->memc_mptpr = CFG_MPTPR;
- memctl->memc_psrt = psrt;
-
- memctl->memc_br2 = CFG_BR2_PRELIM;
- memctl->memc_or2 = or;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
-
- /*
- * Do it a second time for the second set of chips if the DIMM has
- * two chip selects (double sided).
- */
- if(chipselects > 1)
- {
- ramaddr += sdram_size;
-
- memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
- memctl->memc_or3 = or;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
- *ramaddr = c;
- }
-
- /* print info */
- printf("SDRAM configuration read from SPD\n");
- printf("\tSize per side = %dMB\n", sdram_size >> 20);
- printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
- printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
-#if(CONFIG_PBI == 0) /* bank-based interleaving */
- printf(", Using Bank Based Interleave\n");
-#else
- printf(", Using Page Based Interleave\n");
-#endif
- printf("\tTotal size: ");
-
- /* this delay only needed for original 16MB DIMM...
- * Not needed for any other memory configuration */
- if ((sdram_size * chipselects) == (16 *1024 *1024))
- udelay (250000);
- return (sdram_size * chipselects);
- /*return (16 * 1024 * 1024);*/
-}
-
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
COBJS-y += cmd_sata.o
COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
+COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o
COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o
COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o
COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o
"must RESET the board to recover.\n");
do_reset (cmdtp, flag, argc, argv);
}
-#ifdef CONFIG_OF_HAS_UBOOT_ENV
- if (fdt_env(of_flat_tree) < 0) {
- puts ("ERROR: /u-boot-env node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
-#endif
-#ifdef CONFIG_OF_HAS_BD_T
- if (fdt_bd_t(of_flat_tree) < 0) {
- puts ("ERROR: /bd_t node create failed - "
- "must RESET the board to recover.\n");
- do_reset (cmdtp, flag, argc, argv);
- }
-#endif
#ifdef CONFIG_OF_BOARD_SETUP
/* Call the board-specific fixup routine */
ft_board_setup(of_flat_tree, gd->bd);
/* Create a chosen node */
else if (argv[1][0] == 'c')
fdt_chosen(fdt, 0, 0, 1);
-
-#ifdef CONFIG_OF_HAS_UBOOT_ENV
- /* Create a u-boot-env node */
- else if (argv[1][0] == 'e')
- fdt_env(fdt);
-#endif
-#ifdef CONFIG_OF_HAS_BD_T
- /* Create a bd_t node */
- else if (argv[1][0] == 'b')
- fdt_bd_t(fdt);
-#endif
else {
/* Unrecognized command */
printf ("Usage:\n%s\n", cmdtp->usage);
"fdt rsvmem add <addr> <size> - Add a mem reserve\n"
"fdt rsvmem delete <index> - Delete a mem reserves\n"
"fdt chosen - Add/update the /chosen branch in the tree\n"
-#ifdef CONFIG_OF_HAS_UBOOT_ENV
- "fdt env - Add/replace the /u-boot-env branch in the tree\n"
-#endif
-#ifdef CONFIG_OF_HAS_BD_T
- "fdt bd_t - Add/replace the /bd_t branch in the tree\n"
-#endif
"NOTE: If the path or property you are setting/printing has a '#' character\n"
" or spaces, you MUST escape it with a \\ character or quote it with \".\n"
);
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file provides a shell like 'expr' function to return.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+
+int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong a, b;
+ char buf[16];
+
+ /* Validate arguments */
+ if ((argc != 5) || (strlen(argv[3]) != 1)) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ a = simple_strtoul(argv[2], NULL, 16);
+ b = simple_strtoul(argv[4], NULL, 16);
+
+ switch (argv[3][0]) {
+ case '|': sprintf(buf, "%lx", (a | b)); break;
+ case '&': sprintf(buf, "%lx", (a & b)); break;
+ case '+': sprintf(buf, "%lx", (a + b)); break;
+ case '^': sprintf(buf, "%lx", (a ^ b)); break;
+ case '-': sprintf(buf, "%lx", (a - b)); break;
+ case '*': sprintf(buf, "%lx", (a * b)); break;
+ case '/': sprintf(buf, "%lx", (a / b)); break;
+ case '%': sprintf(buf, "%lx", (a % b)); break;
+ default:
+ printf("invalid op\n");
+ return 1;
+ }
+
+ setenv(argv[1], buf);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setexpr, 5, 0, do_setexpr,
+ "setexpr - set environment variable as the result of eval expression\n",
+ "name value1 <op> value2\n"
+ " - set environment variable 'name' to the result of the evaluated\n"
+ " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n"
+);
*/
struct fdt_header *fdt;
-/********************************************************************/
/**
* fdt_find_and_setprop: Find a node and set it's property
return err;
}
-/********************************************************************/
-
-#ifdef CONFIG_OF_HAS_UBOOT_ENV
-
-/* Function that returns a character from the environment */
-extern uchar(*env_get_char) (int);
-
-
-int fdt_env(void *fdt)
-{
- int nodeoffset;
- int err;
- int k, nxt;
- int i;
- static char tmpenv[256];
-
- err = fdt_check_header(fdt);
- if (err < 0) {
- printf("fdt_env: %s\n", fdt_strerror(err));
- return err;
- }
-
- /*
- * See if we already have a "u-boot-env" node, delete it if so.
- * Then create a new empty node.
- */
- nodeoffset = fdt_path_offset (fdt, "/u-boot-env");
- if (nodeoffset >= 0) {
- err = fdt_del_node(fdt, nodeoffset);
- if (err < 0) {
- printf("fdt_env: %s\n", fdt_strerror(err));
- return err;
- }
- }
- /*
- * Create a new node "/u-boot-env" (offset 0 is root level)
- */
- nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env");
- if (nodeoffset < 0) {
- printf("WARNING: could not create /u-boot-env %s.\n",
- fdt_strerror(nodeoffset));
- return nodeoffset;
- }
-
- for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
- char *s, *lval, *rval;
-
- /*
- * Find the end of the name=definition
- */
- for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
- ;
- s = tmpenv;
- for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
- *s++ = env_get_char(k);
- *s++ = '\0';
- lval = tmpenv;
- /*
- * Find the first '=': it separates the name from the value
- */
- s = strchr(tmpenv, '=');
- if (s != NULL) {
- *s++ = '\0';
- rval = s;
- } else
- continue;
- err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1);
- if (err < 0) {
- printf("WARNING: could not set %s %s.\n",
- lval, fdt_strerror(err));
- return err;
- }
- }
- return 0;
-}
-#endif /* ifdef CONFIG_OF_HAS_UBOOT_ENV */
-
-/********************************************************************/
-
-#ifdef CONFIG_OF_HAS_BD_T
-
-#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
-
-static const struct {
- const char *name;
- int offset;
-} bd_map[] = {
- BDM(memstart),
- BDM(memsize),
- BDM(flashstart),
- BDM(flashsize),
- BDM(flashoffset),
- BDM(sramstart),
- BDM(sramsize),
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
- || defined(CONFIG_E500)
- BDM(immr_base),
-#endif
-#if defined(CONFIG_MPC5xxx)
- BDM(mbar_base),
-#endif
-#if defined(CONFIG_MPC83XX)
- BDM(immrbar),
-#endif
-#if defined(CONFIG_MPC8220)
- BDM(mbar_base),
- BDM(inpfreq),
- BDM(pcifreq),
- BDM(pevfreq),
- BDM(flbfreq),
- BDM(vcofreq),
-#endif
- BDM(bootflags),
- BDM(ip_addr),
- BDM(intfreq),
- BDM(busfreq),
-#ifdef CONFIG_CPM2
- BDM(cpmfreq),
- BDM(brgfreq),
- BDM(sccfreq),
- BDM(vco),
-#endif
-#if defined(CONFIG_MPC5xxx)
- BDM(ipbfreq),
- BDM(pcifreq),
-#endif
- BDM(baudrate),
-};
-
-
-int fdt_bd_t(void *fdt)
-{
- bd_t *bd = gd->bd;
- int nodeoffset;
- int err;
- u32 tmp; /* used to set 32 bit integer properties */
- int i;
-
- err = fdt_check_header(fdt);
- if (err < 0) {
- printf("fdt_bd_t: %s\n", fdt_strerror(err));
- return err;
- }
-
- /*
- * See if we already have a "bd_t" node, delete it if so.
- * Then create a new empty node.
- */
- nodeoffset = fdt_path_offset (fdt, "/bd_t");
- if (nodeoffset >= 0) {
- err = fdt_del_node(fdt, nodeoffset);
- if (err < 0) {
- printf("fdt_bd_t: %s\n", fdt_strerror(err));
- return err;
- }
- }
- /*
- * Create a new node "/bd_t" (offset 0 is root level)
- */
- nodeoffset = fdt_add_subnode(fdt, 0, "bd_t");
- if (nodeoffset < 0) {
- printf("WARNING: could not create /bd_t %s.\n",
- fdt_strerror(nodeoffset));
- printf("fdt_bd_t: %s\n", fdt_strerror(nodeoffset));
- return nodeoffset;
- }
- /*
- * Use the string/pointer structure to create the entries...
- */
- for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
- tmp = cpu_to_be32(getenv("bootargs"));
- err = fdt_setprop(fdt, nodeoffset,
- bd_map[i].name, &tmp, sizeof(tmp));
- if (err < 0)
- printf("WARNING: could not set %s %s.\n",
- bd_map[i].name, fdt_strerror(err));
- }
- /*
- * Add a couple of oddball entries...
- */
- err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6);
- if (err < 0)
- printf("WARNING: could not set enetaddr %s.\n",
- fdt_strerror(err));
- err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4);
- if (err < 0)
- printf("WARNING: could not set ethspeed %s.\n",
- fdt_strerror(err));
- return 0;
-}
-#endif /* ifdef CONFIG_OF_HAS_BD_T */
-
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
const void *val, int len, int create)
{
{
int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
char * cpu_path = "/cpus/" OF_CPU;
+#ifdef CONFIG_MPC5xxx_FEC
char * eth_path = "/" OF_SOC "/ethernet@3000";
+#endif
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
bd->bi_busfreq*div, 1);
+#ifdef CONFIG_MPC5xxx_FEC
do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
+#endif
}
#endif
START = start.o kgdb.o
COBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
- fec.o i2c.o interrupts.o lcd.o scc.o \
+ fec.o fdt.o i2c.o interrupts.o lcd.o scc.o \
serial.o speed.o spi.o \
traps.o upatch.o video.o
SOBJS = plprcr_write.o
#endif /* CONFIG_WATCHDOG */
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT)
-void ft_cpu_setup (void *blob, bd_t *bd)
-{
- char * cpu_path = "/cpus/" OF_CPU;
-
- do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
- do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
-}
-#endif /* CONFIG_OF_LIBFDT */
--- /dev/null
+/*
+ * Copyright 2008 (C) Bryan O'Donoghue
+ *
+ * Code copied & edited from Freescale mpc85xx stuff.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "timebase-frequency", get_tbclk(), 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
+ gd->brg_clk, 1);
+
+ /* Fixup ethernet MAC addresses */
+ fdt_fixup_ethernet(blob, bd);
+
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
#endif
+void get_brgclk(uint sccr)
+{
+ uint divider = 0;
+
+ switch((sccr&SCCR_DFBRG11)>>11){
+ case 0:
+ divider = 1;
+ break;
+ case 1:
+ divider = 4;
+ break;
+ case 2:
+ divider = 16;
+ break;
+ case 3:
+ divider = 64;
+ break;
+ }
+ gd->brg_clk = gd->cpu_clk/divider;
+}
+
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
/*
gd->bus_clk = gd->cpu_clk / 2;
}
+ get_brgclk(sccr);
+
return (0);
}
gd->cpu_clk = measure_gclk ();
#endif
+ get_brgclk(immr->im_clkrst.car_sccr);
+
/* if cpu clock <= 66 MHz then set bus division factor to 1,
* otherwise set it to 2
*/
if (maf_id != bram_maf_id || dev_id != bram_dev_id)
return -ENXIO;
+ /* FIXME : Current OneNAND MTD doesn't support Flex-OneNAND */
+ if (dev_id & (1 << 9)) {
+ printk("Not yet support Flex-OneNAND\n");
+ return -ENXIO;
+ }
+
/* Flash device information */
onenand_print_device_info(dev_id, 0);
this->device_id = dev_id;
COBJS-y += 3c589.o
COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o
+COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
COBJS-y += cs8900.o
COBJS-y += dc2114x.o
COBJS-y += dm9000x.o
COBJS-y += macb.o
COBJS-y += mcffec.o
COBJS-y += natsemi.o
-COBJS-y += ne2000.o
+COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o
COBJS-y += netarm_eth.o
COBJS-y += netconsole.o
COBJS-y += ns7520_eth.o
--- /dev/null
+/*
+ * AX88796L(NE2000) support
+ *
+ * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DRIVERS_AX88796L_H__
+#define __DRIVERS_AX88796L_H__
+
+#define DP_DATA (0x10 << 1)
+#define START_PG 0x40 /* First page of TX buffer */
+#define START_PG2 0x48
+#define STOP_PG 0x80 /* Last page +1 of RX ring */
+#define TX_PAGES 12
+#define RX_START (START_PG+TX_PAGES)
+#define RX_END STOP_PG
+
+#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
+#define AX88796L_BYTE_ACCESS 0x00001000
+#define AX88796L_OFFSET 0x00000400
+#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
+ AX88796L_BYTE_ACCESS + AX88796L_OFFSET
+#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
+#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
+
+#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
+#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
+
+#define EECS_HIGH (AX88796L_MEMR |= 0x10)
+#define EECS_LOW (AX88796L_MEMR &= 0xef)
+#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
+#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
+#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
+#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
+#define EEDO ((AX88796L_MEMR & 0x40)>>6)
+
+#define PAGE0_SET (AX88796L_CR &= 0x3f)
+#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
+
+#define BIT_DUMMY 0
+#define MAC_EEP_READ 1
+#define MAC_EEP_WRITE 2
+#define MAC_EEP_ERACE 3
+#define MAC_EEP_EWEN 4
+#define MAC_EEP_EWDS 5
+
+/* R7780MP Specific code */
+#if defined(CONFIG_R7780MP)
+#define ISA_OFFSET 0x1400
+#define DP_IN(_b_, _o_, _d_) (_d_) = \
+ *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
+#define DP_OUT(_b_, _o_, _d_) \
+ *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
+#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
+#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
+#else
+/* Please change for your target boards */
+#define ISA_OFFSET 0x0000
+#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
+#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
+#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
+#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
+#endif
+
+
+/*
+ * Set 1 bit data
+ */
+static void ax88796_bitset(u32 bit)
+{
+ /* DATA1 */
+ if( bit )
+ EEDI_HIGH;
+ else
+ EEDI_LOW;
+
+ EECLK_LOW;
+ udelay(1000);
+ EECLK_HIGH;
+ udelay(1000);
+ EEDI_LOW;
+}
+
+/*
+ * Get 1 bit data
+ */
+static u8 ax88796_bitget(void)
+{
+ u8 bit;
+
+ EECLK_LOW;
+ udelay(1000);
+ /* DATA */
+ bit = EEDO;
+ EECLK_HIGH;
+ udelay(1000);
+
+ return bit;
+}
+
+/*
+ * Send COMMAND to EEPROM
+ */
+static void ax88796_eep_cmd(u8 cmd)
+{
+ ax88796_bitset(BIT_DUMMY);
+ switch(cmd){
+ case MAC_EEP_READ:
+ ax88796_bitset(1);
+ ax88796_bitset(1);
+ ax88796_bitset(0);
+ break;
+
+ case MAC_EEP_WRITE:
+ ax88796_bitset(1);
+ ax88796_bitset(0);
+ ax88796_bitset(1);
+ break;
+
+ case MAC_EEP_ERACE:
+ ax88796_bitset(1);
+ ax88796_bitset(1);
+ ax88796_bitset(1);
+ break;
+
+ case MAC_EEP_EWEN:
+ ax88796_bitset(1);
+ ax88796_bitset(0);
+ ax88796_bitset(0);
+ break;
+
+ case MAC_EEP_EWDS:
+ ax88796_bitset(1);
+ ax88796_bitset(0);
+ ax88796_bitset(0);
+ break;
+ default:
+ break;
+ }
+}
+
+static void ax88796_eep_setaddr(u16 addr)
+{
+ int i ;
+ for( i = 7 ; i >= 0 ; i-- )
+ ax88796_bitset(addr & (1 << i));
+}
+
+/*
+ * Get data from EEPROM
+ */
+static u16 ax88796_eep_getdata(void)
+{
+ ushort data = 0;
+ int i;
+
+ ax88796_bitget(); /* DUMMY */
+ for( i = 0 ; i < 16 ; i++ ){
+ data <<= 1;
+ data |= ax88796_bitget();
+ }
+ return data;
+}
+
+static void ax88796_mac_read(u8 *buff)
+{
+ int i ;
+ u16 data, addr = 0;
+
+ for( i = 0 ; i < 3; i++ )
+ {
+ EECS_HIGH;
+ EEDI_LOW;
+ udelay(1000);
+ /* READ COMMAND */
+ ax88796_eep_cmd(MAC_EEP_READ);
+ /* ADDRESS */
+ ax88796_eep_setaddr(addr++);
+ /* GET DATA */
+ data = ax88796_eep_getdata();
+ *buff++ = (uchar)(data & 0xff);
+ *buff++ = (uchar)((data >> 8) & 0xff);
+ EECLK_LOW;
+ EEDI_LOW;
+ EECS_LOW;
+ }
+}
+
+int get_prom(u8* mac_addr)
+{
+ u8 prom[32];
+ int i;
+
+ ax88796_mac_read(prom);
+ for (i = 0; i < 6; i++){
+ mac_addr[i] = prom[i];
+ }
+ return 1;
+}
+
+#endif /* __DRIVERS_AX88796L_H__ */
--- /dev/null
+/*
+ * Driver for Blackfin On-Chip MAC device
+ *
+ * Copyright (c) 2005-2008 Analog Device, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <command.h>
+#include <malloc.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/emac.h>
+#include <asm/mach-common/bits/pll.h>
+
+#include "bfin_mac.h"
+
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
+
+#undef DEBUG_ETHERNET
+
+#ifdef DEBUG_ETHERNET
+#define DEBUGF(fmt, args...) printf(fmt, ##args)
+#else
+#define DEBUGF(fmt, args...)
+#endif
+
+#define RXBUF_BASE_ADDR 0xFF900000
+#define TXBUF_BASE_ADDR 0xFF800000
+#define TX_BUF_CNT 1
+
+#define TOUT_LOOP 1000000
+
+ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
+ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
+static u16 txIdx; /* index of the current RX buffer */
+static u16 rxIdx; /* index of the current TX buffer */
+
+u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
+
+/* DMAx_CONFIG values at DMA Restart */
+const ADI_DMA_CONFIG_REG rxdmacfg = {
+ .b_DMA_EN = 1, /* enabled */
+ .b_WNR = 1, /* write to memory */
+ .b_WDSIZE = 2, /* wordsize is 32 bits */
+ .b_DMA2D = 0,
+ .b_RESTART = 0,
+ .b_DI_SEL = 0,
+ .b_DI_EN = 0, /* no interrupt */
+ .b_NDSIZE = 5, /* 5 half words is desc size */
+ .b_FLOW = 7 /* large desc flow */
+};
+
+const ADI_DMA_CONFIG_REG txdmacfg = {
+ .b_DMA_EN = 1, /* enabled */
+ .b_WNR = 0, /* read from memory */
+ .b_WDSIZE = 2, /* wordsize is 32 bits */
+ .b_DMA2D = 0,
+ .b_RESTART = 0,
+ .b_DI_SEL = 0,
+ .b_DI_EN = 0, /* no interrupt */
+ .b_NDSIZE = 5, /* 5 half words is desc size */
+ .b_FLOW = 7 /* large desc flow */
+};
+
+int bfin_EMAC_initialize(bd_t *bis)
+{
+ struct eth_device *dev;
+ dev = (struct eth_device *)malloc(sizeof(*dev));
+ if (dev == NULL)
+ hang();
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "Blackfin EMAC");
+
+ dev->iobase = 0;
+ dev->priv = 0;
+ dev->init = bfin_EMAC_init;
+ dev->halt = bfin_EMAC_halt;
+ dev->send = bfin_EMAC_send;
+ dev->recv = bfin_EMAC_recv;
+
+ eth_register(dev);
+
+ return 1;
+}
+
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
+ int length)
+{
+ int i;
+ int result = 0;
+ unsigned int *buf;
+ buf = (unsigned int *)packet;
+
+ if (length <= 0) {
+ printf("Ethernet: bad packet size: %d\n", length);
+ goto out;
+ }
+
+ if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
+ printf("Ethernet: tx DMA error\n");
+ goto out;
+ }
+
+ for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
+ if (i > TOUT_LOOP) {
+ puts("Ethernet: tx time out\n");
+ goto out;
+ }
+ }
+ txbuf[txIdx]->FrmData->NoBytes = length;
+ memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
+ txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
+ *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
+ *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
+ *pEMAC_OPMODE |= TE;
+
+ for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
+ if (i > TOUT_LOOP) {
+ puts("Ethernet: tx error\n");
+ goto out;
+ }
+ }
+ result = txbuf[txIdx]->StatusWord;
+ txbuf[txIdx]->StatusWord = 0;
+ if ((txIdx + 1) >= TX_BUF_CNT)
+ txIdx = 0;
+ else
+ txIdx++;
+ out:
+ DEBUGF("BFIN EMAC send: length = %d\n", length);
+ return result;
+}
+
+static int bfin_EMAC_recv(struct eth_device *dev)
+{
+ int length = 0;
+
+ for (;;) {
+ if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
+ length = -1;
+ break;
+ }
+ if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
+ printf("Ethernet: rx dma overrun\n");
+ break;
+ }
+ if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
+ printf("Ethernet: rx error\n");
+ break;
+ }
+ length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
+ if (length <= 4) {
+ printf("Ethernet: bad frame\n");
+ break;
+ }
+ NetRxPackets[rxIdx] =
+ (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
+ NetReceive(NetRxPackets[rxIdx], length - 4);
+ *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
+ rxbuf[rxIdx]->StatusWord = 0x00000000;
+ if ((rxIdx + 1) >= PKTBUFSRX)
+ rxIdx = 0;
+ else
+ rxIdx++;
+ }
+
+ return length;
+}
+
+/**************************************************************
+ *
+ * Ethernet Initialization Routine
+ *
+ *************************************************************/
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
+{
+ u32 opmode;
+ int dat;
+ int i;
+ DEBUGF("Eth_init: ......\n");
+
+ txIdx = 0;
+ rxIdx = 0;
+
+/* Initialize System Register */
+ if (SetupSystemRegs(&dat) < 0)
+ return -1;
+
+/* Initialize EMAC address */
+ bfin_EMAC_setup_addr(bd);
+
+/* Initialize TX and RX buffer */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ rxbuf[i] = SetupRxBuffer(i);
+ if (i > 0) {
+ rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+ &(rxbuf[i]->Dma[0]);
+ if (i == (PKTBUFSRX - 1))
+ rxbuf[i]->Dma[1].NEXT_DESC_PTR =
+ &(rxbuf[0]->Dma[0]);
+ }
+ }
+ for (i = 0; i < TX_BUF_CNT; i++) {
+ txbuf[i] = SetupTxBuffer(i);
+ if (i > 0) {
+ txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+ &(txbuf[i]->Dma[0]);
+ if (i == (TX_BUF_CNT - 1))
+ txbuf[i]->Dma[1].NEXT_DESC_PTR =
+ &(txbuf[0]->Dma[0]);
+ }
+ }
+
+ /* Set RX DMA */
+ *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
+ *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
+
+ /* Wait MII done */
+ PollMdcDone();
+
+ /* We enable only RX here */
+ /* ASTP : Enable Automatic Pad Stripping
+ PR : Promiscuous Mode for test
+ PSF : Receive frames with total length less than 64 bytes.
+ FDMODE : Full Duplex Mode
+ LB : Internal Loopback for test
+ RE : Receiver Enable */
+ if (dat == FDMODE)
+ opmode = ASTP | FDMODE | PSF;
+ else
+ opmode = ASTP | PSF;
+ opmode |= RE;
+#ifdef CONFIG_BFIN_MAC_RMII
+ opmode |= TE | RMII;
+#endif
+ /* Turn on the EMAC */
+ *pEMAC_OPMODE = opmode;
+ return 0;
+}
+
+static void bfin_EMAC_halt(struct eth_device *dev)
+{
+ DEBUGF("Eth_halt: ......\n");
+ /* Turn off the EMAC */
+ *pEMAC_OPMODE = 0x00000000;
+ /* Turn off the EMAC RX DMA */
+ *pDMA1_CONFIG = 0x0000;
+ *pDMA2_CONFIG = 0x0000;
+
+}
+
+void bfin_EMAC_setup_addr(bd_t *bd)
+{
+ *pEMAC_ADDRLO =
+ bd->bi_enetaddr[0] |
+ bd->bi_enetaddr[1] << 8 |
+ bd->bi_enetaddr[2] << 16 |
+ bd->bi_enetaddr[3] << 24;
+ *pEMAC_ADDRHI =
+ bd->bi_enetaddr[4] |
+ bd->bi_enetaddr[5] << 8;
+}
+
+static void PollMdcDone(void)
+{
+ /* poll the STABUSY bit */
+ while (*pEMAC_STAADD & STABUSY) ;
+}
+
+static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
+{
+ PollMdcDone();
+
+ *pEMAC_STADAT = Data;
+
+ *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+ STAOP | STAIE | STABUSY;
+}
+
+/*********************************************************************************
+ * Read an off-chip register in a PHY through the MDC/MDIO port *
+ *********************************************************************************/
+static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
+{
+ u16 Data;
+
+ PollMdcDone();
+
+ *pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+ STAIE | STABUSY;
+
+ PollMdcDone();
+
+ Data = (u16) * pEMAC_STADAT;
+
+ PHYregs[RegAddr] = Data; /* save shadow copy */
+
+ return Data;
+}
+
+#if 0 /* dead code ? */
+static void SoftResetPHY(void)
+{
+ u16 phydat;
+ /* set the reset bit */
+ WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
+ /* and clear it again */
+ WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
+ do {
+ /* poll until reset is complete */
+ phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
+ } while ((phydat & PHY_RESET) != 0);
+}
+#endif
+
+static int SetupSystemRegs(int *opmode)
+{
+ u16 sysctl, phydat;
+ int count = 0;
+ /* Enable PHY output */
+ *pVR_CTL |= CLKBUFOE;
+ /* Set all the pins to peripheral mode */
+
+#ifndef CONFIG_BFIN_MAC_RMII
+ *pPORTH_FER = 0xFFFF;
+#ifdef __ADSPBF52x__
+ *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
+#endif
+#else
+#if defined(__ADSPBF536__) || defined(__ADSPBF537__)
+ *pPORTH_FER = 0xC373;
+#endif
+#ifdef __ADSPBF52x__
+ *pPORTH_FER = 0x01FF;
+ *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
+#endif
+#endif
+ /* MDC = 2.5 MHz */
+ sysctl = SET_MDCDIV(24);
+ /* Odd word alignment for Receive Frame DMA word */
+ /* Configure checksum support and rcve frame word alignment */
+ sysctl |= RXDWA | RXCKS;
+ *pEMAC_SYSCTL = sysctl;
+ /* auto negotiation on */
+ /* full duplex */
+ /* 100 Mbps */
+ phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
+ WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
+ do {
+ udelay(1000);
+ phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
+ if (count > 3000) {
+ printf
+ ("Link is down, please check your network connection\n");
+ return -1;
+ }
+ count++;
+ } while (!(phydat & 0x0004));
+
+ phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
+
+ if ((phydat & 0x0100) || (phydat & 0x0040))
+ *opmode = FDMODE;
+ else
+ *opmode = 0;
+
+ *pEMAC_MMC_CTL = RSTC | CROLL;
+
+ /* Initialize the TX DMA channel registers */
+ *pDMA2_X_COUNT = 0;
+ *pDMA2_X_MODIFY = 4;
+ *pDMA2_Y_COUNT = 0;
+ *pDMA2_Y_MODIFY = 0;
+
+ /* Initialize the RX DMA channel registers */
+ *pDMA1_X_COUNT = 0;
+ *pDMA1_X_MODIFY = 4;
+ *pDMA1_Y_COUNT = 0;
+ *pDMA1_Y_MODIFY = 0;
+ return 0;
+}
+
+ADI_ETHER_BUFFER *SetupRxBuffer(int no)
+{
+ ADI_ETHER_FRAME_BUFFER *frmbuf;
+ ADI_ETHER_BUFFER *buf;
+ int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
+ int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+ buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
+ frmbuf =
+ (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
+ nobytes_buffer);
+
+ memset(buf, 0x00, nobytes_buffer);
+ buf->FrmData = frmbuf;
+ memset(frmbuf, 0xfe, RECV_BUFSIZE);
+
+ /* set up first desc to point to receive frame buffer */
+ buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+ buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+ buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
+ buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
+ buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
+
+ /* set up second desc to point to status word */
+ buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+ buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
+ buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
+ buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
+ buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
+ buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
+
+ return buf;
+}
+
+ADI_ETHER_BUFFER *SetupTxBuffer(int no)
+{
+ ADI_ETHER_FRAME_BUFFER *frmbuf;
+ ADI_ETHER_BUFFER *buf;
+ int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
+ int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+ buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
+ frmbuf =
+ (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
+ nobytes_buffer);
+
+ memset(buf, 0x00, nobytes_buffer);
+ buf->FrmData = frmbuf;
+ memset(frmbuf, 0x00, RECV_BUFSIZE);
+
+ /* set up first desc to point to receive frame buffer */
+ buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+ buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+ buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
+ buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
+ buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
+
+ /* set up second desc to point to status word */
+ buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+ buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
+ buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
+ buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
+ buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
+ buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
+ buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
+ buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
+
+ return buf;
+}
+
+#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
+int ether_post_test(int flags)
+{
+ uchar buf[64];
+ int i, value = 0;
+ int length;
+
+ printf("\n--------");
+ bfin_EMAC_init(NULL, NULL);
+ /* construct the package */
+ buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
+ buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
+ buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
+ buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
+ buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
+ buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
+ buf[12] = 0x08; /* Type: ARP */
+ buf[13] = 0x06;
+ buf[14] = 0x00; /* Hardware type: Ethernet */
+ buf[15] = 0x01;
+ buf[16] = 0x08; /* Protocal type: IP */
+ buf[17] = 0x00;
+ buf[18] = 0x06; /* Hardware size */
+ buf[19] = 0x04; /* Protocol size */
+ buf[20] = 0x00; /* Opcode: request */
+ buf[21] = 0x01;
+
+ for (i = 0; i < 42; i++)
+ buf[i + 22] = i;
+ printf("--------Send 64 bytes......\n");
+ bfin_EMAC_send(NULL, (volatile void *)buf, 64);
+ for (i = 0; i < 100; i++) {
+ udelay(10000);
+ if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
+ value = 1;
+ break;
+ }
+ }
+ if (value == 0) {
+ printf("--------EMAC can't receive any data\n");
+ eth_halt();
+ return -1;
+ }
+ length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
+ for (i = 0; i < length; i++) {
+ if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
+ printf("--------EMAC receive error data!\n");
+ eth_halt();
+ return -1;
+ }
+ }
+ printf("--------receive %d bytes, matched\n", length);
+ bfin_EMAC_halt(NULL);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
+ *
+ * Copyright (c) 2005-2008 Analog Device, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MAC_H__
+#define __BFIN_MAC_H__
+
+#define PHYADDR 0x01
+#define NO_PHY_REGS 0x20
+
+#define DEFAULT_PHY_PHYID1 0x0007
+#define DEFAULT_PHY_PHYID2 0xC0A3
+#define PHY_MODECTL 0x00
+#define PHY_MODESTAT 0x01
+#define PHY_PHYID1 0x02
+#define PHY_PHYID2 0x03
+#define PHY_ANAR 0x04
+#define PHY_ANLPAR 0x05
+#define PHY_ANER 0x06
+
+#define PHY_RESET 0x8000
+#define PHY_ANEG_EN 0x1000
+#define PHY_DUPLEX 0x0100
+#define PHY_SPD_SET 0x2000
+
+#define RECV_BUFSIZE (0x614)
+
+typedef volatile u32 reg32;
+typedef volatile u16 reg16;
+
+typedef struct ADI_DMA_CONFIG_REG {
+ u16 b_DMA_EN:1; /* 0 Enabled */
+ u16 b_WNR:1; /* 1 Direction */
+ u16 b_WDSIZE:2; /* 2:3 Transfer word size */
+ u16 b_DMA2D:1; /* 4 DMA mode */
+ u16 b_RESTART:1; /* 5 Retain FIFO */
+ u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
+ u16 b_DI_EN:1; /* 7 Data interrupt enabled */
+ u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
+ u16 b_FLOW:3; /* 12:14Flow */
+} ADI_DMA_CONFIG_REG;
+
+typedef struct adi_ether_frame_buffer {
+ u16 NoBytes; /* the no. of following bytes */
+ u8 Dest[6]; /* destination MAC address */
+ u8 Srce[6]; /* source MAC address */
+ u16 LTfield; /* length/type field */
+ u8 Data[0]; /* payload bytes */
+} ADI_ETHER_FRAME_BUFFER;
+/* 16 bytes/struct */
+
+typedef struct dma_descriptor {
+ struct dma_descriptor *NEXT_DESC_PTR;
+ u32 START_ADDR;
+ ADI_DMA_CONFIG_REG CONFIG;
+} DMA_DESCRIPTOR;
+/* 10 bytes/struct in 12 bytes */
+
+typedef struct adi_ether_buffer {
+ DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
+ ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
+ struct adi_ether_buffer *pNext; /* next buffer */
+ struct adi_ether_buffer *pPrev; /* prev buffer */
+ u16 IPHdrChksum; /* the IP header checksum */
+ u16 IPPayloadChksum; /* the IP header and payload checksum */
+ volatile u32 StatusWord; /* the frame status word */
+} ADI_ETHER_BUFFER;
+/* 40 bytes/struct in 44 bytes */
+
+static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
+static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
+static void bfin_EMAC_halt(struct eth_device *dev);
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
+static int bfin_EMAC_recv(struct eth_device *dev);
+
+static void PollMdcDone(void);
+static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
+static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
+static int SetupSystemRegs(int *opmode);
+
+static void bfin_EMAC_setup_addr(bd_t *bd);
+
+#endif
#include <net.h>
#include <malloc.h>
-#ifdef CONFIG_DRIVER_NE2000
-
-/* wor around udelay resetting OCR */
-static void my_udelay(long us) {
- long tmo;
-
- tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */
- while (get_timer (0) < tmo);
-}
-
-#define mdelay(n) my_udelay((n)*1000)
-
+#define mdelay(n) udelay((n)*1000)
/* forward definition of function used for the uboot interface */
void uboot_push_packet_len(int len);
void uboot_push_tx_done(int key, int val);
-/* timeout for tx/rx in s */
-#define TOUT 5
-
-#define ETHER_ADDR_LEN 6
-
/*
------------------------------------------------------------------------
Debugging details
#if DEBUG & 1
#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
+#define PRINTK(args...) printf(args)
#else
#define DEBUG_FUNCTION() do {} while(0)
#define DEBUG_LINE() do {} while(0)
+#define PRINTK(args...)
#endif
-#include "ne2000.h"
+/* NE2000 base header file */
+#include "ne2000_base.h"
-#if DEBUG & 1
-#define PRINTK(args...) printf(args)
+#if defined(CONFIG_DRIVER_AX88796L)
+/* AX88796L support */
+#include "ax88796.h"
#else
-#define PRINTK(args...)
+/* Basic NE2000 chip support */
+#include "ne2000.h"
#endif
static dp83902a_priv_data_t nic; /* just one instance of the card supported */
dp83902a_init(void)
{
dp83902a_priv_data_t *dp = &nic;
- cyg_uint8* base;
- int i;
+ u8* base;
DEBUG_FUNCTION();
DEBUG_LINE();
+#if defined(NE2000_BASIC_INIT)
+ /* AX88796L doesn't need */
/* Prepare ESA */
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */
/* Use the address from the serial EEPROM */
dp->esa[4],
dp->esa[5] );
+#endif /* NE2000_BASIC_INIT */
return true;
}
dp83902a_stop(void)
{
dp83902a_priv_data_t *dp = &nic;
- cyg_uint8 *base = dp->base;
+ u8 *base = dp->base;
DEBUG_FUNCTION();
the hardware ready to send/receive packets.
*/
static void
-dp83902a_start(unsigned char * enaddr)
+dp83902a_start(u8 * enaddr)
{
dp83902a_priv_data_t *dp = &nic;
- cyg_uint8 *base = dp->base;
+ u8 *base = dp->base;
int i;
DEBUG_FUNCTION();
dp->tx1 = dp->tx2 = 0;
dp->tx_next = dp->tx_buf1;
dp->tx_started = false;
+ dp->running = true;
DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */
DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */
dp->rx_next = dp->rx_buf_start-1;
+ dp->running = true;
DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */
DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */
DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */
+ dp->running = true;
for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ /* FIXME */
+ //*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + 0x1400)) = enaddr[i];
DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
}
/* Enable and start device */
DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
dp->running = true;
+
}
/*
dp83902a_start_xmit(int start_page, int len)
{
dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
- cyg_uint8 *base = dp->base;
+ u8 *base = dp->base;
DEBUG_FUNCTION();
that there is free buffer space (dp->tx_next).
*/
static void
-dp83902a_send(unsigned char *data, int total_len, unsigned long key)
+dp83902a_send(u8 *data, int total_len, u32 key)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- cyg_uint8 *base = dp->base;
+ u8 *base = dp->base;
int len, start_page, pkt_len, i, isr;
#if DEBUG & 4
int dx;
/* but the code is extended a bit to do what Hitachi's monitor */
/* does (i.e., also read data). */
- cyg_uint16 tmp;
+ u16 tmp;
int len = 1;
DP_OUT(base, DP_RSAL, 0x100-len);
/* Put data into buffer */
#if DEBUG & 4
- printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len);
+ printf(" sg buf %08lx len %08x\n ", (u32)data, len);
dx = 0;
#endif
while (len > 0) {
printf(" %02x", *data);
if (0 == (++dx % 16)) printf("\n ");
#endif
+
DP_OUT_DATA(dp->data, *data++);
len--;
}
do {
DP_IN(base, DP_ISR, isr);
} while ((isr & DP_ISR_RDC) == 0);
+
/* Then disable DMA */
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
dp83902a_RxEvent(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- cyg_uint8 *base = dp->base;
- unsigned char rsr;
- unsigned char rcv_hdr[4];
+ u8 *base = dp->base;
+ u8 rsr;
+ u8 rcv_hdr[4];
int i, len, pkt, cur;
DEBUG_FUNCTION();
CYGACC_CALL_IF_DELAY_US(10);
#endif
+ /* read header (get data size)*/
for (i = 0; i < sizeof(rcv_hdr);) {
DP_IN_DATA(dp->data, rcv_hdr[i++]);
}
rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
#endif
len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
+
+ /* data read */
uboot_push_packet_len(len);
+
if (rcv_hdr[1] == dp->rx_buf_start)
DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
else
efficient processing in the upper layers of the stack.
*/
static void
-dp83902a_recv(unsigned char *data, int len)
+dp83902a_recv(u8 *data, int len)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- cyg_uint8 *base = dp->base;
+ u8 *base = dp->base;
int i, mlen;
- cyg_uint8 saved_char = 0;
+ u8 saved_char = 0;
bool saved;
#if DEBUG & 4
int dx;
if (data) {
mlen = len;
#if DEBUG & 4
- printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen);
+ printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
dx = 0;
#endif
while (0 < mlen) {
}
{
- cyg_uint8 tmp;
+ u8 tmp;
DP_IN_DATA(dp->data, tmp);
#if DEBUG & 4
printf(" %02x", tmp);
dp83902a_TxEvent(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- cyg_uint8 *base = dp->base;
- unsigned char tsr;
- unsigned long key;
+ u8 *base = dp->base;
+ u8 tsr;
+ u32 key;
DEBUG_FUNCTION();
dp83902a_ClearCounters(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- cyg_uint8 *base = dp->base;
- cyg_uint8 cnt1, cnt2, cnt3;
+ u8 *base = dp->base;
+ u8 cnt1, cnt2, cnt3;
DP_IN(base, DP_FER, cnt1);
DP_IN(base, DP_CER, cnt2);
dp83902a_Overflow(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
- cyg_uint8 *base = dp->base;
- cyg_uint8 isr;
+ u8 *base = dp->base;
+ u8 isr;
/* Issue a stop command and wait 1.6ms for it to complete. */
DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
dp83902a_poll(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- cyg_uint8 *base = dp->base;
- unsigned char isr;
+ u8 *base = dp->base;
+ u8 isr;
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
DP_IN(base, DP_ISR, isr);
/* find prom (taken from pc_net_cs.c from Linux) */
#include "8390.h"
-
+/*
typedef struct hw_info_t {
u_int offset;
u_char a0, a1, a2;
u_int flags;
} hw_info_t;
-
+*/
#define DELAY_OUTPUT 0x01
#define HAS_MISC_REG 0x02
#define USE_BIG_BUF 0x04
static hw_info_t default_info = { 0, 0, 0, 0, 0 };
-unsigned char dev_addr[6];
+u8 dev_addr[6];
#define PCNET_CMD 0x00
#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */
-unsigned long nic_base;
-
-static void pcnet_reset_8390(void)
-{
- int i, r;
-
- PRINTK("nic base is %lx\n", nic_base);
-
- n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
- n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
- n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
- n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-
- n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
-
- for (i = 0; i < 100; i++) {
- if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
- break;
- PRINTK("got %x in reset\n", r);
- my_udelay(100);
- }
- n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
-
- if (i == 100)
- printf("pcnet_reset_8390() did not complete.\n");
-} /* pcnet_reset_8390 */
-
-static hw_info_t * get_prom(void ) {
- unsigned char prom[32];
- int i, j;
- struct {
- u_char value, offset;
- } program_seq[] = {
- {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
- {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
- {0x00, EN0_RCNTLO}, /* Clear the count regs. */
- {0x00, EN0_RCNTHI},
- {0x00, EN0_IMR}, /* Mask completion irq. */
- {0xFF, EN0_ISR},
- {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
- {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
- {32, EN0_RCNTLO},
- {0x00, EN0_RCNTHI},
- {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
- {0x00, EN0_RSARHI},
- {E8390_RREAD+E8390_START, E8390_CMD},
- };
-
- PRINTK("trying to get MAC via prom reading\n");
-
- pcnet_reset_8390();
-
- mdelay(10);
-
- for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
- n2k_outb(program_seq[i].value, program_seq[i].offset);
-
- PRINTK("PROM:");
- for (i = 0; i < 32; i++) {
- prom[i] = n2k_inb(PCNET_DATAPORT);
- PRINTK(" %02x", prom[i]);
- }
- PRINTK("\n");
- for (i = 0; i < NR_INFO; i++) {
- if ((prom[0] == hw_info[i].a0) &&
- (prom[2] == hw_info[i].a1) &&
- (prom[4] == hw_info[i].a2)) {
- PRINTK("matched board %d\n", i);
- break;
- }
- }
- if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
- for (j = 0; j < 6; j++)
- dev_addr[j] = prom[j<<1];
- PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
- PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]);
- return (i < NR_INFO) ? hw_info+i : &default_info;
- }
- return NULL;
-}
+u32 nic_base;
/* U-boot specific routines */
-
-
-static unsigned char *pbuf = NULL;
+static u8 *pbuf = NULL;
static int pkey = -1;
static int initialized=0;
}
dp83902a_recv(&pbuf[0], len);
- /* Just pass it to the upper layer */
+ /*Just pass it to the upper layer*/
NetReceive(&pbuf[0], len);
}
#ifdef CONFIG_DRIVER_NE2000_CCR
{
- volatile unsigned char *p = (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR;
+ vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
PRINTK("CCR before is %x\n", *p);
*p = CONFIG_DRIVER_NE2000_VAL;
#endif
nic_base = CONFIG_DRIVER_NE2000_BASE;
- nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE;
+ nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
- r = get_prom();
+ r = get_prom(dev_addr);
if (!r)
return -1;
PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
setenv ("ethaddr", ethaddr);
-
-#define DP_DATA 0x10
nic.data = nic.base + DP_DATA;
- nic.tx_buf1 = 0x40;
- nic.tx_buf2 = 0x48;
- nic.rx_buf_start = 0x50;
- nic.rx_buf_end = 0x80;
+ nic.tx_buf1 = START_PG;
+ nic.tx_buf2 = START_PG2;
+ nic.rx_buf_start = RX_START;
+ nic.rx_buf_end = RX_END;
if (dp83902a_init() == false)
return -1;
+
dp83902a_start(dev_addr);
initialized=1;
+
return 0;
}
void eth_halt() {
+
PRINTK("### eth_halt\n");
if(initialized)
dp83902a_stop();
pkey = -1;
- dp83902a_send((unsigned char *) packet, length, 666);
+ dp83902a_send((u8 *) packet, length, 666);
tmo = get_timer (0) + TOUT * CFG_HZ;
while(1) {
dp83902a_poll();
}
return 0;
}
-#endif
*/
/*
- ------------------------------------------------------------------------
- Macros for accessing DP registers
- These can be overridden by the platform header
-*/
-
-#define DP_IN(_b_, _o_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
-#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)
-
-#define DP_IN_DATA(_b_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)))
-#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)
-
-
-/* here is all the data */
-
-#define cyg_uint8 unsigned char
-#define cyg_uint16 unsigned short
-#define bool int
-
-#define false 0
-#define true 1
-
-#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
-#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
-
-typedef struct dp83902a_priv_data {
- cyg_uint8* base;
- cyg_uint8* data;
- cyg_uint8* reset;
- int tx_next; /* First free Tx page */
- int tx_int; /* Expecting interrupt from this buffer */
- int rx_next; /* First free Rx page */
- int tx1, tx2; /* Page numbers for Tx buffers */
- unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */
- int tx1_len, tx2_len;
- bool tx_started, running, hardwired_esa;
- cyg_uint8 esa[6];
- void* plf_priv;
-
- /* Buffer allocation */
- int tx_buf1, tx_buf2;
- int rx_buf_start, rx_buf_end;
-} dp83902a_priv_data_t;
-
-/*
- ------------------------------------------------------------------------
- Some forward declarations
-*/
-static void dp83902a_poll(void);
-
-/* ------------------------------------------------------------------------ */
-/* Register offsets */
-
-#define DP_CR 0x00
-#define DP_CLDA0 0x01
-#define DP_PSTART 0x01 /* write */
-#define DP_CLDA1 0x02
-#define DP_PSTOP 0x02 /* write */
-#define DP_BNDRY 0x03
-#define DP_TSR 0x04
-#define DP_TPSR 0x04 /* write */
-#define DP_NCR 0x05
-#define DP_TBCL 0x05 /* write */
-#define DP_FIFO 0x06
-#define DP_TBCH 0x06 /* write */
-#define DP_ISR 0x07
-#define DP_CRDA0 0x08
-#define DP_RSAL 0x08 /* write */
-#define DP_CRDA1 0x09
-#define DP_RSAH 0x09 /* write */
-#define DP_RBCL 0x0a /* write */
-#define DP_RBCH 0x0b /* write */
-#define DP_RSR 0x0c
-#define DP_RCR 0x0c /* write */
-#define DP_FER 0x0d
-#define DP_TCR 0x0d /* write */
-#define DP_CER 0x0e
-#define DP_DCR 0x0e /* write */
-#define DP_MISSED 0x0f
-#define DP_IMR 0x0f /* write */
-#define DP_DATAPORT 0x10 /* "eprom" data port */
-
-#define DP_P1_CR 0x00
-#define DP_P1_PAR0 0x01
-#define DP_P1_PAR1 0x02
-#define DP_P1_PAR2 0x03
-#define DP_P1_PAR3 0x04
-#define DP_P1_PAR4 0x05
-#define DP_P1_PAR5 0x06
-#define DP_P1_CURP 0x07
-#define DP_P1_MAR0 0x08
-#define DP_P1_MAR1 0x09
-#define DP_P1_MAR2 0x0a
-#define DP_P1_MAR3 0x0b
-#define DP_P1_MAR4 0x0c
-#define DP_P1_MAR5 0x0d
-#define DP_P1_MAR6 0x0e
-#define DP_P1_MAR7 0x0f
-
-#define DP_P2_CR 0x00
-#define DP_P2_PSTART 0x01
-#define DP_P2_CLDA0 0x01 /* write */
-#define DP_P2_PSTOP 0x02
-#define DP_P2_CLDA1 0x02 /* write */
-#define DP_P2_RNPP 0x03
-#define DP_P2_TPSR 0x04
-#define DP_P2_LNPP 0x05
-#define DP_P2_ACH 0x06
-#define DP_P2_ACL 0x07
-#define DP_P2_RCR 0x0c
-#define DP_P2_TCR 0x0d
-#define DP_P2_DCR 0x0e
-#define DP_P2_IMR 0x0f
-
-/* Command register - common to all pages */
-
-#define DP_CR_STOP 0x01 /* Stop: software reset */
-#define DP_CR_START 0x02 /* Start: initialize device */
-#define DP_CR_TXPKT 0x04 /* Transmit packet */
-#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
-#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
-#define DP_CR_SEND 0x18 /* Send packet */
-#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
-#define DP_CR_PAGE0 0x00 /* Page select */
-#define DP_CR_PAGE1 0x40
-#define DP_CR_PAGE2 0x80
-#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
-
-/* Data configuration register */
-
-#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
-#define DP_DCR_BOS 0x02 /* 1=Little Endian */
-#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
-#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
-#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
-#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
-#define DP_DCR_FIFO_2 0x20
-#define DP_DCR_FIFO_4 0x40
-#define DP_DCR_FIFO_6 0x60
-
-#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
-
-/* Interrupt status register */
-
-#define DP_ISR_RxP 0x01 /* Packet received */
-#define DP_ISR_TxP 0x02 /* Packet transmitted */
-#define DP_ISR_RxE 0x04 /* Receive error */
-#define DP_ISR_TxE 0x08 /* Transmit error */
-#define DP_ISR_OFLW 0x10 /* Receive overflow */
-#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
-#define DP_ISR_RDC 0x40 /* Remote DMA complete */
-#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
-
-/* Interrupt mask register */
-
-#define DP_IMR_RxP 0x01 /* Packet received */
-#define DP_IMR_TxP 0x02 /* Packet transmitted */
-#define DP_IMR_RxE 0x04 /* Receive error */
-#define DP_IMR_TxE 0x08 /* Transmit error */
-#define DP_IMR_OFLW 0x10 /* Receive overflow */
-#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
-#define DP_IMR_RDC 0x40 /* Remote DMA complete */
-
-#define DP_IMR_All 0x3F /* Everything but remote DMA */
-
-/* Receiver control register */
-
-#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
-#define DP_RCR_AR 0x02 /* Accept runt packets */
-#define DP_RCR_AB 0x04 /* Accept broadcast packets */
-#define DP_RCR_AM 0x08 /* Accept multicast packets */
-#define DP_RCR_PROM 0x10 /* Promiscuous mode */
-#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
-
-/* Receiver status register */
-
-#define DP_RSR_RxP 0x01 /* Packet received */
-#define DP_RSR_CRC 0x02 /* CRC error */
-#define DP_RSR_FRAME 0x04 /* Framing error */
-#define DP_RSR_FO 0x08 /* FIFO overrun */
-#define DP_RSR_MISS 0x10 /* Missed packet */
-#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
-#define DP_RSR_DIS 0x40 /* Receiver disabled */
-#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
-
-/* Transmitter control register */
-
-#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
-#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
-#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
-#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
-#define DP_TCR_OUTLOOP 0x08 /* External loopback */
-#define DP_TCR_ATD 0x10 /* Auto transmit disable */
-#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
-
-/* Transmit status register */
-
-#define DP_TSR_TxP 0x01 /* Packet transmitted */
-#define DP_TSR_COL 0x04 /* Collision (at least one) */
-#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
-#define DP_TSR_CRS 0x10 /* Lost carrier */
-#define DP_TSR_FU 0x20 /* FIFO underrun */
-#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
-#define DP_TSR_OWC 0x80 /* Collision outside normal window */
-
-#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
-#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
+ * NE2000 support header file.
+ * Created by Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#ifndef __DRIVERS_NE2000_H__
+#define __DRIVERS_NE2000_H__
+
+/* Enable NE2000 basic init function */
+#define NE2000_BASIC_INIT
+
+#define DP_DATA 0x10
+#define START_PG 0x50 /* First page of TX buffer */
+#define STOP_PG 0x80 /* Last page +1 of RX ring */
+
+#define RX_START 0x50
+#define RX_END 0x80
+
+#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_)))
+#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_)
+#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_)))
+#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_)
+
+static void pcnet_reset_8390(void)
+{
+ int i, r;
+
+ PRINTK("nic base is %lx\n", nic_base);
+
+ n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+ PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+ n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
+ PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+ n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+ PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+ n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+
+ n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
+
+ for (i = 0; i < 100; i++) {
+ if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
+ break;
+ PRINTK("got %x in reset\n", r);
+ udelay(100);
+ }
+ n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
+
+ if (i == 100)
+ printf("pcnet_reset_8390() did not complete.\n");
+} /* pcnet_reset_8390 */
+
+int get_prom(u8* mac_addr)
+{
+ u8 prom[32];
+ int i, j;
+ struct {
+ u_char value, offset;
+ } program_seq[] = {
+ {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
+ {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
+ {0x00, EN0_RCNTLO}, /* Clear the count regs. */
+ {0x00, EN0_RCNTHI},
+ {0x00, EN0_IMR}, /* Mask completion irq. */
+ {0xFF, EN0_ISR},
+ {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
+ {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
+ {32, EN0_RCNTLO},
+ {0x00, EN0_RCNTHI},
+ {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
+ {0x00, EN0_RSARHI},
+ {E8390_RREAD+E8390_START, E8390_CMD},
+ };
+
+ PRINTK("trying to get MAC via prom reading\n");
+
+ pcnet_reset_8390();
+
+ mdelay(10);
+
+ for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
+ n2k_outb(program_seq[i].value, program_seq[i].offset);
+
+ PRINTK("PROM:");
+ for (i = 0; i < 32; i++) {
+ prom[i] = n2k_inb(PCNET_DATAPORT);
+ PRINTK(" %02x", prom[i]);
+ }
+ PRINTK("\n");
+ for (i = 0; i < NR_INFO; i++) {
+ if ((prom[0] == hw_info[i].a0) &&
+ (prom[2] == hw_info[i].a1) &&
+ (prom[4] == hw_info[i].a2)) {
+ PRINTK("matched board %d\n", i);
+ break;
+ }
+ }
+ if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
+ PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
+ PRINTK("MAC address is ");
+ for (j = 0; j < 6; j++){
+ mac_addr[j] = prom[j<<1];
+ PRINTK("%02x:",mac_addr[i]);
+ }
+ PRINTK("\n");
+ return (i < NR_INFO) ? i : 0;
+ }
+ return NULL;
+}
+
+
+#endif /* __DRIVERS_NE2000_H__ */
--- /dev/null
+/*
+Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+
+==========================================================================
+
+ dev/dp83902a.h
+
+ National Semiconductor DP83902a ethernet chip
+
+==========================================================================
+####ECOSGPLCOPYRIGHTBEGIN####
+ -------------------------------------------
+ This file is part of eCos, the Embedded Configurable Operating System.
+ Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+
+ eCos is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 2 or (at your option) any later version.
+
+ eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with eCos; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+ As a special exception, if other files instantiate templates or use macros
+ or inline functions from this file, or you compile this file and link it
+ with other works to produce a work based on this file, this file does not
+ by itself cause the resulting work to be covered by the GNU General Public
+ License. However the source code for this file must still be made available
+ in accordance with section (3) of the GNU General Public License.
+
+ This exception does not invalidate any other reasons why a work based on
+ this file might be covered by the GNU General Public License.
+
+ Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ at http://sources.redhat.com/ecos/ecos-license/
+ -------------------------------------------
+####ECOSGPLCOPYRIGHTEND####
+####BSDCOPYRIGHTBEGIN####
+
+ -------------------------------------------
+
+ Portions of this software may have been derived from OpenBSD or other sources,
+ and are covered by the appropriate copyright disclaimers included herein.
+
+ -------------------------------------------
+
+####BSDCOPYRIGHTEND####
+==========================================================================
+#####DESCRIPTIONBEGIN####
+
+ Author(s): gthomas
+ Contributors: gthomas, jskov
+ Date: 2001-06-13
+ Purpose:
+ Description:
+
+####DESCRIPTIONEND####
+
+==========================================================================
+
+*/
+
+/*
+ ------------------------------------------------------------------------
+ Macros for accessing DP registers
+ These can be overridden by the platform header
+*/
+
+#define bool int
+
+#define false 0
+#define true 1
+
+/* timeout for tx/rx in s */
+#define TOUT 5
+/* Ether MAC address size */
+#define ETHER_ADDR_LEN 6
+
+
+#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
+#define CYGACC_CALL_IF_DELAY_US(X) udelay(X)
+
+/* H/W infomation struct */
+typedef struct hw_info_t {
+ u32 offset;
+ u8 a0, a1, a2;
+ u32 flags;
+} hw_info_t;
+
+typedef struct dp83902a_priv_data {
+ u8* base;
+ u8* data;
+ u8* reset;
+ int tx_next; /* First free Tx page */
+ int tx_int; /* Expecting interrupt from this buffer */
+ int rx_next; /* First free Rx page */
+ int tx1, tx2; /* Page numbers for Tx buffers */
+ u32 tx1_key, tx2_key; /* Used to ack when packet sent */
+ int tx1_len, tx2_len;
+ bool tx_started, running, hardwired_esa;
+ u8 esa[6];
+ void* plf_priv;
+
+ /* Buffer allocation */
+ int tx_buf1, tx_buf2;
+ int rx_buf_start, rx_buf_end;
+} dp83902a_priv_data_t;
+
+/*
+ ------------------------------------------------------------------------
+ Some forward declarations
+*/
+int get_prom( u8* mac_addr);
+static void dp83902a_poll(void);
+
+/* ------------------------------------------------------------------------ */
+/* Register offsets */
+
+#define DP_CR 0x00
+#define DP_CLDA0 0x01
+#define DP_PSTART 0x01 /* write */
+#define DP_CLDA1 0x02
+#define DP_PSTOP 0x02 /* write */
+#define DP_BNDRY 0x03
+#define DP_TSR 0x04
+#define DP_TPSR 0x04 /* write */
+#define DP_NCR 0x05
+#define DP_TBCL 0x05 /* write */
+#define DP_FIFO 0x06
+#define DP_TBCH 0x06 /* write */
+#define DP_ISR 0x07
+#define DP_CRDA0 0x08
+#define DP_RSAL 0x08 /* write */
+#define DP_CRDA1 0x09
+#define DP_RSAH 0x09 /* write */
+#define DP_RBCL 0x0a /* write */
+#define DP_RBCH 0x0b /* write */
+#define DP_RSR 0x0c
+#define DP_RCR 0x0c /* write */
+#define DP_FER 0x0d
+#define DP_TCR 0x0d /* write */
+#define DP_CER 0x0e
+#define DP_DCR 0x0e /* write */
+#define DP_MISSED 0x0f
+#define DP_IMR 0x0f /* write */
+#define DP_DATAPORT 0x10 /* "eprom" data port */
+
+#define DP_P1_CR 0x00
+#define DP_P1_PAR0 0x01
+#define DP_P1_PAR1 0x02
+#define DP_P1_PAR2 0x03
+#define DP_P1_PAR3 0x04
+#define DP_P1_PAR4 0x05
+#define DP_P1_PAR5 0x06
+#define DP_P1_CURP 0x07
+#define DP_P1_MAR0 0x08
+#define DP_P1_MAR1 0x09
+#define DP_P1_MAR2 0x0a
+#define DP_P1_MAR3 0x0b
+#define DP_P1_MAR4 0x0c
+#define DP_P1_MAR5 0x0d
+#define DP_P1_MAR6 0x0e
+#define DP_P1_MAR7 0x0f
+
+#define DP_P2_CR 0x00
+#define DP_P2_PSTART 0x01
+#define DP_P2_CLDA0 0x01 /* write */
+#define DP_P2_PSTOP 0x02
+#define DP_P2_CLDA1 0x02 /* write */
+#define DP_P2_RNPP 0x03
+#define DP_P2_TPSR 0x04
+#define DP_P2_LNPP 0x05
+#define DP_P2_ACH 0x06
+#define DP_P2_ACL 0x07
+#define DP_P2_RCR 0x0c
+#define DP_P2_TCR 0x0d
+#define DP_P2_DCR 0x0e
+#define DP_P2_IMR 0x0f
+
+/* Command register - common to all pages */
+
+#define DP_CR_STOP 0x01 /* Stop: software reset */
+#define DP_CR_START 0x02 /* Start: initialize device */
+#define DP_CR_TXPKT 0x04 /* Transmit packet */
+#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
+#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
+#define DP_CR_SEND 0x18 /* Send packet */
+#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
+#define DP_CR_PAGE0 0x00 /* Page select */
+#define DP_CR_PAGE1 0x40
+#define DP_CR_PAGE2 0x80
+#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
+
+/* Data configuration register */
+
+#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
+#define DP_DCR_BOS 0x02 /* 1=Little Endian */
+#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
+#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
+#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
+#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
+#define DP_DCR_FIFO_2 0x20
+#define DP_DCR_FIFO_4 0x40
+#define DP_DCR_FIFO_6 0x60
+
+#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
+
+/* Interrupt status register */
+
+#define DP_ISR_RxP 0x01 /* Packet received */
+#define DP_ISR_TxP 0x02 /* Packet transmitted */
+#define DP_ISR_RxE 0x04 /* Receive error */
+#define DP_ISR_TxE 0x08 /* Transmit error */
+#define DP_ISR_OFLW 0x10 /* Receive overflow */
+#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
+#define DP_ISR_RDC 0x40 /* Remote DMA complete */
+#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
+
+/* Interrupt mask register */
+
+#define DP_IMR_RxP 0x01 /* Packet received */
+#define DP_IMR_TxP 0x02 /* Packet transmitted */
+#define DP_IMR_RxE 0x04 /* Receive error */
+#define DP_IMR_TxE 0x08 /* Transmit error */
+#define DP_IMR_OFLW 0x10 /* Receive overflow */
+#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
+#define DP_IMR_RDC 0x40 /* Remote DMA complete */
+
+#define DP_IMR_All 0x3F /* Everything but remote DMA */
+
+/* Receiver control register */
+
+#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
+#define DP_RCR_AR 0x02 /* Accept runt packets */
+#define DP_RCR_AB 0x04 /* Accept broadcast packets */
+#define DP_RCR_AM 0x08 /* Accept multicast packets */
+#define DP_RCR_PROM 0x10 /* Promiscuous mode */
+#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
+
+/* Receiver status register */
+
+#define DP_RSR_RxP 0x01 /* Packet received */
+#define DP_RSR_CRC 0x02 /* CRC error */
+#define DP_RSR_FRAME 0x04 /* Framing error */
+#define DP_RSR_FO 0x08 /* FIFO overrun */
+#define DP_RSR_MISS 0x10 /* Missed packet */
+#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
+#define DP_RSR_DIS 0x40 /* Receiver disabled */
+#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
+
+/* Transmitter control register */
+
+#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
+#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
+#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
+#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
+#define DP_TCR_OUTLOOP 0x08 /* External loopback */
+#define DP_TCR_ATD 0x10 /* Auto transmit disable */
+#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
+
+/* Transmit status register */
+
+#define DP_TSR_TxP 0x01 /* Packet transmitted */
+#define DP_TSR_COL 0x04 /* Collision (at least one) */
+#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
+#define DP_TSR_CRS 0x10 /* Lost carrier */
+#define DP_TSR_FU 0x20 /* FIFO underrun */
+#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
+#define DP_TSR_OWC 0x80 /* Collision outside normal window */
+
+#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
+#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
#ifdef CONFIG_ADNPESC1
#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
#elif CONFIG_BLACKFIN
-#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;})
+#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;})
#else
#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
#endif
#ifdef CONFIG_ADNPESC1
#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
#elif CONFIG_BLACKFIN
-#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");}
+#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();}
#else
#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
#endif
COBJS-y += m41t11.o
COBJS-y += m41t60.o
COBJS-$(CONFIG_RTC_M41T62) += m41t62.o
-COBJS-y += max6900.o
COBJS-y += m48t35ax.o
COBJS-y += max6900.o
COBJS-y += mc146818.o
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
+ unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
+#if defined(CONFIG_8xx)
+ unsigned long brg_clk;
+#endif
#if defined(CONFIG_CPM2)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SETEXPR /* setexpr support */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SNTP /* SNTP support */
#define CONFIG_CMD_SPI /* SPI utility */
#define CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
#endif /* __CONFIG_H */
#define OF_CPU "PowerPC,MPC870@0"
#define OF_TBCLK (MPC8XX_HZ / 16)
-#define CONFIG_OF_HAS_BD_T 1
-#define CONFIG_OF_HAS_UBOOT_ENV 1
#endif /* __CONFIG_H */
const void *val, int len, int create);
void fdt_fixup_qe_firmware(void *fdt);
-#ifdef CONFIG_OF_HAS_UBOOT_ENV
-int fdt_env(void *fdt);
-#endif
-
-#ifdef CONFIG_OF_HAS_BD_T
-int fdt_bd_t(void *fdt);
-#endif
-
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
*/
len = (ulong)&_end - CFG_MONITOR_BASE;
+#ifndef CONFIG_MAX_MEM_MAPPED
+#define CONFIG_MAX_MEM_MAPPED (256 << 20)
+#endif
+
+#ifndef CONFIG_VERY_BIG_RAM
addr = CFG_SDRAM_BASE + get_effective_memsize();
+#else
+ /* only allow stack below 256M */
+ addr = CFG_SDRAM_BASE +
+ (gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+ CONFIG_MAX_MEM_MAPPED : get_effective_memsize();
+#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
CFLAGS += -DCONFIG_ONENAND_IPL
OBJCLFAGS += --gap-fill=0x00
-SOBJS = start.o low_levelinit.o # _memcpy32.o
+SOBJS = start.o low_levelinit.o
COBJS = apollon.o onenand_read.o onenand_boot.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
onenandobj := $(OBJTREE)/onenand_ipl/
-ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin
+ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin
all: $(obj).depend $(ALL)
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
+$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@
+
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
buf = (uchar *) CFG_LOAD_ADDR;
- if (!onenand_read_block(buf, ONENAND_START_BLOCK))
+ if (!onenand_read_block0(buf))
buf += ONENAND_BLOCK_SIZE;
if (buf == (uchar *)CFG_LOAD_ADDR)
#include <linux/mtd/onenand_regs.h>
-#define ONENAND_START_BLOCK 0
#define ONENAND_BLOCK_SIZE 2048
#ifndef CFG_PRINTF
#define ONENAND_PAGE_SIZE 2048
-extern int onenand_read_block(unsigned char *buf, ulong block);
+extern int onenand_read_block0(unsigned char *buf);
#endif
#define onenand_buffer_address() ((1 << 3) << 8)
#define onenand_bufferram_address(block) (0)
+#ifdef __HAVE_ARCH_MEMCPY32
+extern void *memcpy32(void *dest, void *src, int size);
+#endif
+
/* read a page with ECC */
-static inline int onenand_read_page(ulong block, ulong page, u_char *buf)
+static inline int onenand_read_page(ulong block, ulong page,
+ u_char * buf, int pagesize)
{
unsigned long *base;
onenand_writew(onenand_block_address(block),
THIS_ONENAND(ONENAND_REG_START_ADDRESS1));
+ onenand_writew(onenand_bufferram_address(block),
+ THIS_ONENAND(ONENAND_REG_START_ADDRESS2));
+
onenand_writew(onenand_sector_address(page),
THIS_ONENAND(ONENAND_REG_START_ADDRESS8));
onenand_writew(onenand_buffer_address(),
THIS_ONENAND(ONENAND_REG_START_BUFFER));
- onenand_writew(onenand_bufferram_address(block),
- THIS_ONENAND(ONENAND_REG_START_ADDRESS2));
-
onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT));
onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND));
#ifdef __HAVE_ARCH_MEMCPY32
/* 32 bytes boundary memory copy */
- memcpy32(buf, base, ONENAND_PAGE_SIZE);
+ memcpy32(buf, base, pagesize);
#else
- for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) {
+ for (offset = 0; offset < (pagesize >> 2); offset++) {
value = *(base + offset);
*p++ = value;
}
* onenand_read_block - Read a block data to buf
* @return 0 on success
*/
-int onenand_read_block(unsigned char *buf, ulong block)
+int onenand_read_block0(unsigned char *buf)
{
int page, offset = 0;
+ int pagesize = ONENAND_PAGE_SIZE;
+
+ /* MLC OneNAND has 4KiB page size */
+ if (onenand_readw(THIS_ONENAND(ONENAND_REG_TECHNOLOGY)))
+ pagesize <<= 1;
/* NOTE: you must read page from page 1 of block 0 */
/* read the block page by page*/
for (page = ONENAND_START_PAGE;
page < ONENAND_PAGES_PER_BLOCK; page++) {
- onenand_read_page(block, page, buf + offset);
-
- offset += ONENAND_PAGE_SIZE;
+ onenand_read_page(0, page, buf + offset, pagesize);
+ offset += pagesize;
}
return 0;
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