]> git.sur5r.net Git - u-boot/commitdiff
tny_a9260/tny_a9g20: update board to the new AT91 organization
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thu, 4 Aug 2011 02:48:56 +0000 (02:48 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 3 Sep 2011 20:40:44 +0000 (22:40 +0200)
Cc: Albin Tonnerre <tonnerrealbin@gmail.com>
CC: Gregory Hermant <gregory.hermant@calao-systems.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
MAKEALL
Makefile
board/calao/tny_a9260/tny_a9260.c
boards.cfg
include/configs/tny_a9260.h

diff --git a/MAKEALL b/MAKEALL
index 0ec668522dab3912d34c3d0430640afef3687312..7e748d60f9417a1b7be645331fe0dfdd41bae5f8 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -446,8 +446,6 @@ LIST_ARMV7="                \
 LIST_at91="$(boards_by_soc at91)\
        at91sam9m10g45ek        \
        pm9g45                  \
-       TNY_A9260               \
-       TNY_A9G20               \
 "
 
 #########################################################################
index 47dc73f9f37cc09bbe6038a820a97ad00b572061..f478ec6053575c6a70fffd5f52aafe3acf15c925 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -827,16 +827,6 @@ pm9g45_config      :       unconfig
        @mkdir -p $(obj)include
        @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
 
-TNY_A9G20_NANDFLASH_config \
-TNY_A9G20_EEPROM_config \
-TNY_A9G20_config \
-TNY_A9260_NANDFLASH_config \
-TNY_A9260_EEPROM_config \
-TNY_A9260_config       :       unconfig
-       @mkdir -p $(obj)include
-       @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
-       @$(MKCONFIG) -n $@ -a tny_a9260 arm arm926ejs tny_a9260 calao at91
-
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
 integratorap_config    \
index d51ca150ccdfff72f64d27321306cf92478837b4..ab51a335a0263a27f422a51c56e4891c07b18a8f 100644 (file)
  */
 
 #include <common.h>
-#include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -45,33 +43,36 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void tny_a9260_nand_hw_init(void)
 {
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
        unsigned long csa;
 
-       /* Enable CS3 */
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA,
-                      csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       /* Assign CS3 to NAND/SmartMedia Interface */
+       csa = readl(&matrix->ebicsa);
+       csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+       writel(csa, &matrix->ebicsa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-       at91_sys_write(AT91_SMC_MODE(3),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+               &smc->cs[3].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+               AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-                      AT91_SMC_DBW_16 |
+               AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-                      AT91_SMC_DBW_8 |
+               AT91_SMC_MODE_DBW_8 |
 #endif
-                      AT91_SMC_TDF_(2));
+               AT91_SMC_MODE_TDF_CYCLE(2),
+               &smc->cs[3].mode);
 
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+       writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
        /* Configure RDY/BSY */
        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -91,9 +92,9 @@ int board_init(void)
        gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20;
 #endif
        /* adress of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-       at91_serial_hw_init();
+       at91_seriald_hw_init();
        tny_a9260_nand_hw_init();
        at91_spi0_hw_init(1 << 5);
        return 0;
@@ -101,10 +102,8 @@ int board_init(void)
 
 int dram_init(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM;
-       if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
-               return -1;
-
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size(
+               (void *)CONFIG_SYS_SDRAM_BASE,
+               CONFIG_SYS_SDRAM_SIZE);
        return 0;
 }
index 89d4c7a59051b990d1a9c90376718d2ce53856c1..6e9ab9b1a9b851a4c2c5c18a5179edaa748d6381 100644 (file)
@@ -104,6 +104,10 @@ snapper9260                  arm         arm926ejs   -                   bluewat
 snapper9g20                  arm         arm926ejs   snapper9260         bluewater      at91        snapper9260:AT91SAM9G20
 sbc35_a9g20_nandflash        arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
 sbc35_a9g20_eeprom           arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
+tny_a9g20_nandflash          arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH
+tny_a9g20_eeprom             arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9G20,SYS_USE_EEPROM
+tny_a9260_nandflash          arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH
+tny_a9260_eeprom             arm         arm926ejs   tny_a9260           calao          at91        tny_a9260:AT91SAM9260,SYS_USE_EEPROM
 cpu9260                      arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260
 cpu9260_nand                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,NANDBOOT
 cpu9260_128M                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,CPU9260_128M
index 7b18022c6e36c7f10a31d453aeba86f37bad8182..986aebaae447252f75c07518ffa8ed504b3bcfa3 100644 (file)
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
-#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
-#define CONFIG_TNY_A9260
-#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
-#define CONFIG_TNY_A9G20
-#endif
-
-#ifdef CONFIG_TNY_A9260
-#define CONFIG_AT91SAM9260
-#else
-#define CONFIG_AT91SAM9G20
-#endif
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
 
 #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_IS_IN_EEPROM
 #endif
 
+/* Define actual evaluation board type from used processor type */
+#ifdef CONFIG_AT91SAM9G20
+# define CONFIG_TNY_A9G20
+#else
+# define CONFIG_TNY_A9260
+#endif
+
 /* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK     32768           /* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK     12000000        /* 12 MHz crystal */
-#define CONFIG_SYS_HZ          1000
+#define CONFIG_SYS_HZ                  1000
 
-#define CONFIG_ARM926EJS       1       /* This is an ARM926EJS Core */
 #define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
-
-#define CONFIG_CMDLINE_TAG     1       /* enable passing of ATAGs      */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG      1
-
+#define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO       1
-#define CONFIG_ATMEL_USART     1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3          1       /* USART 3 is DBGU */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE              ATMEL_BASE_DBGU
+#define        CONFIG_USART_ID                 ATMEL_ID_SYS
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
 
 #define CONFIG_BOOTDELAY       3
 
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 #undef CONFIG_CMD_SOURCE
 #undef CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS           1
-#define PHYS_SDRAM                     0x20000000
-#define PHYS_SDRAM_SIZE                        0x04000000      /* 64 megs */
+#define CONFIG_SYS_SDRAM_BASE          ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE          0x04000000      /* 64 megs */
+# define CONFIG_SYS_INIT_SP_ADDR \
+       (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
 
 /* SPI EEPROM */
 #define CONFIG_SPI
 #define CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE             1
-#define CONFIG_SYS_NAND_BASE                   0x40000000
-#define CONFIG_SYS_NAND_DBW_8                  1
+#define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PC13
 
 /* NOR flash - no real flash on this board */
-#define CONFIG_SYS_NO_FLASH                    1
+#define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_DOS_PARTITION           1
-#define CONFIG_CMD_FAT                 1
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
 
 #define CONFIG_SYS_LOAD_ADDR                   0x22000000      /* load address */
 
-#define CONFIG_SYS_MEMTEST_START               PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START               CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END                 0x23e00000
 
 /* Env in EEPROM, bootstrap + u-boot in NAND*/
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_OFFSET              0x20
-#define CONFIG_ENV_SIZE                0x1000
+#define CONFIG_ENV_SIZE                        0x1000
 #endif
 
 /* Env, bootstrap and u-boot in NAND */
 #ifdef CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
-#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET               0x60000
+#define CONFIG_ENV_OFFSET_REDUND        0x80000
+#define CONFIG_ENV_SIZE                 0x20000
 #endif
 
 #define CONFIG_BOOTCOMMAND     "nboot 0x21000000 0 400000"
                                "120M(rootfs),-(other) " \
                                "rw rootfstype=jffs2"
 
-#define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
-
 #define CONFIG_SYS_PROMPT      "U-Boot> "
 #define CONFIG_SYS_CBSIZE      256
 #define CONFIG_SYS_MAXARGS     16
 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP    1
-#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
 
 /*
  * Size of malloc() pool