]> git.sur5r.net Git - u-boot/commitdiff
fpga: xilinx: zynqmp: Add PL bitstream download support for ZynqMP
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Wed, 13 Jan 2016 10:55:37 +0000 (16:25 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 22 Sep 2016 05:33:21 +0000 (07:33 +0200)
Add PL bitstream dowload support for ZynqMP
Bitstream will be validated by uboot and loaded
to PL by invoking an smc instruction to ATF which route this request to
PMU FW which will take care of loading it to PL

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
13 files changed:
configs/xilinx_zynqmp_ep_defconfig
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
configs/xilinx_zynqmp_zcu102_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig
drivers/fpga/Kconfig
drivers/fpga/Makefile
drivers/fpga/xilinx.c
drivers/fpga/zynqmppl.c [new file with mode: 0644]
include/xilinx.h
include/zynqmppl.h [new file with mode: 0644]

index 196eb6974e1f361d6bb1fb0e5fe51384b37fa0df..e7dc1c6f8dbfafcb20916be028d167c806c03d27 100644 (file)
@@ -46,6 +46,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
index a3fb226e9183400868d8de7e86cc9dfe4e8d00f2..6afacd2d91aac103c24e80dc5ef24e2f2a62d1be 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
index aec4f9b3ee63b220729db9f523ce4a9453b57389..4068c28818e90313168a717713d560a32992c169 100644 (file)
@@ -41,6 +41,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
index 0b2ebb1a54b06ce457b412d7833f9ecc905f0a2e..5116ff3c38819720757a6e1e5b01c2c31fc0d0fd 100644 (file)
@@ -34,6 +34,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
index f570b2aa424a34f09b6745e2f23fc6061509df36..1a27bd06ab927686de35a16ed323c1d1fde43782 100644 (file)
@@ -33,6 +33,8 @@ CONFIG_OF_EMBED=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_CADENCE=y
index 8fcb2fd3eed1db4ea0ecce1fee910737dfa65857..78db9d9f13cd253ad1466e2d1916198d2c420566 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_MMC_OPS=y
index b7ba599a091577ca2cbd92314336e65d58ac003c..62762820b79848162b6e9d536d8140718669312f 100644 (file)
@@ -38,6 +38,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BLK=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_DM_MMC_OPS=y
index 1ba02f09825aeb5b87788f42ddce4b10586797b3..f3f6bf7f6747fc214f9456a0edea8d48a4826ff2 100644 (file)
@@ -1,3 +1,20 @@
 menu "FPGA support"
 
+config FPGA
+       bool
+
+config FPGA_XILINX
+       bool "Enable Xilinx FPGA drivers"
+       select FPGA
+       help
+         Enable Xilinx FPGA specific functions which includes bitstream
+         (in BIT format), fpga and device validation.
+
+config FPGA_ZYNQMPPL
+       bool "Enable Xilinx FPGA driver for ZynqMP"
+       depends on FPGA_XILINX
+       help
+         Enable FPGA driver for loading bitstream in BIT and BIN format
+         on Xilinx Zynq UltraScale+ (ZynqMP) device.
+
 endmenu
index fec3fecbdfbf0e8b06a37bf332f1237458f84240..777706f186dd0b8fb1913ccc0029d77d72be83d2 100644 (file)
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
 obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
 obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
 obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
+obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
 obj-$(CONFIG_FPGA_XILINX) += xilinx.o
 obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
 ifdef CONFIG_FPGA_ALTERA
index d459a2f7a572180954bdc34a82fcf39c32be868e..2cd0104d8b154b35f8c85de42e50028ad614d57a 100644 (file)
@@ -199,6 +199,9 @@ int xilinx_info(xilinx_desc *desc)
                case xilinx_zynq:
                        printf("Zynq PL\n");
                        break;
+               case xilinx_zynqmp:
+                       printf("ZynqMP PL\n");
+                       break;
                        /* Add new family types here */
                default:
                        printf ("Unknown family type, %d\n", desc->family);
@@ -227,6 +230,9 @@ int xilinx_info(xilinx_desc *desc)
                case devcfg:
                        printf("Device configuration interface (Zynq)\n");
                        break;
+               case csu_dma:
+                       printf("csu_dma configuration interface (ZynqMP)\n");
+                       break;
                        /* Add new interface types here */
                default:
                        printf ("Unsupported interface type, %d\n", desc->iface);
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
new file mode 100644 (file)
index 0000000..23039c3
--- /dev/null
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2015 - 2016, Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <console.h>
+#include <common.h>
+#include <zynqmppl.h>
+#include <linux/sizes.h>
+
+#define DUMMY_WORD     0xffffffff
+
+/* Xilinx binary format header */
+static const u32 bin_format[] = {
+       DUMMY_WORD, /* Dummy words */
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       DUMMY_WORD,
+       0x000000bb, /* Sync word */
+       0x11220044, /* Sync word */
+       DUMMY_WORD,
+       DUMMY_WORD,
+       0xaa995566, /* Sync word */
+};
+
+#define SWAP_NO                1
+#define SWAP_DONE      2
+
+/*
+ * Load the whole word from unaligned buffer
+ * Keep in your mind that it is byte loading on little-endian system
+ */
+static u32 load_word(const void *buf, u32 swap)
+{
+       u32 word = 0;
+       u8 *bitc = (u8 *)buf;
+       int p;
+
+       if (swap == SWAP_NO) {
+               for (p = 0; p < 4; p++) {
+                       word <<= 8;
+                       word |= bitc[p];
+               }
+       } else {
+               for (p = 3; p >= 0; p--) {
+                       word <<= 8;
+                       word |= bitc[p];
+               }
+       }
+
+       return word;
+}
+
+static u32 check_header(const void *buf)
+{
+       u32 i, pattern;
+       int swap = SWAP_NO;
+       u32 *test = (u32 *)buf;
+
+       debug("%s: Let's check bitstream header\n", __func__);
+
+       /* Checking that passing bin is not a bitstream */
+       for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
+               pattern = load_word(&test[i], swap);
+
+               /*
+                * Bitstreams in binary format are swapped
+                * compare to regular bistream.
+                * Do not swap dummy word but if swap is done assume
+                * that parsing buffer is binary format
+                */
+               if ((__swab32(pattern) != DUMMY_WORD) &&
+                   (__swab32(pattern) == bin_format[i])) {
+                       swap = SWAP_DONE;
+                       debug("%s: data swapped - let's swap\n", __func__);
+               }
+
+               debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
+                     &test[i], pattern, bin_format[i]);
+       }
+       debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
+             buf, swap == SWAP_NO ? "without" : "with");
+
+       return swap;
+}
+
+static void *check_data(u8 *buf, size_t bsize, u32 *swap)
+{
+       u32 word, p = 0; /* possition */
+
+       /* Because buf doesn't need to be aligned let's read it by chars */
+       for (p = 0; p < bsize; p++) {
+               word = load_word(&buf[p], SWAP_NO);
+               debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
+
+               /* Find the first bitstream dummy word */
+               if (word == DUMMY_WORD) {
+                       debug("%s: Found dummy word at position %x/%px\n",
+                             __func__, p, &buf[p]);
+                       *swap = check_header(&buf[p]);
+                       if (*swap) {
+                               /* FIXME add full bitstream checking here */
+                               return &buf[p];
+                       }
+               }
+               /* Loop can be huge - support CTRL + C */
+               if (ctrlc())
+                       return NULL;
+       }
+       return NULL;
+}
+
+static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+       u32 *new_buf;
+       u32 i;
+
+       if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
+               new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
+
+               /*
+                * This might be dangerous but permits to flash if
+                * ARCH_DMA_MINALIGN is greater than header size
+                */
+               if (new_buf > (u32 *)buf) {
+                       debug("%s: Aligned buffer is after buffer start\n",
+                             __func__);
+                       new_buf -= ARCH_DMA_MINALIGN;
+               }
+               printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
+                      buf, new_buf, swap);
+
+               for (i = 0; i < (len/4); i++)
+                       new_buf[i] = load_word(&buf[i], swap);
+
+               buf = new_buf;
+       } else if (swap != SWAP_DONE) {
+               /* For bitstream which are aligned */
+               u32 *new_buf = (u32 *)buf;
+
+               printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+                      swap);
+
+               for (i = 0; i < (len/4); i++)
+                       new_buf[i] = load_word(&buf[i], swap);
+       }
+
+       return (ulong)buf;
+}
+
+static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
+                                  size_t bsize, u32 blocksize, u32 *swap)
+{
+       ulong *buf_start;
+       ulong diff;
+
+       buf_start = check_data((u8 *)buf, blocksize, swap);
+
+       if (!buf_start)
+               return FPGA_FAIL;
+
+       /* Check if data is postpone from start */
+       diff = (ulong)buf_start - (ulong)buf;
+       if (diff) {
+               printf("%s: Bitstream is not validated yet (diff %lx)\n",
+                      __func__, diff);
+               return FPGA_FAIL;
+       }
+
+       if ((ulong)buf < SZ_1M) {
+               printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
+                      __func__, buf);
+               return FPGA_FAIL;
+       }
+
+       return 0;
+}
+
+static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
+{
+       struct pt_regs regs;
+       regs.regs[0] = id;
+       regs.regs[1] = reg0;
+       regs.regs[2] = reg1;
+       regs.regs[3] = reg2;
+
+       smc_call(&regs);
+
+       return regs.regs[0];
+}
+
+static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
+                    bitstream_type bstype)
+{
+       u32 swap;
+       ulong bin_buf, flags;
+       int ret;
+
+       if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
+               return FPGA_FAIL;
+
+       bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
+
+       debug("%s called!\n", __func__);
+       flush_dcache_range(bin_buf, bin_buf + bsize);
+
+       if (bsize % 4)
+               bsize = bsize / 4 + 1;
+       else
+               bsize = bsize / 4;
+
+       flags = (u32)bsize | ((u64)bstype << 32);
+
+       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
+       if (ret)
+               debug("PL FPGA LOAD fail\n");
+
+       return ret;
+}
+
+struct xilinx_fpga_op zynqmp_op = {
+       .load = zynqmp_load,
+};
index aebcb3bfdf29d7f87e4701fd01387bfe8f95b34a..d2a2ea71e1211a4b8382c3ec29297e86b9288984 100644 (file)
@@ -21,6 +21,7 @@ typedef enum {                        /* typedef xilinx_iface */
        master_selectmap,       /* master SelectMap (virtex2)           */
        slave_selectmap,        /* slave SelectMap (virtex2)            */
        devcfg,                 /* devcfg interface (zynq) */
+       csu_dma,                /* csu_dma interface (zynqmp) */
        max_xilinx_iface_type   /* insert all new types before this */
 } xilinx_iface;                        /* end, typedef xilinx_iface */
 
@@ -31,6 +32,7 @@ typedef enum {                        /* typedef xilinx_family */
        xilinx_virtex2,         /* Virtex2 Family */
        xilinx_spartan3,        /* Spartan-III Family */
        xilinx_zynq,            /* Zynq Family */
+       xilinx_zynqmp,          /* ZynqMP Family */
        max_xilinx_type         /* insert all new types before this */
 } xilinx_family;               /* end, typedef xilinx_family */
 
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
new file mode 100644 (file)
index 0000000..002ee2a
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Xilinx, Inc,
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef _ZYNQMPPL_H_
+#define _ZYNQMPPL_H_
+
+#include <xilinx.h>
+
+#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD            0xC2000016
+#define ZYNQMP_FPGA_OP_INIT                    (1 << 0)
+#define ZYNQMP_FPGA_OP_LOAD                    (1 << 1)
+#define ZYNQMP_FPGA_OP_DONE                    (1 << 2)
+
+extern struct xilinx_fpga_op zynqmp_op;
+
+#define XILINX_ZYNQMP_DESC \
+{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+
+#endif /* _ZYNQMPPL_H_ */