]> git.sur5r.net Git - u-boot/commitdiff
Add support for AMCC 440SPe CPU based eval board (Yucca).
authorMarian Balakowicz <m8@semihalf.com>
Fri, 30 Jun 2006 14:30:46 +0000 (16:30 +0200)
committerMarian Balakowicz <m8@semihalf.com>
Fri, 30 Jun 2006 14:30:46 +0000 (16:30 +0200)
31 files changed:
CHANGELOG
MAKEALL
Makefile
board/amcc/yucca/Makefile [new file with mode: 0644]
board/amcc/yucca/cmd_yucca.c [new file with mode: 0644]
board/amcc/yucca/config.mk [new file with mode: 0644]
board/amcc/yucca/flash.c [new file with mode: 0644]
board/amcc/yucca/init.S [new file with mode: 0644]
board/amcc/yucca/u-boot.lds [new file with mode: 0644]
board/amcc/yucca/u-boot.lds.debug [new file with mode: 0644]
board/amcc/yucca/yucca.c [new file with mode: 0644]
board/amcc/yucca/yucca.h [new file with mode: 0644]
common/cmd_bdinfo.c
common/serial.c
cpu/ppc4xx/405gp_pci.c
cpu/ppc4xx/4xx_enet.c
cpu/ppc4xx/cpu.c
cpu/ppc4xx/interrupts.c
cpu/ppc4xx/miiphy.c
cpu/ppc4xx/serial.c
cpu/ppc4xx/speed.c
cpu/ppc4xx/start.S
cpu/ppc4xx/vecnum.h
drivers/pci_indirect.c
include/405_mal.h
include/asm-ppc/mmu.h
include/asm-ppc/processor.h
include/common.h
include/configs/yucca.h [new file with mode: 0644]
include/ppc440.h
include/ppc4xx_enet.h

index a326f7ddfa3fda5c00841758844197ad8e21cc2b..865648d3efcf7ac30a49335960853f28c1e65a78 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Add support for AMCC 440SPe CPU based eval board (Yucca).
+
 * Call serial_initialize() before first debug() is used.
 
 * Changes to Yellowstone & Yosemite 440EP/GR eval boards:
diff --git a/MAKEALL b/MAKEALL
index fcbab47cab7c8aee706799f50c94d1676170e6c3..937b4db0248b64ec1dd90484d52be8cd204eefd7 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -74,7 +74,7 @@ LIST_4xx="    \
        PLU405          PMC405          PPChameleonEVB  sbc405          \
        VOH405          VOM405          W7OLMC          W7OLMG          \
        walnut          WUH405          XPEDITE1K       yellowstone     \
-       yosemite                                                        \
+       yosemite        yucca                                           \
 "
 
 #########################################################################
index 9305cab38bb4257e58b9da2d8de3ba1d93182fc2..06e2299b2c75ff536eb9f6eae143cb5af63856f5 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -922,6 +922,9 @@ yosemite_config:    unconfig
 yellowstone_config:    unconfig
        @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
 
+yucca_config:  unconfig
+       @./mkconfig $(@:_config=) ppc ppc4xx yucca amcc
+
 #########################################################################
 ## MPC8220 Systems
 #########################################################################
diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile
new file mode 100644 (file)
index 0000000..c85fa31
--- /dev/null
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o flash.o cmd_yucca.o
+SOBJS  = init.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
new file mode 100644 (file)
index 0000000..9c7afb2
--- /dev/null
@@ -0,0 +1,288 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for evb440spe
+ */
+
+#include <common.h>
+#include <command.h>
+#include "yucca.h"
+#include <i2c.h>
+#include <asm/byteorder.h>
+
+extern void print_evb440spe_info(void);
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, 
+               int flag, int argc, char *argv[]);
+
+extern int cmd_get_data_size(char* arg, int default_size);
+
+/* ------------------------------------------------------------------------- */
+int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       return setBootStrapClock (cmdtp, 1, flag, argc, argv);
+}
+
+/* ------------------------------------------------------------------------- */
+/* Modify memory.
+ *
+ * Syntax:
+ *     evb440spe wrclk prom0,prom1
+ */
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
+               int argc, char *argv[])
+{
+       uchar   chip;
+       ulong   data;
+       int     nbytes;
+       extern char console_buffer[];
+
+       char sysClock[4];
+       char cpuClock[4];
+       char plbClock[4];
+       char pcixClock[4];
+
+       if (argc < 3) {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+
+       if (strcmp(argv[2], "prom0") == 0)
+               chip = IIC0_BOOTPROM_ADDR;
+       else
+               chip = IIC0_ALT_BOOTPROM_ADDR;
+
+       do {
+               printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
+               nbytes = readline (" ? ");
+
+               if (strcmp(console_buffer, "quit") == 0)
+                       return 0;
+
+               if ((strcmp(console_buffer, "33") != 0) &
+                               (strcmp(console_buffer, "66") != 0))
+                       nbytes=0;
+
+               strcpy(sysClock, console_buffer);
+
+       } while (nbytes == 0);
+
+       do {
+               if (strcmp(sysClock, "66") == 0) {
+                       printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
+               } else {
+#ifdef CONFIG_STRESS
+                       printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
+#else
+                       printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
+#endif
+               }
+               nbytes = readline (" ? ");
+
+               if (strcmp(console_buffer, "quit") == 0)
+                       return 0;
+
+               if (strcmp(sysClock, "66") == 0) {
+                       if ((strcmp(console_buffer, "400") != 0) &
+                                       (strcmp(console_buffer, "533") != 0)
+#ifdef CONFIG_STRESS
+                                       & (strcmp(console_buffer, "667") != 0)
+#endif
+                          ) {
+                               nbytes = 0;
+                       }
+               } else {
+                       if ((strcmp(console_buffer, "400") != 0) &
+                                       (strcmp(console_buffer, "500") != 0) &
+                                       (strcmp(console_buffer, "533") != 0)
+#ifdef CONFIG_STRESS
+                                       & (strcmp(console_buffer, "667") != 0)
+#endif
+                          ) {
+                               nbytes = 0;
+                       }
+               }
+
+               strcpy(cpuClock, console_buffer);
+
+       } while (nbytes == 0);
+
+       if (strcmp(cpuClock, "500") == 0){
+               strcpy(plbClock, "166");
+       } else if (strcmp(cpuClock, "533") == 0){
+               strcpy(plbClock, "133");
+       } else {
+               do {
+                       if (strcmp(cpuClock, "400") == 0)
+                               printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
+
+#ifdef CONFIG_STRESS
+                       if (strcmp(cpuClock, "667") == 0)
+                               printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
+
+#endif
+                       nbytes = readline (" ? ");
+
+                       if (strcmp(console_buffer, "quit") == 0)
+                               return 0;
+
+                       if (strcmp(cpuClock, "400") == 0) {
+                               if ((strcmp(console_buffer, "100") != 0) &
+                                               (strcmp(console_buffer, "133") != 0))
+                                       nbytes = 0;
+                       }
+#ifdef CONFIG_STRESS
+                       if (strcmp(cpuClock, "667") == 0) {
+                               if ((strcmp(console_buffer, "133") != 0) &
+                                               (strcmp(console_buffer, "166") != 0))
+                                       nbytes = 0;
+                       }
+#endif
+                       strcpy(plbClock, console_buffer);
+
+               } while (nbytes == 0);
+       }
+
+       do {
+               printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
+               nbytes = readline (" ? ");
+
+               if (strcmp(console_buffer, "quit") == 0)
+                       return 0;
+
+               if ((strcmp(console_buffer, "33") != 0) &
+                               (strcmp(console_buffer, "66") != 0) &
+                               (strcmp(console_buffer, "100") != 0) &
+                               (strcmp(console_buffer, "133") != 0)) {
+                       nbytes = 0;
+               }
+               strcpy(pcixClock, console_buffer);
+
+       } while (nbytes == 0);
+
+       printf("\nsys clk   = %sMhz\n", sysClock);
+       printf("cpu clk   = %sMhz\n", cpuClock);
+       printf("plb clk   = %sMhz\n", plbClock);
+       printf("Pci-X clk = %sMhz\n", pcixClock);
+
+       do {
+               printf("\npress [y] to write I2C bootstrap \n");
+               printf("or [n] to abort.  \n");
+               printf("Don't forget to set board switches \n");
+               printf("according to your choice before re-starting \n");
+               printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+
+               nbytes = readline (" ? ");
+               if (strcmp(console_buffer, "n") == 0)
+                       return 0;
+
+       } while (nbytes == 0);
+
+       if (strcmp(sysClock, "33") == 0) {
+               if ((strcmp(cpuClock, "400") == 0) &
+                               (strcmp(plbClock, "100") == 0))
+                       data = 0x8678c206;
+
+               if ((strcmp(cpuClock, "400") == 0) &
+                               (strcmp(plbClock, "133") == 0))
+                       data = 0x8678c2c6;
+
+               if ((strcmp(cpuClock, "500") == 0))
+                       data = 0x8778f2c6;
+
+               if ((strcmp(cpuClock, "533") == 0))
+                       data = 0x87790252;
+
+#ifdef CONFIG_STRESS
+               if ((strcmp(cpuClock, "667") == 0) &
+                               (strcmp(plbClock, "133") == 0))
+                       data = 0x87794256;
+
+               if ((strcmp(cpuClock, "667") == 0) &
+                               (strcmp(plbClock, "166") == 0))
+                       data = 0x87794206;
+
+#endif
+       }
+       if (strcmp(sysClock, "66") == 0) {
+               if ((strcmp(cpuClock, "400") == 0) &
+                               (strcmp(plbClock, "100") == 0))
+                       data = 0x84706206;
+
+               if ((strcmp(cpuClock, "400") == 0) &
+                               (strcmp(plbClock, "133") == 0))
+                       data = 0x847062c6;
+
+               if ((strcmp(cpuClock, "533") == 0))
+                       data = 0x85708206;
+
+#ifdef CONFIG_STRESS
+               if ((strcmp(cpuClock, "667") == 0) &
+                               (strcmp(plbClock, "133") == 0))
+                       data = 0x8570a256;
+
+               if ((strcmp(cpuClock, "667") == 0) &
+                               (strcmp(plbClock, "166") == 0))
+                       data = 0x8570a206;
+
+#endif
+       }
+
+#ifdef DEBUG
+       printf(" pin strap0 to write in i2c  = %x\n", data);
+#endif /* DEBUG */
+
+       if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
+               printf("Error writing strap0 in %s\n", argv[2]);
+
+       if (strcmp(pcixClock, "33") == 0)
+               data = 0x00000701;
+
+       if (strcmp(pcixClock, "66") == 0)
+               data = 0x00000601;
+
+       if (strcmp(pcixClock, "100") == 0)
+               data = 0x00000501;
+
+       if (strcmp(pcixClock, "133") == 0)
+               data = 0x00000401;
+
+       if (strcmp(plbClock, "166") == 0)
+               data = data | 0x05950000;
+       else
+               data = data | 0x05A50000;
+
+#ifdef DEBUG
+       printf(" pin strap1 to write in i2c  = %x\n", data);
+#endif /* DEBUG */
+
+       udelay(1000);
+       if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
+               printf("Error writing strap1 in %s\n", argv[2]);
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       evb440spe,      3,      1,      do_evb440spe,
+       "evb440spe - program the serial device strap\n",
+       "wrclk [prom0|prom1] - program the serial device strap\n"
+);
diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk
new file mode 100644 (file)
index 0000000..ff454eb
--- /dev/null
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440SPe Reference Platform (yucca) board
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
new file mode 100644 (file)
index 0000000..c5a2e31
--- /dev/null
@@ -0,0 +1,1054 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "yucca.h"
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif                         /* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];  /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+       {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
+       {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
+       {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
+       {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+       {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+       {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
+       {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
+       {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
+       {0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+       int i;
+       int k;
+       int size;
+       int erased;
+       volatile unsigned long *flash;
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf("missing or unknown FLASH type\n");
+               return;
+       }
+
+       switch (info->flash_id & FLASH_VENDMASK) {
+               case FLASH_MAN_AMD:
+                       printf("AMD ");
+                       break;
+               case FLASH_MAN_STM:
+                       printf("STM ");
+                       break;
+               case FLASH_MAN_FUJ:
+                       printf("FUJITSU ");
+                       break;
+               case FLASH_MAN_SST:
+                       printf("SST ");
+                       break;
+               case FLASH_MAN_MX:
+                       printf("MIXC ");
+                       break;
+               default:
+                       printf("Unknown Vendor ");
+                       break;
+       }
+
+       switch (info->flash_id & FLASH_TYPEMASK) {
+               case FLASH_AM040:
+                       printf("AM29F040 (512 Kbit, uniform sector size)\n");
+                       break;
+               case FLASH_AM400B:
+                       printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+                       break;
+               case FLASH_AM400T:
+                       printf("AM29LV400T (4 Mbit, top boot sector)\n");
+                       break;
+               case FLASH_AM800B:
+                       printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+                       break;
+               case FLASH_AM800T:
+                       printf("AM29LV800T (8 Mbit, top boot sector)\n");
+                       break;
+               case FLASH_AMD016:
+                       printf("AM29F016D (16 Mbit, uniform sector size)\n");
+                       break;
+               case FLASH_AM160B:
+                       printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+                       break;
+               case FLASH_AM160T:
+                       printf("AM29LV160T (16 Mbit, top boot sector)\n");
+                       break;
+               case FLASH_AM320B:
+                       printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+                       break;
+               case FLASH_AM320T:
+                       printf("AM29LV320T (32 Mbit, top boot sector)\n");
+                       break;
+               case FLASH_AM033C:
+                       printf("AM29LV033C (32 Mbit, top boot sector)\n");
+                       break;
+               case FLASH_SST800A:
+                       printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+                       break;
+               case FLASH_SST160A:
+                       printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+                       break;
+               case FLASH_STMW320DT:
+                       printf ("M29W320DT (32 M, top sector)\n");
+                       break;
+               case FLASH_MXLV320T:
+                       printf ("MXLV320T (32 Mbit, top sector)\n");
+                       break;
+               default:
+                       printf("Unknown Chip Type\n");
+                       break;
+       }
+
+       printf("  Size: %ld KB in %d Sectors\n",
+                       info->size >> 10, info->sector_count);
+
+       printf("  Sector Start Addresses:");
+       for (i = 0; i < info->sector_count; ++i) {
+               /*
+                * Check if whole sector is erased
+                */
+               if (i != (info->sector_count - 1))
+                       size = info->start[i + 1] - info->start[i];
+               else
+                       size = info->start[0] + info->size - info->start[i];
+               erased = 1;
+               flash = (volatile unsigned long *)info->start[i];
+               size = size >> 2;       /* divide by 4 for longword access */
+               for (k = 0; k < size; k++) {
+                       if (*flash++ != 0xffffffff) {
+                               erased = 0;
+                               break;
+                       }
+               }
+
+               if ((i % 5) == 0)
+                       printf("\n   ");
+               printf(" %08lX%s%s",
+                               info->start[i],
+                               erased ? " E" : "  ",
+                               info->protect[i] ? "RO " : "   ");
+       }
+       printf("\n");
+       return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+       /* bit 0 used for big flash marking */
+       if ((ulong)addr & 0x1)
+               return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+       else
+               return flash_get_size_1(addr, info);
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+       short i;
+       CFG_FLASH_WORD_SIZE value;
+       ulong base = (ulong) addr;
+       volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+       DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+       /* Write auto select command: read Manufacturer ID */
+       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+       addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+       udelay(1000);
+
+       value = addr2[0];
+       DEBUGF("FLASH MANUFACT: %x\n", value);
+
+       switch (value) {
+               case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+                       info->flash_id = FLASH_MAN_AMD;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+                       info->flash_id = FLASH_MAN_FUJ;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+                       info->flash_id = FLASH_MAN_SST;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+                       info->flash_id = FLASH_MAN_STM;
+                       break;
+               default:
+                       info->flash_id = FLASH_UNKNOWN;
+                       info->sector_count = 0;
+                       info->size = 0;
+                       return (0);     /* no or unknown flash  */
+       }
+
+       value = addr2[1];       /* device ID            */
+       DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+       switch (value) {
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+                       info->flash_id += FLASH_AM040;
+                       info->sector_count = 8;
+                       info->size = 0x0080000; /* => 512 ko */
+                       break;
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+                       info->flash_id += FLASH_AM040;
+                       info->sector_count = 8;
+                       info->size = 0x0080000; /* => 512 ko */
+                       break;
+
+               case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+                       info->flash_id += FLASH_AM040;
+                       info->sector_count = 8;
+                       info->size = 0x0080000; /* => 512 ko */
+                       break;
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+                       info->flash_id += FLASH_AMD016;
+                       info->sector_count = 32;
+                       info->size = 0x00200000;
+                       break;          /* => 2 MB              */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+                       info->flash_id += FLASH_AMDLV033C;
+                       info->sector_count = 64;
+                       info->size = 0x00400000;
+                       break;          /* => 4 MB              */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+                       info->flash_id += FLASH_AM400T;
+                       info->sector_count = 11;
+                       info->size = 0x00080000;
+                       break;          /* => 0.5 MB            */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+                       info->flash_id += FLASH_AM400B;
+                       info->sector_count = 11;
+                       info->size = 0x00080000;
+                       break;          /* => 0.5 MB            */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+                       info->flash_id += FLASH_AM800T;
+                       info->sector_count = 19;
+                       info->size = 0x00100000;
+                       break;          /* => 1 MB              */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+                       info->flash_id += FLASH_AM800B;
+                       info->sector_count = 19;
+                       info->size = 0x00100000;
+                       break;          /* => 1 MB              */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+                       info->flash_id += FLASH_AM160T;
+                       info->sector_count = 35;
+                       info->size = 0x00200000;
+                       break;          /* => 2 MB              */
+
+               case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+                       info->flash_id += FLASH_AM160B;
+                       info->sector_count = 35;
+                       info->size = 0x00200000;
+                       break;          /* => 2 MB              */
+
+               default:
+                       info->flash_id = FLASH_UNKNOWN;
+                       return (0);     /* => no or unknown flash */
+       }
+
+       /* set up sector start address table */
+       if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+               for (i = 0; i < info->sector_count; i++)
+                       info->start[i] = base + (i * 0x00010000);
+       } else {
+               if (info->flash_id & FLASH_BTYPE) {
+                       /* set sector offsets for bottom boot block type        */
+                       info->start[0] = base + 0x00000000;
+                       info->start[1] = base + 0x00004000;
+                       info->start[2] = base + 0x00006000;
+                       info->start[3] = base + 0x00008000;
+                       for (i = 4; i < info->sector_count; i++) {
+                               info->start[i] =
+                                       base + (i * 0x00010000) - 0x00030000;
+                       }
+               } else {
+                       /* set sector offsets for top boot block type           */
+                       i = info->sector_count - 1;
+                       info->start[i--] = base + info->size - 0x00004000;
+                       info->start[i--] = base + info->size - 0x00006000;
+                       info->start[i--] = base + info->size - 0x00008000;
+                       for (; i >= 0; i--) {
+                               info->start[i] = base + i * 0x00010000;
+                       }
+               }
+       }
+
+       /* check for protected sectors */
+       for (i = 0; i < info->sector_count; i++) {
+               /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+               /* D0 = 1 if protected */
+               addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+               /* For AMD29033C flash we need to resend the command of *
+                * reading flash protection for upper 8 Mb of flash     */
+               if (i == 32) {
+                       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+                       addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+                       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+               }
+
+               if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+                       info->protect[i] = 0;
+               else
+                       info->protect[i] = addr2[2] & 1;
+       }
+
+       /* issue bank reset to return to read mode */
+       addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+       return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+       ulong start, now, last;
+       volatile CFG_FLASH_WORD_SIZE *addr =
+               (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+       start = get_timer(0);
+       last = start;
+       while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+                       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+               if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+                       printf("Timeout\n");
+                       return -1;
+               }
+               /* show that we're waiting */
+               if ((now - last) > 1000) {      /* every second */
+                       putc('.');
+                       last = now;
+               }
+       }
+       return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+       if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+               return flash_erase_2(info, s_first, s_last);
+       } else {
+               return flash_erase_1(info, s_first, s_last);
+       }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+       volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+       volatile CFG_FLASH_WORD_SIZE *addr2;
+       int flag, prot, sect, l_sect;
+       int i;
+
+       if ((s_first < 0) || (s_first > s_last)) {
+               if (info->flash_id == FLASH_UNKNOWN)
+                       printf("- missing\n");
+               else
+                       printf("- no sectors to erase\n");
+               return 1;
+       }
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf("Can't erase unknown flash type - aborted\n");
+               return 1;
+       }
+
+       prot = 0;
+       for (sect = s_first; sect <= s_last; ++sect) {
+               if (info->protect[sect])
+                       prot++;
+       }
+
+       if (prot)
+               printf("- Warning: %d protected sectors will not be erased!", prot);
+
+       printf("\n");
+
+       l_sect = -1;
+
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts();
+
+       /* Start erase on unprotected sectors */
+       for (sect = s_first; sect <= s_last; sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+                       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;    /* block erase */
+                               for (i = 0; i < 50; i++)
+                                       udelay(1000);   /* wait 1 ms */
+                       } else {
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;    /* sector erase */
+                       }
+                       l_sect = sect;
+                       /*
+                        * Wait for each sector to complete, it's more
+                        * reliable.  According to AMD Spec, you must
+                        * issue all erase commands within a specified
+                        * timeout.  This has been seen to fail, especially
+                        * if printf()s are included (for debug)!!
+                        */
+                       wait_for_DQ7_1(info, sect);
+               }
+       }
+
+       /* re-enable interrupts if necessary */
+       if (flag)
+               enable_interrupts();
+
+       /* wait at least 80us - let's wait 1 ms */
+       udelay(1000);
+
+       /* reset to read mode */
+       addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+       addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;     /* reset bank */
+
+       printf(" done\n");
+       return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+       ulong cp, wp, data;
+       int i, l, rc;
+
+       wp = (addr & ~3);       /* get lower word aligned address */
+
+       /*
+        * handle unaligned start bytes
+        */
+       if ((l = addr - wp) != 0) {
+               data = 0;
+               for (i = 0, cp = wp; i < l; ++i, ++cp)
+                       data = (data << 8) | (*(uchar *) cp);
+
+               for (; i < 4 && cnt > 0; ++i) {
+                       data = (data << 8) | *src++;
+                       --cnt;
+                       ++cp;
+               }
+
+               for (; cnt == 0 && i < 4; ++i, ++cp)
+                       data = (data << 8) | (*(uchar *) cp);
+
+               if ((rc = write_word(info, wp, data)) != 0)
+                       return (rc);
+
+               wp += 4;
+       }
+
+       /*
+        * handle word aligned part
+        */
+       while (cnt >= 4) {
+               data = 0;
+               for (i = 0; i < 4; ++i)
+                       data = (data << 8) | *src++;
+
+               if ((rc = write_word(info, wp, data)) != 0)
+                       return (rc);
+
+               wp += 4;
+               cnt -= 4;
+       }
+
+       if (cnt == 0)
+               return (0);
+
+       /*
+        * handle unaligned tail bytes
+        */
+       data = 0;
+       for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+               data = (data << 8) | *src++;
+               --cnt;
+       }
+       for (; i < 4; ++i, ++cp)
+               data = (data << 8) | (*(uchar *) cp);
+
+       return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+       if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+               return write_word_2(info, dest, data);
+       } else {
+               return write_word_1(info, dest, data);
+       }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+       volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+       volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+       volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+       ulong start;
+       int i, flag;
+
+       /* Check if Flash is (sufficiently) erased */
+       if ((*((vu_long *)dest) & data) != data)
+               return (2);
+
+       for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+               /* Disable interrupts which might cause a timeout here */
+               flag = disable_interrupts();
+
+               addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+               addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+               addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+               dest2[i] = data2[i];
+
+               /* re-enable interrupts if necessary */
+               if (flag)
+                       enable_interrupts();
+
+               /* data polling for D7 */
+               start = get_timer(0);
+               while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+                               (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+                       if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+                               return (1);
+               }
+       }
+
+       return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef  CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+       short i;
+       int n;
+       CFG_FLASH_WORD_SIZE value;
+       ulong base = (ulong) addr;
+       volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+       DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+       /* issue bank reset to return to read mode */
+       addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+       /* Write auto select command: read Manufacturer ID */
+       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+       addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+       udelay(1000);
+
+       value = addr2[0];
+       DEBUGF("FLASH MANUFACT: %x\n", value);
+
+       switch (value) {
+               case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+                       info->flash_id = FLASH_MAN_AMD;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+                       info->flash_id = FLASH_MAN_FUJ;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+                       info->flash_id = FLASH_MAN_SST;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+                       info->flash_id = FLASH_MAN_STM;
+                       break;
+               case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+                       info->flash_id = FLASH_MAN_MX;
+                       break;
+               default:
+                       info->flash_id = FLASH_UNKNOWN;
+                       info->sector_count = 0;
+                       info->size = 0;
+                       return (0);     /* no or unknown flash  */
+       }
+
+       value = addr2[1];       /* device ID            */
+       DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+       switch (value) {
+               case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+                       info->flash_id += FLASH_AM320T;
+                       info->sector_count = 71;
+                       info->size = 0x00400000;
+                       break;  /* => 4 MB      */
+               case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+                       info->flash_id += FLASH_AM320B;
+                       info->sector_count = 71;
+                       info->size = 0x00400000;
+                       break;  /* => 4 MB      */
+               case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+                       info->flash_id += FLASH_STMW320DT;
+                       info->sector_count = 67;
+                       info->size = 0x00400000;
+                       break;  /* => 4 MB      */
+               case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+                       info->flash_id += FLASH_MXLV320T;
+                       info->sector_count = 71;
+                       info->size = 0x00400000;
+                       break;  /* => 4 MB      */
+               default:
+                       info->flash_id = FLASH_UNKNOWN;
+                       return (0);     /* => no or unknown flash */
+       }
+
+       /* set up sector start address table */
+       if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+                       ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+               for (i = 0; i < info->sector_count; i++)
+                       info->start[i] = base + (i * 0x00010000);
+       } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+               /* set sector offsets for top boot block type           */
+               base += info->size;
+               i = info->sector_count;
+               /*  1 x 16k boot sector */
+               base -= 16 << 10;
+               --i;
+               info->start[i] = base;
+               /*  2 x 8k  boot sectors */
+               for (n = 0; n < 2; ++n) {
+                       base -= 8 << 10;
+                       --i;
+                       info->start[i] = base;
+               }
+               /*  1 x 32k boot sector */
+               base -= 32 << 10;
+               --i;
+               info->start[i] = base;
+
+               while (i > 0) {                 /* 64k regular sectors  */
+                       base -= 64 << 10;
+                       --i;
+                       info->start[i] = base;
+               }
+       } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+               i = info->sector_count - 1;
+               info->start[i--] = base + info->size - 0x00002000;
+               info->start[i--] = base + info->size - 0x00004000;
+               info->start[i--] = base + info->size - 0x00006000;
+               info->start[i--] = base + info->size - 0x00008000;
+               info->start[i--] = base + info->size - 0x0000a000;
+               info->start[i--] = base + info->size - 0x0000c000;
+               info->start[i--] = base + info->size - 0x0000e000;
+               info->start[i--] = base + info->size - 0x00010000;
+
+               for (; i >= 0; i--)
+                       info->start[i] = base + i * 0x00010000;
+       } else {
+               if (info->flash_id & FLASH_BTYPE) {
+                       /* set sector offsets for bottom boot block type        */
+                       info->start[0] = base + 0x00000000;
+                       info->start[1] = base + 0x00004000;
+                       info->start[2] = base + 0x00006000;
+                       info->start[3] = base + 0x00008000;
+
+                       for (i = 4; i < info->sector_count; i++)
+                               info->start[i] = base + (i * 0x00010000) - 0x00030000;
+               } else {
+                       /* set sector offsets for top boot block type           */
+                       i = info->sector_count - 1;
+                       info->start[i--] = base + info->size - 0x00004000;
+                       info->start[i--] = base + info->size - 0x00006000;
+                       info->start[i--] = base + info->size - 0x00008000;
+
+                       for (; i >= 0; i--)
+                               info->start[i] = base + i * 0x00010000;
+               }
+       }
+
+       /* check for protected sectors */
+       for (i = 0; i < info->sector_count; i++) {
+               /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+               /* D0 = 1 if protected */
+               addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+               /* For AMD29033C flash we need to resend the command of *
+                * reading flash protection for upper 8 Mb of flash     */
+               if (i == 32) {
+                       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+                       addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+                       addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+               }
+
+               if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+                       info->protect[i] = 0;
+               else
+                       info->protect[i] = addr2[2] & 1;
+       }
+
+       /* issue bank reset to return to read mode */
+       addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+       return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+       ulong start, now, last;
+       volatile CFG_FLASH_WORD_SIZE *addr =
+               (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+       start = get_timer(0);
+       last = start;
+       while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+                       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+               if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+                       printf("Timeout\n");
+                       return -1;
+               }
+               /* show that we're waiting */
+               if ((now - last) > 1000) {      /* every second */
+                       putc('.');
+                       last = now;
+               }
+       }
+       return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+       volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+       volatile CFG_FLASH_WORD_SIZE *addr2;
+       int flag, prot, sect, l_sect;
+       int i;
+
+       if ((s_first < 0) || (s_first > s_last)) {
+               if (info->flash_id == FLASH_UNKNOWN)
+                       printf("- missing\n");
+               else
+                       printf("- no sectors to erase\n");
+               return 1;
+       }
+
+       if (info->flash_id == FLASH_UNKNOWN) {
+               printf("Can't erase unknown flash type - aborted\n");
+               return 1;
+       }
+
+       prot = 0;
+       for (sect = s_first; sect <= s_last; ++sect) {
+               if (info->protect[sect])
+                       prot++;
+       }
+
+       if (prot)
+               printf("- Warning: %d protected sectors will not be erased!",   prot);
+
+       printf("\n");
+
+       l_sect = -1;
+
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts();
+
+       /* Start erase on unprotected sectors */
+       for (sect = s_first; sect <= s_last; sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+                       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;    /* block erase */
+                               for (i = 0; i < 50; i++)
+                                       udelay(1000);   /* wait 1 ms */
+                       } else {
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+                               addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+                               addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+                               addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;    /* sector erase */
+                       }
+                       l_sect = sect;
+                       /*
+                        * Wait for each sector to complete, it's more
+                        * reliable.  According to AMD Spec, you must
+                        * issue all erase commands within a specified
+                        * timeout.  This has been seen to fail, especially
+                        * if printf()s are included (for debug)!!
+                        */
+                       wait_for_DQ7_2(info, sect);
+               }
+       }
+
+       /* re-enable interrupts if necessary */
+       if (flag)
+               enable_interrupts();
+
+       /* wait at least 80us - let's wait 1 ms */
+       udelay(1000);
+
+       /* reset to read mode */
+       addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+       addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;     /* reset bank */
+
+       printf(" done\n");
+       return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+       volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+       volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+       volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+       ulong start;
+       int i;
+
+       /* Check if Flash is (sufficiently) erased */
+       if ((*((vu_long *)dest) & data) != data)
+               return (2);
+
+       for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+               int flag;
+
+               /* Disable interrupts which might cause a timeout here */
+               flag = disable_interrupts();
+
+               addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+               addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+               addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+               dest2[i] = data2[i];
+
+               /* re-enable interrupts if necessary */
+               if (flag)
+                       enable_interrupts();
+
+               /* data polling for D7 */
+               start = get_timer(0);
+               while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+                               (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+                       if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+                               return (1);
+               }
+       }
+
+       return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+       unsigned long total_b = 0;
+       unsigned long size_b[CFG_MAX_FLASH_BANKS];
+       unsigned short index = 0;
+       int i;
+       unsigned long val;
+       unsigned long ebc_boot_size;
+       unsigned long boot_selection;
+
+       mfsdr(sdr_pstrp0, val);
+       index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28;
+
+       if ((index == 0xc) || (index == 8)) {
+               /*
+                * Boot Settings in IIC EEprom address 0xA8 or 0xA0
+                * Read Serial Device Strap Register1 in PPC440SPe
+                */
+               mfsdr(sdr_sdstp1, val);
+               boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+               ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+               switch(boot_selection) {
+                       case SDR0_SDSTP1_BOOT_SEL_EBC:
+                               switch(ebc_boot_size) {
+                                       case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+                                               index = 3;
+                                               break;
+                                       case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+                                               index = 0;
+                                               break;
+                               }
+                               break;
+
+                       case SDR0_SDSTP1_BOOT_SEL_PCI:
+                               index = 1;
+                               break;
+
+               }
+       } /*else if (index == 0) {*/
+/*             if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
+/*                     index = 8;*//* sram below op code flash -> new index 8*/
+/*     }*/
+
+       DEBUGF("\n");
+       DEBUGF("FLASH: Index: %d\n", index);
+
+       /* Init: no FLASHes known */
+       for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+               flash_info[i].flash_id = FLASH_UNKNOWN;
+               flash_info[i].sector_count = -1;
+               flash_info[i].size = 0;
+
+               /* check whether the address is 0 */
+               if (flash_addr_table[index][i] == 0)
+                       continue;
+
+               /* call flash_get_size() to initialize sector address */
+               size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+                               &flash_info[i]);
+
+               flash_info[i].size = size_b[i];
+
+               if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+                       printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+                                       i, size_b[i], size_b[i] << 20);
+                       flash_info[i].sector_count = -1;
+                       flash_info[i].size = 0;
+               }
+
+               /* Monitor protection ON by default */
+               (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+                                   CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+                                   &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+               (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+                                   CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+                                   &flash_info[i]);
+#if defined(CFG_ENV_ADDR_REDUND)
+               (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+                                   CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+                                   &flash_info[i]);
+#endif
+#endif
+               total_b += flash_info[i].size;
+       }
+
+       return total_b;
+}
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
new file mode 100644 (file)
index 0000000..8cf2636
--- /dev/null
@@ -0,0 +1,105 @@
+/*
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* port to AMCC 440SPE evaluatioon board - SG April 12,2005  */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K  0x00000000
+#define SZ_4K  0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K        0x00000040
+#define SZ_1M  0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M        0x00000090
+
+/* Storage attributes */
+#define SA_W   0x00000800      /* Write-through */
+#define SA_I   0x00000400      /* Caching inhibited */
+#define SA_M   0x00000200      /* Memory coherence */
+#define SA_G   0x00000100      /* Guarded */
+#define SA_E   0x00000080      /* Endian */
+
+/* Access control */
+#define AC_X   0x00000024      /* Execute */
+#define AC_W   0x00000012      /* Write */
+#define AC_R   0x00000009      /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)         ((e) & 0xfffffc00)
+#define TLB0(epn,sz)   ((EPN((epn)) | (sz) | TLB_VALID ))
+#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
+#define TLB2(a)                ((a) & 0x00000fbf)
+
+#define tlbtab_start\
+       mflr    r1      ;\
+       bl      0f      ;
+
+#define tlbtab_end\
+       .long 0, 0, 0   ;\
+0:     mflr    r0      ;\
+       mtlr    r1      ;\
+       blr             ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+       .section .bootpg,"ax"
+       .globl tlbtab
+
+tlbtab:
+       tlbtab_start
+       tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
+
+       tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+       tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+       tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+
+       tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+       tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+       tlbtab_end
+
diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds
new file mode 100644 (file)
index 0000000..9df4f92
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)      }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)      }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)       }
+  .rela.got      : { *(.rela.got)      }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)       }
+  .rela.bss      : { *(.rela.bss)      }
+  .rel.plt       : { *(.rel.plt)       }
+  .rela.plt      : { *(.rela.plt)      }
+  .init          : { *(.init)          }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector layout of our flash chips!   XXX FIXME XXX   */
+
+    cpu/ppc4xx/start.o         (.text)
+    board/amcc/yucca/init.o    (.text)
+    cpu/ppc4xx/kgdb.o          (.text)
+    cpu/ppc4xx/traps.o         (.text)
+    cpu/ppc4xx/interrupts.o    (.text)
+    cpu/ppc4xx/serial.o                (.text)
+    cpu/ppc4xx/cpu_init.o      (.text)
+    cpu/ppc4xx/speed.o         (.text)
+    common/dlmalloc.o          (.text)
+    lib_generic/crc32.o                (.text)
+    lib_ppc/extable.o          (.text)
+    lib_generic/zlib.o         (.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/yucca/u-boot.lds.debug b/board/amcc/yucca/u-boot.lds.debug
new file mode 100644 (file)
index 0000000..474f922
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)      }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)      }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)       }
+  .rela.got      : { *(.rela.got)      }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)       }
+  .rela.bss      : { *(.rela.bss)      }
+  .rel.plt       : { *(.rel.plt)       }
+  .rela.plt      : { *(.rela.plt)      }
+  .init          : { *(.init)          }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within */
+    /* the sector layout of our flash chips!   XXX FIXME XXX   */
+
+    cpu/ppc4xx/start.o         (.text)
+    board/amcc/yucca/init.o    (.text)
+    cpu/ppc4xx/kgdb.o          (.text)
+    cpu/ppc4xx/traps.o         (.text)
+    cpu/ppc4xx/interrupts.o    (.text)
+    cpu/ppc4xx/serial.o                (.text)
+    cpu/ppc4xx/cpu_init.o      (.text)
+    cpu/ppc4xx/speed.o         (.text)
+    common/dlmalloc.o          (.text)
+    lib_generic/crc32.o                (.text)
+    lib_ppc/extable.o          (.text)
+    lib_generic/zlib.o         (.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
new file mode 100644 (file)
index 0000000..8fb4cfa
--- /dev/null
@@ -0,0 +1,1100 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Port to AMCC-440SPE Evaluation Board SOP - April 2005
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include "yucca.h"
+
+void fpga_init (void);
+
+void get_sys_info(PPC440_SYS_INFO *board_cfg );
+int compare_to_true(char *str );
+char *remove_l_w_space(char *in_str );
+char *remove_t_w_space(char *in_str );
+int get_console_port(void);
+unsigned long ppcMfcpr(unsigned long cpr_reg);
+unsigned long ppcMfsdr(unsigned long sdr_reg);
+
+#define DEBUG_ENV
+#ifdef DEBUG_ENV
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+#define FALSE  0
+#define TRUE   1
+
+int board_early_init_f (void)
+{
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+#define BOOT_FROM_SMALL_FLASH          0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM  0x01
+#define BOOT_FROM_PCI                  0x02
+#define BOOT_DEVICE_UNKNOWN            0x03
+
+/*----------------------------------------------------------------------------+
+| EBC Devices Characteristics
+|   Peripheral Bank Access Parameters       -   EBC_BxAP
+|   Peripheral Bank Configuration Register  -   EBC_BxCR
++----------------------------------------------------------------------------*/
+
+/*
+ * Small Flash and FRAM
+ * BU Value
+ * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_SMALL_FLASH           EBC_BXAP_BME_DISABLED   | \
+                                       EBC_BXAP_TWT_ENCODE(7)  | \
+                                       EBC_BXAP_BCE_DISABLE    | \
+                                       EBC_BXAP_BCT_2TRANS     | \
+                                       EBC_BXAP_CSN_ENCODE(0)  | \
+                                       EBC_BXAP_OEN_ENCODE(0)  | \
+                                       EBC_BXAP_WBN_ENCODE(0)  | \
+                                       EBC_BXAP_WBF_ENCODE(0)  | \
+                                       EBC_BXAP_TH_ENCODE(0)   | \
+                                       EBC_BXAP_RE_DISABLED    | \
+                                       EBC_BXAP_SOR_DELAYED    | \
+                                       EBC_BXAP_BEM_WRITEONLY  | \
+                                       EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_SMALL_FLASH_CS0       EBC_BXCR_BAS_ENCODE(0xFF000000) | \
+                                       EBC_BXCR_BS_16MB                | \
+                                       EBC_BXCR_BU_RW                  | \
+                                       EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SMALL_FLASH_CS2       EBC_BXCR_BAS_ENCODE(0xe7000000) | \
+                                       EBC_BXCR_BS_16MB                | \
+                                       EBC_BXCR_BU_RW                  | \
+                                       EBC_BXCR_BW_8BIT
+
+/*
+ * Large Flash and SRAM
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_LARGE_FLASH           EBC_BXAP_BME_DISABLED   | \
+                                       EBC_BXAP_TWT_ENCODE(7)  | \
+                                       EBC_BXAP_BCE_DISABLE    | \
+                                       EBC_BXAP_BCT_2TRANS     | \
+                                       EBC_BXAP_CSN_ENCODE(0)  | \
+                                       EBC_BXAP_OEN_ENCODE(0)  | \
+                                       EBC_BXAP_WBN_ENCODE(0)  | \
+                                       EBC_BXAP_WBF_ENCODE(0)  | \
+                                       EBC_BXAP_TH_ENCODE(0)   | \
+                                       EBC_BXAP_RE_DISABLED    | \
+                                       EBC_BXAP_SOR_DELAYED    | \
+                                       EBC_BXAP_BEM_WRITEONLY  | \
+                                       EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_LARGE_FLASH_CS0       EBC_BXCR_BAS_ENCODE(0xFF000000) | \
+                                       EBC_BXCR_BS_16MB                | \
+                                       EBC_BXCR_BU_RW                  | \
+                                       EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2       EBC_BXCR_BAS_ENCODE(0xE7000000) | \
+                                       EBC_BXCR_BS_16MB                | \
+                                       EBC_BXCR_BU_RW                  | \
+                                       EBC_BXCR_BW_16BIT
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA                  EBC_BXAP_BME_DISABLED   | \
+                                       EBC_BXAP_TWT_ENCODE(11) | \
+                                       EBC_BXAP_BCE_DISABLE    | \
+                                       EBC_BXAP_BCT_2TRANS     | \
+                                       EBC_BXAP_CSN_ENCODE(10) | \
+                                       EBC_BXAP_OEN_ENCODE(1)  | \
+                                       EBC_BXAP_WBN_ENCODE(1)  | \
+                                       EBC_BXAP_WBF_ENCODE(1)  | \
+                                       EBC_BXAP_TH_ENCODE(1)   | \
+                                       EBC_BXAP_RE_DISABLED    | \
+                                       EBC_BXAP_SOR_DELAYED    | \
+                                       EBC_BXAP_BEM_RW         | \
+                                       EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_FPGA_CS1              EBC_BXCR_BAS_ENCODE(0xe2000000) | \
+                                       EBC_BXCR_BS_1MB                 | \
+                                       EBC_BXCR_BU_RW                  | \
+                                       EBC_BXCR_BW_16BIT
+
+        unsigned long mfr;
+       /*
+        * Define Variables for EBC initialization depending on BOOTSTRAP option
+        */
+       unsigned long sdr0_pinstp, sdr0_sdstp1 ;
+       unsigned long bootstrap_settings, ebc_data_width, boot_selection;
+       int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+       /*-------------------------------------------------------------------+
+        | Initialize EBC CONFIG -
+        | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+        | default value :
+        |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+        |
+        +-------------------------------------------------------------------*/
+       mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+                       EBC_CFG_PTD_ENABLE |
+                       EBC_CFG_RTC_16PERCLK |
+                       EBC_CFG_ATC_PREVIOUS |
+                       EBC_CFG_DTC_PREVIOUS |
+                       EBC_CFG_CTC_PREVIOUS |
+                       EBC_CFG_OEO_PREVIOUS |
+                       EBC_CFG_EMC_DEFAULT |
+                       EBC_CFG_PME_DISABLE |
+                       EBC_CFG_PR_16);
+
+       /*-------------------------------------------------------------------+
+        |
+        |  PART 1 : Initialize EBC Bank 1
+        |  ==============================
+        | Bank1 is always associated to the EPLD.
+        | It has to be initialized prior to other banks settings computation
+        | since some board registers values may be needed to determine the
+        | boot type
+        |
+        +-------------------------------------------------------------------*/
+       mtebc(pb1ap, EBC_BXAP_FPGA);
+       mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
+
+       /*-------------------------------------------------------------------+
+        |
+        |  PART 2 : Determine which boot device was selected
+        |  =================================================
+        |
+        |  Read Pin Strap Register in PPC440SPe
+        |  Result can either be :
+        |   - Boot strap = boot from EBC 8bits     => Small Flash
+        |   - Boot strap = boot from PCI
+        |   - Boot strap = IIC
+        |  In case of boot from IIC, read Serial Device Strap Register1
+        |
+        |  Result can either be :
+        |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
+        |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
+        |   - Boot from PCI
+        |
+        +-------------------------------------------------------------------*/
+       /* Read Pin Strap Register in PPC440SP */
+       sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
+       bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
+
+       switch (bootstrap_settings) {
+               case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
+                       /*
+                        * Strapping Option A
+                        * Boot from EBC - 8 bits , Small Flash
+                        */
+                       computed_boot_device = BOOT_FROM_SMALL_FLASH;
+                       break;
+               case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
+                       /*
+                        * Strappping Option B
+                        * Boot from PCI
+                        */
+                       computed_boot_device = BOOT_FROM_PCI;
+                       break;
+               case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
+               case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
+                       /*
+                        * Strapping Option C or D
+                        * Boot Settings in IIC EEprom address 0x50 or 0x54
+                        * Read Serial Device Strap Register1 in PPC440SPe
+                        */
+                       sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
+                       boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
+                       ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
+
+                       switch (boot_selection) {
+                               case SDR0_SDSTP1_ERPN_EBC:
+                                       switch (ebc_data_width) {
+                                               case SDR0_SDSTP1_EBCW_16_BITS:
+                                                       computed_boot_device =
+                                                               BOOT_FROM_LARGE_FLASH_OR_SRAM;
+                                                       break;
+                                               case SDR0_SDSTP1_EBCW_8_BITS :
+                                                       computed_boot_device = BOOT_FROM_SMALL_FLASH;
+                                                       break;
+                                       }
+                                       break;
+
+                               case SDR0_SDSTP1_ERPN_PCI:
+                                       computed_boot_device = BOOT_FROM_PCI;
+                                       break;
+                               default:
+                                       /* should not occure */
+                                       computed_boot_device = BOOT_DEVICE_UNKNOWN;
+                       }
+                       break;
+               default:
+                       /* should not be */
+                       computed_boot_device = BOOT_DEVICE_UNKNOWN;
+                       break;
+       }
+
+       /*-------------------------------------------------------------------+
+        |
+        |  PART 3 : Compute EBC settings depending on selected boot device
+        |  ======   ======================================================
+        |
+        | Resulting EBC init will be among following configurations :
+        |
+        |  - Boot from EBC 8bits => boot from Small Flash selected
+        |            EBC-CS0     = Small Flash
+        |            EBC-CS2     = Large Flash and SRAM
+        |
+        |  - Boot from EBC 16bits => boot from Large Flash or SRAM
+        |            EBC-CS0     = Large Flash or SRAM
+        |            EBC-CS2     = Small Flash
+        |
+        |  - Boot from PCI
+        |            EBC-CS0     = not initialized to avoid address contention
+        |            EBC-CS2     = same as boot from Small Flash selected
+        |
+        +-------------------------------------------------------------------*/
+       unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+       unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+       switch (computed_boot_device) {
+               /*-------------------------------------------------------------------*/
+               case BOOT_FROM_PCI:
+               /*-------------------------------------------------------------------*/
+                       /*
+                        * By Default CS2 is affected to LARGE Flash
+                        * do not initialize SMALL FLASH to avoid address contention
+                        * Large Flash
+                        */
+                       ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
+                       ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+                       break;
+
+               /*-------------------------------------------------------------------*/
+               case BOOT_FROM_SMALL_FLASH:
+               /*-------------------------------------------------------------------*/
+                       ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
+                       ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
+
+                       /*
+                        * Large Flash or SRAM
+                        */
+                       /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
+                       ebc0_cs2_bxap_value = 0x048ff240;
+                       ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+                       break;
+
+               /*-------------------------------------------------------------------*/
+               case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+               /*-------------------------------------------------------------------*/
+                       ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
+                       ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
+
+                       /* Small flash */
+                       ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
+                       ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
+                       break;
+
+               /*-------------------------------------------------------------------*/
+               default:
+               /*-------------------------------------------------------------------*/
+                       /* BOOT_DEVICE_UNKNOWN */
+                       break;
+       }
+
+       mtebc(pb0ap, ebc0_cs0_bxap_value);
+       mtebc(pb0cr, ebc0_cs0_bxcr_value);
+       mtebc(pb2ap, ebc0_cs2_bxap_value);
+       mtebc(pb2cr, ebc0_cs2_bxcr_value);
+
+       /*--------------------------------------------------------------------+
+        | Interrupt controller setup for the AMCC 440SPe Evaluation board.
+        +--------------------------------------------------------------------+
+       +---------------------------------------------------------------------+
+       |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+       +---------+-----------------------------------+-------+-------+-------+
+       | IRQ 00  | UART0                             | High  | Level | Non   |
+       | IRQ 01  | UART1                             | High  | Level | Non   |
+       | IRQ 02  | IIC0                              | High  | Level | Non   |
+       | IRQ 03  | IIC1                              | High  | Level | Non   |
+       | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
+       | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
+       | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
+       | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
+       | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
+       | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
+       | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
+       | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
+       | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
+       | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
+       | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
+       | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
+       | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
+       | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
+       | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
+       | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+       | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+       | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+       | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+       | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
+       | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
+       | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
+       | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
+       | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
+       | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
+       | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
+       | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
+       | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
+       |----------------------------------------------------------------------
+       | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 33  | MAL Serr                          | High  | Level | Non   |
+       | IRQ 34  | MAL Txde                          | High  | Level | Non   |
+       | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
+       | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
+       | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
+       | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
+       | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
+       | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
+       | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
+       | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
+       | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
+       | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
+       | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
+       | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
+       | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
+       | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
+       | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
+       | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 54  | DMA Error                         | High  | Level | Non   |
+       | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
+       | IRQ 56  | Serial ROM                        | High  | Level | Non   |
+       | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
+       | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
+       | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
+       | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
+       | IRQ 62  | Reserved                          | High  | Level | Non   |
+       | IRQ 63  | XOR                               | High  | Level | Non   |
+       |----------------------------------------------------------------------
+       | IRQ 64  | PE0 AL                            | High  | Level | Non   |
+       | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
+       | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+       | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+       | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
+       | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+       | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
+       | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
+       | IRQ 72  | PE1 AL                            | High  | Level | Non   |
+       | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
+       | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+       | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+       | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
+       | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+       | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
+       | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
+       | IRQ 80  | PE2 AL                            | High  | Level | Non   |
+       | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
+       | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+       | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+       | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
+       | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+       | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
+       | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
+       | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
+       | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+       | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+       | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+       | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+       | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+       | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
+       | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
+       |---------------------------------------------------------------------
+       | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
+       | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
+       | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
+       | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
+       | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
+       | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
+       | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
+       | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
+       | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
+       | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
+       | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
+       | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
+       | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
+       | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
+       | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
+       | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
+       | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
+       | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
+       | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
+       | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
+       | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
+       | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
+       | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
+       | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
+       | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
+       | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
+       | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
+       | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
+       | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
+       | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
+       | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
+       | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
+       +---------+-----------------------------------+-------+-------+------*/
+       /*--------------------------------------------------------------------+
+        | Put UICs in PowerPC440SPemode.
+        | Initialise UIC registers.  Clear all interrupts.  Disable all
+        | interrupts.
+        | Set critical interrupt values.  Set interrupt polarities.  Set
+        | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+        | interrupts again.
+        +-------------------------------------------------------------------*/
+       mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
+       mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
+                                        * interrupts */
+       mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
+       mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+                                        * priority */
+       mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
+
+       mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
+       mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
+                                        * interrupts */
+       mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
+       mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
+       mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+                                        * priority */
+       mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
+       mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
+
+       mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
+       mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
+                                        * interrupts */
+       mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
+       mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+                                        * priority */
+       mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
+       mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
+
+       mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
+                                        * cascade to be checked */
+       mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
+                                        * interrupts */
+       mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
+       mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+                                        * priority */
+       mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
+       mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
+
+       /* SDR0_MFR should be part of Ethernet init */
+       mfsdr (sdr_mfr, mfr);
+       mfr &= ~SDR0_MFR_ECS_MASK;
+       /*mtsdr(sdr_mfr, mfr);*/
+       fpga_init();
+
+       return 0;
+}
+
+int checkboard (void)
+{
+       sys_info_t sysinfo;
+
+       get_sys_info (&sysinfo);
+
+       printf ("Board: AMCC 440SPe Evaluation Board\n");
+       printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+       printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+       printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+       printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+       printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+       printf ("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
+       printf ("\tDDR: %lu MHz\n", sysinfo.freqDDR / 1000000);
+       return 0;
+}
+
+static long int yucca_probe_for_dimms(void)
+{
+       long int        dimm_installed[MAXDIMMS];
+       long int        dimm_num, probe_result;
+       long int        dimms_found = 0;
+       uchar           dimm_addr = IIC0_DIMM0_ADDR;
+
+       for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
+               /* check if there is a chip at the dimm address */
+               switch (dimm_num) {
+                       case 0:
+                               dimm_addr = IIC0_DIMM0_ADDR;
+                               break;
+                       case 1:
+                               dimm_addr = IIC0_DIMM1_ADDR;
+                               break;
+               }
+               probe_result = i2c_probe(dimm_addr);
+
+               if (probe_result == 0) {
+                       dimm_installed[dimm_num] = TRUE;
+                       dimms_found++;
+                       debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num);
+               } else {
+                       dimm_installed[dimm_num] = FALSE;
+                       debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
+               }
+       }
+
+       if (dimms_found == 0) {
+               printf("ERROR - No memory installed.  Install a DDR-SDRAM DIMM.\n\n");
+               hang();
+       }
+
+       if (dimm_installed[0] != TRUE) {
+               printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
+               printf("        Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
+               hang();
+       }
+
+       return dimms_found;
+}
+
+/*************************************************************************
+ * init SDRAM controller with fixed value
+ * the initialization values are for 2x MICRON DDR2
+ * PN: MT18HTF6472DY-53EB2
+ * 512MB, DDR2, 533, CL4, ECC, REG
+ ************************************************************************/
+static long int fixed_sdram(void)
+{
+       long int yucca_dimms = 0;
+
+       yucca_dimms = yucca_probe_for_dimms();
+
+       /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT  */
+       mtdcr( 0x10, 0x00000021 );
+       mtdcr( 0x11, 0x84000000 );
+
+       /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2      */
+       mtdcr( 0x10, 0x00000020 );
+       mtdcr( 0x11, 0x2D122000 );
+
+       /* SET MCIF0_CODT   Die Termination On  */
+       mtdcr( 0x10, 0x00000026 );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x2A800021 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x02800021 );
+
+       /* On-Die Termination for Bank 0        */
+       mtdcr( 0x10, 0x00000022 );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x18000000 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x06000000 );
+
+       /*      On-Die Termination for Bank 1   */
+       mtdcr( 0x10, 0x00000023 );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x18000000 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x01800000 );
+
+       /*      On-Die Termination for Bank 2   */
+       mtdcr( 0x10, 0x00000024 );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x01800000 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x00000000 );
+
+       /*      On-Die Termination for Bank 3   */
+       mtdcr( 0x10, 0x00000025 );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x01800000 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x00000000 );
+
+       /* Refresh Time register (0x30) Refresh every 7.8125uS  */
+       mtdcr( 0x10, 0x00000030 );
+       mtdcr( 0x11, 0x08200000 );
+
+       /* SET MCIF0_MMODE       CL 4   */
+       mtdcr( 0x10, 0x00000088 );
+       mtdcr( 0x11, 0x00000642 );
+
+       /* MCIF0_MEMODE */
+       mtdcr( 0x10, 0x00000089 );
+       mtdcr( 0x11, 0x00000004 );
+
+       /*SET MCIF0_MB0CF       */
+       mtdcr( 0x10, 0x00000040 );
+       mtdcr( 0x11, 0x00000201 );
+
+       /* SET MCIF0_MB1CF      */
+       mtdcr( 0x10, 0x00000044 );
+       mtdcr( 0x11, 0x00000201 );
+
+       /* SET MCIF0_MB2CF      */
+       mtdcr( 0x10, 0x00000048 );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x00000201 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x00000000 );
+
+       /* SET MCIF0_MB3CF      */
+       mtdcr( 0x10, 0x0000004c );
+       if (yucca_dimms == 2)
+               mtdcr( 0x11, 0x00000201 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x11, 0x00000000 );
+
+       /* SET MCIF0_INITPLR0  # NOP            */
+       mtdcr( 0x10, 0x00000050 );
+       mtdcr( 0x11, 0xB5380000 );
+
+       /* SET MCIF0_INITPLR1  # PRE            */
+       mtdcr( 0x10, 0x00000051 );
+       mtdcr( 0x11, 0x82100400 );
+
+       /* SET MCIF0_INITPLR2  # EMR2           */
+       mtdcr( 0x10, 0x00000052 );
+       mtdcr( 0x11, 0x80820000 );
+
+       /* SET MCIF0_INITPLR3  # EMR3           */
+       mtdcr( 0x10, 0x00000053 );
+       mtdcr( 0x11, 0x80830000 );
+
+       /* SET MCIF0_INITPLR4  # EMR DLL ENABLE */
+       mtdcr( 0x10, 0x00000054 );
+       mtdcr( 0x11, 0x80810000 );
+
+       /* SET MCIF0_INITPLR5  # MR DLL RESET   */
+       mtdcr( 0x10, 0x00000055 );
+       mtdcr( 0x11, 0x80800542 );
+
+       /* SET MCIF0_INITPLR6  # PRE            */
+       mtdcr( 0x10, 0x00000056 );
+       mtdcr( 0x11, 0x82100400 );
+
+       /* SET MCIF0_INITPLR7  # Refresh        */
+       mtdcr( 0x10, 0x00000057 );
+       mtdcr( 0x11, 0x8A080000 );
+
+       /* SET MCIF0_INITPLR8  # Refresh        */
+       mtdcr( 0x10, 0x00000058 );
+       mtdcr( 0x11, 0x8A080000 );
+
+       /* SET MCIF0_INITPLR9  # Refresh        */
+       mtdcr( 0x10, 0x00000059 );
+       mtdcr( 0x11, 0x8A080000 );
+
+       /* SET MCIF0_INITPLR10 # Refresh        */
+       mtdcr( 0x10, 0x0000005A );
+       mtdcr( 0x11, 0x8A080000 );
+
+       /* SET MCIF0_INITPLR11 # MR             */
+       mtdcr( 0x10, 0x0000005B );
+       mtdcr( 0x11, 0x80800442 );
+
+       /* SET MCIF0_INITPLR12 # EMR OCD Default*/
+       mtdcr( 0x10, 0x0000005C );
+       mtdcr( 0x11, 0x80810380 );
+
+       /* SET MCIF0_INITPLR13 # EMR OCD Exit   */
+       mtdcr( 0x10, 0x0000005D );
+       mtdcr( 0x11, 0x80810000 );
+
+       /* 0x80: Adv Addr clock by 180 deg      */
+       mtdcr( 0x10, 0x00000080 );
+       mtdcr( 0x11, 0x80000000 );
+
+       /* 0x21: Exit self refresh, set DC_EN   */
+       mtdcr( 0x10, 0x00000021 );
+       mtdcr( 0x11, 0x28000000 );
+
+       /* 0x81: Write DQS Adv 90 + Fractional DQS Delay        */
+       mtdcr( 0x10, 0x00000081 );
+       mtdcr( 0x11, 0x80000800 );
+
+       /* MCIF0_SDTR1  */
+       mtdcr( 0x10, 0x00000085 );
+       mtdcr( 0x11, 0x80201000 );
+
+       /* MCIF0_SDTR2  */
+       mtdcr( 0x10, 0x00000086 );
+       mtdcr( 0x11, 0x42103242 );
+
+       /* MCIF0_SDTR3  */
+       mtdcr( 0x10, 0x00000087 );
+       mtdcr( 0x11, 0x0C100D14 );
+
+       /* SET MQ0_B0BAS  base addr 00000000 / 256MB    */
+       mtdcr( 0x40, 0x0000F800 );
+
+       /* SET MQ0_B1BAS  base addr 10000000 / 256MB    */
+       mtdcr( 0x41, 0x0400F800 );
+
+       /* SET MQ0_B2BAS  base addr 20000000 / 256MB    */
+       if (yucca_dimms == 2)
+               mtdcr( 0x42, 0x0800F800 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x42, 0x00000000 );
+
+       /* SET MQ0_B3BAS  base addr 30000000 / 256MB    */
+       if (yucca_dimms == 2)
+               mtdcr( 0x43, 0x0C00F800 );
+       else if (yucca_dimms == 1)
+               mtdcr( 0x43, 0x00000000 );
+
+       /* SDRAM_RQDC   */
+       mtdcr( 0x10, 0x00000070 );
+       mtdcr( 0x11, 0x8000003F );
+
+       /* SDRAM_RDCC   */
+       mtdcr( 0x10, 0x00000078 );
+       mtdcr( 0x11, 0x80000000 );
+
+       /* SDRAM_RFDC   */
+       mtdcr( 0x10, 0x00000074 );
+       mtdcr( 0x11, 0x00000220 );
+
+       return (yucca_dimms * 512) << 20;
+}
+
+long int initdram (int board_type)
+{
+       long dram_size = 0;
+
+       dram_size = fixed_sdram();
+
+       return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+       uint *pstart = (uint *) 0x00000000;
+       uint *pend = (uint *) 0x08000000;
+       uint *p;
+
+       for (p = pstart; p < pend; p++)
+               *p = 0xaaaaaaaa;
+
+       for (p = pstart; p < pend; p++) {
+               if (*p != 0xaaaaaaaa) {
+                       printf ("SDRAM test fails at: %08x\n", (uint) p);
+                       return 1;
+               }
+       }
+
+       for (p = pstart; p < pend; p++)
+               *p = 0x55555555;
+
+       for (p = pstart; p < pend; p++) {
+               if (*p != 0x55555555) {
+                       printf ("SDRAM test fails at: %08x\n", (uint) p);
+                       return 1;
+               }
+       }
+       return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *     Different boards may wish to customize the pci controller structure
+ *     (add regions, override default access routines, etc) or perform
+ *     certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+       unsigned long strap;
+
+       /*-------------------------------------------------------------------+
+        *      The yucca board is always configured as the host & requires the
+        *      PCI arbiter to be enabled.
+        *-------------------------------------------------------------------*/
+       mfsdr(sdr_sdstp1, strap);
+       if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+               printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+               return 0;
+       }
+
+       return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *     The bootstrap configuration provides default settings for the pci
+ *     inbound map (PIM). But the bootstrap config choices are limited and
+ *     may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       /*-------------------------------------------------------------------+
+        * Disable everything
+        *-------------------------------------------------------------------*/
+       out32r( PCIX0_PIM0SA, 0 ); /* disable */
+       out32r( PCIX0_PIM1SA, 0 ); /* disable */
+       out32r( PCIX0_PIM2SA, 0 ); /* disable */
+       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+       /*-------------------------------------------------------------------+
+        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+        * strapping options to not support sizes such as 128/256 MB.
+        *-------------------------------------------------------------------*/
+       out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+       out32r( PCIX0_PIM0LAH, 0 );
+       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+       out32r( PCIX0_BAR0, 0 );
+
+       /*-------------------------------------------------------------------+
+        * Program the board's subsystem id/vendor id
+        *-------------------------------------------------------------------*/
+       out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+       out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *     This routine is called to determine if a pci scan should be
+ *     performed. With various hardware environments (especially cPCI and
+ *     PPMC) it's insufficient to depend on the state of the arbiter enable
+ *     bit in the strap register, or generic host/adapter assumptions.
+ *
+ *     Rather than hard-code a bad assumption in the general 440 code, the
+ *     440 pci code requires the board to decide at runtime.
+ *
+ *     Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+       /* The yucca board is always configured as host. */
+       return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+int misc_init_f (void)
+{
+       uint reg;
+#if defined(CONFIG_STRESS)
+       uint i ;
+       uint disp;
+#endif
+
+       out16(FPGA_REG10, (in16(FPGA_REG10) &
+                       ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
+                               FPGA_REG10_10MHZ_ENABLE |
+                               FPGA_REG10_100MHZ_ENABLE |
+                               FPGA_REG10_GIGABIT_ENABLE |
+                               FPGA_REG10_FULL_DUPLEX );
+
+       udelay(10000);  /* wait 10ms */
+
+       out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
+
+       /* minimal init for PCIe */
+       /* pci express 0 Endpoint Mode */
+       mfsdr(SDR0_PE0DLPSET, reg);
+       reg &= (~0x00400000);
+       mtsdr(SDR0_PE0DLPSET, reg);
+       /* pci express 1 Rootpoint  Mode */
+       mfsdr(SDR0_PE1DLPSET, reg);
+       reg |= 0x00400000;
+       mtsdr(SDR0_PE1DLPSET, reg);
+       /* pci express 2 Rootpoint  Mode */
+       mfsdr(SDR0_PE2DLPSET, reg);
+       reg |= 0x00400000;
+       mtsdr(SDR0_PE2DLPSET, reg);
+
+       out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
+                               ~FPGA_REG1C_PE0_ROOTPOINT &
+                               ~FPGA_REG1C_PE1_ENDPOINT  &
+                               ~FPGA_REG1C_PE2_ENDPOINT));
+
+#if defined(CONFIG_STRESS)
+       /*
+        * all this setting done by linux only needed by stress an charac. test
+        * procedure
+        * PCIe 1 Rootpoint PCIe2 Endpoint
+        * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
+        * Power Level
+        */
+       for (i = 0, disp = 0; i < 8; i++, disp += 3) {
+               mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
+               reg |= 0x33000000;
+               mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
+       }
+
+       /*
+        * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
+        * Power Level
+        */
+       for (i = 0, disp = 0; i < 4; i++, disp += 3) {
+               mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
+               reg |= 0x33000000;
+               mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
+       }
+
+       /*
+        * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
+        * Power Level
+        */
+       for (i = 0, disp = 0; i < 4; i++, disp += 3) {
+               mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
+               reg |= 0x33000000;
+               mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
+       }
+
+       reg = 0x21242222;
+       mtsdr(SDR0_PE2UTLSET1, reg);
+       reg = 0x11000000;
+       mtsdr(SDR0_PE2UTLSET2, reg);
+       /* pci express 1 Endpoint  Mode */
+       reg = 0x00004000;
+       mtsdr(SDR0_PE2DLPSET, reg);
+
+       mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
+#endif
+       return 0;
+}
+
+void fpga_init(void)
+{
+       /*
+        * by default sdram access is disabled by fpga
+        */
+       out16(FPGA_REG10, (in16 (FPGA_REG10) |
+                               FPGA_REG10_SDRAM_ENABLE |
+                               FPGA_REG10_ENABLE_DISPLAY ));
+
+       return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+       return (ctrlc());
+}
+#endif
+
+/*---------------------------------------------------------------------------+
+ | onboard_pci_arbiter_selected => from EPLD
+ +---------------------------------------------------------------------------*/
+int onboard_pci_arbiter_selected(int core_pci)
+{
+#if 0
+       unsigned long onboard_pci_arbiter_sel;
+
+       onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
+
+       if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
+               return (BOARD_OPTION_SELECTED);
+       else
+#endif
+       return (BOARD_OPTION_NOT_SELECTED);
+}
+
+/*---------------------------------------------------------------------------+
+ | ppcMfcpr.
+ +---------------------------------------------------------------------------*/
+unsigned long ppcMfcpr(unsigned long cpr_reg)
+{
+       unsigned long msr;
+       unsigned long cpr_cfgaddr_temp;
+       unsigned long cpr_value;
+
+       msr = (mfmsr () & ~(MSR_EE));
+       cpr_cfgaddr_temp =  mfdcr(CPR0_CFGADDR);
+       mtdcr(CPR0_CFGADDR, cpr_reg);
+       cpr_value =  mfdcr(CPR0_CFGDATA);
+       mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
+       mtmsr(msr);
+
+       return (cpr_value);
+}
+
+/*----------------------------------------------------------------------------+
+| Indirect Access of the System DCR's (SDR)
+| ppcMfsdr
++----------------------------------------------------------------------------*/
+unsigned long ppcMfsdr(unsigned long sdr_reg)
+{
+       unsigned long msr;
+       unsigned long sdr_cfgaddr_temp;
+       unsigned long sdr_value;
+
+       msr = (mfmsr () & ~(MSR_EE));
+       sdr_cfgaddr_temp =  mfdcr(SDR0_CFGADDR);
+       mtdcr(SDR0_CFGADDR, sdr_reg);
+       sdr_value =  mfdcr(SDR0_CFGDATA);
+       mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
+       mtmsr(msr);
+
+       return (sdr_value);
+}
+
diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h
new file mode 100644 (file)
index 0000000..91caee8
--- /dev/null
@@ -0,0 +1,382 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __YUCCA_H_
+#define __YUCCA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+
+#define TMR_FREQ_EXT           25000000
+#define BOARD_UART_CLOCK       11059200
+
+#define BOARD_OPTION_SELECTED          1
+#define BOARD_OPTION_NOT_SELECTED      0
+
+#define ENGINEERING_CLOCK_CHECKING "clk_chk"
+#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
+
+#define ENGINEERING_CLOCK_CHECKING_DATA        1
+#define ENGINEERING_EXTERNAL_CLOCK_DATA        2
+
+/* ethernet definition */
+#define MAX_ENETMODE_PARM      3
+#define ENETMODE_NEG           0
+#define ENETMODE_SPEED         1
+#define ENETMODE_DUPLEX                2
+
+#define ENETMODE_AUTONEG       0
+#define ENETMODE_NO_AUTONEG    1
+#define ENETMODE_10            2
+#define ENETMODE_100           3
+#define ENETMODE_1000          4
+#define ENETMODE_HALF          5
+#define ENETMODE_FULL          6
+
+#define NUM_TLB_ENTRIES          64
+
+/*----------------------------------------------------------------------------+
+| TLB specific defines.
++----------------------------------------------------------------------------*/
+#define TLB_256MB_ALIGN_MASK   0xF0000000
+#define TLB_16MB_ALIGN_MASK    0xFF000000
+#define TLB_1MB_ALIGN_MASK     0xFFF00000
+#define TLB_256KB_ALIGN_MASK   0xFFFC0000
+#define TLB_64KB_ALIGN_MASK    0xFFFF0000
+#define TLB_16KB_ALIGN_MASK    0xFFFFC000
+#define TLB_4KB_ALIGN_MASK     0xFFFFF000
+#define TLB_1KB_ALIGN_MASK     0xFFFFFC00
+#define TLB_256MB_SIZE         0x10000000
+#define TLB_16MB_SIZE          0x01000000
+#define TLB_1MB_SIZE           0x00100000
+#define TLB_256KB_SIZE         0x00040000
+#define TLB_64KB_SIZE          0x00010000
+#define TLB_16KB_SIZE          0x00004000
+#define TLB_4KB_SIZE           0x00001000
+#define TLB_1KB_SIZE           0x00000400
+
+#define TLB_WORD0_EPN_MASK     0xFFFFFC00
+#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_V_MASK       0x00000200
+#define TLB_WORD0_V_ENABLE     0x00000200
+#define TLB_WORD0_V_DISABLE    0x00000000
+#define TLB_WORD0_TS_MASK      0x00000100
+#define TLB_WORD0_TS_1         0x00000100
+#define TLB_WORD0_TS_0         0x00000000
+#define TLB_WORD0_SIZE_MASK    0x000000F0
+#define TLB_WORD0_SIZE_1KB     0x00000000
+#define TLB_WORD0_SIZE_4KB     0x00000010
+#define TLB_WORD0_SIZE_16KB    0x00000020
+#define TLB_WORD0_SIZE_64KB    0x00000030
+#define TLB_WORD0_SIZE_256KB   0x00000040
+#define TLB_WORD0_SIZE_1MB     0x00000050
+#define TLB_WORD0_SIZE_16MB    0x00000070
+#define TLB_WORD0_SIZE_256MB   0x00000090
+#define TLB_WORD0_TPAR_MASK    0x0000000F
+#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD1_RPN_MASK     0xFFFFFC00
+#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_PAR1_MASK    0x00000300
+#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define TLB_WORD1_PAR1_0       0x00000000
+#define TLB_WORD1_PAR1_1       0x00000100
+#define TLB_WORD1_PAR1_2       0x00000200
+#define TLB_WORD1_PAR1_3       0x00000300
+#define TLB_WORD1_ERPN_MASK    0x0000000F
+#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD2_PAR2_MASK    0xC0000000
+#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+#define TLB_WORD2_PAR2_0       0x00000000
+#define TLB_WORD2_PAR2_1       0x40000000
+#define TLB_WORD2_PAR2_2       0x80000000
+#define TLB_WORD2_PAR2_3       0xC0000000
+#define TLB_WORD2_U0_MASK      0x00008000
+#define TLB_WORD2_U0_ENABLE    0x00008000
+#define TLB_WORD2_U0_DISABLE   0x00000000
+#define TLB_WORD2_U1_MASK      0x00004000
+#define TLB_WORD2_U1_ENABLE    0x00004000
+#define TLB_WORD2_U1_DISABLE   0x00000000
+#define TLB_WORD2_U2_MASK      0x00002000
+#define TLB_WORD2_U2_ENABLE    0x00002000
+#define TLB_WORD2_U2_DISABLE   0x00000000
+#define TLB_WORD2_U3_MASK      0x00001000
+#define TLB_WORD2_U3_ENABLE    0x00001000
+#define TLB_WORD2_U3_DISABLE   0x00000000
+#define TLB_WORD2_W_MASK       0x00000800
+#define TLB_WORD2_W_ENABLE     0x00000800
+#define TLB_WORD2_W_DISABLE    0x00000000
+#define TLB_WORD2_I_MASK       0x00000400
+#define TLB_WORD2_I_ENABLE     0x00000400
+#define TLB_WORD2_I_DISABLE    0x00000000
+#define TLB_WORD2_M_MASK       0x00000200
+#define TLB_WORD2_M_ENABLE     0x00000200
+#define TLB_WORD2_M_DISABLE    0x00000000
+#define TLB_WORD2_G_MASK       0x00000100
+#define TLB_WORD2_G_ENABLE     0x00000100
+#define TLB_WORD2_G_DISABLE    0x00000000
+#define TLB_WORD2_E_MASK       0x00000080
+#define TLB_WORD2_E_ENABLE     0x00000080
+#define TLB_WORD2_E_DISABLE    0x00000000
+#define TLB_WORD2_UX_MASK      0x00000020
+#define TLB_WORD2_UX_ENABLE    0x00000020
+#define TLB_WORD2_UX_DISABLE   0x00000000
+#define TLB_WORD2_UW_MASK      0x00000010
+#define TLB_WORD2_UW_ENABLE    0x00000010
+#define TLB_WORD2_UW_DISABLE   0x00000000
+#define TLB_WORD2_UR_MASK      0x00000008
+#define TLB_WORD2_UR_ENABLE    0x00000008
+#define TLB_WORD2_UR_DISABLE   0x00000000
+#define TLB_WORD2_SX_MASK      0x00000004
+#define TLB_WORD2_SX_ENABLE    0x00000004
+#define TLB_WORD2_SX_DISABLE   0x00000000
+#define TLB_WORD2_SW_MASK      0x00000002
+#define TLB_WORD2_SW_ENABLE    0x00000002
+#define TLB_WORD2_SW_DISABLE   0x00000000
+#define TLB_WORD2_SR_MASK      0x00000001
+#define TLB_WORD2_SR_ENABLE    0x00000001
+#define TLB_WORD2_SR_DISABLE   0x00000000
+
+/*----------------------------------------------------------------------------+
+| Board specific defines.
++----------------------------------------------------------------------------*/
+#define NONCACHE_MEMORY_SIZE     (64*1024)
+#define NONCACHE_AREA0_ENDOFFSET (64*1024)
+#define NONCACHE_AREA1_ENDOFFSET (32*1024)
+
+#define FLASH_SECTORSIZE       0x00010000
+
+/* SDRAM MICRON */
+#define SDRAM_MICRON           0x2C
+
+#define SDRAM_TRUE             1
+#define SDRAM_FALSE            0
+#define SDRAM_DDR1             1
+#define SDRAM_DDR2             2
+#define SDRAM_NONE             0
+#define MAXDIMMS               2               /* Changes le 12/01/05 pour 1.6 */
+#define MAXRANKS               4               /* Changes le 12/01/05 pour 1.6 */
+#define MAXBANKSPERDIMM                2
+#define MAXRANKSPERDIMM                2
+#define MAXBXCF                        4               /* Changes le 12/01/05 pour 1.6 */
+#define MAXSDRAMMEMORY         0xFFFFFFFF      /* 4GB */
+#define ERROR_STR_LENGTH       256
+#define MAX_SPD_BYTES          256             /* Max number of bytes on the DIMM's SPD EEPROM */
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define sdr_pstrp0     0x0040
+
+#define        SDR0_SDSTP1_EBC_ROM_BS_MASK     0x00000080 /* EBC Boot bus width Mask */
+#define        SDR0_SDSTP1_EBC_ROM_BS_16BIT    0x00000080 /* EBC 16 Bits */
+#define        SDR0_SDSTP1_EBC_ROM_BS_8BIT     0x00000000 /* EBC  8 Bits */
+
+#define        SDR0_SDSTP1_BOOT_SEL_MASK       0x00080000 /* Boot device Selection Mask */
+#define        SDR0_SDSTP1_BOOT_SEL_EBC        0x00000000 /* EBC */
+#define        SDR0_SDSTP1_BOOT_SEL_PCI        0x00080000 /* PCI */
+
+#define        SDR0_SDSTP1_EBC_SIZE_MASK       0x00000060 /* Boot rom size Mask */
+#define        SDR0_SDSTP1_BOOT_SIZE_16MB      0x00000060 /* 16 MB */
+#define        SDR0_SDSTP1_BOOT_SIZE_8MB       0x00000040 /*  8 MB */
+#define        SDR0_SDSTP1_BOOT_SIZE_4MB       0x00000020 /*  4 MB */
+#define        SDR0_SDSTP1_BOOT_SIZE_2MB       0x00000000 /*  2 MB */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0                    0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK     0xE0000000  /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0        0x00000000  /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1        0x20000000  /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2        0x40000000  /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3        0x60000000  /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4        0x80000000  /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5        0xA0000000  /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6        0xC0000000  /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7        0xE0000000  /* Default strap settings 7 */
+
+/* fpgareg - defines are in include/config/YUCCA.h */
+
+#define SDR0_CUST0_ENET3_MASK          0x00000080
+#define SDR0_CUST0_ENET3_COPPER                0x00000000
+#define SDR0_CUST0_ENET3_FIBER         0x00000080
+#define SDR0_CUST0_RGMII3_MASK         0x00000070
+#define SDR0_CUST0_RGMII3_ENCODE(n)    ((((unsigned long)(n))&0x7)<<4)
+#define SDR0_CUST0_RGMII3_DECODE(n)    ((((unsigned long)(n))>>4)&0x07)
+#define SDR0_CUST0_RGMII3_DISAB                0x00000000
+#define SDR0_CUST0_RGMII3_RTBI         0x00000040
+#define SDR0_CUST0_RGMII3_RGMII                0x00000050
+#define SDR0_CUST0_RGMII3_TBI          0x00000060
+#define SDR0_CUST0_RGMII3_GMII         0x00000070
+#define SDR0_CUST0_ENET2_MASK          0x00000008
+#define SDR0_CUST0_ENET2_COPPER                0x00000000
+#define SDR0_CUST0_ENET2_FIBER         0x00000008
+#define SDR0_CUST0_RGMII2_MASK         0x00000007
+#define SDR0_CUST0_RGMII2_ENCODE(n)    ((((unsigned long)(n))&0x7)<<0)
+#define SDR0_CUST0_RGMII2_DECODE(n)    ((((unsigned long)(n))>>0)&0x07)
+#define SDR0_CUST0_RGMII2_DISAB                0x00000000
+#define SDR0_CUST0_RGMII2_RTBI         0x00000004
+#define SDR0_CUST0_RGMII2_RGMII                0x00000005
+#define SDR0_CUST0_RGMII2_TBI          0x00000006
+#define SDR0_CUST0_RGMII2_GMII         0x00000007
+
+#define ONE_MILLION                    1000000
+#define ONE_BILLION                    1000000000
+
+/*----------------------------------------------------------------------------+
+|                               X
+|                              XX
+| XX  XXX   XXXXX   XX XXX    XXXXX
+| XX  XX        X    XXX XX    XX
+| XX  XX   XXXXXX    XX        XX
+| XX  XX   X   XX    XX        XX XX
+|  XXX XX  XXXXX X  XXXX        XXX
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+| Declare Configuration values
++----------------------------------------------------------------------------*/
+
+typedef enum config_selection {
+       CONFIG_NOT_SELECTED,
+       CONFIG_SELECTED
+} config_selection_t;
+
+typedef enum config_list {
+       UART2_IN_SERVICE_MODE,
+       CPU_TRACE_MODE,
+       UART1_CTS_RTS,
+       CONFIG_NB
+} config_list_t;
+
+#define MAX_CONFIG_SELECT_NB                   3
+
+#define BOARD_INFO_UART2_IN_SERVICE_MODE       1
+#define BOARD_INFO_CPU_TRACE_MODE              2
+#define BOARD_INFO_UART1_CTS_RTS_MODE          4
+
+void force_bup_config_selection(config_selection_t *confgi_select_P);
+void update_config_selection_table(config_selection_t *config_select_P);
+void display_config_selection(config_selection_t *config_select_P);
+
+/*----------------------------------------------------------------------------+
+|                     XX
+|
+|   XXXX    XX XXX   XXX     XXXX
+|  XX        XX  XX   XX    XX  XX
+|  XX  XXX   XX  XX   XX    XX  XX
+|  XX  XX    XXXXX    XX    XX  XX
+|   XXXX     XX      XXXX    XXXX
+|           XXXX
+|
+|
+|
+| +------------------------------------------------------------------+
+| |  GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
+| +----------------------+------------------+-----+------------+-----+
+| |                      |                  |     |            |     |
+| | GPIO0_0              | PCIX0REQ2_N      | I/O |  TRCCLK    |     |
+| | GPIO0_1              | PCIX0REQ3_N      | I/O |  TRCBS0    |     |
+| | GPIO0_2              | PCIX0GNT2_N      | I/O |  TRCBS1    |     |
+| | GPIO0_3              | PCIX0GNT3_N      | I/O |  TRCBS2    |     |
+| | GPIO0_4              | PCIX1REQ2_N      | I/O |  TRCES0    |     |
+| | GPIO0_5              | PCIX1REQ3_N      | I/O |  TRCES1    |     |
+| | GPIO0_6              | PCIX1GNT2_N      | I/O |  TRCES2    | NA  |
+| | GPIO0_7              | PCIX1GNT3_N      | I/O |  TRCES3    | NA  |
+| | GPIO0_8              | PERREADY         |  I  |  TRCES4    | NA  |
+| | GPIO0_9              | PERCS1_N         |  O  |  TRCTS0    | NA  |
+| | GPIO0_10             | PERCS2_N         |  O  |  TRCTS1    | NA  |
+| | GPIO0_11             | IRQ0             |  I  |  TRCTS2    | NA  |
+| | GPIO0_12             | IRQ1             |  I  |  TRCTS3    | NA  |
+| | GPIO0_13             | IRQ2             |  I  |  TRCTS4    | NA  |
+| | GPIO0_14             | IRQ3             |  I  |  TRCTS5    | NA  |
+| | GPIO0_15             | IRQ4             |  I  |  TRCTS6    | NA  |
+| | GPIO0_16             | IRQ5             |  I  |  UART2RX   |  I  |
+| | GPIO0_17             | PERBE0_N         |  O  |  UART2TX   |  O  |
+| | GPIO0_18             | PCI0GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_19             | PCI0GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_20             | PCI0REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_21             | PCI0REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_22             | PCI1GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_23             | PCI1GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_24             | PCI1REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_25             | PCI1REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_26             | PCI2GNT0_N       | I/O |  NA        | NA  |
+| | GPIO0_27             | PCI2GNT1_N       | I/O |  NA        | NA  |
+| | GPIO0_28             | PCI2REQ0_N       | I/O |  NA        | NA  |
+| | GPIO0_29             | PCI2REQ1_N       | I/O |  NA        | NA  |
+| | GPIO0_30             | UART1RX          |  I  |  NA        | NA  |
+| | GPIO0_31             | UART1TX          |  O  |  NA        | NA  |
+| |                      |                  |     |            |     |
+| +----------------------+------------------+-----+------------+-----+
+|
++----------------------------------------------------------------------------*/
+
+#define GPIO_MAX       32
+#define GPIO_ALT1_SEL  0x40000000      /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL  0x80000000      /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL  0xC0000000      /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK      0xC0000000      /* GPIO_MASK */
+#define GPIO_IN_SEL    0x40000000      /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+                                       /* For the other GPIO number, you must shift */
+/*----------------------------------------------------------------------------+
+| Declare GPIO Configuration values
++----------------------------------------------------------------------------*/
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct {
+       unsigned long   add;    /* gpio core base address */
+       gpio_driver_t   in_out; /* Driver Setting */
+       gpio_select_t   alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+unsigned long auto_calc_speed(void);
+/*----------------------------------------------------------------------------+
+| Prototypes
++----------------------------------------------------------------------------*/
+void print_evb440spe_info(void);
+
+int onboard_pci_arbiter_selected(int core_pci);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __YUCCA_H_ */
index 40e28dd9d23b4e14774b536bdd854e671f431ffd..90a6ad09bdf8ce3a9e4c0122c1b75d58170cf6d0 100644 (file)
@@ -62,11 +62,12 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        print_num ("bootflags",     bd->bi_bootflags    );
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+       defined(CONFIG_440SP)
        print_str ("procfreq",      strmhz(buf, bd->bi_procfreq));
        print_str ("plb_busfreq",   strmhz(buf, bd->bi_plb_busfreq));
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
        print_str ("pci_busfreq",   strmhz(buf, bd->bi_pci_busfreq));
 #endif
 #else  /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
index 22d8fd0584febae96c2083a7bc6dc6d489488d4c..d725a3cdb15c64102c4d87d10f73c17929417662 100644 (file)
@@ -40,7 +40,11 @@ struct serial_device *default_serial_console (void)
        return &serial_scc_device;
 #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
    || defined(CONFIG_405EP)
-       return &serial0_device;
+#if defined(CONFIG_UART1_CONSOLE)
+               return &serial1_device;
+#else
+               return &serial0_device;
+#endif
 #else
 #error No default console
 #endif
index 64431ab13a450ca54d1f561085d0ff20728481c7..2fda60e39051c9a89fdc292c780c37175807944d 100644 (file)
@@ -437,7 +437,7 @@ void pci_440_init (struct pci_controller *hose)
         * The PCI initialization sequence enable bit must be set ... if not abort
         * pci setup since updating the bit requires chip reset.
         *--------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        unsigned long strap;
 
        mfsdr(sdr_sdstp1,strap);
@@ -501,7 +501,7 @@ void pci_440_init (struct pci_controller *hose)
        out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
        out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
 #elif defined(PCIX0_BRDGOPT1)
@@ -519,8 +519,13 @@ void pci_440_init (struct pci_controller *hose)
        out32r( PCIX0_POM0SA, 0 ); /* disable */
        out32r( PCIX0_POM1SA, 0 ); /* disable */
        out32r( PCIX0_POM2SA, 0 ); /* disable */
+#if defined(CONFIG_440SPE)
+       out32r( PCIX0_POM0LAL, 0x10000000 );
+       out32r( PCIX0_POM0LAH, 0x0000000c );
+#else
        out32r( PCIX0_POM0LAL, 0x00000000 );
        out32r( PCIX0_POM0LAH, 0x00000003 );
+#endif
        out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
        out32r( PCIX0_POM0PCIAH, 0x00000000 );
        out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
index 86dc2d066e8118cc3827460967c59f0c4928dbac..fab65aff78acb90eb89a608c0e5be1349d7a4ad3 100644 (file)
@@ -181,6 +181,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 {
        EMAC_4XX_HW_PST hw_p = dev->priv;
        uint32_t failsafe = 10000;
+#if defined(CONFIG_440SPE)
+       unsigned long mfr;
+#endif
 
        out32 (EMAC_IER + hw_p->hw_addr, 0x00000000);   /* disable emac interrupts */
 
@@ -202,8 +205,23 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
        }
 
        /* EMAC RESET */
+#if defined(CONFIG_440SPE)
+       /* provide clocks for EMAC internal loopback  */
+       mfsdr (sdr_mfr, mfr);
+       mfr |= 0x08000000;
+       mtsdr(sdr_mfr, mfr);
+#endif
+
        out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
 
+#if defined(CONFIG_440SPE)
+       /* remove clocks for EMAC internal loopback  */
+       mfsdr (sdr_mfr, mfr);
+       mfr &= ~0x08000000;
+       mtsdr(sdr_mfr, mfr);
+#endif
+
+
 #ifndef CONFIG_NETCONSOLE
        hw_p->print_speed = 1;  /* print speed message again next time */
 #endif
@@ -301,7 +319,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
        return ((int)pfc1);
 
 }
-#endif
+#endif /* CONFIG_440_GX */
 
 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 {
@@ -314,12 +332,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        unsigned mode_reg;
        unsigned short devnum;
        unsigned short reg_short;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        sys_info_t sysinfo;
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        int ethgroup = -1;
 #endif
 #endif
+#if defined(CONFIG_440SPE)
+       unsigned long mfr;
+#endif
+
 
        EMAC_4XX_HW_PST hw_p = dev->priv;
 
@@ -330,7 +352,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
                return -1;
        }
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        /* Need to get the OPB frequency so we can access the PHY */
        get_sys_info (&sysinfo);
 #endif
@@ -360,6 +382,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        hw_p->stats.pkts_tx = 0;
        hw_p->stats.pkts_rx = 0;
        hw_p->stats.pkts_handled = 0;
+       hw_p->print_speed = 1;  /* print speed message again next time */
 #endif
 
        hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
@@ -373,7 +396,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        hw_p->tx_i_index = 0;   /* Transmit Interrupt Queue Index */
        hw_p->tx_u_index = 0;   /* Transmit User Queue Index */
 
-#if defined(CONFIG_440) && !defined(CONFIG_440SP)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
        /* set RMII mode */
        /* NOTE: 440GX spec states that mode is mutually exclusive */
        /* NOTE: Therefore, disable all other EMACS, since we handle */
@@ -406,6 +429,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        __asm__ volatile ("eieio");
 
        /* reset emac so we have access to the phy */
+#if defined(CONFIG_440SPE)
+       /* provide clocks for EMAC internal loopback  */
+       mfsdr (sdr_mfr, mfr);
+       mfr |= 0x08000000;
+       mtsdr(sdr_mfr, mfr);
+#endif
 
        out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
        __asm__ volatile ("eieio");
@@ -416,7 +445,14 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
                failsafe--;
        }
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440SPE)
+       /* remove clocks for EMAC internal loopback  */
+       mfsdr (sdr_mfr, mfr);
+       mfr &= ~0x08000000;
+       mtsdr(sdr_mfr, mfr);
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        /* Whack the M1 register */
        mode_reg = 0x0;
        mode_reg &= ~0x00000038;
@@ -468,7 +504,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
        if (hw_p->first_init == 0) {
                miiphy_reset (dev->name, reg);
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #if defined(CONFIG_CIS8201_PHY)
                /*
                 * Cicada 8201 PHY needs to have an extended register whacked
@@ -544,7 +580,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
                        (int) speed, (duplex == HALF) ? "HALF" : "FULL");
        }
 
-#if defined(CONFIG_440) && !defined(CONFIG_440SP)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
        mfsdr(sdr_mfr, reg);
        if (speed == 100) {
@@ -575,7 +611,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
 
        /* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
               MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
 #else
@@ -759,8 +795,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
        /* set speed */
        if (speed == _1000BASET) {
-#if defined(CONFIG_440SP)
-#define SDR0_PFC1_EM_1000      0x00200000
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
                unsigned long pfc1;
                mfsdr (sdr_pfc1, pfc1);
                pfc1 |= SDR0_PFC1_EM_1000;
@@ -787,7 +822,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
        /* set receive  low/high water mark register */
 #if defined(CONFIG_440)
-       /* 440GP has a 64 byte burst length */
+       /* 440s has a 64 byte burst length */
        out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
 #else
        /* 405s have a 16 byte burst length */
@@ -895,7 +930,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
 
 #if defined (CONFIG_440)
 
-#if defined(CONFIG_440SP)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /*
  * Hack: On 440SP all enet irq sources are located on UIC1
  * Needs some cleanup. --sr
@@ -1367,20 +1402,19 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 #endif
        /* set phy num and mode */
        bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+       bis->bi_phymode[0] = 0;
+
 #if defined(CONFIG_PHY1_ADDR)
        bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+       bis->bi_phymode[1] = 0;
 #endif
 #if defined(CONFIG_440GX)
        bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
        bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
-       bis->bi_phymode[0] = 0;
-       bis->bi_phymode[1] = 0;
        bis->bi_phymode[2] = 2;
        bis->bi_phymode[3] = 2;
 
-#if defined (CONFIG_440GX)
        ppc_4xx_eth_setup_bridge(0, bis);
-#endif
 #endif
 
        for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
@@ -1478,9 +1512,15 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 
                if (0 == virgin) {
                        /* set the MAL IER ??? names may change with new spec ??? */
+#if defined(CONFIG_440SPE)
+                       mal_ier =
+                               MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
+                               MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
+#else
                        mal_ier =
                                MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
                                MAL_IER_OPBE | MAL_IER_PLBE;
+#endif
                        mtdcr (malesr, 0xffffffff);     /* clear pending interrupts */
                        mtdcr (maltxdeir, 0xffffffff);  /* clear pending interrupts */
                        mtdcr (malrxdeir, 0xffffffff);  /* clear pending interrupts */
@@ -1510,11 +1550,13 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 #else
                emac0_dev = dev;
 #endif
+
+#if defined(CONFIG_NET_MULTI)
 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
                miiphy_register (dev->name,
                                 emac4xx_miiphy_read, emac4xx_miiphy_write);
 #endif
-
+#endif
        }                       /* end for each supported device */
        return (1);
 }
index a26533c59c7e553e94143138f30cc623f2a6abe0..3e85a8856024d5049828016feaa7fa4433d9a789 100644 (file)
@@ -78,7 +78,9 @@ int pci_arbiter_enabled(void)
        return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+     defined(CONFIG_440SPE)
        unsigned long val;
 
        mfsdr(sdr_sdstp1, val);
@@ -87,8 +89,8 @@ int pci_arbiter_enabled(void)
 }
 #endif
 
-#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-       defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) ||  \
+     defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 
 #define I2C_BOOTROM
 
@@ -98,7 +100,9 @@ int i2c_bootrom_enabled(void)
        return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
        unsigned long val;
 
        mfsdr(sdr_sdcs, val);
@@ -237,6 +241,12 @@ int checkcpu (void)
                puts("SP Rev. B");
                break;
 
+       case PVR_440SPe_RA:
+               puts("SPe 3GA533C");
+               break;
+       case PVR_440SPe_RB:
+               puts("SPe 3GB533C");
+               break;
        default:
                printf (" UNKNOWN (PVR=%08x)", pvr);
                break;
index 1d8dc7c221deb4be50465424e94f46cc29a00875..fdae846dcc17e3abd46752cb3ee341b9afbe9ab9 100644 (file)
@@ -48,18 +48,22 @@ struct      irq_action {
 };
 
 static struct irq_action irq_vecs[32];
+void uic0_interrupt( void * parms); /* UIC0 handler */
 
 #if defined(CONFIG_440)
 static struct irq_action irq_vecs1[32]; /* For UIC1 */
 
 void uic1_interrupt( void * parms); /* UIC1 handler */
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
 static struct irq_action irq_vecs2[32]; /* For UIC2 */
-
-void uic0_interrupt( void * parms); /* UIC0 handler */
 void uic2_interrupt( void * parms); /* UIC2 handler */
-#endif /* CONFIG_440GX */
+#endif /* CONFIG_440GX CONFIG_440SPE */
+
+#if defined(CONFIG_440SPE)
+static struct irq_action irq_vecs3[32]; /* For UIC3 */
+void uic3_interrupt( void * parms); /* UIC3 handler */
+#endif /* CONFIG_440SPE */
 
 #endif /* CONFIG_440 */
 
@@ -115,11 +119,16 @@ int interrupt_init_cpu (unsigned *decrementer_count)
                irq_vecs1[vec].handler = NULL;
                irq_vecs1[vec].arg = NULL;
                irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
                irq_vecs2[vec].handler = NULL;
                irq_vecs2[vec].arg = NULL;
                irq_vecs2[vec].count = 0;
 #endif /* CONFIG_440GX */
+#if defined(CONFIG_440SPE)
+               irq_vecs3[vec].handler = NULL;
+               irq_vecs3[vec].arg = NULL;
+               irq_vecs3[vec].count = 0;
+#endif /* CONFIG_440SPE */
 #endif
        }
 
@@ -221,6 +230,34 @@ void external_interrupt(struct pt_regs *regs)
 
 } /* external_interrupt CONFIG_440GX */
 
+#elif defined(CONFIG_440SPE)
+void external_interrupt(struct pt_regs *regs)
+{
+       ulong uic_msr;
+
+       /*
+        * Read masked interrupt status register to determine interrupt source
+        */
+       /* 440 SPe uses base uic register */
+       uic_msr = mfdcr(uic0msr);
+
+       if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+               uic1_interrupt(0);
+
+       if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+               uic2_interrupt(0);
+
+       if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) )
+               uic3_interrupt(0);
+
+       if (uic_msr & ~(UICB0_ALL))
+               uic0_interrupt(0);
+
+       mtdcr(uic0sr, uic_msr);
+
+       return;
+} /* external_interrupt CONFIG_440SPE */
+
 #else
 
 void external_interrupt(struct pt_regs *regs)
@@ -266,7 +303,7 @@ void external_interrupt(struct pt_regs *regs)
 }
 #endif
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
 /* Handler for UIC0 interrupt */
 void uic0_interrupt( void * parms)
 {
@@ -357,8 +394,8 @@ void uic1_interrupt( void * parms)
 }
 #endif /* defined(CONFIG_440) */
 
-#if defined(CONFIG_440GX)
-/* Handler for UIC1 interrupt */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+/* Handler for UIC2 interrupt */
 void uic2_interrupt( void * parms)
 {
        ulong uic2_msr;
@@ -384,7 +421,7 @@ void uic2_interrupt( void * parms)
                                (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
                        } else {
                                mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
-                               printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
+                               printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec);
                        }
 
                        /*
@@ -402,6 +439,51 @@ void uic2_interrupt( void * parms)
 }
 #endif /* defined(CONFIG_440GX) */
 
+#if defined(CONFIG_440SPE)
+/* Handler for UIC3 interrupt */
+void uic3_interrupt( void * parms)
+{
+       ulong uic3_msr;
+       ulong msr_shift;
+       int vec;
+
+       /*
+        * Read masked interrupt status register to determine interrupt source
+        */
+       uic3_msr = mfdcr(uic3msr);
+       msr_shift = uic3_msr;
+       vec = 0;
+
+       while (msr_shift != 0) {
+               if (msr_shift & 0x80000000) {
+                       /*
+                        * Increment irq counter (for debug purpose only)
+                        */
+                       irq_vecs3[vec].count++;
+
+                       if (irq_vecs3[vec].handler != NULL) {
+                               /* call isr */
+                               (*irq_vecs3[vec].handler)(irq_vecs3[vec].arg);
+                       } else {
+                               mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec));
+                               printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec);
+                       }
+
+                       /*
+                        * After servicing the interrupt, we have to remove the status indicator.
+                        */
+                       mtdcr(uic3sr, (0x80000000 >> vec));
+               }
+
+               /*
+                * Shift msr to next position and increment vector
+                */
+               msr_shift <<= 1;
+               vec++;
+       }
+}
+#endif /* defined(CONFIG_440SPE) */
+
 /****************************************************************************/
 
 /*
@@ -414,7 +496,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
        int i = vec;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        if ((vec > 31) && (vec < 64)) {
                i = vec - 32;
                irqa = irq_vecs1;
@@ -441,7 +523,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
        irqa[i].arg = arg;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        if ((vec > 31) && (vec < 64))
                mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
        else if (vec > 63)
@@ -464,7 +546,7 @@ void irq_free_handler (int vec)
        int i = vec;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        if ((vec > 31) && (vec < 64)) {
                irqa = irq_vecs1;
                i = vec - 32;
@@ -485,7 +567,7 @@ void irq_free_handler (int vec)
 #endif
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        if ((vec > 31) && (vec < 64))
                mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
        else if (vec > 63)
@@ -553,7 +635,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        printf("\n");
 #endif
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
        printf ("\nUIC 2\n");
        printf ("Nr  Routine   Arg       Count\n");
 
@@ -566,6 +648,19 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        printf("\n");
 #endif
 
+#if defined(CONFIG_440SPE)
+       printf ("\nUIC 3\n");
+       printf ("Nr  Routine   Arg       Count\n");
+
+       for (vec=0; vec<32; vec++) {
+               if (irq_vecs3[vec].handler != NULL)
+                       printf ("%02d  %08lx  %08lx  %d\n",
+                                       vec+63, (ulong)irq_vecs3[vec].handler,
+                                       (ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count);
+       }
+       printf("\n");
+#endif
+
        return 0;
 }
 #endif  /* CONFIG_COMMANDS & CFG_CMD_IRQ */
index f26f2a203a0e8c0c3b43edab5c0ec6c3381b62c4..aa580ed48f99376a68ec0ce77be3cb24aadc0c26 100644 (file)
@@ -50,7 +50,7 @@
 #include <405_mal.h>
 #include <miiphy.h>
 
-
+#undef ET_DEBUG
 /***********************************************************/
 /* Dump out to the screen PHY regs                        */
 /***********************************************************/
@@ -90,6 +90,10 @@ int phy_setup_aneg (char *devname, unsigned char addr)
                PHY_ANLPAR_10);
        miiphy_write (devname, addr, PHY_ANAR, adv);
 
+       miiphy_read (devname, addr, PHY_1000BTCR, &adv);
+       adv |= (0x0300);
+       miiphy_write (devname, addr, PHY_1000BTCR, adv);
+
        /* Start/Restart aneg */
        miiphy_read (devname, addr, PHY_BMCR, &ctl);
        ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
@@ -104,7 +108,7 @@ int phy_setup_aneg (char *devname, unsigned char addr)
 /***********************************************************/
 unsigned int miiphy_getemac_offset (void)
 {
-#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI)
+#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI)
        unsigned long zmii;
        unsigned long eoffset;
 
@@ -155,10 +159,12 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
        i = 0;
 
        /* see if it is ready for  sec */
-       while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+       while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
                udelay (7);
                if (i > 5) {
-#if 0
+#ifdef ET_DEBUG
+                       sta_reg = in32 (EMAC_STACR + emac_reg);
+                       printf ("read : EMAC_STACR=0x%0x\n", sta_reg);  /* test-only */
                        printf ("read err 1\n");
 #endif
                        return -1;
@@ -167,31 +173,41 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
        }
        sta_reg = reg;          /* reg address */
        /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX)
-       sta_reg |= EMAC_STACR_READ;
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
+               sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
+#else
+               sta_reg |= EMAC_STACR_READ;
+#endif
 #else
        sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
        sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
 #endif
        sta_reg = sta_reg | (addr << 5);        /* Phy address */
-
+       sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
        out32 (EMAC_STACR + emac_reg, sta_reg);
-#if 0                          /* test-only */
+#ifdef ET_DEBUG
        printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);      /* test-only */
 #endif
 
        sta_reg = in32 (EMAC_STACR + emac_reg);
+#ifdef ET_DEBUG
+               printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg);     /* test-only */
+#endif
        i = 0;
-       while ((sta_reg & EMAC_STACR_OC) == 0) {
+       while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
                udelay (7);
                if (i > 5) {
                        return -1;
                }
                i++;
                sta_reg = in32 (EMAC_STACR + emac_reg);
+#ifdef ET_DEBUG
+               printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg);     /* test-only */
+#endif
        }
        if ((sta_reg & EMAC_STACR_PHYE) != 0) {
                return -1;
@@ -219,7 +235,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
        /* see if it is ready for 1000 nsec */
        i = 0;
 
-       while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
+       while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
                if (i > 5)
                        return -1;
                udelay (7);
@@ -228,16 +244,21 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
        sta_reg = 0;
        sta_reg = reg;          /* reg address */
        /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX)
-       sta_reg |= EMAC_STACR_WRITE;
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
+               sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
+#else
+               sta_reg |= EMAC_STACR_WRITE;
+#endif
 #else
        sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
        sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;        /* Set clock frequency (PLB freq. dependend) */
 #endif
-       sta_reg = sta_reg | ((unsigned long) addr << 5);        /* Phy address */
+       sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
+       sta_reg = sta_reg | EMAC_STACR_OC_MASK;         /* new IBM emac v4 */
        memcpy (&sta_reg, &value, 2);   /* put in data */
 
        out32 (EMAC_STACR + emac_reg, sta_reg);
@@ -245,12 +266,18 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
        /* wait for completion */
        i = 0;
        sta_reg = in32 (EMAC_STACR + emac_reg);
-       while ((sta_reg & EMAC_STACR_OC) == 0) {
+#ifdef ET_DEBUG
+               printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg);     /* test-only */
+#endif
+       while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
                udelay (7);
                if (i > 5)
                        return -1;
                i++;
                sta_reg = in32 (EMAC_STACR + emac_reg);
+#ifdef ET_DEBUG
+               printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg);     /* test-only */
+#endif
        }
 
        if ((sta_reg & EMAC_STACR_PHYE) != 0)
index e7f6bcbe1e8bed440382e9556d272ba3c7eda1c0..273452098726a910f69bff1a223824f07c3cff2f 100644 (file)
@@ -277,11 +277,11 @@ int serial_tstc ()
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
 #endif
 
-#if defined(CONFIG_440SP)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define CR0_MASK        0xdfffffff
 #define CR0_EXTCLK_ENA  0x00800000
 #define CR0_UDIV_POS    0
@@ -311,14 +311,18 @@ int serial_tstc ()
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE      UART1_BASE
 #define ACTING_UART1_BASE      UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+       defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
 #define UART0_SDR           sdr_uart1
 #define UART1_SDR           sdr_uart0
 #endif /* CONFIG_440GX */
 #else
 #define ACTING_UART0_BASE      UART0_BASE
 #define ACTING_UART1_BASE      UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+       defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
 #define UART0_SDR           sdr_uart0
 #define UART1_SDR           sdr_uart1
 #endif /* CONFIG_440GX */
@@ -441,7 +445,8 @@ int serial_init(void)
        unsigned long tmp;
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
 #if defined(CONFIG_SERIAL_MULTI)
        if (UART0_BASE == dev_base) {
                mfsdr(UART0_SDR,reg);
@@ -470,7 +475,9 @@ int serial_init(void)
        serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+       defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
        reg |= udiv << CR0_UDIV_POS;    /* set the UART divisor */
 #if defined(CONFIG_SERIAL_MULTI)
        if (UART0_BASE == dev_base) {
@@ -615,8 +622,28 @@ void serial_setbrg (void)
 #else
        udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
 #endif /* CONFIG_405EP */
+
+#if !defined(CFG_EXT_SERIAL_CLOCK) && \
+       ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+         defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+         defined(CONFIG_440SPE) )
+       serial_divs (gd->baudrate, &udiv, &bdiv);
+       tmp = udiv << CR0_UDIV_POS;             /* set the UART divisor */
+#if defined(CONFIG_SERIAL_MULTI)
+       if (UART0_BASE == dev_base) {
+               mtsdr (UART0_SDR, tmp);
+       } else {
+               mtsdr (UART1_SDR, tmp);
+       }
+#else
+       mtsdr (UART0_SDR, tmp);
+#endif
+
+#else
+
        tmp = gd->baudrate * udiv * 16;
        bdiv = (clk + tmp / 2) / tmp;
+#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ 
 
 #if defined(CONFIG_SERIAL_MULTI)
        out8 (dev_base + UART_LCR, 0x80);       /* set DLAB bit */
index 553c491e245bab4a6527ac8fab12f3ec29b3f2a6..77782719320655ba3798d8fa3de9ae474d63f053 100644 (file)
 /* ------------------------------------------------------------------------- */
 
 #define ONE_BILLION        1000000000
-
+#ifdef DEBUG
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
 
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR)
 
@@ -283,7 +287,7 @@ ulong get_PCI_freq (void)
        return sys_info.freqPCI;
 }
 
-#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
+#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 void get_sys_info (sys_info_t * sysInfo)
 {
        unsigned long strp0;
@@ -326,6 +330,26 @@ void get_sys_info (sys_info_t * sysInfo)
        unsigned long m;
        unsigned long prbdv0;
 
+#if defined(CONFIG_440SPE)
+       unsigned long sys_freq;
+       unsigned long sys_per=0;
+       unsigned long msr;
+       unsigned long pci_clock_per;
+       unsigned long sdr_ddrpll;
+
+       /*-------------------------------------------------------------------------+
+        | Get the system clock period.
+        +-------------------------------------------------------------------------*/
+       sys_per = determine_sysper();
+
+       msr = (mfmsr () & ~(MSR_EE));   /* disable interrupts */
+
+       /*-------------------------------------------------------------------------+
+        | Calculate the system clock speed from the period.
+        +-------------------------------------------------------------------------*/
+       sys_freq=(ONE_BILLION/sys_per)*1000;
+#endif
+
        /* Extract configured divisors */
        mfsdr( sdr_sdstp0,strp0 );
        mfsdr( sdr_sdstp1,strp1 );
@@ -360,12 +384,238 @@ void get_sys_info (sys_info_t * sysInfo)
                m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 
        /* Now calculate the individual clocks */
+#if defined(CONFIG_440SPE)
+       sysInfo->freqVCOMhz = (m * sys_freq) ;
+#else
        sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+#endif
        sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
        sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
        sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
        sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
+#if defined(CONFIG_440SPE)
+       /* Determine PCI Clock Period */
+       pci_clock_per = determine_pci_clock_per();
+       sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
+       mfsdr(sdr_ddr0, sdr_ddrpll);
+       sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
+#endif
+
+
+}
+
+#endif
+
+#if defined(CONFIG_440SPE)
+unsigned long determine_sysper(void)
+{
+       unsigned int fpga_clocking_reg;
+       unsigned int master_clock_selection;
+       unsigned long master_clock_per = 0;
+       unsigned long fb_div_selection;
+       unsigned int vco_div_reg_value;
+       unsigned long vco_div_selection;
+       unsigned long sys_per = 0;
+       int extClkVal;
+
+       /*-------------------------------------------------------------------------+
+        | Read FPGA reg 0 and reg 1 to get FPGA reg information
+        +-------------------------------------------------------------------------*/
+       fpga_clocking_reg = in16(FPGA_REG16);
+
+
+       /* Determine Master Clock Source Selection */
+       master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;
+
+       switch(master_clock_selection) {
+               case FPGA_REG16_MASTER_CLK_66_66:
+                       master_clock_per = PERIOD_66_66MHZ;
+                       break;
+               case FPGA_REG16_MASTER_CLK_50:
+                       master_clock_per = PERIOD_50_00MHZ;
+                       break;
+               case FPGA_REG16_MASTER_CLK_33_33:
+                       master_clock_per = PERIOD_33_33MHZ;
+                       break;
+               case FPGA_REG16_MASTER_CLK_25:
+                       master_clock_per = PERIOD_25_00MHZ;
+                       break;
+               case FPGA_REG16_MASTER_CLK_EXT:
+                       if ((extClkVal==EXTCLK_33_33)
+                                       && (extClkVal==EXTCLK_50)
+                                       && (extClkVal==EXTCLK_66_66)
+                                       && (extClkVal==EXTCLK_83)) {
+                               /* calculate master clock period from external clock value */
+                               master_clock_per=(ONE_BILLION/extClkVal) * 1000;
+                       } else {
+                               /* Unsupported */
+                               DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
+                               hang();
+                       }
+                       break;
+               default:
+                       /* Unsupported */
+                       DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
+                       hang();
+                       break;
+       }
+
+       /* Determine FB divisors values */
+       if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
+               if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
+                       fb_div_selection = FPGA_FB_DIV_6;
+               else
+                       fb_div_selection = FPGA_FB_DIV_12;
+       } else {
+               if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
+                       fb_div_selection = FPGA_FB_DIV_10;
+               else
+                       fb_div_selection = FPGA_FB_DIV_20;
+       }
+
+       /* Determine VCO divisors values */
+       vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;
+
+       switch(vco_div_reg_value) {
+               case FPGA_REG16_VCO_DIV_4:
+                       vco_div_selection = FPGA_VCO_DIV_4;
+                       break;
+               case FPGA_REG16_VCO_DIV_6:
+                       vco_div_selection = FPGA_VCO_DIV_6;
+                       break;
+               case FPGA_REG16_VCO_DIV_8:
+                       vco_div_selection = FPGA_VCO_DIV_8;
+                       break;
+               case FPGA_REG16_VCO_DIV_10:
+               default:
+                       vco_div_selection = FPGA_VCO_DIV_10;
+                       break;
+       }
+
+       if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
+               switch(master_clock_per) {
+                       case PERIOD_25_00MHZ:
+                               if (fb_div_selection == FPGA_FB_DIV_12) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_4)
+                                               sys_per = PERIOD_75_00MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_50_00MHZ;
+                               }
+                               break;
+                       case PERIOD_33_33MHZ:
+                               if (fb_div_selection == FPGA_FB_DIV_6) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_4)
+                                               sys_per = PERIOD_50_00MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_33_33MHZ;
+                               }
+                               if (fb_div_selection == FPGA_FB_DIV_10) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_4)
+                                               sys_per = PERIOD_83_33MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_10)
+                                               sys_per = PERIOD_33_33MHZ;
+                               }
+                               if (fb_div_selection == FPGA_FB_DIV_12) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_4)
+                                               sys_per = PERIOD_100_00MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_66_66MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_8)
+                                               sys_per = PERIOD_50_00MHZ;
+                               }
+                               break;
+                       case PERIOD_50_00MHZ:
+                               if (fb_div_selection == FPGA_FB_DIV_6) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_4)
+                                               sys_per = PERIOD_75_00MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_50_00MHZ;
+                               }
+                               if (fb_div_selection == FPGA_FB_DIV_10) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_83_33MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_10)
+                                               sys_per = PERIOD_50_00MHZ;
+                               }
+                               if (fb_div_selection == FPGA_FB_DIV_12) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_100_00MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_8)
+                                               sys_per = PERIOD_75_00MHZ;
+                               }
+                               break;
+                       case PERIOD_66_66MHZ:
+                               if (fb_div_selection == FPGA_FB_DIV_6) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_4)
+                                               sys_per = PERIOD_100_00MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_6)
+                                               sys_per = PERIOD_66_66MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_8)
+                                               sys_per = PERIOD_50_00MHZ;
+                               }
+                               if (fb_div_selection == FPGA_FB_DIV_10) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_8)
+                                               sys_per = PERIOD_83_33MHZ;
+                                       if (vco_div_selection == FPGA_VCO_DIV_10)
+                                               sys_per = PERIOD_66_66MHZ;
+                               }
+                               if (fb_div_selection == FPGA_FB_DIV_12) {
+                                       if (vco_div_selection == FPGA_VCO_DIV_8)
+                                               sys_per = PERIOD_100_00MHZ;
+                               }
+                               break;
+                       default:
+                               break;
+               }
+
+               if (sys_per == 0) {
+                       /* Other combinations are not supported */
+                       DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
+                       hang();
+               }
+       } else {
+               /* calcul system clock without cheking */
+               /* if engineering option clock no check is selected */
+               /* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
+               sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
+       }
+
+       return(sys_per);
+
+}
+
+/*-------------------------------------------------------------------------+
+| determine_pci_clock_per.
++-------------------------------------------------------------------------*/
+unsigned long determine_pci_clock_per(void)
+{
+       unsigned long pci_clock_selection,  pci_period;
+
+       /*-------------------------------------------------------------------------+
+        | Read FPGA reg 6 to get PCI 0 FPGA reg information
+        +-------------------------------------------------------------------------*/
+       pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */
+
+
+       pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;
+
+       switch (pci_clock_selection) {
+               case FPGA_REG16_PCI0_CLK_133_33:
+                       pci_period = PERIOD_133_33MHZ;
+                       break;
+               case FPGA_REG16_PCI0_CLK_100:
+                       pci_period = PERIOD_100_00MHZ;
+                       break;
+               case FPGA_REG16_PCI0_CLK_66_66:
+                       pci_period = PERIOD_66_66MHZ;
+                       break;
+               default:
+                       pci_period = PERIOD_33_33MHZ;;
+                       break;
+       }
+
+       return(pci_period);
 }
 #endif
 
index 48b430d14d8583042f68dd2741fba99326f8fa9b..c1e787f680305020da22566570ee7d3210f0ede1 100644 (file)
 
 /**************************************************************************/
 _start_440:
+       /*----------------------------------------------------------------+
+       | Core bug fix.  Clear the esr
+       +-----------------------------------------------------------------*/
+        addi   r0,r0,0x0000
+        mtspr  esr,r0
        /*----------------------------------------------------------------*/
        /* Clear and set up some registers. */
        /*----------------------------------------------------------------*/
@@ -166,7 +171,7 @@ _start_440:
        mtspr   srr1,r0
        mtspr   csrr0,r0
        mtspr   csrr1,r0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)  /* NOTE: 440GX adds machine check status regs */
        mtspr   mcsrr0,r0
        mtspr   mcsrr1,r0
        mfspr   r1, mcsr
@@ -200,6 +205,33 @@ _start_440:
        ori     r1,r1,0x6000    /* cache touch */
        mtspr   ccr0,r1
 
+#if defined (CONFIG_440SPE)
+       /*----------------------------------------------------------------+
+       | Initialize Core Configuration Reg1.
+       | a. ICDPEI: Record even parity. Normal operation.
+       | b. ICTPEI: Record even parity. Normal operation.
+       | c. DCTPEI: Record even parity. Normal operation.
+       | d. DCDPEI: Record even parity. Normal operation.
+       | e. DCUPEI: Record even parity. Normal operation.
+       | f. DCMPEI: Record even parity. Normal operation.
+       | g. FCOM:   Normal operation
+       | h. MMUPEI: Record even parity. Normal operation.
+       | i. FFF:    Flush only as much data as necessary.
+       | j. TCS:    Timebase increments from externally supplied clock
+       +-----------------------------------------------------------------*/
+       addis   r0, r0, 0x0000
+       ori     r0, r0, 0x0080
+       mtspr   ccr1, r0
+
+       /*----------------------------------------------------------------+
+       | Reset the timebase.
+       | The previous write to CCR1 sets the timebase source.
+       +-----------------------------------------------------------------*/
+       addi    r0, r0, 0x0000
+       mtspr   tbl, r0
+       mtspr   tbu, r0
+#endif
+
        /*----------------------------------------------------------------*/
        /* Setup interrupt vectors */
        /*----------------------------------------------------------------*/
@@ -261,15 +293,26 @@ _start_440:
        mtspr   ivlim,r1
        mtspr   dvlim,r1
 
+       /*----------------------------------------------------------------+
+       |Initialize MMUCR[STID] = 0.
+       +-----------------------------------------------------------------*/
+       mfspr   r0,mmucr
+       addis   r1,0,0xFFFF
+       ori     r1,r1,0xFF00
+       and     r0,r0,r1
+       mtspr   mmucr,r0
+
        /*----------------------------------------------------------------*/
        /* Clear all TLB entries -- TID = 0, TS = 0 */
        /*----------------------------------------------------------------*/
-       mtspr   mmucr,r0
+       addis   r0,0,0x0000
        li      r1,0x003f       /* 64 TLB entries */
        mtctr   r1
-0:     tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
+rsttlb:        tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
+       tlbwe   r0,r1,0x0001
+       tlbwe   r0,r1,0x0002
        subi    r1,r1,0x0001
-       bdnz    0b
+       bdnz    rsttlb
 
        /*----------------------------------------------------------------*/
        /* TLB entry setup -- step thru tlbtab */
@@ -340,7 +383,7 @@ _start:
        mtspr   tcr,r0                  /* disable all */
        mtspr   esr,r0                  /* clear exception syndrome register */
        mtxer   r0                      /* clear integer exception register */
-#if !defined(CONFIG_440GX)
+#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
        lis     r1,0x0002               /* set CE bit (Critical Exceptions) */
        ori     r1,r1,0x1000            /* set ME bit (Machine Exceptions) */
        mtmsr   r1                      /* change MSR */
@@ -394,7 +437,7 @@ __440gx_msr_continue:
        addi    r3,r3,32
        bdnz    ..d_ag
 #else
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
        mtdcr   l2_cache_cfg,r0         /* Ensure L2 Cache is off */
 #endif
        mtdcr   isram0_sb1cr,r0         /* Disable bank 1 */
@@ -421,6 +464,19 @@ __440gx_msr_continue:
        lis     r1, 0x8003
        ori     r1,r1, 0x0980           /* fourth 64k */
        mtdcr   isram0_sb3cr,r1
+#elif defined(CONFIG_440SPE)
+       lis     r1,0x0000               /* BAS = 0000_0000 */
+       ori     r1,r1,0x0984            /* first 64k */
+       mtdcr   isram0_sb0cr,r1
+       lis     r1,0x0001
+       ori     r1,r1,0x0984            /* second 64k */
+       mtdcr   isram0_sb1cr,r1
+       lis     r1, 0x0002
+       ori     r1,r1, 0x0984           /* third 64k */
+       mtdcr   isram0_sb2cr,r1
+       lis     r1, 0x0003
+       ori     r1,r1, 0x0984           /* fourth 64k */
+       mtdcr   isram0_sb3cr,r1
 #else
        ori     r1,r1,0x0380            /* 8k rw */
        mtdcr   isram0_sb0cr,r1
@@ -1220,7 +1276,7 @@ ppcSync:
  */
        .globl  relocate_code
 relocate_code:
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
        dccci   0,0                         /* Invalidate data cache, now no longer our stack */
        sync
        addi    r1,r0,0x0000            /* TLB entry #0 */
index cbfe41db9cc0b33eb8a74dc9e2d525b0eb6def81..93cef026a3f77b671d25d2c09249724e01b25006 100644 (file)
 #ifndef _VECNUMS_H_
 #define _VECNUMS_H_
 
-#if defined(CONFIG_440SP)
+#if defined(CONFIG_440SPE)
+/* UIC 0 */
+#define VECNUM_U0           0           /* UART0                        */
+#define VECNUM_U1           1           /* UART1                        */
+#define VECNUM_IIC0         2           /* IIC0                         */
+#define VECNUM_IIC1         3           /* IIC1                         */
+#define VECNUM_PIM          4           /* PCI inbound message          */
+#define VECNUM_PCRW         5           /* PCI command reg write        */
+#define VECNUM_PPM          6           /* PCI power management         */
+#define VECNUM_MSI0         7           /* PCI MSI level 0              */
+#define VECNUM_MSI1         8           /* PCI MSI level 0              */
+#define VECNUM_MSI2         9           /* PCI MSI level 0              */
+#define VECNUM_D0           12          /* DMA channel 0                */
+#define VECNUM_D1           13          /* DMA channel 1                */
+#define VECNUM_D2           14          /* DMA channel 2                */
+#define VECNUM_D3           15          /* DMA channel 3                */
+#define VECNUM_UIC1NC       30          /* UIC1 non-critical interrupt  */
+#define VECNUM_UIC1C        31          /* UIC1 critical interrupt      */
+
+/* UIC 1 */
+#define VECNUM_MS           (32 + 1 )   /* MAL SERR                     */
+#define VECNUM_TXDE         (32 + 2 )   /* MAL TXDE                     */
+#define VECNUM_RXDE         (32 + 3 )   /* MAL RXDE                     */
+#define VECNUM_MTE          (32 + 6 )   /* MAL Tx EOB                   */
+#define VECNUM_MRE          (32 + 7 )   /* MAL Rx EOB                   */
+#define VECNUM_CT0          (32 + 12 )  /* GPT compare timer 0          */
+#define VECNUM_CT1          (32 + 13 )  /* GPT compare timer 1          */
+#define VECNUM_CT2          (32 + 14 )  /* GPT compare timer 2          */
+#define VECNUM_CT3          (32 + 15 )  /* GPT compare timer 3          */
+#define VECNUM_CT4          (32 + 16 )  /* GPT compare timer 4          */
+#define VECNUM_ETH0         (32 + 28)   /* Ethernet interrupt status    */
+#define VECNUM_EWU0         (32 + 29)   /* Emac  wakeup                 */
+
+/* UIC 2 */
+#define VECNUM_EIR5         (62 + 24)   /* External interrupt 5         */
+#define VECNUM_EIR4         (62 + 25)   /* External interrupt 4         */
+#define VECNUM_EIR3         (62 + 26)   /* External interrupt 3         */
+#define VECNUM_EIR2         (62 + 27)   /* External interrupt 2         */
+#define VECNUM_EIR1         (62 + 28)   /* External interrupt 1         */
+#define VECNUM_EIR0         (62 + 29)   /* External interrupt 0         */
+
+#elif defined(CONFIG_440SP)
 
 /* UIC 0 */
 #define VECNUM_U0           0           /* UART0                        */
index e8f19f57010dfcb49d1258b38794f720661fb57c..0ae470141391053eade4383deefdac66e769db3d 100644 (file)
@@ -52,7 +52,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
        cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
        return 0;                                                        \
 }
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)                       \
 static int                                                              \
 indirect_##rw##_config_##size(struct pci_controller *hose,              \
index 69d20c98ffd3b96db59109126106e7dbccdcf306..05985869534b440a38750e39e954cb07ba000c0e 100644 (file)
 #define MAL_ESR_PBEI     0x00000001
       /* ^^                     ^^   */
       /* Mal IER                     */
+#ifdef CONFIG_440SPE
+#define MAL_IER_PT       0x00000080
+#define MAL_IER_PRE      0x00000040
+#define MAL_IER_PWE      0x00000020
+#define MAL_IER_DE       0x00000010
+#define MAL_IER_OTE      0x00000004
+#define MAL_IER_OE       0x00000002
+#define MAL_IER_PE       0x00000001
+#else
 #define MAL_IER_DE       0x00000010
 #define MAL_IER_NE       0x00000008
 #define MAL_IER_TE       0x00000004
 #define MAL_IER_OPBE     0x00000002
 #define MAL_IER_PLBE     0x00000001
+#endif
 
 /* MAL Channel Active Set and Reset Registers */
 #define MAL_TXRX_CASR  (0x80000000)
index 2606b79a2495d31463db0f642c6ead44a67dff30..baaf6f79766d4c08df4ac72ade89ecfd32350c54 100644 (file)
@@ -470,4 +470,45 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_SIZE_1G          (LAWAR_SIZE_BASE+19)
 #define LAWAR_SIZE_2G          (LAWAR_SIZE_BASE+20)
 
+#ifdef CONFIG_440SPE
+/*----------------------------------------------------------------------------+
+| Following instructions are not available in Book E mode of the GNU assembler.
++----------------------------------------------------------------------------*/
+#define DCCCI(ra,rb)                   .long 0x7c000000|\
+                                       (ra<<16)|(rb<<11)|(454<<1)
+
+#define ICCCI(ra,rb)                   .long 0x7c000000|\
+                                       (ra<<16)|(rb<<11)|(966<<1)
+
+#define DCREAD(rt,ra,rb)               .long 0x7c000000|\
+                                       (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
+
+#define ICREAD(ra,rb)                  .long 0x7c000000|\
+                                       (ra<<16)|(rb<<11)|(998<<1)
+
+#define TLBSX(rt,ra,rb)                        .long 0x7c000000|\
+                                       (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
+
+#define TLBWE(rs,ra,ws)                        .long 0x7c000000|\
+                                       (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
+
+#define TLBRE(rt,ra,ws)                        .long 0x7c000000|\
+                                       (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+
+#define TLBSXDOT(rt,ra,rb)             .long 0x7c000001|\
+                                       (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
+
+#define MSYNC                          .long 0x7c000000|\
+                                       (598<<1)
+
+#define MBAR_INST                              .long 0x7c000000|\
+                                       (854<<1)
+
+/*----------------------------------------------------------------------------+
+| Following instruction is not available in PPC405 mode of the GNU assembler.
++----------------------------------------------------------------------------*/
+#define TLBRE(rt,ra,ws)                        .long 0x7c000000|\
+                                       (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+
+#endif
 #endif /* _PPC_MMU_H_ */
index 811378383dfe5dd9ef604308b46174fcd52e9c81..9a9b8ba7161ad7348be9b3d6c2cfbb11087f07c9 100644 (file)
 #define PVR_405EP_RB   0x51210950
 #define PVR_440SP_RA   0x53221850
 #define PVR_440SP_RB   0x53221891
+#define PVR_440SPe_RA  0x53421890
+#define PVR_440SPe_RB  0x53521891
 #define PVR_601                0x00010000
 #define PVR_602                0x00050000
 #define PVR_603                0x00030000
index d2570a803ea45eb96b924c956e015a3d3f7df65d..408d1422b678b851f7f5e47d24f4d2a22d48e40b 100644 (file)
@@ -457,6 +457,10 @@ void       get_sys_info  ( sys_info_t * );
 #if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
 #  if defined(CONFIG_440)
     typedef PPC440_SYS_INFO sys_info_t;
+#      if defined(CONFIG_440SPE)
+        unsigned long determine_sysper(void);
+        unsigned long determine_pci_clock_per(void);
+#      endif
 #  else
     typedef PPC405_SYS_INFO sys_info_t;
 #  endif
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
new file mode 100644 (file)
index 0000000..95de1ea
--- /dev/null
@@ -0,0 +1,518 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * 1 january 2005      Alain Saurel <asaurel@amcc.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+/************************************************************************
+ * yucca.h - configuration for AMCC 440SPe Ref (yucca)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+#define         CONFIG_IDENT_STRING "\nU_440SPe_V1R01 level06"
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_4xx                     1       /* ... PPC4xx family    */
+#define CONFIG_440                     1       /* ... PPC440 family    */
+#define CONFIG_440SPE                  1       /* Specifc SPe support  */
+#define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init  */
+#undef CFG_DRAM_TEST                           /* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ    33333333        /* external freq to pll */
+#define EXTCLK_33_33           33333333
+#define EXTCLK_66_66           66666666
+#define EXTCLK_50              50000000
+#define EXTCLK_83              83333333
+
+#define        CONFIG_IBM_EMAC4_V4             1
+#define        CONFIG_MISC_INIT_F              1       /* Use misc_init_f()    */
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+#undef  CONFIG_STRESS
+#undef  ENABLE_ECC
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE         0x00000000      /* _must_ be 0          */
+#define CFG_FLASH_BASE         0xfff00000      /* start of FLASH       */
+#define CFG_MONITOR_BASE       0xfffb0000      /* start of monitor     */
+#define CFG_PERIPHERAL_BASE    0xa0000000      /* internal peripherals */
+#define CFG_ISRAM_BASE         0x90000000      /* internal SRAM        */
+
+#define CFG_PCI_MEMBASE                0x80000000      /* mapped pci memory    */
+#define CFG_PCI_MEMBASE1       0x90000000      /* mapped pci memory    */
+#define CFG_PCI_MEMBASE2       0xa0000000      /* mapped pci memory    */
+#define CFG_PCI_MEMBASE3       0xb0000000      /* mapped pci memory    */
+
+#define CFG_PCI_BASE           0xd0000000      /* internal PCI regs    */
+#define CFG_PCI_TARGBASE       0x80000000      /*PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* #define CFG_PCI_BASE_IO     0xB8000000 */   /* internal PCI I-O     */
+/* #define CFG_PCI_BASE_REGS   0xBEC00000 */   /* internal PCI regs    */
+/* #define CFG_PCI_BASE_CYCLE  0xBED00000 */   /* internal PCI regs    */
+
+#define CFG_FPGA_BASE          0xe2000000      /* epld                 */
+#define CFG_OPER_FLASH         0xe7000000      /* SRAM - OPER Flash    */
+
+/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM     1
+#define CFG_OCM_DATA_ADDR      CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR      CFG_ISRAM_BASE  /* Initial RAM address  */
+#define CFG_INIT_RAM_END       0x2000          /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE      128             /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR     (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET     CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN                (320 * 1024)    /* Reserve 320 kB for Mon */
+#define CFG_MALLOC_LEN         (512 * 1024)    /* Reserve 512 kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI    1
+#undef CONFIG_UART1_CONSOLE
+
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK
+/* #define CFG_EXT_SERIAL_CLOCK        (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
+
+#define CONFIG_BAUDRATE                115200
+
+#define CFG_BAUDRATE_TABLE  \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
+#define SPD_EEPROM_ADDRESS {0x53, 0x52}        /* SPD i2c spd addresses        */
+#define IIC0_DIMM0_ADDR                0x53
+#define IIC0_DIMM1_ADDR                0x52
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C                1       /* I2C with hardware support    */
+#undef CONFIG_SOFT_I2C                 /* I2C bit-banged               */
+#define CFG_I2C_SPEED          400000  /* I2C speed and slave address  */
+#define CFG_I2C_SLAVE          0x7F
+
+#define IIC0_BOOTPROM_ADDR     0x50
+#define IIC0_ALT_BOOTPROM_ADDR 0x54
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES       {0x50, 0x52, 0x53, 0x54}
+
+/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
+/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM              */
+#define CFG_I2C_EEPROM_ADDR_LEN        2       /* Bytes of address             */
+/* #endif */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/* #define CFG_NVRAM_SIZE      (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
+
+#undef  CFG_ENV_IS_IN_NVRAM            /* ... not in NVRAM             */
+#define        CFG_ENV_IS_IN_FLASH     1       /* Environment uses flash       */
+#undef CFG_ENV_IS_IN_EEPROM            /* ... not in EEPROM            */
+#define CONFIG_ENV_OVERWRITE   1
+
+#define CONFIG_BOOTARGS                "console=ttyS0,115200n8 root=/dev/nfs rw"
+#define CONFIG_BOOTCOMMAND     "bootm E7C00000"        /* autoboot command */
+#define CONFIG_BOOTDELAY       -1      /* -1 to disable autoboot */
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#undef CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR                1       /* PHY address, See schematics  */
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET        1      /* reset phy upon startup       */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_CIS8201_PHY     1       /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE                1       /* Include GbE speed/duplex detection */
+#define CONFIG_NETMASK         255.255.0.0
+#define CONFIG_IPADDR          192.168.80.10
+#define CONFIG_ETHADDR         00:04:AC:01:CA:FE
+#define CFG_RX_ETH_BUFFER      32      /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SERVERIP                192.168.1.1
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "loads_echo=1\0"                                                \
+       "netdev=eth0\0"                                                 \
+       "hostname=yucca\0"                                              \
+       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
+       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
+       "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+       "flash_nfs=run nfsargs addip addtty;"                           \
+               "bootm ${kernel_addr}\0"                                \
+       "flash_self=run ramargs addip addtty;"                          \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+               "bootm\0"                                               \
+       "rootpath=/opt/eldk-4.0/ppc_4xx\0"                              \
+       "bootfile=yucca/uImage\0"                                       \
+       "kernel_addr=E7F10000\0"                                        \
+       "ramdisk_addr=E7F20000\0"                                       \
+       "load=tftp 100000 yuca/u-boot.bin\0"                            \
+       "update=protect off 2:4-7;era 2:4-7;"                           \
+               "cp.b ${fileaddr} fffc0000 ${filesize};"                \
+               "setenv filesize;saveenv\0"                             \
+       "upd=run load;run update\0"                                     \
+       ""
+
+#define CONFIG_COMMANDS        (CONFIG_CMD_DFL         | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_DIAG    | \
+                               CFG_CMD_NET     | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_EEPROM  | \
+                               CFG_CMD_ELF     )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                           /* undef to save memory         */
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt       */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024            /* Console I/O Buffer Size      */
+#else
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE             (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on             */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM          */
+
+#define CFG_LOAD_ADDR          0x100000        /* default load address         */
+#define CFG_EXTBDINFO          1               /* To use extended board_into (bd_t) */
+
+#define CFG_HZ                 1               /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS    3       /* number of banks              */
+#define CFG_MAX_FLASH_SECT     256     /* sectors per device           */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0                0x5555
+#define CFG_FLASH_ADDR1                0x2aaa
+#define CFG_FLASH_WORD_SIZE    unsigned char
+
+#define CFG_FLASH_2ND_16BIT_DEV        1       /* evb440SPe has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR     0xe7c00000 /* evb440SPe has 8 and 16bit device*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE      0x10000 /* size of one complete sector  */
+#define CFG_ENV_ADDR           0xfffa0000
+/* #define CFG_ENV_ADDR                (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
+#define CFG_ENV_SIZE           0x10000 /* Size of Environment vars     */
+#endif /* CFG_ENV_IS_IN_FLASH */
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_PNP         1       /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW   i       /* show pci devices on startup  */
+#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT       1       /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT            /* let board init pci target    */
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM                          */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever                     */
+/* #define CFG_PCI_SUBSYS_ID   CFG_PCI_SUBSYS_DEVICEID */
+
+/*
+ *  NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /*Initial Memory map for Linux*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE                8192    /* For AMCC 405 CPUs            */
+#define CFG_CACHELINE_SIZE     32      /* ...                          */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM  0x02            /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
+#endif
+
+/* FB Divisor selection */
+#define FPGA_FB_DIV_6          6
+#define FPGA_FB_DIV_10         10
+#define FPGA_FB_DIV_12         12
+#define FPGA_FB_DIV_20         20
+
+/* VCO Divisor selection */
+#define        FPGA_VCO_DIV_4          4
+#define        FPGA_VCO_DIV_6          6
+#define        FPGA_VCO_DIV_8          8
+#define        FPGA_VCO_DIV_10         10
+
+/*----------------------------------------------------------------------------+
+| FPGA registers and bit definitions
++----------------------------------------------------------------------------*/
+/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
+/* TLB initialization makes it correspond to logical address 0xE2000000. */
+/* => Done init_chip.s in bootlib */
+#define FPGA_REG_BASE_ADDR     0xE2000000
+#define FPGA_GPIO_BASE_ADDR    0xE2010000
+#define FPGA_INT_BASE_ADDR     0xE2020000
+
+/*----------------------------------------------------------------------------+
+| Display
++----------------------------------------------------------------------------*/
+#define PPC440SPE_DISPLAY      FPGA_REG_BASE_ADDR
+
+#define PPC440SPE_DISPLAY_D8   (FPGA_REG_BASE_ADDR+0x06)
+#define PPC440SPE_DISPLAY_D4   (FPGA_REG_BASE_ADDR+0x04)
+#define PPC440SPE_DISPLAY_D2   (FPGA_REG_BASE_ADDR+0x02)
+#define PPC440SPE_DISPLAY_D1   (FPGA_REG_BASE_ADDR+0x00)
+/*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
+/*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
+
+/*----------------------------------------------------------------------------+
+| ethernet/reset/boot Register 1
++----------------------------------------------------------------------------*/
+#define FPGA_REG10     (FPGA_REG_BASE_ADDR+0x10)
+
+#define FPGA_REG10_10MHZ_ENABLE                0x8000
+#define FPGA_REG10_100MHZ_ENABLE       0x4000
+#define FPGA_REG10_GIGABIT_ENABLE      0x2000
+#define FPGA_REG10_FULL_DUPLEX         0x1000  /* force Full Duplex*/
+#define FPGA_REG10_RESET_ETH           0x0800
+#define FPGA_REG10_AUTO_NEG_DIS                0x0400
+#define FPGA_REG10_INTP_ETH            0x0200
+
+#define FPGA_REG10_RESET_HISR          0x0080
+#define FPGA_REG10_ENABLE_DISPLAY      0x0040
+#define FPGA_REG10_RESET_SDRAM         0x0020
+#define FPGA_REG10_OPER_BOOT           0x0010
+#define FPGA_REG10_SRAM_BOOT           0x0008
+#define FPGA_REG10_SMALL_BOOT          0x0004
+#define FPGA_REG10_FORCE_COLA          0x0002
+#define FPGA_REG10_COLA_MANUAL         0x0001
+
+#define FPGA_REG10_SDRAM_ENABLE                0x0020
+
+#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
+#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
+
+/*----------------------------------------------------------------------------+
+| MUX control
++----------------------------------------------------------------------------*/
+#define FPGA_REG12     (FPGA_REG_BASE_ADDR+0x12)
+
+#define FPGA_REG12_EBC_CTL             0x8000
+#define FPGA_REG12_UART1_CTS_RTS       0x4000
+#define FPGA_REG12_UART0_RX_ENABLE     0x2000
+#define FPGA_REG12_UART1_RX_ENABLE     0x1000
+#define FPGA_REG12_UART2_RX_ENABLE     0x0800
+#define FPGA_REG12_EBC_OUT_ENABLE      0x0400
+#define FPGA_REG12_GPIO0_OUT_ENABLE    0x0200
+#define FPGA_REG12_GPIO1_OUT_ENABLE    0x0100
+#define FPGA_REG12_GPIO_SELECT         0x0010
+#define FPGA_REG12_GPIO_CHREG          0x0008
+#define FPGA_REG12_GPIO_CLK_CHREG      0x0004
+#define FPGA_REG12_GPIO_OETRI          0x0002
+#define FPGA_REG12_EBC_ERROR           0x0001
+
+/*----------------------------------------------------------------------------+
+| PCI Clock control
++----------------------------------------------------------------------------*/
+#define FPGA_REG16     (FPGA_REG_BASE_ADDR+0x16)
+
+#define FPGA_REG16_PCI_CLK_CTL0                0x8000
+#define FPGA_REG16_PCI_CLK_CTL1                0x4000
+#define FPGA_REG16_PCI_CLK_CTL2                0x2000
+#define FPGA_REG16_PCI_CLK_CTL3                0x1000
+#define FPGA_REG16_PCI_CLK_CTL4                0x0800
+#define FPGA_REG16_PCI_CLK_CTL5                0x0400
+#define FPGA_REG16_PCI_CLK_CTL6                0x0200
+#define FPGA_REG16_PCI_CLK_CTL7                0x0100
+#define FPGA_REG16_PCI_CLK_CTL8                0x0080
+#define FPGA_REG16_PCI_CLK_CTL9                0x0040
+#define FPGA_REG16_PCI_EXT_ARB0                0x0020
+#define FPGA_REG16_PCI_MODE_1          0x0010
+#define FPGA_REG16_PCI_TARGET_MODE     0x0008
+#define FPGA_REG16_PCI_INTP_MODE       0x0004
+
+/* FB1 Divisor selection */
+#define FPGA_REG16_FB2_DIV_MASK                0x1000
+#define FPGA_REG16_FB2_DIV_LOW         0x0000
+#define FPGA_REG16_FB2_DIV_HIGH                0x1000
+/* FB2 Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_FB1_DIV_MASK                0x2000
+#define FPGA_REG16_FB1_DIV_LOW         0x0000
+#define FPGA_REG16_FB1_DIV_HIGH                0x2000
+/* PCI0 Clock Selection */
+/* S3 switch on Board */
+#define FPGA_REG16_PCI0_CLK_MASK       0x0c00
+#define FPGA_REG16_PCI0_CLK_33_33      0x0000
+#define FPGA_REG16_PCI0_CLK_66_66      0x0800
+#define FPGA_REG16_PCI0_CLK_100                0x0400
+#define FPGA_REG16_PCI0_CLK_133_33     0x0c00
+/* VCO Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_VCO_DIV_MASK                0xc000
+#define FPGA_REG16_VCO_DIV_4           0x0000
+#define FPGA_REG16_VCO_DIV_8           0x4000
+#define FPGA_REG16_VCO_DIV_6           0x8000
+#define FPGA_REG16_VCO_DIV_10          0xc000
+/* Master Clock Selection */
+/* S3, S4 switches on Board */
+#define FPGA_REG16_MASTER_CLK_MASK     0x01c0
+#define FPGA_REG16_MASTER_CLK_EXT      0x0000
+#define FPGA_REG16_MASTER_CLK_66_66    0x0040
+#define FPGA_REG16_MASTER_CLK_50       0x0080
+#define FPGA_REG16_MASTER_CLK_33_33    0x00c0
+#define FPGA_REG16_MASTER_CLK_25       0x0100
+
+/*----------------------------------------------------------------------------+
+| PCI Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG18     (FPGA_REG_BASE_ADDR+0x18)
+
+#define FPGA_REG18_PCI_PRSNT1          0x8000
+#define FPGA_REG18_PCI_PRSNT2          0x4000
+#define FPGA_REG18_PCI_INTA            0x2000
+#define FPGA_REG18_PCI_SLOT0_INTP      0x1000
+#define FPGA_REG18_PCI_SLOT1_INTP      0x0800
+#define FPGA_REG18_PCI_SLOT2_INTP      0x0400
+#define FPGA_REG18_PCI_SLOT3_INTP      0x0200
+#define FPGA_REG18_PCI_PCI0_VC         0x0100
+#define FPGA_REG18_PCI_PCI0_VTH1       0x0080
+#define FPGA_REG18_PCI_PCI0_VTH2       0x0040
+#define FPGA_REG18_PCI_PCI0_VTH3       0x0020
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1A     (FPGA_REG_BASE_ADDR+0x1A)
+
+#define FPGA_REG1A_PE0_GLED            0x8000
+#define FPGA_REG1A_PE1_GLED            0x4000
+#define FPGA_REG1A_PE2_GLED            0x2000
+#define FPGA_REG1A_PE0_YLED            0x1000
+#define FPGA_REG1A_PE1_YLED            0x0800
+#define FPGA_REG1A_PE2_YLED            0x0400
+#define FPGA_REG1A_PE0_PWRON           0x0200
+#define FPGA_REG1A_PE1_PWRON           0x0100
+#define FPGA_REG1A_PE2_PWRON           0x0080
+#define FPGA_REG1A_PE0_REFCLK_ENABLE   0x0040
+#define FPGA_REG1A_PE1_REFCLK_ENABLE   0x0020
+#define FPGA_REG1A_PE2_REFCLK_ENABLE   0x0010
+#define FPGA_REG1A_PE_SPREAD0          0x0008
+#define FPGA_REG1A_PE_SPREAD1          0x0004
+#define FPGA_REG1A_PE_SELSOURCE_0      0x0002
+#define FPGA_REG1A_PE_SELSOURCE_1      0x0001
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1C     (FPGA_REG_BASE_ADDR+0x1C)
+
+#define FPGA_REG1C_PE0_ROOTPOINT       0x8000
+#define FPGA_REG1C_PE1_ENDPOINT                0x4000
+#define FPGA_REG1C_PE2_ENDPOINT                0x2000
+#define FPGA_REG1C_PE0_PRSNT           0x1000
+#define FPGA_REG1C_PE1_PRSNT           0x0800
+#define FPGA_REG1C_PE2_PRSNT           0x0400
+#define FPGA_REG1C_PE0_WAKE            0x0080
+#define FPGA_REG1C_PE1_WAKE            0x0040
+#define FPGA_REG1C_PE2_WAKE            0x0020
+#define FPGA_REG1C_PE0_PERST           0x0010
+#define FPGA_REG1C_PE1_PERST           0x0080
+#define FPGA_REG1C_PE2_PERST           0x0040
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+#define PERIOD_133_33MHZ       7500    /* 7,5ns */
+#define PERIOD_100_00MHZ       10000   /* 10ns */
+#define PERIOD_83_33MHZ                12000   /* 12ns */
+#define PERIOD_75_00MHZ                13333   /* 13,333ns */
+#define PERIOD_66_66MHZ                15000   /* 15ns */
+#define PERIOD_50_00MHZ                20000   /* 20ns */
+#define PERIOD_33_33MHZ                30000   /* 30ns */
+#define PERIOD_25_00MHZ                40000   /* 40ns */
+
+/*---------------------------------------------------------------------------*/
+
+#endif /* __CONFIG_H */
index 018f7be8ac0090ec5a3d4edbe64ccb191eb0cad2..6f73c327ac4e77ba569d155d0ae8ed2dd7d7fd34 100644 (file)
@@ -25,6 +25,8 @@
 /*--------------------------------------------------------------------- */
 /* Special Purpose Registers                                           */
 /*--------------------------------------------------------------------- */
+#define         xer_reg 0x001
+#define         lr_reg 0x008
 #define         dec    0x016   /* decrementer */
 #define         srr0   0x01a   /* save/restore register 0 */
 #define         srr1   0x01b   /* save/restore register 1 */
@@ -37,6 +39,8 @@
 #define         ivpr   0x03f   /* interrupt prefix register */
 #define         usprg0 0x100   /* user special purpose register general 0 */
 #define         usprg1 0x110   /* user special purpose register general 1 */
+#define         tblr   0x10c   /* time base lower, read only */
+#define         tbur   0x10d   /* time base upper, read only */
 #define         sprg1  0x111   /* special purpose register general 1 */
 #define         sprg2  0x112   /* special purpose register general 2 */
 #define         sprg3  0x113   /* special purpose register general 3 */
@@ -78,7 +82,7 @@
 #define         ivor13 0x19d   /* interrupt vector offset register 13 */
 #define         ivor14 0x19e   /* interrupt vector offset register 14 */
 #define         ivor15 0x19f   /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define         mcsrr0 0x23a   /* machine check save/restore register 0 */
 #define         mcsrr1 0x23b   /* mahcine check save/restore register 1 */
 #define         mcsr   0x23c   /* machine check status register */
 #define sdr_malrbl     0x02a0
 #define sdr_maltbs     0x02c0
 #define sdr_malrbs     0x02e0
-#define sdr_pci0        0x0300
-#define sdr_usb0        0x0320
+#define sdr_pci0       0x0300
+#define sdr_usb0       0x0320
 #define sdr_cust0      0x4000
-#define sdr_sdstp2     0x4001
 #define sdr_cust1      0x4002
-#define sdr_sdstp3     0x4003
 #define sdr_pfc0       0x4100  /* Pin Function 0 */
 #define sdr_pfc1       0x4101  /* Pin Function 1 */
 #define sdr_plbtr      0x4200
 #define mem_dlycal     0x0084  /* delay line calibration register          */
 #define mem_eccesr     0x0098  /* ECC error status                         */
 
+#ifdef CONFIG_440_GX
+#define sdr_amp                0x0240
+#define sdr_xpllc      0x01c1
+#define sdr_xplld      0x01c2
+#define sdr_xcr                0x01c0
+#define sdr_sdstp2     0x4001
+#define sdr_sdstp3     0x4003
+#endif /* CONFIG_440_GX */
+
+#ifdef CONFIG_440SPE
+#undef sdr_sdstp2
+#define sdr_sdstp2     0x0022
+#undef sdr_sdstp3
+#define sdr_sdstp3     0x0023
+#define sdr_ddr0       0x00E1
+#define sdr_uart2      0x0122
+#define sdr_xcr0       0x01c0
+/* #define sdr_xcr1    0x01c3  only one PCIX - SG */
+/* #define sdr_xcr2    0x01c6  only one PCIX - SG */
+#define sdr_xpllc0     0x01c1
+#define sdr_xplld0     0x01c2
+#define sdr_xpllc1     0x01c4  /*notRCW  - SG */
+#define sdr_xplld1     0x01c5  /*notRCW  - SG */
+#define sdr_xpllc2     0x01c7  /*notRCW  - SG */
+#define sdr_xplld2     0x01c8  /*notRCW  - SG */
+#define sdr_amp0       0x0240
+#define sdr_amp1       0x0241
+#define sdr_cust2      0x4004
+#define sdr_cust3      0x4006
+#define sdr_sdstp4     0x4001
+#define sdr_sdstp5     0x4003
+#define sdr_sdstp6     0x4005
+#define sdr_sdstp7     0x4007
+
+/*----------------------------------------------------------------------------+
+| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
++----------------------------------------------------------------------------*/
+#define CCR0_PRE               0x40000000
+#define CCR0_CRPE              0x08000000
+#define CCR0_DSTG              0x00200000
+#define CCR0_DAPUIB            0x00100000
+#define CCR0_DTB               0x00008000
+#define CCR0_GICBT             0x00004000
+#define CCR0_GDCBT             0x00002000
+#define CCR0_FLSTA             0x00000100
+#define CCR0_ICSLC_MASK                0x0000000C
+#define CCR0_ICSLT_MASK                0x00000003
+#define CCR1_TCS_MASK          0x00000080
+#define CCR1_TCS_INTCLK                0x00000000
+#define CCR1_TCS_EXTCLK                0x00000080
+#define MMUCR_SEOA             0x01000000
+#define MMUCR_U1TE             0x00400000
+#define MMUCR_U2SWOAE          0x00200000
+#define MMUCR_DULXE            0x00800000
+#define MMUCR_IULXE            0x00400000
+#define MMUCR_STS              0x00100000
+#define MMUCR_STID_MASK                0x000000FF
+
+#define SDR0_CFGADDR           0x00E
+#define SDR0_CFGDATA           0x00F
+
+/******************************************************************************
+ * PCI express defines
+ ******************************************************************************/
+#define SDR0_PE0UTLSET1                0x00000300      /* PE0 Upper transaction layer conf setting */
+#define SDR0_PE0UTLSET2                0x00000301      /* PE0 Upper transaction layer conf setting 2 */
+#define SDR0_PE0DLPSET         0x00000302      /* PE0 Data link & logical physical configuration */
+#define SDR0_PE0LOOP           0x00000303      /* PE0 Loopback interface status */
+#define SDR0_PE0RCSSET         0x00000304      /* PE0 Reset, clock & shutdown setting */
+#define SDR0_PE0RCSSTS         0x00000305      /* PE0 Reset, clock & shutdown status */
+#define SDR0_PE0HSSSET1L0      0x00000306      /* PE0 HSS Control Setting 1: Lane 0 */
+#define SDR0_PE0HSSSET2L0      0x00000307      /* PE0 HSS Control Setting 2: Lane 0 */
+#define SDR0_PE0HSSSTSL0       0x00000308      /* PE0 HSS Control Status : Lane 0 */
+#define SDR0_PE0HSSSET1L1      0x00000309      /* PE0 HSS Control Setting 1: Lane 1 */
+#define SDR0_PE0HSSSET2L1      0x0000030A      /* PE0 HSS Control Setting 2: Lane 1 */
+#define SDR0_PE0HSSSTSL1       0x0000030B      /* PE0 HSS Control Status : Lane 1 */
+#define SDR0_PE0HSSSET1L2      0x0000030C      /* PE0 HSS Control Setting 1: Lane 2 */
+#define SDR0_PE0HSSSET2L2      0x0000030D      /* PE0 HSS Control Setting 2: Lane 2 */
+#define SDR0_PE0HSSSTSL2       0x0000030E      /* PE0 HSS Control Status : Lane 2 */
+#define SDR0_PE0HSSSET1L3      0x0000030F      /* PE0 HSS Control Setting 1: Lane 3 */
+#define SDR0_PE0HSSSET2L3      0x00000310      /* PE0 HSS Control Setting 2: Lane 3 */
+#define SDR0_PE0HSSSTSL3       0x00000311      /* PE0 HSS Control Status : Lane 3 */
+#define SDR0_PE0HSSSET1L4      0x00000312      /* PE0 HSS Control Setting 1: Lane 4 */
+#define SDR0_PE0HSSSET2L4      0x00000313      /* PE0 HSS Control Setting 2: Lane 4 */
+#define SDR0_PE0HSSSTSL4       0x00000314      /* PE0 HSS Control Status : Lane 4 */
+#define SDR0_PE0HSSSET1L5      0x00000315      /* PE0 HSS Control Setting 1: Lane 5 */
+#define SDR0_PE0HSSSET2L5      0x00000316      /* PE0 HSS Control Setting 2: Lane 5 */
+#define SDR0_PE0HSSSTSL5       0x00000317      /* PE0 HSS Control Status : Lane 5 */
+#define SDR0_PE0HSSSET1L6      0x00000318      /* PE0 HSS Control Setting 1: Lane 6 */
+#define SDR0_PE0HSSSET2L6      0x00000319      /* PE0 HSS Control Setting 2: Lane 6 */
+#define SDR0_PE0HSSSTSL6       0x0000031A      /* PE0 HSS Control Status : Lane 6 */
+#define SDR0_PE0HSSSET1L7      0x0000031B      /* PE0 HSS Control Setting 1: Lane 7 */
+#define SDR0_PE0HSSSET2L7      0x0000031C      /* PE0 HSS Control Setting 2: Lane 7 */
+#define SDR0_PE0HSSSTSL7       0x0000031D      /* PE0 HSS Control Status : Lane 7 */
+#define SDR0_PE0HSSSEREN       0x0000031E      /* PE0 Serdes Transmitter Enable */
+#define SDR0_PE0LANEABCD       0x0000031F      /* PE0 Lanes ABCD affectation */
+#define SDR0_PE0LANEEFGH       0x00000320      /* PE0 Lanes EFGH affectation */
+
+#define SDR0_PE1UTLSET1                0x00000340      /* PE1 Upper transaction layer conf setting */
+#define SDR0_PE1UTLSET2                0x00000341      /* PE1 Upper transaction layer conf setting 2 */
+#define SDR0_PE1DLPSET         0x00000342      /* PE1 Data link & logical physical configuration */
+#define SDR0_PE1LOOP           0x00000343      /* PE1 Loopback interface status */
+#define SDR0_PE1RCSSET         0x00000344      /* PE1 Reset, clock & shutdown setting */
+#define SDR0_PE1RCSSTS         0x00000345      /* PE1 Reset, clock & shutdown status */
+#define SDR0_PE1HSSSET1L0      0x00000346      /* PE1 HSS Control Setting 1: Lane 0 */
+#define SDR0_PE1HSSSET2L0      0x00000347      /* PE1 HSS Control Setting 2: Lane 0 */
+#define SDR0_PE1HSSSTSL0       0x00000348      /* PE1 HSS Control Status : Lane 0 */
+#define SDR0_PE1HSSSET1L1      0x00000349      /* PE1 HSS Control Setting 1: Lane 1 */
+#define SDR0_PE1HSSSET2L1      0x0000034A      /* PE1 HSS Control Setting 2: Lane 1 */
+#define SDR0_PE1HSSSTSL1       0x0000034B      /* PE1 HSS Control Status : Lane 1 */
+#define SDR0_PE1HSSSET1L2      0x0000034C      /* PE1 HSS Control Setting 1: Lane 2 */
+#define SDR0_PE1HSSSET2L2      0x0000034D      /* PE1 HSS Control Setting 2: Lane 2 */
+#define SDR0_PE1HSSSTSL2       0x0000034E      /* PE1 HSS Control Status : Lane 2 */
+#define SDR0_PE1HSSSET1L3      0x0000034F      /* PE1 HSS Control Setting 1: Lane 3 */
+#define SDR0_PE1HSSSET2L3      0x00000350      /* PE1 HSS Control Setting 2: Lane 3 */
+#define SDR0_PE1HSSSTSL3       0x00000351      /* PE1 HSS Control Status : Lane 3 */
+#define SDR0_PE1HSSSEREN       0x00000352      /* PE1 Serdes Transmitter Enable */
+#define SDR0_PE1LANEABCD       0x00000353      /* PE1 Lanes ABCD affectation */
+#define SDR0_PE2UTLSET1                0x00000370      /* PE2 Upper transaction layer conf setting */
+#define SDR0_PE2UTLSET2                0x00000371      /* PE2 Upper transaction layer conf setting 2 */
+#define SDR0_PE2DLPSET         0x00000372      /* PE2 Data link & logical physical configuration */
+#define SDR0_PE2LOOP           0x00000373      /* PE2 Loopback interface status */
+#define SDR0_PE2RCSSET         0x00000374      /* PE2 Reset, clock & shutdown setting */
+#define SDR0_PE2RCSSTS         0x00000375      /* PE2 Reset, clock & shutdown status */
+#define SDR0_PE2HSSSET1L0      0x00000376      /* PE2 HSS Control Setting 1: Lane 0 */
+#define SDR0_PE2HSSSET2L0      0x00000377      /* PE2 HSS Control Setting 2: Lane 0 */
+#define SDR0_PE2HSSSTSL0       0x00000378      /* PE2 HSS Control Status : Lane 0 */
+#define SDR0_PE2HSSSET1L1      0x00000379      /* PE2 HSS Control Setting 1: Lane 1 */
+#define SDR0_PE2HSSSET2L1      0x0000037A      /* PE2 HSS Control Setting 2: Lane 1 */
+#define SDR0_PE2HSSSTSL1       0x0000037B      /* PE2 HSS Control Status : Lane 1 */
+#define SDR0_PE2HSSSET1L2      0x0000037C      /* PE2 HSS Control Setting 1: Lane 2 */
+#define SDR0_PE2HSSSET2L2      0x0000037D      /* PE2 HSS Control Setting 2: Lane 2 */
+#define SDR0_PE2HSSSTSL2       0x0000037E      /* PE2 HSS Control Status : Lane 2 */
+#define SDR0_PE2HSSSET1L3      0x0000037F      /* PE2 HSS Control Setting 1: Lane 3 */
+#define SDR0_PE2HSSSET2L3      0x00000380      /* PE2 HSS Control Setting 2: Lane 3 */
+#define SDR0_PE2HSSSTSL3       0x00000381      /* PE2 HSS Control Status : Lane 3 */
+#define SDR0_PE2HSSSEREN       0x00000382      /* PE2 Serdes Transmitter Enable */
+#define SDR0_PE2LANEABCD       0x00000383      /* PE2 Lanes ABCD affectation */
+#define SDR0_PEGPLLSET1                0x000003A0      /* PE Pll LC Tank Setting1 */
+#define SDR0_PEGPLLSET2                0x000003A1      /* PE Pll LC Tank Setting2 */
+#define SDR0_PEGPLLSTS         0x000003A2      /* PE Pll LC Tank Status */
+
+/*----------------------------------------------------------------------------+
+| SDRAM Controller
++----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+| SDRAM DLYCAL Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_DLYCAL_DLCV_MASK         0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x)    (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x)    (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+/*----------------------------------------------------------------------------+
+| Memory queue defines
++----------------------------------------------------------------------------*/
+/* A REVOIR versus RWC  - SG*/
+#define SDRAMQ_DCR_BASE        0x040
+
+#define SDRAM_R0BAS    (SDRAMQ_DCR_BASE+0x0)   /* rank 0 base address & size  */
+#define SDRAM_R1BAS    (SDRAMQ_DCR_BASE+0x1)   /* rank 1 base address & size  */
+#define SDRAM_R2BAS    (SDRAMQ_DCR_BASE+0x2)   /* rank 2 base address & size  */
+#define SDRAM_R3BAS    (SDRAMQ_DCR_BASE+0x3)   /* rank 3 base address & size  */
+#define SDRAM_CONF1HB  (SDRAMQ_DCR_BASE+0x5)   /* configuration 1 HB          */
+#define SDRAM_ERRSTATHB        (SDRAMQ_DCR_BASE+0x7)   /* error status HB             */
+#define SDRAM_ERRADDUHB        (SDRAMQ_DCR_BASE+0x8)   /* error address upper 32 HB   */
+#define SDRAM_ERRADDLHB        (SDRAMQ_DCR_BASE+0x9)   /* error address lower 32 HB   */
+#define SDRAM_PLBADDULL        (SDRAMQ_DCR_BASE+0xA)   /* PLB base address upper 32 LL */
+#define SDRAM_CONF1LL  (SDRAMQ_DCR_BASE+0xB)   /* configuration 1 LL          */
+#define SDRAM_ERRSTATLL        (SDRAMQ_DCR_BASE+0xC)   /* error status LL             */
+#define SDRAM_ERRADDULL        (SDRAMQ_DCR_BASE+0xD)   /* error address upper 32 LL   */
+#define SDRAM_ERRADDLLL        (SDRAMQ_DCR_BASE+0xE)   /* error address lower 32 LL   */
+#define SDRAM_CONFPATHB        (SDRAMQ_DCR_BASE+0xF)   /* configuration between paths */
+#define SDRAM_PLBADDUHB        (SDRAMQ_DCR_BASE+0x10)  /* PLB base address upper 32 LL */
+
+/*-----------------------------------------------------------------------------+
+|  Memory Bank 0-7 configuration
++-----------------------------------------------------------------------------*/
+#define SDRAM_RXBAS_SDBA_MASK          0xFF800000      /* Base address */
+#define SDRAM_RXBAS_SDBA_ENCODE(n)     ((((unsigned long)(n))&0xFFE00000)>>2)
+#define SDRAM_RXBAS_SDBA_DECODE(n)     ((((unsigned long)(n))&0xFFE00000)<<2)
+#define SDRAM_RXBAS_SDSZ_MASK          0x0000FFC0      /* Size         */
+#define SDRAM_RXBAS_SDSZ_ENCODE(n)     ((((unsigned long)(n))&0x3FF)<<6)
+#define SDRAM_RXBAS_SDSZ_DECODE(n)     ((((unsigned long)(n))>>6)&0x3FF)
+#define SDRAM_RXBAS_SDSZ_0             0x00000000      /*   0M         */
+#define SDRAM_RXBAS_SDSZ_8             0x0000FFC0      /*   8M         */
+#define SDRAM_RXBAS_SDSZ_16            0x0000FF80      /*  16M         */
+#define SDRAM_RXBAS_SDSZ_32            0x0000FF00      /*  32M         */
+#define SDRAM_RXBAS_SDSZ_64            0x0000FE00      /*  64M         */
+#define SDRAM_RXBAS_SDSZ_128           0x0000FC00      /* 128M         */
+#define SDRAM_RXBAS_SDSZ_256           0x0000F800      /* 256M         */
+#define SDRAM_RXBAS_SDSZ_512           0x0000F000      /* 512M         */
+#define SDRAM_RXBAS_SDSZ_1024          0x0000E000      /* 1024M        */
+#define SDRAM_RXBAS_SDSZ_2048          0x0000C000      /* 2048M        */
+#define SDRAM_RXBAS_SDSZ_4096          0x00008000      /* 4096M        */
+
+/*----------------------------------------------------------------------------+
+| Memory controller defines
++----------------------------------------------------------------------------*/
+#define SDRAMC_DCR_BASE        0x010
+#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0)   /* Memory configuration add  */
+#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1)   /* Memory configuration data */
+
+/* A REVOIR versus specs 4 bank  - SG*/
+#define SDRAM_MCSTAT   0x14    /* memory controller status                  */
+#define SDRAM_MCOPT1   0x20    /* memory controller options 1               */
+#define SDRAM_MCOPT2   0x21    /* memory controller options 2               */
+#define SDRAM_MODT0    0x22    /* on die termination for bank 0             */
+#define SDRAM_MODT1    0x23    /* on die termination for bank 1             */
+#define SDRAM_MODT2    0x24    /* on die termination for bank 2             */
+#define SDRAM_MODT3    0x25    /* on die termination for bank 3             */
+#define SDRAM_CODT     0x26    /* on die termination for controller         */
+#define SDRAM_VVPR     0x27    /* variable VRef programmming                */
+#define SDRAM_OPARS    0x28    /* on chip driver control setup              */
+#define SDRAM_OPART    0x29    /* on chip driver control trigger            */
+#define SDRAM_RTR      0x30    /* refresh timer                             */
+#define SDRAM_PMIT     0x34    /* power management idle timer               */
+#define SDRAM_MB0CF    0x40    /* memory bank 0 configuration               */
+#define SDRAM_MB1CF    0x44    /* memory bank 1 configuration               */
+#define SDRAM_MB2CF    0x48
+#define SDRAM_MB3CF    0x4C
+#define SDRAM_INITPLR0 0x50    /* manual initialization control             */
+#define SDRAM_INITPLR1 0x51    /* manual initialization control             */
+#define SDRAM_INITPLR2 0x52    /* manual initialization control             */
+#define SDRAM_INITPLR3 0x53    /* manual initialization control             */
+#define SDRAM_INITPLR4 0x54    /* manual initialization control             */
+#define SDRAM_INITPLR5 0x55    /* manual initialization control             */
+#define SDRAM_INITPLR6 0x56    /* manual initialization control             */
+#define SDRAM_INITPLR7 0x57    /* manual initialization control             */
+#define SDRAM_INITPLR8 0x58    /* manual initialization control             */
+#define SDRAM_INITPLR9 0x59    /* manual initialization control             */
+#define SDRAM_INITPLR10        0x5a    /* manual initialization control             */
+#define SDRAM_INITPLR11        0x5b    /* manual initialization control             */
+#define SDRAM_INITPLR12        0x5c    /* manual initialization control             */
+#define SDRAM_INITPLR13        0x5d    /* manual initialization control             */
+#define SDRAM_INITPLR14        0x5e    /* manual initialization control             */
+#define SDRAM_INITPLR15        0x5f    /* manual initialization control             */
+#define SDRAM_RQDC     0x70    /* read DQS delay control                    */
+#define SDRAM_RFDC     0x74    /* read feedback delay control               */
+#define SDRAM_RDCC     0x78    /* read data capture control                 */
+#define SDRAM_DLCR     0x7A    /* delay line calibration                    */
+#define SDRAM_CLKTR    0x80    /* DDR clock timing                          */
+#define SDRAM_WRDTR    0x81    /* write data, DQS, DM clock, timing         */
+#define SDRAM_SDTR1    0x85    /* DDR SDRAM timing 1                        */
+#define SDRAM_SDTR2    0x86    /* DDR SDRAM timing 2                        */
+#define SDRAM_SDTR3    0x87    /* DDR SDRAM timing 3                        */
+#define SDRAM_MMODE    0x88    /* memory mode                               */
+#define SDRAM_MEMODE   0x89    /* memory extended mode                      */
+#define SDRAM_ECCCR    0x98    /* ECC error status                          */
+#define SDRAM_CID      0xA4    /* core ID                                   */
+#define SDRAM_RID      0xA8    /* revision ID                               */
+
+/*-----------------------------------------------------------------------------+
+|  Memory Controller Status
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCSTAT_MIC_MASK          0x80000000      /* Memory init status mask      */
+#define SDRAM_MCSTAT_MIC_NOTCOMP       0x00000000      /* Mem init not complete        */
+#define SDRAM_MCSTAT_MIC_COMP          0x80000000      /* Mem init complete            */
+#define SDRAM_MCSTAT_SRMS_MASK         0x80000000      /* Mem self refresh stat mask   */
+#define SDRAM_MCSTAT_SRMS_NOT_SF       0x00000000      /* Mem not in self refresh      */
+#define SDRAM_MCSTAT_SRMS_SF           0x80000000      /* Mem in self refresh          */
+
+/*-----------------------------------------------------------------------------+
+|  Memory Controller Options 1
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCOPT1_MCHK_MASK         0x30000000 /* Memory data err check mask*/
+#define SDRAM_MCOPT1_MCHK_NON          0x00000000 /* No ECC generation         */
+#define SDRAM_MCOPT1_MCHK_GEN          0x20000000 /* ECC generation            */
+#define SDRAM_MCOPT1_MCHK_CHK          0x10000000 /* ECC generation and check  */
+#define SDRAM_MCOPT1_MCHK_CHK_REP      0x30000000 /* ECC generation, chk, report*/
+#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n)        ((((unsigned long)(n))>>28)&0x3)
+#define SDRAM_MCOPT1_RDEN_MASK         0x08000000 /* Registered DIMM mask      */
+#define SDRAM_MCOPT1_RDEN              0x08000000 /* Registered DIMM enable    */
+#define SDRAM_MCOPT1_PMU_MASK          0x06000000 /* Page management unit mask */
+#define SDRAM_MCOPT1_PMU_CLOSE         0x00000000 /* PMU Close                 */
+#define SDRAM_MCOPT1_PMU_OPEN          0x04000000 /* PMU Open                  */
+#define SDRAM_MCOPT1_PMU_AUTOCLOSE     0x02000000 /* PMU AutoClose             */
+#define SDRAM_MCOPT1_DMWD_MASK         0x01000000 /* DRAM width mask           */
+#define SDRAM_MCOPT1_DMWD_32           0x00000000 /* 32 bits                   */
+#define SDRAM_MCOPT1_DMWD_64           0x01000000 /* 64 bits                   */
+#define SDRAM_MCOPT1_UIOS_MASK         0x00C00000 /* Unused IO State           */
+#define SDRAM_MCOPT1_BCNT_MASK         0x00200000 /* Bank count                */
+#define SDRAM_MCOPT1_4_BANKS           0x00000000 /* 4 Banks                   */
+#define SDRAM_MCOPT1_8_BANKS           0x00200000 /* 8 Banks                   */
+#define SDRAM_MCOPT1_DDR_TYPE_MASK     0x00100000 /* DDR Memory Type mask      */
+#define SDRAM_MCOPT1_DDR1_TYPE         0x00000000 /* DDR1 Memory Type          */
+#define SDRAM_MCOPT1_DDR2_TYPE         0x00100000 /* DDR2 Memory Type          */
+#define SDRAM_MCOPT1_QDEP              0x00020000 /* 4 commands deep           */
+#define SDRAM_MCOPT1_RWOO_MASK         0x00008000 /* Out of Order Read mask    */
+#define SDRAM_MCOPT1_RWOO_DISABLED     0x00000000 /* disabled                  */
+#define SDRAM_MCOPT1_RWOO_ENABLED      0x00008000 /* enabled                   */
+#define SDRAM_MCOPT1_WOOO_MASK         0x00004000 /* Out of Order Write mask   */
+#define SDRAM_MCOPT1_WOOO_DISABLED     0x00000000 /* disabled                  */
+#define SDRAM_MCOPT1_WOOO_ENABLED      0x00004000 /* enabled                   */
+#define SDRAM_MCOPT1_DCOO_MASK         0x00002000 /* All Out of Order mask     */
+#define SDRAM_MCOPT1_DCOO_DISABLED     0x00002000 /* disabled                  */
+#define SDRAM_MCOPT1_DCOO_ENABLED      0x00000000 /* enabled                   */
+#define SDRAM_MCOPT1_DREF_MASK         0x00001000 /* Deferred refresh mask     */
+#define SDRAM_MCOPT1_DREF_NORMAL       0x00000000 /* normal refresh            */
+#define SDRAM_MCOPT1_DREF_DEFER_4      0x00001000 /* defer up to 4 refresh cmd */
+
+/*-----------------------------------------------------------------------------+
+|  Memory Controller Options 2
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCOPT2_SREN_MASK         0x80000000 /* Self Test mask            */
+#define SDRAM_MCOPT2_SREN_EXIT         0x00000000 /* Self Test exit            */
+#define SDRAM_MCOPT2_SREN_ENTER                0x80000000 /* Self Test enter           */
+#define SDRAM_MCOPT2_PMEN_MASK         0x40000000 /* Power Management mask     */
+#define SDRAM_MCOPT2_PMEN_DISABLE      0x00000000 /* disable                   */
+#define SDRAM_MCOPT2_PMEN_ENABLE       0x40000000 /* enable                    */
+#define SDRAM_MCOPT2_IPTR_MASK         0x20000000 /* Init Trigger Reg mask     */
+#define SDRAM_MCOPT2_IPTR_IDLE         0x00000000 /* idle                      */
+#define SDRAM_MCOPT2_IPTR_EXECUTE      0x20000000 /* execute preloaded init    */
+#define SDRAM_MCOPT2_XSRP_MASK         0x10000000 /* Exit Self Refresh Prevent */
+#define SDRAM_MCOPT2_XSRP_ALLOW                0x00000000 /* allow self refresh exit   */
+#define SDRAM_MCOPT2_XSRP_PREVENT      0x10000000 /* prevent self refresh exit */
+#define SDRAM_MCOPT2_DCEN_MASK         0x08000000 /* SDRAM Controller Enable   */
+#define SDRAM_MCOPT2_DCEN_DISABLE      0x00000000 /* SDRAM Controller Enable   */
+#define SDRAM_MCOPT2_DCEN_ENABLE       0x08000000 /* SDRAM Controller Enable   */
+#define SDRAM_MCOPT2_ISIE_MASK         0x04000000 /* Init Seq Interruptable mas*/
+#define SDRAM_MCOPT2_ISIE_DISABLE      0x00000000 /* disable                   */
+#define SDRAM_MCOPT2_ISIE_ENABLE       0x04000000 /* enable                    */
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Refresh Timer Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RTR_RINT_MASK            0xFFF80000
+#define SDRAM_RTR_RINT_ENCODE(n)       ((((unsigned long)(n))&0xFFF8)<<16)
+#define SDRAM_RTR_RINT_DECODE(n)       ((((unsigned long)(n))>>16)&0xFFF8)
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Read DQS Delay Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RQDC_RQDE_MASK           0x80000000
+#define SDRAM_RQDC_RQDE_DISABLE                0x00000000
+#define SDRAM_RQDC_RQDE_ENABLE         0x80000000
+#define SDRAM_RQDC_RQFD_MASK           0x000001FF
+#define SDRAM_RQDC_RQFD_ENCODE(n)      ((((unsigned long)(n))&0x1FF)<<0)
+
+#define SDRAM_RQDC_RQFD_MAX            0x1FF
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Read Data Capture Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RDCC_RDSS_MASK           0xC0000000
+#define SDRAM_RDCC_RDSS_T1             0x00000000
+#define SDRAM_RDCC_RDSS_T2             0x40000000
+#define SDRAM_RDCC_RDSS_T3             0x80000000
+#define SDRAM_RDCC_RDSS_T4             0xC0000000
+#define SDRAM_RDCC_RSAE_MASK           0x00000001
+#define SDRAM_RDCC_RSAE_DISABLE                0x00000001
+#define SDRAM_RDCC_RSAE_ENABLE         0x00000000
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Read Feedback Delay Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RFDC_ARSE_MASK           0x80000000
+#define SDRAM_RFDC_ARSE_DISABLE                0x80000000
+#define SDRAM_RFDC_ARSE_ENABLE         0x00000000
+#define SDRAM_RFDC_RFOS_MASK           0x007F0000
+#define SDRAM_RFDC_RFOS_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK           0x000003FF
+#define SDRAM_RFDC_RFFD_ENCODE(n)      ((((unsigned long)(n))&0x3FF)<<0)
+
+#define SDRAM_RFDC_RFFD_MAX            0x7FF
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Delay Line Calibration Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_DLCR_DCLM_MASK           0x80000000
+#define SDRAM_DLCR_DCLM_MANUEL         0x80000000
+#define SDRAM_DLCR_DCLM_AUTO           0x00000000
+#define SDRAM_DLCR_DLCR_MASK           0x08000000
+#define SDRAM_DLCR_DLCR_CALIBRATE      0x08000000
+#define SDRAM_DLCR_DLCR_IDLE           0x00000000
+#define SDRAM_DLCR_DLCS_MASK           0x07000000
+#define SDRAM_DLCR_DLCS_NOT_RUN                0x00000000
+#define SDRAM_DLCR_DLCS_IN_PROGRESS    0x01000000
+#define SDRAM_DLCR_DLCS_COMPLETE       0x02000000
+#define SDRAM_DLCR_DLCS_CONT_DONE      0x03000000
+#define SDRAM_DLCR_DLCS_ERROR          0x04000000
+#define SDRAM_DLCR_DLCV_MASK           0x000001FF
+#define SDRAM_DLCR_DLCV_ENCODE(n)      ((((unsigned long)(n))&0x1FF)<<0)
+#define SDRAM_DLCR_DLCV_DECODE(n)      ((((unsigned long)(n))>>0)&0x1FF)
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Controller On Die Termination Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_CODT_ODT_ON                      0x80000000
+#define SDRAM_CODT_ODT_OFF                     0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK                0x00000020
+#define SDRAM_CODT_DQS_2_5_V_DDR1              0x00000000
+#define SDRAM_CODT_DQS_1_8_V_DDR2              0x00000020
+#define SDRAM_CODT_DQS_MASK                    0x00000010
+#define SDRAM_CODT_DQS_DIFFERENTIAL            0x00000000
+#define SDRAM_CODT_DQS_SINGLE_END              0x00000010
+#define SDRAM_CODT_CKSE_DIFFERENTIAL           0x00000000
+#define SDRAM_CODT_CKSE_SINGLE_END             0x00000008
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END     0x00000004
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END     0x00000002
+#define SDRAM_CODT_IO_HIZ                      0x00000000
+#define SDRAM_CODT_IO_NMODE                    0x00000001
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Mode Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_MMODE_WR_MASK            0x00000E00
+#define SDRAM_MMODE_WR_DDR1            0x00000000
+#define SDRAM_MMODE_WR_DDR2_3_CYC      0x00000400
+#define SDRAM_MMODE_WR_DDR2_4_CYC      0x00000600
+#define SDRAM_MMODE_WR_DDR2_5_CYC      0x00000800
+#define SDRAM_MMODE_WR_DDR2_6_CYC      0x00000A00
+#define SDRAM_MMODE_DCL_MASK           0x00000070
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK   0x00000020
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK   0x00000060
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK   0x00000030
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK   0x00000020
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK   0x00000030
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK   0x00000040
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK   0x00000050
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK   0x00000060
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK   0x00000070
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Extended Mode Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_MEMODE_DIC_MASK          0x00000002
+#define SDRAM_MEMODE_DIC_NORMAL                0x00000000
+#define SDRAM_MEMODE_DIC_WEAK          0x00000002
+#define SDRAM_MEMODE_DLL_MASK          0x00000001
+#define SDRAM_MEMODE_DLL_DISABLE       0x00000001
+#define SDRAM_MEMODE_DLL_ENABLE                0x00000000
+#define SDRAM_MEMODE_RTT_MASK          0x00000044
+#define SDRAM_MEMODE_RTT_DISABLED      0x00000000
+#define SDRAM_MEMODE_RTT_75OHM         0x00000004
+#define SDRAM_MEMODE_RTT_150OHM                0x00000040
+#define SDRAM_MEMODE_DQS_MASK          0x00000400
+#define SDRAM_MEMODE_DQS_DISABLE       0x00000400
+#define SDRAM_MEMODE_DQS_ENABLE                0x00000000
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Clock Timing Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_CLKTR_CLKP_MASK          0xC0000000
+#define SDRAM_CLKTR_CLKP_0_DEG         0x00000000
+#define SDRAM_CLKTR_CLKP_180_DEG_ADV   0x80000000
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM Write Timing Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_WRDTR_LLWP_MASK          0x10000000
+#define SDRAM_WRDTR_LLWP_DIS           0x10000000
+#define SDRAM_WRDTR_LLWP_1_CYC         0x00000000
+#define SDRAM_WRDTR_WTR_MASK           0x0E000000
+#define SDRAM_WRDTR_WTR_0_DEG          0x06000000
+#define SDRAM_WRDTR_WTR_180_DEG_ADV    0x02000000
+#define SDRAM_WRDTR_WTR_270_DEG_ADV    0x00000000
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM SDTR1 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR1_LDOF_MASK          0x80000000
+#define SDRAM_SDTR1_LDOF_1_CLK         0x00000000
+#define SDRAM_SDTR1_LDOF_2_CLK         0x80000000
+#define SDRAM_SDTR1_RTW_MASK           0x00F00000
+#define SDRAM_SDTR1_RTW_2_CLK          0x00200000
+#define SDRAM_SDTR1_RTW_3_CLK          0x00300000
+#define SDRAM_SDTR1_WTWO_MASK          0x000F0000
+#define SDRAM_SDTR1_WTWO_0_CLK         0x00000000
+#define SDRAM_SDTR1_WTWO_1_CLK         0x00010000
+#define SDRAM_SDTR1_RTRO_MASK          0x0000F000
+#define SDRAM_SDTR1_RTRO_1_CLK         0x00001000
+#define SDRAM_SDTR1_RTRO_2_CLK         0x00002000
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM SDTR2 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR2_RCD_MASK           0xF0000000
+#define SDRAM_SDTR2_RCD_1_CLK          0x10000000
+#define SDRAM_SDTR2_RCD_2_CLK          0x20000000
+#define SDRAM_SDTR2_RCD_3_CLK          0x30000000
+#define SDRAM_SDTR2_RCD_4_CLK          0x40000000
+#define SDRAM_SDTR2_RCD_5_CLK          0x50000000
+#define SDRAM_SDTR2_WTR_MASK           0x0F000000
+#define SDRAM_SDTR2_WTR_1_CLK          0x01000000
+#define SDRAM_SDTR2_WTR_2_CLK          0x02000000
+#define SDRAM_SDTR2_WTR_3_CLK          0x03000000
+#define SDRAM_SDTR2_WTR_4_CLK          0x04000000
+#define SDRAM_SDTR3_WTR_ENCODE(n)      ((((unsigned long)(n))&0xF)<<24)
+#define SDRAM_SDTR2_XSNR_MASK          0x00FF0000
+#define SDRAM_SDTR2_XSNR_8_CLK         0x00080000
+#define SDRAM_SDTR2_XSNR_16_CLK                0x00100000
+#define SDRAM_SDTR2_XSNR_32_CLK                0x00200000
+#define SDRAM_SDTR2_XSNR_64_CLK                0x00400000
+#define SDRAM_SDTR2_WPC_MASK           0x0000F000
+#define SDRAM_SDTR2_WPC_2_CLK          0x00002000
+#define SDRAM_SDTR2_WPC_3_CLK          0x00003000
+#define SDRAM_SDTR2_WPC_4_CLK          0x00004000
+#define SDRAM_SDTR2_WPC_5_CLK          0x00005000
+#define SDRAM_SDTR2_WPC_6_CLK          0x00006000
+#define SDRAM_SDTR3_WPC_ENCODE(n)      ((((unsigned long)(n))&0xF)<<12)
+#define SDRAM_SDTR2_RPC_MASK           0x00000F00
+#define SDRAM_SDTR2_RPC_2_CLK          0x00000200
+#define SDRAM_SDTR2_RPC_3_CLK          0x00000300
+#define SDRAM_SDTR2_RPC_4_CLK          0x00000400
+#define SDRAM_SDTR2_RP_MASK            0x000000F0
+#define SDRAM_SDTR2_RP_3_CLK           0x00000030
+#define SDRAM_SDTR2_RP_4_CLK           0x00000040
+#define SDRAM_SDTR2_RP_5_CLK           0x00000050
+#define SDRAM_SDTR2_RP_6_CLK           0x00000060
+#define SDRAM_SDTR2_RP_7_CLK           0x00000070
+#define SDRAM_SDTR2_RRD_MASK           0x0000000F
+#define SDRAM_SDTR2_RRD_2_CLK          0x00000002
+#define SDRAM_SDTR2_RRD_3_CLK          0x00000003
+
+/*-----------------------------------------------------------------------------+
+|  SDRAM SDTR3 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR3_RAS_MASK           0x1F000000
+#define SDRAM_SDTR3_RAS_ENCODE(n)      ((((unsigned long)(n))&0x1F)<<24)
+#define SDRAM_SDTR3_RC_MASK            0x001F0000
+#define SDRAM_SDTR3_RC_ENCODE(n)       ((((unsigned long)(n))&0x1F)<<16)
+#define SDRAM_SDTR3_XCS_MASK           0x00001F00
+#define SDRAM_SDTR3_XCS                        0x00000D00
+#define SDRAM_SDTR3_RFC_MASK           0x0000003F
+#define SDRAM_SDTR3_RFC_ENCODE(n)      ((((unsigned long)(n))&0x3F)<<0)
+
+/*-----------------------------------------------------------------------------+
+|  Memory Bank 0-1 configuration
++-----------------------------------------------------------------------------*/
+#define SDRAM_BXCF_M_AM_MASK           0x00000F00      /* Addressing mode      */
+#define SDRAM_BXCF_M_AM_0              0x00000000      /*   Mode 0             */
+#define SDRAM_BXCF_M_AM_1              0x00000100      /*   Mode 1             */
+#define SDRAM_BXCF_M_AM_2              0x00000200      /*   Mode 2             */
+#define SDRAM_BXCF_M_AM_3              0x00000300      /*   Mode 3             */
+#define SDRAM_BXCF_M_AM_4              0x00000400      /*   Mode 4             */
+#define SDRAM_BXCF_M_AM_5              0x00000500      /*   Mode 5             */
+#define SDRAM_BXCF_M_AM_6              0x00000600      /*   Mode 6             */
+#define SDRAM_BXCF_M_AM_7              0x00000700      /*   Mode 7             */
+#define SDRAM_BXCF_M_AM_8              0x00000800      /*   Mode 8             */
+#define SDRAM_BXCF_M_AM_9              0x00000900      /*   Mode 9             */
+#define SDRAM_BXCF_M_BE_MASK           0x00000001      /* Memory Bank Enable   */
+#define SDRAM_BXCF_M_BE_DISABLE                0x00000000      /* Memory Bank Enable   */
+#define SDRAM_BXCF_M_BE_ENABLE         0x00000001      /* Memory Bank Enable   */
+#endif /* CONFIG_440SPE */
+
+#ifndef CONFIG_440_GX
+#endif /* not CONFIG_440SPE       */
+
 /*-----------------------------------------------------------------------------
  | External Bus Controller
  +----------------------------------------------------------------------------*/
 /*-----------------------------------------------------------------------------
  | L2 Cache
  +----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define L2_CACHE_BASE  0x030
 #define l2_cache_cfg   (L2_CACHE_BASE+0x00)    /* L2 Cache Config      */
 #define l2_cache_cmd   (L2_CACHE_BASE+0x01)    /* L2 Cache Command     */
  | Clocking, Power Management and Chip Control
  +----------------------------------------------------------------------------*/
 #define CNTRL_DCR_BASE 0x0b0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define cpc0_er                (CNTRL_DCR_BASE+0x00)   /* CPM enable register          */
 #define cpc0_fr                (CNTRL_DCR_BASE+0x01)   /* CPM force register           */
 #define cpc0_sr                (CNTRL_DCR_BASE+0x02)   /* CPM status register          */
 #define uic1vr (UIC1_DCR_BASE+0x7)   /* UIC1 vector                       */
 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration        */
 
+#if defined(CONFIG_440SPE)
+#define UIC2_DCR_BASE 0xe0
+#define uic2sr (UIC0_DCR_BASE+0x0)   /* UIC2 status-Read Clear         */
+#define uic2srs        (UIC0_DCR_BASE+0x1)   /* UIC2 status-Read Set */
+#define uic2er (UIC0_DCR_BASE+0x2)   /* UIC2 enable                    */
+#define uic2cr (UIC0_DCR_BASE+0x3)   /* UIC2 critical                  */
+#define uic2pr (UIC0_DCR_BASE+0x4)   /* UIC2 polarity                  */
+#define uic2tr (UIC0_DCR_BASE+0x5)   /* UIC2 triggering                */
+#define uic2msr (UIC0_DCR_BASE+0x6)   /* UIC2 masked status            */
+#define uic2vr (UIC0_DCR_BASE+0x7)   /* UIC2 vector                    */
+#define uic2vcr (UIC0_DCR_BASE+0x8)   /* UIC2 vector configuration     */
+
+#define UIC3_DCR_BASE 0xf0
+#define uic3sr (UIC1_DCR_BASE+0x0)   /* UIC3 status-Read Clear         */
+#define uic3srs        (UIC0_DCR_BASE+0x1)   /* UIC3 status-Read Set */
+#define uic3er (UIC1_DCR_BASE+0x2)   /* UIC3 enable                    */
+#define uic3cr (UIC1_DCR_BASE+0x3)   /* UIC3 critical                  */
+#define uic3pr (UIC1_DCR_BASE+0x4)   /* UIC3 polarity                  */
+#define uic3tr (UIC1_DCR_BASE+0x5)   /* UIC3 triggering                */
+#define uic3msr (UIC1_DCR_BASE+0x6)   /* UIC3 masked status            */
+#define uic3vr (UIC1_DCR_BASE+0x7)   /* UIC3 vector                    */
+#define uic3vcr (UIC1_DCR_BASE+0x8)   /* UIC3 vector configuration     */
+#endif /* CONFIG_440SPE */
+
 #if defined(CONFIG_440GX)
 #define UIC2_DCR_BASE 0x210
 #define uic2sr (UIC2_DCR_BASE+0x0)   /* UIC2 status                       */
 #define uicvr  uic0vr
 #define uicvcr uic0vcr
 
+#if defined(CONFIG_440SPE)
+/*----------------------------------------------------------------------------+
+| Clock / Power-on-reset DCR's.
++----------------------------------------------------------------------------*/
+#define CPR0_CFGADDR                   0x00C
+#define CPR0_CFGDATA                   0x00D
+
+#define CPR0_CLKUPD                    0x20
+#define CPR0_CLKUPD_BSY_MASK           0x80000000
+#define CPR0_CLKUPD_BSY_COMPLETED      0x00000000
+#define CPR0_CLKUPD_BSY_BUSY           0x80000000
+#define CPR0_CLKUPD_CUI_MASK           0x80000000
+#define CPR0_CLKUPD_CUI_DISABLE                0x00000000
+#define CPR0_CLKUPD_CUI_ENABLE         0x80000000
+#define CPR0_CLKUPD_CUD_MASK           0x40000000
+#define CPR0_CLKUPD_CUD_DISABLE                0x00000000
+#define CPR0_CLKUPD_CUD_ENABLE         0x40000000
+
+#define CPR0_PLLC                      0x40
+#define CPR0_PLLC_RST_MASK             0x80000000
+#define CPR0_PLLC_RST_PLLLOCKED                0x00000000
+#define CPR0_PLLC_RST_PLLRESET         0x80000000
+#define CPR0_PLLC_ENG_MASK             0x40000000
+#define CPR0_PLLC_ENG_DISABLE          0x00000000
+#define CPR0_PLLC_ENG_ENABLE           0x40000000
+#define CPR0_PLLC_ENG_ENCODE(n)                ((((unsigned long)(n))&0x01)<<30)
+#define CPR0_PLLC_ENG_DECODE(n)                ((((unsigned long)(n))>>30)&0x01)
+#define CPR0_PLLC_SRC_MASK             0x20000000
+#define CPR0_PLLC_SRC_PLLOUTA          0x00000000
+#define CPR0_PLLC_SRC_PLLOUTB          0x20000000
+#define CPR0_PLLC_SRC_ENCODE(n)                ((((unsigned long)(n))&0x01)<<29)
+#define CPR0_PLLC_SRC_DECODE(n)                ((((unsigned long)(n))>>29)&0x01)
+#define CPR0_PLLC_SEL_MASK             0x07000000
+#define CPR0_PLLC_SEL_PLLOUT           0x00000000
+#define CPR0_PLLC_SEL_CPU              0x01000000
+#define CPR0_PLLC_SEL_EBC              0x05000000
+#define CPR0_PLLC_SEL_ENCODE(n)                ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PLLC_SEL_DECODE(n)                ((((unsigned long)(n))>>24)&0x07)
+#define CPR0_PLLC_TUNE_MASK            0x000003FF
+#define CPR0_PLLC_TUNE_ENCODE(n)       ((((unsigned long)(n))&0x3FF)<<0)
+#define CPR0_PLLC_TUNE_DECODE(n)       ((((unsigned long)(n))>>0)&0x3FF)
+
+#define CPR0_PLLD                      0x60
+#define CPR0_PLLD_FBDV_MASK            0x1F000000
+#define CPR0_PLLD_FBDV_ENCODE(n)       ((((unsigned long)(n))&0x1F)<<24)
+#define CPR0_PLLD_FBDV_DECODE(n)       ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+#define CPR0_PLLD_FWDVA_MASK           0x000F0000
+#define CPR0_PLLD_FWDVA_ENCODE(n)      ((((unsigned long)(n))&0x0F)<<16)
+#define CPR0_PLLD_FWDVA_DECODE(n)      ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+#define CPR0_PLLD_FWDVB_MASK           0x00000700
+#define CPR0_PLLD_FWDVB_ENCODE(n)      ((((unsigned long)(n))&0x07)<<8)
+#define CPR0_PLLD_FWDVB_DECODE(n)      ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+#define CPR0_PLLD_LFBDV_MASK           0x0000003F
+#define CPR0_PLLD_LFBDV_ENCODE(n)      ((((unsigned long)(n))&0x3F)<<0)
+#define CPR0_PLLD_LFBDV_DECODE(n)      ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+
+#define CPR0_PRIMAD                    0x80
+#define CPR0_PRIMAD_PRADV0_MASK                0x07000000
+#define CPR0_PRIMAD_PRADV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PRIMAD_PRADV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+
+#define CPR0_PRIMBD                    0xA0
+#define CPR0_PRIMBD_PRBDV0_MASK                0x07000000
+#define CPR0_PRIMBD_PRBDV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PRIMBD_PRBDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+
+#define CPR0_OPBD                      0xC0
+#define CPR0_OPBD_OPBDV0_MASK          0x03000000
+#define CPR0_OPBD_OPBDV0_ENCODE(n)     ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_OPBD_OPBDV0_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+#define CPR0_PERD                      0xE0
+#define CPR0_PERD_PERDV0_MASK          0x03000000
+#define CPR0_PERD_PERDV0_ENCODE(n)     ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_PERD_PERDV0_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+#define CPR0_MALD                      0x100
+#define CPR0_MALD_MALDV0_MASK          0x03000000
+#define CPR0_MALD_MALDV0_ENCODE(n)     ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_MALD_MALDV0_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+#define CPR0_ICFG                      0x140
+#define CPR0_ICFG_RLI_MASK             0x80000000
+#define CPR0_ICFG_RLI_RESETCPR         0x00000000
+#define CPR0_ICFG_RLI_PRESERVECPR      0x80000000
+#define CPR0_ICFG_ICS_MASK             0x00000007
+#define CPR0_ICFG_ICS_ENCODE(n)                ((((unsigned long)(n))&0x3F)<<0)
+#define CPR0_ICFG_ICS_DECODE(n)                ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+
+/************************/
+/* IIC defines          */
+/************************/
+#define IIC0_MMIO_BASE 0xA0000400
+#define IIC1_MMIO_BASE 0xA0000500
+
+#endif /* CONFIG_440SP */
+
 /*-----------------------------------------------------------------------------
  | DMA
  +----------------------------------------------------------------------------*/
 #define UIC_GPTCT      0x00000004      /* GPT count timer                  */
 #define UIC_UIC1NC     0x00000002      /* UIC1 non-critical interrupt      */
 #define UIC_UIC1C      0x00000001      /* UIC1 critical interrupt          */
-#else  /* CONFIG_440SP */
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
 #define UIC_U0         0x80000000      /* UART 0                           */
 #define UIC_U1         0x40000000      /* UART 1                           */
 #define UIC_IIC0       0x20000000      /* IIC                              */
 #define UIC_EIR6       0x00000004      /* External interrupt 6             */
 #define UIC_UIC1NC     0x00000002      /* UIC1 non-critical interrupt      */
 #define UIC_UIC1C      0x00000001      /* UIC1 critical interrupt          */
-#endif /* CONFIG_440SP */
+#elif !defined(CONFIG_440SPE)
+#define UIC_U0         0x80000000      /* UART 0                           */
+#define UIC_U1         0x40000000      /* UART 1                           */
+#define UIC_IIC0       0x20000000      /* IIC                              */
+#define UIC_IIC1       0x10000000      /* IIC                              */
+#define UIC_PIM                0x08000000      /* PCI inbound message              */
+#define UIC_PCRW       0x04000000      /* PCI command register write       */
+#define UIC_PPM                0x02000000      /* PCI power management             */
+#define UIC_MSI0       0x01000000      /* PCI MSI level 0                  */
+#define UIC_MSI1       0x00800000      /* PCI MSI level 1                  */
+#define UIC_MSI2       0x00400000      /* PCI MSI level 2                  */
+#define UIC_MTE                0x00200000      /* MAL TXEOB                        */
+#define UIC_MRE                0x00100000      /* MAL RXEOB                        */
+#define UIC_D0         0x00080000      /* DMA channel 0                    */
+#define UIC_D1         0x00040000      /* DMA channel 1                    */
+#define UIC_D2         0x00020000      /* DMA channel 2                    */
+#define UIC_D3         0x00010000      /* DMA channel 3                    */
+#define UIC_RSVD0      0x00008000      /* Reserved                         */
+#define UIC_RSVD1      0x00004000      /* Reserved                         */
+#define UIC_CT0                0x00002000      /* GPT compare timer 0              */
+#define UIC_CT1                0x00001000      /* GPT compare timer 1              */
+#define UIC_CT2                0x00000800      /* GPT compare timer 2              */
+#define UIC_CT3                0x00000400      /* GPT compare timer 3              */
+#define UIC_CT4                0x00000200      /* GPT compare timer 4              */
+#define UIC_EIR0       0x00000100      /* External interrupt 0             */
+#define UIC_EIR1       0x00000080      /* External interrupt 1             */
+#define UIC_EIR2       0x00000040      /* External interrupt 2             */
+#define UIC_EIR3       0x00000020      /* External interrupt 3             */
+#define UIC_EIR4       0x00000010      /* External interrupt 4             */
+#define UIC_EIR5       0x00000008      /* External interrupt 5             */
+#define UIC_EIR6       0x00000004      /* External interrupt 6             */
+#define UIC_UIC1NC     0x00000002      /* UIC1 non-critical interrupt      */
+#define UIC_UIC1C      0x00000001      /* UIC1 critical interrupt          */
+#endif /* CONFIG_440GX */
 
 /* For compatibility with 405 code */
 #define UIC_MAL_TXEOB  UIC_MTE
 #define UIC_EWU0       0x00000004      /* Ethernet 0 wakeup                */
 #define UIC_ETH1       0x00000002      /* Reserved                         */
 #define UIC_XOR                0x00000001      /* XOR                              */
-#else /* CONFIG_440SP */
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
+#define UIC_MS         0x80000000      /* MAL SERR                         */
+#define UIC_MTDE       0x40000000      /* MAL TXDE                         */
+#define UIC_MRDE       0x20000000      /* MAL RXDE                         */
+#define UIC_DEUE       0x10000000      /* DDR SDRAM ECC uncorrectible error*/
+#define UIC_DECE       0x08000000      /* DDR SDRAM correctible error      */
+#define UIC_EBCO       0x04000000      /* EBCO interrupt status            */
+#define UIC_EBMI       0x02000000      /* EBMI interrupt status            */
+#define UIC_OPB                0x01000000      /* OPB to PLB bridge interrupt stat */
+#define UIC_MSI3       0x00800000      /* PCI MSI level 3                  */
+#define UIC_MSI4       0x00400000      /* PCI MSI level 4                  */
+#define UIC_MSI5       0x00200000      /* PCI MSI level 5                  */
+#define UIC_MSI6       0x00100000      /* PCI MSI level 6                  */
+#define UIC_MSI7       0x00080000      /* PCI MSI level 7                  */
+#define UIC_MSI8       0x00040000      /* PCI MSI level 8                  */
+#define UIC_MSI9       0x00020000      /* PCI MSI level 9                  */
+#define UIC_MSI10      0x00010000      /* PCI MSI level 10                 */
+#define UIC_MSI11      0x00008000      /* PCI MSI level 11                 */
+#define UIC_PPMI       0x00004000      /* PPM interrupt status             */
+#define UIC_EIR7       0x00002000      /* External interrupt 7             */
+#define UIC_EIR8       0x00001000      /* External interrupt 8             */
+#define UIC_EIR9       0x00000800      /* External interrupt 9             */
+#define UIC_EIR10      0x00000400      /* External interrupt 10            */
+#define UIC_EIR11      0x00000200      /* External interrupt 11            */
+#define UIC_EIR12      0x00000100      /* External interrupt 12            */
+#define UIC_SRE                0x00000080      /* Serial ROM error                 */
+#define UIC_RSVD2      0x00000040      /* Reserved                         */
+#define UIC_RSVD3      0x00000020      /* Reserved                         */
+#define UIC_PAE                0x00000010      /* PCI asynchronous error           */
+#define UIC_ETH0       0x00000008      /* Ethernet 0                       */
+#define UIC_EWU0       0x00000004      /* Ethernet 0 wakeup                */
+#define UIC_ETH1       0x00000002      /* Ethernet 1                       */
+#define UIC_EWU1       0x00000001      /* Ethernet 1 wakeup                */
+#elif !defined(CONFIG_440SPE)
 #define UIC_MS         0x80000000      /* MAL SERR                         */
 #define UIC_MTDE       0x40000000      /* MAL TXDE                         */
 #define UIC_MRDE       0x20000000      /* MAL RXDE                         */
 
 #define UICB0_ALL              (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
                                                 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
-#endif /* CONFIG_440GX */
+#endif /* CONFIG_440_GX */
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller interrupts
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SPE)
+/*#define UICB0_UIC0CI 0x80000000*/    /* UIC0 Critical Interrupt          */
+/*#define UICB0_UIC0NCI        0x40000000*/    /* UIC0 Noncritical Interrupt       */
+#define UICB0_UIC1CI   0x00000002      /* UIC1 Critical Interrupt          */
+#define UICB0_UIC1NCI  0x00000001      /* UIC1 Noncritical Interrupt       */
+#define UICB0_UIC2CI   0x00200000      /* UIC2 Critical Interrupt          */
+#define UICB0_UIC2NCI  0x00100000      /* UIC2 Noncritical Interrupt       */
+#define UICB0_UIC3CI   0x00008000      /* UIC3 Critical Interrupt          */
+#define UICB0_UIC3NCI  0x00004000      /* UIC3 Noncritical Interrupt       */
+
+#define UICB0_ALL              (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
+                                                UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 0 interrupts (UIC0)
++---------------------------------------------------------------------------*/
+#define UIC_U0         0x80000000      /* UART 0                           */
+#define UIC_U1         0x40000000      /* UART 1                           */
+#define UIC_IIC0       0x20000000      /* IIC                              */
+#define UIC_IIC1       0x10000000      /* IIC                              */
+#define UIC_PIM                0x08000000      /* PCI inbound message              */
+#define UIC_PCRW       0x04000000      /* PCI command register write       */
+#define UIC_PPM                0x02000000      /* PCI power management             */
+#define UIC_PVPDA      0x01000000      /* PCIx 0 vpd access                */
+#define UIC_MSI0       0x00800000      /* PCIx MSI level 0                 */
+#define UIC_EIR15      0x00400000      /* External intp 15                 */
+#define UIC_PEMSI0     0x00080000      /* PCIe MSI level 0                 */
+#define UIC_PEMSI1     0x00040000      /* PCIe MSI level 1                 */
+#define UIC_PEMSI2     0x00020000      /* PCIe MSI level 2                 */
+#define UIC_PEMSI3     0x00010000      /* PCIe MSI level 3                 */
+#define UIC_EIR14      0x00002000      /* External interrupt 14            */
+#define UIC_D0CPFF     0x00001000      /* DMA0 cp fifo full                */
+#define UIC_D0CSNS     0x00000800      /* DMA0 cs fifo needs service       */
+#define UIC_D1CPFF     0x00000400      /* DMA1 cp fifo full                */
+#define UIC_D1CSNS     0x00000200      /* DMA1 cs fifo needs service       */
+#define UIC_I2OID      0x00000100      /* I2O inbound door bell            */
+#define UIC_I2OLNE     0x00000080      /* I2O Inbound Post List FIFO Not Empty */
+#define UIC_I20R0LL    0x00000040      /* I2O Region 0 Low Latency PLB Write */
+#define UIC_I2OR1LL    0x00000020      /* I2O Region 1 Low Latency PLB Write */
+#define UIC_I20R0HB    0x00000010      /* I2O Region 0 High Bandwidth PLB Write */
+#define UIC_I2OR1HB    0x00000008      /* I2O Region 1 High Bandwidth PLB Write */
+#define UIC_CPTCNT     0x00000004      /* GPT Count Timer                  */
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 1 interrupts (UIC1)
++---------------------------------------------------------------------------*/
+#define UIC_EIR13      0x80000000      /* externei intp 13                 */
+#define UIC_MS         0x40000000      /* MAL SERR                         */
+#define UIC_MTDE       0x20000000      /* MAL TXDE                         */
+#define UIC_MRDE       0x10000000      /* MAL RXDE                         */
+#define UIC_DEUE       0x08000000      /* DDR SDRAM ECC correct/uncorrectable error */
+#define UIC_EBCO       0x04000000      /* EBCO interrupt status            */
+#define UIC_MTE                0x02000000      /* MAL TXEOB                        */
+#define UIC_MRE                0x01000000      /* MAL RXEOB                        */
+#define UIC_MSI1       0x00800000      /* PCI MSI level 1                  */
+#define UIC_MSI2       0x00400000      /* PCI MSI level 2                  */
+#define UIC_MSI3       0x00200000      /* PCI MSI level 3                  */
+#define UIC_L2C                0x00100000      /* L2 cache                         */
+#define UIC_CT0                0x00080000      /* GPT compare timer 0              */
+#define UIC_CT1                0x00040000      /* GPT compare timer 1              */
+#define UIC_CT2                0x00020000      /* GPT compare timer 2              */
+#define UIC_CT3                0x00010000      /* GPT compare timer 3              */
+#define UIC_CT4                0x00008000      /* GPT compare timer 4              */
+#define UIC_EIR12      0x00004000      /* External interrupt 12            */
+#define UIC_EIR11      0x00002000      /* External interrupt 11            */
+#define UIC_EIR10      0x00001000      /* External interrupt 10            */
+#define UIC_EIR9       0x00000800      /* External interrupt 9             */
+#define UIC_EIR8       0x00000400      /* External interrupt 8             */
+#define UIC_DMAE       0x00000200      /* dma error                        */
+#define UIC_I2OE       0x00000100      /* i2o error                        */
+#define UIC_SRE                0x00000080      /* Serial ROM error                 */
+#define UIC_PCIXAE     0x00000040      /* Pcix0 async error                */
+#define UIC_EIR7       0x00000020      /* External interrupt 7             */
+#define UIC_EIR6       0x00000010      /* External interrupt 6             */
+#define UIC_ETH0       0x00000008      /* Ethernet 0                       */
+#define UIC_EWU0       0x00000004      /* Ethernet 0 wakeup                */
+#define UIC_ETH1       0x00000002      /* reserved                         */
+#define UIC_XOR                0x00000001      /* xor                              */
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 2 interrupts (UIC2)
++---------------------------------------------------------------------------*/
+#define UIC_PEOAL      0x80000000      /* PE0  AL                          */
+#define UIC_PEOVA      0x40000000      /* PE0  VPD access                  */
+#define UIC_PEOHRR     0x20000000      /* PE0 Host reset request rising    */
+#define UIC_PE0HRF     0x10000000      /* PE0 Host reset request falling   */
+#define UIC_PE0TCR     0x08000000      /* PE0 TCR                          */
+#define UIC_PE0BVCO    0x04000000      /* PE0 Busmaster VCO                */
+#define UIC_PE0DCRE    0x02000000      /* PE0 DCR error                    */
+#define UIC_PE1AL      0x00800000      /* PE1  AL                          */
+#define UIC_PE1VA      0x00400000      /* PE1  VPD access                  */
+#define UIC_PE1HRR     0x00200000      /* PE1 Host reset request rising    */
+#define UIC_PE1HRF     0x00100000      /* PE1 Host reset request falling   */
+#define UIC_PE1TCR     0x00080000      /* PE1 TCR                          */
+#define UIC_PE1BVCO    0x00040000      /* PE1 Busmaster VCO                */
+#define UIC_PE1DCRE    0x00020000      /* PE1 DCR error                    */
+#define UIC_PE2AL      0x00008000      /* PE2  AL                          */
+#define UIC_PE2VA      0x00004000      /* PE2  VPD access                  */
+#define UIC_PE2HRR     0x00002000      /* PE2 Host reset request rising    */
+#define UIC_PE2HRF     0x00001000      /* PE2 Host reset request falling   */
+#define UIC_PE2TCR     0x00000800      /* PE2 TCR                          */
+#define UIC_PE2BVCO    0x00000400      /* PE2 Busmaster VCO                */
+#define UIC_PE2DCRE    0x00000200      /* PE2 DCR error                    */
+#define UIC_EIR5       0x00000080      /* External interrupt 5             */
+#define UIC_EIR4       0x00000040      /* External interrupt 4             */
+#define UIC_EIR3       0x00000020      /* External interrupt 3             */
+#define UIC_EIR2       0x00000010      /* External interrupt 2             */
+#define UIC_EIR1       0x00000008      /* External interrupt 1             */
+#define UIC_EIR0       0x00000004      /* External interrupt 0             */
+#endif /* CONFIG_440SPE */
 
 /*-----------------------------------------------------------------------------+
 |  External Bus Controller Bit Settings
 /*-----------------------------------------------------------------------------+
 |  SDR0 Bit Settings
 +-----------------------------------------------------------------------------*/
+#if defined(CONFIG_440SPE)
+#define SDR0_CP440                     0x0180
+#define SDR0_CP440_ERPN_MASK           0x30000000
+#define SDR0_CP440_ERPN_MASK_HI                0x3000
+#define SDR0_CP440_ERPN_MASK_LO                0x0000
+#define SDR0_CP440_ERPN_EBC            0x10000000
+#define SDR0_CP440_ERPN_EBC_HI         0x1000
+#define SDR0_CP440_ERPN_EBC_LO         0x0000
+#define SDR0_CP440_ERPN_PCI            0x20000000
+#define SDR0_CP440_ERPN_PCI_HI         0x2000
+#define SDR0_CP440_ERPN_PCI_LO         0x0000
+#define SDR0_CP440_ERPN_ENCODE(n)      ((((unsigned long)(n))&0x03)<<28)
+#define SDR0_CP440_ERPN_DECODE(n)      ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_CP440_NTO1_MASK           0x00000002
+#define SDR0_CP440_NTO1_NTOP           0x00000000
+#define SDR0_CP440_NTO1_NTO1           0x00000002
+#define SDR0_CP440_NTO1_ENCODE(n)      ((((unsigned long)(n))&0x01)<<1)
+#define SDR0_CP440_NTO1_DECODE(n)      ((((unsigned long)(n))>>1)&0x01)
+#define SDR0_CFGADDR                   0x00E   /*already defined line 277 */
+#define SDR0_CFGDATA                   0x00F
+
+
+#define SDR0_SDSTP0                    0x0020
+#define SDR0_SDSTP0_ENG_MASK           0x80000000
+#define SDR0_SDSTP0_ENG_PLLDIS         0x00000000
+#define SDR0_SDSTP0_ENG_PLLENAB                0x80000000
+#define SDR0_SDSTP0_ENG_ENCODE(n)      ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_SDSTP0_ENG_DECODE(n)      ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_SDSTP0_SRC_MASK           0x40000000
+#define SDR0_SDSTP0_SRC_PLLOUTA                0x00000000
+#define SDR0_SDSTP0_SRC_PLLOUTB                0x40000000
+#define SDR0_SDSTP0_SRC_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_SDSTP0_SRC_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_SDSTP0_SEL_MASK           0x38000000
+#define SDR0_SDSTP0_SEL_PLLOUT         0x00000000
+#define SDR0_SDSTP0_SEL_CPU            0x08000000
+#define SDR0_SDSTP0_SEL_EBC            0x28000000
+#define SDR0_SDSTP0_SEL_ENCODE(n)      ((((unsigned long)(n))&0x07)<<27)
+#define SDR0_SDSTP0_SEL_DECODE(n)      ((((unsigned long)(n))>>27)&0x07)
+#define SDR0_SDSTP0_TUNE_MASK          0x07FE0000
+#define SDR0_SDSTP0_TUNE_ENCODE(n)     ((((unsigned long)(n))&0x3FF)<<17)
+#define SDR0_SDSTP0_TUNE_DECODE(n)     ((((unsigned long)(n))>>17)&0x3FF)
+#define SDR0_SDSTP0_FBDV_MASK          0x0001F000
+#define SDR0_SDSTP0_FBDV_ENCODE(n)     ((((unsigned long)(n))&0x1F)<<12)
+#define SDR0_SDSTP0_FBDV_DECODE(n)     ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
+#define SDR0_SDSTP0_FWDVA_MASK         0x00000F00
+#define SDR0_SDSTP0_FWDVA_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<8)
+#define SDR0_SDSTP0_FWDVA_DECODE(n)    ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
+#define SDR0_SDSTP0_FWDVB_MASK         0x000000E0
+#define SDR0_SDSTP0_FWDVB_ENCODE(n)    ((((unsigned long)(n))&0x07)<<5)
+#define SDR0_SDSTP0_FWDVB_DECODE(n)    ((((((unsigned long)(n))>>5)-1)&0x07)+1)
+#define SDR0_SDSTP0_PRBDV0_MASK                0x0000001C
+#define SDR0_SDSTP0_PRBDV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<2)
+#define SDR0_SDSTP0_PRBDV0_DECODE(n)   ((((((unsigned long)(n))>>2)-1)&0x07)+1)
+#define SDR0_SDSTP0_OPBDV0_MASK                0x00000003
+#define SDR0_SDSTP0_OPBDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<0)
+#define SDR0_SDSTP0_OPBDV0_DECODE(n)   ((((((unsigned long)(n))>>0)-1)&0x03)+1)
+
+
+#define SDR0_SDSTP1                    0x0021
+#define SDR0_SDSTP1_LFBDV_MASK         0xFC000000
+#define SDR0_SDSTP1_LFBDV_ENCODE(n)    ((((unsigned long)(n))&0x3F)<<26)
+#define SDR0_SDSTP1_LFBDV_DECODE(n)    ((((unsigned long)(n))>>26)&0x3F)
+#define SDR0_SDSTP1_PERDV0_MASK                0x03000000
+#define SDR0_SDSTP1_PERDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define SDR0_SDSTP1_PERDV0_DECODE(n)   ((((unsigned long)(n))>>24)&0x03)
+#define SDR0_SDSTP1_MALDV0_MASK                0x00C00000
+#define SDR0_SDSTP1_MALDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<22)
+#define SDR0_SDSTP1_MALDV0_DECODE(n)   ((((unsigned long)(n))>>22)&0x03)
+#define SDR0_SDSTP1_DDR_MODE_MASK      0x00300000
+#define SDR0_SDSTP1_DDR1_MODE          0x00100000
+#define SDR0_SDSTP1_DDR2_MODE          0x00200000
+#define SDR0_SDSTP1_DDR_ENCODE(n)      ((((unsigned long)(n))&0x03)<<20)
+#define SDR0_SDSTP1_DDR_DECODE(n)      ((((unsigned long)(n))>>20)&0x03)
+#define SDR0_SDSTP1_ERPN_MASK          0x00080000
+#define SDR0_SDSTP1_ERPN_EBC           0x00000000
+#define SDR0_SDSTP1_ERPN_PCI           0x00080000
+#define SDR0_SDSTP1_PAE_MASK           0x00040000
+#define SDR0_SDSTP1_PAE_DISABLE                0x00000000
+#define SDR0_SDSTP1_PAE_ENABLE         0x00040000
+#define SDR0_SDSTP1_PAE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<18)
+#define SDR0_SDSTP1_PAE_DECODE(n)      ((((unsigned long)(n))>>18)&0x01)
+#define SDR0_SDSTP1_PHCE_MASK          0x00020000
+#define SDR0_SDSTP1_PHCE_DISABLE       0x00000000
+#define SDR0_SDSTP1_PHCE_ENABLE                0x00020000
+#define SDR0_SDSTP1_PHCE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<17)
+#define SDR0_SDSTP1_PHCE_DECODE(n)     ((((unsigned long)(n))>>17)&0x01)
+#define SDR0_SDSTP1_PISE_MASK          0x00010000
+#define SDR0_SDSTP1_PISE_DISABLE       0x00000000
+#define SDR0_SDSTP1_PISE_ENABLE                0x00001000
+#define SDR0_SDSTP1_PISE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<16)
+#define SDR0_SDSTP1_PISE_DECODE(n)     ((((unsigned long)(n))>>16)&0x01)
+#define SDR0_SDSTP1_PCWE_MASK          0x00008000
+#define SDR0_SDSTP1_PCWE_DISABLE       0x00000000
+#define SDR0_SDSTP1_PCWE_ENABLE                0x00008000
+#define SDR0_SDSTP1_PCWE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<15)
+#define SDR0_SDSTP1_PCWE_DECODE(n)     ((((unsigned long)(n))>>15)&0x01)
+#define SDR0_SDSTP1_PPIM_MASK          0x00007800
+#define SDR0_SDSTP1_PPIM_ENCODE(n)     ((((unsigned long)(n))&0x0F)<<11)
+#define SDR0_SDSTP1_PPIM_DECODE(n)     ((((unsigned long)(n))>>11)&0x0F)
+#define SDR0_SDSTP1_PR64E_MASK         0x00000400
+#define SDR0_SDSTP1_PR64E_DISABLE      0x00000000
+#define SDR0_SDSTP1_PR64E_ENABLE       0x00000400
+#define SDR0_SDSTP1_PR64E_ENCODE(n)    ((((unsigned long)(n))&0x01)<<10)
+#define SDR0_SDSTP1_PR64E_DECODE(n)    ((((unsigned long)(n))>>10)&0x01)
+#define SDR0_SDSTP1_PXFS_MASK          0x00000300
+#define SDR0_SDSTP1_PXFS_100_133       0x00000000
+#define SDR0_SDSTP1_PXFS_66_100                0x00000100
+#define SDR0_SDSTP1_PXFS_50_66         0x00000200
+#define SDR0_SDSTP1_PXFS_0_50          0x00000300
+#define SDR0_SDSTP1_PXFS_ENCODE(n)     ((((unsigned long)(n))&0x03)<<8)
+#define SDR0_SDSTP1_PXFS_DECODE(n)     ((((unsigned long)(n))>>8)&0x03)
+#define SDR0_SDSTP1_EBCW_MASK          0x00000080 /* SOP */
+#define SDR0_SDSTP1_EBCW_8_BITS                0x00000000 /* SOP */
+#define SDR0_SDSTP1_EBCW_16_BITS       0x00000080 /* SOP */
+#define SDR0_SDSTP1_DBGEN_MASK         0x00000030 /* $218C */
+#define SDR0_SDSTP1_DBGEN_FUNC         0x00000000
+#define SDR0_SDSTP1_DBGEN_TRACE                0x00000010
+#define SDR0_SDSTP1_DBGEN_ENCODE(n)    ((((unsigned long)(n))&0x03)<<4) /* $218C */
+#define SDR0_SDSTP1_DBGEN_DECODE(n)    ((((unsigned long)(n))>>4)&0x03) /* $218C */
+#define SDR0_SDSTP1_ETH_MASK           0x00000004
+#define SDR0_SDSTP1_ETH_10_100         0x00000000
+#define SDR0_SDSTP1_ETH_GIGA           0x00000004
+#define SDR0_SDSTP1_ETH_ENCODE(n)      ((((unsigned long)(n))&0x01)<<2)
+#define SDR0_SDSTP1_ETH_DECODE(n)      ((((unsigned long)(n))>>2)&0x01)
+#define SDR0_SDSTP1_NTO1_MASK          0x00000001
+#define SDR0_SDSTP1_NTO1_DISABLE       0x00000000
+#define SDR0_SDSTP1_NTO1_ENABLE                0x00000001
+#define SDR0_SDSTP1_NTO1_ENCODE(n)     ((((unsigned long)(n))&0x01)<<0)
+#define SDR0_SDSTP1_NTO1_DECODE(n)     ((((unsigned long)(n))>>0)&0x01)
+
+#define SDR0_SDSTP2                    0x0022
+#define SDR0_SDSTP2_P1AE_MASK          0x80000000
+#define SDR0_SDSTP2_P1AE_DISABLE       0x00000000
+#define SDR0_SDSTP2_P1AE_ENABLE                0x80000000
+#define SDR0_SDSTP2_P1AE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_SDSTP2_P1AE_DECODE(n)     ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_SDSTP2_P1HCE_MASK         0x40000000
+#define SDR0_SDSTP2_P1HCE_DISABLE      0x00000000
+#define SDR0_SDSTP2_P1HCE_ENABLE       0x40000000
+#define SDR0_SDSTP2_P1HCE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_SDSTP2_P1HCE_DECODE(n)    ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_SDSTP2_P1ISE_MASK         0x20000000
+#define SDR0_SDSTP2_P1ISE_DISABLE      0x00000000
+#define SDR0_SDSTP2_P1ISE_ENABLE       0x20000000
+#define SDR0_SDSTP2_P1ISE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<29)
+#define SDR0_SDSTP2_P1ISE_DECODE(n)    ((((unsigned long)(n))>>29)&0x01)
+#define SDR0_SDSTP2_P1CWE_MASK         0x10000000
+#define SDR0_SDSTP2_P1CWE_DISABLE      0x00000000
+#define SDR0_SDSTP2_P1CWE_ENABLE       0x10000000
+#define SDR0_SDSTP2_P1CWE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<28)
+#define SDR0_SDSTP2_P1CWE_DECODE(n)    ((((unsigned long)(n))>>28)&0x01)
+#define SDR0_SDSTP2_P1PIM_MASK         0x0F000000
+#define SDR0_SDSTP2_P1PIM_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<24)
+#define SDR0_SDSTP2_P1PIM_DECODE(n)    ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_SDSTP2_P1R64E_MASK                0x00800000
+#define SDR0_SDSTP2_P1R64E_DISABLE     0x00000000
+#define SDR0_SDSTP2_P1R64E_ENABLE      0x00800000
+#define SDR0_SDSTP2_P1R64E_ENCODE(n)   ((((unsigned long)(n))&0x01)<<23)
+#define SDR0_SDSTP2_P1R64E_DECODE(n)   ((((unsigned long)(n))>>23)&0x01)
+#define SDR0_SDSTP2_P1XFS_MASK         0x00600000
+#define SDR0_SDSTP2_P1XFS_100_133      0x00000000
+#define SDR0_SDSTP2_P1XFS_66_100       0x00200000
+#define SDR0_SDSTP2_P1XFS_50_66                0x00400000
+#define SDR0_SDSTP2_P1XFS_0_50         0x00600000
+#define SDR0_SDSTP2_P1XFS_ENCODE(n)    ((((unsigned long)(n))&0x03)<<21)
+#define SDR0_SDSTP2_P1XFS_DECODE(n)    ((((unsigned long)(n))>>21)&0x03)
+#define SDR0_SDSTP2_P2AE_MASK          0x00040000
+#define SDR0_SDSTP2_P2AE_DISABLE       0x00000000
+#define SDR0_SDSTP2_P2AE_ENABLE                0x00040000
+#define SDR0_SDSTP2_P2AE_ENCODE(n)     ((((unsigned long)(n))&0x01)<<18)
+#define SDR0_SDSTP2_P2AE_DECODE(n)     ((((unsigned long)(n))>>18)&0x01)
+#define SDR0_SDSTP2_P2HCE_MASK         0x00020000
+#define SDR0_SDSTP2_P2HCE_DISABLE      0x00000000
+#define SDR0_SDSTP2_P2HCE_ENABLE       0x00020000
+#define SDR0_SDSTP2_P2HCE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<17)
+#define SDR0_SDSTP2_P2HCE_DECODE(n)    ((((unsigned long)(n))>>17)&0x01)
+#define SDR0_SDSTP2_P2ISE_MASK         0x00010000
+#define SDR0_SDSTP2_P2ISE_DISABLE      0x00000000
+#define SDR0_SDSTP2_P2ISE_ENABLE       0x00010000
+#define SDR0_SDSTP2_P2ISE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<16)
+#define SDR0_SDSTP2_P2ISE_DECODE(n)    ((((unsigned long)(n))>>16)&0x01)
+#define SDR0_SDSTP2_P2CWE_MASK         0x00008000
+#define SDR0_SDSTP2_P2CWE_DISABLE      0x00000000
+#define SDR0_SDSTP2_P2CWE_ENABLE       0x00008000
+#define SDR0_SDSTP2_P2CWE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<15)
+#define SDR0_SDSTP2_P2CWE_DECODE(n)    ((((unsigned long)(n))>>15)&0x01)
+#define SDR0_SDSTP2_P2PIM_MASK         0x00007800
+#define SDR0_SDSTP2_P2PIM_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<11)
+#define SDR0_SDSTP2_P2PIM_DECODE(n)    ((((unsigned long)(n))>>11)&0x0F)
+#define SDR0_SDSTP2_P2XFS_MASK         0x00000300
+#define SDR0_SDSTP2_P2XFS_100_133      0x00000000
+#define SDR0_SDSTP2_P2XFS_66_100       0x00000100
+#define SDR0_SDSTP2_P2XFS_50_66                0x00000200
+#define SDR0_SDSTP2_P2XFS_0_50         0x00000100
+#define SDR0_SDSTP2_P2XFS_ENCODE(n)    ((((unsigned long)(n))&0x03)<<8)
+#define SDR0_SDSTP2_P2XFS_DECODE(n)    ((((unsigned long)(n))>>8)&0x03)
+
+#define SDR0_SDSTP3                    0x0023
+
+#define SDR0_PINSTP                    0x0040
+#define SDR0_PINSTP_BOOTSTRAP_MASK     0xC0000000  /* Strap Bits */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0        0x00000000  /* Default strap settings 0 (EBC boot) */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1        0x40000000  /* Default strap settings 1 (PCI boot) */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN        0x80000000  /* Serial Device Enabled - Addr = 0x54 */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN        0xC0000000  /* Serial Device Enabled - Addr = 0x50 */
+#define SDR0_SDCS                      0x0060
+#define SDR0_ECID0                     0x0080
+#define SDR0_ECID1                     0x0081
+#define SDR0_ECID2                     0x0082
+#define SDR0_JTAG                      0x00C0
+
+#define SDR0_DDR0                      0x00E1
+#define SDR0_DDR0_DPLLRST              0x80000000
+#define SDR0_DDR0_DDRM_MASK            0x60000000
+#define SDR0_DDR0_DDRM_DDR1            0x20000000
+#define SDR0_DDR0_DDRM_DDR2            0x40000000
+#define SDR0_DDR0_DDRM_ENCODE(n)       ((((unsigned long)(n))&0x03)<<29)
+#define SDR0_DDR0_DDRM_DECODE(n)       ((((unsigned long)(n))>>29)&0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n)       ((((unsigned long)(n))&0x2FF)<<0)
+#define SDR0_DDR0_TUNE_DECODE(n)       ((((unsigned long)(n))>>0)&0x2FF)
+
+#define SDR0_UART0                     0x0120
+#define SDR0_UART1                     0x0121
+#define SDR0_UART2                     0x0122
+#define SDR0_UARTX_UXICS_MASK          0xF0000000
+#define SDR0_UARTX_UXICS_PLB           0x20000000
+#define SDR0_UARTX_UXEC_MASK           0x00800000
+#define SDR0_UARTX_UXEC_INT            0x00000000
+#define SDR0_UARTX_UXEC_EXT            0x00800000
+#define SDR0_UARTX_UXDIV_MASK          0x000000FF
+#define SDR0_UARTX_UXDIV_ENCODE(n)     ((((unsigned long)(n))&0xFF)<<0)
+#define SDR0_UARTX_UXDIV_DECODE(n)     ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
+
+#define SDR0_CP440                     0x0180
+#define SDR0_CP440_ERPN_MASK           0x30000000
+#define SDR0_CP440_ERPN_MASK_HI                0x3000
+#define SDR0_CP440_ERPN_MASK_LO                0x0000
+#define SDR0_CP440_ERPN_EBC            0x10000000
+#define SDR0_CP440_ERPN_EBC_HI         0x1000
+#define SDR0_CP440_ERPN_EBC_LO         0x0000
+#define SDR0_CP440_ERPN_PCI            0x20000000
+#define SDR0_CP440_ERPN_PCI_HI         0x2000
+#define SDR0_CP440_ERPN_PCI_LO         0x0000
+#define SDR0_CP440_ERPN_ENCODE(n)      ((((unsigned long)(n))&0x03)<<28)
+#define SDR0_CP440_ERPN_DECODE(n)      ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_CP440_NTO1_MASK           0x00000002
+#define SDR0_CP440_NTO1_NTOP           0x00000000
+#define SDR0_CP440_NTO1_NTO1           0x00000002
+#define SDR0_CP440_NTO1_ENCODE(n)      ((((unsigned long)(n))&0x01)<<1)
+#define SDR0_CP440_NTO1_DECODE(n)      ((((unsigned long)(n))>>1)&0x01)
+
+#define SDR0_XCR0                      0x01C0
+#define SDR0_XCR1                      0x01C3
+#define SDR0_XCR2                      0x01C6
+#define SDR0_XCRn_PAE_MASK             0x80000000
+#define SDR0_XCRn_PAE_DISABLE          0x00000000
+#define SDR0_XCRn_PAE_ENABLE           0x80000000
+#define SDR0_XCRn_PAE_ENCODE(n)                ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_XCRn_PAE_DECODE(n)                ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_XCRn_PHCE_MASK            0x40000000
+#define SDR0_XCRn_PHCE_DISABLE         0x00000000
+#define SDR0_XCRn_PHCE_ENABLE          0x40000000
+#define SDR0_XCRn_PHCE_ENCODE(n)       ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_XCRn_PHCE_DECODE(n)       ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_XCRn_PISE_MASK            0x20000000
+#define SDR0_XCRn_PISE_DISABLE         0x00000000
+#define SDR0_XCRn_PISE_ENABLE          0x20000000
+#define SDR0_XCRn_PISE_ENCODE(n)       ((((unsigned long)(n))&0x01)<<29)
+#define SDR0_XCRn_PISE_DECODE(n)       ((((unsigned long)(n))>>29)&0x01)
+#define SDR0_XCRn_PCWE_MASK            0x10000000
+#define SDR0_XCRn_PCWE_DISABLE         0x00000000
+#define SDR0_XCRn_PCWE_ENABLE          0x10000000
+#define SDR0_XCRn_PCWE_ENCODE(n)       ((((unsigned long)(n))&0x01)<<28)
+#define SDR0_XCRn_PCWE_DECODE(n)       ((((unsigned long)(n))>>28)&0x01)
+#define SDR0_XCRn_PPIM_MASK            0x0F000000
+#define SDR0_XCRn_PPIM_ENCODE(n)       ((((unsigned long)(n))&0x0F)<<24)
+#define SDR0_XCRn_PPIM_DECODE(n)       ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_XCRn_PR64E_MASK           0x00800000
+#define SDR0_XCRn_PR64E_DISABLE                0x00000000
+#define SDR0_XCRn_PR64E_ENABLE         0x00800000
+#define SDR0_XCRn_PR64E_ENCODE(n)      ((((unsigned long)(n))&0x01)<<23)
+#define SDR0_XCRn_PR64E_DECODE(n)      ((((unsigned long)(n))>>23)&0x01)
+#define SDR0_XCRn_PXFS_MASK            0x00600000
+#define SDR0_XCRn_PXFS_100_133         0x00000000
+#define SDR0_XCRn_PXFS_66_100          0x00200000
+#define SDR0_XCRn_PXFS_50_66           0x00400000
+#define SDR0_XCRn_PXFS_0_33            0x00600000
+#define SDR0_XCRn_PXFS_ENCODE(n)       ((((unsigned long)(n))&0x03)<<21)
+#define SDR0_XCRn_PXFS_DECODE(n)       ((((unsigned long)(n))>>21)&0x03)
+
+#define SDR0_XPLLC0                    0x01C1
+#define SDR0_XPLLD0                    0x01C2
+#define SDR0_XPLLC1                    0x01C4
+#define SDR0_XPLLD1                    0x01C5
+#define SDR0_XPLLC2                    0x01C7
+#define SDR0_XPLLD2                    0x01C8
+#define SDR0_SRST                      0x0200
+#define SDR0_SLPIPE                    0x0220
+
+#define SDR0_AMP0                      0x0240
+#define SDR0_AMP0_PRIORITY             0xFFFF0000
+#define SDR0_AMP0_ALTERNATE_PRIORITY   0x0000FF00
+#define SDR0_AMP0_RESERVED_BITS_MASK   0x000000FF
+
+#define SDR0_AMP1                      0x0241
+#define SDR0_AMP1_PRIORITY             0xFC000000
+#define SDR0_AMP1_ALTERNATE_PRIORITY   0x0000E000
+#define SDR0_AMP1_RESERVED_BITS_MASK   0x03FF1FFF
+
+#define SDR0_MIRQ0                     0x0260
+#define SDR0_MIRQ1                     0x0261
+#define SDR0_MALTBL                    0x0280
+#define SDR0_MALRBL                    0x02A0
+#define SDR0_MALTBS                    0x02C0
+#define SDR0_MALRBS                    0x02E0
+
+/* Reserved for Customer Use */
+#define SDR0_CUST0                     0x4000
+#define SDR0_CUST0_AUTONEG_MASK                0x8000000
+#define SDR0_CUST0_NO_AUTONEG          0x0000000
+#define SDR0_CUST0_AUTONEG             0x8000000
+#define SDR0_CUST0_ETH_FORCE_MASK      0x6000000
+#define SDR0_CUST0_ETH_FORCE_10MHZ     0x0000000
+#define SDR0_CUST0_ETH_FORCE_100MHZ    0x2000000
+#define SDR0_CUST0_ETH_FORCE_1000MHZ   0x4000000
+#define SDR0_CUST0_ETH_DUPLEX_MASK     0x1000000
+#define SDR0_CUST0_ETH_HALF_DUPLEX     0x0000000
+#define SDR0_CUST0_ETH_FULL_DUPLEX     0x1000000
+
+#define SDR0_SDSTP4                    0x4001
+#define SDR0_CUST1                     0x4002
+#define SDR0_SDSTP5                    0x4003
+#define SDR0_CUST2                     0x4004
+#define SDR0_SDSTP6                    0x4005
+#define SDR0_CUST3                     0x4006
+#define SDR0_SDSTP7                    0x4007
+
+#define SDR0_PFC0                      0x4100
+#define SDR0_PFC0_GPIO_0               0x80000000
+#define SDR0_PFC0_PCIX0REQ2_N          0x00000000
+#define SDR0_PFC0_GPIO_1               0x40000000
+#define SDR0_PFC0_PCIX0REQ3_N          0x00000000
+#define SDR0_PFC0_GPIO_2               0x20000000
+#define SDR0_PFC0_PCIX0GNT2_N          0x00000000
+#define SDR0_PFC0_GPIO_3               0x10000000
+#define SDR0_PFC0_PCIX0GNT3_N          0x00000000
+#define SDR0_PFC0_GPIO_4               0x08000000
+#define SDR0_PFC0_PCIX1REQ2_N          0x00000000
+#define SDR0_PFC0_GPIO_5               0x04000000
+#define SDR0_PFC0_PCIX1REQ3_N          0x00000000
+#define SDR0_PFC0_GPIO_6               0x02000000
+#define SDR0_PFC0_PCIX1GNT2_N          0x00000000
+#define SDR0_PFC0_GPIO_7               0x01000000
+#define SDR0_PFC0_PCIX1GNT3_N          0x00000000
+#define SDR0_PFC0_GPIO_8               0x00800000
+#define SDR0_PFC0_PERREADY             0x00000000
+#define SDR0_PFC0_GPIO_9               0x00400000
+#define SDR0_PFC0_PERCS1_N             0x00000000
+#define SDR0_PFC0_GPIO_10              0x00200000
+#define SDR0_PFC0_PERCS2_N             0x00000000
+#define SDR0_PFC0_GPIO_11              0x00100000
+#define SDR0_PFC0_IRQ0                 0x00000000
+#define SDR0_PFC0_GPIO_12              0x00080000
+#define SDR0_PFC0_IRQ1                 0x00000000
+#define SDR0_PFC0_GPIO_13              0x00040000
+#define SDR0_PFC0_IRQ2                 0x00000000
+#define SDR0_PFC0_GPIO_14              0x00020000
+#define SDR0_PFC0_IRQ3                 0x00000000
+#define SDR0_PFC0_GPIO_15              0x00010000
+#define SDR0_PFC0_IRQ4                 0x00000000
+#define SDR0_PFC0_GPIO_16              0x00008000
+#define SDR0_PFC0_IRQ5                 0x00000000
+#define SDR0_PFC0_GPIO_17              0x00004000
+#define SDR0_PFC0_PERBE0_N             0x00000000
+#define SDR0_PFC0_GPIO_18              0x00002000
+#define SDR0_PFC0_PCI0GNT0_N           0x00000000
+#define SDR0_PFC0_GPIO_19              0x00001000
+#define SDR0_PFC0_PCI0GNT1_N           0x00000000
+#define SDR0_PFC0_GPIO_20              0x00000800
+#define SDR0_PFC0_PCI0REQ0_N           0x00000000
+#define SDR0_PFC0_GPIO_21              0x00000400
+#define SDR0_PFC0_PCI0REQ1_N           0x00000000
+#define SDR0_PFC0_GPIO_22              0x00000200
+#define SDR0_PFC0_PCI1GNT0_N           0x00000000
+#define SDR0_PFC0_GPIO_23              0x00000100
+#define SDR0_PFC0_PCI1GNT1_N           0x00000000
+#define SDR0_PFC0_GPIO_24              0x00000080
+#define SDR0_PFC0_PCI1REQ0_N           0x00000000
+#define SDR0_PFC0_GPIO_25              0x00000040
+#define SDR0_PFC0_PCI1REQ1_N           0x00000000
+#define SDR0_PFC0_GPIO_26              0x00000020
+#define SDR0_PFC0_PCI2GNT0_N           0x00000000
+#define SDR0_PFC0_GPIO_27              0x00000010
+#define SDR0_PFC0_PCI2GNT1_N           0x00000000
+#define SDR0_PFC0_GPIO_28              0x00000008
+#define SDR0_PFC0_PCI2REQ0_N           0x00000000
+#define SDR0_PFC0_GPIO_29              0x00000004
+#define SDR0_PFC0_PCI2REQ1_N           0x00000000
+#define SDR0_PFC0_GPIO_30              0x00000002
+#define SDR0_PFC0_UART1RX              0x00000000
+#define SDR0_PFC0_GPIO_31              0x00000001
+#define SDR0_PFC0_UART1TX              0x00000000
+
+#define SDR0_PFC1                      0x4101
+#define SDR0_PFC1_UART1_CTS_RTS_MASK   0x02000000
+#define SDR0_PFC1_UART1_DSR_DTR                0x00000000
+#define SDR0_PFC1_UART1_CTS_RTS                0x02000000
+#define SDR0_PFC1_UART2_IN_SERVICE_MASK        0x01000000
+#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
+#define SDR0_PFC1_UART2_IN_SERVICE     0x01000000
+#define SDR0_PFC1_ETH_GIGA_MASK                0x00200000
+#define SDR0_PFC1_ETH_10_100           0x00000000
+#define SDR0_PFC1_ETH_GIGA             0x00200000
+#define SDR0_PFC1_ETH_GIGA_ENCODE(n)   ((((unsigned long)(n))&0x1)<<21)
+#define SDR0_PFC1_ETH_GIGA_DECODE(n)   ((((unsigned long)(n))>>21)&0x01)
+#define SDR0_PFC1_CPU_TRACE_MASK       0x00180000   /* $218C */
+#define SDR0_PFC1_CPU_NO_TRACE         0x00000000
+#define SDR0_PFC1_CPU_TRACE            0x00080000
+#define SDR0_PFC1_CPU_TRACE_ENCODE(n)  ((((unsigned long)(n))&0x3)<<19)     /* $218C */
+#define SDR0_PFC1_CPU_TRACE_DECODE(n)  ((((unsigned long)(n))>>19)&0x03)    /* $218C */
+
+#define SDR0_MFR                       0x4300
+#endif /* CONFIG_440SPE        */
+
+
 #define SDR0_SDCS_SDD                  (0x80000000 >> 31)
 
 #if defined(CONFIG_440GP)
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #define PLLSYS0_TUNE_MASK      0xffc00000      /* PLL TUNE bits            */
 #define PLLSYS0_FB_DIV_MASK    0x003c0000      /* Feedback divisor         */
 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000      /* Forward divisor A        */
@@ -1448,6 +2722,9 @@ typedef struct {
        unsigned long freqOPB;
        unsigned long freqEPB;
        unsigned long freqPCI;
+#ifdef CONFIG_440SPE
+       unsigned long freqDDR;
+#endif
        unsigned long pciIntArbEn;            /* Internal PCI arbiter is enabled */
        unsigned long pciClkSync;             /* PCI clock is synchronous        */
 } PPC440_SYS_INFO;
index d6d33b6957b4a13f1174393067d7039f8d6ab043..ec2e3629bb894c55ac31ac30fa65be0baed165fc 100644 (file)
@@ -133,12 +133,21 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_NUM_DEV       4
 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&        \
        defined(CONFIG_NET_MULTI) &&                    \
-       !defined(CONFIG_440SP)
+       !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #define EMAC_NUM_DEV       2
 #else
 #define EMAC_NUM_DEV       1
 #endif
 
+#ifdef CONFIG_IBM_EMAC4_V4     /* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_OC_MASK     (0x00008000)
+#else
+#define EMAC_STACR_OC_MASK     (0x00000000)
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define SDR0_PFC1_EM_1000      (0x00200000)
+#endif
 
 /*ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
@@ -323,7 +332,7 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M0_WKE                        (0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE            (0x80000000)
 #define EMAC_M1_ILE            (0x40000000)
@@ -424,8 +433,21 @@ typedef struct emac_4xx_hw_st {
 /* STA CONTROL REG */
 #define EMAC_STACR_OC                  (0x00008000)
 #define EMAC_STACR_PHYE                        (0x00004000)
+
+#ifdef CONFIG_IBM_EMAC4_V4     /* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_INDIRECT_MODE       (0x00002000)
+#define EMAC_STACR_WRITE               (0x00000800) /* $BUC */
+#define EMAC_STACR_READ                        (0x00001000) /* $BUC */
+#define EMAC_STACR_OP_MASK             (0x00001800)
+#define EMAC_STACR_MDIO_ADDR           (0x00000000)
+#define EMAC_STACR_MDIO_WRITE          (0x00000800)
+#define EMAC_STACR_MDIO_READ           (0x00001800)
+#define EMAC_STACR_MDIO_READ_INC       (0x00001000)
+#else
 #define EMAC_STACR_WRITE               (0x00002000)
 #define EMAC_STACR_READ                        (0x00001000)
+#endif
+
 #define EMAC_STACR_CLK_83MHZ   (0x00000800)  /* 0's for 50Mhz */
 #define EMAC_STACR_CLK_66MHZ   (0x00000400)
 #define EMAC_STACR_CLK_100MHZ  (0x00000C00)