]> git.sur5r.net Git - u-boot/commitdiff
fpga: zynqmppl: Reuse invoke_smc routine
authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Fri, 17 Feb 2017 10:46:01 +0000 (16:16 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 20 Jun 2017 14:42:13 +0000 (16:42 +0200)
Reuse invoke_smc() routine which is already defined
instead of duplicating same at multiple places.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/fpga/zynqmppl.c

index 23039c3eb2d85fb453d1a953c1ff186df58a1b21..57a4e6c88e7a122483f29d016dff67eba2371267 100644 (file)
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <zynqmppl.h>
 #include <linux/sizes.h>
+#include <asm/arch/sys_proto.h>
 
 #define DUMMY_WORD     0xffffffff
 
@@ -191,25 +192,14 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
        return 0;
 }
 
-static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
-{
-       struct pt_regs regs;
-       regs.regs[0] = id;
-       regs.regs[1] = reg0;
-       regs.regs[2] = reg1;
-       regs.regs[3] = reg2;
-
-       smc_call(&regs);
-
-       return regs.regs[0];
-}
-
 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
                     bitstream_type bstype)
 {
        u32 swap;
-       ulong bin_buf, flags;
+       ulong bin_buf;
        int ret;
+       u32 buf_lo, buf_hi;
+       u32 ret_payload[PAYLOAD_ARG_CNT];
 
        if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
                return FPGA_FAIL;
@@ -224,9 +214,10 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
        else
                bsize = bsize / 4;
 
-       flags = (u32)bsize | ((u64)bstype << 32);
-
-       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
+       buf_lo = (u32)bin_buf;
+       buf_hi = upper_32_bits(bin_buf);
+       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
+                        bstype, ret_payload);
        if (ret)
                debug("PL FPGA LOAD fail\n");