]> git.sur5r.net Git - u-boot/commitdiff
rockchip: rk3288: dts: Make core devices available early
authorSimon Glass <sjg@chromium.org>
Sun, 30 Aug 2015 22:55:21 +0000 (16:55 -0600)
committerSimon Glass <sjg@chromium.org>
Thu, 3 Sep 2015 03:28:23 +0000 (21:28 -0600)
In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/dts/rk3288.dtsi

index 6b5145cc6d304144ea7d1af7650848afe57b0d88..0f497099679470ea39078d6ca9e5b1ae550995b0 100644 (file)
 
        interrupt-parent = <&gic>;
        aliases {
+               gpio0 = &gpio0;
+               gpio1 = &gpio1;
+               gpio2 = &gpio2;
+               gpio3 = &gpio3;
+               gpio4 = &gpio4;
+               gpio5 = &gpio5;
+               gpio6 = &gpio6;
+               gpio7 = &gpio7;
+               gpio8 = &gpio8;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
        };
 
        dmc: dmc@ff610000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-dmc", "syscon";
                rockchip,cru = <&cru>;
                rockchip,grf = <&grf>;
        };
 
        pmu: power-management@ff730000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-pmu", "syscon";
                reg = <0xff730000 0x100>;
        };
 
        sgrf: syscon@ff740000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-sgrf", "syscon";
                reg = <0xff740000 0x1000>;
        };
                compatible = "rockchip,rk3288-cru";
                reg = <0xff760000 0x1000>;
                rockchip,grf = <&grf>;
+               u-boot,dm-pre-reloc;
                #clock-cells = <1>;
                #reset-cells = <1>;
                assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
        };
 
        grf: syscon@ff770000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-grf", "syscon";
                reg = <0xff770000 0x1000>;
        };
        };
 
        noc: syscon@ffac0000 {
+               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-noc", "syscon";
                reg = <0xffac0000 0x2000>;
        };