Andreas Bießmann <andreas.devel@googlemail.com>
Aneesh V <aneesh@ti.com>
Dirk Behme <dirk.behme@googlemail.com>
-Fabio Estevam <fabio.estevam@freescale.com>
+Fabio Estevam <fabio.estevam@nxp.com>
Jagan Teki <402jagan@gmail.com>
Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com>
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Wolfgang Denk <wdenk>
York Sun <yorksun@freescale.com>
+York Sun <york.sun@nxp.com>
Łukasz Majewski <l.majewski@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/mach-uniphier/
-F: configs/ph1_*_defconfig
+F: configs/uniphier_*_defconfig
N: uniphier
ARM ZYNQ
T: git git://git.denx.de/u-boot-freebsd.git
FREESCALE QORIQ
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
F: arch/powerpc/include/asm/arch-mpc83xx/
POWERPC MPC85XX
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
VERSION = 2016
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
$(call if_changed,mkimage)
ifeq ($(ARCH),arm)
-ifdef CONFIG_DM
+ifdef CONFIG_OF_CONTROL
UBOOT_BINLOAD := u-boot-dtb.img
else
UBOOT_BINLOAD := u-boot.img
Makefile have been tested to some extent and can be considered
"working". In fact, many of them are used in production systems.
-In case of problems see the CHANGELOG and CREDITS files to find out
-who contributed the specific port. The boards.cfg file lists board
-maintainers.
+In case of problems see the CHANGELOG file to find out who contributed
+the specific port. In addition, there are various MAINTAINERS files
+scattered throughout the U-Boot source identifying the people or
+companies responsible for various boards and subsystems.
-Note: There is no CHANGELOG file in the actual U-Boot source tree;
-it can be created dynamically from the Git log using:
+Note: As of August, 2010, there is no longer a CHANGELOG file in the
+actual U-Boot source tree; however, it can be created dynamically
+from the Git log using:
make CHANGELOG
==================
In case you have questions about, problems with or contributions for
-U-Boot you should send a message to the U-Boot mailing list at
+U-Boot, you should send a message to the U-Boot mailing list at
<u-boot@lists.denx.de>. There is also an archive of previous traffic
on the mailing list - please search the archive before asking FAQ's.
Please see http://lists.denx.de/pipermail/u-boot and
Where to get source code:
=========================
-The U-Boot source code is maintained in the git repository at
+The U-Boot source code is maintained in the Git repository at
git://www.denx.de/git/u-boot.git ; you can browse it online at
http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary
/arch Architecture specific files
/arc Files generic to ARC architecture
- /cpu CPU specific files
- /arc700 Files specific to ARC 700 CPUs
- /lib Architecture specific library files
/arm Files generic to ARM architecture
- /cpu CPU specific files
- /arm720t Files specific to ARM 720 CPUs
- /arm920t Files specific to ARM 920 CPUs
- /at91 Files specific to Atmel AT91RM9200 CPU
- /imx Files specific to Freescale MC9328 i.MX CPUs
- /s3c24x0 Files specific to Samsung S3C24X0 CPUs
- /arm926ejs Files specific to ARM 926 CPUs
- /arm1136 Files specific to ARM 1136 CPUs
- /pxa Files specific to Intel XScale PXA CPUs
- /sa1100 Files specific to Intel StrongARM SA1100 CPUs
- /lib Architecture specific library files
/avr32 Files generic to AVR32 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/blackfin Files generic to Analog Devices Blackfin architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/m68k Files generic to m68k architecture
- /cpu CPU specific files
- /mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- /mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs
- /mcf532x Files specific to Freescale ColdFire MCF5329 CPUs
- /mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs
- /mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs
- /lib Architecture specific library files
/microblaze Files generic to microblaze architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/mips Files generic to MIPS architecture
- /cpu CPU specific files
- /mips32 Files specific to MIPS32 CPUs
- /mips64 Files specific to MIPS64 CPUs
- /lib Architecture specific library files
/nds32 Files generic to NDS32 architecture
- /cpu CPU specific files
- /n1213 Files specific to Andes Technology N1213 CPUs
- /lib Architecture specific library files
/nios2 Files generic to Altera NIOS2 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/openrisc Files generic to OpenRISC architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/powerpc Files generic to PowerPC architecture
- /cpu CPU specific files
- /mpc5xx Files specific to Freescale MPC5xx CPUs
- /mpc5xxx Files specific to Freescale MPC5xxx CPUs
- /mpc8xx Files specific to Freescale MPC8xx CPUs
- /mpc8260 Files specific to Freescale MPC8260 CPUs
- /mpc85xx Files specific to Freescale MPC85xx CPUs
- /ppc4xx Files specific to AMCC PowerPC 4xx CPUs
- /lib Architecture specific library files
+ /sandbox Files generic to HW-independent "sandbox"
/sh Files generic to SH architecture
- /cpu CPU specific files
- /sh2 Files specific to sh2 CPUs
- /sh3 Files specific to sh3 CPUs
- /sh4 Files specific to sh4 CPUs
- /lib Architecture specific library files
/sparc Files generic to SPARC architecture
- /cpu CPU specific files
- /leon2 Files specific to Gaisler LEON2 SPARC CPU
- /leon3 Files specific to Gaisler LEON3 SPARC CPU
- /lib Architecture specific library files
/x86 Files generic to x86 architecture
- /cpu CPU specific files
- /lib Architecture specific library files
/api Machine/arch independent API for external apps
/board Board dependent files
/common Misc architecture independent functions
+/configs Board default configuration files
/disk Code for disk drive partition handling
/doc Documentation (don't expect too much)
/drivers Commonly used device drivers
/examples Example code for standalone applications, etc.
/fs Filesystem code (cramfs, ext2, jffs2, etc.)
/include Header Files
-/lib Files generic to all architectures
- /libfdt Library files to support flattened device trees
- /lzma Library files to support LZMA decompression
- /lzo Library files to support LZO decompression
+/lib Library routines generic to all architectures
+/Licenses Various license files
/net Networking code
/post Power On Self Test
-/spl Secondary Program Loader framework
+/scripts Various build scripts and Makefiles
+/test Various unit test files
/tools Tools to build S-Record or U-Boot images, etc.
Software Configuration:
you don't know what you're doing; they have names beginning with
"CONFIG_SYS_".
-Later we will add a configuration tool - probably similar to or even
-identical to what's used for the Linux kernel. Right now, we have to
-do the configuration by hand, which means creating some symbolic
-links and editing some configuration files. We use the TQM8xxL boards
-as an example here.
+Previously, all configuration was done by hand, which involved creating
+symbolic links and editing configuration files manually. More recently,
+U-Boot has added the Kbuild infrastructure used by the Linux kernel,
+allowing you to use the "make menuconfig" command to configure your
+build.
Selection of Processor Architecture and Board Type:
cd u-boot
make TQM823L_defconfig
-For the Cogent platform, you need to specify the CPU type as well;
-e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent
-directory according to the instructions in cogent/README.
-
+Note: If you're looking for the default configuration file for a board
+you're sure used to be there but is now missing, check the file
+doc/README.scrapyard for a list of no longer supported boards.
Sandbox Environment:
--------------------
--------------------------
This is the intended start-up flow for boards. This should apply for both
-SPL and U-Boot proper (i.e. they both follow the same rules). At present SPL
-mostly uses a separate code path, but the funtion names and roles of each
-function are the same. Some boards or architectures may not conform to this.
-At least most ARM boards which use CONFIG_SPL_FRAMEWORK conform to this.
+SPL and U-Boot proper (i.e. they both follow the same rules).
+
+Note: "SPL" stands for "Secondary Program Loader," which is explained in
+more detail later in this file.
+
+At present, SPL mostly uses a separate code path, but the function names
+and roles of each function are the same. Some boards or architectures
+may not conform to this. At least most ARM boards which use
+CONFIG_SPL_FRAMEWORK conform to this.
+
+Execution typically starts with an architecture-specific (and possibly
+CPU-specific) start.S file, such as:
+
+ - arch/arm/cpu/armv7/start.S
+ - arch/powerpc/cpu/mpc83xx/start.S
+ - arch/mips/cpu/start.S
-Execution starts with start.S with three functions called during init after
-that. The purpose and limitations of each is described below.
+and so on. From there, three functions are called; the purpose and
+limitations of each of these functions are described below.
lowlevel_init():
- purpose: essential init to permit execution to reach board_init_f()
* A CHANGELOG entry as plaintext (separate from the patch)
-* For major contributions, your entry to the CREDITS file
+* For major contributions, add a MAINTAINERS file with your
+ information and associated file and directory references.
* When you add support for a new board, don't forget to add a
maintainer e-mail address to the boards.cfg file, too.
reg = < 0xe0040000 0x100 >;
interrupts = < 8 >;
};
+
+ ohci@0xe0060000 {
+ compatible = "generic-ohci";
+ reg = < 0xe0060000 0x100 >;
+ interrupts = < 8 >;
+ };
};
bool "Support sunxi (Allwinner) SoCs"
select CMD_USB
select DM
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_KEYBOARD
select DM_SERIAL
select DM_USB
select OF_CONTROL
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
+/**
+ * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
+ * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock
+ *
+ * This function configures and then enables an alternative PLL clock source
+ * for the DC-DC converters.
+ */
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
+{
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
+
+ /* Select clocksource for DC-DC converters */
+ clrsetbits_le32(&power_regs->hw_power_misc,
+ POWER_MISC_FREQSEL_MASK,
+ freqsel);
+ setbits_le32(&power_regs->hw_power_misc,
+ POWER_MISC_SEL_PLLCLK);
+}
+
+/**
+ * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
+ *
+ * Normally, there is no need to switch DC-DC clocksource. This is the reason,
+ * why this function is a stub and does nothing. However, boards can implement
+ * this function when required and call mxs_power_switch_dcdc_clocksource() to
+ * switch to an alternative clock source.
+ */
+__weak void mxs_power_setup_dcdc_clocksource(void)
+{
+ debug("SPL: Using default DC-DC clocksource\n");
+}
+
/**
* mxs_src_power_init() - Preconfigure the power block
*
debug("SPL: Configuring power source\n");
+ mxs_power_setup_dcdc_clocksource();
mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
# endif
# endif
};
+
+#ifdef CONFIG_DM_GPIO
+static const struct omap_gpio_platdata am33xx_gpio[] = {
+ { 0, AM33XX_GPIO0_BASE },
+ { 1, AM33XX_GPIO1_BASE },
+ { 2, AM33XX_GPIO2_BASE },
+ { 3, AM33XX_GPIO3_BASE },
+#ifdef CONFIG_AM43XX
+ { 4, AM33XX_GPIO4_BASE },
+ { 5, AM33XX_GPIO5_BASE },
#endif
+};
+U_BOOT_DEVICES(am33xx_gpios) = {
+ { "gpio_omap", &am33xx_gpio[0] },
+ { "gpio_omap", &am33xx_gpio[1] },
+ { "gpio_omap", &am33xx_gpio[2] },
+ { "gpio_omap", &am33xx_gpio[3] },
+#ifdef CONFIG_AM43XX
+ { "gpio_omap", &am33xx_gpio[4] },
+ { "gpio_omap", &am33xx_gpio[5] },
+#endif
+};
+#endif
+#endif
#ifndef CONFIG_DM_GPIO
static const struct gpio_bank gpio_bank_am33xx[] = {
reg = readl(&imx_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_LCD_MASK;
writel(reg, &imx_ccm->CCGR2);
+
+ return 0;
}
#endif
debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
debug("SRT=%d\n", ddr3_cfg->SRT);
- debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr);
/*
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
+ sun5i-a13-empire-electronix-d709.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-86vs.dtb \
sun5i-a13-inet-98v-rev2.dtb \
serial0 = &uart0;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
+ spi0 = &qspi;
};
cpus {
qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
- reg = <0x47900000 0x100>;
+ reg = <0x47900000 0x100>,
+ <0x30000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "mx66l51235l";
+ compatible = "mx66l51235l","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-cpol;
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
ethernet1 = &cpsw_emac1;
d_can0 = &dcan1;
d_can1 = &dcan2;
+ spi0 = &qspi;
};
timer {
qspi: qspi@4b300000 {
compatible = "ti,dra7xxx-qspi";
- reg = <0x4b300000 0x100>;
- reg-names = "qspi_base";
+ reg = <0x4b300000 0x100>,
+ <0x5c000000 0x4000000>,
+ <0x4a002558 0x4>;
+ reg-names = "qspi_base", "qspi_mmap",
+ "qspi_ctrlmod";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
spi-max-frequency = <48000000>;
m25p80@0 {
- compatible = "s25fl256s1";
+ compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
+ udc0 = &usb1;
};
regulator_3_3v: 3-3-v-regulator {
aliases {
ethernet0 = &gmac1;
+ udc0 = &usb1;
};
memory {
status = "okay";
u-boot,dm-pre-reloc;
};
+
+&usb1 {
+ status = "okay";
+};
aliases {
ethernet0 = &gmac0;
+ udc0 = &usb1;
};
memory {
bus-width = <8>;
u-boot,dm-pre-reloc;
};
+
+&usb1 {
+ status = "okay";
+};
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
+ udc0 = &usb1;
};
regulator_3_3v: 3-3-v-regulator {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
vqmmc-supply = <®ulator_3_3v>;
};
-&usb1 {
- status = "okay";
-};
-
&qspi {
status = "okay";
tslch-ns = <4>;
};
};
+
+&usb1 {
+ status = "okay";
+};
bootargs = "console=ttyS0,115200";
};
- aliases {
+ aliases {
ethernet0 = &gmac1;
- };
+ udc0 = &usb1;
+ };
memory {
name = "memory";
tslch-ns = <4>;
};
};
+
+&usb1 {
+ status = "okay";
+};
bootargs = "console=ttyS0,115200";
};
+ aliases {
+ udc0 = &usb1;
+ };
+
memory {
name = "memory";
device_type = "memory";
&gmac1 {
status = "okay";
phy-mode = "rgmii";
+
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
};
&i2c0 {
tslch-ns = <4>;
};
};
+
+&usb1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Empire Electronix D709 tablet";
+ compatible = "empire-electronix,d709", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ /* TODO: backlight uses axp gpio1 as enable pin */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+
+ mmccard: mmccard@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb0_vbus_pin_a {
+ allwinner,pins = "PG12";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Source commonly used by UniPhier ARM SoCs
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&intc>;
+
+ extbus: extbus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&uart_clk>;
+ };
+
+ serial1: serial@54006900 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006900 0x40>;
+ interrupts = <0 35 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&uart_clk>;
+ };
+
+ serial2: serial@54006a00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006a00 0x40>;
+ interrupts = <0 37 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&uart_clk>;
+ };
+
+ serial3: serial@54006b00 {
+ compatible = "socionext,uniphier-uart";
+ status = "disabled";
+ reg = <0x54006b00 0x40>;
+ interrupts = <0 177 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ clocks = <&uart_clk>;
+ };
+
+ system-bus-controller@58c00000 {
+ compatible = "socionext,uniphier-system-bus-controller";
+ reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
+ };
+
+ timer@60000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x60000200 0x20>;
+ interrupts = <1 11 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ timer@60000600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x60000600 0x20>;
+ interrupts = <1 13 0x104>;
+ clocks = <&arm_timer_clk>;
+ };
+
+ intc: interrupt-controller@60001000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x60001000 0x1000>,
+ <0x60000100 0x100>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ pinctrl: pinctrl@5f801000 {
+ /* specify compatible in each SoC DTSI */
+ reg = <0x5f801000 0xe00>;
+ };
+
+ nand: nand@68000000 {
+ compatible = "denali,denali-nand-dt";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ reg-names = "nand_data", "denali_reg";
+ };
+ };
+};
+
+/include/ "uniphier-pinctrl.dtsi"
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-ld4";
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
};
clock-frequency = <100000000>;
};
};
+};
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 29 4>;
- clocks = <&uart_clk>;
- clock-frequency = <36864000>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(512 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 80 4>;
- };
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- interrupts = <0 81 4>;
- };
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- interrupts = <0 82 4>;
- };
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-ld4-pinctrl",
- "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ };
+};
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <36864000>;
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial1 {
+ clock-frequency = <36864000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial2 {
+ clock-frequency = <36864000>;
+};
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
+&serial3 {
+ interrupts = <0 29 4>;
+ clock-frequency = <36864000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-ld4-pinctrl", "syscon";
+};
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-pro4";
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ next-level-cache = <&l2>;
};
};
clock-frequency = <50000000>;
};
};
+};
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 29 4>;
- clocks = <&uart_clk>;
- clock-frequency = <73728000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(768 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* i2c4 does not exist */
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* i2c4 does not exist */
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- usb2: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- interrupts = <0 80 4>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- usb3: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb3>;
- interrupts = <0 81 4>;
- };
+ usb2: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ };
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 134 4>;
- };
+ usb3: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ };
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- interrupts = <0 137 4>;
- };
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-pro4-pinctrl",
- "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
+};
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <73728000>;
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
+&serial1 {
+ clock-frequency = <73728000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial2 {
+ clock-frequency = <73728000>;
+};
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
+&serial3 {
+ clock-frequency = <73728000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+};
};
chosen {
- bootargs = "console=ttyS1,115200";
- stdout-path = &serial1;
+ stdout-path = "serial1:115200n8";
};
aliases {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-pro5";
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ next-level-cache = <&l2>;
};
};
clock-frequency = <50000000>;
};
};
+};
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 177 4>;
- clocks = <&uart_clk>;
- };
+ l3: l3-cache@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(2 * 1024 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* i2c4 does not exist */
-
- /* chip-internal connection for DMD */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* i2c4 does not exist */
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* chip-internal connection for DMD */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-pro5-pinctrl", "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
- clocks = <&arm_timer_clk>;
- };
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+ };
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <73728000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial1 {
+ clock-frequency = <73728000>;
+};
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 134 4>;
- };
+&serial2 {
+ clock-frequency = <73728000>;
+};
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
- interrupts = <0 137 4>;
- };
- };
+&serial3 {
+ clock-frequency = <73728000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-pro5-pinctrl", "syscon";
+};
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &serial0;
+ stdout-path = "serial0:115200n8";
};
aliases {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,ph1-sld8";
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
};
clock-frequency = <100000000>;
};
};
+};
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 29 4>;
- clocks = <&uart_clk>;
- clock-frequency = <80000000>;
- };
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
-
- i2c1: i2c@58480000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58480000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(256 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- /* chip-internal connection for DMD */
- i2c2: i2c@58500000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58500000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <400000>;
- };
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58580000 {
- compatible = "socionext,uniphier-i2c";
- status = "disabled";
- reg = <0x58580000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 1>;
- clocks = <&iobus_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58480000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58480000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for DMD */
+ i2c2: i2c@58500000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58500000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 43 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <400000>;
+ };
- usb0: usb@5a800100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a800100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- interrupts = <0 80 4>;
- };
+ i2c3: i2c@58580000 {
+ compatible = "socionext,uniphier-i2c";
+ status = "disabled";
+ reg = <0x58580000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&iobus_clk>;
+ clock-frequency = <100000>;
+ };
- usb1: usb@5a810100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a810100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- interrupts = <0 81 4>;
- };
+ usb0: usb@5a800100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a800100 0x100>;
+ interrupts = <0 80 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ };
- usb2: usb@5a820100 {
- compatible = "socionext,uniphier-ehci", "generic-ehci";
- status = "disabled";
- reg = <0x5a820100 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2>;
- interrupts = <0 82 4>;
- };
+ usb1: usb@5a810100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a810100 0x100>;
+ interrupts = <0 81 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,ph1-sld8-pinctrl",
- "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb2: usb@5a820100 {
+ compatible = "socionext,uniphier-ehci", "generic-ehci";
+ status = "disabled";
+ reg = <0x5a820100 0x100>;
+ interrupts = <0 82 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+ };
+};
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <80000000>;
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0x104>;
- clocks = <&arm_timer_clk>;
- };
+&serial1 {
+ clock-frequency = <80000000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial2 {
+ clock-frequency = <80000000>;
+};
- nand: nand@68000000 {
- compatible = "denali,denali-nand-dt";
- reg = <0x68000000 0x20>, <0x68100000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- };
- };
+&serial3 {
+ interrupts = <0 29 4>;
+ clock-frequency = <80000000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,ph1-sld8-pinctrl", "syscon";
+};
*/
&pinctrl {
+ pinctrl_emmc: emmc_grp {
+ groups = "emmc", "emmc_dat8";
+ function = "emmc";
+ };
+
pinctrl_i2c0: i2c0_grp {
groups = "i2c0";
function = "i2c0";
function = "i2c3";
};
+ pinctrl_sd: sd_grp {
+ groups = "sd";
+ function = "sd";
+ };
+
+ pinctrl_sd1: sd1_grp {
+ groups = "sd1";
+ function = "sd1";
+ };
+
pinctrl_uart0: uart0_grp {
groups = "uart0";
function = "uart0";
};
chosen {
- bootargs = "console=ttyS2,115200";
- stdout-path = &serial2;
+ stdout-path = "serial2:115200n8";
};
aliases {
};
chosen {
- bootargs = "console=ttyS2,115200";
- stdout-path = &serial2;
+ stdout-path = "serial2:115200n8";
};
aliases {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
+/include/ "uniphier-common32.dtsi"
/ {
compatible = "socionext,proxstream2";
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ next-level-cache = <&l2>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ next-level-cache = <&l2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ next-level-cache = <&l2>;
};
};
clock-frequency = <50000000>;
};
};
+};
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-parent = <&intc>;
-
- extbus: extbus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006800 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- serial1: serial@54006900 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006900 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- interrupts = <0 35 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- serial2: serial@54006a00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006a00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- interrupts = <0 37 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- serial3: serial@54006b00 {
- compatible = "socionext,uniphier-uart";
- status = "disabled";
- reg = <0x54006b00 0x40>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- interrupts = <0 177 4>;
- clocks = <&uart_clk>;
- clock-frequency = <88900000>;
- };
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <(1280 * 1024)>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
- i2c1: i2c@58781000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58781000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- interrupts = <0 42 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c2: i2c@58782000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58782000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- interrupts = <0 43 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c1: i2c@58781000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58781000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 42 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- i2c3: i2c@58783000 {
- compatible = "socionext,uniphier-fi2c";
- status = "disabled";
- reg = <0x58783000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- interrupts = <0 44 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
+ i2c2: i2c@58782000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58782000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ interrupts = <0 43 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for DMD */
- i2c4: i2c@58784000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58784000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ i2c3: i2c@58783000 {
+ compatible = "socionext,uniphier-fi2c";
+ status = "disabled";
+ reg = <0x58783000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 44 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
- /* chip-internal connection for STM */
- i2c5: i2c@58785000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58785000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* chip-internal connection for DMD */
+ i2c4: i2c@58784000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58784000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 45 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- /* chip-internal connection for HDMI */
- i2c6: i2c@58786000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58786000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <400000>;
- };
+ /* chip-internal connection for STM */
+ i2c5: i2c@58785000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58785000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 25 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- system-bus-controller-misc@59800000 {
- compatible = "socionext,uniphier-system-bus-controller-misc",
- "syscon";
- reg = <0x59800000 0x2000>;
- };
+ /* chip-internal connection for HDMI */
+ i2c6: i2c@58786000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58786000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 26 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <400000>;
+ };
- pinctrl: pinctrl@5f801000 {
- compatible = "socionext,proxstream2-pinctrl", "syscon";
- reg = <0x5f801000 0xe00>;
- };
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65a00000 0x100>;
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+ };
- timer@60000200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x60000200 0x20>;
- interrupts = <1 11 0xf04>;
- clocks = <&arm_timer_clk>;
- };
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-xhci", "generic-xhci";
+ status = "disabled";
+ reg = <0x65c00000 0x100>;
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+ };
+};
- timer@60000600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x60000600 0x20>;
- interrupts = <1 13 0xf04>;
- clocks = <&arm_timer_clk>;
- };
+&serial0 {
+ clock-frequency = <88900000>;
+};
- intc: interrupt-controller@60001000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x60001000 0x1000>,
- <0x60000100 0x100>;
- };
+&serial1 {
+ clock-frequency = <88900000>;
+};
- usb0: usb@65a00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65a00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
- interrupts = <0 134 4>;
- };
+&serial2 {
+ clock-frequency = <88900000>;
+};
- usb1: usb@65c00000 {
- compatible = "socionext,uniphier-xhci", "generic-xhci";
- status = "disabled";
- reg = <0x65c00000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
- interrupts = <0 137 4>;
- };
- };
+&serial3 {
+ clock-frequency = <88900000>;
};
-/include/ "uniphier-pinctrl.dtsi"
+&pinctrl {
+ compatible = "socionext,proxstream2-pinctrl", "syscon";
+};
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
+ unsigned int bmode = readl(&psrc->sbmr2);
+ /*
+ * Check for BMODE if serial downloader is enabled
+ * BOOT_MODE - see IMX6DQRM Table 8-1
+ */
+ if ((((bmode >> 24) & 0x03) == 0x01) || /* Serial Downloader */
+ (gpr10_boot && (reg == 1)))
+ return BOOT_DEVICE_UART;
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x000000FF) >> 4) {
/* EIM: See 8.5.1, Table 8-9 */
#include <asm/types.h>
/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
- MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
-#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ? \
- MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR
+#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
+
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
#endif
struct mxs_pair {
obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
endif
obj-y += rk_timer.o
-obj-y += rk_early_print.o
obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
*/
#include <common.h>
+#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3036.h>
#include <asm/arch/hardware.h>
GPIO1C2_MASK << GPIO1C2_SHIFT,
GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
- rk_uart_init((void *)DEBUG_UART_BASE);
+ debug_uart_init();
#endif
rockchip_timer_init();
sdram_init();
while (1)
;
}
+
+void hang(void)
+{
+ while (1)
+ ;
+}
+++ /dev/null
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <asm/arch/uart.h>
-#include <common.h>
-
-static struct rk_uart *uart_ptr;
-
-static void uart_wrtie_byte(char byte)
-{
- writel(byte, &uart_ptr->rbr);
- while (!(readl(&uart_ptr->lsr) & 0x40))
- ;
-}
-
-void print(char *s)
-{
- while (*s) {
- if (*s == '\n')
- uart_wrtie_byte('\r');
- uart_wrtie_byte(*s);
- s++;
- }
-}
-
-void print_hex(unsigned int n)
-{
- int i;
- int temp;
-
- uart_wrtie_byte('0');
- uart_wrtie_byte('x');
-
- for (i = 8; i > 0; i--) {
- temp = (n >> (i - 1) * 4) & 0x0f;
- if (temp < 10)
- uart_wrtie_byte((char)(temp + '0'));
- else
- uart_wrtie_byte((char)(temp - 10 + 'a'));
- }
- uart_wrtie_byte('\n');
- uart_wrtie_byte('\r');
-}
-
-/*
- * TODO: since rk3036 only 4K sram to use in SPL, for saving space,
- * we implement uart driver this way, we should convert this to use
- * ns16550 driver in future, which support DEBUG_UART in the standard way
- */
-void rk_uart_init(void *base)
-{
- uart_ptr = (struct rk_uart *)base;
- writel(0x83, &uart_ptr->lcr);
- writel(0x0d, &uart_ptr->rbr);
- writel(0x03, &uart_ptr->lcr);
-
- /* fifo enable, sfe is shadow register of FCR[0] */
- writel(0x01, &uart_ptr->sfe);
-}
config TARGET_SOCFPGA_ARRIA5
bool
+ select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_CYCLONE5
bool
+ select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+ bool
choice
prompt "Altera SOCFPGA board select"
#
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
- fpga_manager.o scan_manager.o
+ fpga_manager.o board.o
+
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
# QTS-generated config file wrappers
-obj-y += wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o
obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
wrap_sdram_config.o
CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
--- /dev/null
+/*
+ * Altera SoCFPGA common board code
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+struct dwc2_plat_otg_data socfpga_otg_data = {
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node[2], count;
+ fdt_addr_t addr;
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
+ COMPAT_ALTERA_SOCFPGA_DWC2USB,
+ node, 2);
+ if (count <= 0) /* No controller found. */
+ return 0;
+
+ addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("UDC Controller has no 'reg' property!\n");
+ return -EINVAL;
+ }
+
+ /* Patch the address from OF into the controller pdata. */
+ socfpga_otg_data.regs_otg = addr;
+
+ return dwc2_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
*/
#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
#define SYSMGR_FPGAINTF_NAND (1 << 4)
#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
-/* FIXME: This is questionable macro. */
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
- ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#else
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#endif
+
+#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
/* EMAC Group Bit definitions */
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
void v7_outer_cache_enable(void)
{
- /* disable the L2 cache */
- writel(0, &pl310->pl310_ctrl);
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
L310_AUX_CTRL_INST_PREFETCH_MASK |
L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
/*
socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
#endif
+#ifdef CONFIG_NAND_DENALI
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
+
return 0;
}
return BOOT_DEVICE_RAM;
case 0x2: /* NAND Flash (1.8V) */
case 0x3: /* NAND Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
return BOOT_DEVICE_NAND;
case 0x4: /* SD/MMC External Transceiver (1.8V) */
case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
config TEGRA_COMMON
bool "Tegra common options"
select DM
+ select DM_ETH
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
+ depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \
+ ARCH_UNIPHIER_PH1_SLD8
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
+config CMD_DDRMPHY_DUMP
+ bool "Enable dump command of DDR Multi PHY parameters"
+ depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B
+ help
+ The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
+ training; it is useful for the evaluation of DDR Multi PHY training.
+
endif
obj-y += lowlevel_init.o
obj-y += init_page_table.o
-obj-y += boards.o
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
obj-$(CONFIG_DEBUG_LL) += debug_ll.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
obj-y += cache_uniphier.o
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-y += pinctrl/ clk/
endif
obj-y += timer.o
+obj-y += boards.o
obj-y += soc_info.o
obj-y += boot-mode/
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_MPCORE_H
+#define ARCH_ARM_MPCORE_H
+
+/* Snoop Control Unit */
+#define SCU_OFFSET 0x00
+
+/* SCU Control Register */
+#define SCU_CTRL 0x00
+/* SCU Configuration Register */
+#define SCU_CONF 0x04
+/* SCU CPU Power Status Register */
+#define SCU_PWR_STATUS 0x08
+/* SCU Invalidate All Registers in Secure State */
+#define SCU_INV_ALL 0x0C
+/* SCU Filtering Start Address Register */
+#define SCU_FILTER_START 0x40
+/* SCU Filtering End Address Register */
+#define SCU_FILTER_END 0x44
+/* SCU Access Control Register */
+#define SCU_SAC 0x50
+/* SCU Non-secure Access Control Register */
+#define SCU_SNSAC 0x54
+
+/* Global Timer */
+#define GLOBAL_TIMER_OFFSET 0x200
+
+/* Global Timer Counter Registers */
+#define GTIMER_CNT_L 0x00
+#define GTIMER_CNT_H 0x04
+/* Global Timer Control Register */
+#define GTIMER_CTRL 0x08
+/* Global Timer Interrupt Status Register */
+#define GTIMER_STAT 0x0C
+/* Comparator Value Registers */
+#define GTIMER_CMP_L 0x10
+#define GTIMER_CMP_H 0x14
+/* Auto-increment Register */
+#define GTIMER_INC 0x18
+
+#endif /* ARCH_ARM_MPCORE_H */
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
*/
#include <linux/io.h>
-#include <mach/bcu-regs.h>
-#include <mach/init.h>
+
+#include "../init.h"
+#include "bcu-regs.h"
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
--- /dev/null
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define BCU_BASE 0x50080000
+
+#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
+#define BCSCR0 (BCSCR(0))
+#define BCSCR1 (BCSCR(1))
+#define BCSCR2 (BCSCR(2))
+#define BCSCR3 (BCSCR(3))
+#define BCSCR4 (BCSCR(4))
+#define BCSCR5 (BCSCR(5))
+
+#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
+#define BCIPPCCHR0 (BCIPPCCHR(0))
+#define BCIPPCCHR1 (BCIPPCCHR(1))
+#define BCIPPCCHR2 (BCIPPCCHR(2))
+#define BCIPPCCHR3 (BCIPPCCHR(3))
+#define BCIPPCCHR4 (BCIPPCCHR(4))
+#define BCIPPCCHR5 (BCIPPCCHR(5))
+
+#endif /* ARCH_BCU_REGS_H */
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_init(void)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
-#include <mach/soc_info.h>
+#include "init.h"
+#include "micro-support-card.h"
+#include "soc-info.h"
int board_early_init_f(void)
{
*/
#include <common.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
int board_early_init_r(void)
{
#include <common.h>
#include <spl.h>
+#include <libfdt.h>
#include <nand.h>
#include <linux/io.h>
#include <../drivers/mtd/nand/denali.h>
#endif
}
+struct uniphier_fdt_file {
+ const char *compatible;
+ const char *file_name;
+};
+
+static const struct uniphier_fdt_file uniphier_fdt_files[] = {
+ { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
+ { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
+ { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
+ { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
+ { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
+ { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
+ { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
+ { "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
+ { "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
+};
+
+static void uniphier_set_fdt_file(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int i;
+
+ /* lookup DTB file name based on the compatible string */
+ for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) {
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+ uniphier_fdt_files[i].compatible)) {
+ setenv("fdt_file", uniphier_fdt_files[i].file_name);
+ return;
+ }
+ }
+}
+
int board_late_init(void)
{
puts("MODE: ");
return -1;
}
+ uniphier_set_fdt_file();
+
return 0;
}
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <libfdt.h>
#include <linux/kernel.h>
-#include <mach/init.h>
+
+#include "init.h"
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
static const struct uniphier_board_data ph1_sld3_data = {
};
#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
static const struct uniphier_board_data proxstream2_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x40000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xc0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_ch2_base = 0xe0000000,
+ .dram_ch2_size = 0x20000000,
+ .dram_ch2_width = 16,
+ .dram_freq = 2133,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data ph1_ld6b_data = {
.dram_ch0_base = 0x80000000,
.dram_ch0_size = 0x40000000,
.dram_ch0_width = 32,
{ "socionext,proxstream2", &proxstream2_data, },
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- { "socionext,ph1-ld6b", &proxstream2_data, },
+ { "socionext,ph1-ld6b", &ph1_ld6b_data, },
#endif
};
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
+const struct uniphier_board_data *uniphier_get_board_param(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
- if (!fdt_node_check_compatible(fdt, 0,
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
uniphier_boards[i].compatible))
return uniphier_boards[i].param;
}
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o
+
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_DEVICE_H_
+#define _ASM_BOOT_DEVICE_H_
+
+struct boot_device_info {
+ u32 type;
+ char *info;
+};
+
+u32 ph1_sld3_boot_device(void);
+u32 ph1_ld4_boot_device(void);
+u32 ph1_pro5_boot_device(void);
+u32 proxstream2_boot_device(void);
+
+void ph1_sld3_boot_mode_show(void);
+void ph1_ld4_boot_mode_show(void);
+void ph1_pro5_boot_mode_show(void);
+void proxstream2_boot_mode_show(void);
+
+#endif /* _ASM_BOOT_DEVICE_H_ */
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sg-regs.h>
-#include <mach/sbc-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
#include <common.h>
#include <spl.h>
-#include <linux/io.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
u32 spl_boot_device(void)
{
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../sbc/sbc-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
+
+static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_LD4:
+ case SOC_UNIPHIER_PH1_PRO4:
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_ld4_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ proxstream2_boot_mode_show();
+ break;
+#endif
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ pinmon, 1, 1, do_pinmon,
+ "pin monitor",
+ ""
+);
#include <common.h>
#include <linux/io.h>
#include <asm/armv7.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_ld4_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro4_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void ph1_pro5_clk_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
void proxstream2_clk_init(void)
{
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "ddrmphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+static void __iomem *get_phy_base(int ch)
+{
+ return (void __iomem *)(0x5b830000 + ch * 0x00200000);
+}
+
+static int get_nr_ch(void)
+{
+ const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+ return bd->dram_ch2_width ? 3 : 2;
+}
+
+static int get_nr_datx8(int ch)
+{
+ unsigned int width;
+
+ const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+ switch (ch) {
+ case 0:
+ width = bd->dram_ch0_width;
+ break;
+ case 1:
+ width = bd->dram_ch1_width;
+ break;
+ default:
+ width = bd->dram_ch2_width;
+ break;
+ }
+
+ return width / 8;
+}
+
+static void print_bdl(void __iomem *reg, int n)
+{
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
+}
+
+static void dump_loop(void (*callback)(void __iomem *))
+{
+ int ch, dx, nr_ch, nr_dx;
+ void __iomem *dx_base;
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
+ nr_dx = get_nr_datx8(ch);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ printf("CH%dDX%d:", ch, dx);
+ (*callback)(dx_base);
+ dx_base += DMPHY_DX_STRIDE;
+ printf("\n");
+ }
+ }
+}
+
+static void zq_dump(void)
+{
+ int ch, zq, nr_ch, nr_zq, i;
+ void __iomem *zq_base;
+ u32 dr, pr;
+
+ printf("\n--- Impedance Data ---\n");
+ printf(" ZPD ZPU OPD OPU ZDV ODV\n");
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
+ nr_zq = 3;
+
+ for (zq = 0; zq < nr_zq; zq++) {
+ printf("CH%dZQ%d:", ch, zq);
+
+ dr = readl(zq_base + DMPHY_ZQ_DR);
+ for (i = 0; i < 4; i++) {
+ printf(FS PRINTF_FORMAT, dr & 0x7f);
+ dr >>= 7;
+ }
+
+ pr = readl(zq_base + DMPHY_ZQ_PR);
+ for (i = 0; i < 2; i++) {
+ printf(FS PRINTF_FORMAT, pr & 0xf);
+ pr >>= 4;
+ }
+
+ zq_base += DMPHY_ZQ_STRIDE;
+ printf("\n");
+ }
+ }
+}
+
+static void __wbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
+}
+
+static void wbdl_dump(void)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(void __iomem *dx_base)
+{
+ print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
+ print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
+
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
+}
+
+static void rbdl_dump(void)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
+
+ dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+static void wld_dump(void)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(void __iomem *dx_base)
+{
+ int rank;
+ u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+static void dqsgd_dump(void)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(void __iomem *dx_base)
+{
+ int i;
+ u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
+
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(void)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %p : %08x\n", \
+ ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
+
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
+ DMPHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %p : %08x\n", \
+ ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
+
+static void reg_dump(void)
+{
+ int ch, dx, nr_ch, nr_dx;
+ void __iomem *phy_base;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ nr_ch = get_nr_ch();
+
+ for (ch = 0; ch < nr_ch; ch++) {
+ phy_base = get_phy_base(ch);
+ nr_dx = get_nr_datx8(ch);
+
+ printf("== Ch%d ==\n", ch);
+ printf(" No: Name : Address : Data\n");
+
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGCR2);
+ REG_DUMP(PGCR3);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR0);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(DTPR3);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR0);
+ DX_REG_DUMP(dx, GCR1);
+ DX_REG_DUMP(dx, GCR2);
+ DX_REG_DUMP(dx, GCR3);
+ DX_REG_DUMP(dx, GTR);
+ }
+ }
+}
+
+static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd = argv[1];
+
+ if (argc == 1)
+ cmd = "all";
+
+ if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
+ zq_dump();
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump();
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump();
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump();
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump();
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump();
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddrm, 2, 1, do_ddrm,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the followings\n"
+ "ddrm zq - dump Impedance Data\n"
+ "ddrm wbdl - dump Write Bit Delay\n"
+ "ddrm rbdl - dump Read Bit Delay\n"
+ "ddrm wld - dump Write Leveling\n"
+ "ddrm dqsgd - dump DQS Gating Delay\n"
+ "ddrm mdl - dump Master Delay Line\n"
+ "ddrm reg - dump registers\n"
+);
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-/* Select either decimal or hexadecimal */
-#if 1
-#define PRINTF_FORMAT "%2d"
-#else
-#define PRINTF_FORMAT "%02x"
-#endif
-/* field separator */
-#define FS " "
-
-static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
-{
- return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
-}
-
-static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
-{
- int ch, p, dx;
- struct ddrphy __iomem *phy;
-
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- printf("CH%dP%dDX%d:", ch, p, dx);
- (*callback)(&phy->dx[dx]);
- printf("\n");
- }
- }
- }
-}
-
-static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
-
- for (i = 0; i < 10; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
-}
-
-void wbdl_dump(void)
-{
- printf("\n--- Write Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
-
- dump_loop(&__wbdl_dump);
-}
-
-static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
-
- for (i = 15; i < 24; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
-}
-
-void rbdl_dump(void)
-{
- printf("\n--- Read Bit Delay Line ---\n");
- printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
-
- dump_loop(&__rbdl_dump);
-}
-
-static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int rank;
- u32 lcdlr0 = readl(&dx->lcdlr[0]);
- u32 gtr = readl(&dx->gtr);
-
- for (rank = 0; rank < 4; rank++) {
- u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
- u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
-
- printf(FS PRINTF_FORMAT "%sT", wld,
- wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
- }
-}
-
-void wld_dump(void)
-{
- printf("\n--- Write Leveling Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
-
- dump_loop(&__wld_dump);
-}
-
-static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int rank;
- u32 lcdlr2 = readl(&dx->lcdlr[2]);
- u32 gtr = readl(&dx->gtr);
-
- for (rank = 0; rank < 4; rank++) {
- u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
- u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
-
- printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
- }
-}
-
-void dqsgd_dump(void)
-{
- printf("\n--- DQS Gating Delay ---\n");
- printf(" Rank0 Rank1 Rank2 Rank3\n");
-
- dump_loop(&__dqsgd_dump);
-}
-
-static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
- int i;
- u32 mdl = readl(&dx->mdlr);
- for (i = 0; i < 3; i++)
- printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
-}
-
-void mdl_dump(void)
-{
- printf("\n--- Master Delay Line ---\n");
- printf(" IPRD TPRD MDLD\n");
-
- dump_loop(&__mdl_dump);
-}
-
-#define REG_DUMP(x) \
- { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
- p - (u32 *)phy, #x, p, readl(p)); }
-
-void reg_dump(void)
-{
- int ch, p;
- struct ddrphy __iomem *phy;
-
- printf("\n--- DDR PHY registers ---\n");
-
- for (ch = 0; ch < NR_DDRCH; ch++) {
- for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
- printf("== Ch%d, PHY%d ==\n", ch, p);
- printf(" No: Name : Address : Data\n");
-
- phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
- }
- }
-}
-
-static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *cmd = argv[1];
-
- if (argc == 1)
- cmd = "all";
-
- if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump();
-
- if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump();
-
- if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump();
-
- if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump();
-
- if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump();
-
- if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump();
-
- return 0;
-}
-
-U_BOOT_CMD(
- ddr, 2, 1, do_ddr,
- "UniPhier DDR PHY parameters dumper",
- "- dump all of the followings\n"
- "ddr wbdl - dump Write Bit Delay\n"
- "ddr rbdl - dump Read Bit Delay\n"
- "ddr wld - dump Write Leveling\n"
- "ddr dqsgd - dump DQS Gating Delay\n"
- "ddr mdl - dump Master Delay Line\n"
- "ddr reg - dump registers\n"
-);
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mach/boot-device.h>
-#include <mach/sbc-regs.h>
-#include <mach/soc_info.h>
-
-static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
-
- switch (uniphier_get_soc_type()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- case SOC_UNIPHIER_PH1_SLD3:
- ph1_sld3_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- case SOC_UNIPHIER_PH1_LD4:
- case SOC_UNIPHIER_PH1_PRO4:
- case SOC_UNIPHIER_PH1_SLD8:
- ph1_ld4_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- case SOC_UNIPHIER_PH1_PRO5:
- ph1_pro5_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- case SOC_UNIPHIER_PROXSTREAM2:
- case SOC_UNIPHIER_PH1_LD6B:
- proxstream2_boot_mode_show();
- break;
-#endif
- default:
- break;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- pinmon, 1, 1, do_pinmon,
- "pin monitor",
- ""
-);
#include <common.h>
#include <linux/io.h>
-#include <mach/sg-regs.h>
+
+#include "sg-regs.h"
int print_cpuinfo(void)
{
case 0x2F:
puts("PH1-LD6b (MN2WS0320)");
break;
+ case 0x31:
+ puts("PH1-sLD11 ()");
+ break;
+ case 0x32:
+ puts("PH1-LD10 ()");
+ break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
}
- if (model > 1)
- printf(" model %d", model);
+ printf(" model %d", model);
printf(" (rev. %d)\n", rev);
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8253c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a82dbc0, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000800, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
- writel(0x00000000, &phy->mr3);
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
- u32 tmp;
-
- writel(0x0300c473, &phy->pgcr[1]);
- if (freq == 1333) {
- writel(0x0a806844, &phy->ptr[0]);
- writel(0x208e0124, &phy->ptr[1]);
- } else {
- writel(0x0c807d04, &phy->ptr[0]);
- writel(0x2710015E, &phy->ptr[1]);
- }
- writel(0x00083DEF, &phy->ptr[2]);
- if (freq == 1333) {
- writel(0x0f051616, &phy->ptr[3]);
- writel(0x06ae08d6, &phy->ptr[4]);
- } else {
- writel(0x12061A80, &phy->ptr[3]);
- writel(0x08027100, &phy->ptr[4]);
- }
- writel(0xF004001A, &phy->dsgcr);
-
- /* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
- tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
-
- writel(0x0000040B, &phy->dcr);
- if (freq == 1333) {
- writel(0x85589955, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a8363c0, &phy->dtpr[1]);
- else
- writel(0x1a8363c0, &phy->dtpr[1]);
- writel(0x5002c200, &phy->dtpr[2]);
- writel(0x00000b51, &phy->mr0);
- } else {
- writel(0x999cbb66, &phy->dtpr[0]);
- if (size == 1)
- writel(0x1a878400, &phy->dtpr[1]);
- else
- writel(0x1a878400, &phy->dtpr[1]);
- writel(0xa00214f8, &phy->dtpr[2]);
- writel(0x00000d71, &phy->mr0);
- }
- writel(0x00000006, &phy->mr1);
- if (freq == 1333)
- writel(0x00000290, &phy->mr2);
- else
- writel(0x00000298, &phy->mr2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, &phy->mr3);
-#else
- writel(0x00000800, &phy->mr3);
-#endif
-
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
- ;
-
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/ddrphy-regs.h>
-
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
-{
- int dx;
- u32 __iomem tmp, *p;
-
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- p = &phy->dx[dx].gcr;
-
- tmp = readl(p);
- /* Specify the rank that should be write leveled */
- tmp &= ~DXGCR_WLRKEN_MASK;
- tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
- writel(tmp, p);
- }
-
- p = &phy->dtcr;
-
- tmp = readl(p);
- /* Specify the rank used during data bit deskew and eye centering */
- tmp &= ~DTCR_DTRANK_MASK;
- tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
- /* Use Multi-Purpose Register for DQS gate training */
- tmp |= DTCR_DTMPR;
- /* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RNKEN_MASK;
- tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
- writel(tmp, p);
-}
-
-struct ddrphy_init_sequence {
- char *description;
- u32 init_flag;
- u32 done_flag;
- u32 err_flag;
-};
-
-static struct ddrphy_init_sequence init_sequence[] = {
- {
- "DRAM Initialization",
- PIR_DRAMRST | PIR_DRAMINIT,
- PGSR0_DIDONE,
- PGSR0_DIERR
- },
- {
- "Write Leveling",
- PIR_WL,
- PGSR0_WLDONE,
- PGSR0_WLERR
- },
- {
- "Read DQS Gate Training",
- PIR_QSGATE,
- PGSR0_QSGDONE,
- PGSR0_QSGERR
- },
- {
- "Write Leveling Adjustment",
- PIR_WLADJ,
- PGSR0_WLADONE,
- PGSR0_WLAERR
- },
- {
- "Read Bit Deskew",
- PIR_RDDSKW,
- PGSR0_RDDONE,
- PGSR0_RDERR
- },
- {
- "Write Bit Deskew",
- PIR_WRDSKW,
- PGSR0_WDDONE,
- PGSR0_WDERR
- },
- {
- "Read Eye Training",
- PIR_RDEYE,
- PGSR0_REDONE,
- PGSR0_REERR
- },
- {
- "Write Eye Training",
- PIR_WREYE,
- PGSR0_WEDONE,
- PGSR0_WEERR
- }
-};
-
-int ddrphy_training(struct ddrphy __iomem *phy)
-{
- int i;
- u32 pgsr0;
- u32 init_flag = PIR_INIT;
- u32 done_flag = PGSR0_IDONE;
- int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
- ulong start = get_timer(0);
-#endif
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- init_flag |= init_sequence[i].init_flag;
- done_flag |= init_sequence[i].done_flag;
- }
-
- writel(init_flag, &phy->pir);
-
- do {
- if (--timeout < 0) {
- printf("%s: error: timeout during DDR training\n",
- __func__);
- return -1;
- }
- udelay(1);
- pgsr0 = readl(&phy->pgsr[0]);
- } while ((pgsr0 & done_flag) != done_flag);
-
- for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
- if (pgsr0 & init_sequence[i].err_flag) {
- printf("%s: error: %s failed\n", __func__,
- init_sequence[i].description);
- return -1;
- }
- }
-
-#ifdef DISPLAY_ELAPSED_TIME
- printf("%s: info: elapsed time %ld msec\n", get_timer(start));
-#endif
-
- return 0;
-}
#include <linux/serial_reg.h>
#include <linux/linkage.h>
-#include <mach/bcu-regs.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "bcu/bcu-regs.h"
+#include "sc-regs.h"
+#include "sg-regs.h"
#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o \
+ ddrphy-training.o ddrphy-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o \
+ ddrphy-training.o ddrphy-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o \
+ ddrphy-training.o ddrphy-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
+
+obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "ddrphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS " "
+
+static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
+{
+ return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
+}
+
+static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
+{
+ int ch, p, dx;
+ struct ddrphy __iomem *phy;
+
+ for (ch = 0; ch < NR_DDRCH; ch++) {
+ for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+ phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ printf("CH%dP%dDX%d:", ch, p, dx);
+ (*callback)(&phy->dx[dx]);
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+
+ for (i = 0; i < 10; i++)
+ printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+ printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
+}
+
+static void wbdl_dump(void)
+{
+ printf("\n--- Write Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
+
+ dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+
+ for (i = 15; i < 24; i++)
+ printf(FS PRINTF_FORMAT, read_bdl(dx, i));
+
+ printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
+}
+
+static void rbdl_dump(void)
+{
+ printf("\n--- Read Bit Delay Line ---\n");
+ printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
+
+ dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int rank;
+ u32 lcdlr0 = readl(&dx->lcdlr[0]);
+ u32 gtr = readl(&dx->gtr);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+ u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "%sT", wld,
+ wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+ }
+}
+
+static void wld_dump(void)
+{
+ printf("\n--- Write Leveling Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int rank;
+ u32 lcdlr2 = readl(&dx->lcdlr[2]);
+ u32 gtr = readl(&dx->gtr);
+
+ for (rank = 0; rank < 4; rank++) {
+ u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+ u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+ printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+ }
+}
+
+static void dqsgd_dump(void)
+{
+ printf("\n--- DQS Gating Delay ---\n");
+ printf(" Rank0 Rank1 Rank2 Rank3\n");
+
+ dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
+{
+ int i;
+ u32 mdl = readl(&dx->mdlr);
+ for (i = 0; i < 3; i++)
+ printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(void)
+{
+ printf("\n--- Master Delay Line ---\n");
+ printf(" IPRD TPRD MDLD\n");
+
+ dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x) \
+ { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
+ p - (u32 *)phy, #x, p, readl(p)); }
+
+static void reg_dump(void)
+{
+ int ch, p;
+ struct ddrphy __iomem *phy;
+
+ printf("\n--- DDR PHY registers ---\n");
+
+ for (ch = 0; ch < NR_DDRCH; ch++) {
+ for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
+ printf("== Ch%d, PHY%d ==\n", ch, p);
+ printf(" No: Name : Address : Data\n");
+
+ phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
+
+ REG_DUMP(ridr);
+ REG_DUMP(pir);
+ REG_DUMP(pgcr[0]);
+ REG_DUMP(pgcr[1]);
+ REG_DUMP(pgsr[0]);
+ REG_DUMP(pgsr[1]);
+ REG_DUMP(pllcr);
+ REG_DUMP(ptr[0]);
+ REG_DUMP(ptr[1]);
+ REG_DUMP(ptr[2]);
+ REG_DUMP(ptr[3]);
+ REG_DUMP(ptr[4]);
+ REG_DUMP(acmdlr);
+ REG_DUMP(acbdlr);
+ REG_DUMP(dxccr);
+ REG_DUMP(dsgcr);
+ REG_DUMP(dcr);
+ REG_DUMP(dtpr[0]);
+ REG_DUMP(dtpr[1]);
+ REG_DUMP(dtpr[2]);
+ REG_DUMP(mr0);
+ REG_DUMP(mr1);
+ REG_DUMP(mr2);
+ REG_DUMP(mr3);
+ REG_DUMP(dx[0].gcr);
+ REG_DUMP(dx[0].gtr);
+ REG_DUMP(dx[1].gcr);
+ REG_DUMP(dx[1].gtr);
+ }
+ }
+}
+
+static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd = argv[1];
+
+ if (argc == 1)
+ cmd = "all";
+
+ if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+ wbdl_dump();
+
+ if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+ rbdl_dump();
+
+ if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+ wld_dump();
+
+ if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+ dqsgd_dump();
+
+ if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+ mdl_dump();
+
+ if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+ reg_dump();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddr, 2, 1, do_ddr,
+ "UniPhier DDR PHY parameters dumper",
+ "- dump all of the followings\n"
+ "ddr wbdl - dump Write Bit Delay\n"
+ "ddr rbdl - dump Read Bit Delay\n"
+ "ddr wld - dump Write Leveling\n"
+ "ddr dqsgd - dump DQS Gating Delay\n"
+ "ddr mdl - dump Master Delay Line\n"
+ "ddr reg - dump registers\n"
+);
--- /dev/null
+/*
+ * UniPhier DDR MultiPHY registers
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRMPHY_REGS_H
+#define ARCH_DDRMPHY_REGS_H
+
+#include <linux/bitops.h>
+
+#define DMPHY_SHIFT 2
+
+#define DMPHY_RIDR (0x000 << DMPHY_SHIFT)
+#define DMPHY_PIR (0x001 << DMPHY_SHIFT)
+#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define DMPHY_PIR_WL BIT(9) /* Write Leveling */
+#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT)
+#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
+#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT)
+#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT)
+#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
+#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
+#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT)
+#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT)
+#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
+#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT)
+#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
+#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT)
+#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT)
+#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT)
+#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT)
+#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT)
+#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT)
+#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT)
+#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT)
+#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT)
+#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT)
+#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT)
+#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT)
+#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT)
+#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT)
+#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT)
+#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT)
+#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT)
+#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT)
+#define DMPHY_DCR (0x022 << DMPHY_SHIFT)
+#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT)
+#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT)
+#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT)
+#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT)
+#define DMPHY_MR0 (0x027 << DMPHY_SHIFT)
+#define DMPHY_MR1 (0x028 << DMPHY_SHIFT)
+#define DMPHY_MR2 (0x029 << DMPHY_SHIFT)
+#define DMPHY_MR3 (0x02A << DMPHY_SHIFT)
+#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT)
+#define DMPHY_DTCR (0x02C << DMPHY_SHIFT)
+#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT))
+#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT)
+#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT)
+#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT)
+#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT)
+#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT)
+#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT)
+#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT)
+#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT)
+#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT)
+#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
+#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
+/* ZQ */
+#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT)
+#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT)
+#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT)
+#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT)
+#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT)
+/* DATX8 */
+#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT)
+#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT))
+#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT)
+#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT)
+#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT)
+#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT)
+#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT)
+#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT)
+#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT)
+
+#endif /* ARCH_DDRMPHY_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include "ddrphy-regs.h"
+
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8253c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a82dbc0, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000800, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include "ddrphy-regs.h"
+
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+ writel(0x00000000, &phy->mr3);
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include "ddrphy-regs.h"
+
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+ u32 tmp;
+
+ writel(0x0300c473, &phy->pgcr[1]);
+ if (freq == 1333) {
+ writel(0x0a806844, &phy->ptr[0]);
+ writel(0x208e0124, &phy->ptr[1]);
+ } else {
+ writel(0x0c807d04, &phy->ptr[0]);
+ writel(0x2710015E, &phy->ptr[1]);
+ }
+ writel(0x00083DEF, &phy->ptr[2]);
+ if (freq == 1333) {
+ writel(0x0f051616, &phy->ptr[3]);
+ writel(0x06ae08d6, &phy->ptr[4]);
+ } else {
+ writel(0x12061A80, &phy->ptr[3]);
+ writel(0x08027100, &phy->ptr[4]);
+ }
+ writel(0xF004001A, &phy->dsgcr);
+
+ /* change the value of the on-die pull-up/pull-down registors */
+ tmp = readl(&phy->dxccr);
+ tmp &= ~0x0ee0;
+ tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+ writel(tmp, &phy->dxccr);
+
+ writel(0x0000040B, &phy->dcr);
+ if (freq == 1333) {
+ writel(0x85589955, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ else
+ writel(0x1a8363c0, &phy->dtpr[1]);
+ writel(0x5002c200, &phy->dtpr[2]);
+ writel(0x00000b51, &phy->mr0);
+ } else {
+ writel(0x999cbb66, &phy->dtpr[0]);
+ if (size == 1)
+ writel(0x1a878400, &phy->dtpr[1]);
+ else
+ writel(0x1a878400, &phy->dtpr[1]);
+ writel(0xa00214f8, &phy->dtpr[2]);
+ writel(0x00000d71, &phy->mr0);
+ }
+ writel(0x00000006, &phy->mr1);
+ if (freq == 1333)
+ writel(0x00000290, &phy->mr2);
+ else
+ writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, &phy->mr3);
+#else
+ writel(0x00000800, &phy->mr3);
+#endif
+
+ while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ ;
+
+ writel(0x0300C473, &phy->pgcr[1]);
+ writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+ u32 ridr; /* Revision Identification Register */
+ u32 pir; /* PHY Initialixation Register */
+ u32 pgcr[2]; /* PHY General Configuration Register */
+ u32 pgsr[2]; /* PHY General Status Register */
+ u32 pllcr; /* PLL Control Register */
+ u32 ptr[5]; /* PHY Timing Register */
+ u32 acmdlr; /* AC Master Delay Line Register */
+ u32 acbdlr; /* AC Bit Delay Line Register */
+ u32 aciocr; /* AC I/O Configuration Register */
+ u32 dxccr; /* DATX8 Common Configuration Register */
+ u32 dsgcr; /* DDR System General Configuration Register */
+ u32 dcr; /* DRAM Configuration Register */
+ u32 dtpr[3]; /* DRAM Timing Parameters Register */
+ u32 mr0; /* Mode Register 0 */
+ u32 mr1; /* Mode Register 1 */
+ u32 mr2; /* Mode Register 2 */
+ u32 mr3; /* Mode Register 3 */
+ u32 odtcr; /* ODT Configuration Register */
+ u32 dtcr; /* Data Training Configuration Register */
+ u32 dtar[4]; /* Data Training Address Register */
+ u32 dtdr[2]; /* Data Training Data Register */
+ u32 dtedr[2]; /* Data Training Eye Data Register */
+ u32 pgcr2; /* PHY General Configuration Register 2 */
+ u32 rsv0[8]; /* Reserved */
+ u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
+ u32 rdimmcr0[2]; /* RDIMM Control Register */
+ u32 dcuar; /* DCU Address Register */
+ u32 dcudr; /* DCU Data Register */
+ u32 dcurr; /* DCU Run Register */
+ u32 dculr; /* DCU Loop Register */
+ u32 dcugcr; /* DCU General Configuration Register */
+ u32 dcutpr; /* DCU Timing Parameters Register */
+ u32 dcusr[2]; /* DCU Status Register */
+ u32 rsv1[8]; /* Reserved */
+ u32 bistrr; /* BIST Run Register */
+ u32 bistwcr; /* BIST Word Count Register */
+ u32 bistmskr[3]; /* BIST Mask Register */
+ u32 bistlsr; /* BIST LFSR Sed Register */
+ u32 bistar[3]; /* BIST Address Register */
+ u32 bistudpr; /* BIST User Data Pattern Register */
+ u32 bistgsr; /* BIST General Status Register */
+ u32 bistwer; /* BIST Word Error Register */
+ u32 bistber[4]; /* BIST Bit Error Register */
+ u32 bistwcsr; /* BIST Word Count Status Register */
+ u32 bistfwr[3]; /* BIST Fail Word Register */
+ u32 rsv2[10]; /* Reserved */
+ u32 gpr[2]; /* General Purpose Register */
+ struct ddrphy_zq { /* ZQ */
+ u32 cr[2]; /* Impedance Control Register */
+ u32 sr[2]; /* Impedance Status Register */
+ } zq[4];
+ struct ddrphy_datx8 { /* DATX8 */
+ u32 gcr; /* General Configuration Register */
+ u32 gsr[2]; /* General Status Register */
+ u32 bdlr[5]; /* Bit Delay Line Register */
+ u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
+ u32 mdlr; /* Master Delay Line Register */
+ u32 gtr; /* General Timing Register */
+ u32 gsr2; /* General Status Register 2 */
+ u32 rsv[2]; /* Reserved */
+ } dx[9];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT BIT(0) /* Initialization Trigger */
+#define PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PIR_DCAL BIT(5) /* DDL Calibration */
+#define PIR_PHYRST BIT(6) /* PHY Reset */
+#define PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PIR_WL BIT(9) /* Write Leveling */
+#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PIR_INITBYP BIT(31) /* Initialization Bypass */
+
+#define PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PGSR0_IERR BIT(16) /* Initialization Error */
+#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
+#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
+#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
+#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN (0 << 5)
+#define DXCCR_DQSRES_688_OHM (1 << 5)
+#define DXCCR_DQSRES_611_OHM (2 << 5)
+#define DXCCR_DQSRES_550_OHM (3 << 5)
+#define DXCCR_DQSRES_500_OHM (4 << 5)
+#define DXCCR_DQSRES_458_OHM (5 << 5)
+#define DXCCR_DQSRES_393_OHM (6 << 5)
+#define DXCCR_DQSRES_344_OHM (7 << 5)
+
+#define DXCCR_DQSNRES_OPEN (0 << 9)
+#define DXCCR_DQSNRES_688_OHM (1 << 9)
+#define DXCCR_DQSNRES_611_OHM (2 << 9)
+#define DXCCR_DQSNRES_550_OHM (3 << 9)
+#define DXCCR_DQSNRES_500_OHM (4 << 9)
+#define DXCCR_DQSNRES_458_OHM (5 << 9)
+#define DXCCR_DQSNRES_393_OHM (6 << 9)
+#define DXCCR_DQSNRES_344_OHM (7 << 9)
+
+#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY 2
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+#define NR_DDRPHY_PER_CH 1
+#else
+#define NR_DDRPHY_PER_CH 2
+#endif
+
+#define NR_DDRCH 2
+
+#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "ddrphy-regs.h"
+
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+{
+ int dx;
+ u32 __iomem tmp, *p;
+
+ for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ p = &phy->dx[dx].gcr;
+
+ tmp = readl(p);
+ /* Specify the rank that should be write leveled */
+ tmp &= ~DXGCR_WLRKEN_MASK;
+ tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
+ writel(tmp, p);
+ }
+
+ p = &phy->dtcr;
+
+ tmp = readl(p);
+ /* Specify the rank used during data bit deskew and eye centering */
+ tmp &= ~DTCR_DTRANK_MASK;
+ tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+ /* Use Multi-Purpose Register for DQS gate training */
+ tmp |= DTCR_DTMPR;
+ /* Specify the rank enabled for data-training */
+ tmp &= ~DTCR_RANKEN_MASK;
+ tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
+ writel(tmp, p);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence init_sequence[] = {
+ {
+ "DRAM Initialization",
+ PIR_DRAMRST | PIR_DRAMINIT,
+ PGSR0_DIDONE,
+ PGSR0_DIERR
+ },
+ {
+ "Write Leveling",
+ PIR_WL,
+ PGSR0_WLDONE,
+ PGSR0_WLERR
+ },
+ {
+ "Read DQS Gate Training",
+ PIR_QSGATE,
+ PGSR0_QSGDONE,
+ PGSR0_QSGERR
+ },
+ {
+ "Write Leveling Adjustment",
+ PIR_WLADJ,
+ PGSR0_WLADONE,
+ PGSR0_WLAERR
+ },
+ {
+ "Read Bit Deskew",
+ PIR_RDDSKW,
+ PGSR0_RDDONE,
+ PGSR0_RDERR
+ },
+ {
+ "Write Bit Deskew",
+ PIR_WRDSKW,
+ PGSR0_WDDONE,
+ PGSR0_WDERR
+ },
+ {
+ "Read Eye Training",
+ PIR_RDEYE,
+ PGSR0_REDONE,
+ PGSR0_REERR
+ },
+ {
+ "Write Eye Training",
+ PIR_WREYE,
+ PGSR0_WEDONE,
+ PGSR0_WEERR
+ }
+};
+
+int ddrphy_training(struct ddrphy __iomem *phy)
+{
+ int i;
+ u32 pgsr0;
+ u32 init_flag = PIR_INIT;
+ u32 done_flag = PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ init_flag |= init_sequence[i].init_flag;
+ done_flag |= init_sequence[i].done_flag;
+ }
+
+ writel(init_flag, &phy->pir);
+
+ do {
+ if (--timeout < 0) {
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(&phy->pgsr[0]);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
+ if (pgsr0 & init_sequence[i].err_flag) {
+ printf("%s: error: %s failed\n", __func__,
+ init_sequence[i].description);
+ return -EIO;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+ if (freq == 1333) {
+ writel(0x45990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958924, dramcont + UMC_CMDCTLB);
+ writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x27028B0A, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+ writel(0x000FF0FF, dramcont + UMC_INITCTLC);
+ writel(0x00000b51, dramcont + UMC_DRMMR0);
+ } else if (freq == 1600) {
+ writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
+ writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
+ writel(0x5101387F, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x2F030D3F, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x43030D3F, dramcont + UMC_INITCTLB);
+
+ writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+ writel(0x00000d71, dramcont + UMC_DRMMR0);
+ }
+
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+
+ if (freq == 1333)
+ writel(0x00000290, dramcont + UMC_DRMMR2);
+ else if (freq == 1600)
+ writel(0x00000298, dramcont + UMC_DRMMR2);
+
+ writel(0x00000800, dramcont + UMC_DRMMR3);
+
+ if (freq == 1333) {
+ if (size == 1)
+ writel(0x00240512, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+ writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+ } else if (freq == 1600) {
+ if (size == 1)
+ writel(0x002B0617, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x003F0617, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+ }
+
+ writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x00000003, dramcont + 0x7000);
+ writel(0x0000000f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000071, dramcont + 0x8008);
+ writel(0x0000003b, dramcont + UMC_DICGCTLA);
+ writel(0x020a0808, dramcont + UMC_DICGCTLB);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00000000, dramcont + UMC_SPCSETD);
+ writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
+{
+ if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
+ (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+ (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
+ bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000001, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x07ffffff, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+
+ writel(0x03010100, ssif_base + UMC_HDMCHSEL);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DVCCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+ writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_HDMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_HDDRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_GIORST);
+ writel(0x00000001, ssif_base + UMC_HD2RST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_DVCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_VPERST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+ writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
+ writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
+ writel(0x5101387f, dramcont + UMC_INITCTLA);
+ writel(0x43030d3f, dramcont + UMC_INITCTLB);
+ writel(0x00ff00ff, dramcont + UMC_INITCTLC);
+ writel(0x00000d71, dramcont + UMC_DRMMR0);
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+ writel(0x00000298, dramcont + UMC_DRMMR2);
+ writel(0x00000000, dramcont + UMC_DRMMR3);
+ writel(0x003f0617, dramcont + UMC_SPCCTLA);
+ writel(0x00ff0008, dramcont + UMC_SPCCTLB);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+ writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
+ writel(0x04060802, dramcont + UMC_WDATACTL_D0);
+ writel(0x04060802, dramcont + UMC_WDATACTL_D1);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x0000000f, dramcont + 0x7000);
+ writel(0x0000000f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000071, dramcont + 0x8008);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x00000000, dramcont + 0x0060);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00010000, dramcont + UMC_SPCSETD);
+ writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+ void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000103, dramcont0 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_1, 1);
+ ddrphy_training(phy0_1);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 0);
+ ddrphy_training(phy1_0);
+
+ writel(0x00000103, dramcont1 + UMC_DIOCTLA);
+
+ ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_1, 1);
+ ddrphy_training(phy1_1);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
+{
+ if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
+ (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
+ ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
+ (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
+ bd->dram_freq == 1600) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "../init.h"
+#include "ddrphy-regs.h"
+#include "umc-regs.h"
+
+static void umc_start_ssif(void __iomem *ssif_base)
+{
+ writel(0x00000000, ssif_base + 0x0000b004);
+ writel(0xffffffff, ssif_base + 0x0000c004);
+ writel(0x000fffcf, ssif_base + 0x0000c008);
+ writel(0x00000001, ssif_base + 0x0000b000);
+ writel(0x00000001, ssif_base + 0x0000c000);
+ writel(0x03010101, ssif_base + UMC_MDMCHSEL);
+ writel(0x03010100, ssif_base + UMC_DMDCHSEL);
+
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
+ writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
+
+ writel(0x00000001, ssif_base + UMC_CPURST);
+ writel(0x00000001, ssif_base + UMC_IDSRST);
+ writel(0x00000001, ssif_base + UMC_IXMRST);
+ writel(0x00000001, ssif_base + UMC_MDMRST);
+ writel(0x00000001, ssif_base + UMC_MDDRST);
+ writel(0x00000001, ssif_base + UMC_SIORST);
+ writel(0x00000001, ssif_base + UMC_VIORST);
+ writel(0x00000001, ssif_base + UMC_FRCRST);
+ writel(0x00000001, ssif_base + UMC_RGLRST);
+ writel(0x00000001, ssif_base + UMC_AIORST);
+ writel(0x00000001, ssif_base + UMC_DMDRST);
+}
+
+static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+ int size, int freq)
+{
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x55990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958944, dramcont + UMC_CMDCTLB);
+#else
+ writel(0x45990b11, dramcont + UMC_CMDCTLA);
+ writel(0x16958924, dramcont + UMC_CMDCTLB);
+#endif
+
+ writel(0x5101046A, dramcont + UMC_INITCTLA);
+
+ if (size == 1)
+ writel(0x27028B0A, dramcont + UMC_INITCTLB);
+ else if (size == 2)
+ writel(0x38028B0A, dramcont + UMC_INITCTLB);
+
+ writel(0x00FF00FF, dramcont + UMC_INITCTLC);
+ writel(0x00000b51, dramcont + UMC_DRMMR0);
+ writel(0x00000006, dramcont + UMC_DRMMR1);
+ writel(0x00000290, dramcont + UMC_DRMMR2);
+
+#ifdef CONFIG_DDR_STANDARD
+ writel(0x00000000, dramcont + UMC_DRMMR3);
+#else
+ writel(0x00000800, dramcont + UMC_DRMMR3);
+#endif
+
+ if (size == 1)
+ writel(0x00240512, dramcont + UMC_SPCCTLA);
+ else if (size == 2)
+ writel(0x00350512, dramcont + UMC_SPCCTLA);
+
+ writel(0x00ff0006, dramcont + UMC_SPCCTLB);
+ writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
+ writel(0x04060806, dramcont + UMC_WDATACTL_D0);
+ writel(0x04a02000, dramcont + UMC_DATASET);
+ writel(0x00000000, ca_base + 0x2300);
+ writel(0x00400020, dramcont + UMC_DCCGCTL);
+ writel(0x00000003, dramcont + 0x7000);
+ writel(0x0000004f, dramcont + 0x8000);
+ writel(0x000000c3, dramcont + 0x8004);
+ writel(0x00000077, dramcont + 0x8008);
+ writel(0x0000003b, dramcont + UMC_DICGCTLA);
+ writel(0x020a0808, dramcont + UMC_DICGCTLB);
+ writel(0x00000004, dramcont + UMC_FLOWCTLG);
+ writel(0x80000201, ca_base + 0xc20);
+ writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
+ writel(0x00200000, dramcont + UMC_FLOWCTLB);
+ writel(0x00004444, dramcont + UMC_FLOWCTLC);
+ writel(0x200a0a00, dramcont + UMC_SPCSETB);
+ writel(0x00000000, dramcont + UMC_SPCSETD);
+ writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+}
+
+static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+{
+ void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
+ void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
+ void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
+ void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
+ void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+ void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+ void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+
+ umc_dram_init_start(dramcont0);
+ umc_dram_init_start(dramcont1);
+ umc_dram_init_poll(dramcont0);
+ umc_dram_init_poll(dramcont1);
+
+ writel(0x00000101, dramcont0 + UMC_DIOCTLA);
+
+ ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
+
+ ddrphy_prepare_training(phy0_0, 0);
+ ddrphy_training(phy0_0);
+
+ writel(0x00000101, dramcont1 + UMC_DIOCTLA);
+
+ ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
+
+ ddrphy_prepare_training(phy1_0, 1);
+ ddrphy_training(phy1_0);
+
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+
+ umc_start_ssif(ssif_base);
+
+ return 0;
+}
+
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
+{
+ if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
+ (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+ bd->dram_freq == 1333 &&
+ bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * based on commit 21b6e480f92ccc38fe0502e3116411d6509d3bf2 of Diag by:
+ * Copyright (C) 2015 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "../soc-info.h"
+#include "ddrmphy-regs.h"
+
+/* UM registers */
+#define UMC_MBUS0 0x00080004
+#define UMC_MBUS1 0x00081004
+#define UMC_MBUS2 0x00082004
+#define UMC_MBUS3 0x00083004
+
+/* UD registers */
+#define UMC_BITPERPIXELMODE_D0 0x010
+#define UMC_PAIR1DOFF_D0 0x054
+
+/* DC registers */
+#define UMC_INITSET 0x014
+#define UMC_INITSTAT 0x018
+#define UMC_CMDCTLA 0x000
+#define UMC_CMDCTLB 0x004
+#define UMC_SPCCTLA 0x030
+#define UMC_SPCCTLB 0x034
+#define UMC_SPCSETB 0x03c
+#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
+#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
+#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
+#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
+#define UMC_ACSSETA 0x060
+#define UMC_FLOWCTLA 0x400
+#define UMC_FLOWCTLB 0x404
+#define UMC_FLOWCTLC 0x408
+#define UMC_FLOWCTLG 0x508
+#define UMC_FLOWCTLOB0 0x520
+#define UMC_FLOWCTLOB1 0x524
+#define UMC_RDATACTL_D0 0x600
+#define UMC_RDATACTL_RADLTY_SHIFT 4
+#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
+#define UMC_RDATACTL_RAD2LTY_SHIFT 8
+#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
+#define UMC_WDATACTL_D0 0x604
+#define UMC_RDATACTL_D1 0x608
+#define UMC_WDATACTL_D1 0x60c
+#define UMC_DATASET 0x610
+#define UMC_RESPCTL 0x624
+#define UMC_DCCGCTL 0x720
+#define UMC_ERRMASKA 0x958
+#define UMC_ERRMASKB 0x95c
+#define UMC_BSICMAPSET 0x988
+#define UMC_DIOCTLA 0xc00
+#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
+#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
+#define UMC_DFICUPDCTLA 0xc20
+
+enum dram_freq {
+ FREQ_1866M,
+ FREQ_2133M,
+ FREQ_NR,
+};
+
+enum dram_size {
+ SIZE_0,
+ SIZE_512M,
+ SIZE_1G,
+ SIZE_NR,
+};
+
+static u32 ddrphy_pgcr2[FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
+static u32 ddrphy_ptr0[FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
+static u32 ddrphy_ptr1[FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
+static u32 ddrphy_ptr3[FREQ_NR] = {0x15171e45, 0x18182357};
+static u32 ddrphy_ptr4[FREQ_NR] = {0x0e9ad8e9, 0x10b34157};
+static u32 ddrphy_dtpr0[FREQ_NR] = {0x35a00d88, 0x39e40e88};
+static u32 ddrphy_dtpr1[FREQ_NR] = {0x2288cc2c, 0x228a04d0};
+static u32 ddrphy_dtpr2[FREQ_NR] = {0x50005e00, 0x50006a00};
+static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89};
+static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125};
+static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8};
+
+static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722};
+/*
+ * The ch2 is a different generation UMC core.
+ * The register spec is different, unfortunately.
+ */
+static u32 umc_cmdctlb_ch01[FREQ_NR] = {0x13E87C44, 0x18F88C44};
+static u32 umc_cmdctlb_ch2[FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
+static u32 umc_spcctla[FREQ_NR][SIZE_NR] = {
+ {0x00000000, 0x004A071D, 0x0078071D},
+ {0x00000000, 0x0055081E, 0x0089081E},
+};
+
+static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
+/* The ch2 is different for some reason only hardware guys know... */
+static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
+static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
+
+/* DDR multiPHY */
+static inline int ddrphy_get_rank(int dx)
+{
+ return dx / 2;
+}
+
+static void ddrphy_fifo_reset(void __iomem *phy_base)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR0);
+ tmp &= ~DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+
+ tmp |= DMPHY_PGCR0_PHYFRST;
+ writel(tmp, phy_base + DMPHY_PGCR0);
+
+ udelay(1);
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + DMPHY_PGCR1);
+
+ if (enable)
+ tmp &= ~DMPHY_PGCR1_INHVT;
+ else
+ tmp |= DMPHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + DMPHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
+{
+ int dx;
+ u32 lcdlr1, rdqsd;
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqsd = clamp(rdqsd + step, 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
+ writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
+ readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
+{
+ void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
+ const int nr_dx = width / 8;
+ int dx, rank;
+ u32 gtr;
+ int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
+
+ for (dx = 0; dx < nr_dx; dx++) {
+ gtr = readl(dx_base + DMPHY_DX_GTR);
+ for (rank = 0; rank < 4; rank++) {
+ dgsl = gtr & 0x7;
+ /* if dgsl is zero, this rank was not trained. skip. */
+ if (dgsl) {
+ dgsl_min = min(dgsl_min, dgsl);
+ dgsl_max = max(dgsl_max, dgsl);
+ }
+ gtr >>= 3;
+ }
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ if (dgsl_min != dgsl_max)
+ printf("DQS Gateing System Latencies are not all leveled.\n");
+
+ return dgsl_max;
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
+{
+ u32 tmp;
+ void __iomem *zq_base, *dx_base;
+ int zq, dx;
+ int nr_dx;
+
+ nr_dx = width / 8;
+
+ writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
+ /*
+ * Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
+ * to avoid read error issue.
+ */
+ writel(0x07d81e37, phy_base + DMPHY_PGCR0);
+ writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
+
+ tmp = ddrphy_pgcr2[freq];
+ if (width >= 32)
+ tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
+ writel(tmp, phy_base + DMPHY_PGCR2);
+
+ writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
+ writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
+ writel(0x00083def, phy_base + DMPHY_PTR2);
+ writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
+ writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
+
+ writel(0x55555555, phy_base + DMPHY_ACIOCR1);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR2);
+ writel(0x55555555, phy_base + DMPHY_ACIOCR3);
+ writel(0x00000000, phy_base + DMPHY_ACIOCR4);
+ writel(0x00000055, phy_base + DMPHY_ACIOCR5);
+ writel(0x00181aa4, phy_base + DMPHY_DXCCR);
+
+ writel(0x0024641e, phy_base + DMPHY_DSGCR);
+ writel(0x0000040b, phy_base + DMPHY_DCR);
+ writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
+ writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
+ writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
+ writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
+ writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
+ writel(0x00000006, phy_base + DMPHY_MR1);
+ writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
+ writel(0x00000000, phy_base + DMPHY_MR3);
+
+ tmp = 0;
+ for (dx = 0; dx < nr_dx; dx++)
+ tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
+ writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
+
+ writel(0x00000000, phy_base + DMPHY_DTAR0);
+ writel(0x00000008, phy_base + DMPHY_DTAR1);
+ writel(0x00000010, phy_base + DMPHY_DTAR2);
+ writel(0x00000018, phy_base + DMPHY_DTAR3);
+ writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
+ writel(0x7788bb44, phy_base + DMPHY_DTDR1);
+
+ /* impedance control settings */
+ writel(0x04048900, phy_base + DMPHY_ZQCR);
+
+ zq_base = phy_base + DMPHY_ZQ_BASE;
+ for (zq = 0; zq < 4; zq++) {
+ /*
+ * board-dependent
+ * PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
+ */
+ writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
+ zq_base += DMPHY_ZQ_STRIDE;
+ }
+
+ /* DATX8 settings */
+ dx_base = phy_base + DMPHY_DX_BASE;
+ for (dx = 0; dx < 4; dx++) {
+ tmp = readl(dx_base + DMPHY_DX_GCR0);
+ tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
+ tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
+ DMPHY_DX_GCR0_WLRKEN_MASK;
+ writel(tmp, dx_base + DMPHY_DX_GCR0);
+
+ writel(0x00000000, dx_base + DMPHY_DX_GCR1);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR2);
+ writel(0x00000000, dx_base + DMPHY_DX_GCR3);
+ dx_base += DMPHY_DX_STRIDE;
+ }
+
+ while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
+ cpu_relax();
+
+ ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
+}
+
+struct ddrphy_init_sequence {
+ char *description;
+ u32 init_flag;
+ u32 done_flag;
+ u32 err_flag;
+};
+
+static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
+ {
+ "Impedance Calibration",
+ DMPHY_PIR_ZCAL,
+ DMPHY_PGSR0_ZCDONE,
+ DMPHY_PGSR0_ZCERR,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence dram_init_sequence[] = {
+ {
+ "DRAM Initialization",
+ DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
+ DMPHY_PGSR0_DIDONE,
+ 0,
+ },
+ { /* sentinel */ }
+};
+
+static const struct ddrphy_init_sequence training_sequence[] = {
+ {
+ "Write Leveling",
+ DMPHY_PIR_WL,
+ DMPHY_PGSR0_WLDONE,
+ DMPHY_PGSR0_WLERR,
+ },
+ {
+ "Read DQS Gate Training",
+ DMPHY_PIR_QSGATE,
+ DMPHY_PGSR0_QSGDONE,
+ DMPHY_PGSR0_QSGERR,
+ },
+ {
+ "Write Leveling Adjustment",
+ DMPHY_PIR_WLADJ,
+ DMPHY_PGSR0_WLADONE,
+ DMPHY_PGSR0_WLAERR,
+ },
+ {
+ "Read Bit Deskew",
+ DMPHY_PIR_RDDSKW,
+ DMPHY_PGSR0_RDDONE,
+ DMPHY_PGSR0_RDERR,
+ },
+ {
+ "Write Bit Deskew",
+ DMPHY_PIR_WRDSKW,
+ DMPHY_PGSR0_WDDONE,
+ DMPHY_PGSR0_WDERR,
+ },
+ {
+ "Read Eye Training",
+ DMPHY_PIR_RDEYE,
+ DMPHY_PGSR0_REDONE,
+ DMPHY_PGSR0_REERR,
+ },
+ {
+ "Write Eye Training",
+ DMPHY_PIR_WREYE,
+ DMPHY_PGSR0_WEDONE,
+ DMPHY_PGSR0_WEERR,
+ },
+ { /* sentinel */ }
+};
+
+static int __ddrphy_training(void __iomem *phy_base,
+ const struct ddrphy_init_sequence *seq)
+{
+ const struct ddrphy_init_sequence *s;
+ u32 pgsr0;
+ u32 init_flag = DMPHY_PIR_INIT;
+ u32 done_flag = DMPHY_PGSR0_IDONE;
+ int timeout = 50000; /* 50 msec is long enough */
+#ifdef DISPLAY_ELAPSED_TIME
+ ulong start = get_timer(0);
+#endif
+
+ for (s = seq; s->description; s++) {
+ init_flag |= s->init_flag;
+ done_flag |= s->done_flag;
+ }
+
+ writel(init_flag, phy_base + DMPHY_PIR);
+
+ do {
+ if (--timeout < 0) {
+ printf("%s: error: timeout during DDR training\n",
+ __func__);
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ pgsr0 = readl(phy_base + DMPHY_PGSR0);
+ } while ((pgsr0 & done_flag) != done_flag);
+
+ for (s = seq; s->description; s++) {
+ if (pgsr0 & s->err_flag) {
+ printf("%s: error: %s failed\n", __func__,
+ s->description);
+ return -EIO;
+ }
+ }
+
+#ifdef DISPLAY_ELAPSED_TIME
+ printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#endif
+
+ return 0;
+}
+
+static int ddrphy_impedance_calibration(void __iomem *phy_base)
+{
+ int ret;
+ u32 tmp;
+
+ ret = __ddrphy_training(phy_base, impedance_calibration_sequence);
+ if (ret)
+ return ret;
+
+ /*
+ * Because of a hardware bug, IDONE flag is set when the first ZQ block
+ * is calibrated. The flag does not guarantee the completion for all
+ * the ZQ blocks. Wait a little more just in case.
+ */
+ udelay(1);
+
+ /* reflect ZQ settings and enable average algorithm*/
+ tmp = readl(phy_base + DMPHY_ZQCR);
+ tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+ tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
+ tmp |= DMPHY_ZQCR_AVGEN;
+ writel(tmp, phy_base + DMPHY_ZQCR);
+
+ return 0;
+}
+
+static int ddrphy_dram_init(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, dram_init_sequence);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+ return __ddrphy_training(phy_base, training_sequence);
+}
+
+/* UMC */
+static void umc_set_system_latency(void __iomem *umc_dc_base, int phy_latency)
+{
+ u32 val;
+ int latency;
+
+ val = readl(umc_dc_base + UMC_RDATACTL_D0);
+ latency = (val & UMC_RDATACTL_RADLTY_MASK) >> UMC_RDATACTL_RADLTY_SHIFT;
+ latency += (val & UMC_RDATACTL_RAD2LTY_MASK) >>
+ UMC_RDATACTL_RAD2LTY_SHIFT;
+ /*
+ * UMC works at the half clock rate of the PHY.
+ * The LSB of latency is ignored
+ */
+ latency += phy_latency & ~1;
+
+ val &= ~(UMC_RDATACTL_RADLTY_MASK | UMC_RDATACTL_RAD2LTY_MASK);
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, umc_dc_base + UMC_RDATACTL_D0);
+ writel(val, umc_dc_base + UMC_RDATACTL_D1);
+
+ readl(umc_dc_base + UMC_RDATACTL_D1); /* relax */
+}
+
+/* enable/disable auto refresh */
+void umc_refresh_ctrl(void __iomem *umc_dc_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(umc_dc_base + UMC_SPCSETB);
+ tmp &= ~UMC_SPCSETB_AREFMD_MASK;
+
+ if (enable)
+ tmp |= UMC_SPCSETB_AREFMD_ARB;
+ else
+ tmp |= UMC_SPCSETB_AREFMD_REG;
+
+ writel(tmp, umc_dc_base + UMC_SPCSETB);
+ udelay(1);
+}
+
+static void umc_ud_init(void __iomem *umc_base, int ch)
+{
+ writel(0x00000003, umc_base + UMC_BITPERPIXELMODE_D0);
+
+ if (ch == 2)
+ writel(0x00000033, umc_base + UMC_PAIR1DOFF_D0);
+}
+
+static void umc_dc_init(void __iomem *umc_dc_base, enum dram_freq freq,
+ enum dram_size size, int ch, int width)
+{
+ int latency;
+ u32 val;
+
+ writel(umc_cmdctla[freq], umc_dc_base + UMC_CMDCTLA);
+
+ writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq],
+ umc_dc_base + UMC_CMDCTLB);
+
+ writel(umc_spcctla[freq][size / (width / 16)],
+ umc_dc_base + UMC_SPCCTLA);
+ writel(umc_spcctlb[freq], umc_dc_base + UMC_SPCCTLB);
+
+ val = 0x000e000e;
+ latency = 12;
+ /* ES2 inserted one more FF to the logic. */
+ if (uniphier_get_soc_model() >= 2)
+ latency += 2;
+
+ if (latency > 0xf) {
+ val |= 0xf << UMC_RDATACTL_RADLTY_SHIFT;
+ val |= (latency - 0xf) << UMC_RDATACTL_RAD2LTY_SHIFT;
+ } else {
+ val |= latency << UMC_RDATACTL_RADLTY_SHIFT;
+ }
+
+ writel(val, umc_dc_base + UMC_RDATACTL_D0);
+ if (width >= 32)
+ writel(val, umc_dc_base + UMC_RDATACTL_D1);
+
+ writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D0);
+ if (width >= 32)
+ writel(0x04060A02, umc_dc_base + UMC_WDATACTL_D1);
+ writel(0x04000000, umc_dc_base + UMC_DATASET);
+ writel(0x00400020, umc_dc_base + UMC_DCCGCTL);
+ writel(0x00000084, umc_dc_base + UMC_FLOWCTLG);
+ writel(0x00000000, umc_dc_base + UMC_ACSSETA);
+
+ writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq],
+ umc_dc_base + UMC_FLOWCTLA);
+
+ writel(0x00004400, umc_dc_base + UMC_FLOWCTLC);
+ writel(0x200A0A00, umc_dc_base + UMC_SPCSETB);
+ writel(0x00000520, umc_dc_base + UMC_DFICUPDCTLA);
+ writel(0x0000000D, umc_dc_base + UMC_RESPCTL);
+
+ if (ch != 2) {
+ writel(0x00202000, umc_dc_base + UMC_FLOWCTLB);
+ writel(0xFDBFFFFF, umc_dc_base + UMC_FLOWCTLOB0);
+ writel(0xFFFFFFFF, umc_dc_base + UMC_FLOWCTLOB1);
+ writel(0x00080700, umc_dc_base + UMC_BSICMAPSET);
+ } else {
+ writel(0x00200000, umc_dc_base + UMC_FLOWCTLB);
+ writel(0x00000000, umc_dc_base + UMC_BSICMAPSET);
+ }
+
+ writel(0x00000000, umc_dc_base + UMC_ERRMASKA);
+ writel(0x00000000, umc_dc_base + UMC_ERRMASKB);
+}
+
+static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch,
+ enum dram_size size, int width)
+{
+ void __iomem *umc_dc_base = umc_base + 0x00011000;
+ void __iomem *phy_base = umc_base + 0x00030000;
+ int ret;
+
+ writel(0x00000002, umc_dc_base + UMC_INITSET);
+ while (readl(umc_dc_base + UMC_INITSTAT) & BIT(2))
+ cpu_relax();
+
+ /* deassert PHY reset signals */
+ writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+ umc_dc_base + UMC_DIOCTLA);
+
+ ddrphy_init(phy_base, freq, width);
+
+ ret = ddrphy_impedance_calibration(phy_base);
+ if (ret)
+ return ret;
+
+ ddrphy_dram_init(phy_base);
+ if (ret)
+ return ret;
+
+ umc_dc_init(umc_dc_base, freq, size, ch, width);
+
+ umc_ud_init(umc_base, ch);
+
+ if (size) {
+ ret = ddrphy_training(phy_base);
+ if (ret)
+ return ret;
+ }
+
+ udelay(1);
+
+ /* match the system latency between UMC and PHY */
+ umc_set_system_latency(umc_dc_base,
+ ddrphy_get_system_latency(phy_base, width));
+
+ udelay(1);
+
+ /* stop auto refresh before clearing FIFO in PHY */
+ umc_refresh_ctrl(umc_dc_base, 0);
+ ddrphy_fifo_reset(phy_base);
+ umc_refresh_ctrl(umc_dc_base, 1);
+
+ udelay(10);
+
+ return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+ writel(0x000000ff, um_base + UMC_MBUS0);
+ writel(0x000000ff, um_base + UMC_MBUS1);
+ writel(0x000000ff, um_base + UMC_MBUS2);
+ writel(0x000000ff, um_base + UMC_MBUS3);
+}
+
+int proxstream2_umc_init(const struct uniphier_board_data *bd)
+{
+ void __iomem *um_base = (void __iomem *)0x5b600000;
+ void __iomem *umc_ch0_base = (void __iomem *)0x5b800000;
+ void __iomem *umc_ch1_base = (void __iomem *)0x5ba00000;
+ void __iomem *umc_ch2_base = (void __iomem *)0x5bc00000;
+ enum dram_freq freq;
+ int ret;
+
+ switch (bd->dram_freq) {
+ case 1866:
+ freq = FREQ_1866M;
+ break;
+ case 2133:
+ freq = FREQ_2133M;
+ break;
+ default:
+ printf("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+ return -EINVAL;
+ }
+
+ ret = umc_init(umc_ch0_base, freq, 0, bd->dram_ch0_size / SZ_256M,
+ bd->dram_ch0_width);
+ if (ret) {
+ printf("failed to initialize UMC ch0\n");
+ return ret;
+ }
+
+ ret = umc_init(umc_ch1_base, freq, 1, bd->dram_ch1_size / SZ_256M,
+ bd->dram_ch1_width);
+ if (ret) {
+ printf("failed to initialize UMC ch1\n");
+ return ret;
+ }
+
+ ret = umc_init(umc_ch2_base, freq, 2, bd->dram_ch2_size / SZ_256M,
+ bd->dram_ch2_width);
+ if (ret) {
+ printf("failed to initialize UMC ch2\n");
+ return ret;
+ }
+
+ um_init(um_base);
+
+ return 0;
+}
--- /dev/null
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE 0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE UMC_BASE
+
+#define UMC_CPURST 0x00000700
+#define UMC_IDSRST 0x0000070C
+#define UMC_IXMRST 0x00000714
+#define UMC_HDMRST 0x00000718
+#define UMC_MDMRST 0x0000071C
+#define UMC_HDDRST 0x00000720
+#define UMC_MDDRST 0x00000724
+#define UMC_SIORST 0x00000728
+#define UMC_GIORST 0x0000072C
+#define UMC_HD2RST 0x00000734
+#define UMC_VIORST 0x0000073C
+#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST 0x00000748 /* Pro4 */
+#define UMC_RGLRST 0x00000750
+#define UMC_VPERST 0x00000758
+#define UMC_AIORST 0x00000764
+#define UMC_DMDRST 0x00000770
+
+#define UMC_HDMCHSEL 0x00000898
+#define UMC_MDMCHSEL 0x0000089C
+#define UMC_DVCCHSEL 0x000008C8
+#define UMC_DMDCHSEL 0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH 0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
+#define UMC_CLKEN_SSIF_WC 0x0000C07C
+#define UMC_CLKEN_SSIF_RC 0x0000C080
+#define UMC_CLKEN_SSIF_DST 0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA 0x00000000
+#define UMC_CMDCTLB 0x00000004
+#define UMC_INITCTLA 0x00000008
+#define UMC_INITCTLB 0x0000000C
+#define UMC_INITCTLC 0x00000010
+#define UMC_INITSET 0x00000014
+#define UMC_INITSTAT 0x00000018
+#define UMC_DRMMR0 0x0000001C
+#define UMC_DRMMR1 0x00000020
+#define UMC_DRMMR2 0x00000024
+#define UMC_DRMMR3 0x00000028
+#define UMC_SPCCTLA 0x00000030
+#define UMC_SPCCTLB 0x00000034
+#define UMC_SPCSETA 0x00000038
+#define UMC_SPCSETB 0x0000003C
+#define UMC_SPCSETC 0x00000040
+#define UMC_SPCSETD 0x00000044
+#define UMC_SPCSTATA 0x00000050
+#define UMC_SPCSTATB 0x00000054
+#define UMC_SPCSTATC 0x00000058
+#define UMC_ACSSETA 0x00000060
+#define UMC_FLOWCTLA 0x00000400
+#define UMC_FLOWCTLB 0x00000404
+#define UMC_FLOWCTLC 0x00000408
+#define UMC_FLOWCTLG 0x00000508
+#define UMC_RDATACTL_D0 0x00000600
+#define UMC_WDATACTL_D0 0x00000604
+#define UMC_RDATACTL_D1 0x00000608
+#define UMC_WDATACTL_D1 0x0000060C
+#define UMC_DATASET 0x00000610
+#define UMC_DCCGCTL 0x00000720
+#define UMC_DICGCTLA 0x00000724
+#define UMC_DICGCTLB 0x00000728
+#define UMC_DIOCTLA 0x00000C00
+#define UMC_DFICUPDCTLA 0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+ u32 nmask = ~mask;
+ u32 data;
+ do {
+ data = readl(address) & nmask;
+ } while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+ writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+ while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+ ;
+}
+
+#endif
+
+#endif
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
+++ /dev/null
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_ARM_MPCORE_H
-#define ARCH_ARM_MPCORE_H
-
-/* Snoop Control Unit */
-#define SCU_OFFSET 0x00
-
-/* SCU Control Register */
-#define SCU_CTRL 0x00
-/* SCU Configuration Register */
-#define SCU_CONF 0x04
-/* SCU CPU Power Status Register */
-#define SCU_PWR_STATUS 0x08
-/* SCU Invalidate All Registers in Secure State */
-#define SCU_INV_ALL 0x0C
-/* SCU Filtering Start Address Register */
-#define SCU_FILTER_START 0x40
-/* SCU Filtering End Address Register */
-#define SCU_FILTER_END 0x44
-/* SCU Access Control Register */
-#define SCU_SAC 0x50
-/* SCU Non-secure Access Control Register */
-#define SCU_SNSAC 0x54
-
-/* Global Timer */
-#define GLOBAL_TIMER_OFFSET 0x200
-
-/* Global Timer Counter Registers */
-#define GTIMER_CNT_L 0x00
-#define GTIMER_CNT_H 0x04
-/* Global Timer Control Register */
-#define GTIMER_CTRL 0x08
-/* Global Timer Interrupt Status Register */
-#define GTIMER_STAT 0x0C
-/* Comparator Value Registers */
-#define GTIMER_CMP_L 0x10
-#define GTIMER_CMP_H 0x14
-/* Auto-increment Register */
-#define GTIMER_INC 0x18
-
-#endif /* ARCH_ARM_MPCORE_H */
+++ /dev/null
-/*
- * UniPhier BCU (Bus Control Unit) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BCU_REGS_H
-#define ARCH_BCU_REGS_H
-
-#define BCU_BASE 0x50080000
-
-#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
-#define BCSCR0 (BCSCR(0))
-#define BCSCR1 (BCSCR(1))
-#define BCSCR2 (BCSCR(2))
-#define BCSCR3 (BCSCR(3))
-#define BCSCR4 (BCSCR(4))
-#define BCSCR5 (BCSCR(5))
-
-#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
-#define BCIPPCCHR0 (BCIPPCCHR(0))
-#define BCIPPCCHR1 (BCIPPCCHR(1))
-#define BCIPPCCHR2 (BCIPPCCHR(2))
-#define BCIPPCCHR3 (BCIPPCCHR(3))
-#define BCIPPCCHR4 (BCIPPCCHR(4))
-#define BCIPPCCHR5 (BCIPPCCHR(5))
-
-#endif /* ARCH_BCU_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_BOOT_DEVICE_H_
-#define _ASM_BOOT_DEVICE_H_
-
-struct boot_device_info {
- u32 type;
- char *info;
-};
-
-u32 ph1_sld3_boot_device(void);
-u32 ph1_ld4_boot_device(void);
-u32 ph1_pro5_boot_device(void);
-u32 proxstream2_boot_device(void);
-
-void ph1_sld3_boot_mode_show(void);
-void ph1_ld4_boot_mode_show(void);
-void ph1_pro5_boot_mode_show(void);
-void proxstream2_boot_mode_show(void);
-
-#endif /* _ASM_BOOT_DEVICE_H_ */
+++ /dev/null
-/*
- * UniPhier DDR PHY registers
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_DDRPHY_REGS_H
-#define ARCH_DDRPHY_REGS_H
-
-#include <linux/compiler.h>
-
-#ifndef __ASSEMBLY__
-
-struct ddrphy {
- u32 ridr; /* Revision Identification Register */
- u32 pir; /* PHY Initialixation Register */
- u32 pgcr[2]; /* PHY General Configuration Register */
- u32 pgsr[2]; /* PHY General Status Register */
- u32 pllcr; /* PLL Control Register */
- u32 ptr[5]; /* PHY Timing Register */
- u32 acmdlr; /* AC Master Delay Line Register */
- u32 acbdlr; /* AC Bit Delay Line Register */
- u32 aciocr; /* AC I/O Configuration Register */
- u32 dxccr; /* DATX8 Common Configuration Register */
- u32 dsgcr; /* DDR System General Configuration Register */
- u32 dcr; /* DRAM Configuration Register */
- u32 dtpr[3]; /* DRAM Timing Parameters Register */
- u32 mr0; /* Mode Register 0 */
- u32 mr1; /* Mode Register 1 */
- u32 mr2; /* Mode Register 2 */
- u32 mr3; /* Mode Register 3 */
- u32 odtcr; /* ODT Configuration Register */
- u32 dtcr; /* Data Training Configuration Register */
- u32 dtar[4]; /* Data Training Address Register */
- u32 dtdr[2]; /* Data Training Data Register */
- u32 dtedr[2]; /* Data Training Eye Data Register */
- u32 pgcr2; /* PHY General Configuration Register 2 */
- u32 rsv0[8]; /* Reserved */
- u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
- u32 rdimmcr0[2]; /* RDIMM Control Register */
- u32 dcuar; /* DCU Address Register */
- u32 dcudr; /* DCU Data Register */
- u32 dcurr; /* DCU Run Register */
- u32 dculr; /* DCU Loop Register */
- u32 dcugcr; /* DCU General Configuration Register */
- u32 dcutpr; /* DCU Timing Parameters Register */
- u32 dcusr[2]; /* DCU Status Register */
- u32 rsv1[8]; /* Reserved */
- u32 bistrr; /* BIST Run Register */
- u32 bistwcr; /* BIST Word Count Register */
- u32 bistmskr[3]; /* BIST Mask Register */
- u32 bistlsr; /* BIST LFSR Sed Register */
- u32 bistar[3]; /* BIST Address Register */
- u32 bistudpr; /* BIST User Data Pattern Register */
- u32 bistgsr; /* BIST General Status Register */
- u32 bistwer; /* BIST Word Error Register */
- u32 bistber[4]; /* BIST Bit Error Register */
- u32 bistwcsr; /* BIST Word Count Status Register */
- u32 bistfwr[3]; /* BIST Fail Word Register */
- u32 rsv2[10]; /* Reserved */
- u32 gpr[2]; /* General Purpose Register */
- struct ddrphy_zq { /* ZQ */
- u32 cr[2]; /* Impedance Control Register */
- u32 sr[2]; /* Impedance Status Register */
- } zq[4];
- struct ddrphy_datx8 { /* DATX8 */
- u32 gcr; /* General Configuration Register */
- u32 gsr[2]; /* General Status Register */
- u32 bdlr[5]; /* Bit Delay Line Register */
- u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
- u32 mdlr; /* Master Delay Line Register */
- u32 gtr; /* General Timing Register */
- u32 gsr2; /* General Status Register 2 */
- u32 rsv[2]; /* Reserved */
- } dx[9];
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PIR_INIT (1 << 0) /* Initialization Trigger */
-#define PIR_ZCAL (1 << 1) /* Impedance Calibration */
-#define PIR_PLLINIT (1 << 4) /* PLL Initialization */
-#define PIR_DCAL (1 << 5) /* DDL Calibration */
-#define PIR_PHYRST (1 << 6) /* PHY Reset */
-#define PIR_DRAMRST (1 << 7) /* DRAM Reset */
-#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */
-#define PIR_WL (1 << 9) /* Write Leveling */
-#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */
-#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */
-#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */
-#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */
-#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */
-#define PIR_WREYE (1 << 15) /* Write Data Eye Training */
-#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */
-#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */
-#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */
-#define PIR_INITBYP (1 << 31) /* Initialization Bypass */
-
-#define PGSR0_IDONE (1 << 0) /* Initialization Done */
-#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */
-#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */
-#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */
-#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */
-#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */
-#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */
-#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */
-#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */
-#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */
-#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */
-#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */
-#define PGSR0_IERR (1 << 16) /* Initialization Error */
-#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */
-#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */
-#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */
-#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */
-#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */
-#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */
-#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */
-#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */
-#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */
-#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */
-#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */
-#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
-#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */
-
-#define DXCCR_DQSRES_OPEN (0 << 5)
-#define DXCCR_DQSRES_688_OHM (1 << 5)
-#define DXCCR_DQSRES_611_OHM (2 << 5)
-#define DXCCR_DQSRES_550_OHM (3 << 5)
-#define DXCCR_DQSRES_500_OHM (4 << 5)
-#define DXCCR_DQSRES_458_OHM (5 << 5)
-#define DXCCR_DQSRES_393_OHM (6 << 5)
-#define DXCCR_DQSRES_344_OHM (7 << 5)
-
-#define DXCCR_DQSNRES_OPEN (0 << 9)
-#define DXCCR_DQSNRES_688_OHM (1 << 9)
-#define DXCCR_DQSNRES_611_OHM (2 << 9)
-#define DXCCR_DQSNRES_550_OHM (3 << 9)
-#define DXCCR_DQSNRES_500_OHM (4 << 9)
-#define DXCCR_DQSNRES_458_OHM (5 << 9)
-#define DXCCR_DQSNRES_393_OHM (6 << 9)
-#define DXCCR_DQSNRES_344_OHM (7 << 9)
-
-#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
-#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */
-#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT))
-
-#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
-#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
-
-/* SoC-specific parameters */
-#define NR_DATX8_PER_DDRPHY 2
-
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
- defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-#define NR_DDRPHY_PER_CH 1
-#else
-#define NR_DDRPHY_PER_CH 2
-#endif
-
-#define NR_DDRCH 2
-
-#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
-
-#ifndef __ASSEMBLY__
-int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
-int ddrphy_training(struct ddrphy __iomem *phy);
-#endif
-
-#endif /* ARCH_DDRPHY_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MACH_INIT_H
-#define __MACH_INIT_H
-
-struct uniphier_board_data {
- unsigned long dram_ch0_base;
- unsigned long dram_ch0_size;
- unsigned long dram_ch0_width;
- unsigned long dram_ch1_base;
- unsigned long dram_ch1_size;
- unsigned long dram_ch1_width;
- unsigned long dram_ch2_base;
- unsigned long dram_ch2_size;
- unsigned long dram_ch2_width;
- unsigned int dram_freq;
-};
-
-const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
-
-int ph1_sld3_init(const struct uniphier_board_data *bd);
-int ph1_ld4_init(const struct uniphier_board_data *bd);
-int ph1_pro4_init(const struct uniphier_board_data *bd);
-int ph1_sld8_init(const struct uniphier_board_data *bd);
-int ph1_pro5_init(const struct uniphier_board_data *bd);
-int proxstream2_init(const struct uniphier_board_data *bd);
-
-#if defined(CONFIG_MICRO_SUPPORT_CARD)
-int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
-int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
-int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
-int proxstream2_sbc_init(const struct uniphier_board_data *bd);
-#else
-static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-
-static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-
-static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-
-static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
-{
- return 0;
-}
-#endif
-
-int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
-int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
-
-int memconf_init(const struct uniphier_board_data *bd);
-int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
-int proxstream2_memconf_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
-int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
-int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
-int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
-int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
-
-int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
-int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
-int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
-
-int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
-
-int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
-
-void ph1_sld3_pin_init(void);
-void ph1_ld4_pin_init(void);
-void ph1_pro4_pin_init(void);
-void ph1_sld8_pin_init(void);
-void ph1_pro5_pin_init(void);
-void proxstream2_pin_init(void);
-void ph1_ld6b_pin_init(void);
-
-void ph1_ld4_clk_init(void);
-void ph1_pro4_clk_init(void);
-void ph1_pro5_clk_init(void);
-void proxstream2_clk_init(void);
-
-#define pr_err(fmt, args...) printf(fmt, ##args)
-
-#endif /* __MACH_INIT_H */
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
-
-#if defined(CONFIG_MICRO_SUPPORT_CARD)
-void support_card_reset(void);
-void support_card_init(void);
-void support_card_late_init(void);
-int check_support_card(void);
-void led_puts(const char *s);
-#else
-static inline void support_card_reset(void)
-{
-}
-
-static inline void support_card_init(void)
-{
-}
-
-static inline void support_card_late_init(void)
-{
-}
-
-static inline int check_support_card(void)
-{
- return 0;
-}
-
-static inline void led_puts(const char *s)
-{
-}
-#endif
-
-#endif /* ARCH_BOARD_H */
+++ /dev/null
-/*
- * UniPhier SBC (System Bus Controller) registers
- *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SBC_REGS_H
-#define ARCH_SBC_REGS_H
-
-#define SBBASE_BASE 0x58c00100
-#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
-
-#define SBBASE0 (SBBASE(0))
-#define SBBASE1 (SBBASE(1))
-#define SBBASE2 (SBBASE(2))
-#define SBBASE3 (SBBASE(3))
-#define SBBASE4 (SBBASE(4))
-#define SBBASE5 (SBBASE(5))
-#define SBBASE6 (SBBASE(6))
-#define SBBASE7 (SBBASE(7))
-
-#define SBBASE_BANK_ENABLE (0x00000001)
-
-#define SBCTRL_BASE 0x58c00200
-#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
-
-#define SBCTRL00 SBCTRL(0, 0)
-#define SBCTRL01 SBCTRL(0, 1)
-#define SBCTRL02 SBCTRL(0, 2)
-#define SBCTRL03 SBCTRL(0, 3)
-#define SBCTRL04 (SBCTRL_BASE + 0x100)
-
-#define SBCTRL10 SBCTRL(1, 0)
-#define SBCTRL11 SBCTRL(1, 1)
-#define SBCTRL12 SBCTRL(1, 2)
-#define SBCTRL13 SBCTRL(1, 3)
-#define SBCTRL14 (SBCTRL_BASE + 0x110)
-
-#define SBCTRL20 SBCTRL(2, 0)
-#define SBCTRL21 SBCTRL(2, 1)
-#define SBCTRL22 SBCTRL(2, 2)
-#define SBCTRL23 SBCTRL(2, 3)
-#define SBCTRL24 (SBCTRL_BASE + 0x120)
-
-#define SBCTRL30 SBCTRL(3, 0)
-#define SBCTRL31 SBCTRL(3, 1)
-#define SBCTRL32 SBCTRL(3, 2)
-#define SBCTRL33 SBCTRL(3, 3)
-#define SBCTRL34 (SBCTRL_BASE + 0x130)
-
-#define SBCTRL40 SBCTRL(4, 0)
-#define SBCTRL41 SBCTRL(4, 1)
-#define SBCTRL42 SBCTRL(4, 2)
-#define SBCTRL43 SBCTRL(4, 3)
-#define SBCTRL44 (SBCTRL_BASE + 0x140)
-
-#define SBCTRL50 SBCTRL(5, 0)
-#define SBCTRL51 SBCTRL(5, 1)
-#define SBCTRL52 SBCTRL(5, 2)
-#define SBCTRL53 SBCTRL(5, 3)
-#define SBCTRL54 (SBCTRL_BASE + 0x150)
-
-#define SBCTRL60 SBCTRL(6, 0)
-#define SBCTRL61 SBCTRL(6, 1)
-#define SBCTRL62 SBCTRL(6, 2)
-#define SBCTRL63 SBCTRL(6, 3)
-#define SBCTRL64 (SBCTRL_BASE + 0x160)
-
-#define SBCTRL70 SBCTRL(7, 0)
-#define SBCTRL71 SBCTRL(7, 1)
-#define SBCTRL72 SBCTRL(7, 2)
-#define SBCTRL73 SBCTRL(7, 3)
-#define SBCTRL74 (SBCTRL_BASE + 0x170)
-
-/* slower but LED works */
-#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
-#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
-
-/* faster but LED does not work */
-#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
-/* NOR flash needs more wait counts than SRAM */
-#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
-
-#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
-
-#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
-#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
-#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
-
-#define PC0CTRL 0x598000c0
-#define ROM_BOOT_ROMRSV2 0x59801208
-
-#ifndef __ASSEMBLY__
-#include <linux/io.h>
-static inline int boot_is_swapped(void)
-{
- return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
-}
-#endif
-
-#endif /* ARCH_SBC_REGS_H */
+++ /dev/null
-/*
- * UniPhier SC (System Control) block registers
- *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SC_REGS_H
-#define ARCH_SC_REGS_H
-
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
-#define SC_BASE_ADDR 0xf1840000
-#else
-#define SC_BASE_ADDR 0x61840000
-#endif
-
-#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
-#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
-#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
-
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
-#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
-#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
-#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
-
-#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
-#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
-
-#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
-#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
-#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
-
-#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
-
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
-#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
-#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
-
-#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
-#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
-#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
-
-#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
-#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
-#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
-#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
-#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
-#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
-/* Pro4 or older */
-#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
-#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
-#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
-
-#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
-#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
-#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
-
-#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
-
-/* Pro5 or newer */
-#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
-#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
-#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
-#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
-#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
-#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
-#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
-#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
-
-#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
-#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
-#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
-#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
-#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
-#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
-#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
-/* Pro4 or older */
-#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
-#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
-#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
-#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
-
-/* Pro5 or newer */
-#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
-#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
-#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
-#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
-#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
-
-/* System reset control register */
-#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
-#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
-#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
-
-#endif /* ARCH_SC_REGS_H */
+++ /dev/null
-/*
- * UniPhier SG (SoC Glue) block registers
- *
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SG_REGS_H
-#define ARCH_SG_REGS_H
-
-/* Base Address */
-#define SG_CTRL_BASE 0x5f800000
-#define SG_DBG_BASE 0x5f900000
-
-/* Revision */
-#define SG_REVISION (SG_CTRL_BASE | 0x0000)
-#define SG_REVISION_TYPE_SHIFT 16
-#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
-#define SG_REVISION_MODEL_SHIFT 8
-#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
-#define SG_REVISION_REV_SHIFT 0
-#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
-
-/* Memory Configuration */
-#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
-
-#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
-#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
-#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
-#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
-#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
-
-#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
-#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
-#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
-#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
-#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
-
-#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
-#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
-#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
-#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
-#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
-#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
-#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
-#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
-#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
-
-#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
-
-/* Pin Control */
-#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
-
-/* PH1-Pro4, PH1-Pro5 */
-#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
-
-/* Input Enable */
-#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
-
-/* Pin Monitor */
-#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
-
-#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
-#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
-
-#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
-
-#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
-#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
-
-#ifdef __ASSEMBLY__
-
- .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
- ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
- ldr \rd, [\ra]
- and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
- orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
- str \rd, [\ra]
- .endm
-
-#else
-
-#include <linux/types.h>
-#include <linux/io.h>
-
-static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
- unsigned mux_bits, unsigned reg_stride)
-{
- unsigned shift = pin * mux_bits % 32;
- unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
- u32 mask = (1U << mux_bits) - 1;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~(mask << shift);
- tmp |= (mask & muxval) << shift;
- writel(tmp, reg);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* ARCH_SG_REGS_H */
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MACH_SOC_INFO_H__
-#define __MACH_SOC_INFO_H__
-
-enum uniphier_soc_id {
- SOC_UNIPHIER_PH1_SLD3,
- SOC_UNIPHIER_PH1_LD4,
- SOC_UNIPHIER_PH1_PRO4,
- SOC_UNIPHIER_PH1_SLD8,
- SOC_UNIPHIER_PH1_PRO5,
- SOC_UNIPHIER_PROXSTREAM2,
- SOC_UNIPHIER_PH1_LD6B,
- SOC_UNIPHIER_UNKNOWN,
-};
-
-#define UNIPHIER_NR_ENABLED_SOCS \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
- IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
-
-#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
-
-#if UNIPHIER_MULTI_SOC
-enum uniphier_soc_id uniphier_get_soc_type(void);
-#else
-static inline enum uniphier_soc_id uniphier_get_soc_type(void)
-{
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
- return SOC_UNIPHIER_PH1_SLD3;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
- return SOC_UNIPHIER_PH1_LD4;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
- return SOC_UNIPHIER_PH1_PRO4;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
- return SOC_UNIPHIER_PH1_SLD8;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
- return SOC_UNIPHIER_PH1_PRO5;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
- return SOC_UNIPHIER_PROXSTREAM2;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
- return SOC_UNIPHIER_PH1_LD6B;
-#endif
-
- return SOC_UNIPHIER_UNKNOWN;
-}
-#endif
-
-#endif /* __MACH_SOC_INFO_H__ */
+++ /dev/null
-/*
- * UniPhier System Cache (L2 Cache) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_SSC_REGS_H
-#define ARCH_SSC_REGS_H
-
-#define SSCC 0x500c0000
-#define SSCC_BST (0x1 << 20)
-#define SSCC_ACT (0x1 << 19)
-#define SSCC_WTG (0x1 << 18)
-#define SSCC_PRD (0x1 << 17)
-#define SSCC_WBWA (0x1 << 16)
-#define SSCC_EX (0x1 << 13)
-#define SSCC_ON (0x1 << 0)
-
-#define SSCLPDAWCR 0x500c0030
-
-#define SSCOPE 0x506c0244
-#define SSCOPE_CM_SYNC 0x00000008
-
-#define SSCOQM 0x506c0248
-#define SSCOQM_TID_MASK (0x3 << 21)
-#define SSCOQM_TID_BY_WAY (0x2 << 21)
-#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
-#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
-#define SSCOQM_S_MASK (0x3 << 17)
-#define SSCOQM_S_WAY (0x2 << 17)
-#define SSCOQM_S_ALL (0x1 << 17)
-#define SSCOQM_S_ADDRESS (0x0 << 17)
-#define SSCOQM_CE (0x1 << 15)
-#define SSCOQM_CW (0x1 << 14)
-#define SSCOQM_CM_MASK (0x7)
-#define SSCOQM_CM_DIRT_TOUCH (0x7)
-#define SSCOQM_CM_ZERO_TOUCH (0x6)
-#define SSCOQM_CM_NORM_TOUCH (0x5)
-#define SSCOQM_CM_PREF_FETCH (0x4)
-#define SSCOQM_CM_SSC_FETCH (0x3)
-#define SSCOQM_CM_WB_INV (0x2)
-#define SSCOQM_CM_WB (0x1)
-#define SSCOQM_CM_INV (0x0)
-
-#define SSCOQAD 0x506c024c
-#define SSCOQSZ 0x506c0250
-#define SSCOQWN 0x506c0258
-
-#define SSCOPPQSEF 0x506c025c
-#define SSCOPPQSEF_FE (0x1 << 1)
-#define SSCOPPQSEF_OE (0x1 << 0)
-
-#define SSCOLPQS 0x506c0260
-#define SSCOLPQS_EF (0x1 << 2)
-#define SSCOLPQS_EST (0x1 << 1)
-#define SSCOLPQS_QST (0x1 << 0)
-
-#define SSCOQCE0 0x506c0270
-
-#define SSC_LINE_SIZE 128
-#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
-
-#endif /* ARCH_SSC_REGS_H */
+++ /dev/null
-/*
- * UniPhier UMC (Universal Memory Controller) registers
- *
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_UMC_REGS_H
-#define ARCH_UMC_REGS_H
-
-#define UMC_BASE 0x5b800000
-
-/* SSIF registers */
-#define UMC_SSIF_BASE UMC_BASE
-
-#define UMC_CPURST 0x00000700
-#define UMC_IDSRST 0x0000070C
-#define UMC_IXMRST 0x00000714
-#define UMC_HDMRST 0x00000718
-#define UMC_MDMRST 0x0000071C
-#define UMC_HDDRST 0x00000720
-#define UMC_MDDRST 0x00000724
-#define UMC_SIORST 0x00000728
-#define UMC_GIORST 0x0000072C
-#define UMC_HD2RST 0x00000734
-#define UMC_VIORST 0x0000073C
-#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
-#define UMC_DVCRST 0x00000748 /* Pro4 */
-#define UMC_RGLRST 0x00000750
-#define UMC_VPERST 0x00000758
-#define UMC_AIORST 0x00000764
-#define UMC_DMDRST 0x00000770
-
-#define UMC_HDMCHSEL 0x00000898
-#define UMC_MDMCHSEL 0x0000089C
-#define UMC_DVCCHSEL 0x000008C8
-#define UMC_DMDCHSEL 0x000008F0
-
-#define UMC_CLKEN_SSIF_FETCH 0x0000C060
-#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
-#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
-#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
-#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
-#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
-#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
-#define UMC_CLKEN_SSIF_WC 0x0000C07C
-#define UMC_CLKEN_SSIF_RC 0x0000C080
-#define UMC_CLKEN_SSIF_DST 0x0000C084
-
-/* CA registers */
-#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
-
-/* DRAM controller registers */
-#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
-
-#define UMC_CMDCTLA 0x00000000
-#define UMC_CMDCTLB 0x00000004
-#define UMC_INITCTLA 0x00000008
-#define UMC_INITCTLB 0x0000000C
-#define UMC_INITCTLC 0x00000010
-#define UMC_INITSET 0x00000014
-#define UMC_INITSTAT 0x00000018
-#define UMC_DRMMR0 0x0000001C
-#define UMC_DRMMR1 0x00000020
-#define UMC_DRMMR2 0x00000024
-#define UMC_DRMMR3 0x00000028
-#define UMC_SPCCTLA 0x00000030
-#define UMC_SPCCTLB 0x00000034
-#define UMC_SPCSETA 0x00000038
-#define UMC_SPCSETB 0x0000003C
-#define UMC_SPCSETC 0x00000040
-#define UMC_SPCSETD 0x00000044
-#define UMC_SPCSTATA 0x00000050
-#define UMC_SPCSTATB 0x00000054
-#define UMC_SPCSTATC 0x00000058
-#define UMC_ACSSETA 0x00000060
-#define UMC_FLOWCTLA 0x00000400
-#define UMC_FLOWCTLB 0x00000404
-#define UMC_FLOWCTLC 0x00000408
-#define UMC_FLOWCTLG 0x00000508
-#define UMC_RDATACTL_D0 0x00000600
-#define UMC_WDATACTL_D0 0x00000604
-#define UMC_RDATACTL_D1 0x00000608
-#define UMC_WDATACTL_D1 0x0000060C
-#define UMC_DATASET 0x00000610
-#define UMC_DCCGCTL 0x00000720
-#define UMC_DICGCTLA 0x00000724
-#define UMC_DICGCTLB 0x00000728
-#define UMC_DIOCTLA 0x00000C00
-#define UMC_DFICUPDCTLA 0x00000C20
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-static inline void umc_polling(u32 address, u32 expval, u32 mask)
-{
- u32 nmask = ~mask;
- u32 data;
- do {
- data = readl(address) & nmask;
- } while (data != expval);
-}
-
-static inline void umc_dram_init_start(void __iomem *dramcont)
-{
- writel(0x00000002, dramcont + UMC_INITSET);
-}
-
-static inline void umc_dram_init_poll(void __iomem *dramcont)
-{
- while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
- ;
-}
-
-#endif
-
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+struct uniphier_board_data {
+ unsigned long dram_ch0_base;
+ unsigned long dram_ch0_size;
+ unsigned long dram_ch0_width;
+ unsigned long dram_ch1_base;
+ unsigned long dram_ch1_size;
+ unsigned long dram_ch1_width;
+ unsigned long dram_ch2_base;
+ unsigned long dram_ch2_size;
+ unsigned long dram_ch2_width;
+ unsigned int dram_freq;
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(void);
+
+int ph1_sld3_init(const struct uniphier_board_data *bd);
+int ph1_ld4_init(const struct uniphier_board_data *bd);
+int ph1_pro4_init(const struct uniphier_board_data *bd);
+int ph1_sld8_init(const struct uniphier_board_data *bd);
+int ph1_pro5_init(const struct uniphier_board_data *bd);
+int proxstream2_init(const struct uniphier_board_data *bd);
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
+int proxstream2_sbc_init(const struct uniphier_board_data *bd);
+#else
+static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+#endif
+
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
+
+int memconf_init(const struct uniphier_board_data *bd);
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
+int proxstream2_memconf_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+int proxstream2_umc_init(const struct uniphier_board_data *bd);
+
+void ph1_sld3_pin_init(void);
+void ph1_ld4_pin_init(void);
+void ph1_pro4_pin_init(void);
+void ph1_sld8_pin_init(void);
+void ph1_pro5_pin_init(void);
+void proxstream2_pin_init(void);
+void ph1_ld6b_pin_init(void);
+
+void ph1_ld4_clk_init(void);
+void ph1_pro4_clk_init(void);
+void ph1_pro5_clk_init(void);
+void proxstream2_clk_init(void);
+
+#define pr_err(fmt, args...) printf(fmt, ##args)
+
+#endif /* __MACH_INIT_H */
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_ld4_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro4_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_pro5_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld3_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int ph1_sld8_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/init.h>
-#include <mach/micro-support-card.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
int proxstream2_init(const struct uniphier_board_data *bd)
{
+ int ret;
+
proxstream2_sbc_init(bd);
support_card_reset();
led_puts("L4");
+ ret = proxstream2_umc_init(bd);
+ if (ret)
+ return ret;
+
+ led_puts("L5");
+
return 0;
}
#include <common.h>
#include <spl.h>
-#include <mach/init.h>
-#include <mach/soc_info.h>
-DECLARE_GLOBAL_DATA_PTR;
+#include "../init.h"
+#include "../soc-info.h"
void spl_board_init(void)
{
const struct uniphier_board_data *param;
- param = uniphier_get_board_param(gd->fdt_blob);
+ param = uniphier_get_board_param();
if (!param)
hang();
*/
#include <linux/linkage.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
ldr r1, = SSCC
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
-#include <mach/arm-mpcore.h>
-#include <mach/sbc-regs.h>
-#include <mach/ssc-regs.h>
+
+#include "ssc-regs.h"
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int proxstream2_memconf_init(const struct uniphier_board_data *bd)
{
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
int memconf_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/ctype.h>
#include <linux/io.h>
-#include <mach/micro-support-card.h>
+
+#include "micro-support-card.h"
#define MICRO_SUPPORT_CARD_BASE 0x43f00000
#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
-#include <mach/sbc-regs.h>
struct memory_bank {
phys_addr_t base;
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+void support_card_late_init(void);
+int check_support_card(void);
+void led_puts(const char *s);
+#else
+static inline void support_card_reset(void)
+{
+}
+
+static inline void support_card_init(void)
+{
+}
+
+static inline void support_card_late_init(void)
+{
+}
+
+static inline int check_support_card(void)
+{
+ return 0;
+}
+
+static inline void led_puts(const char *s)
+{
+}
+#endif
+
+#endif /* ARCH_BOARD_H */
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld4_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_ld6b_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro4_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_pro5_pin_init(void)
{
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld3_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void ph1_sld8_pin_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
void proxstream2_pin_init(void)
{
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/init.h>
+#include "../init.h"
int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
static void dpll_init(void)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sc-regs.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/micro-support-card.h>
+#include "micro-support-card.h"
int misc_init_f(void)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/sc-regs.h>
+
+#include "sc-regs.h"
void reset_cpu(unsigned long ignored)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
{
#include <common.h>
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
{
*/
#include <linux/io.h>
-#include <mach/init.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+#include "sbc-regs.h"
int proxstream2_sbc_init(const struct uniphier_board_data *bd)
{
--- /dev/null
+/*
+ * UniPhier SBC (System Bus Controller) registers
+ *
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SBC_REGS_H
+#define ARCH_SBC_REGS_H
+
+#define SBBASE_BASE 0x58c00100
+#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
+
+#define SBBASE0 (SBBASE(0))
+#define SBBASE1 (SBBASE(1))
+#define SBBASE2 (SBBASE(2))
+#define SBBASE3 (SBBASE(3))
+#define SBBASE4 (SBBASE(4))
+#define SBBASE5 (SBBASE(5))
+#define SBBASE6 (SBBASE(6))
+#define SBBASE7 (SBBASE(7))
+
+#define SBBASE_BANK_ENABLE (0x00000001)
+
+#define SBCTRL_BASE 0x58c00200
+#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
+
+#define SBCTRL00 SBCTRL(0, 0)
+#define SBCTRL01 SBCTRL(0, 1)
+#define SBCTRL02 SBCTRL(0, 2)
+#define SBCTRL03 SBCTRL(0, 3)
+#define SBCTRL04 (SBCTRL_BASE + 0x100)
+
+#define SBCTRL10 SBCTRL(1, 0)
+#define SBCTRL11 SBCTRL(1, 1)
+#define SBCTRL12 SBCTRL(1, 2)
+#define SBCTRL13 SBCTRL(1, 3)
+#define SBCTRL14 (SBCTRL_BASE + 0x110)
+
+#define SBCTRL20 SBCTRL(2, 0)
+#define SBCTRL21 SBCTRL(2, 1)
+#define SBCTRL22 SBCTRL(2, 2)
+#define SBCTRL23 SBCTRL(2, 3)
+#define SBCTRL24 (SBCTRL_BASE + 0x120)
+
+#define SBCTRL30 SBCTRL(3, 0)
+#define SBCTRL31 SBCTRL(3, 1)
+#define SBCTRL32 SBCTRL(3, 2)
+#define SBCTRL33 SBCTRL(3, 3)
+#define SBCTRL34 (SBCTRL_BASE + 0x130)
+
+#define SBCTRL40 SBCTRL(4, 0)
+#define SBCTRL41 SBCTRL(4, 1)
+#define SBCTRL42 SBCTRL(4, 2)
+#define SBCTRL43 SBCTRL(4, 3)
+#define SBCTRL44 (SBCTRL_BASE + 0x140)
+
+#define SBCTRL50 SBCTRL(5, 0)
+#define SBCTRL51 SBCTRL(5, 1)
+#define SBCTRL52 SBCTRL(5, 2)
+#define SBCTRL53 SBCTRL(5, 3)
+#define SBCTRL54 (SBCTRL_BASE + 0x150)
+
+#define SBCTRL60 SBCTRL(6, 0)
+#define SBCTRL61 SBCTRL(6, 1)
+#define SBCTRL62 SBCTRL(6, 2)
+#define SBCTRL63 SBCTRL(6, 3)
+#define SBCTRL64 (SBCTRL_BASE + 0x160)
+
+#define SBCTRL70 SBCTRL(7, 0)
+#define SBCTRL71 SBCTRL(7, 1)
+#define SBCTRL72 SBCTRL(7, 2)
+#define SBCTRL73 SBCTRL(7, 3)
+#define SBCTRL74 (SBCTRL_BASE + 0x170)
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
+
+#define PC0CTRL 0x598000c0
+#define ROM_BOOT_ROMRSV2 0x59801208
+
+#ifndef __ASSEMBLY__
+#include <linux/io.h>
+static inline int boot_is_swapped(void)
+{
+ return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+#endif
+
+#endif /* ARCH_SBC_REGS_H */
--- /dev/null
+/*
+ * UniPhier SC (System Control) block registers
+ *
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SC_REGS_H
+#define ARCH_SC_REGS_H
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+#define SC_BASE_ADDR 0xf1840000
+#else
+#define SC_BASE_ADDR 0x61840000
+#endif
+
+#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
+#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
+#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
+
+#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
+#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
+#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
+#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
+
+#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
+
+#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
+#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
+
+#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
+
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
+#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
+#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
+
+#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
+#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
+#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
+
+#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
+#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
+#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
+#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
+#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
+/* Pro4 or older */
+#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
+#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
+#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
+
+#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
+#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
+
+#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+
+/* Pro5 or newer */
+#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
+#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
+#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
+#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
+#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
+#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
+
+#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
+#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
+#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
+#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
+#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
+#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
+/* Pro4 or older */
+#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
+#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
+#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
+#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
+
+/* Pro5 or newer */
+#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
+#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
+#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
+
+/* System reset control register */
+#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
+#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
+#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
+
+#endif /* ARCH_SC_REGS_H */
--- /dev/null
+/*
+ * UniPhier SG (SoC Glue) block registers
+ *
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SG_REGS_H
+#define ARCH_SG_REGS_H
+
+/* Base Address */
+#define SG_CTRL_BASE 0x5f800000
+#define SG_DBG_BASE 0x5f900000
+
+/* Revision */
+#define SG_REVISION (SG_CTRL_BASE | 0x0000)
+#define SG_REVISION_TYPE_SHIFT 16
+#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
+#define SG_REVISION_MODEL_SHIFT 8
+#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
+#define SG_REVISION_REV_SHIFT 0
+#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
+
+/* Memory Configuration */
+#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
+
+#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
+
+#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+
+#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+/* PH1-LD6b, ProXstream2 only */
+#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
+
+#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
+
+/* Pin Control */
+#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
+
+/* PH1-Pro4, PH1-Pro5 */
+#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
+
+/* Input Enable */
+#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
+
+/* Pin Monitor */
+#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
+
+#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
+
+#ifdef __ASSEMBLY__
+
+ .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
+ ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
+ ldr \rd, [\ra]
+ and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
+ orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
+ str \rd, [\ra]
+ .endm
+
+#else
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
+ unsigned mux_bits, unsigned reg_stride)
+{
+ unsigned shift = pin * mux_bits % 32;
+ unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+ u32 mask = (1U << mux_bits) - 1;
+ u32 tmp;
+
+ tmp = readl(reg);
+ tmp &= ~(mask << shift);
+ tmp |= (mask & muxval) << shift;
+ writel(tmp, reg);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* ARCH_SG_REGS_H */
--- /dev/null
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_SOC_INFO_H__
+#define __MACH_SOC_INFO_H__
+
+enum uniphier_soc_id {
+ SOC_UNIPHIER_PH1_SLD3,
+ SOC_UNIPHIER_PH1_LD4,
+ SOC_UNIPHIER_PH1_PRO4,
+ SOC_UNIPHIER_PH1_SLD8,
+ SOC_UNIPHIER_PH1_PRO5,
+ SOC_UNIPHIER_PROXSTREAM2,
+ SOC_UNIPHIER_PH1_LD6B,
+ SOC_UNIPHIER_PH1_SLD11,
+ SOC_UNIPHIER_PH1_LD10,
+ SOC_UNIPHIER_UNKNOWN,
+};
+
+#define UNIPHIER_NR_ENABLED_SOCS \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD11) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+
+#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void);
+#else
+static inline enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ return SOC_UNIPHIER_PH1_SLD3;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ return SOC_UNIPHIER_PH1_LD4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ return SOC_UNIPHIER_PH1_PRO4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ return SOC_UNIPHIER_PH1_SLD8;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ return SOC_UNIPHIER_PH1_PRO5;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ return SOC_UNIPHIER_PROXSTREAM2;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ return SOC_UNIPHIER_PH1_LD6B;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD11)
+ return SOC_UNIPHIER_PH1_SLD11;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD10)
+ return SOC_UNIPHIER_PH1_LD10;
+#endif
+
+ return SOC_UNIPHIER_UNKNOWN;
+}
+#endif
+
+int uniphier_get_soc_model(void);
+int uniphier_get_soc_revision(void);
+
+#endif /* __MACH_SOC_INFO_H__ */
#include <linux/io.h>
#include <linux/types.h>
-#include <mach/sg-regs.h>
-#include <mach/soc_info.h>
+
+#include "sg-regs.h"
+#include "soc-info.h"
#if UNIPHIER_MULTI_SOC
enum uniphier_soc_id uniphier_get_soc_type(void)
case 0x2F:
ret = SOC_UNIPHIER_PH1_LD6B;
break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD11
+ case 0x31:
+ ret = SOC_UNIPHIER_PH1_SLD11;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD10
+ case 0x32:
+ ret = SOC_UNIPHIER_PH1_LD10;
+ break;
#endif
default:
ret = SOC_UNIPHIER_UNKNOWN;
return ret;
}
#endif
+
+int uniphier_get_soc_model(void)
+{
+ return (readl(SG_REVISION) & SG_REVISION_MODEL_MASK) >>
+ SG_REVISION_MODEL_SHIFT;
+}
+
+int uniphier_get_soc_revision(void)
+{
+ return (readl(SG_REVISION) & SG_REVISION_REV_MASK) >>
+ SG_REVISION_REV_SHIFT;
+}
--- /dev/null
+/*
+ * UniPhier System Cache (L2 Cache) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_SSC_REGS_H
+#define ARCH_SSC_REGS_H
+
+#define SSCC 0x500c0000
+#define SSCC_BST (0x1 << 20)
+#define SSCC_ACT (0x1 << 19)
+#define SSCC_WTG (0x1 << 18)
+#define SSCC_PRD (0x1 << 17)
+#define SSCC_WBWA (0x1 << 16)
+#define SSCC_EX (0x1 << 13)
+#define SSCC_ON (0x1 << 0)
+
+#define SSCLPDAWCR 0x500c0030
+
+#define SSCOPE 0x506c0244
+#define SSCOPE_CM_SYNC 0x00000008
+
+#define SSCOQM 0x506c0248
+#define SSCOQM_TID_MASK (0x3 << 21)
+#define SSCOQM_TID_BY_WAY (0x2 << 21)
+#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
+#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
+#define SSCOQM_S_MASK (0x3 << 17)
+#define SSCOQM_S_WAY (0x2 << 17)
+#define SSCOQM_S_ALL (0x1 << 17)
+#define SSCOQM_S_ADDRESS (0x0 << 17)
+#define SSCOQM_CE (0x1 << 15)
+#define SSCOQM_CW (0x1 << 14)
+#define SSCOQM_CM_MASK (0x7)
+#define SSCOQM_CM_DIRT_TOUCH (0x7)
+#define SSCOQM_CM_ZERO_TOUCH (0x6)
+#define SSCOQM_CM_NORM_TOUCH (0x5)
+#define SSCOQM_CM_PREF_FETCH (0x4)
+#define SSCOQM_CM_SSC_FETCH (0x3)
+#define SSCOQM_CM_WB_INV (0x2)
+#define SSCOQM_CM_WB (0x1)
+#define SSCOQM_CM_INV (0x0)
+
+#define SSCOQAD 0x506c024c
+#define SSCOQSZ 0x506c0250
+#define SSCOQWN 0x506c0258
+
+#define SSCOPPQSEF 0x506c025c
+#define SSCOPPQSEF_FE (0x1 << 1)
+#define SSCOPPQSEF_OE (0x1 << 0)
+
+#define SSCOLPQS 0x506c0260
+#define SSCOLPQS_EF (0x1 << 2)
+#define SSCOLPQS_EST (0x1 << 1)
+#define SSCOLPQS_QST (0x1 << 0)
+
+#define SSCOQCE0 0x506c0270
+
+#define SSC_LINE_SIZE 128
+#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
+
+#endif /* ARCH_SSC_REGS_H */
#include <common.h>
#include <linux/io.h>
-#include <mach/arm-mpcore.h>
+
+#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- if (freq == 1333) {
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x000FF0FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- } else if (freq == 1600) {
- writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
- writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
- writel(0x5101387F, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x2F030D3F, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x43030D3F, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- }
-
- writel(0x00000006, dramcont + UMC_DRMMR1);
-
- if (freq == 1333)
- writel(0x00000290, dramcont + UMC_DRMMR2);
- else if (freq == 1600)
- writel(0x00000298, dramcont + UMC_DRMMR2);
-
- writel(0x00000800, dramcont + UMC_DRMMR3);
-
- if (freq == 1333) {
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- } else if (freq == 1600) {
- if (size == 1)
- writel(0x002B0617, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x003F0617, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- }
-
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
-{
- if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
- (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
- (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
- bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
- return umc_init_sub(bd->dram_freq,
- bd->dram_ch0_size / SZ_128M,
- bd->dram_ch1_size / SZ_128M);
- } else {
- pr_err("Unsupported DDR configuration\n");
- return -EINVAL;
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000001, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x07ffffff, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
-
- writel(0x03010100, ssif_base + UMC_HDMCHSEL);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DVCCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
- writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_HDMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_HDDRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_GIORST);
- writel(0x00000001, ssif_base + UMC_HD2RST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_DVCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_VPERST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
- writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
- writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
- writel(0x5101387f, dramcont + UMC_INITCTLA);
- writel(0x43030d3f, dramcont + UMC_INITCTLB);
- writel(0x00ff00ff, dramcont + UMC_INITCTLC);
- writel(0x00000d71, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000298, dramcont + UMC_DRMMR2);
- writel(0x00000000, dramcont + UMC_DRMMR3);
- writel(0x003f0617, dramcont + UMC_SPCCTLA);
- writel(0x00ff0008, dramcont + UMC_SPCCTLB);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
- writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
- writel(0x04060802, dramcont + UMC_WDATACTL_D0);
- writel(0x04060802, dramcont + UMC_WDATACTL_D1);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x0000000f, dramcont + 0x7000);
- writel(0x0000000f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000071, dramcont + 0x8008);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x00000000, dramcont + 0x0060);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00010000, dramcont + UMC_SPCSETD);
- writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
- void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000103, dramcont0 + UMC_DIOCTLA);
-
- ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_1, 1);
- ddrphy_training(phy0_1);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 0);
- ddrphy_training(phy1_0);
-
- writel(0x00000103, dramcont1 + UMC_DIOCTLA);
-
- ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_1, 1);
- ddrphy_training(phy1_1);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
-{
- if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
- (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
- ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
- (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
- bd->dram_freq == 1600) {
- return umc_init_sub(bd->dram_freq,
- bd->dram_ch0_size / SZ_128M,
- bd->dram_ch1_size / SZ_128M);
- } else {
- pr_err("Unsupported DDR configuration\n");
- return -EINVAL;
- }
-}
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <mach/init.h>
-#include <mach/umc-regs.h>
-#include <mach/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
- writel(0x00000000, ssif_base + 0x0000b004);
- writel(0xffffffff, ssif_base + 0x0000c004);
- writel(0x000fffcf, ssif_base + 0x0000c008);
- writel(0x00000001, ssif_base + 0x0000b000);
- writel(0x00000001, ssif_base + 0x0000c000);
- writel(0x03010101, ssif_base + UMC_MDMCHSEL);
- writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
- writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
- writel(0x00000001, ssif_base + UMC_CPURST);
- writel(0x00000001, ssif_base + UMC_IDSRST);
- writel(0x00000001, ssif_base + UMC_IXMRST);
- writel(0x00000001, ssif_base + UMC_MDMRST);
- writel(0x00000001, ssif_base + UMC_MDDRST);
- writel(0x00000001, ssif_base + UMC_SIORST);
- writel(0x00000001, ssif_base + UMC_VIORST);
- writel(0x00000001, ssif_base + UMC_FRCRST);
- writel(0x00000001, ssif_base + UMC_RGLRST);
- writel(0x00000001, ssif_base + UMC_AIORST);
- writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
-{
-#ifdef CONFIG_DDR_STANDARD
- writel(0x55990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
-
- writel(0x5101046A, dramcont + UMC_INITCTLA);
-
- if (size == 1)
- writel(0x27028B0A, dramcont + UMC_INITCTLB);
- else if (size == 2)
- writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
- writel(0x00FF00FF, dramcont + UMC_INITCTLC);
- writel(0x00000b51, dramcont + UMC_DRMMR0);
- writel(0x00000006, dramcont + UMC_DRMMR1);
- writel(0x00000290, dramcont + UMC_DRMMR2);
-
-#ifdef CONFIG_DDR_STANDARD
- writel(0x00000000, dramcont + UMC_DRMMR3);
-#else
- writel(0x00000800, dramcont + UMC_DRMMR3);
-#endif
-
- if (size == 1)
- writel(0x00240512, dramcont + UMC_SPCCTLA);
- else if (size == 2)
- writel(0x00350512, dramcont + UMC_SPCCTLA);
-
- writel(0x00ff0006, dramcont + UMC_SPCCTLB);
- writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
- writel(0x04060806, dramcont + UMC_WDATACTL_D0);
- writel(0x04a02000, dramcont + UMC_DATASET);
- writel(0x00000000, ca_base + 0x2300);
- writel(0x00400020, dramcont + UMC_DCCGCTL);
- writel(0x00000003, dramcont + 0x7000);
- writel(0x0000004f, dramcont + 0x8000);
- writel(0x000000c3, dramcont + 0x8004);
- writel(0x00000077, dramcont + 0x8008);
- writel(0x0000003b, dramcont + UMC_DICGCTLA);
- writel(0x020a0808, dramcont + UMC_DICGCTLB);
- writel(0x00000004, dramcont + UMC_FLOWCTLG);
- writel(0x80000201, ca_base + 0xc20);
- writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
- writel(0x00200000, dramcont + UMC_FLOWCTLB);
- writel(0x00004444, dramcont + UMC_FLOWCTLC);
- writel(0x200a0a00, dramcont + UMC_SPCSETB);
- writel(0x00000000, dramcont + UMC_SPCSETD);
- writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
- void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
- void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
- void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
- void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
- void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
- void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
- void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
- umc_dram_init_start(dramcont0);
- umc_dram_init_start(dramcont1);
- umc_dram_init_poll(dramcont0);
- umc_dram_init_poll(dramcont1);
-
- writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
- ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
-
- ddrphy_prepare_training(phy0_0, 0);
- ddrphy_training(phy0_0);
-
- writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
- ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
-
- ddrphy_prepare_training(phy1_0, 1);
- ddrphy_training(phy1_0);
-
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
- umc_start_ssif(ssif_base);
-
- return 0;
-}
-
-int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
-{
- if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
- (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
- bd->dram_freq == 1333 &&
- bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
- return umc_init_sub(bd->dram_freq,
- bd->dram_ch0_size / SZ_128M,
- bd->dram_ch1_size / SZ_128M);
- } else {
- pr_err("Unsupported DDR configuration\n");
- return -EINVAL;
- }
-}
}
#endif /* CONFIG_DISPLAY_CPUINFO */
+#ifdef CONFIG_ALTERA_SYSID
+int checkboard(void)
+{
+ display_sysid();
+ return 0;
+}
+#endif
+
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
li r5,GD_SIZE /* parameter 3: count */
bl memset
+ li r3, 0 /* parameter 1: bootflag */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
#else
/* r3: IMMR */
bl cpu_init_f /* run low-level CPU init code (in Flash)*/
+ li r3, 0 /* parameter 1: bootflag */
bl board_init_f /* run 1st part of board init code (in Flash)*/
/* NOTREACHED - board_init_f() does not return */
printf("Memory Error Disable:\n");
printf(" Multiple-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
- printf(" Sinle-Bit Error Disable: %d\n",
+ printf(" Single-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
printf(" Memory Select Error Disable: %d\n\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) {
- printf("Address not alligned on "
+ printf("Address not aligned on "
"double word boundary\n");
return 1;
}
count = simple_strtoul(argv[3], NULL, 16);
if ((u32) addr % 8) {
- printf("Address not alligned on "
+ printf("Address not aligned on "
"double word boundary\n");
return 1;
}
int i;
if (num_buses > MAX_BUSES) {
- printf("%d PCI buses requsted, %d supported\n",
+ printf("%d PCI buses requested, %d supported\n",
num_buses, MAX_BUSES);
num_buses = MAX_BUSES;
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
- /* Caculate pin location and 2bit mask and dir */
+ /* Calculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
/*
* Empirically set ~MCAS-to-preamble override for DDR 2.
- * Your milage will vary.
+ * Your mileage will vary.
*/
cpo = 0;
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
- * Use timebase counter, get_timer() is not availabe
+ * Use timebase counter, get_timer() is not available
* at this point of initialization yet.
*/
static __inline__ unsigned long get_tbms (void)
tsec1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC1CM value */
+ /* unknown SCCR_TSEC1CM value */
return -2;
}
#endif
usbdr_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBDRCM value */
+ /* unknown SCCR_USBDRCM value */
return -3;
}
#endif
tsec2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TSEC2CM value */
+ /* unknown SCCR_TSEC2CM value */
return -4;
}
#elif defined(CONFIG_MPC8313)
usbmph_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_USBMPHCM value */
+ /* unknown SCCR_USBMPHCM value */
return -5;
}
enc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_ENCCM value */
+ /* unknown SCCR_ENCCM value */
return -7;
}
#endif
sdhc_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SDHCCM value */
+ /* unknown SCCR_SDHCCM value */
return -8;
}
#endif
tdm_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_TDMCM value */
+ /* unknown SCCR_TDMCM value */
return -8;
}
#endif
pciexp1_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP1CM value */
+ /* unknown SCCR_PCIEXP1CM value */
return -9;
}
pciexp2_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_PCIEXP2CM value */
+ /* unknown SCCR_PCIEXP2CM value */
return -10;
}
#endif
sata_clk = csb_clk / 3;
break;
default:
- /* unkown SCCR_SATACM value */
+ /* unknown SCCR_SATA1CM value */
return -11;
}
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
- /* corecnf_tab_index is too high, possibly worng value */
+ /* corecnf_tab_index is too high, possibly wrong value */
return -11;
}
switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
core_clk = 3 * csb_clk;
break;
default:
- /* unkown core to csb ratio */
+ /* unknown core to csb ratio */
return -13;
}
(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
#endif
- /* Enable Time Base & Decrimenter (so we will have udelay()) */
+ /* Enable Time Base & Decrementer (so we will have udelay()) */
im->sysconf.spcr |= SPCR_TBEN;
/* DDR control driver register */
printf("Failed to set promiscuous mode: %d %s\n"
"Falling back to the old \"flags\" way...\n",
errno, strerror(errno));
+ if (strlen(ifname) >= IFNAMSIZ) {
+ printf("Interface name %s is too long.\n", ifname);
+ return -EINVAL;
+ }
strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) {
printf("Failed to read flags: %d %s\n", errno,
0x38 8>;
};
+ timer {
+ compatible = "sandbox,timer";
+ clock-frequency = <1000000>;
+ };
+
uart0: serial {
compatible = "sandbox,serial";
u-boot,dm-pre-reloc;
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("ValleyView SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported);
}
#ifndef CONFIG_EFI_APP
debug("%s: Cannot find GMA node\n", __func__);
return -EINVAL;
}
- ret = gma_func0_init(PCH_VIDEO_DEV, pci_bus_to_hose(0), blob,
- gma_node);
+ ret = dm_pci_bus_find_bdf(PCH_VIDEO_DEV, &dev);
+ if (ret)
+ return ret;
+ ret = gma_func0_init(dev, blob, gma_node);
if (ret)
return ret;
return res;
}
-int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
- const void *blob, int node)
+int gma_func0_init(struct udevice *dev, const void *blob, int node)
{
#ifdef CONFIG_VIDEO
ulong start;
int ret;
/* IGD needs to be Bus Master */
- reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
+ dm_pci_read_config32(dev, PCI_COMMAND, ®32);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- x86_pci_write_config32(dev, PCI_COMMAND, reg32);
+ dm_pci_write_config32(dev, PCI_COMMAND, reg32);
/* Use write-combining for the graphics memory, 256MB */
- base = pci_read_bar32(hose, dev, 2);
+ base = dm_pci_read_bar32(dev, 2);
mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
mtrr_commit(true);
- gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
+ gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
debug("GT bar %p\n", gtt_bar);
ret = gma_pm_init_pre_vbios(gtt_bar);
if (ret)
#ifdef CONFIG_VIDEO
start = get_timer(0);
- ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
+ ret = dm_pci_run_vga_bios(dev, int15_handler,
+ PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
debug("BIOS ran in %lums\n", get_timer(start));
#endif
/* Post VBIOS init */
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
+ {},
};
/*
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Quark SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Quark SDHCI", mmc_supported);
}
void cpu_irq_init(void)
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
+ {},
};
int cpu_mmc_init(bd_t *bis)
{
- return pci_mmc_init("Topcliff SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ return pci_mmc_init("Topcliff SDHCI", mmc_supported);
}
void bd82x6x_pci_init(pci_dev_t dev);
void bd82x6x_usb_ehci_init(pci_dev_t dev);
void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
- const void *blob, int node);
+int gma_func0_init(struct udevice *dev, const void *blob, int node);
int bd82x6x_init(void);
/**
vbe_set_mode(mode_info);
}
-void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
struct vbe_mode_info *mode_info)
{
+ pci_dev_t pcidev = dm_pci_get_bdf(dev);
u32 num_dev;
num_dev = PCI_BUS(pcidev) << 8 | PCI_DEV(pcidev) << 3 |
unsigned short func = (unsigned short)M.x86.R_EAX;
int retval = 1;
unsigned short devid, vendorid, devfn;
+ struct udevice *dev;
/* Use short to get rid of gabage in upper half of 32-bit register */
short devindex;
unsigned char bus;
- pci_dev_t dev;
+ pci_dev_t bdf;
u32 dword;
u16 word;
u8 byte, reg;
+ int ret;
switch (func) {
case 0xb101: /* PCIBIOS Check */
devid = M.x86.R_ECX;
vendorid = M.x86.R_EDX;
devindex = M.x86.R_ESI;
- dev = pci_find_device(vendorid, devid, devindex);
- if (dev != -1) {
+ bdf = -1;
+ ret = dm_pci_find_device(vendorid, devid, devindex, &dev);
+ if (!ret) {
unsigned short busdevfn;
+
+ bdf = dm_pci_get_bdf(dev);
M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
/*
* busnum is an unsigned char;
* devfn is an int, so we mask it off.
*/
- busdevfn = (PCI_BUS(dev) << 8) | PCI_DEV(dev) << 3 |
- PCI_FUNC(dev);
+ busdevfn = (PCI_BUS(bdf) << 8) | PCI_DEV(bdf) << 3 |
+ PCI_FUNC(bdf);
debug("0x%x: return 0x%x\n", func, busdevfn);
M.x86.R_EBX = busdevfn;
retval = 1;
devfn = M.x86.R_EBX & 0xff;
bus = M.x86.R_EBX >> 8;
reg = M.x86.R_EDI;
- dev = PCI_BDF(bus, devfn >> 3, devfn & 7);
+ bdf = PCI_BDF(bus, devfn >> 3, devfn & 7);
+
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
+ if (ret) {
+ debug("%s: Device %x not found\n", __func__, bdf);
+ break;
+ }
switch (func) {
case 0xb108: /* Read Config Byte */
- byte = x86_pci_read_config8(dev, reg);
+ dm_pci_read_config8(dev, reg, &byte);
M.x86.R_ECX = byte;
break;
case 0xb109: /* Read Config Word */
- word = x86_pci_read_config16(dev, reg);
+ dm_pci_read_config16(dev, reg, &word);
M.x86.R_ECX = word;
break;
case 0xb10a: /* Read Config Dword */
- dword = x86_pci_read_config32(dev, reg);
+ dm_pci_read_config32(dev, reg, &dword);
M.x86.R_ECX = dword;
break;
case 0xb10b: /* Write Config Byte */
byte = M.x86.R_ECX;
- x86_pci_write_config8(dev, reg, byte);
+ dm_pci_write_config8(dev, reg, byte);
break;
case 0xb10c: /* Write Config Word */
word = M.x86.R_ECX;
- x86_pci_write_config16(dev, reg, word);
+ dm_pci_write_config16(dev, reg, word);
break;
case 0xb10d: /* Write Config Dword */
dword = M.x86.R_ECX;
- x86_pci_write_config32(dev, reg, dword);
+ dm_pci_write_config32(dev, reg, dword);
break;
}
-
#ifdef CONFIG_REALMODE_DEBUG
debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
bus, devfn, reg, M.x86.R_ECX);
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
const u8 sys_mgr_init_table[] = {
3, /* EMACIO0 */
- 3, /* EMACIO1 */
- 3, /* EMACIO2 */
- 3, /* EMACIO3 */
- 3, /* EMACIO4 */
- 3, /* EMACIO5 */
- 3, /* EMACIO6 */
- 3, /* EMACIO7 */
- 3, /* EMACIO8 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
3, /* EMACIO9 */
- 3, /* EMACIO10 */
- 3, /* EMACIO11 */
- 3, /* EMACIO12 */
- 3, /* EMACIO13 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */
0, /* GENERALIO12 */
2, /* GENERALIO13 */
2, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
+ 3, /* GENERALIO15 */
+ 3, /* GENERALIO16 */
2, /* GENERALIO17 */
2, /* GENERALIO18 */
0, /* GENERALIO19 */
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include <i2c.h>
-#include <netdev.h>
void pin_mux_usb(void)
{
/* For CD GPIO PP1 */
pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}
-
-#ifdef CONFIG_PCI
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-#endif
S: Maintained
F: board/congatec/cgtqmx6eval/
F: include/configs/cgtqmx6eval.h
-F: configs/cgtqmx6qeval_defconfig
+F: configs/cgtqmx6eval_defconfig
=> sf probe
+=> setenv serverip <server_ip_address>
+
+=> setenv ipaddr <board_ip_address>
+
=> tftp 0x12000000 SPL
=> sf erase 0x0 0x10000
-=> sf write 0x12000000 0x400 0x100
+=> sf write 0x12000000 0x400 0x10000
=> tftp 0x12000000 u-boot.img
#ifdef CONFIG_MXC_SPI
static void setup_spi(void)
{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+ SETUP_IOMUX_PADS(ecspi1_pads);
gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
}
#endif
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
- u32 id, ret;
+ u32 id;
+ int ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id);
id = id & 0xf;
LS2080A BOARD
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
F: board/freescale/ls2080a/
F: include/configs/ls2080a_emu.h
MPC8572DS BOARD
-M: York Sun <yorksun@freescale.com>
+M: York Sun <york.sun@nxp.com>
S: Maintained
F: board/freescale/mpc8572ds/
F: include/configs/MPC8572DS.h
MX25PDK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx25pdk/
F: include/configs/mx25pdk.h
MX28EVK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx28evk/
F: include/configs/mx28evk.h
MX53ARD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx53ard/
F: include/configs/mx53ard.h
MX53SMD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx53smd/
F: include/configs/mx53smd.h
MX6QSABREAUTO BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6qsabreauto/
}
#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ clrbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
static void do_enable_hdmi(struct display_info_t const *dev)
{
+ disable_lvds(dev);
imx_enable_hdmi_phy();
}
struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = NULL,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
} } };
size_t display_count = ARRAY_SIZE(displays);
+iomux_v3_cfg_t const backlight_pads[] = {
+ MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_backlight(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+}
+
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
+ setup_iomux_backlight();
enable_ipu_clock();
imx_setup_hdmi();
+ /* Turn on LDB_DI0 and LDB_DI1 clocks */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+ reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
}
#endif /* CONFIG_VIDEO_IPUV3 */
int board_early_init_f(void)
{
setup_iomux_uart();
-#ifdef CONFIG_VIDEO_IPUV3
- setup_display();
-#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
setup_iomux_eimnor();
return 0;
}
MX6SABRESD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx6sabresd/
F: include/configs/mx6sabresd.h
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ udelay(100);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
}
#endif
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
static void disable_lvds(struct display_info_t const *dev)
{
MX6SLEVK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
M: Peng Fan <Peng.Fan@freescale.com>
S: Maintained
F: board/freescale/mx6slevk/
MX6SXSABRESD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/freescale/mx6sxsabresd/
F: include/configs/mx6sxsabresd.h
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg;
+ int reg, ret;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+ if (ret)
+ return ret;
+
imx_iomux_v3_setup_multiple_pads(phy_control_pads,
ARRAY_SIZE(phy_control_pads));
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
reg = readl(&anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
- return enable_fec_anatop_clock(0, ENET_125MHZ);
+ return 0;
}
int board_eth_init(bd_t *bis)
ulong map_addr;
int r;
- r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
+ r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
if (r)
return r;
#include <asm/gpio.h>
#include "pinmux-config-cardhu.h"
#include <i2c.h>
-#include <netdev.h>
#define PMU_I2C_ADDRESS 0x2D
#define MAX_I2C_RETRY 3
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
*/
#include <common.h>
-#include <netdev.h>
#include <power/as3722.h>
#include <asm/arch/gpio.h>
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
*/
#include <common.h>
-#include <netdev.h>
#include <i2c.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* PCI */
MX6CUBOXI BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/solidrun/mx6cuboxi/
F: include/configs/mx6cuboxi.h
SETUP_IOMUX_PADS(enet_pads);
gpio_direction_output(ETH_PHY_RESET, 0);
- mdelay(2);
+ mdelay(10);
gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
}
int board_phy_config(struct phy_device *phydev)
writel(0x007F007F, &iomux->gpr[7]);
}
-/*
- * This section requires the differentiation between Solidrun mx6 boards, but
- * for now, it will configure only for the mx6dual hummingboard version.
- */
static void spl_dram_init(int width)
{
struct mx6_ddr_sysinfo sysinfo = {
#if defined(CONFIG_ETH_DESIGNWARE)
u32 interface = PHY_INTERFACE_MODE_MII;
-#if defined(CONFIG_DW_AUTONEG)
- interface = PHY_INTERFACE_MODE_GMII;
-#endif
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
*/
#include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
#include <asm/arch/reset_manager.h>
#include <asm/gpio.h>
#include <asm/io.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
int board_early_init_f(void)
{
int ret;
F: configs/Auxtek-T003_defconfig
F: configs/Auxtek-T004_defconfig
F: configs/CHIP_defconfig
+F: configs/Empire_electronix_d709_defconfig
F: configs/inet98v_rev2_defconfig
F: configs/mk802_a10s_defconfig
F: configs/q8_a13_tablet_defconfig
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9031
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x70);
- if (ret)
- return ret;
-
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x7777);
- if (ret)
- return ret;
-
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0);
- if (ret)
- return ret;
-
- ret = ksz9031_phy_extended_write(phydev, 0x2,
- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
- MII_KSZ9031_MOD_DATA_NO_POST_INC,
- 0x03FC);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
#include <asm/io.h>
#include <dm.h>
#include <i2c.h>
-#include <netdev.h>
#include "pinmux-config-apalis_t30.h"
return 0;
}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
#endif /* CONFIG_PCI_TEGRA */
UDOO BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/udoo/
F: include/configs/udoo.h
WANDBOARD BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Fabio Estevam <fabio.estevam@nxp.com>
S: Maintained
F: board/wandboard/
F: include/configs/wandboard.h
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(ETH_PHY_RESET, 1);
+ udelay(100);
}
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
return 0;
}
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
#if defined(CONFIG_VIDEO_IPUV3)
struct i2c_pads_info mx6q_i2c2_pad_info = {
.scl = {
* is pretty rare.
*/
rcode = cli_simple_run_command_list(buff, flag);
+#endif
if (need_buff)
free(buff);
-#endif
return rcode;
}
addr[offset] = 0;
}
- return 0;
+ return errs;
}
static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
val += incr;
}
- return 0;
+ return errs;
}
/*
/* Set read buffer to initial value or empty sting */
init_val = getenv(argv[1]);
if (init_val)
- sprintf(buffer, "%s", init_val);
+ snprintf(buffer, CONFIG_SYS_CBSIZE, "%s", init_val);
else
buffer[0] = '\0';
}
#ifdef CONFIG_DM_PCI
- ret = pci_bus_find_bdf(bdf, &dev);
+ ret = dm_pci_bus_find_bdf(bdf, &dev);
if (ret) {
printf("No such device\n");
return CMD_RET_FAILURE;
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
void scsi_init(void)
{
- int busdevfunc;
+ int busdevfunc = -1;
int i;
/*
* Find a device from the list, this driver will support a single
*/
for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
/* get PCI Device ID */
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_find_device(scsi_device_list[i].vendor,
+ scsi_device_list[i].device, 0, &dev);
+ if (!ret) {
+ busdevfunc = dm_pci_get_bdf(dev);
+ break;
+ }
+#else
busdevfunc = pci_find_device(scsi_device_list[i].vendor,
scsi_device_list[i].device,
0);
+#endif
if (busdevfunc != -1)
break;
}
e.key = name;
e.data = NULL;
+ e.callback = NULL;
hsearch_r(e, FIND, &ep, &env_htab, 0);
/* does the env variable actually exist? */
e.key = name;
e.data = NULL;
+ e.callback = NULL;
hsearch_r(e, FIND, &ep, &env_htab, 0);
/* does the env variable actually exist? */
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR FDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
- (ns) > 0)
+#define OF_CHECK_COUNTS(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
/* Debug utility */
#ifdef DEBUG
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
- if (!OF_CHECK_COUNTS(na, ns)) {
+ if (!OF_CHECK_COUNTS(na)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
goto bail;
/* Get new parent bus and counts */
pbus = &of_busses[0];
pbus->count_cells(blob, parent, &pna, &pns);
- if (!OF_CHECK_COUNTS(pna, pns)) {
+ if (!OF_CHECK_COUNTS(pna)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
break;
return 0;
}
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+ uint8_t *output, int *output_size)
+{
+ struct hash_algo *algo;
+ int ret;
+
+ ret = hash_lookup_algo(algo_name, &algo);
+ if (ret)
+ return ret;
+
+ if (output_size && *output_size < algo->digest_size) {
+ debug("Output buffer size %d too small (need %d bytes)",
+ *output_size, algo->digest_size);
+ return -ENOSPC;
+ }
+ if (output_size)
+ *output_size = algo->digest_size;
+ algo->hash_func_ws(data, len, output, algo->chunk_size);
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)
/**
* store_result: Store the resulting sum to an address or variable
*
return 0;
}
-void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
+static void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
{
int i;
printf("%02x", output[i]);
}
-int hash_block(const char *algo_name, const void *data, unsigned int len,
- uint8_t *output, int *output_size)
-{
- struct hash_algo *algo;
- int ret;
-
- ret = hash_lookup_algo(algo_name, &algo);
- if (ret)
- return ret;
-
- if (output_size && *output_size < algo->digest_size) {
- debug("Output buffer size %d too small (need %d bytes)",
- *output_size, algo->digest_size);
- return -ENOSPC;
- }
- if (output_size)
- *output_size = algo->digest_size;
- algo->hash_func_ws(data, len, output, algo->chunk_size);
-
- return 0;
-}
-
int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
return 0;
}
#endif
+#endif
if (initrd_high == ~0)
initrd_copy_to_ram = 0;
} else {
- /* not set, no restrictions to load high */
- initrd_high = ~0;
+ initrd_high = getenv_bootm_mapsize() + getenv_bootm_low();
}
}
/**********************************************************************
- * gets configuration cfgno and store it in the buffer
+ * gets len of configuration cfgno
*/
-int usb_get_configuration_no(struct usb_device *dev,
- unsigned char *buffer, int cfgno)
+int usb_get_configuration_len(struct usb_device *dev, int cfgno)
{
int result;
- unsigned int length;
+ ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, 9);
struct usb_config_descriptor *config;
config = (struct usb_config_descriptor *)&buffer[0];
"(expected %i, got %i)\n", 9, result);
return -EIO;
}
- length = le16_to_cpu(config->wTotalLength);
+ return le16_to_cpu(config->wTotalLength);
+}
- if (length > USB_BUFSIZ) {
- printf("%s: failed to get descriptor - too long: %d\n",
- __func__, length);
- return -EIO;
- }
+/**********************************************************************
+ * gets configuration cfgno and store it in the buffer
+ */
+int usb_get_configuration_no(struct usb_device *dev, int cfgno,
+ unsigned char *buffer, int length)
+{
+ int result;
+ struct usb_config_descriptor *config;
+ config = (struct usb_config_descriptor *)&buffer[0];
result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length);
- debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, length);
- config->wTotalLength = length; /* validated, with CPU byte order */
+ debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result,
+ le16_to_cpu(config->wTotalLength));
+ config->wTotalLength = result; /* validated, with CPU byte order */
return result;
}
int usb_select_config(struct usb_device *dev)
{
- ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ);
+ unsigned char *tmpbuf = 0;
int err;
err = get_descriptor_len(dev, USB_DT_DEVICE_SIZE, USB_DT_DEVICE_SIZE);
le16_to_cpus(&dev->descriptor.bcdDevice);
/* only support for one config for now */
- err = usb_get_configuration_no(dev, tmpbuf, 0);
+ err = usb_get_configuration_len(dev, 0);
+ if (err >= 0) {
+ tmpbuf = (unsigned char *)malloc_cache_aligned(err);
+ if (!tmpbuf)
+ err = -ENOMEM;
+ else
+ err = usb_get_configuration_no(dev, 0, tmpbuf, err);
+ }
if (err < 0) {
printf("usb_new_device: Cannot read configuration, " \
"skipping device %04x:%04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
+ free(tmpbuf);
return err;
}
usb_parse_config(dev, tmpbuf, 0);
+ free(tmpbuf);
usb_set_maxpacket(dev);
/*
* we set the default configuration here
#endif
}
+#ifdef CONFIG_DM_USB
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+ uint8_t *hub_address, uint8_t *hub_port)
+{
+ struct udevice *parent;
+ struct usb_device *uparent, *ttdev;
+
+ /*
+ * When called from usb-uclass.c: usb_scan_device() udev->dev points
+ * to the parent udevice, not the actual udevice belonging to the
+ * udev as the device is not instantiated yet. So when searching
+ * for the first usb-2 parent start with udev->dev not
+ * udev->dev->parent .
+ */
+ ttdev = udev;
+ parent = udev->dev;
+ uparent = dev_get_parent_priv(parent);
+
+ while (uparent->speed != USB_SPEED_HIGH) {
+ struct udevice *dev = parent;
+
+ if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
+ printf("Error: Cannot find high speed parent of usb-1 device\n");
+ *hub_address = 0;
+ *hub_port = 0;
+ return;
+ }
+
+ ttdev = dev_get_parent_priv(dev);
+ parent = dev->parent;
+ uparent = dev_get_parent_priv(parent);
+ }
+ *hub_address = uparent->devnum;
+ *hub_port = ttdev->portnr;
+}
+#else
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+ uint8_t *hub_address, uint8_t *hub_port)
+{
+ /* Find out the nearest parent which is high speed */
+ while (udev->parent->parent != NULL)
+ if (udev->parent->speed != USB_SPEED_HIGH) {
+ udev = udev->parent;
+ } else {
+ *hub_address = udev->parent->devnum;
+ *hub_port = udev->portnr;
+ return;
+ }
+
+ printf("Error: Cannot find high speed parent of usb-1 device\n");
+ *hub_address = 0;
+ *hub_port = 0;
+}
+#endif
+
+
/* EOF */
return ret;
}
+static int usb_kbd_remove(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct usb_kbd_pdata *data;
+ struct stdio_dev *sdev;
+ int ret;
+
+ sdev = stdio_get_by_name(DEVNAME);
+ if (!sdev) {
+ ret = -ENXIO;
+ goto err;
+ }
+ data = udev->privptr;
+ if (stdio_deregister_dev(sdev, true)) {
+ ret = -EPERM;
+ goto err;
+ }
+#ifdef CONFIG_CONSOLE_MUX
+ if (iomux_doenv(stdin, getenv("stdin"))) {
+ ret = -ENOLINK;
+ goto err;
+ }
+#endif
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+ destroy_int_queue(udev, data->intq);
+#endif
+ free(data->new);
+ free(data);
+
+ return 0;
+err:
+ printf("%s: warning, ret=%d", __func__, ret);
+ return ret;
+}
+
static const struct udevice_id usb_kbd_ids[] = {
{ .compatible = "usb-keyboard" },
{ }
.id = UCLASS_KEYBOARD,
.of_match = usb_kbd_ids,
.probe = usb_kbd_probe,
+ .remove = usb_kbd_remove,
};
static const struct usb_device_id kbd_id_table[] = {
static ccb usb_ccb __attribute__((aligned(ARCH_DMA_MINALIGN)));
static __u32 CBWTag;
-#define USB_MAX_STOR_DEV 5
+#define USB_MAX_STOR_DEV 7
static int usb_max_devs; /* number of highest available usb device */
static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
+CONFIG_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
+CONFIG_FIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTD is not set
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC3_CD_PIN="PH0"
+CONFIG_MMC3_PINS="PH"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_EMR1=0
+CONFIG_MMC0_CD_PIN="PG0"
+CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_USB0_VBUS_DET="PG1"
+CONFIG_USB0_ID_DET="PG2"
+CONFIG_AXP_GPIO=y
+# CONFIG_VIDEO_HDMI is not set
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SUNXI_NO_PMIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DM_MMC=y
CONFIG_ROCKCHIP_DWMMC=y
CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
CONFIG_ROCKCHIP_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_BASE=0x20068000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN8I_H3=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
# CONFIG_VIDEO is not set
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_LD4=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_LD6B=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld6b-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_PRO4=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_PRO5=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro5-4kbox"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_ARCH_UNIPHIER_PH1_SLD3=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_SIMPLE_BUS=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_UNIPHIER_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_MMC=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_LD4=y
+CONFIG_ARCH_UNIPHIER_PH1_SLD8=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_PRO4=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PH1_PRO5=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro5-4kbox"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_PROXSTREAM2=y
+CONFIG_ARCH_UNIPHIER_PH1_LD6B=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_ARCH_UNIPHIER_PH1_SLD3=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NAND_DENALI=y
+CONFIG_SYS_NAND_DENALI_64BIT=y
+CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
+CONFIG_SPL_NAND_DENALI=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
/* Convert char[4] in little endian format to the host format integer
*/
-static inline int le32_to_int(unsigned char *le32)
+static inline unsigned int le32_to_int(unsigned char *le32)
{
return ((le32[3] << 24) +
(le32[2] << 16) +
return p->boot_ind == 0x80;
}
-static void print_one_part(dos_partition_t *p, int ext_part_sector,
+static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
int part_num, unsigned int disksig)
{
- int lba_start = ext_part_sector + le32_to_int (p->start4);
- int lba_size = le32_to_int (p->size4);
+ lbaint_t lba_start = ext_part_sector + le32_to_int (p->start4);
+ lbaint_t lba_size = le32_to_int (p->size4);
- printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
+ printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength
+ "u\t%08x-%02x\t%02x%s%s\n",
part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
(is_bootable(p) ? " Boot" : ""));
/* Print a partition that is relative to its Extended partition table
*/
static void print_partition_extended(block_dev_desc_t *dev_desc,
- int ext_part_sector, int relative,
+ lbaint_t ext_part_sector,
+ lbaint_t relative,
int part_num, unsigned int disksig)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
int i;
if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return;
}
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
print_partition_extended(dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
/* Print a partition that is relative to its Extended partition table
*/
-static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector,
- int relative, int part_num,
+static int get_partition_info_extended (block_dev_desc_t *dev_desc,
+ lbaint_t ext_part_sector,
+ lbaint_t relative, int part_num,
int which_part, disk_partition_t *info,
unsigned int disksig)
{
int dos_type;
if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
- printf ("** Can't read partition table on %d:%d **\n",
+ printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->dev, ext_part_sector);
return -1;
}
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if (is_extended (pt->sys_ind)) {
- int lba_start = le32_to_int (pt->start4) + relative;
+ lbaint_t lba_start
+ = le32_to_int (pt->start4) + relative;
return get_partition_info_extended (dev_desc, lba_start,
ext_part_sector == 0 ? lba_start : relative,
Reading bank 4:
Word 0x00000002: 9f027772 00000004
+
+2. Using imx_usb_loader for first install with SPL
+--------------------------------------------------
+
+imx_usb_loader is a very nice tool by BoundaryDevice that
+allow to install U-Boot without a JTAG debugger, using
+the USB boot mode as described in the manual. It is
+a replacement for Freescale's MFGTOOLS.
+
+The sources can be found here:
+
+ https://github.com/boundarydevices/imx_usb_loader.git
+
+Booting in USB mode, the i.MX6 announces itself to the Linux Host as:
+
+Bus 001 Device 111: ID 15a2:0061 Freescale Semiconductor, Inc.
+
+imx_usb_loader is able to download a single file (u-boot.imx)
+to the board. For boards without SPL support, it is enough to
+issue the command:
+
+ sudo ../imx_usb_loader/imx_usb -v u-boot.imx
+
+Getting U-Boot when SPL support is active, it requires
+two downloads. imx_usb_loader downloads the SPL into
+OCRAM and starts it. SPL will check for a valid u-boot.img, and
+because it is not found, it will wait for it using the y-modem
+protocol via the console.
+
+A first install is then possible by combining imx_usb_loader with
+another tool such as kermit.
+
+sudo ../imx_usb_loader/imx_usb -v SPL
+kermit kermit_uboot
+
+and kermit_uboot contains something like this (set line should be adjusted):
+
+set line /dev/ttyUSB1
+set speed 115200
+SET CARRIER-WATCH OFF
+set flow-control none
+set handshake none
+set prefixing all
+set file type bin
+set protocol ymodem
+send u-boot.img
+c
+
+The last "c" command tells kermit (from ckermit package in most distros)
+to switch from command line mode to communication mode, and when the
+script is finished, the U-Boot prompt is shown in the same shell.
To write an image that boots from SPI flash (e.g. for the Haier Chromebook):
- ./chromebook_jerry/tools/mkimage -n rk3036 -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out
- dd if=spl.bin of=out.bin bs=128K conv=sync
- cat chromebook_jerry/u-boot-dtb.img out.bin
+ ./chromebook_jerry/tools/mkimage -n rk3288 -T rkspi \
+ -d chromebook_jerry/spl/u-boot-spl-dtb.bin spl.bin && \
+ dd if=spl.bin of=spl-out.bin bs=128K conv=sync && \
+ cat spl-out.bin chromebook_jerry/u-boot-dtb.img >out.bin && \
dd if=out.bin of=out.bin.pad bs=4M conv=sync
This converts the SPL image to the required SPI format by adding the Rockchip
Compile the source
------------------
-PH1-sLD3:
- $ make ph1_sld3_defconfig
+PH1-sLD3 reference board:
+ $ make uniphier_sld3_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-LD4:
- $ make ph1_ld4_defconfig
+PH1-LD4 reference board:
+ $ make uniphier_ld4_sld8_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-Pro4:
- $ make ph1_pro4_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+PH1-sLD8 reference board:
+ $ make uniphier_ld4_sld8_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref
-PH1-sLD8:
- $ make ph1_sld8_defconfig
+PH1-Pro4 reference board:
+ $ make uniphier_pro4_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-PH1-Pro5:
- $ make ph1_pro5_defconfig
+PH1-Pro5 4KBOX Board:
+ $ make uniphier_pro5_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
-ProXstream2:
- $ make pxs2_defconfig
- $ make CROSS_COMPILE=arm-linux-gnueabi-
+ProXstream2 Gentil board:
+ $ make uniphier_pxs2_ld6b_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil
-PH1-LD6b:
- $ make ph1_ld6b_defconfig
+ProXstream2 Vodka board:
+ $ make uniphier_pxs2_ld6b_defconfig
$ make CROSS_COMPILE=arm-linux-gnueabi-
+PH1-LD6b reference board:
+ $ make uniphier_pxs2_ld6b_defconfig
+ $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref
+
You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-"
to use your favorite compiler.
SW8 OFF(1)/ON(0) Description
------------------------------------------
- bit 1 ----> CS1_SPLIT
+ bit 1 <---- CS1_SPLIT
bit 2 <---- CASE9_ON
bit 3 <---- CASE10_ON
bit 4 Don't Care Reserve
About 16 of 33 serial drivers have been converted as at September 2015. It
is time for maintainers to start converting over the remaining serial drivers:
- altera_jtag_uart.c
- altera_uart.c
arm_dcc.c
lpc32xx_hsuart.c
mcfuart.c
alias bmeng Bin Meng <bmeng.cn@gmail.com>
alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
alias galak Kumar Gala <galak@kernel.crashing.org>
-alias gruss Graeme Russ <graeme.russ@gmail.com>
alias hs Heiko Schocher <hs@denx.de>
alias ijc Ian Campbell <ijc+uboot@hellion.org.uk>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias superh uboot, iwamatsu
alias sh superh
-alias x86 uboot, sjg, gruss, bmeng
+alias x86 uboot, sjg, bmeng
# Subsystem aliases
alias dm uboot, sjg
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev = probe_ent->dev;
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+# else
pci_dev_t pdev = probe_ent->dev;
- u16 tmp16;
unsigned short vendor;
+# endif
+ u16 tmp16;
#endif
void __iomem *mmio = probe_ent->mmio_base;
u32 tmp, cap_save, cmd;
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
+ u16 tmp16;
+
+ dm_pci_read_config16(dev, 0x92, &tmp16);
+ dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
+ }
+# else
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
+# endif
#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
+ tmp |= PCI_COMMAND_MASTER;
+ dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
+# else
pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
+# endif
#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev = probe_ent->dev;
+# else
pci_dev_t pdev = probe_ent->dev;
+# endif
u16 cc;
#endif
void __iomem *mmio = probe_ent->mmio_base;
#ifdef CONFIG_SCSI_AHCI_PLAT
scc_s = "SATA";
#else
+# ifdef CONFIG_DM_PCI
+ dm_pci_read_config16(dev, 0x0a, &cc);
+# else
pci_read_config_word(pdev, 0x0a, &cc);
+# endif
if (cc == 0x0101)
scc_s = "IDE";
else if (cc == 0x0106)
}
#ifndef CONFIG_SCSI_AHCI_PLAT
-static int ahci_init_one(pci_dev_t pdev)
+# ifdef CONFIG_DM_PCI
+static int ahci_init_one(struct udevice *dev)
+# else
+static int ahci_init_one(pci_dev_t dev)
+# endif
{
u16 vendor;
int rc;
}
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
- probe_ent->dev = pdev;
+ probe_ent->dev = dev;
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
+#ifdef CONFIG_DM_PCI
+ probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
+ PCI_REGION_MEM);
+
+ /* Take from kernel:
+ * JMicron-specific fixup:
+ * make sure we're in AHCI mode
+ */
+ dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
+ if (vendor == 0x197b)
+ dm_pci_write_config8(dev, 0x41, 0xa1);
+#else
+ probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
- debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* Take from kernel:
* JMicron-specific fixup:
* make sure we're in AHCI mode
*/
- pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+ pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
if (vendor == 0x197b)
- pci_write_config_byte(pdev, 0x41, 0xa1);
+ pci_write_config_byte(dev, 0x41, 0xa1);
+#endif
+ debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* initialize adapter */
rc = ahci_host_init(probe_ent);
if (rc)
u32 linkmap;
#ifndef CONFIG_SCSI_AHCI_PLAT
+# ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+ int ret;
+
+ ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
+ if (ret)
+ return;
+ ahci_init_one(dev);
+# else
ahci_init_one(busdevfunc);
+# endif
#endif
linkmap = probe_ent->link_port_map;
#if defined(CONFIG_MPC8260)
#include <asm/cpm_8260.h>
-
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
#endif /* defined(CONFIG_MPC8260) */
#if defined(CONFIG_QE)
#include <linux/immap_qe.h>
-
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
QE_MURAM_SIZE - 2 * sizeof(u32))
-#endif /* defined(CONFIG_MPC8360) */
+#endif /* defined(CONFIG_QE) */
#if defined(CONFIG_4xx)
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \
#else
raw_bootcount_store(reg, a);
raw_bootcount_store(reg + 4, BOOTCOUNT_MAGIC);
-#endif
+#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD */
}
__weak ulong bootcount_load(void)
return 0;
else
return raw_bootcount_load(reg);
-#endif
+#endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) */
}
-#endif
+#endif /* defined(CONFIG_SYS_BOOTCOUNT_ADDR) */
return dev->uclass->uc_drv->name;
}
-fdt_addr_t dev_get_addr(struct udevice *dev)
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
fdt_addr_t addr;
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
const fdt32_t *reg;
+ int len = 0;
+ int na, ns;
+
+ na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (na < 1) {
+ debug("bad #address-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
+
+ ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ if (ns < 0) {
+ debug("bad #size-cells\n");
+ return FDT_ADDR_T_NONE;
+ }
- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
- if (!reg)
+ reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+ if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
+ debug("Req index out of range\n");
return FDT_ADDR_T_NONE;
+ }
+
+ reg += index * (na + ns);
/*
* Use the full-fledged translate function for complex
* bus setups.
*/
- return fdt_translate_address((void *)gd->fdt_blob,
+ addr = fdt_translate_address((void *)gd->fdt_blob,
dev->of_offset, reg);
+ } else {
+ /*
+ * Use the "simple" translate function for less complex
+ * bus setups.
+ */
+ addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
+ dev->parent->of_offset,
+ dev->of_offset, "reg",
+ index, NULL);
+ if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
+ if (device_get_uclass_id(dev->parent) ==
+ UCLASS_SIMPLE_BUS)
+ addr = simple_bus_translate(dev->parent, addr);
+ }
}
/*
- * Use the "simple" translate function for less complex
- * bus setups.
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling dm_set_translation_offset() that
+ * will get added to all addresses returned by dev_get_addr().
*/
- addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev->parent->of_offset,
- dev->of_offset, "reg",
- 0, NULL);
- if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
- if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
- addr = simple_bus_translate(dev->parent, addr);
- }
+ addr += dm_get_translation_offset();
return addr;
#else
#endif
}
+fdt_addr_t dev_get_addr(struct udevice *dev)
+{
+ return dev_get_addr_index(dev, 0);
+}
+
bool device_has_children(struct udevice *dev)
{
return !list_empty(&dev->child_head);
DECLARE_GLOBAL_DATA_PTR;
+struct root_priv {
+ fdt_addr_t translation_offset; /* optional translation offset */
+};
+
static const struct driver_info root_info = {
.name = "root_driver",
};
return gd->dm_root;
}
+fdt_addr_t dm_get_translation_offset(void)
+{
+ struct udevice *root = dm_root();
+ struct root_priv *priv = dev_get_priv(root);
+
+ return priv->translation_offset;
+}
+
+void dm_set_translation_offset(fdt_addr_t offs)
+{
+ struct udevice *root = dm_root();
+ struct root_priv *priv = dev_get_priv(root);
+
+ priv->translation_offset = offs;
+}
+
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fix_drivers(void)
{
U_BOOT_DRIVER(root_driver) = {
.name = "root_driver",
.id = UCLASS_ROOT,
+ .priv_auto_alloc_size = sizeof(struct root_priv),
};
/* This is the root uclass */
{
return 0;
}
+
+int name_to_gpio(const char *name)
+{
+ unsigned bank, pin;
+ char *end;
+
+ bank = simple_strtoul(name, &end, 10);
+
+ if (!*end || *end != ':')
+ return bank;
+
+ pin = simple_strtoul(end + 1, NULL, 10);
+
+ return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
+}
return;
}
- mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
- mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
+ /*
+ * Warning: Be careful to allow the assignment to a static
+ * variable here. This function could be called while U-Boot is
+ * still running in flash memory. So such assignment is equal
+ * to write data to flash without erasing.
+ */
+ if (idle_bus_fn)
+ mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
+ if (idle_bus_data)
+ mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
ret = enable_i2c_clk(1, index);
if (ret < 0) {
clk = (pre_div << 8) | (div << 4);
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+#else
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
+#endif
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
- clk = SYSCTL_PEREN | SYSCTL_CKEN;
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA);
+#else
+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
- esdhc_setbits32(®s->sysctl, clk);
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
esdhc_write32(®s->scr, 0x00000040);
#endif
+#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#endif
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000);
/* First reset the eSDHC controller */
esdhc_reset(regs);
+#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
+#endif
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
goto err_out;
cmd.cmdidx = MMC_CMD_ERASE;
- cmd.cmdarg = SECURE_ERASE;
+ cmd.cmdarg = MMC_ERASE_ARG;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, &cmd, NULL);
#include <sdhci.h>
#include <asm/pci.h>
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids)
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
{
struct sdhci_host *mmc_host;
- pci_dev_t devbusfn;
u32 iobase;
int ret;
int i;
- for (i = 0; i < num_ids; i++) {
- devbusfn = pci_find_devices(mmc_supported, i);
- if (devbusfn == -1)
- return -ENODEV;
+ for (i = 0; ; i++) {
+ struct udevice *dev;
+ ret = pci_find_device_id(mmc_supported, i, &dev);
+ if (ret)
+ return ret;
mmc_host = malloc(sizeof(struct sdhci_host));
if (!mmc_host)
return -ENOMEM;
mmc_host->name = (char *)name;
- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
mmc_host->ioaddr = (void *)iobase;
mmc_host->quirks = 0;
ret = add_sdhci(mmc_host, 0, 0);
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
+ u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
+ ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
/* Disable SDMMC clock. */
clrbits_le32(&clock_manager_base->per_pll.en,
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
- &system_manager_base->sdmmcgrp_ctrl);
+ writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(&system_manager_base->sdmmcgrp_ctrl));
*/
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <errno.h>
#include <fdt_support.h>
unsigned long size;
};
+static uint flash_verbose;
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
putc('\n');
}
+void flash_set_verbose(uint v)
+{
+ flash_verbose = v;
+}
+
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
struct mtd_info *mtd = info->mtd;
int ret;
memset(&instr, 0, sizeof(instr));
+ instr.mtd = mtd;
instr.addr = mtd->erasesize * s_first;
instr.len = mtd->erasesize * (s_last + 1 - s_first);
+ flash_set_verbose(1);
ret = mtd_erase(mtd, &instr);
+ flash_set_verbose(0);
if (ret)
return ERR_PROTECTED;
+ puts(" done\n");
return 0;
}
size_t end = addr + len;
u32 sect;
u32 stat;
+ u32 *flash, *last;
instr->state = MTD_ERASING;
addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
while (addr < end) {
- sect = addr / mtd->erasesize;
- sect <<= 8;
- sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
- debug("erase %08x\n", sect);
- writel(sect, ®s->mem_op);
- stat = readl(®s->isr);
- if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
- /* erase failed, sector might be protected */
- debug("erase %08x fail %x\n", sect, stat);
- writel(stat, ®s->isr); /* clear isr */
+ if (ctrlc()) {
+ if (flash_verbose)
+ putc('\n');
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
instr->state = MTD_ERASE_FAILED;
+ mtd_erase_callback(instr);
return -EIO;
}
+ flash = pdata->base + addr;
+ last = pdata->base + addr + mtd->erasesize;
+ /* skip erase if sector is blank */
+ while (flash < last) {
+ if (readl(flash) != 0xffffffff)
+ break;
+ flash++;
+ }
+ if (flash < last) {
+ sect = addr / mtd->erasesize;
+ sect <<= 8;
+ sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
+ debug("erase %08x\n", sect);
+ writel(sect, ®s->mem_op);
+ stat = readl(®s->isr);
+ if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
+ /* erase failed, sector might be protected */
+ debug("erase %08x fail %x\n", sect, stat);
+ writel(stat, ®s->isr); /* clear isr */
+ instr->fail_addr = addr;
+ instr->state = MTD_ERASE_FAILED;
+ mtd_erase_callback(instr);
+ return -EIO;
+ }
+ if (flash_verbose)
+ putc('.');
+ } else {
+ if (flash_verbose)
+ putc(',');
+ }
addr += mtd->erasesize;
}
instr->state = MTD_ERASE_DONE;
void spi_flash_free(struct spi_flash *flash)
{
- spi_flash_remove(flash->spi->dev);
+ device_remove(flash->spi->dev);
}
int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
return 0;
}
-int spi_flash_remove(struct udevice *dev)
-{
- return device_remove(dev);
-}
-
static int spi_flash_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
enum spi_dual_flash {
SF_SINGLE_FLASH = 0,
- SF_DUAL_STACKED_FLASH = 1 << 0,
- SF_DUAL_PARALLEL_FLASH = 1 << 1,
+ SF_DUAL_STACKED_FLASH = BIT(0),
+ SF_DUAL_PARALLEL_FLASH = BIT(1),
};
/* Enum list - Full read commands */
enum spi_read_cmds {
- ARRAY_SLOW = 1 << 0,
- ARRAY_FAST = 1 << 1,
- DUAL_OUTPUT_FAST = 1 << 2,
- DUAL_IO_FAST = 1 << 3,
- QUAD_OUTPUT_FAST = 1 << 4,
- QUAD_IO_FAST = 1 << 5,
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ QUAD_OUTPUT_FAST = BIT(3),
+ DUAL_IO_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
};
/* Normal - Extended - Full command set */
/* sf param flags */
enum {
-#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
- SECT_4K = 1 << 0,
+#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
+ SECT_4K = 0,
#else
- SECT_4K = 0 << 0,
+ SECT_4K = BIT(0),
#endif
- SECT_32K = 1 << 1,
- E_FSR = 1 << 2,
- SST_WR = 1 << 3,
- WR_QPP = 1 << 4,
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_WR = BIT(3),
+ WR_QPP = BIT(4),
};
enum spi_nor_option_flags {
- SNOR_F_SST_WR = (1 << 0),
- SNOR_F_USE_FSR = (1 << 1),
+ SNOR_F_SST_WR = BIT(0),
+ SNOR_F_USE_FSR = BIT(1),
};
#define SPI_FLASH_3B_ADDR_LEN 3
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS1 0x35
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
#endif
/* Common status */
-#define STATUS_WIP (1 << 0)
-#define STATUS_QEB_WINSPAN (1 << 1)
-#define STATUS_QEB_MXIC (1 << 6)
-#define STATUS_PEC (1 << 7)
+#define STATUS_WIP BIT(0)
+#define STATUS_QEB_WINSPAN BIT(1)
+#define STATUS_QEB_MXIC BIT(6)
+#define STATUS_PEC BIT(7)
+#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (flash->spi->mode & SPI_TX_BYTE)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
cmd[3] = addr >> 0;
}
-/* Read commands array */
-static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_QUAD_IO_FAST,
-};
-
static int read_sr(struct spi_flash *flash, u8 *rs)
{
int ret;
}
#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int read_evcr(struct spi_flash *flash, u8 *evcr)
+{
+ int ret;
+ const u8 cmd = CMD_READ_EVCR;
+
+ ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
+ if (ret < 0) {
+ debug("SF: error reading EVCR\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int write_evcr(struct spi_flash *flash, u8 evcr)
+{
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_WRITE_EVCR;
+ ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
+ if (ret < 0) {
+ debug("SF: error while writing EVCR register\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
{
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bank_end;
+ goto bar_end;
switch (idcode0) {
case SPI_FLASH_CFI_MFR_SPANSION:
return ret;
}
-bank_end:
+bar_end:
flash->bank_curr = curr_bank;
return 0;
}
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
+ struct spi_slave *spi = flash->spi;
+
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- flash->spi->flags |= SPI_XFER_U_PAGE;
+ spi->flags |= SPI_XFER_U_PAGE;
} else {
- flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ spi->flags &= ~SPI_XFER_U_PAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
if (buf == NULL)
timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
byte_addr = offset % page_size;
chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
- if (flash->spi->max_write_size)
+ if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
+ (size_t)spi->max_write_size);
spi_flash_addr(write_addr, cmd);
struct spi_slave *spi = flash->spi;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ struct spi_slave *spi = flash->spi;
u8 *cmd, cmdsz;
u32 remain_len, read_len, read_addr;
int bank_sel = 0;
/* Handle memory-mapped SPI */
if (flash->memory_map) {
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
}
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
spi_flash_copy_mmap(data, flash->memory_map + offset, len);
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
- spi_release_bus(flash->spi);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+ spi_release_bus(spi);
return 0;
}
#ifdef CONFIG_SPI_FLASH_SST
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
int ret;
u8 cmd[4] = {
CMD_SST_BP,
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
return ret;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
if (ret)
return ret;
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual, cmd_len;
int ret;
u8 cmd[4];
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
cmd[0], offset);
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len,
buf + actual, 2);
if (ret) {
debug("SF: sst word program failed\n");
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
#endif
return ret;
/* Cannot unlock; would unlock larger region than requested */
- if (stm_is_locked_sr(flash, status_old, ofs - flash->erase_size,
- flash->erase_size))
+ if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size,
+ status_old))
return -EINVAL;
/*
* Need largest pow such that:
#ifdef CONFIG_SPI_FLASH_MACRONIX
-static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+static int macronix_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_MXIC) {
- debug("SF: mxic: QEB is already set\n");
- } else {
- ret = write_sr(flash, STATUS_QEB_MXIC);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_MXIC)
+ return 0;
+
+ ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+
+ /* read SR and check it */
+ ret = read_sr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
+ printf("SF: Macronix SR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_WINSPAN) {
- debug("SF: winspan: QEB is already set\n");
- } else {
- ret = write_cr(flash, STATUS_QEB_WINSPAN);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_WINSPAN)
+ return 0;
+
+ ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+
+ /* read CR and check it */
+ ret = read_cr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
+ printf("SF: Spansion CR Quad bit not clear\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int micron_quad_enable(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = read_evcr(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (!(qeb_status & STATUS_QEB_MICRON))
+ return 0;
+
+ ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
+ if (ret < 0)
+ return ret;
+
+ /* read EVCR and check it */
+ ret = read_evcr(flash, &qeb_status);
+ if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
+ printf("SF: Micron EVCR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
}
#endif
-static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
- return spi_flash_set_qeb_mxic(flash);
+ return macronix_quad_enable(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
- return spi_flash_set_qeb_winspan(flash);
+ return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- debug("SF: QEB is volatile for %02x flash\n", idcode0);
- return 0;
+ return micron_quad_enable(flash);
#endif
default:
printf("SF: Need set QEB func for %02x flash\n", idcode0);
struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params;
u16 jedec, ext_jedec;
- u8 idcode[5];
- u8 cmd;
+ u8 cmd, idcode[5];
int ret;
+ static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_ARRAY_FAST,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_IO_FAST };
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
/* Assign spi data */
flash->name = params->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = flash->spi->option;
+ flash->dual_flash = spi->option;
/* Assign spi flash flags */
if (params->flags & SST_WR)
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (spi->mode & SPI_TX_BYTE)
flash->write = sst_write_bp;
else
flash->write = sst_write_wp;
flash->sector_size = flash->erase_size;
/* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ cmd = fls(params->e_rd_cmd & spi->mode_rx);
if (cmd) {
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
}
/* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = spi_flash_set_qeb(flash, idcode[0]);
+ ret = set_quad_mode(flash, idcode[0]);
if (ret) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
return -EINVAL;
ubi_err(ubi, "self-check failed for PEB %d:%d, len %d",
pnum, offset, len);
ubi_msg(ubi, "data differ at position %d", i);
- dump_len = max_t(int, 128, len - i);
ubi_msg(ubi, "hex dump of the original buffer from %d to %d",
i, i + dump_len);
print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1,
config ETH_DESIGNWARE
bool "Synopsys Designware Ethernet MAC"
+ select PHYLIB
help
This MAC is present in SoCs from various vendors. It supports
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_PHYLIB)
-# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
-#endif
-
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct eth_mac_regs *mac_p = bus->priv;
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
- DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
- DESC_TXSTS_TXCHECKINSCTRL | \
+ DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
+ DESC_TXSTS_TXCHECKINSCTRL |
DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
desc_p->dmamac_next = &desc_table_p[idx + 1];
desc_p->dmamac_cntl =
- (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
+ (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
DESC_RXCTRL_RXCHAIN;
desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
- desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
+ desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
DESC_TXCTRL_SIZE1MASK;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
- desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
- DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
+ desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
/* Check if the owner is the CPU */
if (!(status & DESC_RXSTS_OWNBYDMA)) {
- length = (status & DESC_RXSTS_FRMLENMSK) >> \
+ length = (status & DESC_RXSTS_FRMLENMSK) >>
DESC_RXSTS_FRMLENSHFT;
/* Invalidate received data */
* or via a PCI bridge, fill in platdata before we probe the hardware.
*/
if (device_is_on_pci_bus(dev)) {
- pci_dev_t bdf = pci_get_bdf(dev);
+ pci_dev_t bdf = dm_pci_get_bdf(dev);
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
invalidate_dcache_range(inval_start, inval_end);
- if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
+ if (!(rd->status & E1000_RXD_STAT_DD))
return 0;
/* DEBUGOUT("recv: packet len=%d\n", rd->length); */
/* Packet received, make sure the data are re-loaded from RAM. */
- len = le32_to_cpu(rd->length);
+ len = le16_to_cpu(rd->length);
invalidate_dcache_range((unsigned long)packet,
(unsigned long)packet +
roundup(len, ARCH_DMA_MINALIGN));
int ret;
hw->name = dev->name;
- ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev),
- plat->enetaddr);
+ ret = e1000_init_one(hw, trailing_strtol(dev->name),
+ dm_pci_get_bdf(dev), plat->enetaddr);
if (ret < 0) {
printf(pr_fmt("failed to initialize card: %d\n"), ret);
return ret;
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+ *
+ * The i.MX28 and i.MX6 types have another field in the MSCR (aka
+ * MII_SPEED) register that defines the MDIO output hold time. Earlier
+ * versions are RAZ there, so just ignore the difference and write the
+ * register always.
+ * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
+ * HOLDTIME + 1 is the number of clk cycles the fec is holding the
+ * output.
+ * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
+ * Given that ceil(clkrate / 5000000) <= 64, the calculation for
+ * holdtime cannot result in a value greater than 3.
*/
- register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
+ u32 pclk = imx_get_fecclk();
+ u32 speed = DIV_ROUND_UP(pclk, 5000000);
+ u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
#ifdef FEC_QUIRK_ENET_MAC
speed--;
#endif
- speed <<= 1;
- writel(speed, ð->mii_speed);
+ writel(speed << 1 | hold << 8, ð->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
}
#ifdef CONFIG_PHYLIB
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
+ mdio_unregister(bus);
free(bus);
return -ENOMEM;
}
#ifdef CONFIG_PHYLIB
free(phydev);
#endif
+ mdio_unregister(bus);
free(bus);
}
return ret;
pci_dev_t devno;
u32 iobase;
- devno = pci_get_bdf(dev);
+ devno = dm_pci_get_bdf(dev);
/*
* The priv structure contains the descriptors and frame buffers which
.uid = 0x4dd074,
.mask = 0xffffffef,
.features = PHY_GBIT_FEATURES,
- .config = ar8021_config,
+ .config = ar8035_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
*/
#include <config.h>
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
#include <micrel.h>
#include <phy.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static struct phy_driver KSZ804_driver = {
.name = "Micrel KSZ804",
.uid = 0x221510,
return 0;
}
+/* Common OF config bits for KSZ9021 and KSZ9031 */
+#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
+#ifdef CONFIG_DM_ETH
+struct ksz90x1_reg_field {
+ const char *name;
+ const u8 size; /* Size of the bitfield, in bits */
+ const u8 off; /* Offset from bit 0 */
+ const u8 dflt; /* Default value */
+};
+
+struct ksz90x1_ofcfg {
+ const u16 reg;
+ const u16 devad;
+ const struct ksz90x1_reg_field *grp;
+ const u16 grpsz;
+};
+
+static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
+ { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
+ { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
+};
+
+static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
+ { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
+ { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz90x1_of_config_group(struct phy_device *phydev,
+ struct ksz90x1_ofcfg *ofcfg)
+{
+ struct udevice *dev = phydev->dev;
+ struct phy_driver *drv = phydev->drv;
+ const int ps_to_regval = 200;
+ int val[4];
+ int i, changed = 0, offset, max;
+ u16 regval = 0;
+
+ if (!drv || !drv->writeext)
+ return -EOPNOTSUPP;
+
+ for (i = 0; i < ofcfg->grpsz; i++) {
+ val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ ofcfg->grp[i].name, -1);
+ offset = ofcfg->grp[i].off;
+ if (val[i] == -1) {
+ /* Default register value for KSZ9021 */
+ regval |= ofcfg->grp[i].dflt << offset;
+ } else {
+ changed = 1; /* Value was changed in OF */
+ /* Calculate the register value and fix corner cases */
+ if (val[i] > ps_to_regval * 0xf) {
+ max = (1 << ofcfg->grp[i].size) - 1;
+ regval |= max << offset;
+ } else {
+ regval |= (val[i] / ps_to_regval) << offset;
+ }
+ }
+ }
+
+ if (!changed)
+ return 0;
+
+ return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
+}
+#endif
+#endif
+
#ifdef CONFIG_PHY_MICREL_KSZ9021
/*
* KSZ9021
#define CTRL1000_CONFIG_MASTER (1 << 11)
#define CTRL1000_MANUAL_CONFIG (1 << 12)
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
+ { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
+ { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+ struct ksz90x1_ofcfg ofcfg[] = {
+ { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
+ { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
+ { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
+ };
+ int i, ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+ ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#else
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+ return 0;
+}
+#endif
+
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
{
/* extended registers */
const unsigned master = CTRL1000_PREFER_MASTER |
CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
unsigned features = phydev->drv->features;
+ int ret;
+
+ ret = ksz9021_of_config(phydev);
+ if (ret)
+ return ret;
if (getenv("disable_giga"))
features &= ~(SUPPORTED_1000baseT_Half |
#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
#define MII_KSZ9031_MMD_REG_DATA 0x0e
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
+ { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
+static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
+ { { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+ struct ksz90x1_ofcfg ofcfg[] = {
+ { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
+ { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
+ { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
+ { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
+ };
+ int i, ret = 0;
+
+ for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+ ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#else
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+ return 0;
+}
+#endif
+
/* Accessors to extended registers*/
int ksz9031_phy_extended_write(struct phy_device *phydev,
int devaddr, int regnum, u16 mode, u16 val)
MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
};
+static int ksz9031_config(struct phy_device *phydev)
+{
+ int ret;
+ ret = ksz9031_of_config(phydev);
+ if (ret)
+ return ret;
+ return genphy_config(phydev);
+}
static struct phy_driver ksz9031_driver = {
.name = "Micrel ksz9031",
.uid = 0x221620,
.mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
- .config = &genphy_config,
+ .config = &ksz9031_config,
.startup = &ksz90xx_startup,
.shutdown = &genphy_shutdown,
.writeext = &ksz9031_phy_extwrite,
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
-static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
+#ifdef CONFIG_DM_ETH
+static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
+ uchar **packetp)
+#else
+static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
uchar **packetp)
+#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
+#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
- pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)
+ dm_pci_mem_to_phys(dev,
+ (pci_addr_t)(unsigned long)
+ tpc->RxBufferRing[cur_rx]));
+#else
+ tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
+ pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
+#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
#ifdef CONFIG_DM_ETH
*packetp = rxdata;
{
struct rtl8169_private *priv = dev_get_priv(dev);
- return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp);
+ return rtl_recv_common(dev, priv->iobase, packetp);
}
#else
static int rtl_recv(struct eth_device *dev)
/**************************************************************************
SEND - Transmit a frame
***************************************************************************/
-static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
+#ifdef CONFIG_DM_ETH
+static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
void *packet, int length)
+#else
+static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
+ void *packet, int length)
+#endif
{
/* send the packet to destination */
ptxb[len++] = '\0';
tpc->TxDescArray[entry].buf_Haddr = 0;
+#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
- pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
+ dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
+#else
+ tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
+ pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
+#endif
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
{
struct rtl8169_private *priv = dev_get_priv(dev);
- return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length);
+ return rtl_send_common(dev, priv->iobase, packet, length);
}
#else
RTL_W32(MAR0 + 4, mc_filter[1]);
}
-static void rtl8169_hw_start(pci_dev_t bdf)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_hw_start(struct udevice *dev)
+#else
+static void rtl8169_hw_start(pci_dev_t dev)
+#endif
{
u32 i;
tpc->cur_rx = 0;
- RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf,
+#ifdef CONFIG_DM_ETH
+ RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
+#else
+ RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
+ (pci_addr_t)(unsigned long)tpc->TxDescArray));
+#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
+#ifdef CONFIG_DM_ETH
+ RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
+ dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+#else
RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
- bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+ dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
+#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
#endif
}
-static void rtl8169_init_ring(pci_dev_t bdf)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_init_ring(struct udevice *dev)
+#else
+static void rtl8169_init_ring(pci_dev_t dev)
+#endif
{
int i;
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
+#ifdef CONFIG_DM_ETH
+ tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
+ dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+#else
tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
- bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+ dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
+#endif
rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
#endif
}
-static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr)
+#ifdef CONFIG_DM_ETH
+static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr)
+#else
+static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr)
+#endif
{
int i;
printf ("%s\n", __FUNCTION__);
#endif
- rtl8169_init_ring(bdf);
- rtl8169_hw_start(bdf);
+ rtl8169_init_ring(dev);
+ rtl8169_hw_start(dev);
/* Construct a perfect filter frame with the mac address as first match
* and broadcast for all others */
for (i = 0; i < 192; i++)
{
struct eth_pdata *plat = dev_get_platdata(dev);
- rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr);
+ rtl8169_common_start(dev, plat->enetaddr);
return 0;
}
region = 1;
break;
}
- pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4,
- &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
iobase &= ~0xf;
- priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase);
+ priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
if (ret < 0) {
struct eth_sandbox_priv *priv = dev_get_priv(dev);
if (skip_timeout) {
- sandbox_timer_add_offset(10000UL);
+ sandbox_timer_add_offset(11000UL);
skip_timeout = false;
}
#
ifneq ($(CONFIG_DM_PCI),)
-obj-$(CONFIG_PCI) += pci-uclass.o
+obj-y += pci_rom.o
+obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o
else
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
endif
-obj-$(CONFIG_PCI) += pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o
+obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
#include <fdtdec.h>
#include <inttypes.h>
#include <pci.h>
+#include <asm/io.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
#endif
+#include "pci_internal.h"
DECLARE_GLOBAL_DATA_PTR;
return dev;
}
-pci_dev_t pci_get_bdf(struct udevice *dev)
+pci_dev_t dm_pci_get_bdf(struct udevice *dev)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct udevice *bus = dev->parent;
return -ENODEV;
}
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
{
struct udevice *bus;
int ret;
return -ENODEV;
}
+static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
+ unsigned int device, int *indexp,
+ struct udevice **devp)
+{
+ struct pci_child_platdata *pplat;
+ struct udevice *dev;
+
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ pplat = dev_get_parent_platdata(dev);
+ if (pplat->vendor == vendor && pplat->device == device) {
+ if (!(*indexp)--) {
+ *devp = dev;
+ return 0;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+ struct udevice **devp)
+{
+ struct udevice *bus;
+
+ /* Scan all known buses */
+ for (uclass_first_device(UCLASS_PCI, &bus);
+ bus;
+ uclass_next_device(&bus)) {
+ if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
+ return device_probe(*devp);
+ }
+ *devp = NULL;
+
+ return -ENODEV;
+}
+
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ /* Scan all known buses */
+ for (pci_find_first_device(&dev);
+ dev;
+ pci_find_next_device(&dev)) {
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+
+ if (pplat->class == find_class && !index--) {
+ *devp = dev;
+ return device_probe(*devp);
+ }
+ }
+ *devp = NULL;
+
+ return -ENODEV;
+}
+
int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
unsigned long value, enum pci_size_t size)
{
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
+ return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
+ size);
}
for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
- return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
+ return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
size);
}
int ret;
debug("%s: device %s\n", __func__, dev->name);
- ret = pciauto_config_device(hose, pci_get_bdf(dev));
+ ret = dm_pciauto_config_device(dev);
if (ret < 0)
return ret;
max_bus = ret;
return sub_bus;
}
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
+int dm_pci_hose_probe_bus(struct udevice *bus)
{
- struct udevice *parent, *bus;
int sub_bus;
int ret;
debug("%s\n", __func__);
- parent = hose->bus;
-
- /* Find the bus within the parent */
- ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
- if (ret) {
- debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
- bdf, parent->name, ret);
- return ret;
- }
sub_bus = pci_get_bus_max() + 1;
debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
- pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
+ dm_pciauto_prescan_setup_bridge(bus, sub_bus);
ret = device_probe(bus);
if (ret) {
return -EPIPE;
}
sub_bus = pci_get_bus_max();
- pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
+ dm_pciauto_postscan_setup_bridge(bus, sub_bus);
return sub_bus;
}
/* Find this device in the device tree */
ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
- /* Search for a driver */
-
- /* If nothing in the device tree, bind a generic device */
+ /* If nothing in the device tree, bind a device */
if (ret == -ENODEV) {
struct pci_device_id find_id;
ulong val;
return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
}
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
+{
+ u32 addr;
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ dm_pci_read_config32(dev, bar, &addr);
+ if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+ return addr & PCI_BASE_ADDRESS_IO_MASK;
+ else
+ return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
+
+static int _dm_pci_bus_to_phys(struct udevice *ctlr,
+ pci_addr_t bus_addr, unsigned long flags,
+ unsigned long skip_mask, phys_addr_t *pa)
+{
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ struct pci_region *res;
+ int i;
+
+ for (i = 0; i < hose->region_count; i++) {
+ res = &hose->regions[i];
+
+ if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+ continue;
+
+ if (res->flags & skip_mask)
+ continue;
+
+ if (bus_addr >= res->bus_start &&
+ (bus_addr - res->bus_start) < res->size) {
+ *pa = (bus_addr - res->bus_start + res->phys_start);
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
+ unsigned long flags)
+{
+ phys_addr_t phys_addr = 0;
+ struct udevice *ctlr;
+ int ret;
+
+ /* The root controller has the region information */
+ ctlr = pci_get_controller(dev);
+
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
+ if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+ ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
+ flags, PCI_REGION_SYS_MEMORY,
+ &phys_addr);
+ if (!ret)
+ return phys_addr;
+ }
+
+ ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
+
+ if (ret)
+ puts("pci_hose_bus_to_phys: invalid physical address\n");
+
+ return phys_addr;
+}
+
+int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags, unsigned long skip_mask,
+ pci_addr_t *ba)
+{
+ struct pci_region *res;
+ struct udevice *ctlr;
+ pci_addr_t bus_addr;
+ int i;
+ struct pci_controller *hose;
+
+ /* The root controller has the region information */
+ ctlr = pci_get_controller(dev);
+ hose = dev_get_uclass_priv(ctlr);
+
+ for (i = 0; i < hose->region_count; i++) {
+ res = &hose->regions[i];
+
+ if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+ continue;
+
+ if (res->flags & skip_mask)
+ continue;
+
+ bus_addr = phys_addr - res->phys_start + res->bus_start;
+
+ if (bus_addr >= res->bus_start &&
+ (bus_addr - res->bus_start) < res->size) {
+ *ba = bus_addr;
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+ unsigned long flags)
+{
+ pci_addr_t bus_addr = 0;
+ int ret;
+
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
+ if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+ ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
+ PCI_REGION_SYS_MEMORY, &bus_addr);
+ if (!ret)
+ return bus_addr;
+ }
+
+ ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
+
+ if (ret)
+ puts("pci_hose_phys_to_bus: invalid physical address\n");
+
+ return bus_addr;
+}
+
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
+{
+ pci_addr_t pci_bus_addr;
+ u32 bar_response;
+
+ /* read BAR address */
+ dm_pci_read_config32(dev, bar, &bar_response);
+ pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+
+ /*
+ * Pass "0" as the length argument to pci_bus_to_virt. The arg
+ * isn't actualy used on any platform because u-boot assumes a static
+ * linear mapping. In the future, this could read the BAR size
+ * and pass that as the size if needed.
+ */
+ return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
*/
/*
- * PCI routines
+ * Old PCI routines
+ *
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci-uclass.c.
*/
#include <common.h>
--- /dev/null
+/*
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+#endif
+
+void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+ struct pci_region *mem,
+ struct pci_region *prefetch, struct pci_region *io,
+ bool enum_only)
+{
+ u32 bar_response;
+ pci_size_t bar_size;
+ u16 cmdstat = 0;
+ int bar, bar_nr = 0;
+ u8 header_type;
+ int rom_addr;
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
+ int found_mem64 = 0;
+ u16 class;
+
+ dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+ cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
+ PCI_COMMAND_MASTER;
+
+ for (bar = PCI_BASE_ADDRESS_0;
+ bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+ /* Tickle the BAR and get the response */
+ if (!enum_only)
+ dm_pci_write_config32(dev, bar, 0xffffffff);
+ dm_pci_read_config32(dev, bar, &bar_response);
+
+ /* If BAR is not implemented go to the next BAR */
+ if (!bar_response)
+ continue;
+
+ found_mem64 = 0;
+
+ /* Check the BAR type and set our address mask */
+ if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+ bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
+ if (!enum_only)
+ bar_res = io;
+
+ debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+ bar_nr, (unsigned long long)bar_size);
+ } else {
+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+
+ if (!enum_only) {
+ dm_pci_write_config32(dev, bar + 4,
+ 0xffffffff);
+ }
+ dm_pci_read_config32(dev, bar + 4,
+ &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) |
+ bar_response;
+
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
+ + 1;
+ if (!enum_only)
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response &
+ PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
+ if (!enum_only) {
+ if (prefetch && (bar_response &
+ PCI_BASE_ADDRESS_MEM_PREFETCH)) {
+ bar_res = prefetch;
+ } else {
+ bar_res = mem;
+ }
+ }
+
+ debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+ bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+ (unsigned long long)bar_size);
+ }
+
+ if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
+ &bar_value) == 0) {
+ /* Write it out and update our limit */
+ dm_pci_write_config32(dev, bar, (u32)bar_value);
+
+ if (found_mem64) {
+ bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, bar,
+ (u32)(bar_value >> 32));
+#else
+ /*
+ * If we are a 64-bit decoder then increment to
+ * the upper 32 bits of the bar and force it to
+ * locate in the lower 4GB of memory.
+ */
+ dm_pci_write_config32(dev, bar, 0x00000000);
+#endif
+ }
+ }
+
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
+
+ debug("\n");
+
+ bar_nr++;
+ }
+
+ if (!enum_only) {
+ /* Configure the expansion ROM address */
+ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+ if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+ rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+ PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+ dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
+ dm_pci_read_config32(dev, rom_addr, &bar_response);
+ if (bar_response) {
+ bar_size = -(bar_response & ~1);
+ debug("PCI Autoconfig: ROM, size=%#x, ",
+ (unsigned int)bar_size);
+ if (pciauto_region_allocate(mem, bar_size,
+ &bar_value) == 0) {
+ dm_pci_write_config32(dev, rom_addr,
+ bar_value);
+ }
+ cmdstat |= PCI_COMMAND_MEMORY;
+ debug("\n");
+ }
+ }
+ }
+
+ /* PCI_COMMAND_IO must be set for VGA device */
+ dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+ if (class == PCI_CLASS_DISPLAY_VGA)
+ cmdstat |= PCI_COMMAND_IO;
+
+ dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
+ dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
+ CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
+}
+
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ u16 cmdstat, prefechable_64;
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+ dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Configure bus number registers */
+ dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
+ PCI_BUS(dm_pci_get_bdf(dev)));
+ dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus);
+ dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ dm_pci_write_config16(dev, PCI_MEMORY_BASE,
+ (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ }
+
+ if (pci_prefetch) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ /*
+ * Set up memory and I/O filter limits, assume 32-bit
+ * I/O space
+ */
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
+ (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
+#endif
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ } else {
+ /* We don't support prefetchable memory for now, so disable */
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+ dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
+ dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ dm_pci_write_config8(dev, PCI_IO_BASE,
+ (pci_io->bus_lower & 0x0000f000) >> 8);
+ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+ (pci_io->bus_lower & 0xffff0000) >> 16);
+
+ cmdstat |= PCI_COMMAND_IO;
+ }
+
+ /* Enable memory and I/O accesses, enable bus master */
+ dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+}
+
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ /* Configure bus number registers */
+ dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
+ (pci_mem->bus_lower - 1) >> 16);
+ }
+
+ if (pci_prefetch) {
+ u16 prefechable_64;
+
+ dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
+ (pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+#endif
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ dm_pci_write_config8(dev, PCI_IO_LIMIT,
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+ }
+}
+
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
+ */
+int dm_pciauto_config_device(struct udevice *dev)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
+ unsigned short class;
+ bool enum_only = false;
+ int n;
+
+#ifdef CONFIG_PCI_ENUM_ONLY
+ enum_only = true;
+#endif
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+
+ dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+
+ switch (class) {
+ case PCI_CLASS_BRIDGE_PCI:
+ debug("PCI Autoconfig: Found P2P bridge, device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+
+ dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+
+ n = dm_pci_hose_probe_bus(dev);
+ if (n < 0)
+ return n;
+ sub_bus = (unsigned int)n;
+ break;
+
+ case PCI_CLASS_BRIDGE_CARDBUS:
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+
+ debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+
+ break;
+
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+ case PCI_CLASS_BRIDGE_OTHER:
+ debug("PCI Autoconfig: Skipping bridge device %d\n",
+ PCI_DEV(dm_pci_get_bdf(dev)));
+ break;
+#endif
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+ case PCI_CLASS_BRIDGE_OTHER:
+ /*
+ * The host/PCI bridge 1 seems broken in 8349 - it presents
+ * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+ * device claiming resources io/mem/irq.. we only allow for
+ * the PIMMR window to be allocated (BAR0 - 1MB size)
+ */
+ debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
+ dm_pciauto_setup_device(dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io,
+ enum_only);
+ break;
+#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ debug("PCI AutoConfig: Found PowerPC device\n");
+
+ default:
+ dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
+ enum_only);
+ break;
+ }
+
+ return sub_bus;
+}
/*
- * arch/powerpc/kernel/pci_auto.c
- *
- * PCI autoconfiguration library
+ * PCI autoconfiguration library (legacy version, do not change)
*
* Author: Matt Porter <mporter@mvista.com>
*
#include <errno.h>
#include <pci.h>
+/*
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci_auto.c.
+ */
+
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
-#else
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
PCI_BUS(dev) - hose->first_busno);
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
sub_bus - hose->first_busno);
-#endif
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
-#else
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
sub_bus - hose->first_busno);
-#endif
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
unsigned short class;
int n;
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
-#endif
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
pciauto_setup_device(hose, dev, 2, pci_mem,
pci_prefetch, pci_io);
-#ifdef CONFIG_DM_PCI
- n = dm_pci_hose_probe_bus(hose, dev);
- if (n < 0)
- return n;
- sub_bus = (unsigned int)n;
-#else
/* Passing in current_busno allows for sibling P2P bridges */
hose->current_busno++;
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
-#endif
break;
case PCI_CLASS_BRIDGE_CARDBUS:
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dev));
-#ifndef CONFIG_DM_PCI
hose->current_busno++;
-#endif
break;
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
};
}
-pci_dev_t pci_find_class(uint find_class, int index)
-{
- int bus;
- int devnum;
- pci_dev_t bdf;
- uint32_t class;
-
- for (bus = 0; bus <= pci_last_busno(); bus++) {
- for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
- pci_read_config_dword(PCI_BDF(bus, devnum, 0),
- PCI_CLASS_REVISION, &class);
- if (class >> 16 == 0xffff)
- continue;
-
- for (bdf = PCI_BDF(bus, devnum, 0);
- bdf <= PCI_BDF(bus, devnum,
- PCI_MAX_PCI_FUNCTIONS - 1);
- bdf += PCI_BDF(0, 0, 1)) {
- pci_read_config_dword(bdf, PCI_CLASS_REVISION,
- &class);
- class >>= 8;
-
- if (class != find_class)
- continue;
- /*
- * Decrement the index. We want to return the
- * correct device, so index is 0 for the first
- * matching device, 1 for the second, etc.
- */
- if (index) {
- index--;
- continue;
- }
- /* Return index'th controller. */
- return bdf;
- }
- }
- }
-
- return -ENODEV;
-}
-
__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
return 0;
}
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
/* Get a virtual address associated with a BAR region */
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
return -1;
}
+
+pci_dev_t pci_find_class(uint find_class, int index)
+{
+ int bus;
+ int devnum;
+ pci_dev_t bdf;
+ uint32_t class;
+
+ for (bus = 0; bus <= pci_last_busno(); bus++) {
+ for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
+ pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+ PCI_CLASS_REVISION, &class);
+ if (class >> 16 == 0xffff)
+ continue;
+
+ for (bdf = PCI_BDF(bus, devnum, 0);
+ bdf <= PCI_BDF(bus, devnum,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ bdf += PCI_BDF(0, 0, 1)) {
+ pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+ &class);
+ class >>= 8;
+
+ if (class != find_class)
+ continue;
+ /*
+ * Decrement the index. We want to return the
+ * correct device, so index is 0 for the first
+ * matching device, 1 for the second, etc.
+ */
+ if (index) {
+ index--;
+ continue;
+ }
+ /* Return index'th controller. */
+ return bdf;
+ }
+ }
+ }
+
+ return -ENODEV;
+}
+#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
if (pci_find_device_id(ids, index, &dev))
return -1;
- return pci_get_bdf(dev);
+ return dm_pci_get_bdf(dev);
}
--- /dev/null
+/*
+ * Internal PCI functions, not exported outside drivers/pci
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __pci_internal_h
+#define __pci_internal_h
+
+/**
+ * dm_pciauto_prescan_setup_bridge() - Set up a bridge for scanning
+ *
+ * This gets a bridge ready so that its downstream devices can be scanned.
+ * It sets up the bus number and memory range registers. Once the scan is
+ * completed, dm_pciauto_postscan_setup_bridge() should be called.
+ *
+ * @dev: Bridge device to be scanned
+ * @sub_bus: Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_postscan_setup_bridge() - Finish set up of a bridge after scanning
+ *
+ * This should be called after a bus scan is complete. It adjusts the memory
+ * ranges to fit with the devices actually found on the other side (downstream)
+ * of the bridge.
+ *
+ * @dev: Bridge device that was scanned
+ * @sub_bus: Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_config_device() - Configure a PCI device ready for use
+ *
+ * If the device is a bridge, downstream devices will be probed.
+ *
+ * @dev: Device to configure
+ * @return the maximum PCI bus number found by this device. If there are no
+ * bridges, this just returns the device's bus number. If the device is a
+ * bridge then it will return a larger number, depending on the devices on
+ * that bridge. On error, returns a -ve error number.
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+#endif
#include <common.h>
#include <bios_emul.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <pci.h>
#include <video_fb.h>
#include <linux/screen_info.h>
-__weak bool board_should_run_oprom(pci_dev_t dev)
+__weak bool board_should_run_oprom(struct udevice *dev)
{
return true;
}
-static bool should_load_oprom(pci_dev_t dev)
+static bool should_load_oprom(struct udevice *dev)
{
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
return 1;
return vendev;
}
-static int pci_rom_probe(pci_dev_t dev, uint class,
- struct pci_rom_header **hdrp)
+static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
{
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct pci_rom_header *rom_header;
struct pci_rom_data *rom_data;
- u16 vendor, device;
u16 rom_vendor, rom_device;
u32 rom_class;
u32 vendev;
u32 mapped_vendev;
u32 rom_address;
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(dev, PCI_DEVICE_ID, &device);
- vendev = vendor << 16 | device;
+ vendev = pplat->vendor << 16 | pplat->device;
mapped_vendev = board_map_oprom_vendev(vendev);
if (vendev != mapped_vendev)
debug("Device ID mapped to %#08x\n", mapped_vendev);
rom_address = CONFIG_VGA_BIOS_ADDR;
#else
- pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+ dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
debug("%s: rom_address=%x\n", __func__, rom_address);
return -ENOENT;
}
/* Enable expansion ROM address decoding. */
- pci_write_config_dword(dev, PCI_ROM_ADDRESS,
- rom_address | PCI_ROM_ADDRESS_ENABLE);
+ dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
+ rom_address | PCI_ROM_ADDRESS_ENABLE);
#endif
debug("Option ROM address %x\n", rom_address);
rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
le16_to_cpu(rom_header->signature));
#ifndef CONFIG_VGA_BIOS_ADDR
/* Disable expansion ROM address decoding */
- pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address);
+ dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
#endif
return -EINVAL;
}
rom_vendor, rom_device);
/* If the device id is mapped, a mismatch is expected */
- if ((vendor != rom_vendor || device != rom_device) &&
+ if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
(vendev == mapped_vendev)) {
printf("ID mismatch: vendor ID %04x, device ID %04x\n",
rom_vendor, rom_device);
debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
rom_class, rom_data->type);
- if (class != rom_class) {
+ if (pplat->class != rom_class) {
debug("Class Code mismatch ROM %06x, dev %06x\n",
- rom_class, class);
+ rom_class, pplat->class);
}
*hdrp = rom_header;
screen_info->rsvd_pos = vesa->reserved_mask_pos;
}
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+ int exec_method)
{
+ struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
struct pci_rom_header *rom, *ram;
int vesa_mode = -1;
- uint class;
bool emulate;
int ret;
/* Only execute VGA ROMs */
- pci_read_config_dword(dev, PCI_REVISION_ID, &class);
- if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
- debug("%s: Class %#x, should be %#x\n", __func__, class,
+ if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
PCI_CLASS_DISPLAY_VGA);
return -ENODEV;
}
- class >>= 8;
if (!should_load_oprom(dev))
return -ENXIO;
- ret = pci_rom_probe(dev, class, &rom);
+ ret = pci_rom_probe(dev, &rom);
if (ret)
return ret;
#ifdef CONFIG_BIOSEMU
BE_VGAInfo *info;
- ret = biosemu_setup(dev, &info);
+ ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
if (ret)
return ret;
biosemu_set_interrupt_handler(0x15, int15_handler);
- ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
- vesa_mode, &mode_info);
+ ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
+ info, true, vesa_mode, &mode_info);
if (ret)
return ret;
#endif
ret = imx_pcie_addr_valid(d);
if (ret) {
*val = 0xffffffff;
- return ret;
+ return 0;
}
va_address = get_bus_address(d, where);
if (ls_pcie_addr_valid(hose, d)) {
*val = 0xffffffff;
- return -EINVAL;
+ return 0;
}
if (PCI_BUS(d) == hose->first_busno) {
during serial port initialization (default y). Set this to n on
boards which have no debug serial port whatsoever.
+config SERIAL_PRESENT
+ bool "Provide a serial driver"
+ depends on DM_SERIAL
+ default y
+ help
+ In very space-constrained devices even the full UART driver is too
+ large. In this case the debug UART can still be used in some cases.
+ This option enables the full UART in U-Boot, so if is it disabled,
+ the full UART driver will be omitted, thus saving space.
+
+config SPL_SERIAL_PRESENT
+ bool "Provide a serial driver in SPL"
+ depends on DM_SERIAL
+ default y
+ help
+ In very space-constrained devices even the full UART driver is too
+ large. In this case the debug UART can still be used in some cases.
+ This option enables the full UART in SPL, so if is it disabled,
+ the full UART driver will be omitted, thus saving space.
+
config DM_SERIAL
bool "Enable Driver Model for serial drivers"
depends on DM
/* try Processor Local Bus device first */
addr = dev_get_addr(dev);
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
return ret;
}
- ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset,
- &pci_addr, &bar);
+ ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
};
#endif
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
U_BOOT_DRIVER(ns16550_serial) = {
.name = "ns16550_serial",
.id = UCLASS_SERIAL,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+#endif
#endif /* CONFIG_DM_SERIAL */
{
}
-#ifdef CONFIG_DM_STDIO
+#if defined(CONFIG_DM_STDIO) && CONFIG_IS_ENABLED(SERIAL_PRESENT)
static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
_serial_putc(sdev->priv, ch);
}
U_BOOT_ENV_CALLBACK(baudrate, on_baudrate);
+#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_post_probe(struct udevice *dev)
{
struct dm_serial_ops *ops = serial_get_ops(dev);
.pre_remove = serial_pre_remove,
.per_device_auto_alloc_size = sizeof(struct serial_dev_priv),
};
+#endif
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
DECLARE_GLOBAL_DATA_PTR;
+#define TXTL 2 /* reset default */
+#define RXTL 1 /* reset default */
+#define RFDIV 4 /* divide input clock by 2 */
+
static void mxc_serial_setbrg(void)
{
u32 clk = imx_get_uartclk();
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
+ __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
+ | (TXTL << UFCR_TXTL_SHF)
+ | (RXTL << UFCR_RXTL_SHF);
__REG(UART_PHYS + UBIR) = 0xf;
__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
};
#ifdef CONFIG_DEBUG_UART_ZYNQ
-void _debug_uart_init(void)
+static inline void _debug_uart_init(void)
{
struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
#define TX_BUFFER_SIZE 0x40
#endif
-#define OFFSET_BITS_MASK GENMASK(24, 0)
+#define OFFSET_BITS_MASK GENMASK(23, 0)
#define FLASH_STATUS_WEL 0x02
* and byte program command for SST flash
*/
if (plat->ich_version == 7) {
- slave->op_mode_rx = SPI_OPM_RX_AS;
- slave->op_mode_tx = SPI_OPM_TX_BP;
+ slave->mode_rx = SPI_RX_SLOW;
+ slave->mode = SPI_TX_BYTE;
}
return 0;
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
+ slave->mode_rx = plat->mode_rx;
return 0;
}
int spi_slave_ofdata_to_platdata(const void *blob, int node,
struct dm_spi_slave_platdata *plat)
{
- int mode = 0;
+ int mode = 0, mode_rx = 0;
+ int value;
plat->cs = fdtdec_get_int(blob, node, "reg", -1);
plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
mode |= SPI_3WIRE;
if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
+
+ /* Device DUAL/QUAD mode */
+ value = fdtdec_get_uint(blob, node, "spi-tx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode |= SPI_TX_DUAL;
+ break;
+ case 4:
+ mode |= SPI_TX_QUAD;
+ break;
+ default:
+ error("spi-tx-bus-width %d not supported\n", value);
+ break;
+ }
+
plat->mode = mode;
+ value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1);
+ switch (value) {
+ case 1:
+ break;
+ case 2:
+ mode_rx |= SPI_RX_DUAL;
+ break;
+ case 4:
+ mode_rx |= SPI_RX_QUAD;
+ break;
+ default:
+ error("spi-rx-bus-width %d not supported\n", value);
+ break;
+ }
+
+ plat->mode_rx = mode_rx;
+
return 0;
}
#include <asm/arch/omap.h>
#include <malloc.h>
#include <spi.h>
+#include <dm.h>
#include <asm/gpio.h>
#include <asm/omap_gpio.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
#define QSPI_XFER_DONE QSPI_WC
#define MM_SWITCH 0x01
-#define MEM_CS 0x100
+#define MEM_CS(cs) ((cs + 1) << 8)
#define MEM_CS_UNSELECT 0xfffff0ff
#define MMAP_START_ADDR_DRA 0x5c000000
#define MMAP_START_ADDR_AM43x 0x30000000
#define CORE_CTRL_IO 0x4a002558
#define QSPI_CMD_READ (0x3 << 0)
+#define QSPI_CMD_READ_DUAL (0x6b << 0)
#define QSPI_CMD_READ_QUAD (0x6b << 0)
#define QSPI_CMD_READ_FAST (0x0b << 0)
#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
+#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
#define QSPI_CMD_WRITE (0x2 << 16)
#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
u32 data3;
};
-/* ti qspi slave */
-struct ti_qspi_slave {
+/* ti qspi priv */
+struct ti_qspi_priv {
+#ifndef CONFIG_DM_SPI
struct spi_slave slave;
+#else
+ void *memory_map;
+ uint max_hz;
+ u32 num_cs;
+#endif
struct ti_qspi_regs *base;
+ void *ctrl_mod_mmap;
unsigned int mode;
u32 cmd;
u32 dc;
};
-static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct ti_qspi_slave, slave);
-}
-
-static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
+static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
{
- struct spi_slave *slave = &qslave->slave;
- u32 memval = 0;
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- slave->memory_map = (void *)MMAP_START_ADDR_DRA;
-#else
- slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
-#endif
-
-#ifdef CONFIG_QSPI_QUAD_SUPPORT
- memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_8_BITS |
- QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS);
- slave->op_mode_rx = SPI_OPM_RX_QOF;
-#else
- memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
- QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
- QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
- QSPI_NUM_DUMMY_BITS;
-#endif
-
- writel(memval, &qslave->base->setup0);
-}
-
-static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint clk_div;
debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
clk_div = (QSPI_FCLK / hz) - 1;
/* disable SCLK */
- writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
- &qslave->base->clk_ctrl);
+ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
+ &priv->base->clk_ctrl);
/* assign clk_div values */
if (clk_div < 0)
clk_div = QSPI_CLK_DIV_MAX;
/* enable SCLK */
- writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return 1;
+ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
}
-void spi_cs_activate(struct spi_slave *slave)
+static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
{
- /* CS handled in xfer */
- return;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
-
- writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+ writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
/* dummy readl to ensure bus sync */
- readl(&qslave->base->cmd);
+ readl(&priv->base->cmd);
}
-void spi_init(void)
+static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
{
- /* nothing to do */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct ti_qspi_slave *qslave;
-
-#ifdef CONFIG_AM43XX
- gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
- gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
-#endif
-
- qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
- if (!qslave) {
- printf("SPI_error: Fail to allocate ti_qspi_slave\n");
- return NULL;
- }
-
- qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
- qslave->mode = mode;
-
- ti_spi_set_speed(&qslave->slave, max_hz);
+ priv->dc = 0;
+ if (mode & SPI_CPHA)
+ priv->dc |= QSPI_CKPHA(0);
+ if (mode & SPI_CPOL)
+ priv->dc |= QSPI_CKPOL(0);
+ if (mode & SPI_CS_HIGH)
+ priv->dc |= QSPI_CSPOL(0);
-#ifdef CONFIG_TI_SPI_MMAP
- ti_spi_setup_spi_register(qslave);
-#endif
-
- return &qslave->slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
- free(qslave);
-}
+ writel(priv->dc, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
-
- debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
-
- qslave->dc = 0;
- if (qslave->mode & SPI_CPHA)
- qslave->dc |= QSPI_CKPHA(slave->cs);
- if (qslave->mode & SPI_CPOL)
- qslave->dc |= QSPI_CKPOL(slave->cs);
- if (qslave->mode & SPI_CS_HIGH)
- qslave->dc |= QSPI_CSPOL(slave->cs);
-
- writel(qslave->dc, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ priv->dc <<= cs * 8;
+ writel(priv->dc, &priv->base->dc);
return 0;
}
-void spi_release_bus(struct spi_slave *slave)
+static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
+ writel(0, &priv->base->dc);
+ writel(0, &priv->base->cmd);
+ writel(0, &priv->base->data);
+}
- debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
+static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
+{
+ u32 val;
- writel(0, &qslave->base->dc);
- writel(0, &qslave->base->cmd);
- writel(0, &qslave->base->data);
+ val = readl(ctrl_mod_mmap);
+ if (enable)
+ val |= MEM_CS(cs);
+ else
+ val &= MEM_CS_UNSELECT;
+ writel(val, ctrl_mod_mmap);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags,
+ u32 cs)
{
- struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
uint words = bitlen >> 3; /* fixed 8-bit word length */
const uchar *txp = dout;
uchar *rxp = din;
uint status;
int timeout;
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- int val;
-#endif
-
- debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
- slave->bus, slave->cs, bitlen, words, flags);
-
/* Setup mmap flags */
if (flags & SPI_XFER_MMAP) {
- writel(MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val |= MEM_CS;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
return 0;
} else if (flags & SPI_XFER_MMAP_END) {
- writel(~MM_SWITCH, &qslave->base->memswitch);
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
- val = readl(CORE_CTRL_IO);
- val &= MEM_CS_UNSELECT;
- writel(val, CORE_CTRL_IO);
-#endif
+ writel(~MM_SWITCH, &priv->base->memswitch);
+ if (priv->ctrl_mod_mmap)
+ ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
return 0;
}
}
/* Setup command reg */
- qslave->cmd = 0;
- qslave->cmd |= QSPI_WLEN(8);
- qslave->cmd |= QSPI_EN_CS(slave->cs);
- if (qslave->mode & SPI_3WIRE)
- qslave->cmd |= QSPI_3_PIN;
- qslave->cmd |= 0xfff;
+ priv->cmd = 0;
+ priv->cmd |= QSPI_WLEN(8);
+ priv->cmd |= QSPI_EN_CS(cs);
+ if (priv->mode & SPI_3WIRE)
+ priv->cmd |= QSPI_3_PIN;
+ priv->cmd |= 0xfff;
/* FIXME: This delay is required for successfull
* completion of read/write/erase. Once its root
while (words--) {
if (txp) {
debug("tx cmd %08x dc %08x data %02x\n",
- qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
- writel(*txp++, &qslave->base->data);
- writel(qslave->cmd | QSPI_WR_SNGL,
- &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
+ writel(*txp++, &priv->base->data);
+ writel(priv->cmd | QSPI_WR_SNGL,
+ &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: TX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
debug("tx done, status %08x\n", status);
}
if (rxp) {
- qslave->cmd |= QSPI_RD_SNGL;
+ priv->cmd |= QSPI_RD_SNGL;
debug("rx cmd %08x dc %08x\n",
- qslave->cmd, qslave->dc);
+ priv->cmd, priv->dc);
#ifdef CONFIG_DRA7XX
udelay(500);
#endif
- writel(qslave->cmd, &qslave->base->cmd);
- status = readl(&qslave->base->status);
+ writel(priv->cmd, &priv->base->cmd);
+ status = readl(&priv->base->status);
timeout = QSPI_TIMEOUT;
while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
if (--timeout < 0) {
printf("spi_xfer: RX timeout!\n");
return -1;
}
- status = readl(&qslave->base->status);
+ status = readl(&priv->base->status);
}
- *rxp++ = readl(&qslave->base->data);
+ *rxp++ = readl(&priv->base->data);
debug("rx done, status %08x, read %02x\n",
status, *(rxp-1));
}
/* Terminate frame */
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ ti_qspi_cs_deactivate(priv);
return 0;
}
*((unsigned int *)offset) += len;
}
#endif
+
+#ifndef CONFIG_DM_SPI
+
+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
+{
+ return container_of(slave, struct ti_qspi_priv, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* CS handled in xfer */
+ return;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ ti_qspi_cs_deactivate(priv);
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
+{
+ u32 memval = 0;
+
+#ifdef CONFIG_QSPI_QUAD_SUPPORT
+ struct spi_slave *slave = &priv->slave;
+ memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_8_BITS |
+ QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS);
+ slave->mode_rx = SPI_RX_QUAD;
+#else
+ memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
+ QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
+ QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
+ QSPI_NUM_DUMMY_BITS;
+#endif
+
+ writel(memval, &priv->base->setup0);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct ti_qspi_priv *priv;
+
+#ifdef CONFIG_AM43XX
+ gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
+ gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
+#endif
+
+ priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
+ if (!priv) {
+ printf("SPI_error: Fail to allocate ti_qspi_priv\n");
+ return NULL;
+ }
+
+ priv->base = (struct ti_qspi_regs *)QSPI_BASE;
+ priv->mode = mode;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+ priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
+#else
+ priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
+#endif
+
+ ti_spi_set_speed(priv, max_hz);
+
+#ifdef CONFIG_TI_SPI_MMAP
+ ti_spi_setup_spi_register(priv);
+#endif
+
+ return &priv->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+ free(priv);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_set_mode(priv, priv->mode);
+ return __ti_qspi_claim_bus(priv, priv->slave.cs);
+}
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
+ __ti_qspi_release_bus(priv);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
+
+ debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
+ priv->slave.bus, priv->slave.cs, bitlen, flags);
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
+}
+
+#else /* CONFIG_DM_SPI */
+
+static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
+ struct spi_slave *slave,
+ bool enable)
+{
+ u32 memval;
+ u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
+
+ if (!enable) {
+ writel(0, &priv->base->setup0);
+ return;
+ }
+
+ memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
+
+ switch (mode) {
+ case SPI_RX_QUAD:
+ memval |= QSPI_CMD_READ_QUAD;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_QUAD;
+ slave->mode_rx = SPI_RX_QUAD;
+ break;
+ case SPI_RX_DUAL:
+ memval |= QSPI_CMD_READ_DUAL;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
+ memval |= QSPI_SETUP0_READ_DUAL;
+ break;
+ default:
+ memval |= QSPI_CMD_READ;
+ memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
+ memval |= QSPI_SETUP0_READ_NORMAL;
+ break;
+ }
+
+ writel(memval, &priv->base->setup0);
+}
+
+
+static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ ti_spi_set_speed(priv, max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ return __ti_qspi_set_mode(priv, mode);
+}
+
+static int ti_qspi_claim_bus(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave_plat->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ __ti_qspi_setup_memorymap(priv, slave, true);
+
+ return __ti_qspi_claim_bus(priv, slave_plat->cs);
+}
+
+static int ti_qspi_release_bus(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ __ti_qspi_setup_memorymap(priv, slave, false);
+ __ti_qspi_release_bus(priv);
+
+ return 0;
+}
+
+static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ struct ti_qspi_priv *priv;
+ struct udevice *bus;
+
+ bus = dev->parent;
+ priv = dev_get_priv(bus);
+
+ if (slave->cs > priv->num_cs) {
+ debug("invalid qspi chip select\n");
+ return -EINVAL;
+ }
+
+ return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
+}
+
+static int ti_qspi_probe(struct udevice *bus)
+{
+ /* Nothing to do in probe */
+ return 0;
+}
+
+static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
+ fdt_addr_t addr;
+
+ priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
+ priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+ addr = dev_get_addr_index(bus, 2);
+ priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+
+ priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
+ if (priv->max_hz < 0) {
+ debug("Error: Max frequency missing\n");
+ return -ENODEV;
+ }
+ priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
+
+ debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
+ (int)priv->base, priv->max_hz);
+
+ return 0;
+}
+
+static int ti_qspi_child_pre_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct ti_qspi_priv *priv = dev_get_priv(bus);
+
+ slave->memory_map = priv->memory_map;
+ return 0;
+}
+
+static const struct dm_spi_ops ti_qspi_ops = {
+ .claim_bus = ti_qspi_claim_bus,
+ .release_bus = ti_qspi_release_bus,
+ .xfer = ti_qspi_xfer,
+ .set_speed = ti_qspi_set_speed,
+ .set_mode = ti_qspi_set_mode,
+};
+
+static const struct udevice_id ti_qspi_ids[] = {
+ { .compatible = "ti,dra7xxx-qspi" },
+ { .compatible = "ti,am4372-qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(ti_qspi) = {
+ .name = "ti_qspi",
+ .id = UCLASS_SPI,
+ .of_match = ti_qspi_ids,
+ .ops = &ti_qspi_ops,
+ .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
+ .probe = ti_qspi_probe,
+ .child_pre_probe = ti_qspi_child_pre_probe,
+};
+#endif /* CONFIG_DM_SPI */
#elif defined(CONFIG_MX7)
static int read_cpu_temperature(struct udevice *dev)
{
- unsigned int reg, tmp, start;
+ unsigned int reg, tmp;
unsigned int raw_25c, te1;
int temperature;
unsigned int *priv = dev_get_priv(dev);
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
- start = get_timer(0);
- /* Wait max 100ms */
- do {
+ if (soc_rev() >= CHIP_REV_1_1) {
+ while ((readl(&ccm_anatop->tempsense1) &
+ TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
+ ;
+ reg = readl(&ccm_anatop->tempsense1);
+ tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+ >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
+ } else {
/*
- * Since we can not rely on finish bit, use 1ms delay to get
- * temperature. From RM, 17us is enough to get data, but
- * to gurantee to get the data, delay 100ms here.
+ * Since we can not rely on finish bit, use 10ms
+ * delay to get temperature. From RM, 17us is
+ * enough to get data, but to gurantee to get
+ * the data, delay 10ms here.
*/
+ udelay(10000);
reg = readl(&ccm_anatop->tempsense1);
tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
>> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
- } while (get_timer(0) < (start + 100));
+ }
writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <linux/mii.h>
#include <malloc.h>
* @mchash: shadow for the network adapter's multicast hash registers
*/
struct mcs7830_private {
+#ifdef CONFIG_DM_ETH
+ uint8_t rx_buf[MCS7830_RX_URB_SIZE];
+ struct ueth_data ueth;
+#endif
uint8_t config;
uint8_t mchash[8];
};
/*
* mcs7830_read_reg() - read a register of the network adapter
- * @dev: network device to read from
+ * @udev: network device to read from
* @idx: index of the register to start reading from
* @size: number of bytes to read
* @data: buffer to read into
* Return: zero upon success, negative upon error
*/
-static int mcs7830_read_reg(struct ueth_data *dev, uint8_t idx,
+static int mcs7830_read_reg(struct usb_device *udev, uint8_t idx,
uint16_t size, void *data)
{
int len;
debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
- len = usb_control_msg(dev->pusb_dev,
- usb_rcvctrlpipe(dev->pusb_dev, 0),
+ len = usb_control_msg(udev,
+ usb_rcvctrlpipe(udev, 0),
MCS7830_RD_BREQ,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, idx, buf, size,
/*
* mcs7830_write_reg() - write a register of the network adapter
- * @dev: network device to write to
+ * @udev: network device to write to
* @idx: index of the register to start writing to
* @size: number of bytes to write
* @data: buffer holding the data to write
* Return: zero upon success, negative upon error
*/
-static int mcs7830_write_reg(struct ueth_data *dev, uint8_t idx,
+static int mcs7830_write_reg(struct usb_device *udev, uint8_t idx,
uint16_t size, void *data)
{
int len;
debug("%s() idx=0x%04X sz=%d\n", __func__, idx, size);
memcpy(buf, data, size);
- len = usb_control_msg(dev->pusb_dev,
- usb_sndctrlpipe(dev->pusb_dev, 0),
+ len = usb_control_msg(udev,
+ usb_sndctrlpipe(udev, 0),
MCS7830_WR_BREQ,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, idx, buf, size,
/*
* mcs7830_phy_emit_wait() - emit PHY read/write access, wait for its execution
- * @dev: network device to talk to
+ * @udev: network device to talk to
* @rwflag: PHY_CMD1_READ or PHY_CMD1_WRITE opcode
* @index: number of the PHY register to read or write
* Return: zero upon success, negative upon error
*/
-static int mcs7830_phy_emit_wait(struct ueth_data *dev,
+static int mcs7830_phy_emit_wait(struct usb_device *udev,
uint8_t rwflag, uint8_t index)
{
int rc;
/* send the PHY read/write request */
cmd[0] = rwflag | PHY_CMD1_PHYADDR;
cmd[1] = PHY_CMD2_PEND | (index & 0x1f);
- rc = mcs7830_write_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ rc = mcs7830_write_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd);
if (rc < 0)
return rc;
/* wait for the response to become available (usually < 1ms) */
retry = 10;
do {
- rc = mcs7830_read_reg(dev, REG_PHY_CMD, sizeof(cmd), cmd);
+ rc = mcs7830_read_reg(udev, REG_PHY_CMD, sizeof(cmd), cmd);
if (rc < 0)
return rc;
if (cmd[1] & PHY_CMD2_READY)
/*
* mcs7830_read_phy() - read a PHY register of the network adapter
- * @dev: network device to read from
+ * @udev: network device to read from
* @index: index of the PHY register to read from
* Return: non-negative 16bit register content, negative upon error
*/
-static int mcs7830_read_phy(struct ueth_data *dev, uint8_t index)
+static int mcs7830_read_phy(struct usb_device *udev, uint8_t index)
{
int rc;
uint16_t val;
/* issue the PHY read request and wait for its execution */
- rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_READ, index);
+ rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_READ, index);
if (rc < 0)
return rc;
/* fetch the PHY data which was read */
- rc = mcs7830_read_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ rc = mcs7830_read_reg(udev, REG_PHY_DATA, sizeof(val), &val);
if (rc < 0)
return rc;
rc = le16_to_cpu(val);
- debug("%s(%s, %d) => 0x%04X\n", __func__, dev->eth_dev.name, index, rc);
+ debug("%s(%d) => 0x%04X\n", __func__, index, rc);
return rc;
}
/*
* mcs7830_write_phy() - write a PHY register of the network adapter
- * @dev: network device to write to
+ * @udev: network device to write to
* @index: index of the PHY register to write to
* @val: value to write to the PHY register
* Return: zero upon success, negative upon error
*/
-static int mcs7830_write_phy(struct ueth_data *dev, uint8_t index, uint16_t val)
+static int mcs7830_write_phy(struct usb_device *udev, uint8_t index,
+ uint16_t val)
{
int rc;
- debug("%s(%s, %d, 0x%04X)\n", __func__, dev->eth_dev.name, index, val);
+ debug("%s(%d, 0x%04X)\n", __func__, index, val);
/* setup the PHY data which is to get written */
val = cpu_to_le16(val);
- rc = mcs7830_write_reg(dev, REG_PHY_DATA, sizeof(val), &val);
+ rc = mcs7830_write_reg(udev, REG_PHY_DATA, sizeof(val), &val);
if (rc < 0)
return rc;
/* issue the PHY write request and wait for its execution */
- rc = mcs7830_phy_emit_wait(dev, PHY_CMD1_WRITE, index);
+ rc = mcs7830_phy_emit_wait(udev, PHY_CMD1_WRITE, index);
if (rc < 0)
return rc;
/*
* mcs7830_write_config() - write to the network adapter's config register
- * @eth: network device to write to
+ * @udev: network device to write to
+ * @priv: private data
* Return: zero upon success, negative upon error
*
* the data which gets written is taken from the shadow config register
* within the device driver's private data
*/
-static int mcs7830_write_config(struct ueth_data *dev)
+static int mcs7830_write_config(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
- rc = mcs7830_write_reg(dev, REG_CONFIG,
+ rc = mcs7830_write_reg(udev, REG_CONFIG,
sizeof(priv->config), &priv->config);
if (rc < 0) {
debug("writing config to adapter failed\n");
/*
* mcs7830_write_mchash() - write the network adapter's multicast filter
- * @eth: network device to write to
+ * @udev: network device to write to
+ * @priv: private data
* Return: zero upon success, negative upon error
*
* the data which gets written is taken from the shadow multicast hashes
* within the device driver's private data
*/
-static int mcs7830_write_mchash(struct ueth_data *dev)
+static int mcs7830_write_mchash(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
- rc = mcs7830_write_reg(dev, REG_MULTICAST_HASH,
+ rc = mcs7830_write_reg(udev, REG_MULTICAST_HASH,
sizeof(priv->mchash), &priv->mchash);
if (rc < 0) {
debug("writing multicast hash to adapter failed\n");
/*
* mcs7830_set_autoneg() - setup and trigger ethernet link autonegotiation
- * @eth: network device to run link negotiation on
+ * @udev: network device to run link negotiation on
* Return: zero upon success, negative upon error
*
* the routine advertises available media and starts autonegotiation
*/
-static int mcs7830_set_autoneg(struct ueth_data *dev)
+static int mcs7830_set_autoneg(struct usb_device *udev)
{
int adv, flg;
int rc;
*/
adv = ADVERTISE_PAUSE_CAP | ADVERTISE_ALL | ADVERTISE_CSMA;
- rc = mcs7830_write_phy(dev, MII_ADVERTISE, adv);
+ rc = mcs7830_write_phy(udev, MII_ADVERTISE, adv);
flg = 0;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
flg |= BMCR_ANENABLE;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
flg |= BMCR_ANRESTART;
if (!rc)
- rc = mcs7830_write_phy(dev, MII_BMCR, flg);
+ rc = mcs7830_write_phy(udev, MII_BMCR, flg);
return rc;
}
/*
* mcs7830_get_rev() - identify a network adapter's chip revision
- * @eth: network device to identify
+ * @udev: network device to identify
* Return: non-negative number, reflecting the revision number
*
* currently, only "rev C and higher" and "below rev C" are needed, so
* the return value is #1 for "below rev C", and #2 for "rev C and above"
*/
-static int mcs7830_get_rev(struct ueth_data *dev)
+static int mcs7830_get_rev(struct usb_device *udev)
{
uint8_t buf[2];
int rc;
int rev;
/* register 22 is readable in rev C and higher */
- rc = mcs7830_read_reg(dev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
+ rc = mcs7830_read_reg(udev, REG_FRAME_DROP_COUNTER, sizeof(buf), buf);
if (rc < 0)
rev = 1;
else
/*
* mcs7830_apply_fixup() - identify an adapter and potentially apply fixups
- * @eth: network device to identify and apply fixups to
+ * @udev: network device to identify and apply fixups to
* Return: zero upon success (no errors emitted from here)
*
* this routine identifies the network adapter's chip revision, and applies
* fixups for known issues
*/
-static int mcs7830_apply_fixup(struct ueth_data *dev)
+static int mcs7830_apply_fixup(struct usb_device *udev)
{
int rev;
int i;
uint8_t thr;
- rev = mcs7830_get_rev(dev);
+ rev = mcs7830_get_rev(udev);
debug("%s() rev=%d\n", __func__, rev);
/*
* exactly", the introductory comment says "rev C and above")
*/
if (rev == 2) {
- debug("%s: applying rev C fixup\n", dev->eth_dev.name);
+ debug("%s: applying rev C fixup\n", __func__);
thr = PAUSE_THRESHOLD_DEFAULT;
for (i = 0; i < 2; i++) {
- (void)mcs7830_write_reg(dev, REG_PAUSE_THRESHOLD,
+ (void)mcs7830_write_reg(udev, REG_PAUSE_THRESHOLD,
sizeof(thr), &thr);
mdelay(1);
}
* of the interface callbacks can exchange ethernet frames; link negotiation is
* triggered from here already and continues in background
*/
-static int mcs7830_basic_reset(struct ueth_data *dev)
+static int mcs7830_basic_reset(struct usb_device *udev,
+ struct mcs7830_private *priv)
{
- struct mcs7830_private *priv;
int rc;
debug("%s()\n", __func__);
- priv = dev->dev_priv;
/*
* comment from the respective Linux driver, which
priv->config = CONF_TXENABLE;
priv->config |= CONF_ALLMULTICAST;
- rc = mcs7830_set_autoneg(dev);
+ rc = mcs7830_set_autoneg(udev);
if (rc < 0) {
error("setting autoneg failed\n");
return rc;
}
- rc = mcs7830_write_mchash(dev);
+ rc = mcs7830_write_mchash(udev, priv);
if (rc < 0) {
error("failed to set multicast hash\n");
return rc;
}
- rc = mcs7830_write_config(dev);
+ rc = mcs7830_write_config(udev, priv);
if (rc < 0) {
error("failed to set configuration\n");
return rc;
}
- rc = mcs7830_apply_fixup(dev);
+ rc = mcs7830_apply_fixup(udev);
if (rc < 0) {
error("fixup application failed\n");
return rc;
/*
* mcs7830_read_mac() - read an ethernet adapter's MAC address
- * @eth: network device to read from
+ * @udev: network device to read from
+ * @enetaddr: place to put ethernet MAC address
* Return: zero upon success, negative upon error
*
* this routine fetches the MAC address stored within the ethernet adapter,
* and stores it in the ethernet interface's data structure
*/
-static int mcs7830_read_mac(struct eth_device *eth)
+static int mcs7830_read_mac(struct usb_device *udev, unsigned char enetaddr[])
{
- struct ueth_data *dev;
int rc;
uint8_t buf[ETH_ALEN];
debug("%s()\n", __func__);
- dev = eth->priv;
- rc = mcs7830_read_reg(dev, REG_ETHER_ADDR, ETH_ALEN, buf);
+ rc = mcs7830_read_reg(udev, REG_ETHER_ADDR, ETH_ALEN, buf);
if (rc < 0) {
debug("reading MAC from adapter failed\n");
return rc;
}
- memcpy(ð->enetaddr[0], buf, ETH_ALEN);
+ memcpy(enetaddr, buf, ETH_ALEN);
return 0;
}
-/*
- * mcs7830_write_mac() - write an ethernet adapter's MAC address
- * @eth: network device to write to
- * Return: zero upon success, negative upon error
- *
- * this routine takes the MAC address from the ethernet interface's data
- * structure, and writes it into the ethernet adapter such that subsequent
- * exchange of ethernet frames uses this address
- */
-static int mcs7830_write_mac(struct eth_device *eth)
+static int mcs7830_write_mac_common(struct usb_device *udev,
+ unsigned char enetaddr[])
{
- struct ueth_data *dev;
int rc;
debug("%s()\n", __func__);
- dev = eth->priv;
- if (sizeof(eth->enetaddr) != ETH_ALEN)
- return -EINVAL;
- rc = mcs7830_write_reg(dev, REG_ETHER_ADDR, ETH_ALEN, eth->enetaddr);
+ rc = mcs7830_write_reg(udev, REG_ETHER_ADDR, ETH_ALEN, enetaddr);
if (rc < 0) {
debug("writing MAC to adapter failed\n");
return rc;
return 0;
}
-/*
- * mcs7830_init() - network interface's init callback
- * @eth: network device to initialize
- * @bd: board information
- * Return: zero upon success, negative upon error
- *
- * after initial setup during probe() and get_info(), this init() callback
- * ensures that the link is up and subsequent send() and recv() calls can
- * exchange ethernet frames
- */
-static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+static int mcs7830_init_common(struct usb_device *udev)
{
- struct ueth_data *dev;
int timeout;
int have_link;
debug("%s()\n", __func__);
- dev = eth->priv;
timeout = 0;
do {
- have_link = mcs7830_read_phy(dev, MII_BMSR) & BMSR_LSTATUS;
+ have_link = mcs7830_read_phy(udev, MII_BMSR) & BMSR_LSTATUS;
if (have_link)
break;
udelay(LINKSTATUS_TIMEOUT_RES * 1000);
return 0;
}
-/*
- * mcs7830_send() - network interface's send callback
- * @eth: network device to send the frame from
- * @packet: ethernet frame content
- * @length: ethernet frame length
- * Return: zero upon success, negative upon error
- *
- * this routine send an ethernet frame out of the network interface
- */
-static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+static int mcs7830_send_common(struct ueth_data *ueth, void *packet,
+ int length)
{
- struct ueth_data *dev;
+ struct usb_device *udev = ueth->pusb_dev;
int rc;
int gotlen;
/* there is a status byte after the ethernet frame */
ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, PKTSIZE + sizeof(uint8_t));
- dev = eth->priv;
-
memcpy(buf, packet, length);
- rc = usb_bulk_msg(dev->pusb_dev,
- usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ rc = usb_bulk_msg(udev,
+ usb_sndbulkpipe(udev, ueth->ep_out),
&buf[0], length, &gotlen,
USBCALL_TIMEOUT);
debug("%s() TX want len %d, got len %d, rc %d\n",
return rc;
}
-/*
- * mcs7830_recv() - network interface's recv callback
- * @eth: network device to receive frames from
- * Return: zero upon success, negative upon error
- *
- * this routine checks for available ethernet frames that the network
- * interface might have received, and notifies the network stack
- */
-static int mcs7830_recv(struct eth_device *eth)
+static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf)
{
- struct ueth_data *dev;
- ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
int rc, wantlen, gotlen;
uint8_t sts;
debug("%s()\n", __func__);
- dev = eth->priv;
/* fetch input data from the adapter */
wantlen = MCS7830_RX_URB_SIZE;
- rc = usb_bulk_msg(dev->pusb_dev,
- usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ rc = usb_bulk_msg(ueth->pusb_dev,
+ usb_rcvbulkpipe(ueth->pusb_dev, ueth->ep_in),
&buf[0], wantlen, &gotlen,
USBCALL_TIMEOUT);
debug("%s() RX want len %d, got len %d, rc %d\n",
if (sts == STAT_RX_FRAME_CORRECT) {
debug("%s() got a frame, len=%d\n", __func__, gotlen);
- net_process_received_packet(buf, gotlen);
- return 0;
+ return gotlen;
}
debug("RX: frame error (sts 0x%02X, %s %s %s %s %s)\n",
return -EIO;
}
+#ifndef CONFIG_DM_ETH
+/*
+ * mcs7830_init() - network interface's init callback
+ * @udev: network device to initialize
+ * @bd: board information
+ * Return: zero upon success, negative upon error
+ *
+ * after initial setup during probe() and get_info(), this init() callback
+ * ensures that the link is up and subsequent send() and recv() calls can
+ * exchange ethernet frames
+ */
+static int mcs7830_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev = eth->priv;
+
+ return mcs7830_init_common(dev->pusb_dev);
+}
+
+/*
+ * mcs7830_send() - network interface's send callback
+ * @eth: network device to send the frame from
+ * @packet: ethernet frame content
+ * @length: ethernet frame length
+ * Return: zero upon success, negative upon error
+ *
+ * this routine send an ethernet frame out of the network interface
+ */
+static int mcs7830_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev = eth->priv;
+
+ return mcs7830_send_common(dev, packet, length);
+}
+
+/*
+ * mcs7830_recv() - network interface's recv callback
+ * @eth: network device to receive frames from
+ * Return: zero upon success, negative upon error
+ *
+ * this routine checks for available ethernet frames that the network
+ * interface might have received, and notifies the network stack
+ */
+static int mcs7830_recv(struct eth_device *eth)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
+ struct ueth_data *ueth = eth->priv;
+ int len;
+
+ len = mcs7830_recv_common(ueth, buf);
+ if (len <= 0)
+ net_process_received_packet(buf, len);
+
+ return 0;
+}
+
/*
* mcs7830_halt() - network interface's halt callback
* @eth: network device to cease operation of
debug("%s()\n", __func__);
}
+/*
+ * mcs7830_write_mac() - write an ethernet adapter's MAC address
+ * @eth: network device to write to
+ * Return: zero upon success, negative upon error
+ *
+ * this routine takes the MAC address from the ethernet interface's data
+ * structure, and writes it into the ethernet adapter such that subsequent
+ * exchange of ethernet frames uses this address
+ */
+static int mcs7830_write_mac(struct eth_device *eth)
+{
+ struct ueth_data *ueth = eth->priv;
+
+ return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr);
+}
+
/*
* mcs7830_iface_idx - index of detected network interfaces
*
eth->write_hwaddr = mcs7830_write_mac;
eth->priv = ss;
- if (mcs7830_basic_reset(ss))
+ if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv))
return 0;
- if (mcs7830_read_mac(eth))
+ if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr))
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
+#endif
+
+
+#ifdef CONFIG_DM_ETH
+static int mcs7830_eth_start(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+
+ return mcs7830_init_common(udev);
+}
+
+void mcs7830_eth_stop(struct udevice *dev)
+{
+ debug("** %s()\n", __func__);
+}
+
+int mcs7830_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct ueth_data *ueth = &priv->ueth;
+
+ return mcs7830_send_common(ueth, packet, length);
+}
+
+int mcs7830_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct ueth_data *ueth = &priv->ueth;
+ int len;
+
+ len = mcs7830_recv_common(ueth, priv->rx_buf);
+ *packetp = priv->rx_buf;
+
+ return len;
+}
+
+static int mcs7830_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
+{
+ struct mcs7830_private *priv = dev_get_priv(dev);
+
+ packet_len = ALIGN(packet_len, 4);
+ usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
+
+ return 0;
+}
+
+int mcs7830_write_hwaddr(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return mcs7830_write_mac_common(udev, pdata->enetaddr);
+}
+
+static int mcs7830_eth_probe(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ struct mcs7830_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct ueth_data *ueth = &priv->ueth;
+
+ if (mcs7830_basic_reset(udev, priv))
+ return 0;
+
+ if (mcs7830_read_mac(udev, pdata->enetaddr))
+ return 0;
+
+ return usb_ether_register(dev, ueth, MCS7830_RX_URB_SIZE);
+}
+
+static const struct eth_ops mcs7830_eth_ops = {
+ .start = mcs7830_eth_start,
+ .send = mcs7830_eth_send,
+ .recv = mcs7830_eth_recv,
+ .free_pkt = mcs7830_free_pkt,
+ .stop = mcs7830_eth_stop,
+ .write_hwaddr = mcs7830_write_hwaddr,
+};
+
+U_BOOT_DRIVER(mcs7830_eth) = {
+ .name = "mcs7830_eth",
+ .id = UCLASS_ETH,
+ .probe = mcs7830_eth_probe,
+ .ops = &mcs7830_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct mcs7830_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static const struct usb_device_id mcs7830_eth_id_table[] = {
+ { USB_DEVICE(0x9710, 0x7832) }, /* Moschip 7832 */
+ { USB_DEVICE(0x9710, 0x7830), }, /* Moschip 7830 */
+ { USB_DEVICE(0x9710, 0x7730), }, /* Moschip 7730 */
+ { USB_DEVICE(0x0df6, 0x0021), }, /* Sitecom LN 30 */
+ { } /* Terminating entry */
+};
+
+U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table);
+#endif
(*pid << DWC2_HCTSIZ_PID_OFFSET),
&hc_regs->hctsiz);
- if (!in) {
- memcpy(priv->aligned_buffer, (char *)buffer + done, len);
+ if (!in && xfer_len) {
+ memcpy(priv->aligned_buffer, (char *)buffer + done,
+ xfer_len);
flush_dcache_range((unsigned long)priv->aligned_buffer,
(unsigned long)((void *)priv->aligned_buffer +
- roundup(len, ARCH_DMA_MINALIGN)));
+ roundup(xfer_len, ARCH_DMA_MINALIGN)));
}
writel(phys_to_bus((unsigned long)priv->aligned_buffer),
static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
struct QH *qh)
{
- struct usb_device *ttdev;
- int parent_devnum;
+ uint8_t portnr = 0;
+ uint8_t hubaddr = 0;
if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
return;
- /*
- * For full / low speed devices we need to get the devnum and portnr of
- * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
- * in the tree before that one!
- */
-#ifdef CONFIG_DM_USB
- /*
- * When called from usb-uclass.c: usb_scan_device() udev->dev points
- * to the parent udevice, not the actual udevice belonging to the
- * udev as the device is not instantiated yet. So when searching
- * for the first usb-2 parent start with udev->dev not
- * udev->dev->parent .
- */
- struct udevice *parent;
- struct usb_device *uparent;
-
- ttdev = udev;
- parent = udev->dev;
- uparent = dev_get_parent_priv(parent);
-
- while (uparent->speed != USB_SPEED_HIGH) {
- struct udevice *dev = parent;
-
- if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
- printf("ehci: Error cannot find high-speed parent of usb-1 device\n");
- return;
- }
-
- ttdev = dev_get_parent_priv(dev);
- parent = dev->parent;
- uparent = dev_get_parent_priv(parent);
- }
- parent_devnum = uparent->devnum;
-#else
- ttdev = udev;
- while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
- ttdev = ttdev->parent;
- if (!ttdev->parent)
- return;
- parent_devnum = ttdev->parent->devnum;
-#endif
+ usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
- qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
- QH_ENDPT2_HUBADDR(parent_devnum));
+ qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
+ QH_ENDPT2_HUBADDR(hubaddr));
}
static int
struct ehci_ctrl ehci;
};
-static void ehci_pci_common_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,
- struct ehci_hcor **ret_hcor)
+#ifdef CONFIG_DM_USB
+
+static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
{
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- uint32_t cmd;
+ u32 cmd;
- hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ hccr = (struct ehci_hccr *)dm_pci_map_bar(dev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
+ hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;
*ret_hcor = hcor;
/* enable busmaster */
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ dm_pci_read_config32(dev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
- pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+ dm_pci_write_config32(dev, PCI_COMMAND, cmd);
}
-#ifndef CONFIG_DM_USB
+#else
#ifdef CONFIG_PCI_EHCI_DEVICE
static struct pci_device_id ehci_pci_ids[] = {
};
#endif
+static void ehci_pci_legacy_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,
+ struct ehci_hcor **ret_hcor)
+{
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
+ u32 cmd;
+
+ hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+ hcor = (struct ehci_hcor *)((uintptr_t) hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
+ (u32)hccr, (u32)hcor,
+ (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ *ret_hccr = hccr;
+ *ret_hcor = hcor;
+
+ /* enable busmaster */
+ pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER;
+ pci_write_config_dword(pdev, PCI_COMMAND, cmd);
+}
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
printf("EHCI host controller not found\n");
return -1;
}
- ehci_pci_common_init(pdev, ret_hccr, ret_hcor);
+ ehci_pci_legacy_init(pdev, ret_hccr, ret_hcor);
return 0;
}
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
- ehci_pci_common_init(pci_get_bdf(dev), &hccr, &hcor);
+ ehci_pci_init(dev, &hccr, &hcor);
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
}
}
#else
if (tt_needed(musb, urb->dev)) {
- u16 hub_port = find_tt(urb->dev);
- qh->h_addr_reg = (u8) (hub_port >> 8);
- qh->h_port_reg = (u8) (hub_port & 0xff);
+ uint8_t portnr = 0;
+ uint8_t hubaddr = 0;
+ usb_find_usb2_hub_address_port(urb->dev,
+ &hubaddr,
+ &portnr);
+ qh->h_addr_reg = hubaddr;
+ qh->h_port_reg = portnr;
}
#endif
}
}
#ifdef CONFIG_DM_USB
-static inline u16 find_tt(struct usb_device *udev)
-{
- struct udevice *parent;
- struct usb_device *uparent, *ttdev;
-
- /*
- * When called from usb-uclass.c: usb_scan_device() udev->dev points
- * to the parent udevice, not the actual udevice belonging to the
- * udev as the device is not instantiated yet. So when searching
- * for the first usb-2 parent start with udev->dev not
- * udev->dev->parent .
- */
- ttdev = udev;
- parent = udev->dev;
- uparent = dev_get_parent_priv(parent);
-
- while (uparent->speed != USB_SPEED_HIGH) {
- struct udevice *dev = parent;
-
- if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
- printf("musb: Error cannot find high speed parent of usb-1 device\n");
- return 0;
- }
-
- ttdev = dev_get_parent_priv(dev);
- parent = dev->parent;
- uparent = dev_get_parent_priv(parent);
- }
-
- return (uparent->devnum << 8) | (ttdev->portnr - 1);
-}
-
static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev)
{
struct udevice *parent = udev->dev->parent;
return NULL;
}
#else
-static inline u16 find_tt(struct usb_device *dev)
-{
- u8 chid;
- u8 hub;
-
- /* Find out the nearest parent which is high speed */
- while (dev->parent->parent != NULL)
- if (dev->parent->speed != USB_SPEED_HIGH)
- dev = dev->parent;
- else
- break;
-
- /* determine the port address at that hub */
- hub = dev->parent->devnum;
- for (chid = 0; chid < USB_MAXCHILDREN; chid++)
- if (dev->parent->children[chid] == dev)
- break;
-
- return (hub << 8) | chid;
-}
-
static inline struct usb_device *usb_dev_get_parent(struct usb_device *dev)
{
return dev->parent;
void *video_hw_init(void)
{
GraphicDevice *gdev = &ctfb;
+ struct udevice *dev;
int bits_per_pixel;
- pci_dev_t dev;
int ret;
printf("Video: ");
return NULL;
}
if (vbe_get_video_info(gdev)) {
- dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
- if (dev < 0) {
+ ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev);
+ if (ret) {
printf("no card detected\n");
return NULL;
}
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
- ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
- PCI_ROM_ALLOW_FALLBACK);
+ ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
+ PCI_ROM_ALLOW_FALLBACK);
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- clrsetbits_le16(&wdog->wcr, 0, WCR_WDE);
+ clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
}
puts("\n");
+ setenv_hex("fileaddr", addr);
setenv_hex("filesize", len_read);
return 0;
};
struct ahci_probe_ent {
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev;
+#else
pci_dev_t dev;
+#endif
struct ahci_ioports port[AHCI_MAX_PORTS];
u32 n_ports;
u32 hard_port_no;
int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int cleanUp);
/* Run a BIOS ROM natively (only supported on x86 machines) */
-void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
struct vbe_mode_info *mode_info);
/**
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_LMB
-/*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR 0xf4040000
-
/*
* MEMORY ORGANIZATION
* -Monitor at top of sdram.
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN 0x20000
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+#define CONFIG_ENV_ADDR (0xf4000000 + CONFIG_SYS_MONITOR_LEN)
+
/*
* MISC
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
CONFIG_ENV_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
0x10000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#endif /* __CONFIG_H */
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_LMB
-/*
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
-#define CONFIG_ENV_ADDR 0xe2840000
-
/*
* MEMORY ORGANIZATION
* -Monitor at top of sdram.
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN 0x20000
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
+#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+#define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN)
+
/*
* MISC
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
CONFIG_ENV_SIZE - \
CONFIG_SYS_MALLOC_LEN - \
0x10000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#endif /* __CONFIG_H */
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
#endif
#ifndef CONFIG_SPL_BUILD
/*
* Ethernet PHY configuration
*/
-#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE
/*
- * Ethernet configuration
+ * USB 1.1 configuration
*/
-#define CONFIG_DW_AUTONEG
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
/*
* Commands still not supported in Kconfig
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_MII
#define CONFIG_MII
-#define CONFIG_PHYLIB
/* i2c Settings */
#define CONFIG_SYS_I2C
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPI_FLASH_GIGADEVICE
#endif
#define CONFIG_CMD_EXT2
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL
/* _VIA_CONTROL_EP */
#define CONFIG_CONSOLE_MUX
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
#define CONFIG_QSPI_QUAD_SUPPORT
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x010000 : QSPI.SPL (64KiB)
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_PHYLIB
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_IMX_THERMAL
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
+#endif
#endif
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_FSL_CLK
+
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
#define CONFIG_FIT
#define CONFIG_KEYBOARD
+#include <config_distro_defaults.h>
#include "mx6_common.h"
/* U-Boot Commands */
/* Booting Linux */
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
-#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run net_nfs"
#define CONFIG_HOSTNAME novena
/* Physical Memory Map */
#endif
/* Extra U-Boot environment. */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"rootdev=/dev/mmcblk0p2\0" \
"netdev=eth0\0" \
"kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
+ "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \
+ "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \
+ "ramdisk_addr_r=0x28000000\0" \
+ "fdt_addr_r=0x18000000\0" \
+ "fdtfile=imx6q-novena.dtb\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"console=${consdev},${baudrate}\0" \
"fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
"fi ; " \
"fi\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(SATA, sata, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_H */
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_SPL_SERIAL_SUPPORT
+
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_arria5
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#ifndef __CONFIG_SOCFPGA_COMMON_H__
+#define __CONFIG_SOCFPGA_COMMON_H__
/* Virtual target or real hardware */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
+#ifndef CONFIG_SYS_HOSTNAME
+#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
+#endif
+
/*
* Cache
*/
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE
#endif
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
#endif
+/*
+ * NAND Support
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_DENALI_ECC_SIZE 512
+#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
+#endif
+
/*
* I2C support
*/
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nor0=ff705000.spi"
+#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2
#define CONFIG_USB_STORAGE
-/*
- * NOTE: User must define either of the following to select which
- * of the two USB controllers available on SoCFPGA to use.
- * The DWC2 driver doesn't support multiple USB controllers.
- * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
- * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
- */
#endif
/*
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_FUNCTION_DFU
+#ifdef CONFIG_DM_MMC
#define CONFIG_DFU_MMC
+#endif
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
#ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
+#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR
#endif
#endif
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 4096
+/* Environment for SDMMC boot */
+#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+#endif
+
+/*
+ * mtd partitioning for serial NOR flash
+ *
+ * device nor0 <ff705000.spi.0>, # parts = 6
+ * #: name size offset mask_flags
+ * 0: u-boot 0x00100000 0x00000000 0
+ * 1: env1 0x00040000 0x00100000 0
+ * 2: env2 0x00040000 0x00140000 0
+ * 3: UBI 0x03e80000 0x00180000 0
+ * 4: boot 0x00e80000 0x00180000 0
+ * 5: rootfs 0x01000000 0x01000000 0
+ *
+ */
+#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
+#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
+ "1m(u-boot)," \
+ "256k(env1)," \
+ "256k(env2)," \
+ "14848k(boot)," \
+ "16m(rootfs)," \
+ "-@1536k(UBI)\0"
+#endif
+
+/* UBI and UBIFS support */
+#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
/*
* SPL
*
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_DM_MMC
#define CONFIG_SPL_MMC_SUPPORT
+#endif
+#ifdef CONFIG_DM_SPI
#define CONFIG_SPL_SPI_SUPPORT
+#endif
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif
+/* SPL NAND boot support */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#endif
+
/*
* Stack setup
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
+#endif /* __CONFIG_SOCFPGA_COMMON_H__ */
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Altera"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_cyclone5
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Terasic"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_de0_nano_soc
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
/* Environment is in MMC */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "DENX"
/* Extra Environment */
-#define CONFIG_HOSTNAME mcvevk
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyS0\0" \
"baudrate=115200\0" \
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "Terasic"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_sockit
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-
-/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
-
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER "EBV"
/* Extra Environment */
-#define CONFIG_HOSTNAME socfpga_socrates
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
#define CONFIG_PHY_MARVELL
#define PHY_ANEG_TIMEOUT 8000
-/* Extra Environment */
-#define CONFIG_HOSTNAME sr1500
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* Environment */
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* Ethernet driver configuration */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* GMAC related configs */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_PHY_MICREL
#endif
#ifdef CONFIG_SUNXI_GMAC
-#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_PHYLIB
#endif
#ifdef CONFIG_USB_EHCI_HCD
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
+#endif
#else
#define BOOT_TARGET_DEVICES_MMC(func)
+#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
#endif
#ifdef CONFIG_AHCI
#define BOOT_TARGET_DEVICES(func) \
func(FEL, fel, na) \
BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_MMC_EXTRA(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
/*
* Ethernet PHY configuration
*/
-#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE
/*
"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
"bootm $fit_addr_r\0"
#else
-#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTFILE "zImage"
#define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x00100000\0" \
"fdt_addr_r=0x84100000\0" \
"fdt_size=0x00008000\0" \
- "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"kernel_addr=0x00200000\0" \
- "kernel_addr_r=0x84200000\0" \
+ "kernel_addr_r=0x80208000\0" \
"kernel_size=0x00800000\0" \
"ramdisk_addr=0x00a00000\0" \
"ramdisk_addr_r=0x84a00000\0" \
"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
"setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \
"setexpr fdt_addr $nor_base + $fdt_addr &&" \
- "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
+ "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \
"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
- "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+ "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
"tftpboot $fdt_addr_r $fdt_file &&" \
- "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
+ "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=norkern\0" \
"kernel_alt_name=Image\0" \
- "kernel_addr=0x80000000\0" \
+ "kernel_addr=0x80080000\0" \
"initrd_name=ramdisk.img\0" \
"initrd_addr=0x84000000\0" \
"fdt_name=board.dtb\0" \
#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_name=Image\0" \
- "kernel_addr=0x80000000\0" \
+ "kernel_addr=0x80080000\0" \
"initrd_name=ramdisk.img\0" \
"initrd_addr=0x88000000\0" \
"fdt_name=devtree.dtb\0" \
/* Ethernet config options */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
*/
fdt_addr_t dev_get_addr(struct udevice *dev);
+/**
+ * dev_get_addr_index() - Get the indexed reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @return addr
+ */
+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);
+
/**
* device_has_children() - check if a device has any children
*
#endif /* ! CONFIG_DEVRES */
+/**
+ * dm_set_translation_offset() - Set translation offset
+ * @offs: Translation offset
+ *
+ * Some platforms need a special address translation. Those
+ * platforms (e.g. mvebu in SPL) can configure a translation
+ * offset in the DM by calling this function. It will be
+ * added to all addresses returned in dev_get_addr().
+ */
+void dm_set_translation_offset(fdt_addr_t offs);
+
+/**
+ * dm_get_translation_offset() - Get translation offset
+ *
+ * This function returns the translation offset that can
+ * be configured by calling dm_set_translation_offset().
+ *
+ * @return translation offset for the device address (0 as default).
+ */
+fdt_addr_t dm_get_translation_offset(void);
+
#endif
COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
+ COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
int fdtdec_get_pci_vendev(const void *blob, int node,
u16 *vendor, u16 *device);
-/**
- * Look at the pci address of a device node that represents a PCI device
- * and parse the bus, device and function number from it. For some cases
- * like the bus number encoded in reg property is not correct after pci
- * enumeration, this function looks through the node's compatible strings
- * to get these numbers extracted instead.
- *
- * @param blob FDT blob
- * @param node node to examine
- * @param addr pci address in the form of fdt_pci_addr
- * @param bdf returns bus, device, function triplet
- * @return 0 if ok, negative on error
- */
-int fdtdec_get_pci_bdf(const void *blob, int node,
- struct fdt_pci_addr *addr, pci_dev_t *bdf);
-
/**
* Look at the pci address of a device node that represents a PCI device
* and return base address of the pci device's registers.
*
- * @param blob FDT blob
- * @param node node to examine
+ * @param dev device to examine
* @param addr pci address in the form of fdt_pci_addr
* @param bar returns base address of the pci device's registers
* @return 0 if ok, negative on error
*/
-int fdtdec_get_pci_bar32(const void *blob, int node,
- struct fdt_pci_addr *addr, u32 *bar);
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+ u32 *bar);
/**
* Look up a 32-bit integer property in a node and return it. The property
#define SYSCTL_INITA 0x08000000
#define SYSCTL_TIMEOUT_MASK 0x000f0000
#define SYSCTL_CLOCK_MASK 0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN 0x00000008
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
+#endif
#define SYSCTL_RSTA 0x01000000
#define SYSCTL_RSTC 0x02000000
#define SYSCTL_RSTD 0x04000000
#define WCR_WDT 0x08
#define WCR_SRS 0x10
#define SET_WCR_WT(x) (x << 8)
+#define WCR_WT_MSK SET_WCR_WT(0xFF)
int hash_block(const char *algo_name, const void *data, unsigned int len,
uint8_t *output, int *output_size);
-/**
- * hash_show() - Print out a hash algorithm and value
- *
- * You will get a message like this (without a newline at the end):
- *
- * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257"
- *
- * @algo: Algorithm used for hash
- * @addr: Address of data that was hashed
- * @len: Length of data that was hashed
- * @output: Hash value to display
- */
-void hash_show(struct hash_algo *algo, ulong addr, ulong len,
- uint8_t *output);
-
#endif /* !USE_HOSTCC */
/**
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
-#define LBAF "%llx"
-#define LBAFU "%llu"
+#define LBAFlength "ll"
#else
typedef ulong lbaint_t;
-#define LBAF "%lx"
-#define LBAFU "%lu"
+#define LBAFlength "l"
#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
/*
* Function Prototypes
*
* @dev: the device
* @request: command to be sent to the device
- * @buf: pointer to buffer related to the requset
+ * @buf: pointer to buffer related to the request
* @return: 0 if OK, -ve on error
*/
int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
*
* @dev: the device
* @request: command to be sent to the device
- * @buf: pointer to buffer related to the requset
+ * @buf: pointer to buffer related to the request
* @return: 0 if OK, -ve on error
*/
int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
-#define SECURE_ERASE 0x80000000
+#define MMC_ERASE_ARG 0x00000000
+#define MMC_SECURE_ERASE_ARG 0x80000000
+#define MMC_TRIM_ARG 0x00000001
+#define MMC_DISCARD_ARG 0x00000003
+#define MMC_SECURE_TRIM1_ARG 0x80000001
+#define MMC_SECURE_TRIM2_ARG 0x80008000
#define MMC_STATUS_MASK (~0x0206BF7F)
#define MMC_STATUS_SWITCH_ERROR (1 << 7)
* This finds all the matching PCI IDs and sets them up as MMC devices.
*
* @name: Name to use for devices
- * @mmc_supported: PCI IDs to search for
- * @num_ids: Number of elements in @mmc_supported
+ * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
*/
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
- int num_ids);
+int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
#endif
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
/* For driver model these are defined in macros in pci_compat.c */
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
/**
- * pci_get_bdf() - Get the BDF value for a device
+ * dm_pci_get_bdf() - Get the BDF value for a device
*
* @dev: Device to check
* @return bus/device/function value (see PCI_BDF())
*/
-pci_dev_t pci_get_bdf(struct udevice *dev);
+pci_dev_t dm_pci_get_bdf(struct udevice *dev);
/**
* pci_bind_bus_devices() - scan a PCI bus and bind devices
int pci_auto_config_devices(struct udevice *bus);
/**
- * pci_bus_find_bdf() - Find a device given its PCI bus address
+ * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
*
* @bdf: PCI device address: bus, device and function -see PCI_BDF()
* @devp: Returns the device for this address, if found
* @return 0 if OK, -ENODEV if not found
*/
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
/**
* pci_bus_find_devfn() - Find a device on a bus
* @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
* @return 0 if OK, -ve on error
*/
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf);
+int dm_pci_hose_probe_bus(struct udevice *bus);
/**
* pci_bus_read_config() - Read a configuration value from a device
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
+/**
+ * dm_pci_read_bar32() - read a base address register from a device
+ *
+ * @dev: Device to check
+ * @barnum: Bar number to read (numbered from 0)
+ * @return: value of BAR
+ */
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
+
+/**
+ * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
+ *
+ * @dev: Device containing the PCI address
+ * @addr: PCI address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return physical address corresponding to that PCI bus address
+ */
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
+ *
+ * @dev: Device containing the bus address
+ * @addr: Physical address to convert
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return PCI bus address corresponding to that physical address
+ */
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
+ unsigned long flags);
+
+/**
+ * dm_pci_map_bar() - get a virtual address associated with a BAR region
+ *
+ * Looks up a base address register and finds the physical memory address
+ * that corresponds to it
+ *
+ * @dev: Device to check
+ * @bar: Bar number to read (numbered from 0)
+ * @flags: Flags for the region type (PCI_REGION_...)
+ * @return: pointer to the virtual address to use
+ */
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
+
+#define dm_pci_virt_to_bus(dev, addr, flags) \
+ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
+#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+ map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
+ (len), (map_flags))
+
+#define dm_pci_phys_to_mem(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_phys_to_io(dev, addr) \
+ dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_phys(dev, addr) \
+ dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define dm_pci_virt_to_mem(dev, addr) \
+ dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
+ dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define dm_pci_virt_to_io(dev, addr) \
+ dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
+ dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
+/**
+ * dm_pci_find_device() - find a device by vendor/device ID
+ *
+ * @vendor: Vendor ID
+ * @device: Device ID
+ * @index: 0 to find the first match, 1 for second, etc.
+ * @devp: Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+ struct udevice **devp);
+
+/**
+ * dm_pci_find_class() - find a device by class
+ *
+ * @find_class: 3-byte (24-bit) class value to find
+ * @index: 0 to find the first match, 1 for second, etc.
+ * @devp: Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
+
/**
* struct dm_pci_emul_ops - PCI device emulator operations
*/
};
/**
- * pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ * dm_pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
*
* @dev: Video device containing the BIOS
* @int15_handler: Function to call to handle int 0x15
* @exec_method: flags from enum pci_rom_emul
*/
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void),
- int exec_method);
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+ int exec_method);
/**
* board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
#define __CORE_PMIC_H_
#include <i2c.h>
-#include <spi.h>
#include <linux/list.h>
#include <power/power_chrg.h>
#define _SPI_H_
/* SPI mode flags */
-#define SPI_CPHA 0x01 /* clock phase */
-#define SPI_CPOL 0x02 /* clock polarity */
-#define SPI_MODE_0 (0|0) /* (original MicroWire) */
-#define SPI_MODE_1 (0|SPI_CPHA)
-#define SPI_MODE_2 (SPI_CPOL|0)
-#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
-#define SPI_CS_HIGH 0x04 /* CS active high */
-#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
-#define SPI_3WIRE 0x10 /* SI/SO signals shared */
-#define SPI_LOOP 0x20 /* loopback mode */
-#define SPI_SLAVE 0x40 /* slave mode */
-#define SPI_PREAMBLE 0x80 /* Skip preamble bytes */
-
-/* SPI transfer flags */
-#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
-#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
-#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
-#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
-#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE (1 << 5)
-
-/* SPI TX operation modes */
-#define SPI_OPM_TX_QPP (1 << 0)
-#define SPI_OPM_TX_BP (1 << 1)
-
-/* SPI RX operation modes */
-#define SPI_OPM_RX_AS (1 << 0)
-#define SPI_OPM_RX_AF (1 << 1)
-#define SPI_OPM_RX_DOUT (1 << 2)
-#define SPI_OPM_RX_DIO (1 << 3)
-#define SPI_OPM_RX_QOF (1 << 4)
-#define SPI_OPM_RX_QIOF (1 << 5)
-#define SPI_OPM_RX_EXTN (SPI_OPM_RX_AS | SPI_OPM_RX_AF | SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
- SPI_OPM_RX_QIOF)
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_MODE_0 (0|0) /* (original MicroWire) */
+#define SPI_MODE_1 (0|SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL|0)
+#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
+#define SPI_CS_HIGH BIT(2) /* CS active high */
+#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
+#define SPI_3WIRE BIT(4) /* SI/SO signals shared */
+#define SPI_LOOP BIT(5) /* loopback mode */
+#define SPI_SLAVE BIT(6) /* slave mode */
+#define SPI_PREAMBLE BIT(7) /* Skip preamble bytes */
+#define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */
+#define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */
+#define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
+
+/* SPI mode_rx flags */
+#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */
+#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */
+#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */
+#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */
/* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 << 0)
* @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
*/
struct dm_spi_slave_platdata {
unsigned int cs;
uint max_hz;
uint mode;
+ u8 mode_rx;
};
#endif /* CONFIG_DM_SPI */
*
* @dev: SPI slave device
* @max_hz: Maximum speed for this slave
- * @mode: SPI mode to use for this slave (see SPI mode flags)
* @speed: Current bus speed. This is 0 until the bus is first
* claimed.
* @bus: ID of the bus that the slave is attached to. For
* driver model this is the sequence number of the SPI
* bus (bus->seq) so does not need to be stored
* @cs: ID of the chip select connected to the slave.
- * @op_mode_rx: SPI RX operation mode.
- * @op_mode_tx: SPI TX operation mode.
+ * @mode: SPI mode to use for this slave (see SPI mode flags)
+ * @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
* @wordlen: Size of SPI word in number of bits
* @max_write_size: If non-zero, the maximum number of bytes which can
* be written at once, excluding command bytes.
struct udevice *dev; /* struct spi_slave is dev->parentdata */
uint max_hz;
uint speed;
- uint mode;
#else
unsigned int bus;
unsigned int cs;
#endif
- u8 op_mode_rx;
- u8 op_mode_tx;
+ uint mode;
+ u8 mode_rx;
unsigned int wordlen;
unsigned int max_write_size;
void *memory_map;
u8 option;
+
u8 flags;
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_MMAP BIT(2) /* Memory Mapped start */
+#define SPI_XFER_MMAP_END BIT(3) /* Memory Mapped End */
+#define SPI_XFER_U_PAGE BIT(4)
};
/**
/* Compatibility function - this is the old U-Boot API */
void spi_flash_free(struct spi_flash *flash);
-int spi_flash_remove(struct udevice *flash);
-
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
{
#ifdef CONFIG_USB_STORAGE
-#define USB_MAX_STOR_DEV 5
+#define USB_MAX_STOR_DEV 7
block_dev_desc_t *usb_stor_get_dev(int index);
int usb_stor_scan(int mode);
int usb_stor_info(void);
void *buffer, int transfer_len, int interval);
int usb_disable_asynch(int disable);
int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
-int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
- int cfgno);
+int usb_get_configuration_no(struct usb_device *dev, int cfgno,
+ unsigned char *buffer, int length);
+int usb_get_configuration_len(struct usb_device *dev, int cfgno);
int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
unsigned char id, void *buf, int size);
int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat);
+/*
+ * usb_find_usb2_hub_address_port() - Get hub address and port for TT setting
+ *
+ * Searches for the first HS hub above the given device. If a
+ * HS hub is found, the hub address and the port the device is
+ * connected to is return, as required for SPLIT transactions
+ *
+ * @param: udev full speed or low speed device
+ */
+void usb_find_usb2_hub_address_port(struct usb_device *udev,
+ uint8_t *hub_address, uint8_t *hub_port);
+
/**
* usb_alloc_new_device() - Allocate a new device
*
#ifndef USE_HOSTCC
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <serial.h>
#include <libfdt.h>
COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
+ COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
};
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
const char *prop_name, struct fdt_pci_addr *addr)
{
return -ENOENT;
}
-int fdtdec_get_pci_bdf(const void *blob, int node,
- struct fdt_pci_addr *addr, pci_dev_t *bdf)
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+ u32 *bar)
{
- u16 dt_vendor, dt_device, vendor, device;
- int ret;
-
- /* get vendor id & device id from the compatible string */
- ret = fdtdec_get_pci_vendev(blob, node, &dt_vendor, &dt_device);
- if (ret)
- return ret;
-
- /* extract the bdf from fdt_pci_addr */
- *bdf = addr->phys_hi & 0xffff00;
-
- /* read vendor id & device id based on bdf */
- pci_read_config_word(*bdf, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(*bdf, PCI_DEVICE_ID, &device);
-
- /*
- * Note there are two places in the device tree to fully describe
- * a pci device: one is via compatible string with a format of
- * "pciVVVV,DDDD" and the other one is the bdf numbers encoded in
- * the device node's reg address property. We read the vendor id
- * and device id based on bdf and compare the values with the
- * "VVVV,DDDD". If they are the same, then we are good to use bdf
- * to read device's bar. But if they are different, we have to rely
- * on the vendor id and device id extracted from the compatible
- * string and locate the real bdf by pci_find_device(). This is
- * because normally we may only know device's device number and
- * function number when writing device tree. The bus number is
- * dynamically assigned during the pci enumeration process.
- */
- if ((dt_vendor != vendor) || (dt_device != device)) {
- *bdf = pci_find_device(dt_vendor, dt_device, 0);
- if (*bdf == -1)
- return -ENODEV;
- }
-
- return 0;
-}
-
-int fdtdec_get_pci_bar32(const void *blob, int node,
- struct fdt_pci_addr *addr, u32 *bar)
-{
- pci_dev_t bdf;
int barnum;
- int ret;
-
- /* get pci devices's bdf */
- ret = fdtdec_get_pci_bdf(blob, node, addr, &bdf);
- if (ret)
- return ret;
/* extract the bar number from fdt_pci_addr */
barnum = addr->phys_hi & 0xff;
return -EINVAL;
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
- *bar = pci_read_bar32(pci_bus_to_hose(PCI_BUS(bdf)), bdf, barnum);
+ *bar = dm_pci_read_bar32(dev, barnum);
return 0;
}
int eth_init(void)
{
- struct udevice *current;
+ char *ethact = getenv("ethact");
+ char *ethrotate = getenv("ethrotate");
+ struct udevice *current = NULL;
struct udevice *old_current;
int ret = -ENODEV;
- current = eth_get_dev();
+ /*
+ * When 'ethrotate' variable is set to 'no' and 'ethact' variable
+ * is already set to an ethernet device, we should stick to 'ethact'.
+ */
+ if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) {
+ if (ethact) {
+ current = eth_get_dev_by_name(ethact);
+ if (!current)
+ return -EINVAL;
+ }
+ }
+
if (!current) {
- printf("No ethernet found.\n");
- return -ENODEV;
+ current = eth_get_dev();
+ if (!current) {
+ printf("No ethernet found.\n");
+ return -ENODEV;
+ }
}
old_current = current;
} else if (is_valid_ethaddr(dev->enetaddr)) {
eth_setenv_enetaddr_by_index(base_name, eth_number,
dev->enetaddr);
- printf("\nWarning: %s using MAC address from net device\n",
- dev->name);
} else if (is_zero_ethaddr(dev->enetaddr)) {
#ifdef CONFIG_NET_RANDOM_ETHADDR
net_random_ethaddr(dev->enetaddr);
static void eth_current_changed(void)
{
char *act = getenv("ethact");
+ char *ethrotate;
+
+ /*
+ * The call to eth_get_dev() below has a side effect of rotating
+ * ethernet device if uc_priv->current == NULL. This is not what
+ * we want when 'ethrotate' variable is 'no'.
+ */
+ ethrotate = getenv("ethrotate");
+ if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0))
+ return;
+
/* update current ethernet name */
if (eth_get_dev()) {
if (act == NULL || strcmp(act, eth_get_name()) != 0)
#ifdef CONFIG_SHOW_ACTIVITY
show_activity(1);
#endif
+ if (arp_timeout_check() > 0)
+ time_start = get_timer(0);
+
/*
* Check the ethernet for a new packet. The ethernet
* receive routine will process it.
goto done;
}
- if (arp_timeout_check() > 0) {
- time_start = get_timer(0);
- }
-
/*
* Check for a timeout, and run the timeout handler
* if we have one.
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
- if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
- !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) {
+ if (($line=~/$Type\s*$Ident\(.*\).*\s\{/) and
+ !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) {
ERROR("OPEN_BRACE",
"open brace '{' following function declarations go on the next line\n" . $herecurr);
}
## }
#need space before brace following if, while, etc
- if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
- $line =~ /do{/) {
+ if (($line =~ /\(.*\)\{/ && $line !~ /\($Type\){/) ||
+ $line =~ /do\{/) {
if (ERROR("SPACING",
"space required before the open brace '{'\n" . $herecurr) &&
$fix) {
$dstat !~ /^for\s*$Constant$/ && # for (...)
$dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar()
$dstat !~ /^do\s*{/ && # do {...
- $dstat !~ /^\({/ && # ({...
+ $dstat !~ /^\(\{/ && # ({...
$ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/)
{
$ctx =~ s/\n*$//;
while (<$maint>) {
my $line = $_;
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
for (my $i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'S') {
for (my $i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'M') {
for ($i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'X') {
if (!$exclude) {
for ($i = $start; $i < $end; $i++) {
my $line = $typevalue[$i];
- if ($line =~ m/^(\C):\s*(.*)/) {
+ if ($line =~ m/^([A-Z]):\s*(.*)/) {
my $type = $1;
my $value = $2;
if ($type eq 'F') {
while ($index < @typevalue) {
my $tv = $typevalue[$index];
- if (($tv =~ m/^(\C):\s*(.*)/)) {
+ if (($tv =~ m/^([A-Z]):\s*(.*)/)) {
last;
}
$index++;
while ($index > 0) {
my $tv = $typevalue[$index];
- if (!($tv =~ m/^(\C):\s*(.*)/)) {
+ if (!($tv =~ m/^([A-Z]):\s*(.*)/)) {
last;
}
$index--;
while ($index < @typevalue) {
my $tv = $typevalue[$index];
- if (!($tv =~ m/^(\C):\s*(.*)/)) {
+ if (!($tv =~ m/^([A-Z]):\s*(.*)/)) {
last;
}
$index++;
for ($i = $start + 1; $i < $end; $i++) {
my $tv = $typevalue[$i];
- if ($tv =~ m/^(\C):\s*(.*)/) {
+ if ($tv =~ m/^([A-Z]):\s*(.*)/) {
my $ptype = $1;
my $pvalue = $2;
if ($ptype eq "S") {
for ($i = $start + 1; $i < $end; $i++) {
my $tv = $typevalue[$i];
- if ($tv =~ m/^(\C):\s*(.*)/) {
+ if ($tv =~ m/^([A-Z]):\s*(.*)/) {
my $ptype = $1;
my $pvalue = $2;
if ($ptype eq "L") {
if ($name eq "") {
if ($i > 0) {
my $tv = $typevalue[$i - 1];
- if ($tv =~ m/^(\C):\s*(.*)/) {
+ if ($tv =~ m/^([A-Z]):\s*(.*)/) {
if ($1 eq "P") {
$name = $2;
$pvalue = format_email($name, $address, $email_usename);
obj-$(CONFIG_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_RESET) += reset.o
obj-$(CONFIG_DM_RTC) += rtc.o
-obj-$(CONFIG_DM_SPI_FLASH) += sf.o
-obj-$(CONFIG_DM_SPI) += spi.o
+#obj-$(CONFIG_DM_SPI_FLASH) += sf.o
+#obj-$(CONFIG_DM_SPI) += spi.o
obj-y += syscon.o
obj-$(CONFIG_DM_USB) += usb.o
obj-$(CONFIG_DM_PMIC) += pmic.o
/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
{
- pci_dev_t pci_dev = PCI_BDF(0, 0x1f, 0);
- struct pci_controller *hose;
- struct udevice *bus, *swap;
+ struct udevice *emul, *swap;
ulong io_addr, mem_addr;
char *ptr;
/* Check that asking for the device automatically fires up PCI */
- ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &swap));
-
- ut_assertok(uclass_get_device(UCLASS_PCI, 0, &bus));
- hose = dev_get_uclass_priv(bus);
+ ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul));
+ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
+ ut_assert(device_active(swap));
/* First test I/O */
- io_addr = pci_read_bar32(hose, pci_dev, 0);
+ io_addr = dm_pci_read_bar32(swap, 0);
outb(2, io_addr);
ut_asserteq(2, inb(io_addr));
* Now test memory mapping - note we must unmap and remap to cause
* the swapcase emulation to see our data and response.
*/
- mem_addr = pci_read_bar32(hose, pci_dev, 1);
+ mem_addr = dm_pci_read_bar32(swap, 1);
ptr = map_sysmem(mem_addr, 20);
strcpy(ptr, "This is a TesT");
unmap_sysmem(ptr);
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
- ut_asserteq(5, count_usb_devices());
+ ut_asserteq(6, count_usb_devices());
ut_assertok(usb_stop());
- ut_asserteq(5, count_usb_devices());
+ ut_asserteq(6, count_usb_devices());
/* Remove the second emulation device */
ut_assertok(uclass_find_device_by_name(UCLASS_USB_EMUL, "flash-stick@1",
ut_asserteq(-ENODEV, uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
- ut_asserteq(4, count_usb_devices());
+ ut_asserteq(5, count_usb_devices());
ut_assertok(usb_stop());
- ut_asserteq(4, count_usb_devices());
+ ut_asserteq(5, count_usb_devices());
return 0;
}
" | sandbox flash flash-stick@1\n"
" | \n"
" |\b+-4 Mass Storage (12 Mb/s, 100mA)\n"
-" sandbox flash flash-stick@2\n"
+" | sandbox flash flash-stick@2\n"
+" | \n"
+" |\b+-5 Human Interface (12 Mb/s, 100mA)\n"
+" sandbox keyboard keyb@3\n"
" \n";
/* test that the 'usb tree' command output looks correct */
" | sandbox flash flash-stick@0\n"
" | \n"
" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
-" sandbox flash flash-stick@2\n"
+" | sandbox flash flash-stick@2\n"
+" | \n"
+" |\b+-4 Human Interface (12 Mb/s, 100mA)\n"
+" sandbox keyboard keyb@3\n"
" \n";
/*
" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
" | sandbox flash flash-stick@2\n"
" | \n"
-" |\b+-4 Mass Storage (12 Mb/s, 100mA)\n"
+" |\b+-4 Human Interface (12 Mb/s, 100mA)\n"
+" | sandbox keyboard keyb@3\n"
+" | \n"
+" |\b+-5 Mass Storage (12 Mb/s, 100mA)\n"
" sandbox flash flash-stick@1\n"
" \n";
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o
+ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
* boot ROM. Its rationale is unknown.
*/
for (sector = size / RKSPI_SECT_LEN - 1; sector >= 0; sector--) {
- printf("sector %u\n", sector);
+ debug("sector %u\n", sector);
memmove(buf + sector * RKSPI_SECT_LEN * 2,
buf + sector * RKSPI_SECT_LEN,
RKSPI_SECT_LEN);
projects / u-boot / commitdiff