Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 7c3cf496be7f13cd6eea5b773bc66ba7bb4fec70..36b51007eadba92dc2c156dee05e5ea1f830aba2 100644 (file)
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -34,6 +34,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
+#include <asm/cache.h>
 #include <ppc440.h>
 #include <watchdog.h>
 
@@ -59,7 +60,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
 
 static u32 is_ecc_enabled(void)
 {
@@ -106,6 +106,7 @@ static void program_ecc(u32 start_address,
 {
        u32 val;
        u32 current_addr = start_address;
+       u32 size;
        int bytes_remaining;
 
        sync();
@@ -123,12 +124,18 @@ static void program_ecc(u32 start_address,
         * watchdog.
         */
        while (bytes_remaining > 0) {
-               dcbz_area(current_addr, min((64 << 20), bytes_remaining));
+               size = min((64 << 20), bytes_remaining);
+
+               /* Write zero's to SDRAM */
+               dcbz_area(current_addr, size);
+
+               /* Write modified dcache lines back to memory */
+               clean_dcache_range(current_addr, current_addr + size);
+
                current_addr += 64 << 20;
                bytes_remaining -= 64 << 20;
                WATCHDOG_RESET();
        }
-       dflush();
 
        sync();
        wait_ddr_idle();

diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 0b16b505027d933786a6a5208edaa65691978566..6b1b53a4d058bb62d08d583fe94e8a3555e3ec8e 100644 (file)
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -34,11 +34,11 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 #include <ppc440.h>
 
 void hcu_led_set(u32 value);
 void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
 
 #define DDR_DCR_BASE 0x10
 #define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
@@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 #endif
 
        sync();
-       eieio();
 
        puts(str);
 
        /* ECC bit set method for cached memory */
        /* Fast method, no noticeable delay */
        dcbz_area(start_address, num_bytes);
-       dflush();
+       /* Write modified dcache lines back to memory */
+       clean_dcache_range(start_address, start_address + num_bytes);
        blank_string(strlen(str));
 
        /* Clear error status */

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 9e722b998453faa18c56dcbe9661126ba21f69f1..5b5de48544892180c6261bd469d561dd71cfcf8e 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -40,6 +40,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&                              \
        (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
@@ -237,7 +238,6 @@ static void DQS_calibration_process(void);
 static void ppc440sp_sdram_register_dump(void);
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
 
 static u32 mfdcr_any(u32 dcr)
 {
@@ -2355,7 +2355,8 @@ static void program_ecc_addr(unsigned long start_address,
                } else {
                        /* ECC bit set method for cached memory */
                        dcbz_area(start_address, num_bytes);
-                       dflush();
+                       /* Write modified dcache lines back to memory */
+                       clean_dcache_range(start_address, start_address + num_bytes);
                }
 
                blank_string(strlen(str));

diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c
index e20c9ebf879803ff485466a51359914ecfb83f31..ad805b937b1942ed64fa7481524d225d6764c2bd 100644 (file)
--- a/cpu/ppc4xx/denali_spd_ddr2.c
+++ b/cpu/ppc4xx/denali_spd_ddr2.c
@@ -45,6 +45,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&                              \
        (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
@@ -92,7 +93,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
 
 /*
  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
@@ -1201,7 +1201,8 @@ long int initdram(int board_type)
 #else
 #error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
 #endif
-       dflush();
+       /* Write modified dcache lines back to memory */
+       clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
        debug("Completed\n");
        sync();
        remove_tlb(CFG_SDRAM_BASE, dram_size);

diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 1f4d6f27fdd4af16065fdb1d7a3fb3bde059dabc..02dece0c0ff6ffdf3c99553e04e0c9327e5e1588 100644 (file)
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -83,8 +83,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
                             bd->bi_intfreq, 1);
        do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
        do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
-       do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
-                            sys_info.freqEBC, 1);
+
+       if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
+               do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
+                       sys_info.freqEBC, 1);
+       else
+               do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
+                       sys_info.freqEBC, 1);
+
        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
        /*

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 8d2777dcd923293c127d709e537ed06480a3325e..a513b4507aba89e65fd8915e097a195f569e6dd5 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -1675,35 +1675,6 @@ trap_reloc:
        sync
        blr
        function_epilog(dcbz_area)
-
-/*----------------------------------------------------------------------------+
-| dflush.  Assume 32K at vector address is cachable.
-+----------------------------------------------------------------------------*/
-       function_prolog(dflush)
-       mfmsr   r9
-       rlwinm  r8,r9,0,15,13
-       rlwinm  r8,r8,0,17,15
-       mtmsr   r8
-       mfspr   r8,dvlim
-       addi    r3,r0,0x0000
-       mtspr   dvlim,r3
-       mfspr   r3,ivpr
-       addi    r4,r0,1024
-       mtctr   r4
-..dflush_loop:
-       lwz     r6,0x0(r3)
-       addi    r3,r3,32
-       bdnz    ..dflush_loop
-       addi    r3,r3,-32
-       mtctr   r4
-..ag:  dcbf    r0,r3
-       addi    r3,r3,-32
-       bdnz    ..ag
-       mtspr   dvlim,r8
-       sync
-       mtmsr   r9
-       blr
-       function_epilog(dflush)
 #endif /* CONFIG_440 */
 #endif /* CONFIG_NAND_SPL */
 

diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 122b7006e1dae85671ee69d1d2fd88f70c0a2ff9..d2f6b1021a353366012b337e101759ec8fa5bfa2 100644 (file)
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -48,12 +48,8 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN         (512 * 1024)    /* Reserve 512 kB for malloc */
-
 #define CFG_SDRAM_BASE         0x00000000      /* _must_ be 0          */
 #define CFG_FLASH_BASE         0xff000000      /* start of FLASH       */
-#define CFG_MONITOR_BASE       TEXT_BASE
 #define CFG_PERIPHERAL_BASE    0xa0000000      /* internal peripherals */
 #define CFG_ISRAM_BASE         0x90000000      /* internal SRAM        */
 
@@ -82,6 +78,10 @@
 
 #define CFG_ACE_BASE           0xfe000000      /* Xilinx ACE controller - Compact Flash */
 
+#define CFG_MONITOR_BASE       TEXT_BASE
+#define CFG_MONITOR_LEN                (0xFFFFFFFF - CFG_MONITOR_LEN + 1)
+#define CFG_MALLOC_LEN         (512 * 1024)    /* Reserve 512 kB for malloc */
+
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/