Merge branch 'master' of git://git.denx.de/u-boot-spi

- Fix a conflict in drivers/spi/atcspi200_spi.c related to the riscv
  tree fixing a warning.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8581df9a2778e85187ffa43242810db328af781c..afa7832f8936349817c8f36e812730a4cee828bd 100644 (file)
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -88,10 +88,11 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
-                       reg-names = "QuadSPI", "QuadSPI-memory";
+                       reg-names = "qspi", "qspi_mm";
                        interrupts = <92>;
                        spi-max-frequency = <108000000>;
                        clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
+                       resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
                        status = "disabled";
                };
                usart1: serial@40011000 {

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 2911729b289ed077996cf2cf0c1745fe187204f1..0ed2317554783e8f0e2b828ca177b2f4f4d3e5ba 100644 (file)
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1202,14 +1202,15 @@ int spi_flash_scan(struct spi_flash *flash)
        flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
        flash->page_size = info->page_size;
        /*
-        * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the
-        * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with
-        * the 0x4d00 Extended JEDEC code have 512b pages. All of the others
-        * have 256b pages.
+        * The Spansion S25FS512S, S25FL032P and S25FL064P have 256b pages,
+        * yet use the 0x4d00 Extended JEDEC code. The rest of the Spansion
+        * flashes with the 0x4d00 Extended JEDEC code have 512b pages.
+        * All of the others have 256b pages.
         */
        if (JEDEC_EXT(info) == 0x4d00) {
                if ((JEDEC_ID(info) != 0x0215) &&
-                   (JEDEC_ID(info) != 0x0216))
+                   (JEDEC_ID(info) != 0x0216) &&
+                   (JEDEC_ID(info) != 0x0220))
                        flash->page_size = 512;
        }
        flash->page_size <<= flash->shift;

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index 41879d662a8d5dce6f76142428df23c89cd677d2..5d146e36c64593f0751b229b98d552121fb7abdf 100644 (file)
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -71,6 +71,9 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"is25lp064",      INFO(0x9d6017, 0x0, 64 * 1024,   128, 0) },
        {"is25lp128",      INFO(0x9d6018, 0x0, 64 * 1024,   256, 0) },
        {"is25lp256",      INFO(0x9d6019, 0x0, 64 * 1024,   512, 0) },
+       {"is25wp032",      INFO(0x9d7016, 0x0, 64 * 1024,    64, RD_FULL | SECT_4K) },
+       {"is25wp064",      INFO(0x9d7017, 0x0, 64 * 1024,   128, RD_FULL | SECT_4K) },
+       {"is25wp128",      INFO(0x9d7018, 0x0, 64 * 1024,   256, RD_FULL | SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX       /* MACRONIX */
        {"mx25l2006e",     INFO(0xc22012, 0x0, 64 * 1024,     4, 0) },
@@ -85,6 +88,7 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"mx25u6435f",     INFO(0xc22537, 0x0, 64 * 1024,   128, RD_FULL | WR_QPP) },
        {"mx25l12855e",    INFO(0xc22618, 0x0, 64 * 1024,   256, RD_FULL | WR_QPP) },
        {"mx25u1635e",     INFO(0xc22535, 0x0, 64 * 1024,  32, SECT_4K) },
+       {"mx25u25635f",    INFO(0xc22539, 0x0, 64 * 1024,   512, RD_FULL | WR_QPP) },
        {"mx66u51235f",    INFO(0xc2253a, 0x0, 64 * 1024,  1024, RD_FULL | WR_QPP) },
        {"mx66l1g45g",     INFO(0xc2201b, 0x0, 64 * 1024,  2048, RD_FULL | WR_QPP) },
 #endif
@@ -174,6 +178,7 @@ const struct spi_flash_info spi_flash_ids[] = {
        {"w25q32dw",       INFO(0xef6016, 0x0,  64 * 1024,    64, RD_FULL | WR_QPP | SECT_4K) },
        {"w25q64dw",       INFO(0xef6017, 0x0,  64 * 1024,   128, RD_FULL | WR_QPP | SECT_4K) },
        {"w25q128fw",      INFO(0xef6018, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP | SECT_4K) },
+       {"w25q256fw",      INFO(0xef6019, 0x0,  64 * 1024,   512, RD_FULL | WR_QPP | SECT_4K) },
 #endif
        {},     /* Empty entry to terminate the list */
        /*
@@ -188,5 +193,6 @@ const struct spi_flash_info spi_flash_ids[] = {
         * (w25q32dw, w25q32fv_qpi)
         * (w25q64dw, w25q64fv_qpi)
         * (w25q128fw, w25q128fv_qpi)
+        * (w25q256fw, w25q256fv_qpi)
         */
 };

diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
index be424e0a6f823a9d70cee41beb9dad178ab6dd95..af96c6d21e5c5e04220c2936e8586f5b192b4691 100644 (file)
--- a/drivers/spi/atcspi200_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -229,8 +229,10 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
                        __atcspi200_spi_start(ns);
                        break;
                }
-               debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
-                     *(uint *)data_out, data_out, *(uint *)data_in, data_in, data_len);
+               if (data_out)
+                       debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
+                             *(uint *)data_out, data_out, *(uint *)data_in,
+                             data_in, data_len);
                num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
                din = data_in;
                dout = data_out;

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 368424948478e0691dafbe3e5faa123c7b411537..197f41f9db093b8123c6b04e47ea24c445426461 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -407,7 +407,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 {
        struct fsl_qspi_regs *regs = priv->regs;
        u32 mcr_reg;
-       void *rx_addr = NULL;
+       void *rx_addr;
 
        mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 

diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
index e6c876da07b41f78f2f43804f72df230c9e98a49..ce12eee65715890429258b81aaef45cbf16521fe 100644 (file)
--- a/drivers/spi/lpc32xx_ssp.c
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -129,7 +129,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
                int status = readl(&lslave->regs->sr);
                if ((idx_out < bytelen) && (status & SSP_SR_TNF))
                        writel(((u8 *)dout)[idx_out++], &lslave->regs->data);
-               if ((idx_in < bytelen) && (status & status & SSP_SR_RNE))
+               if ((idx_in < bytelen) && (status & SSP_SR_RNE))
                        ((u8 *)din)[idx_in++] = readl(&lslave->regs->data);
                if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT)
                        return -1;

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 7d1801280773937c6e31f713755560bc10436017..f6cc35336320ce1ec0e5cba4e9f0879e1d34b39d 100644 (file)
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -8,16 +8,16 @@
  */
 
 #include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
 #include <malloc.h>
+#include <reset.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/io.h>
-#include <dm.h>
-#include <errno.h>
 #include <asm/arch/stm32.h>
-#include <clk.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <linux/ioport.h>
 
 struct stm32_qspi_regs {
        u32 cr;         /* 0x00 */
@@ -155,6 +155,8 @@ enum STM32_QSPI_CCR_FMODE {
 /* default SCK frequency, unit: HZ */
 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
 
+#define STM32_MAX_NORCHIP 2
+
 struct stm32_qspi_platdata {
        u32 base;
        u32 memory_map;
@@ -206,11 +208,18 @@ static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 {
        u32 fsize = fls(size) - 1;
+
        clrsetbits_le32(&priv->regs->dcr,
                        STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
                        fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
 }
 
+static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
+{
+       clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+                       cs ? STM32_QSPI_CR_FSEL : 0);
+}
+
 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 {
        unsigned int ccr_reg = 0;
@@ -255,13 +264,15 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 }
 
 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
-               struct spi_flash *flash)
+                                   struct spi_flash *flash)
 {
+       unsigned int ccr_reg;
+
        priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
                        | CMD_HAS_DUMMY;
        priv->dummycycles = flash->dummy_byte * 8;
 
-       unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
+       ccr_reg = _stm32_qspi_gen_ccr(priv);
        ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
 
        _stm32_qspi_wait_for_not_busy(priv);
@@ -291,10 +302,12 @@ static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
 }
 
 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
-               struct spi_flash *flash, unsigned int bitlen,
-               const u8 *dout, u8 *din, unsigned long flags)
+                           struct spi_flash *flash, unsigned int bitlen,
+                           const u8 *dout, u8 *din, unsigned long flags)
 {
        unsigned int words = bitlen / 8;
+       u32 ccr_reg;
+       int i;
 
        if (flags & SPI_XFER_MMAP) {
                _stm32_qspi_enable_mmap(priv, flash);
@@ -346,7 +359,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
                }
 
                if (flags & SPI_XFER_END) {
-                       u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+                       ccr_reg = _stm32_qspi_gen_ccr(priv);
                        ccr_reg |= STM32_QSPI_CCR_IND_WRITE
                                        << STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -365,7 +378,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
                                debug("%s: words:%d data:", __func__, words);
 
-                               int i = 0;
+                               i = 0;
                                while (words > i) {
                                        writeb(dout[i], &priv->regs->dr);
                                        debug("%02x ", dout[i]);
@@ -379,7 +392,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
                        }
                }
        } else if (din) {
-               u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
+               ccr_reg = _stm32_qspi_gen_ccr(priv);
                ccr_reg |= STM32_QSPI_CCR_IND_READ
                                << STM32_QSPI_CCR_FMODE_SHIFT;
 
@@ -394,7 +407,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
                debug("%s: data:", __func__);
 
-               int i = 0;
+               i = 0;
                while (words > i) {
                        din[i] = readb(&priv->regs->dr);
                        debug("%02x ", din[i]);
@@ -408,27 +421,23 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 
 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-       struct fdt_resource res_regs, res_mem;
+       struct resource res_regs, res_mem;
        struct stm32_qspi_platdata *plat = bus->platdata;
-       const void *blob = gd->fdt_blob;
-       int node = dev_of_offset(bus);
        int ret;
 
-       ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-                                    "QuadSPI", &res_regs);
+       ret = dev_read_resource_byname(bus, "qspi", &res_regs);
        if (ret) {
                debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
                return -ENOMEM;
        }
-       ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
-                                    "QuadSPI-memory", &res_mem);
+       ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
        if (ret) {
                debug("Error: can't get mmap base address(ret = %d)!\n", ret);
                return -ENOMEM;
        }
 
-       plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
-                                       STM32_QSPI_DEFAULT_SCK_FREQ);
+       plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
+                                           STM32_QSPI_DEFAULT_SCK_FREQ);
 
        plat->base = res_regs.start;
        plat->memory_map = res_mem.start;
@@ -448,6 +457,9 @@ static int stm32_qspi_probe(struct udevice *bus)
        struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
        struct stm32_qspi_priv *priv = dev_get_priv(bus);
        struct dm_spi_bus *dm_spi_bus;
+       struct clk clk;
+       struct reset_ctl reset_ctl;
+       int ret;
 
        dm_spi_bus = bus->uclass_priv;
 
@@ -457,9 +469,6 @@ static int stm32_qspi_probe(struct udevice *bus)
 
        priv->max_hz = plat->max_hz;
 
-#ifdef CONFIG_CLK
-       int ret;
-       struct clk clk;
        ret = clk_get_by_index(bus, 0, &clk);
        if (ret < 0)
                return ret;
@@ -477,7 +486,19 @@ static int stm32_qspi_probe(struct udevice *bus)
                return priv->clock_rate;
        }
 
-#endif
+       ret = reset_get_by_index(bus, 0, &reset_ctl);
+       if (ret) {
+               if (ret != -ENOENT) {
+                       dev_err(bus, "failed to get reset\n");
+                       clk_disable(&clk);
+                       return ret;
+               }
+       } else {
+               /* Reset QSPI controller */
+               reset_assert(&reset_ctl);
+               udelay(2);
+               reset_deassert(&reset_ctl);
+       }
 
        setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 
@@ -494,10 +515,17 @@ static int stm32_qspi_claim_bus(struct udevice *dev)
        struct stm32_qspi_priv *priv;
        struct udevice *bus;
        struct spi_flash *flash;
+       struct dm_spi_slave_platdata *slave_plat;
 
        bus = dev->parent;
        priv = dev_get_priv(bus);
        flash = dev_get_uclass_priv(dev);
+       slave_plat = dev_get_parent_platdata(dev);
+
+       if (slave_plat->cs >= STM32_MAX_NORCHIP)
+               return -ENODEV;
+
+       _stm32_qspi_set_cs(priv, slave_plat->cs);
 
        _stm32_qspi_set_flash_size(priv, flash->size);
 
@@ -520,7 +548,7 @@ static int stm32_qspi_release_bus(struct udevice *dev)
 }
 
 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
-               const void *dout, void *din, unsigned long flags)
+                          const void *dout, void *din, unsigned long flags)
 {
        struct stm32_qspi_priv *priv;
        struct udevice *bus;
@@ -538,12 +566,13 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 {
        struct stm32_qspi_platdata *plat = bus->platdata;
        struct stm32_qspi_priv *priv = dev_get_priv(bus);
+       u32 qspi_clk = priv->clock_rate;
+       u32 prescaler = 255;
+       u32 csht;
 
        if (speed > plat->max_hz)
                speed = plat->max_hz;
 
-       u32 qspi_clk = priv->clock_rate;
-       u32 prescaler = 255;
        if (speed > 0) {
                prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
                if (prescaler > 255)
@@ -552,7 +581,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
                        prescaler = 0;
        }
 
-       u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
+       csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
        csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 
        _stm32_qspi_wait_for_not_busy(priv);
@@ -562,7 +591,6 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
                        STM32_QSPI_CR_PRESCALER_SHIFT,
                        prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 
-
        clrsetbits_le32(&priv->regs->dcr,
                        STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
                        csht << STM32_QSPI_DCR_CSHT_SHIFT);
@@ -632,6 +660,7 @@ static const struct dm_spi_ops stm32_qspi_ops = {
 
 static const struct udevice_id stm32_qspi_ids[] = {
        { .compatible = "st,stm32-qspi" },
+       { .compatible = "st,stm32f469-qspi" },
        { }
 };