]> git.sur5r.net Git - u-boot/commitdiff
Update origin and copyright information in arch-at91sam9 header files
authorStelian Pop <stelian@popies.net>
Thu, 8 May 2008 20:52:10 +0000 (22:52 +0200)
committerWolfgang Denk <wd@denx.de>
Fri, 9 May 2008 22:28:51 +0000 (00:28 +0200)
When doing the AT91CAP9/AT91SAM9 port, a number of header files were
copied from the Linux kernel sources. This patch explicitly specifies
this origin for all the copied headers, and for those missing copyright
information, adds it.

Additionaly, the header file 'at91sam926x_mc.h' has been superceeded
in the latest kernel sources by 'at91sam9_smc.h'.

The copyright information has been confirmed by the AT91 Linux kernel
maintainer, Andrew Victor <avictor.za@gmail.com>.

Signed-off-by: Stelian Pop <stelian@popies.net>
16 files changed:
board/atmel/at91cap9adk/at91cap9adk.c
board/atmel/at91sam9260ek/at91sam9260ek.c
include/asm-arm/arch-at91sam9/at91_pio.h
include/asm-arm/arch-at91sam9/at91_pit.h
include/asm-arm/arch-at91sam9/at91_pmc.h
include/asm-arm/arch-at91sam9/at91_rstc.h
include/asm-arm/arch-at91sam9/at91_spi.h
include/asm-arm/arch-at91sam9/at91cap9.h
include/asm-arm/arch-at91sam9/at91cap9_matrix.h
include/asm-arm/arch-at91sam9/at91sam9260.h
include/asm-arm/arch-at91sam9/at91sam9260_matrix.h
include/asm-arm/arch-at91sam9/at91sam926x_mc.h [deleted file]
include/asm-arm/arch-at91sam9/at91sam9_smc.h [new file with mode: 0644]
include/asm-arm/arch-at91sam9/gpio.h
include/asm-arm/arch-at91sam9/hardware.h
include/asm-arm/arch-at91sam9/io.h

index 24861ba49de757faabb9f59326d220d6c91d0cee..9f3a5d9b9014bf832bcaaa28f1369ad172c19568 100644 (file)
@@ -25,7 +25,7 @@
 #include <common.h>
 #include <asm/arch/at91cap9.h>
 #include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
index a55468e30d066e177ec673f9da4f7b41fd352a8f..19b540fb7bcb67d8c7d6018c88f68f26dc5abbd7 100644 (file)
@@ -25,7 +25,7 @@
 #include <common.h>
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
index 84c3866d309f84ce818042a6b0ecd3736d40f0ff..f6ce1f924ef0a4a83503a40ac25e9f9a42c166f1 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/at91_pio.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
index 5026325a5ae419b13cad93db555f2b1f79a74983..94dd242a5fbe37ee83c6703c062c33fe558a1f6d 100644 (file)
@@ -1,5 +1,8 @@
 /*
- * include/asm-arm/arch-at91/at91_pit.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
  *
  * Periodic Interval Timer (PIT) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
index 52cd8e5dabc996823368b60797e4a43d6764ec1d..103be8699983fc4720f0bf9513f194e929446f62 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/at91_pmc.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h]
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
index fb8d1618a231a40b2d23387344b53cd09a5828fd..e49caef92189c0e45ff12964c0d8f849fa4dafa9 100644 (file)
@@ -1,5 +1,8 @@
 /*
- * include/asm-arm/arch-at91/at91_rstc.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
  *
  * Reset Controller (RSTC) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
index aaad92621c8ddb0e3422dc21b23c2a2a8207f250..30643c60920b068bce6816fd77545f34a2fb2999 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/at91_spi.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
  *
  * Copyright (C) 2005 Ivan Kokshaysky
  * Copyright (C) SAN People
index e16909c641da62928453a95fc327f298df8b4832..d1b33a069a9c33de4ad4e053eb2811ffc3ef673a 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/at91cap9.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
  *
  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
index a641686b6c3d3b492a4df2905d5bbc3ebc7cde51..22b7e9b8f4bd354d205dafd70ab627a19764c526 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/at91cap9_matrix.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
  *
  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
index 1bf45989b5f4cbe218befc1644e6f3fddd54394d..920a7f3c9ffeb59b3edcb080b9f41e581ba5fa78 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/at91sam9260.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
  *
  * (C) 2006 Andrew Victor
  *
index a8e9fec6c7352ad5ff7441d3f0aa315df42ae689..f8b023d9327c3b1ee5b589bb28850101ab03f32f 100644 (file)
@@ -1,5 +1,7 @@
 /*
- * include/asm-arm/arch-at91/at91sam9260_matrix.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
+ *
+ * Copyright (C) 2007 Atmel Corporation.
  *
  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
  * Based on AT91SAM9260 datasheet revision B.
diff --git a/include/asm-arm/arch-at91sam9/at91sam926x_mc.h b/include/asm-arm/arch-at91sam9/at91sam926x_mc.h
deleted file mode 100644 (file)
index 041138f..0000000
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91sam926x_mc.h
- *
- * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM926x_MC_H
-#define AT91SAM926x_MC_H
-
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR         (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
-#define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                        AT91_SDRAMC_MODE_NORMAL         0
-#define                        AT91_SDRAMC_MODE_NOP            1
-#define                        AT91_SDRAMC_MODE_PRECHARGE      2
-#define                        AT91_SDRAMC_MODE_LMR            3
-#define                        AT91_SDRAMC_MODE_REFRESH        4
-#define                        AT91_SDRAMC_MODE_EXT_LMR        5
-#define                        AT91_SDRAMC_MODE_DEEP           6
-
-#define AT91_SDRAMC_TR         (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
-#define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
-
-#define AT91_SDRAMC_CR         (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
-#define                AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
-#define                        AT91_SDRAMC_NC_8        (0 << 0)
-#define                        AT91_SDRAMC_NC_9        (1 << 0)
-#define                        AT91_SDRAMC_NC_10       (2 << 0)
-#define                        AT91_SDRAMC_NC_11       (3 << 0)
-#define                AT91_SDRAMC_NR          (3 << 2)                /* Number of Row Bits */
-#define                        AT91_SDRAMC_NR_11       (0 << 2)
-#define                        AT91_SDRAMC_NR_12       (1 << 2)
-#define                        AT91_SDRAMC_NR_13       (2 << 2)
-#define                AT91_SDRAMC_NB          (1 << 4)                /* Number of Banks */
-#define                        AT91_SDRAMC_NB_2        (0 << 4)
-#define                        AT91_SDRAMC_NB_4        (1 << 4)
-#define                AT91_SDRAMC_CAS         (3 << 5)                /* CAS Latency */
-#define                        AT91_SDRAMC_CAS_1       (1 << 5)
-#define                        AT91_SDRAMC_CAS_2       (2 << 5)
-#define                        AT91_SDRAMC_CAS_3       (3 << 5)
-#define                AT91_SDRAMC_DBW         (1 << 7)                /* Data Bus Width */
-#define                        AT91_SDRAMC_DBW_32      (0 << 7)
-#define                        AT91_SDRAMC_DBW_16      (1 << 7)
-#define                AT91_SDRAMC_TWR         (0xf <<  8)             /* Write Recovery Delay */
-#define                AT91_SDRAMC_TRC         (0xf << 12)             /* Row Cycle Delay */
-#define                AT91_SDRAMC_TRP         (0xf << 16)             /* Row Precharge Delay */
-#define                AT91_SDRAMC_TRCD        (0xf << 20)             /* Row to Column Delay */
-#define                AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
-#define                AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_LPR                (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
-#define                AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
-#define                        AT91_SDRAMC_LPCB_DISABLE                0
-#define                        AT91_SDRAMC_LPCB_SELF_REFRESH           1
-#define                        AT91_SDRAMC_LPCB_POWER_DOWN             2
-#define                        AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
-#define                AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
-#define                AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
-#define                AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
-#define                AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
-#define                        AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
-#define                        AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
-#define                        AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
-
-#define AT91_SDRAMC_IER                (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR                (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR                (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR                (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
-#define                AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
-
-#define AT91_SDRAMC_MDR                (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
-#define                AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
-#define                        AT91_SDRAMC_MD_SDRAM            0
-#define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
-
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_SETUP(n)      (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
-#define                AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
-#define                        AT91_SMC_NWESETUP_(x)   ((x) << 0)
-#define                AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
-#define                        AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
-#define                AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
-#define                        AT91_SMC_NRDSETUP_(x)   ((x) << 16)
-#define                AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
-#define                        AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
-
-#define AT91_SMC_PULSE(n)      (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
-#define                AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
-#define                        AT91_SMC_NWEPULSE_(x)   ((x) << 0)
-#define                AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
-#define                        AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define                AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
-#define                        AT91_SMC_NRDPULSE_(x)   ((x) << 16)
-#define                AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
-#define                        AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)      (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
-#define                AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
-#define                        AT91_SMC_NWECYCLE_(x)   ((x) << 0)
-#define                AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
-#define                        AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
-
-#define AT91_SMC_MODE(n)       (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
-#define                AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
-#define                AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
-#define                AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
-#define                        AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
-#define                        AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
-#define                        AT91_SMC_EXNWMODE_READY         (3 << 4)
-#define                AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
-#define                        AT91_SMC_BAT_SELECT             (0 << 8)
-#define                        AT91_SMC_BAT_WRITE              (1 << 8)
-#define                AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
-#define                        AT91_SMC_DBW_8                  (0 << 12)
-#define                        AT91_SMC_DBW_16                 (1 << 12)
-#define                        AT91_SMC_DBW_32                 (2 << 12)
-#define                AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
-#define                        AT91_SMC_TDF_(x)                ((x) << 16)
-#define                AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
-#define                AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
-#define                AT91_SMC_PS             (3 << 28)                       /* Page Size */
-#define                        AT91_SMC_PS_4                   (0 << 28)
-#define                        AT91_SMC_PS_8                   (1 << 28)
-#define                        AT91_SMC_PS_16                  (2 << 28)
-#define                        AT91_SMC_PS_32                  (3 << 28)
-
-#if defined(AT91_SMC1)         /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)     (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)     (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)     (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)      (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
-#endif
diff --git a/include/asm-arm/arch-at91sam9/at91sam9_smc.h b/include/asm-arm/arch-at91sam9/at91sam9_smc.h
new file mode 100644 (file)
index 0000000..d64511b
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
+ *
+ * Copyright (C) 2007 Andrew Victor
+ * Copyright (C) 2007 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+
+#define AT91_SMC_SETUP(n)      (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define                AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                        AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define                AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                        AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define                AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                        AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define                AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                        AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+
+#define AT91_SMC_PULSE(n)      (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define                AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                        AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define                AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                        AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define                AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                        AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define                AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                        AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n)      (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define                AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                        AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define                AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                        AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+
+#define AT91_SMC_MODE(n)       (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define                AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define                AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define                AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
+#define                        AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
+#define                        AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
+#define                        AT91_SMC_EXNWMODE_READY         (3 << 4)
+#define                AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                        AT91_SMC_BAT_SELECT             (0 << 8)
+#define                        AT91_SMC_BAT_WRITE              (1 << 8)
+#define                AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                        AT91_SMC_DBW_8                  (0 << 12)
+#define                        AT91_SMC_DBW_16                 (1 << 12)
+#define                        AT91_SMC_DBW_32                 (2 << 12)
+#define                AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                        AT91_SMC_TDF_(x)                ((x) << 16)
+#define                AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define                AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define                AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                        AT91_SMC_PS_4                   (0 << 28)
+#define                        AT91_SMC_PS_8                   (1 << 28)
+#define                        AT91_SMC_PS_16                  (2 << 28)
+#define                        AT91_SMC_PS_32                  (3 << 28)
+
+#if defined(AT91_SMC1)         /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n)     (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n)     (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n)     (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n)      (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+
+#endif
index 2500eae2a4af1fde4ed2d7cac17e255254ea9a2f..c157e107e14f698ac10d0a237f72421b1ca33f6d 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/gpio.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
  *
  *  Copyright (C) 2005 HP Labs
  *
index 80b334f36e38991b07a8d31d2c11549fb9c8db2d..d2fe45388b3908b5b97334cd1531599437ff01ec 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/hardware.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h]
  *
  *  Copyright (C) 2003 SAN People
  *  Copyright (C) 2003 ATMEL
index be9e9abe5694b905cd52fa261c7d87883ad8189a..f09b2df0e311a08e3bdf64458cf4434ff3e7b2a9 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-at91/io.h
+ * [origin: Linux kernel include/asm-arm/arch-at91/io.h]
  *
  *  Copyright (C) 2003 SAN People
  *