]> git.sur5r.net Git - u-boot/commitdiff
arm: dts: imx7: sync with Linux
authorStefan Agner <stefan.agner@toradex.com>
Fri, 22 Jun 2018 16:06:19 +0000 (18:06 +0200)
committerStefano Babic <sbabic@denx.de>
Wed, 27 Jun 2018 07:07:55 +0000 (09:07 +0200)
Sync with Linux commit 60cc43fc8884 ("Linux 4.17-rc1").

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
arch/arm/dts/imx7s.dtsi
include/dt-bindings/clock/imx7d-clock.h
include/dt-bindings/power/imx7-power.h [new file with mode: 0644]

index a7d48e785d34113d3796fb6858194351010b6705..4d42335c0dee991aa18ff8c40526865eb89cd97c 100644 (file)
@@ -42,6 +42,7 @@
  */
 
 #include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -57,7 +58,7 @@
         * Also for U-Boot there must be a pre-existing /memory node.
         */
        chosen {};
-       memory { device_type = "memory"; reg = <0 0>; };
+       memory { device_type = "memory"; };
 
        aliases {
                gpio0 = &gpio1;
                clock-output-names = "osc";
        };
 
+       usbphynop1: usbphynop1 {
+               compatible = "usb-nop-xceiv";
+               clocks = <&clks IMX7D_USB_PHY1_CLK>;
+               clock-names = "main_clk";
+               #phy-cells = <0>;
+       };
+
+       usbphynop3: usbphynop3 {
+               compatible = "usb-nop-xceiv";
+               clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
+               clock-names = "main_clk";
+               #phy-cells = <0>;
+       };
+
+       pmu {
+               compatible = "arm,cortex-a7-pmu";
+               interrupt-parent = <&gpc>;
+               interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>;
+       };
+
+       replicator {
+               /*
+                * non-configurable replicators don't show up on the
+                * AMBA bus.  As such no need to add "arm,primecell"
+                */
+               compatible = "arm,coresight-replicator";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                               /* replicator output ports */
+                       port@0 {
+                               reg = <0>;
+                               replicator_out_port0: endpoint {
+                                       remote-endpoint = <&tpiu_in_port>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               replicator_out_port1: endpoint {
+                                       remote-endpoint = <&etr_in_port>;
+                               };
+                       };
+
+                       /* replicator input port */
+                       port@2 {
+                               reg = <0>;
+                               replicator_in_port0: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&etf_out_port>;
+                               };
+                       };
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&intc>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-               interrupt-parent = <&intc>;
+               interrupt-parent = <&gpc>;
                ranges;
 
                funnel@30041000 {
                        };
                };
 
-               replicator {
-                       /*
-                        * non-configurable replicators don't show up on the
-                        * AMBA bus.  As such no need to add "arm,primecell"
-                        */
-                       compatible = "arm,coresight-replicator";
-
-                       ports {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-
-                               /* replicator output ports */
-                               port@0 {
-                                       reg = <0>;
-                                       replicator_out_port0: endpoint {
-                                               remote-endpoint = <&tpiu_in_port>;
-                                       };
-                               };
-
-                               port@1 {
-                                       reg = <1>;
-                                       replicator_out_port1: endpoint {
-                                               remote-endpoint = <&etr_in_port>;
-                                       };
-                               };
-
-                               /* replicator input port */
-                               port@2 {
-                                       reg = <0>;
-                                       replicator_in_port0: endpoint {
-                                               slave-mode;
-                                               remote-endpoint = <&etf_out_port>;
-                                       };
-                               };
-                       };
-               };
-
                intc: interrupt-controller@31001000 {
                        compatible = "arm,cortex-a7-gic";
                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                        #interrupt-cells = <3>;
                        interrupt-controller;
+                       interrupt-parent = <&intc>;
                        reg = <0x31001000 0x1000>,
                              <0x31002000 0x2000>,
                              <0x31004000 0x2000>,
                              <0x31006000 0x2000>;
                };
 
-               timer {
-                       compatible = "arm,armv7-timer";
-                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-               };
-
                aips1: aips-bus@30000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                                status = "disabled";
                        };
 
+                       kpp: kpp@30320000 {
+                               compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+                               reg = <0x30320000 0x10000>;
+                               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+                               status = "disabled";
+                       };
+
                        iomuxc: iomuxc@30330000 {
                                compatible = "fsl,imx7d-iomuxc";
                                reg = <0x30330000 0x10000>;
                        };
 
                        gpr: iomuxc-gpr@30340000 {
-                               compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
+                               compatible = "fsl,imx7d-iomuxc-gpr",
+                                       "fsl,imx6q-iomuxc-gpr", "syscon";
                                reg = <0x30340000 0x10000>;
                        };
 
                        ocotp: ocotp-ctrl@30350000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
                                compatible = "fsl,imx7d-ocotp", "syscon";
                                reg = <0x30350000 0x10000>;
                                clocks = <&clks IMX7D_OCOTP_CLK>;
+
+                               tempmon_calib: calib@3c {
+                                       reg = <0x3c 0x4>;
+                               };
+
+                               tempmon_temp_grade: temp-grade@10 {
+                                       reg = <0x10 0x4>;
+                               };
+                       };
+
+                       tempmon: tempmon {
+                               compatible = "fsl,imx7d-tempmon";
+                               interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               fsl,tempmon =<&anatop>;
+                               nvmem-cells = <&tempmon_calib>,
+                                       <&tempmon_temp_grade>;
+                               nvmem-cell-names = "calib", "temp_grade";
+                               clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
                        };
 
                        anatop: anatop@30360000 {
                                reg = <0x30360000 0x10000>;
                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
 
-                               reg_1p0d: regulator-vdd1p0d {
+                               reg_1p0d: regulator-vdd1p0d@30360210 {
+                                       reg = <0x30360210>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd1p0d";
                                        regulator-min-microvolt = <800000>;
                                        anatop-min-bit-val = <8>;
                                        anatop-min-voltage = <800000>;
                                        anatop-max-voltage = <1200000>;
+                                       anatop-enable-bit = <0>;
                                };
                        };
 
                                        offset = <0x34>;
                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
                                                     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_SNVS_CLK>;
+                                       clock-names = "snvs-rtc";
                                };
 
                                snvs_poweroff: snvs-poweroff {
                                        compatible = "syscon-poweroff";
                                        regmap = <&snvs>;
                                        offset = <0x38>;
+                                       value = <0x60>;
                                        mask = <0x60>;
                                };
 
                        };
 
                        src: src@30390000 {
-                               compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
+                               compatible = "fsl,imx7d-src", "syscon";
                                reg = <0x30390000 0x10000>;
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                                #reset-cells = <1>;
                        };
+
+                       gpc: gpc@303a0000 {
+                               compatible = "fsl,imx7d-gpc";
+                               reg = <0x303a0000 0x10000>;
+                               interrupt-controller;
+                               interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                               #interrupt-cells = <3>;
+                               interrupt-parent = <&intc>;
+                               #power-domain-cells = <1>;
+
+                               pgc {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       pgc_pcie_phy: pgc-power-domain@1 {
+                                               #power-domain-cells = <0>;
+                                               reg = <1>;
+                                               power-supply = <&reg_1p0d>;
+                                       };
+                               };
+                       };
                };
 
                aips2: aips-bus@30400000 {
                                clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
                                         <&clks IMX7D_PWM1_ROOT_CLK>;
                                clock-names = "ipg", "per";
-                               #pwm-cells = <2>;
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
                                clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
                                         <&clks IMX7D_PWM2_ROOT_CLK>;
                                clock-names = "ipg", "per";
-                               #pwm-cells = <2>;
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
                                clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
                                         <&clks IMX7D_PWM3_ROOT_CLK>;
                                clock-names = "ipg", "per";
-                               #pwm-cells = <2>;
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
                                clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
                                         <&clks IMX7D_PWM4_ROOT_CLK>;
                                clock-names = "ipg", "per";
-                               #pwm-cells = <2>;
+                               #pwm-cells = <3>;
                                status = "disabled";
                        };
 
                        reg = <0x30800000 0x400000>;
                        ranges;
 
-                       ecspi1: ecspi@30820000 {
+                       spba-bus@30800000 {
+                               compatible = "fsl,spba-bus", "simple-bus";
                                #address-cells = <1>;
-                               #size-cells = <0>;
-                               compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                               reg = <0x30820000 0x10000>;
-                               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
-                                       <&clks IMX7D_ECSPI1_ROOT_CLK>;
-                               clock-names = "ipg", "per";
-                               status = "disabled";
-                       };
+                               #size-cells = <1>;
+                               reg = <0x30800000 0x100000>;
+                               ranges;
+
+                               ecspi1: ecspi@30820000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                       reg = <0x30820000 0x10000>;
+                                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+                                               <&clks IMX7D_ECSPI1_ROOT_CLK>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
 
-                       ecspi2: ecspi@30830000 {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                               reg = <0x30830000 0x10000>;
-                               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
-                                       <&clks IMX7D_ECSPI2_ROOT_CLK>;
-                               clock-names = "ipg", "per";
-                               status = "disabled";
-                       };
+                               ecspi2: ecspi@30830000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                       reg = <0x30830000 0x10000>;
+                                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+                                               <&clks IMX7D_ECSPI2_ROOT_CLK>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
 
-                       ecspi3: ecspi@30840000 {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-                               compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                               reg = <0x30840000 0x10000>;
-                               interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
-                                       <&clks IMX7D_ECSPI3_ROOT_CLK>;
-                               clock-names = "ipg", "per";
-                               status = "disabled";
-                       };
+                               ecspi3: ecspi@30840000 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                       reg = <0x30840000 0x10000>;
+                                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+                                               <&clks IMX7D_ECSPI3_ROOT_CLK>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
 
-                       uart1: serial@30860000 {
-                               compatible = "fsl,imx7d-uart",
-                                            "fsl,imx6q-uart";
-                               reg = <0x30860000 0x10000>;
-                               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_UART1_ROOT_CLK>,
-                                       <&clks IMX7D_UART1_ROOT_CLK>;
-                               clock-names = "ipg", "per";
-                               status = "disabled";
-                       };
+                               uart1: serial@30860000 {
+                                       compatible = "fsl,imx7d-uart",
+                                                    "fsl,imx6q-uart";
+                                       reg = <0x30860000 0x10000>;
+                                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+                                               <&clks IMX7D_UART1_ROOT_CLK>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
 
-                       uart2: serial@30890000 {
-                               compatible = "fsl,imx7d-uart",
-                                            "fsl,imx6q-uart";
-                               reg = <0x30890000 0x10000>;
-                               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_UART2_ROOT_CLK>,
-                                       <&clks IMX7D_UART2_ROOT_CLK>;
-                               clock-names = "ipg", "per";
-                               status = "disabled";
-                       };
+                               uart2: serial@30890000 {
+                                       compatible = "fsl,imx7d-uart",
+                                                    "fsl,imx6q-uart";
+                                       reg = <0x30890000 0x10000>;
+                                       interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+                                               <&clks IMX7D_UART2_ROOT_CLK>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
 
-                       uart3: serial@30880000 {
-                               compatible = "fsl,imx7d-uart",
-                                            "fsl,imx6q-uart";
-                               reg = <0x30880000 0x10000>;
-                               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_UART3_ROOT_CLK>,
-                                       <&clks IMX7D_UART3_ROOT_CLK>;
-                               clock-names = "ipg", "per";
-                               status = "disabled";
-                       };
+                               uart3: serial@30880000 {
+                                       compatible = "fsl,imx7d-uart",
+                                                    "fsl,imx6q-uart";
+                                       reg = <0x30880000 0x10000>;
+                                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+                                               <&clks IMX7D_UART3_ROOT_CLK>;
+                                       clock-names = "ipg", "per";
+                                       status = "disabled";
+                               };
 
-                       sai1: sai@308a0000 {
-                               #sound-dai-cells = <0>;
-                               compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                               reg = <0x308a0000 0x10000>;
-                               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_SAI1_IPG_CLK>,
-                                        <&clks IMX7D_SAI1_ROOT_CLK>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>;
-                               clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                               dma-names = "rx", "tx";
-                               dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
-                               status = "disabled";
-                       };
+                               sai1: sai@308a0000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                       reg = <0x308a0000 0x10000>;
+                                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+                                                <&clks IMX7D_SAI1_ROOT_CLK>,
+                                                <&clks IMX7D_CLK_DUMMY>,
+                                                <&clks IMX7D_CLK_DUMMY>;
+                                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                       dma-names = "rx", "tx";
+                                       dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+                                       status = "disabled";
+                               };
 
-                       sai2: sai@308b0000 {
-                               #sound-dai-cells = <0>;
-                               compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                               reg = <0x308b0000 0x10000>;
-                               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_SAI2_IPG_CLK>,
-                                        <&clks IMX7D_SAI2_ROOT_CLK>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>;
-                               clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                               dma-names = "rx", "tx";
-                               dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
-                               status = "disabled";
+                               sai2: sai@308b0000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                       reg = <0x308b0000 0x10000>;
+                                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+                                                <&clks IMX7D_SAI2_ROOT_CLK>,
+                                                <&clks IMX7D_CLK_DUMMY>,
+                                                <&clks IMX7D_CLK_DUMMY>;
+                                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                       dma-names = "rx", "tx";
+                                       dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+                                       status = "disabled";
+                               };
+
+                               sai3: sai@308c0000 {
+                                       #sound-dai-cells = <0>;
+                                       compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                       reg = <0x308c0000 0x10000>;
+                                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+                                                <&clks IMX7D_SAI3_ROOT_CLK>,
+                                                <&clks IMX7D_CLK_DUMMY>,
+                                                <&clks IMX7D_CLK_DUMMY>;
+                                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                       dma-names = "rx", "tx";
+                                       dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+                                       status = "disabled";
+                               };
                        };
 
-                       sai3: sai@308c0000 {
-                               #sound-dai-cells = <0>;
-                               compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                               reg = <0x308c0000 0x10000>;
-                               interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_SAI3_IPG_CLK>,
-                                        <&clks IMX7D_SAI3_ROOT_CLK>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>;
-                               clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                               dma-names = "rx", "tx";
-                               dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
-                               status = "disabled";
+                       crypto: caam@30900000 {
+                               compatible = "fsl,sec-v4.0";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x30900000 0x40000>;
+                               ranges = <0 0x30900000 0x40000>;
+                               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX7D_CAAM_CLK>,
+                                        <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+                               clock-names = "ipg", "aclk";
+
+                               sec_jr0: jr0@1000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x1000 0x1000>;
+                                       interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr1: jr1@2000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x2000 0x1000>;
+                                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr2: jr1@3000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x3000 0x1000>;
+                                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                               };
                        };
 
                        flexcan1: can@30a00000 {
                                reg = <0x30b30200 0x200>;
                        };
 
-                       usbphynop1: usbphynop1 {
-                               compatible = "usb-nop-xceiv";
-                               clocks = <&clks IMX7D_USB_PHY1_CLK>;
-                               clock-names = "main_clk";
-                       };
-
-                       usbphynop3: usbphynop3 {
-                               compatible = "usb-nop-xceiv";
-                               clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
-                               clock-names = "main_clk";
-                       };
-
                        usdhc1: usdhc@30b40000 {
                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
                                reg = <0x30b40000 0x10000>;
                                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_CLK_DUMMY>,
-                                       <&clks IMX7D_CLK_DUMMY>,
+                               clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+                                       <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
                                        <&clks IMX7D_USDHC1_ROOT_CLK>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
                                reg = <0x30b50000 0x10000>;
                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_CLK_DUMMY>,
-                                       <&clks IMX7D_CLK_DUMMY>,
+                               clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+                                       <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
                                        <&clks IMX7D_USDHC2_ROOT_CLK>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
                                reg = <0x30b60000 0x10000>;
                                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_CLK_DUMMY>,
-                                       <&clks IMX7D_CLK_DUMMY>,
+                               clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+                                       <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
                                        <&clks IMX7D_USDHC3_ROOT_CLK>;
                                clock-names = "ipg", "ahb", "per";
                                bus-width = <4>;
                        fec1: ethernet@30be0000 {
                                compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
                                reg = <0x30be0000 0x10000>;
-                               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                               interrupt-names = "int0", "int1", "int2", "pps";
+                               interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-                                       <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                                       <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
                                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
                                        <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
                                status = "disabled";
                        };
                };
+
+               dma_apbh: dma-apbh@33000000 {
+                       compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+                       reg = <0x33000000 0x2000>;
+                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+                       #dma-cells = <1>;
+                       dma-channels = <4>;
+                       clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+               };
+
+               gpmi: gpmi-nand@33002000{
+                       compatible = "fsl,imx7d-gpmi-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+                       reg-names = "gpmi-nand", "bch";
+                       interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "bch";
+                       clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+                               <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+                       clock-names = "gpmi_io", "gpmi_bch_apb";
+                       dmas = <&dma_apbh 0>;
+                       dma-names = "rx-tx";
+                       status = "disabled";
+                       assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+                       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+               };
        };
 };
index a7a1a50f33efe98b00f6f818d2cca609019673bc..b2325d3e236a72ad36f6e29412aa57f6c397e08c 100644 (file)
 #define IMX7D_ARM_M4_ROOT_SRC          67
 #define IMX7D_ARM_M4_ROOT_CG           68
 #define IMX7D_ARM_M4_ROOT_DIV          69
-#define IMX7D_ARM_M0_ROOT_CLK          70
-#define IMX7D_ARM_M0_ROOT_SRC          71
-#define IMX7D_ARM_M0_ROOT_CG           72
-#define IMX7D_ARM_M0_ROOT_DIV          73
+#define IMX7D_ARM_M0_ROOT_CLK          70      /* unused */
+#define IMX7D_ARM_M0_ROOT_SRC          71      /* unused */
+#define IMX7D_ARM_M0_ROOT_CG           72      /* unused */
+#define IMX7D_ARM_M0_ROOT_DIV          73      /* unused */
 #define IMX7D_MAIN_AXI_ROOT_CLK                74
 #define IMX7D_MAIN_AXI_ROOT_SRC                75
 #define IMX7D_MAIN_AXI_ROOT_CG         76
 #define IMX7D_CLK_ARM                  437
 #define IMX7D_CKIL                     438
 #define IMX7D_OCOTP_CLK                        439
-#define IMX7D_CLK_END                  440
+#define IMX7D_NAND_RAWNAND_CLK         440
+#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
+#define IMX7D_SNVS_CLK                 442
+#define IMX7D_CAAM_CLK                 443
+#define IMX7D_KPP_ROOT_CLK             444
+#define IMX7D_CLK_END                  445
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h
new file mode 100644 (file)
index 0000000..3a181e4
--- /dev/null
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 2017 Impinj
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_IMX7_POWER_H__
+#define __DT_BINDINGS_IMX7_POWER_H__
+
+#define IMX7_POWER_DOMAIN_MIPI_PHY             0
+#define IMX7_POWER_DOMAIN_PCIE_PHY             1
+#define IMX7_POWER_DOMAIN_USB_HSIC_PHY         2
+
+#endif