- grub-efi-ia32-bin
- rpm2cpio
- wget
+ - device-tree-compiler
install:
# install latest device tree compiler
- - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
- - make -j4 -C /tmp/dtc
+ #- git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ #- make -j4 -C /tmp/dtc
# Clone uboot-test-hooks
- git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
F: arch/arm/cpu/armv7/stv0991/
F: arch/arm/include/asm/arch-stv0991/
+ARM STI
+M: Patrice Chotard <patrice.chotard@st.com>
+S: Maintained
+F: arch/arm/mach-sti/
+F: arch/arm/include/asm/arch-sti*/
+
ARM SUNXI
M: Jagan Teki <jagan@openedev.com>
M: Maxime Ripard <maxime.ripard@free-electrons.com>
VERSION = 2017
PATCHLEVEL = 03
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
export MAKE AWK PERL PYTHON
-export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
+export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
export KBUILD_CFLAGS KBUILD_AFLAGS
Thumb2 this flag will result in Thumb2 code generated by
GCC.
- CONFIG_ARM_ERRATA_716044
- CONFIG_ARM_ERRATA_742230
- CONFIG_ARM_ERRATA_743622
- CONFIG_ARM_ERRATA_751472
- CONFIG_ARM_ERRATA_761320
- CONFIG_ARM_ERRATA_773022
- CONFIG_ARM_ERRATA_774769
- CONFIG_ARM_ERRATA_794072
-
- If set, the workarounds for these ARM errata are applied early
- during U-Boot startup. Note that these options force the
- workarounds to be applied; no CPU-type/version detection
- exists, unlike the similar options in the Linux kernel. Do not
- set these options unless they apply!
-
COUNTER_FREQUENCY
Generic timer clock source frequency.
different from COUNTER_FREQUENCY, and can only be determined
at run time.
- NOTE: The following can be machine specific errata. These
- do have ability to provide rudimentary version and machine
- specific checks, but expect no product checks.
- CONFIG_ARM_ERRATA_430973
- CONFIG_ARM_ERRATA_454179
- CONFIG_ARM_ERRATA_621766
- CONFIG_ARM_ERRATA_798870
- CONFIG_ARM_ERRATA_801819
-
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
config HAS_THUMB2
bool
+# If set, the workarounds for these ARM errata are applied early during U-Boot
+# startup. Note that in general these options force the workarounds to be
+# applied; no CPU-type/version detection exists, unlike the similar options in
+# the Linux kernel. Do not set these options unless they apply! Also note that
+# the following can be machine specific errata. These do have ability to
+# provide rudimentary version and machine specific checks, but expect no
+# product checks:
+# CONFIG_ARM_ERRATA_430973
+# CONFIG_ARM_ERRATA_454179
+# CONFIG_ARM_ERRATA_621766
+# CONFIG_ARM_ERRATA_798870
+# CONFIG_ARM_ERRATA_801819
+config ARM_ERRATA_430973
+ bool
+
+config ARM_ERRATA_454179
+ bool
+
+config ARM_ERRATA_621766
+ bool
+
+config ARM_ERRATA_716044
+ bool
+
+config ARM_ERRATA_725233
+ bool
+
+config ARM_ERRATA_742230
+ bool
+
+config ARM_ERRATA_743622
+ bool
+
+config ARM_ERRATA_751472
+ bool
+
+config ARM_ERRATA_761320
+ bool
+
+config ARM_ERRATA_773022
+ bool
+
+config ARM_ERRATA_774769
+ bool
+
+config ARM_ERRATA_794072
+ bool
+
+config ARM_ERRATA_798870
+ bool
+
+config ARM_ERRATA_801819
+ bool
+
+config ARM_ERRATA_826974
+ bool
+
+config ARM_ERRATA_828024
+ bool
+
+config ARM_ERRATA_829520
+ bool
+
+config ARM_ERRATA_833069
+ bool
+
+config ARM_ERRATA_833471
+ bool
+
config CPU_ARM720T
bool
select SYS_CACHE_SHIFT_5
config OMAP34XX
bool "OMAP34XX SoC"
select ARCH_OMAP2
+ select ARM_ERRATA_430973
+ select ARM_ERRATA_454179
+ select ARM_ERRATA_621766
+ select ARM_ERRATA_725233
select USE_TINY_PRINTF
+ imply SPL_EXT_SUPPORT
+ imply SPL_FAT_SUPPORT
+ imply SPL_GPIO_SUPPORT
+ imply SPL_I2C_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_MMC_SUPPORT
+ imply SPL_NAND_SUPPORT
+ imply SPL_POWER_SUPPORT
+ imply SPL_SERIAL_SUPPORT
config OMAP44XX
bool "OMAP44XX SoC"
select ARCH_OMAP2
select USE_TINY_PRINTF
+ imply SPL_DISPLAY_PRINT
+ imply SPL_EXT_SUPPORT
+ imply SPL_FAT_SUPPORT
+ imply SPL_GPIO_SUPPORT
+ imply SPL_I2C_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_MMC_SUPPORT
+ imply SPL_NAND_SUPPORT
+ imply SPL_POWER_SUPPORT
+ imply SPL_SERIAL_SUPPORT
config OMAP54XX
bool "OMAP54XX SoC"
select ARCH_OMAP2
+ select ARM_ERRATA_798870
+ imply SPL_DISPLAY_PRINT
+ imply SPL_ENV_SUPPORT
+ imply SPL_EXT_SUPPORT
+ imply SPL_FAT_SUPPORT
+ imply SPL_GPIO_SUPPORT
+ imply SPL_I2C_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_MMC_SUPPORT
+ imply SPL_NAND_SUPPORT
+ imply SPL_POWER_SUPPORT
+ imply SPL_SERIAL_SUPPORT
config AM43XX
bool "AM43XX SoC"
select ENABLE_ARM_SOC_BOOT0_HOOK
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT
+ select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
config TARGET_CM_T43
bool "Support cm_t43"
select DM
select DM_SERIAL
+config ARCH_STI
+ bool "Support STMicrolectronics SoCs"
+ select CPU_V7
+ select DM
+ select DM_SERIAL
+ select BLK
+ select DM_MMC
+ help
+ Support for STMicroelectronics STiH407/10 SoC family.
+ This SoC is used on Linaro 96Board STiH410-B2260
+
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select OF_CONTROL
source "arch/arm/mach-socfpga/Kconfig"
+source "arch/arm/mach-sti/Kconfig"
+
source "arch/arm/mach-stm32/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
config MX6
bool
default y
+ select ARM_ERRATA_743622 if !MX6UL
+ select ARM_ERRATA_751472 if !MX6UL
+ select ARM_ERRATA_761320 if !MX6UL
+ select ARM_ERRATA_794072 if !MX6UL
config MX6D
bool
pop {r1-r5} @ Restore the cpu info - fall through
skip_errata_621766:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_725233
+ cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
+ bge skip_errata_725233
+
+ mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
+ orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_l2aux_ctrl
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_725233:
#endif
mov pc, r5 @ back to my caller
extra-y := start.o
obj-y += cpu.o
+
+obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o
--- /dev/null
+/*
+ * ARM Cortex M3/M4/M7 SysTick timer driver
+ * (C) Copyright 2017 Renesas Electronics Europe Ltd
+ *
+ * Based on arch/arm/mach-stm32/stm32f1/timer.c
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The SysTick timer is a 24-bit count down timer. The clock can be either the
+ * CPU clock or a reference clock. Since the timer will wrap around very quickly
+ * when using the CPU clock, and we do not handle the timer interrupts, it is
+ * expected that this driver is only ever used with a slow reference clock.
+ *
+ * The number of reference clock ticks that correspond to 10ms is normally
+ * defined in the SysTick Calibration register's TENMS field. However, on some
+ * devices this is wrong, so this driver allows the clock rate to be defined
+ * using CONFIG_SYS_HZ_CLOCK.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
+#define SYSTICK_BASE 0xE000E010
+
+struct cm3_systick {
+ uint32_t ctrl;
+ uint32_t reload_val;
+ uint32_t current_val;
+ uint32_t calibration;
+};
+
+#define TIMER_MAX_VAL 0x00FFFFFF
+#define SYSTICK_CTRL_EN BIT(0)
+/* Clock source: 0 = Ref clock, 1 = CPU clock */
+#define SYSTICK_CTRL_CPU_CLK BIT(2)
+#define SYSTICK_CAL_NOREF BIT(31)
+#define SYSTICK_CAL_SKEW BIT(30)
+#define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF
+
+/* read the 24-bit timer */
+static ulong read_timer(void)
+{
+ struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
+
+ /* The timer counts down, therefore convert to an incrementing timer */
+ return TIMER_MAX_VAL - readl(&systick->current_val);
+}
+
+int timer_init(void)
+{
+ struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
+ u32 cal;
+
+ writel(TIMER_MAX_VAL, &systick->reload_val);
+ /* Any write to current_val reg clears it to 0 */
+ writel(0, &systick->current_val);
+
+ cal = readl(&systick->calibration);
+ if (cal & SYSTICK_CAL_NOREF)
+ /* Use CPU clock, no interrupts */
+ writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl);
+ else
+ /* Use external clock, no interrupts */
+ writel(SYSTICK_CTRL_EN, &systick->ctrl);
+
+ /*
+ * If the TENMS field is inexact or wrong, specify the clock rate using
+ * CONFIG_SYS_HZ_CLOCK.
+ */
+#if defined(CONFIG_SYS_HZ_CLOCK)
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#else
+ gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+ gd->arch.lastinc = read_timer();
+
+ return 0;
+}
+
+/* return milli-seconds timer value */
+ulong get_timer(ulong base)
+{
+ unsigned long long t = get_ticks() * 1000;
+
+ return (ulong)((t / gd->arch.timer_rate_hz)) - base;
+}
+
+unsigned long long get_ticks(void)
+{
+ u32 now = read_timer();
+
+ if (now >= gd->arch.lastinc)
+ gd->arch.tbl += (now - gd->arch.lastinc);
+ else
+ gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now;
+
+ gd->arch.lastinc = now;
+
+ return gd->arch.tbl;
+}
+
+ulong get_tbclk(void)
+{
+ return gd->arch.timer_rate_hz;
+}
return !(addr & (align - 1)) && !(size & (align - 1));
}
-static u64 set_one_region(u64 start, u64 size, u64 attrs, int level)
+/* Use flag to indicate if attrs has more than d-cache attributes */
+static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
{
int levelshift = level2shift(level);
u64 levelsize = 1ULL << levelshift;
/* Can we can just modify the current level block PTE? */
if (is_aligned(start, size, levelsize)) {
- *pte &= ~PMD_ATTRINDX_MASK;
- *pte |= attrs;
+ if (flag) {
+ *pte &= ~PMD_ATTRMASK;
+ *pte |= attrs & PMD_ATTRMASK;
+ } else {
+ *pte &= ~PMD_ATTRINDX_MASK;
+ *pte |= attrs & PMD_ATTRINDX_MASK;
+ }
debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
return levelsize;
u64 r;
for (level = 1; level < 4; level++) {
- r = set_one_region(start, size, attrs, level);
+ /* Set d-cache attributes only */
+ r = set_one_region(start, size, attrs, false, level);
if (r) {
/* PTE successfully replaced */
size -= r;
flush_dcache_range(real_start, real_start + real_size);
}
+/*
+ * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
+ * The procecess is break-before-make. The target region will be marked as
+ * invalid during the process of changing.
+ */
+void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
+{
+ int level;
+ u64 r, size, start;
+
+ start = addr;
+ size = siz;
+ /*
+ * Loop through the address range until we find a page granule that fits
+ * our alignment constraints, then set it to "invalid".
+ */
+ while (size > 0) {
+ for (level = 1; level < 4; level++) {
+ /* Set PTE to fault */
+ r = set_one_region(start, size, PTE_TYPE_FAULT, true,
+ level);
+ if (r) {
+ /* PTE successfully invalidated */
+ size -= r;
+ start += r;
+ break;
+ }
+ }
+ }
+
+ flush_dcache_range(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ __asm_invalidate_tlb_all();
+
+ /*
+ * Loop through the address range until we find a page granule that fits
+ * our alignment constraints, then set it to the new cache attributes
+ */
+ start = addr;
+ size = siz;
+ while (size > 0) {
+ for (level = 1; level < 4; level++) {
+ /* Set PTE to new attributes */
+ r = set_one_region(start, size, attrs, true, level);
+ if (r) {
+ /* PTE successfully updated */
+ size -= r;
+ start += r;
+ break;
+ }
+ }
+ }
+ flush_dcache_range(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ __asm_invalidate_tlb_all();
+}
+
#else /* CONFIG_SYS_DCACHE_OFF */
/*
config ARCH_LS2080A
bool
select ARMV8_SET_SMPEN
+ select ARM_ERRATA_826974
+ select ARM_ERRATA_828024
+ select ARM_ERRATA_829520
+ select ARM_ERRATA_833471
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
+config FSL_MC_ENET
+ bool "Management Complex network"
+ depends on ARCH_LS2080A
+ default y
+ select RESV_RAM
+ help
+ Enable Management Complex (MC) network
+
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
clock, in another word SDHC_clk = Platform_clk / this_divider.
endmenu
+config RESV_RAM
+ bool
+ help
+ Reserve memory from the top, tracked by gd->arch.resv_ram. This
+ reserved RAM can be used by special driver that resides in memory
+ after U-Boot exits. It's up to implementation to allocate and allow
+ access to this reserved memory. For example, the reserved RAM can
+ be at the high end of physical memory. The reserve RAM may be
+ excluded from memory bank(s) passed to OS, or marked as reserved.
+
config SYS_FSL_ERRATUM_A008336
bool
config SYS_FSL_ERRATUM_A009929
bool
+
+config SYS_MC_RSV_MEM_ALIGN
+ hex "Management Complex reserved memory alignment"
+ depends on RESV_RAM
+ default 0x20000000
+ help
+ Reserved memory needs to be aligned for MC to use. Default value
+ is 512MB.
{
u64 tlb_addr_save = gd->arch.tlb_addr;
unsigned int el = current_el();
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
int index;
-#endif
mem_map = final_map;
+ /* Update mapping for DDR to actual size */
+ for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
+ /*
+ * Find the entry for DDR mapping and update the address and
+ * size. Zero-sized mapping will be skipped when creating MMU
+ * table.
+ */
+ switch (final_map[index].virt) {
+ case CONFIG_SYS_FSL_DRAM_BASE1:
+ final_map[index].virt = gd->bd->bi_dram[0].start;
+ final_map[index].phys = gd->bd->bi_dram[0].start;
+ final_map[index].size = gd->bd->bi_dram[0].size;
+ break;
+#ifdef CONFIG_SYS_FSL_DRAM_BASE2
+ case CONFIG_SYS_FSL_DRAM_BASE2:
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ final_map[index].virt = gd->bd->bi_dram[1].start;
+ final_map[index].phys = gd->bd->bi_dram[1].start;
+ final_map[index].size = gd->bd->bi_dram[1].size;
+#else
+ final_map[index].size = 0;
+#endif
+ break;
+#endif
+#ifdef CONFIG_SYS_FSL_DRAM_BASE3
+ case CONFIG_SYS_FSL_DRAM_BASE3:
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ final_map[index].virt = gd->bd->bi_dram[2].start;
+ final_map[index].phys = gd->bd->bi_dram[2].start;
+ final_map[index].size = gd->bd->bi_dram[2].size;
+#else
+ final_map[index].size = 0;
+#endif
+ break;
+#endif
+ default:
+ break;
+ }
+ }
+
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) {
setup_pgtables();
gd->arch.tlb_addr = tlb_addr_save;
- /* flush new MMU table */
- flush_dcache_range(gd->arch.tlb_addr,
- gd->arch.tlb_addr + gd->arch.tlb_size);
+ /* Disable cache and MMU */
+ dcache_disable(); /* TLBs are invalidated */
+ invalidate_icache_all();
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
MEMORY_ATTRIBUTES);
- /*
- * EL3 MMU is already enabled, just need to invalidate TLB to load the
- * new table. The new table is compatible with the current table, if
- * MMU somehow walks through the new table before invalidation TLB,
- * it still works. So we don't need to turn off MMU here.
- * When EL2 MMU table is created by calling this function, MMU needs
- * to be enabled.
- */
+
set_sctlr(get_sctlr() | CR_M);
}
{
phys_size_t ram_top = ram_size;
-#ifdef CONFIG_SYS_MEM_TOP_HIDE
-#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET
+ /* The start address of MC reserved memory needs to be aligned. */
ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
#endif
- return ram_top;
+ return ram_size - ram_top;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ phys_size_t ea_size, rem = 0;
+
+ /*
+ * For ARMv8 SoCs, DDR memory is split into two or three regions. The
+ * first region is 2GB space at 0x8000_0000. If the memory extends to
+ * the second region (or the third region if applicable), the secure
+ * memory and Management Complex (MC) memory should be put into the
+ * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
+ * is set to the size of first region so U-Boot doesn't relocate itself
+ * into higher address. Should DDR be configured to skip the first
+ * region, this function needs to be adjusted.
+ */
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ ea_size = CONFIG_MAX_MEM_MAPPED;
+ rem = gd->ram_size - ea_size;
+ } else {
+ ea_size = gd->ram_size;
+ }
+
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ /* Check if we have enough space for secure memory */
+ if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
+ rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ } else {
+ if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
+ ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ rem = 0; /* Presume MC requires more memory */
+ } else {
+ printf("Error: No enough space for secure memory.\n");
+ }
+ }
+#endif
+ /* Check if we have enough memory for MC */
+ if (rem < board_reserve_ram_top(rem)) {
+ /* Not enough memory in high region to reserve */
+ if (ea_size > board_reserve_ram_top(rem))
+ ea_size -= board_reserve_ram_top(rem);
+ else
+ printf("Error: No enough space for reserved memory.\n");
+ }
+
+ return ea_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ phys_size_t dp_ddr_size;
+#endif
+
+ /*
+ * gd->ram_size has the total size of DDR memory, less reserved secure
+ * memory. The DDR extends from low region to high region(s) presuming
+ * no hole is created with DDR configuration. gd->arch.secure_ram tracks
+ * the location of secure memory. gd->arch.resv_ram tracks the location
+ * of reserved memory for Management Complex (MC).
+ */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
+ gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
+ CONFIG_SYS_DDR_BLOCK2_SIZE;
+ gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
+ }
+#endif
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
+ gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ gd->arch.secure_ram = gd->bd->bi_dram[2].start +
+ gd->bd->bi_dram[2].size;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ } else
+#endif
+ {
+ if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
+ gd->bd->bi_dram[1].size -=
+ CONFIG_SYS_MEM_RESERVE_SECURE;
+ gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+ gd->bd->bi_dram[1].size;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ } else if (gd->bd->bi_dram[0].size >
+ CONFIG_SYS_MEM_RESERVE_SECURE) {
+ gd->bd->bi_dram[0].size -=
+ CONFIG_SYS_MEM_RESERVE_SECURE;
+ gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size;
+ gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+ gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+ }
+ }
+#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
+
+#ifdef CONFIG_FSL_MC_ENET
+ /* Assign memory for MC */
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bd->bi_dram[2].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[2].start +
+ gd->bd->bi_dram[2].size -
+ board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ } else
+#endif
+ {
+ if (gd->bd->bi_dram[1].size >=
+ board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[1].start +
+ gd->bd->bi_dram[1].size -
+ board_reserve_ram_top(gd->bd->bi_dram[1].size);
+ } else if (gd->bd->bi_dram[0].size >
+ board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size -
+ board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ }
+ }
+#endif /* CONFIG_FSL_MC_ENET */
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+#error "This SoC shouldn't have DP DDR"
+#endif
+ if (soc_has_dp_ddr()) {
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ CONFIG_DP_DDR_CTRL,
+ CONFIG_DP_DDR_NUM_CTRLS,
+ CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+ NULL, NULL, NULL);
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
+ }
+#endif
+}
+
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+void efi_add_known_memory(void)
+{
+ int i;
+ phys_addr_t ram_start, start;
+ phys_size_t ram_size;
+ u64 pages;
+
+ /* Add RAM */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+#error "This SoC shouldn't have DP DDR"
+#endif
+ if (i == 2)
+ continue; /* skip DP-DDR */
+#endif
+ ram_start = gd->bd->bi_dram[i].start;
+ ram_size = gd->bd->bi_dram[i].size;
+#ifdef CONFIG_RESV_RAM
+ if (gd->arch.resv_ram >= ram_start &&
+ gd->arch.resv_ram < ram_start + ram_size)
+ ram_size = gd->arch.resv_ram - ram_start;
+#endif
+ start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
+ pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
+
+ efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
+ false);
+ }
+}
+#endif
+
+/*
+ * Before DDR size is known, early MMU table have DDR mapped as device memory
+ * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
+ * needs to be set for these mappings.
+ * If a special case configures DDR with holes in the mapping, the holes need
+ * to be marked as invalid. This is not implemented in this function.
+ */
+void update_early_mmu_table(void)
+{
+ if (!gd->arch.tlb_addr)
+ return;
+
+ if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
+ mmu_change_region_attr(
+ CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE |
+ PTE_BLOCK_NS |
+ PTE_TYPE_VALID);
+ } else {
+ mmu_change_region_attr(
+ CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_DDR_BLOCK1_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE |
+ PTE_BLOCK_NS |
+ PTE_TYPE_VALID);
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
+#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
+#endif
+ if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+ CONFIG_SYS_DDR_BLOCK2_SIZE) {
+ mmu_change_region_attr(
+ CONFIG_SYS_DDR_BLOCK2_BASE,
+ CONFIG_SYS_DDR_BLOCK2_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE |
+ PTE_BLOCK_NS |
+ PTE_TYPE_VALID);
+ mmu_change_region_attr(
+ CONFIG_SYS_DDR_BLOCK3_BASE,
+ gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE -
+ CONFIG_SYS_DDR_BLOCK2_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE |
+ PTE_BLOCK_NS |
+ PTE_TYPE_VALID);
+ } else
+#endif
+ {
+ mmu_change_region_attr(
+ CONFIG_SYS_DDR_BLOCK2_BASE,
+ gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE |
+ PTE_BLOCK_NS |
+ PTE_TYPE_VALID);
+ }
+ }
+}
+
+__weak int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
+
+ return 0;
}
{
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-#ifdef CONFIG_ARCH_LS1046A
/* Disable SATA ECC */
out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-#endif
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
-#ifdef CONFIG_LS2080A
- arch_cpu_init();
-#endif
board_early_init_f();
timer_init();
#ifdef CONFIG_LS2080A
dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
+dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
--- /dev/null
+#ifndef _ST_PINCFG_H_
+#define _ST_PINCFG_H_
+
+/* Alternate functions */
+#define ALT1 1
+#define ALT2 2
+#define ALT3 3
+#define ALT4 4
+#define ALT5 5
+#define ALT6 6
+#define ALT7 7
+
+/* Output enable */
+#define OE (1 << 27)
+/* Pull Up */
+#define PU (1 << 26)
+/* Open Drain */
+#define OD (1 << 25)
+#define RT (1 << 23)
+#define INVERTCLK (1 << 22)
+#define CLKNOTDATA (1 << 21)
+#define DOUBLE_EDGE (1 << 20)
+#define CLK_A (0 << 18)
+#define CLK_B (1 << 18)
+#define CLK_C (2 << 18)
+#define CLK_D (3 << 18)
+
+/* User-frendly defines for Pin Direction */
+ /* oe = 0, pu = 0, od = 0 */
+#define IN (0)
+ /* oe = 0, pu = 1, od = 0 */
+#define IN_PU (PU)
+ /* oe = 1, pu = 0, od = 0 */
+#define OUT (OE)
+ /* oe = 1, pu = 0, od = 1 */
+#define BIDIR (OE | OD)
+ /* oe = 1, pu = 1, od = 1 */
+#define BIDIR_PU (OE | PU | OD)
+
+/* RETIME_TYPE */
+/*
+ * B Mode
+ * Bypass retime with optional delay parameter
+ */
+#define BYPASS (0)
+/*
+ * R0, R1, R0D, R1D modes
+ * single-edge data non inverted clock, retime data with clk
+ */
+#define SE_NICLK_IO (RT)
+/*
+ * RIV0, RIV1, RIV0D, RIV1D modes
+ * single-edge data inverted clock, retime data with clk
+ */
+#define SE_ICLK_IO (RT | INVERTCLK)
+/*
+ * R0E, R1E, R0ED, R1ED modes
+ * double-edge data, retime data with clk
+ */
+#define DE_IO (RT | DOUBLE_EDGE)
+/*
+ * CIV0, CIV1 modes with inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define ICLK (RT | CLKNOTDATA | INVERTCLK)
+/*
+ * CLK0, CLK1 modes with non-inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define NICLK (RT | CLKNOTDATA)
+#endif /* _ST_PINCFG_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/clock/stih407-clks.h>
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * A9 PLL.
+ */
+ clockgen-a9@92b0000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x92b0000 0xffff>;
+
+ clockgen_a9_pll: clockgen-a9-pll {
+ #clock-cells = <1>;
+ compatible = "st,stih407-clkgen-plla9";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clockgen-a9-pll-odf";
+ };
+ };
+
+ /*
+ * ARM CPU related clocks.
+ */
+ clk_m_a9: clk-m-a9@92b0000 {
+ #clock-cells = <0>;
+ compatible = "st,stih407-clkgen-a9-mux";
+ reg = <0x92b0000 0x10000>;
+
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ clk_ext2f_a9: clockgen-c0@13 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ clock-output-names = "clk-s-icn-reg-0";
+ };
+
+ clockgen-a@090ff000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x90ff000 0x1000>;
+
+ clk_s_a0_pll: clk-s-a0-pll {
+ #clock-cells = <1>;
+ compatible = "st,clkgen-pll0";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-a0-pll-ofd-0";
+ };
+
+ clk_s_a0_flexgen: clk-s-a0-flexgen {
+ compatible = "st,flexgen";
+
+ #clock-cells = <1>;
+
+ clocks = <&clk_s_a0_pll 0>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-ic-lmi0";
+ };
+ };
+
+ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-pll";
+ reg = <0x9103000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-fs0-ch0",
+ "clk-s-c0-fs0-ch1",
+ "clk-s-c0-fs0-ch2",
+ "clk-s-c0-fs0-ch3";
+ };
+
+ clk_s_c0: clockgen-c@09103000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9103000 0x1000>;
+
+ clk_s_c0_pll0: clk-s-c0-pll0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgen-pll0";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll0-odf-0";
+ };
+
+ clk_s_c0_pll1: clk-s-c0-pll1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgen-pll1";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll1-odf-0";
+ };
+
+ clk_s_c0_flexgen: clk-s-c0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_c0_pll0 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_quadfs 0>,
+ <&clk_s_c0_quadfs 1>,
+ <&clk_s_c0_quadfs 2>,
+ <&clk_s_c0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-icn-gpu",
+ "clk-fdma",
+ "clk-nand",
+ "clk-hva",
+ "clk-proc-stfe",
+ "clk-proc-tp",
+ "clk-rx-icn-dmu",
+ "clk-rx-icn-hva",
+ "clk-icn-cpu",
+ "clk-tx-icn-dmu",
+ "clk-mmc-0",
+ "clk-mmc-1",
+ "clk-jpegdec",
+ "clk-ext2fa9",
+ "clk-ic-bdisp-0",
+ "clk-ic-bdisp-1",
+ "clk-pp-dmu",
+ "clk-vid-dmu",
+ "clk-dss-lpc",
+ "clk-st231-aud-0",
+ "clk-st231-gp-1",
+ "clk-st231-dmu",
+ "clk-icn-lmi",
+ "clk-tx-icn-disp-1",
+ "clk-icn-sbc",
+ "clk-stfe-frc2",
+ "clk-eth-phy",
+ "clk-eth-ref-phyclk",
+ "clk-flash-promip",
+ "clk-main-disp",
+ "clk-aux-disp",
+ "clk-compo-dvp";
+ };
+ };
+
+ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs";
+ reg = <0x9104000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d0-fs0-ch0",
+ "clk-s-d0-fs0-ch1",
+ "clk-s-d0-fs0-ch2",
+ "clk-s-d0-fs0-ch3";
+ };
+
+ clockgen-d0@09104000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9104000 0x1000>;
+
+ clk_s_d0_flexgen: clk-s-d0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen-audio", "st,flexgen";
+
+ clocks = <&clk_s_d0_quadfs 0>,
+ <&clk_s_d0_quadfs 1>,
+ <&clk_s_d0_quadfs 2>,
+ <&clk_s_d0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-pcm-0",
+ "clk-pcm-1",
+ "clk-pcm-2",
+ "clk-spdiff";
+ };
+ };
+
+ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs";
+ reg = <0x9106000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d2-fs0-ch0",
+ "clk-s-d2-fs0-ch1",
+ "clk-s-d2-fs0-ch2",
+ "clk-s-d2-fs0-ch3";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clockgen-d2@x9106000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9106000 0x1000>;
+
+ clk_s_d2_flexgen: clk-s-d2-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen-video", "st,flexgen";
+
+ clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 2>,
+ <&clk_s_d2_quadfs 3>,
+ <&clk_sysin>,
+ <&clk_sysin>,
+ <&clk_tmdsout_hdmi>;
+
+ clock-output-names = "clk-pix-main-disp",
+ "clk-pix-pip",
+ "clk-pix-gdp1",
+ "clk-pix-gdp2",
+ "clk-pix-gdp3",
+ "clk-pix-gdp4",
+ "clk-pix-aux-disp",
+ "clk-denc",
+ "clk-pix-hddac",
+ "clk-hddac",
+ "clk-sddac",
+ "clk-pix-dvo",
+ "clk-dvo",
+ "clk-pix-hdmi",
+ "clk-tmds-hdmi",
+ "clk-ref-hdmiphy";
+ };
+ };
+
+ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs";
+ reg = <0x9107000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d3-fs0-ch0",
+ "clk-s-d3-fs0-ch1",
+ "clk-s-d3-fs0-ch2",
+ "clk-s-d3-fs0-ch3";
+ };
+
+ clockgen-d3@9107000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9107000 0x1000>;
+
+ clk_s_d3_flexgen: clk-s-d3-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d3_quadfs 0>,
+ <&clk_s_d3_quadfs 1>,
+ <&clk_s_d3_quadfs 2>,
+ <&clk_s_d3_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-stfe-frc1",
+ "clk-tsout-0",
+ "clk-tsout-1",
+ "clk-mchi",
+ "clk-vsens-compo",
+ "clk-frc1-remote",
+ "clk-lpc-0",
+ "clk-lpc-1";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih407-pinctrl.dtsi"
+#include <dt-bindings/mfd/st-lpc.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/stih407-resets.h>
+#include <dt-bindings/interrupt-controller/irq-st.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dmu_reserved: rproc@44000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x44000000 0x01000000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+
+ /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+ cpu-release-addr = <0x94100A4>;
+
+ /* kHz uV */
+ operating-points = <1500000 0
+ 1200000 0
+ 800000 0
+ 500000 0>;
+
+ clocks = <&clk_m_a9>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
+ st,syscfg = <&syscfg_core 0x8e0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+
+ /* u-boot puts hpen in SBC dmem at 0xa4 offset */
+ cpu-release-addr = <0x94100A4>;
+
+ /* kHz uV */
+ operating-points = <1500000 0
+ 1200000 0
+ 800000 0
+ 500000 0>;
+ };
+ };
+
+ intc: interrupt-controller@08761000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x08761000 0x1000>, <0x08760100 0x100>;
+ };
+
+ scu@08760000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x08760000 0x1000>;
+ };
+
+ timer@08760200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x08760200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ l2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x08762000 0x1000>;
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ arm-pmu {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pwm_regulator: pwm-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 3 8448>;
+ regulator-name = "CPU_1V0_AVS";
+ regulator-min-microvolt = <784000>;
+ regulator-max-microvolt = <1299000>;
+ regulator-always-on;
+ max-duty-cycle = <255>;
+ status = "okay";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ restart {
+ compatible = "st,stih407-restart";
+ st,syscfg = <&syscfg_sbc_reg>;
+ status = "okay";
+ };
+
+ powerdown: powerdown-controller {
+ compatible = "st,stih407-powerdown";
+ #reset-cells = <1>;
+ };
+
+ softreset: softreset-controller {
+ compatible = "st,stih407-softreset";
+ #reset-cells = <1>;
+ };
+
+ picophyreset: picophyreset-controller {
+ compatible = "st,stih407-picophyreset";
+ #reset-cells = <1>;
+ };
+
+ syscfg_sbc: sbc-syscfg@9620000 {
+ compatible = "st,stih407-sbc-syscfg", "syscon";
+ reg = <0x9620000 0x1000>;
+ };
+
+ syscfg_front: front-syscfg@9280000 {
+ compatible = "st,stih407-front-syscfg", "syscon";
+ reg = <0x9280000 0x1000>;
+ };
+
+ syscfg_rear: rear-syscfg@9290000 {
+ compatible = "st,stih407-rear-syscfg", "syscon";
+ reg = <0x9290000 0x1000>;
+ };
+
+ syscfg_flash: flash-syscfg@92a0000 {
+ compatible = "st,stih407-flash-syscfg", "syscon";
+ reg = <0x92a0000 0x1000>;
+ };
+
+ syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
+ compatible = "st,stih407-sbc-reg-syscfg", "syscon";
+ reg = <0x9600000 0x1000>;
+ };
+
+ syscfg_core: core-syscfg@92b0000 {
+ compatible = "st,stih407-core-syscfg", "syscon";
+ reg = <0x92b0000 0x1000>;
+ };
+
+ syscfg_lpm: lpm-syscfg@94b5100 {
+ compatible = "st,stih407-lpm-syscfg", "syscon";
+ reg = <0x94b5100 0x1000>;
+ };
+
+ irq-syscfg {
+ compatible = "st,stih407-irq-syscfg";
+ st,syscfg = <&syscfg_core>;
+ st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+ <ST_IRQ_SYSCFG_PMU_1>;
+ st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+ <ST_IRQ_SYSCFG_DISABLED>;
+ };
+
+ /* Display */
+ vtg_main: sti-vtg-main@8d02800 {
+ compatible = "st,vtg";
+ reg = <0x8d02800 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
+ };
+
+ vtg_aux: sti-vtg-aux@8d00200 {
+ compatible = "st,vtg";
+ reg = <0x8d00200 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
+ };
+
+ serial@9830000 {
+ compatible = "st,asc";
+ reg = <0x9830000 0x2c>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial0>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ serial@9831000 {
+ compatible = "st,asc";
+ reg = <0x9831000 0x2c>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial1>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ serial@9832000 {
+ compatible = "st,asc";
+ reg = <0x9832000 0x2c>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial2>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ /* SBC_ASC0 - UART10 */
+ sbc_serial0: serial@9530000 {
+ compatible = "st,asc";
+ reg = <0x9530000 0x2c>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial0>;
+ clocks = <&clk_sysin>;
+
+ status = "disabled";
+ };
+
+ serial@9531000 {
+ compatible = "st,asc";
+ reg = <0x9531000 0x2c>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial1>;
+ clocks = <&clk_sysin>;
+
+ status = "disabled";
+ };
+
+ i2c@9840000 {
+ compatible = "st,comms-ssc4-i2c";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x9840000 0x110>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c@9841000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9841000 0x110>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c@9842000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9842000 0x110>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c@9843000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9843000 0x110>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c@9844000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9844000 0x110>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c@9845000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9845000 0x110>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+
+ /* SSCs on SBC */
+ i2c@9540000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9540000 0x110>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c@9541000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9541000 0x110>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb2_picophy0: phy1 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0x100 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY2_RESET>;
+ reset-names = "global", "port";
+ };
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x114 0x818 0xe0 0xec>;
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew";
+
+ st,syscfg = <0x118 0x81c 0xe4 0xf0>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+ };
+
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f90000 0xff>;
+ reg-names = "pipew",
+ "usb3-up";
+
+ st,syscfg = <0x11c 0x820>;
+
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+ };
+ };
+
+ spi@9840000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9840000 0x110>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi@9841000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9841000 0x110>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ status = "disabled";
+ };
+
+ spi@9842000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9842000 0x110>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+
+ status = "disabled";
+ };
+
+ spi@9843000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9843000 0x110>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi3_default>;
+
+ status = "disabled";
+ };
+
+ spi@9844000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9844000 0x110>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi4_default>;
+
+ status = "disabled";
+ };
+
+ /* SBC SSC */
+ spi@9540000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9540000 0x110>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi10_default>;
+
+ status = "disabled";
+ };
+
+ spi@9541000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9541000 0x110>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi11_default>;
+
+ status = "disabled";
+ };
+
+ spi@9542000 {
+ compatible = "st,comms-ssc4-spi";
+ reg = <0x9542000 0x110>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi12_default>;
+
+ status = "disabled";
+ };
+
+ mmc0: sdhci@09060000 {
+ compatible = "st,sdhci-stih407", "st,sdhci";
+ status = "disabled";
+ reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
+ reg-names = "mmc", "top-mmc-delay";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
+ interrupt-names = "mmcirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0>;
+ clock-names = "mmc", "icn";
+ clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
+ bus-width = <8>;
+ };
+
+ mmc1: sdhci@09080000 {
+ compatible = "st,sdhci-stih407", "st,sdhci";
+ status = "disabled";
+ reg = <0x09080000 0x7ff>;
+ reg-names = "mmc";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
+ interrupt-names = "mmcirq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1>;
+ clock-names = "mmc", "icn";
+ clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
+ resets = <&softreset STIH407_MMC1_SOFTRESET>;
+ bus-width = <4>;
+ };
+
+ /* Watchdog and Real-Time Clock */
+ lpc@8787000 {
+ compatible = "st,stih407-lpc";
+ reg = <0x8787000 0x1000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
+ timeout-sec = <120>;
+ st,syscfg = <&syscfg_core>;
+ st,lpc-mode = <ST_LPC_MODE_WDT>;
+ };
+
+ lpc@8788000 {
+ compatible = "st,stih407-lpc";
+ reg = <0x8788000 0x1000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
+ st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
+ };
+
+ sata0: sata@9b20000 {
+ compatible = "st,ahci";
+ reg = <0x9b20000 0x1000>;
+
+ interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+ interrupt-names = "hostc";
+
+ phys = <&phy_port0 PHY_TYPE_SATA>;
+ phy-names = "ahci_phy";
+
+ resets = <&powerdown STIH407_SATA0_POWERDOWN>,
+ <&softreset STIH407_SATA0_SOFTRESET>,
+ <&softreset STIH407_SATA0_PWR_SOFTRESET>;
+ reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
+
+ clock-names = "ahci_clk";
+ clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
+
+ ports-implemented = <0x1>;
+
+ status = "disabled";
+ };
+
+ sata1: sata@9b28000 {
+ compatible = "st,ahci";
+ reg = <0x9b28000 0x1000>;
+
+ interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
+ interrupt-names = "hostc";
+
+ phys = <&phy_port1 PHY_TYPE_SATA>;
+ phy-names = "ahci_phy";
+
+ resets = <&powerdown STIH407_SATA1_POWERDOWN>,
+ <&softreset STIH407_SATA1_SOFTRESET>,
+ <&softreset STIH407_SATA1_PWR_SOFTRESET>;
+ reset-names = "pwr-dwn",
+ "sw-rst",
+ "pwr-rst";
+
+ clock-names = "ahci_clk";
+ clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
+
+ ports-implemented = <0x1>;
+
+ status = "disabled";
+ };
+
+
+ st_dwc3: dwc3@8f94000 {
+ compatible = "st,stih407-dwc3";
+ reg = <0x08f94000 0x1000>, <0x110 0x4>;
+ reg-names = "reg-glue", "syscfg-reg";
+ st,syscfg = <&syscfg_core>;
+ resets = <&powerdown STIH407_USB3_POWERDOWN>,
+ <&softreset STIH407_MIPHY2_SOFTRESET>;
+ reset-names = "powerdown", "softreset";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ ranges;
+
+ status = "disabled";
+
+ dwc3: dwc3@9900000 {
+ compatible = "snps,dwc3";
+ reg = <0x09900000 0x100000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+ dr_mode = "host";
+ phy-names = "usb2-phy", "usb3-phy";
+ phys = <&usb2_picophy0>,
+ <&phy_port2 PHY_TYPE_USB3>;
+ };
+ };
+
+ /* COMMS PWM Module */
+ pwm0: pwm@9810000 {
+ compatible = "st,sti-pwm";
+ #pwm-cells = <2>;
+ reg = <0x9810000 0x68>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ st,pwm-num-chan = <1>;
+
+ status = "disabled";
+ };
+
+ /* SBC PWM Module */
+ pwm1: pwm@9510000 {
+ compatible = "st,sti-pwm";
+ #pwm-cells = <2>;
+ reg = <0x9510000 0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1_chan0_default
+ &pinctrl_pwm1_chan1_default
+ &pinctrl_pwm1_chan2_default
+ &pinctrl_pwm1_chan3_default>;
+ clock-names = "pwm";
+ clocks = <&clk_sysin>;
+ st,pwm-num-chan = <4>;
+
+ status = "disabled";
+ };
+
+ rng10: rng@08a89000 {
+ compatible = "st,rng";
+ reg = <0x08a89000 0x1000>;
+ clocks = <&clk_sysin>;
+ status = "okay";
+ };
+
+ rng11: rng@08a8a000 {
+ compatible = "st,rng";
+ reg = <0x08a8a000 0x1000>;
+ clocks = <&clk_sysin>;
+ status = "okay";
+ };
+
+ ethernet0: dwmac@9630000 {
+ device_type = "network";
+ status = "disabled";
+ compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+ reg = <0x9630000 0x8000>, <0x80 0x4>;
+ reg-names = "stmmaceth", "sti-ethconf";
+
+ st,syscon = <&syscfg_sbc_reg 0x80>;
+ st,gmac_en;
+ resets = <&softreset STIH407_ETH1_SOFTRESET>;
+ reset-names = "stmmaceth";
+
+ interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
+ <GIC_SPI 99 IRQ_TYPE_NONE>;
+ interrupt-names = "macirq", "eth_wake_irq";
+
+ /* DMA Bus Mode */
+ snps,pbl = <8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>;
+
+ clock-names = "stmmaceth", "sti-ethclk";
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_ETH_PHY>;
+ };
+
+ cec: sti-cec@094a087c {
+ compatible = "st,stih-cec";
+ reg = <0x94a087c 0x64>;
+ clocks = <&clk_sysin>;
+ clock-names = "cec-clk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
+ interrupt-names = "cec-irq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cec0_default>;
+ resets = <&softreset STIH407_LPM_SOFTRESET>;
+ };
+
+ rng10: rng@08a89000 {
+ compatible = "st,rng";
+ reg = <0x08a89000 0x1000>;
+ clocks = <&clk_sysin>;
+ status = "okay";
+ };
+
+ rng11: rng@08a8a000 {
+ compatible = "st,rng";
+ reg = <0x08a8a000 0x1000>;
+ clocks = <&clk_sysin>;
+ status = "okay";
+ };
+
+ mailbox0: mailbox@8f00000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f00000 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
+ #mbox-cells = <2>;
+ mbox-name = "a9";
+ status = "okay";
+ };
+
+ mailbox1: mailbox@8f01000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f01000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_gp_1";
+ status = "okay";
+ };
+
+ mailbox2: mailbox@8f02000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f02000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_gp_0";
+ status = "okay";
+ };
+
+ mailbox3: mailbox@8f03000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f03000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_audio_video";
+ status = "okay";
+ };
+
+ st231_delta: st231-delta@44000000 {
+ compatible = "st,st231-rproc";
+ memory-region = <&dmu_reserved>;
+ resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x224>;
+ #mbox-cells = <1>;
+ mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
+ mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
+ };
+
+ /* fdma audio */
+ fdma0: dma-controller@8e20000 {
+ compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
+ reg = <0x8e20000 0x8000>,
+ <0x8e30000 0x3000>,
+ <0x8e37000 0x1000>,
+ <0x8e38000 0x8000>;
+ reg-names = "slimcore", "dmem", "peripherals", "imem";
+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ };
+
+ /* fdma app */
+ fdma1: dma-controller@8e40000 {
+ compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
+ reg = <0x8e40000 0x8000>,
+ <0x8e50000 0x3000>,
+ <0x8e57000 0x1000>,
+ <0x8e58000 0x8000>;
+ reg-names = "slimcore", "dmem", "peripherals", "imem";
+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
+ <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
+ <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ };
+
+ /* fdma free running */
+ fdma2: dma-controller@8e60000 {
+ compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
+ reg = <0x8e60000 0x8000>,
+ <0x8e70000 0x3000>,
+ <0x8e77000 0x1000>,
+ <0x8e78000 0x8000>;
+ reg-names = "slimcore", "dmem", "peripherals", "imem";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
+ dma-channels = <16>;
+ #dma-cells = <3>;
+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+ <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ };
+
+ sti_sasg_codec: sti-sasg-codec {
+ compatible = "st,stih407-sas-codec";
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ st,syscfg = <&syscfg_core>;
+ };
+
+ sti_uni_player0: sti-uni-player@8d80000 {
+ compatible = "st,stih407-uni-player-hdmi";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
+ assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
+ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8d80000 0x158>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 2 0 1>;
+ dma-names = "tx";
+
+ status = "disabled";
+ };
+
+ sti_uni_player1: sti-uni-player@8d81000 {
+ compatible = "st,stih407-uni-player-pcm-out";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
+ assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
+ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8d81000 0x158>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 3 0 1>;
+ dma-names = "tx";
+
+ status = "disabled";
+ };
+
+ sti_uni_player2: sti-uni-player@8d82000 {
+ compatible = "st,stih407-uni-player-dac";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
+ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8d82000 0x158>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 4 0 1>;
+ dma-names = "tx";
+
+ status = "disabled";
+ };
+
+ sti_uni_player3: sti-uni-player@8d85000 {
+ compatible = "st,stih407-uni-player-spdif";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
+ assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
+ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
+ assigned-clock-rates = <50000000>;
+ reg = <0x8d85000 0x158>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 7 0 1>;
+ dma-names = "tx";
+
+ status = "disabled";
+ };
+
+ sti_uni_reader0: sti-uni-reader@8d83000 {
+ compatible = "st,stih407-uni-reader-pcm_in";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ reg = <0x8d83000 0x158>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 5 0 1>;
+ dma-names = "rx";
+
+ status = "disabled";
+ };
+
+ sti_uni_reader1: sti-uni-reader@8d84000 {
+ compatible = "st,stih407-uni-reader-hdmi";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ reg = <0x8d84000 0x158>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 6 0 1>;
+ dma-names = "rx";
+
+ status = "disabled";
+ };
+
+ rc: rc@09518000 {
+ compatible = "st,comms-irb";
+ reg = <0x09518000 0x234>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>;
+ rx-mode = "infrared";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ir
+ &pinctrl_uhf
+ &pinctrl_tx
+ &pinctrl_tx_od>;
+ clocks = <&clk_sysin>;
+ resets = <&softreset STIH407_IRB_SOFTRESET>;
+
+ status = "disabled";
+ };
+
+ socinfo {
+ compatible = "st,stih407-socinfo";
+ st,syscfg = <&syscfg_core>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+
+ aliases {
+ /* 0-5: PIO_SBC */
+ gpio0 = &pio0;
+ gpio1 = &pio1;
+ gpio2 = &pio2;
+ gpio3 = &pio3;
+ gpio4 = &pio4;
+ gpio5 = &pio5;
+ /* 10-19: PIO_FRONT0 */
+ gpio6 = &pio10;
+ gpio7 = &pio11;
+ gpio8 = &pio12;
+ gpio9 = &pio13;
+ gpio10 = &pio14;
+ gpio11 = &pio15;
+ gpio12 = &pio16;
+ gpio13 = &pio17;
+ gpio14 = &pio18;
+ gpio15 = &pio19;
+ /* 20: PIO_FRONT1 */
+ gpio16 = &pio20;
+ /* 30-35: PIO_REAR */
+ gpio17 = &pio30;
+ gpio18 = &pio31;
+ gpio19 = &pio32;
+ gpio20 = &pio33;
+ gpio21 = &pio34;
+ gpio22 = &pio35;
+ /* 40-42: PIO_FLASH */
+ gpio23 = &pio40;
+ gpio24 = &pio41;
+ gpio25 = &pio42;
+ };
+
+ soc {
+ pin-controller-sbc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih407-sbc-pinctrl";
+ st,syscfg = <&syscfg_sbc>;
+ reg = <0x0961f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
+ interrupt-names = "irqmux";
+ ranges = <0 0x09610000 0x6000>;
+
+ pio0: gpio@09610000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x100>;
+ st,bank-name = "PIO0";
+ };
+ pio1: gpio@09611000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO1";
+ };
+ pio2: gpio@09612000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO2";
+ };
+ pio3: gpio@09613000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO3";
+ };
+ pio4: gpio@09614000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO4";
+ };
+
+ pio5: gpio@09615000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO5";
+ st,retime-pin-mask = <0x3f>;
+ };
+
+ cec0 {
+ pinctrl_cec0_default: cec0-default {
+ st,pins {
+ hdmi_cec = <&pio2 4 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ rc {
+ pinctrl_ir: ir0 {
+ st,pins {
+ ir = <&pio4 0 ALT2 IN>;
+ };
+ };
+
+ pinctrl_uhf: uhf0 {
+ st,pins {
+ ir = <&pio4 1 ALT2 IN>;
+ };
+ };
+
+ pinctrl_tx: tx0 {
+ st,pins {
+ tx = <&pio4 2 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_tx_od: tx_od0 {
+ st,pins {
+ tx_od = <&pio4 3 ALT2 OUT>;
+ };
+ };
+ };
+
+ /* SBC_ASC0 - UART10 */
+ sbc_serial0 {
+ pinctrl_sbc_serial0: sbc_serial0-0 {
+ st,pins {
+ tx = <&pio3 4 ALT1 OUT>;
+ rx = <&pio3 5 ALT1 IN>;
+ };
+ };
+ };
+ /* SBC_ASC1 - UART11 */
+ sbc_serial1 {
+ pinctrl_sbc_serial1: sbc_serial1-0 {
+ st,pins {
+ tx = <&pio2 6 ALT3 OUT>;
+ rx = <&pio2 7 ALT3 IN>;
+ };
+ };
+ };
+
+ i2c10 {
+ pinctrl_i2c10_default: i2c10-default {
+ st,pins {
+ sda = <&pio4 6 ALT1 BIDIR>;
+ scl = <&pio4 5 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ i2c11 {
+ pinctrl_i2c11_default: i2c11-default {
+ st,pins {
+ sda = <&pio5 1 ALT1 BIDIR>;
+ scl = <&pio5 0 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ keyscan {
+ pinctrl_keyscan: keyscan {
+ st,pins {
+ keyin0 = <&pio4 0 ALT6 IN>;
+ keyin1 = <&pio4 5 ALT4 IN>;
+ keyin2 = <&pio0 4 ALT2 IN>;
+ keyin3 = <&pio2 6 ALT2 IN>;
+
+ keyout0 = <&pio4 6 ALT4 OUT>;
+ keyout1 = <&pio1 7 ALT2 OUT>;
+ keyout2 = <&pio0 6 ALT2 OUT>;
+ keyout3 = <&pio2 7 ALT2 OUT>;
+ };
+ };
+ };
+
+ gmac1 {
+ /*
+ * Almost all the boards based on STiH407 SoC have an embedded
+ * switch where the mdio/mdc have been used for managing the SMI
+ * iface via I2C. For this reason these lines can be allocated
+ * by using dedicated configuration (in case of there will be a
+ * standard PHY transceiver on-board).
+ */
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+
+ txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
+ txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
+ txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
+ txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
+ txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
+ txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
+ rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
+ rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
+ rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
+ rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
+ rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
+ rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
+ clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
+ phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
+ };
+ };
+
+ pinctrl_rgmii1_mdio: rgmii1-mdio {
+ st,pins {
+ mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+ mdint = <&pio1 3 ALT1 IN BYPASS 0>;
+ };
+ };
+
+ pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
+ st,pins {
+ mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
+ col = <&pio0 7 ALT1 IN BYPASS 1000>;
+
+ mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
+ mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+ crs = <&pio1 2 ALT1 IN BYPASS 1000>;
+ mdint = <&pio1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
+ phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+
+ pinctrl_rmii1: rmii1-0 {
+ st,pins {
+ txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
+ mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+ mdint = <&pio1 3 ALT1 IN BYPASS 0>;
+ rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
+ rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
+ rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
+ rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+
+ pinctrl_rmii1_phyclk: rmii1_phyclk {
+ st,pins {
+ phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
+ };
+ };
+
+ pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
+ st,pins {
+ phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
+ };
+ };
+ };
+
+ pwm1 {
+ pinctrl_pwm1_chan0_default: pwm1-0-default {
+ st,pins {
+ pwm-out = <&pio3 0 ALT1 OUT>;
+ pwm-capturein = <&pio3 2 ALT1 IN>;
+ };
+ };
+ pinctrl_pwm1_chan1_default: pwm1-1-default {
+ st,pins {
+ pwm-capturein = <&pio4 3 ALT1 IN>;
+ pwm-out = <&pio4 4 ALT1 OUT>;
+ };
+ };
+ pinctrl_pwm1_chan2_default: pwm1-2-default {
+ st,pins {
+ pwm-out = <&pio4 6 ALT3 OUT>;
+ };
+ };
+ pinctrl_pwm1_chan3_default: pwm1-3-default {
+ st,pins {
+ pwm-out = <&pio4 7 ALT3 OUT>;
+ };
+ };
+ };
+
+ spi10 {
+ pinctrl_spi10_default: spi10-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio4 6 ALT1 OUT>;
+ mrst = <&pio4 7 ALT1 IN>;
+ scl = <&pio4 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio4 6 ALT1 BIDIR_PU>;
+ scl = <&pio4 5 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi11 {
+ pinctrl_spi11_default: spi11-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 1 ALT2 OUT>;
+ mrst = <&pio3 0 ALT2 IN>;
+ scl = <&pio3 2 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 1 ALT2 BIDIR_PU>;
+ scl = <&pio3 2 ALT2 OUT>;
+ };
+ };
+ };
+
+ spi12 {
+ pinctrl_spi12_default: spi12-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 6 ALT2 OUT>;
+ mrst = <&pio3 4 ALT2 IN>;
+ scl = <&pio3 7 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 6 ALT2 BIDIR_PU>;
+ scl = <&pio3 7 ALT2 OUT>;
+ };
+ };
+ };
+ };
+
+ pin-controller-front0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih407-front-pinctrl";
+ st,syscfg = <&syscfg_front>;
+ reg = <0x0920f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
+ interrupt-names = "irqmux";
+ ranges = <0 0x09200000 0x10000>;
+
+ pio10: pio@09200000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x100>;
+ st,bank-name = "PIO10";
+ };
+ pio11: pio@09201000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO11";
+ };
+ pio12: pio@09202000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO12";
+ };
+ pio13: pio@09203000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO13";
+ };
+ pio14: pio@09204000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO14";
+ };
+ pio15: pio@09205000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO15";
+ };
+ pio16: pio@09206000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x100>;
+ st,bank-name = "PIO16";
+ };
+ pio17: pio@09207000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x100>;
+ st,bank-name = "PIO17";
+ };
+ pio18: pio@09208000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x100>;
+ st,bank-name = "PIO18";
+ };
+ pio19: pio@09209000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x100>;
+ st,bank-name = "PIO19";
+ };
+
+ /* Comms */
+ serial0 {
+ pinctrl_serial0: serial0-0 {
+ st,pins {
+ tx = <&pio17 0 ALT1 OUT>;
+ rx = <&pio17 1 ALT1 IN>;
+ };
+ };
+ pinctrl_serial0_rts: serial0_rts {
+ st,pins {
+ rts = <&pio17 3 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_serial0_cts: serial0_cts {
+ st,pins {
+ cts = <&pio17 2 ALT1 IN>;
+ };
+ };
+ };
+
+ serial1 {
+ pinctrl_serial1: serial1-0 {
+ st,pins {
+ tx = <&pio16 0 ALT1 OUT>;
+ rx = <&pio16 1 ALT1 IN>;
+ };
+ };
+ };
+
+ serial2 {
+ pinctrl_serial2: serial2-0 {
+ st,pins {
+ tx = <&pio15 0 ALT1 OUT>;
+ rx = <&pio15 1 ALT1 IN>;
+ };
+ };
+ };
+
+ mmc1 {
+ pinctrl_sd1: sd1-0 {
+ st,pins {
+ sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
+ sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
+ sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
+ sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
+ sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
+ sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
+ sd_led = <&pio16 6 ALT6 OUT>;
+ sd_pwren = <&pio16 7 ALT6 OUT>;
+ sd_cd = <&pio19 0 ALT6 IN>;
+ sd_wp = <&pio19 1 ALT6 IN>;
+ };
+ };
+ };
+
+
+ i2c0 {
+ pinctrl_i2c0_default: i2c0-default {
+ st,pins {
+ sda = <&pio10 6 ALT2 BIDIR>;
+ scl = <&pio10 5 ALT2 BIDIR>;
+ };
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_default: i2c1-default {
+ st,pins {
+ sda = <&pio11 1 ALT2 BIDIR>;
+ scl = <&pio11 0 ALT2 BIDIR>;
+ };
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_default: i2c2-default {
+ st,pins {
+ sda = <&pio15 6 ALT2 BIDIR>;
+ scl = <&pio15 5 ALT2 BIDIR>;
+ };
+ };
+
+ pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
+ st,pins {
+ sda = <&pio12 6 ALT2 BIDIR>;
+ scl = <&pio12 5 ALT2 BIDIR>;
+ };
+ };
+ };
+
+ i2c3 {
+ pinctrl_i2c3_default: i2c3-alt1-0 {
+ st,pins {
+ sda = <&pio18 6 ALT1 BIDIR>;
+ scl = <&pio18 5 ALT1 BIDIR>;
+ };
+ };
+ pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
+ st,pins {
+ sda = <&pio17 7 ALT1 BIDIR>;
+ scl = <&pio17 6 ALT1 BIDIR>;
+ };
+ };
+ pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
+ st,pins {
+ sda = <&pio13 6 ALT3 BIDIR>;
+ scl = <&pio13 5 ALT3 BIDIR>;
+ };
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0_default: spi0-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio10 6 ALT2 OUT>;
+ mrst = <&pio10 7 ALT2 IN>;
+ scl = <&pio10 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio10 6 ALT2 BIDIR_PU>;
+ scl = <&pio10 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio19 7 ALT1 OUT>;
+ mrst = <&pio19 5 ALT1 IN>;
+ scl = <&pio19 6 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio19 7 ALT1 BIDIR_PU>;
+ scl = <&pio19 6 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1_default: spi1-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio11 1 ALT2 OUT>;
+ mrst = <&pio11 2 ALT2 IN>;
+ scl = <&pio11 0 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio11 1 ALT2 BIDIR_PU>;
+ scl = <&pio11 0 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 3 ALT1 OUT>;
+ mrst = <&pio14 4 ALT1 IN>;
+ scl = <&pio14 2 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 3 ALT1 BIDIR_PU>;
+ scl = <&pio14 2 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi2 {
+ pinctrl_spi2_default: spi2-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio12 6 ALT2 OUT>;
+ mrst = <&pio12 7 ALT2 IN>;
+ scl = <&pio12 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio12 6 ALT2 BIDIR_PU>;
+ scl = <&pio12 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 6 ALT1 OUT>;
+ mrst = <&pio14 7 ALT1 IN>;
+ scl = <&pio14 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 6 ALT1 BIDIR_PU>;
+ scl = <&pio14 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
+ st,pins {
+ mtsr = <&pio15 6 ALT2 OUT>;
+ mrst = <&pio15 7 ALT2 IN>;
+ scl = <&pio15 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
+ st,pins {
+ mtsr = <&pio15 6 ALT2 BIDIR_PU>;
+ scl = <&pio15 5 ALT2 OUT>;
+ };
+ };
+ };
+
+ spi3 {
+ pinctrl_spi3_default: spi3-4w-alt3-0 {
+ st,pins {
+ mtsr = <&pio13 6 ALT3 OUT>;
+ mrst = <&pio13 7 ALT3 IN>;
+ scl = <&pio13 5 ALT3 OUT>;
+ };
+ };
+
+ pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
+ st,pins {
+ mtsr = <&pio13 6 ALT3 BIDIR_PU>;
+ scl = <&pio13 5 ALT3 OUT>;
+ };
+ };
+
+ pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio17 7 ALT1 OUT>;
+ mrst = <&pio17 5 ALT1 IN>;
+ scl = <&pio17 6 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio17 7 ALT1 BIDIR_PU>;
+ scl = <&pio17 6 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
+ st,pins {
+ mtsr = <&pio18 6 ALT1 OUT>;
+ mrst = <&pio18 7 ALT1 IN>;
+ scl = <&pio18 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
+ st,pins {
+ mtsr = <&pio18 6 ALT1 BIDIR_PU>;
+ scl = <&pio18 5 ALT1 OUT>;
+ };
+ };
+ };
+
+ tsin0 {
+ pinctrl_tsin0_parallel: tsin0_parallel {
+ st,pins {
+ DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ pinctrl_tsin0_serial: tsin0_serial {
+ st,pins {
+ DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsin1 {
+ pinctrl_tsin1_parallel: tsin1_parallel {
+ st,pins {
+ DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ pinctrl_tsin1_serial: tsin1_serial {
+ st,pins {
+ DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsin2 {
+ pinctrl_tsin2_parallel: tsin2_parallel {
+ st,pins {
+ DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
+ DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
+ DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
+ DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
+ DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ pinctrl_tsin2_serial: tsin2_serial {
+ st,pins {
+ DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsin3 {
+ pinctrl_tsin3_serial: tsin3_serial {
+ st,pins {
+ DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsin4 {
+ pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
+ st,pins {
+ DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
+ ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
+ PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsin5 {
+ pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
+ st,pins {
+ DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
+ st,pins {
+ DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsout0 {
+ pinctrl_tsout0_parallel: tsout0_parallel {
+ st,pins {
+ DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
+ VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ pinctrl_tsout0_serial: tsout0_serial {
+ st,pins {
+ DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
+ VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ tsout1 {
+ pinctrl_tsout1_serial: tsout1_serial {
+ st,pins {
+ DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
+ VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ mtsin0 {
+ pinctrl_mtsin0_parallel: mtsin0_parallel {
+ st,pins {
+ DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ systrace {
+ pinctrl_systrace_default: systrace-default {
+ st,pins {
+ trc_data0 = <&pio11 3 ALT5 OUT>;
+ trc_data1 = <&pio11 4 ALT5 OUT>;
+ trc_data2 = <&pio11 5 ALT5 OUT>;
+ trc_data3 = <&pio11 6 ALT5 OUT>;
+ trc_clk = <&pio11 7 ALT5 OUT>;
+ };
+ };
+ };
+ };
+
+ pin-controller-front1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih407-front-pinctrl";
+ st,syscfg = <&syscfg_front>;
+ reg = <0x0921f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
+ interrupt-names = "irqmux";
+ ranges = <0 0x09210000 0x10000>;
+
+ pio20: pio@09210000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x100>;
+ st,bank-name = "PIO20";
+ };
+
+ tsin4 {
+ pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
+ st,pins {
+ DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
+ VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+ };
+
+ pin-controller-rear {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih407-rear-pinctrl";
+ st,syscfg = <&syscfg_rear>;
+ reg = <0x0922f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
+ interrupt-names = "irqmux";
+ ranges = <0 0x09220000 0x6000>;
+
+ pio30: gpio@09220000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x100>;
+ st,bank-name = "PIO30";
+ };
+ pio31: gpio@09221000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO31";
+ };
+ pio32: gpio@09222000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO32";
+ };
+ pio33: gpio@09223000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x100>;
+ st,bank-name = "PIO33";
+ };
+ pio34: gpio@09224000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x100>;
+ st,bank-name = "PIO34";
+ };
+ pio35: gpio@09225000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x100>;
+ st,bank-name = "PIO35";
+ st,retime-pin-mask = <0x7f>;
+ };
+
+ dvo {
+ pinctrl_dvo: dvo {
+ st,pins {
+ hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>;
+ d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
+ };
+ };
+ };
+
+ i2c4 {
+ pinctrl_i2c4_default: i2c4-default {
+ st,pins {
+ sda = <&pio30 1 ALT1 BIDIR>;
+ scl = <&pio30 0 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ i2c5 {
+ pinctrl_i2c5_default: i2c5-default {
+ st,pins {
+ sda = <&pio34 4 ALT1 BIDIR>;
+ scl = <&pio34 3 ALT1 BIDIR>;
+ };
+ };
+ };
+
+ usb3 {
+ pinctrl_usb3: usb3-2 {
+ st,pins {
+ usb-oc-detect = <&pio35 4 ALT1 IN>;
+ usb-pwr-enable = <&pio35 5 ALT1 OUT>;
+ usb-vbus-valid = <&pio35 6 ALT1 IN>;
+ };
+ };
+ };
+
+ pwm0 {
+ pinctrl_pwm0_chan0_default: pwm0-0-default {
+ st,pins {
+ pwm-capturein = <&pio31 0 ALT1 IN>;
+ pwm-out = <&pio31 1 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi4 {
+ pinctrl_spi4_default: spi4-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio30 1 ALT1 OUT>;
+ mrst = <&pio30 2 ALT1 IN>;
+ scl = <&pio30 0 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio30 1 ALT1 BIDIR_PU>;
+ scl = <&pio30 0 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
+ st,pins {
+ mtsr = <&pio34 1 ALT3 OUT>;
+ mrst = <&pio34 2 ALT3 IN>;
+ scl = <&pio34 0 ALT3 OUT>;
+ };
+ };
+
+ pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
+ st,pins {
+ mtsr = <&pio34 1 ALT3 BIDIR_PU>;
+ scl = <&pio34 0 ALT3 OUT>;
+ };
+ };
+ };
+
+ i2s_out {
+ pinctrl_i2s_8ch_out: i2s_8ch_out{
+ st,pins {
+ mclk = <&pio33 5 ALT1 OUT>;
+ lrclk = <&pio33 7 ALT1 OUT>;
+ sclk = <&pio33 6 ALT1 OUT>;
+ data0 = <&pio33 4 ALT1 OUT>;
+ data1 = <&pio34 0 ALT1 OUT>;
+ data2 = <&pio34 1 ALT1 OUT>;
+ data3 = <&pio34 2 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_i2s_2ch_out: i2s_2ch_out{
+ st,pins {
+ mclk = <&pio33 5 ALT1 OUT>;
+ lrclk = <&pio33 7 ALT1 OUT>;
+ sclk = <&pio33 6 ALT1 OUT>;
+ data0 = <&pio33 4 ALT1 OUT>;
+ };
+ };
+ };
+
+ i2s_in {
+ pinctrl_i2s_8ch_in: i2s_8ch_in{
+ st,pins {
+ mclk = <&pio32 5 ALT1 IN>;
+ lrclk = <&pio32 7 ALT1 IN>;
+ sclk = <&pio32 6 ALT1 IN>;
+ data0 = <&pio32 4 ALT1 IN>;
+ data1 = <&pio33 0 ALT1 IN>;
+ data2 = <&pio33 1 ALT1 IN>;
+ data3 = <&pio33 2 ALT1 IN>;
+ data4 = <&pio33 3 ALT1 IN>;
+ };
+ };
+
+ pinctrl_i2s_2ch_in: i2s_2ch_in{
+ st,pins {
+ mclk = <&pio32 5 ALT1 IN>;
+ lrclk = <&pio32 7 ALT1 IN>;
+ sclk = <&pio32 6 ALT1 IN>;
+ data0 = <&pio32 4 ALT1 IN>;
+ };
+ };
+ };
+
+ spdif_out {
+ pinctrl_spdif_out: spdif_out{
+ st,pins {
+ spdif_out = <&pio34 7 ALT1 OUT>;
+ };
+ };
+ };
+
+ serial3 {
+ pinctrl_serial3: serial3-0 {
+ st,pins {
+ tx = <&pio31 3 ALT1 OUT>;
+ rx = <&pio31 4 ALT1 IN>;
+ };
+ };
+ };
+ };
+
+ pin-controller-flash {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih407-flash-pinctrl";
+ st,syscfg = <&syscfg_flash>;
+ reg = <0x0923f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
+ interrupts-names = "irqmux";
+ ranges = <0 0x09230000 0x3000>;
+
+ pio40: gpio@09230000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x100>;
+ st,bank-name = "PIO40";
+ };
+ pio41: gpio@09231000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x100>;
+ st,bank-name = "PIO41";
+ };
+ pio42: gpio@09232000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x100>;
+ st,bank-name = "PIO42";
+ };
+
+ mmc0 {
+ pinctrl_mmc0: mmc0-0 {
+ st,pins {
+ emmc_clk = <&pio40 6 ALT1 BIDIR>;
+ emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
+ emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
+ emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
+ emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
+ emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
+ emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
+ emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
+ emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
+ emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
+ };
+ };
+ pinctrl_sd0: sd0-0 {
+ st,pins {
+ sd_clk = <&pio40 6 ALT1 BIDIR>;
+ sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
+ sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
+ sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
+ sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
+ sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
+ sd_led = <&pio42 0 ALT2 OUT>;
+ sd_pwren = <&pio42 2 ALT2 OUT>;
+ sd_vsel = <&pio42 3 ALT2 OUT>;
+ sd_cd = <&pio42 4 ALT2 IN>;
+ sd_wp = <&pio42 5 ALT2 IN>;
+ };
+ };
+ };
+
+ fsm {
+ pinctrl_fsm: fsm {
+ st,pins {
+ spi-fsm-clk = <&pio40 1 ALT1 OUT>;
+ spi-fsm-cs = <&pio40 0 ALT1 OUT>;
+ spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
+ spi-fsm-miso = <&pio40 3 ALT1 IN>;
+ spi-fsm-hol = <&pio40 5 ALT1 OUT>;
+ spi-fsm-wp = <&pio40 4 ALT1 OUT>;
+ };
+ };
+ };
+
+ nand {
+ pinctrl_nand: nand {
+ st,pins {
+ nand_cs1 = <&pio40 6 ALT3 OUT>;
+ nand_cs0 = <&pio40 7 ALT3 OUT>;
+ nand_d0 = <&pio41 0 ALT3 BIDIR>;
+ nand_d1 = <&pio41 1 ALT3 BIDIR>;
+ nand_d2 = <&pio41 2 ALT3 BIDIR>;
+ nand_d3 = <&pio41 3 ALT3 BIDIR>;
+ nand_d4 = <&pio41 4 ALT3 BIDIR>;
+ nand_d5 = <&pio41 5 ALT3 BIDIR>;
+ nand_d6 = <&pio41 6 ALT3 BIDIR>;
+ nand_d7 = <&pio41 7 ALT3 BIDIR>;
+ nand_we = <&pio42 0 ALT3 OUT>;
+ nand_dqs = <&pio42 1 ALT3 OUT>;
+ nand_ale = <&pio42 2 ALT3 OUT>;
+ nand_cle = <&pio42 3 ALT3 OUT>;
+ nand_rnb = <&pio42 4 ALT3 IN>;
+ nand_oe = <&pio42 5 ALT3 OUT>;
+ };
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 STMicroelectronics (R&D) Limited.
+ * Author: Patrice Chotard <patrice.chotard@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih410.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "STiH410 B2260";
+ compatible = "st,stih410-b2260", "st,stih410";
+
+ chosen {
+ bootargs = "console=ttyAS1,115200";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ aliases {
+ ttyAS1 = &uart1;
+ ethernet0 = ðernet0;
+ };
+
+ soc {
+
+ leds {
+ compatible = "gpio-leds";
+ user_green_1 {
+ label = "User_green_1";
+ gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ user_green_2 {
+ label = "User_green_2";
+ gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ user_green_3 {
+ label = "User_green_3";
+ gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ user_green_4 {
+ label = "User_green_4";
+ gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ wifi_yellow {
+ label = "Wifi_yellow";
+ gpios = <&pio4 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "wifi-activity";
+ default-state = "off";
+ };
+
+ bt_blue {
+ label = "Bluetooth_blue";
+ gpios = <&pio3 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
+
+ /* Low speed expansion connector */
+ uart0: serial@9830000 {
+ label = "LS-UART0";
+ status = "okay";
+ };
+
+ /* Low speed expansion connector */
+ uart1: serial@9831000 {
+ label = "LS-UART1";
+ status = "okay";
+ };
+
+ /* Low speed expansion connector */
+ spi0: spi@9844000 {
+ label = "LS-SPI0";
+ cs-gpios = <&pio30 3 0>;
+ status = "okay";
+ };
+
+ /* Low speed expansion connector */
+ i2c0: i2c@9840000 {
+ label = "LS-I2C0";
+ status = "okay";
+ };
+
+ /* Low speed expansion connector */
+ i2c1: i2c@9841000 {
+ label = "LS-I2C1";
+ status = "okay";
+ };
+
+ /* high speed expansion connector */
+ i2c2: i2c@9842000 {
+ label = "HS-I2C2";
+ pinctrl-0 = <&pinctrl_i2c2_alt2_1>;
+ status = "okay";
+ };
+
+ /* high speed expansion connector */
+ i2c3: i2c@9843000 {
+ label = "HS-I2C3";
+ pinctrl-0 = <&pinctrl_i2c3_alt3_0>;
+ status = "okay";
+ };
+
+ mmc0: sdhci@09060000 {
+ pinctrl-0 = <&pinctrl_sd0>;
+ bus-width = <4>;
+ status = "okay";
+ };
+
+ /* high speed expansion connector */
+ mmc1: sdhci@09080000 {
+ status = "okay";
+ };
+
+ pwm0: pwm@9810000 {
+ status = "okay";
+ };
+
+ pwm1: pwm@9510000 {
+ status = "okay";
+ };
+
+ usb2_picophy1: phy2 {
+ status = "okay";
+ };
+
+ usb2_picophy2: phy3 {
+ status = "okay";
+ };
+
+ ohci0: usb@9a03c00 {
+ status = "okay";
+ };
+
+ ehci0: usb@9a03e00 {
+ status = "okay";
+ };
+
+ ohci1: usb@9a83c00 {
+ status = "okay";
+ };
+
+ ehci1: usb@9a83e00 {
+ status = "okay";
+ };
+
+ st_dwc3: dwc3@8f94000 {
+ status = "okay";
+ };
+
+ ethernet0: dwmac@9630000 {
+ phy-mode = "rgmii";
+ pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
+
+ snps,phy-bus-name = "stmmac";
+ snps,phy-bus-id = <0>;
+ snps,phy-addr = <0>;
+ snps,reset-gpio = <&pio0 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+
+ status = "okay";
+ };
+
+ sti_uni_player0: sti-uni-player@8d80000 {
+ status = "okay";
+ };
+
+ /* SSC11 to HDMI */
+ hdmiddc: i2c@9541000 {
+ /* HDMI V1.3a supports Standard mode only */
+ clock-frequency = <100000>;
+ st,i2c-min-scl-pulse-width-us = <0>;
+ st,i2c-min-sda-pulse-width-us = <1>;
+ status = "okay";
+ };
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
+
+ sata1: sata@9b28000 {
+ status = "okay";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "STI-B2260";
+ status = "okay";
+
+ simple-audio-card,dai-link@0 {
+ /* DAC */
+ format = "i2s";
+ mclk-fs = <128>;
+ cpu {
+ sound-dai = <&sti_uni_player0>;
+ };
+
+ codec {
+ sound-dai = <&sti_hdmi>;
+ };
+ };
+ };
+
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/clock/stih410-clks.h>
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ compatible = "st,stih410-clk", "simple-bus";
+
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * A9 PLL.
+ */
+ clockgen-a9@92b0000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x92b0000 0xffff>;
+
+ clockgen_a9_pll: clockgen-a9-pll {
+ #clock-cells = <1>;
+ compatible = "st,stih407-clkgen-plla9";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clockgen-a9-pll-odf";
+ };
+ };
+
+ /*
+ * ARM CPU related clocks.
+ */
+ clk_m_a9: clk-m-a9@92b0000 {
+ #clock-cells = <0>;
+ compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+ reg = <0x92b0000 0x10000>;
+
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ clk_ext2f_a9: clockgen-c0@13 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ clock-output-names = "clk-s-icn-reg-0";
+ };
+
+ clockgen-a@090ff000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x90ff000 0x1000>;
+
+ clk_s_a0_pll: clk-s-a0-pll {
+ #clock-cells = <1>;
+ compatible = "st,clkgen-pll0";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-a0-pll-ofd-0";
+ clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
+ };
+
+ clk_s_a0_flexgen: clk-s-a0-flexgen {
+ compatible = "st,flexgen";
+
+ #clock-cells = <1>;
+
+ clocks = <&clk_s_a0_pll 0>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-ic-lmi0",
+ "clk-ic-lmi1";
+ clock-critical = <CLK_IC_LMI0>;
+ };
+ };
+
+ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-pll";
+ reg = <0x9103000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-fs0-ch0",
+ "clk-s-c0-fs0-ch1",
+ "clk-s-c0-fs0-ch2",
+ "clk-s-c0-fs0-ch3";
+ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
+ };
+
+ clk_s_c0: clockgen-c@09103000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9103000 0x1000>;
+
+ clk_s_c0_pll0: clk-s-c0-pll0 {
+ #clock-cells = <1>;
+ compatible = "st,clkgen-pll0";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll0-odf-0";
+ clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
+ };
+
+ clk_s_c0_pll1: clk-s-c0-pll1 {
+ #clock-cells = <1>;
+ compatible = "st,clkgen-pll1";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll1-odf-0";
+ };
+
+ clk_s_c0_flexgen: clk-s-c0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_c0_pll0 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_quadfs 0>,
+ <&clk_s_c0_quadfs 1>,
+ <&clk_s_c0_quadfs 2>,
+ <&clk_s_c0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-icn-gpu",
+ "clk-fdma",
+ "clk-nand",
+ "clk-hva",
+ "clk-proc-stfe",
+ "clk-proc-tp",
+ "clk-rx-icn-dmu",
+ "clk-rx-icn-hva",
+ "clk-icn-cpu",
+ "clk-tx-icn-dmu",
+ "clk-mmc-0",
+ "clk-mmc-1",
+ "clk-jpegdec",
+ "clk-ext2fa9",
+ "clk-ic-bdisp-0",
+ "clk-ic-bdisp-1",
+ "clk-pp-dmu",
+ "clk-vid-dmu",
+ "clk-dss-lpc",
+ "clk-st231-aud-0",
+ "clk-st231-gp-1",
+ "clk-st231-dmu",
+ "clk-icn-lmi",
+ "clk-tx-icn-disp-1",
+ "clk-icn-sbc",
+ "clk-stfe-frc2",
+ "clk-eth-phy",
+ "clk-eth-ref-phyclk",
+ "clk-flash-promip",
+ "clk-main-disp",
+ "clk-aux-disp",
+ "clk-compo-dvp",
+ "clk-tx-icn-hades",
+ "clk-rx-icn-hades",
+ "clk-icn-reg-16",
+ "clk-pp-hades",
+ "clk-clust-hades",
+ "clk-hwpe-hades",
+ "clk-fc-hades";
+ clock-critical = <CLK_ICN_CPU>,
+ <CLK_TX_ICN_DMU>,
+ <CLK_EXT2F_A9>,
+ <CLK_ICN_LMI>,
+ <CLK_ICN_SBC>;
+ };
+ };
+
+ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs";
+ reg = <0x9104000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d0-fs0-ch0",
+ "clk-s-d0-fs0-ch1",
+ "clk-s-d0-fs0-ch2",
+ "clk-s-d0-fs0-ch3";
+ };
+
+ clockgen-d0@09104000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9104000 0x1000>;
+
+ clk_s_d0_flexgen: clk-s-d0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen-audio", "st,flexgen";
+
+ clocks = <&clk_s_d0_quadfs 0>,
+ <&clk_s_d0_quadfs 1>,
+ <&clk_s_d0_quadfs 2>,
+ <&clk_s_d0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-pcm-0",
+ "clk-pcm-1",
+ "clk-pcm-2",
+ "clk-spdiff",
+ "clk-pcmr10-master",
+ "clk-usb2-phy";
+ };
+ };
+
+ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs";
+ reg = <0x9106000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d2-fs0-ch0",
+ "clk-s-d2-fs0-ch1",
+ "clk-s-d2-fs0-ch2",
+ "clk-s-d2-fs0-ch3";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clockgen-d2@x9106000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9106000 0x1000>;
+
+ clk_s_d2_flexgen: clk-s-d2-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen-video", "st,flexgen";
+
+ clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 2>,
+ <&clk_s_d2_quadfs 3>,
+ <&clk_sysin>,
+ <&clk_sysin>,
+ <&clk_tmdsout_hdmi>;
+
+ clock-output-names = "clk-pix-main-disp",
+ "clk-pix-pip",
+ "clk-pix-gdp1",
+ "clk-pix-gdp2",
+ "clk-pix-gdp3",
+ "clk-pix-gdp4",
+ "clk-pix-aux-disp",
+ "clk-denc",
+ "clk-pix-hddac",
+ "clk-hddac",
+ "clk-sddac",
+ "clk-pix-dvo",
+ "clk-dvo",
+ "clk-pix-hdmi",
+ "clk-tmds-hdmi",
+ "clk-ref-hdmiphy";
+ };
+ };
+
+ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+ #clock-cells = <1>;
+ compatible = "st,quadfs";
+ reg = <0x9107000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d3-fs0-ch0",
+ "clk-s-d3-fs0-ch1",
+ "clk-s-d3-fs0-ch2",
+ "clk-s-d3-fs0-ch3";
+ };
+
+ clockgen-d3@9107000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9107000 0x1000>;
+
+ clk_s_d3_flexgen: clk-s-d3-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d3_quadfs 0>,
+ <&clk_s_d3_quadfs 1>,
+ <&clk_s_d3_quadfs 2>,
+ <&clk_s_d3_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-stfe-frc1",
+ "clk-tsout-0",
+ "clk-tsout-1",
+ "clk-mchi",
+ "clk-vsens-compo",
+ "clk-frc1-remote",
+ "clk-lpc-0",
+ "clk-lpc-1";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+ soc {
+ pin-controller-rear {
+
+ usb0 {
+ pinctrl_usb0: usb2-0 {
+ st,pins {
+ usb-oc-detect = <&pio35 0 ALT1 IN>;
+ usb-pwr-enable = <&pio35 1 ALT1 OUT>;
+ };
+ };
+ };
+
+ usb1 {
+ pinctrl_usb1: usb2-1 {
+ st,pins {
+ usb-oc-detect = <&pio35 2 ALT1 IN>;
+ usb-pwr-enable = <&pio35 3 ALT1 OUT>;
+ };
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih410-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stih410-pinctrl.dtsi"
+/ {
+ aliases {
+ bdisp0 = &bdisp0;
+ };
+
+ cpus {
+ cpu@0 {
+ st,syscfg = <&syscfg_core 0x8e0>;
+ st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
+ clocks = <&clk_m_a9>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ cpu@1 {
+ clocks = <&clk_m_a9>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@1500000000 {
+ opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
+ opp-hz = /bits/ 64 <1500000000>;
+ clock-latency-ns = <10000000>;
+ opp-suspend;
+ };
+ opp@1200000000 {
+ opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
+ opp-hz = /bits/ 64 <1200000000>;
+ clock-latency-ns = <10000000>;
+ };
+ opp@800000000 {
+ opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
+ opp-hz = /bits/ 64 <800000000>;
+ clock-latency-ns = <10000000>;
+ };
+ opp@400000000 {
+ opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
+ opp-hz = /bits/ 64 <400000000>;
+ clock-latency-ns = <10000000>;
+ };
+ };
+
+ soc {
+ syscfg_opp: @08a6583c {
+ compatible = "syscon";
+ reg = <0x08a6583c 0x8>;
+ };
+
+ usb2_picophy1: phy2 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0xf8 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY0_RESET>;
+ reset-names = "global", "port";
+
+ status = "disabled";
+ };
+
+ usb2_picophy2: phy3 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_core 0xfc 0xf4>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY1_RESET>;
+ reset-names = "global", "port";
+
+ status = "disabled";
+ };
+
+ ohci0: usb@9a03c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0x9a03c00 0x100>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ phys = <&usb2_picophy1>;
+ phy-names = "usb";
+
+ status = "disabled";
+ };
+
+ ehci0: usb@9a03e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0x9a03e00 0x100>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ phys = <&usb2_picophy1>;
+ phy-names = "usb";
+
+ status = "disabled";
+ };
+
+ ohci1: usb@9a83c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0x9a83c00 0x100>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ phys = <&usb2_picophy2>;
+ phy-names = "usb";
+
+ status = "disabled";
+ };
+
+ ehci1: usb@9a83e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0x9a83e00 0x100>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
+ <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ phys = <&usb2_picophy2>;
+ phy-names = "usb";
+
+ status = "disabled";
+ };
+
+ sti-display-subsystem {
+ compatible = "st,sti-display-subsystem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ assigned-clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>;
+
+ assigned-clock-parents = <0>,
+ <0>,
+ <0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>;
+
+ assigned-clock-rates = <297000000>,
+ <297000000>,
+ <0>,
+ <400000000>,
+ <400000000>;
+
+ ranges;
+
+ sti-compositor@9d11000 {
+ compatible = "st,stih407-compositor";
+ reg = <0x9d11000 0x1000>;
+
+ clock-names = "compo_main",
+ "compo_aux",
+ "pix_main",
+ "pix_aux",
+ "pix_gdp1",
+ "pix_gdp2",
+ "pix_gdp3",
+ "pix_gdp4",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP1>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP2>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP3>,
+ <&clk_s_d2_flexgen CLK_PIX_GDP4>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
+
+ reset-names = "compo-main", "compo-aux";
+ resets = <&softreset STIH407_COMPO_SOFTRESET>,
+ <&softreset STIH407_COMPO_SOFTRESET>;
+ st,vtg = <&vtg_main>, <&vtg_aux>;
+ };
+
+ sti-tvout@8d08000 {
+ compatible = "st,stih407-tvout";
+ reg = <0x8d08000 0x1000>;
+ reg-names = "tvout-reg";
+ reset-names = "tvout";
+ resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
+ <&clk_s_d2_flexgen CLK_HDDAC>;
+
+ assigned-clock-parents = <&clk_s_d2_quadfs 0>,
+ <&clk_tmdsout_hdmi>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d0_quadfs 0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 0>;
+ };
+
+ sti_hdmi: sti-hdmi@8d04000 {
+ compatible = "st,stih407-hdmi";
+ #sound-dai-cells = <0>;
+ reg = <0x8d04000 0x1000>;
+ reg-names = "hdmi-reg";
+ interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
+ interrupt-names = "irq";
+ clock-names = "pix",
+ "tmds",
+ "phy",
+ "audio",
+ "main_parent",
+ "aux_parent";
+
+ clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
+ <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
+ <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
+ <&clk_s_d0_flexgen CLK_PCM_0>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
+
+ hdmi,hpd-gpio = <&pio5 3>;
+ reset-names = "hdmi";
+ resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
+ ddc = <&hdmiddc>;
+ };
+
+ sti-hda@8d02000 {
+ compatible = "st,stih407-hda";
+ status = "disabled";
+ reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
+ reg-names = "hda-reg", "video-dacs-ctrl";
+ clock-names = "pix",
+ "hddac",
+ "main_parent",
+ "aux_parent";
+ clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
+ <&clk_s_d2_flexgen CLK_HDDAC>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
+ };
+
+ sti-dvo@8d00400 {
+ compatible = "st,stih407-dvo";
+ status = "disabled";
+ reg = <0x8d00400 0x200>;
+ reg-names = "dvo-reg";
+ clock-names = "dvo_pix",
+ "dvo",
+ "main_parent",
+ "aux_parent";
+ clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
+ <&clk_s_d2_flexgen CLK_DVO>,
+ <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvo>;
+ };
+
+ sti-hqvdp@9c000000 {
+ compatible = "st,stih407-hqvdp";
+ reg = <0x9C00000 0x100000>;
+ clock-names = "hqvdp", "pix_main";
+ clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
+ <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
+ reset-names = "hqvdp";
+ resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
+ st,vtg = <&vtg_main>;
+ };
+ };
+
+ bdisp0:bdisp@9f10000 {
+ compatible = "st,stih407-bdisp";
+ reg = <0x9f10000 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
+ clock-names = "bdisp";
+ clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
+ };
+
+ hva@8c85000 {
+ compatible = "st,st-hva";
+ reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
+ reg-names = "hva_registers", "hva_esram";
+ interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
+ <GIC_SPI 59 IRQ_TYPE_NONE>;
+ clock-names = "clk_hva";
+ clocks = <&clk_s_c0_flexgen CLK_HVA>;
+ };
+
+ thermal@91a0000 {
+ compatible = "st,stih407-thermal";
+ reg = <0x91a0000 0x28>;
+ clock-names = "thermal";
+ clocks = <&clk_sysin>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ g1@8c80000 {
+ compatible = "st,g1";
+ reg = <0x8c80000 0x194>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
+ };
+
+ temp0{
+ compatible = "st,stih407-thermal";
+ reg = <0x91a0000 0x28>;
+ clock-names = "thermal";
+ clocks = <&clk_sysin>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ delta0 {
+ compatible = "st,delta";
+ clock-names = "delta", "delta-st231", "delta-flash-promip";
+ clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
+ <&clk_s_c0_flexgen CLK_ST231_DMU>,
+ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
+ };
+
+ h264pp0: h264pp@8c00000 {
+ compatible = "st,h264pp";
+ reg = <0x8c00000 0x20000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
+ clock-names = "clk_h264pp_0";
+ clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
+ };
+
+ mali: mali@09f00000 {
+ compatible = "arm,mali-400";
+ reg = <0x09f00000 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
+ <GIC_SPI 50 IRQ_TYPE_NONE>,
+ <GIC_SPI 41 IRQ_TYPE_NONE>,
+ <GIC_SPI 45 IRQ_TYPE_NONE>,
+ <GIC_SPI 42 IRQ_TYPE_NONE>,
+ <GIC_SPI 46 IRQ_TYPE_NONE>,
+ <GIC_SPI 43 IRQ_TYPE_NONE>,
+ <GIC_SPI 47 IRQ_TYPE_NONE>,
+ <GIC_SPI 44 IRQ_TYPE_NONE>,
+ <GIC_SPI 48 IRQ_TYPE_NONE>;
+ interrupt-names = "IRQGP",
+ "IRQGPMMU",
+ "IRQPP0",
+ "IRQPPMMU0",
+ "IRQPP1",
+ "IRQPPMMU1",
+ "IRQPP2",
+ "IRQPPMMU2",
+ "IRQPP3",
+ "IRQPPMMU3";
+ clock-names = "gpu-clk";
+ clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
+ reset-names = "gpu";
+ resets = <&softreset STIH407_GPU_SOFTRESET>;
+ };
+
+ delta0 {
+ compatible = "st,st-delta";
+ clock-names = "delta",
+ "delta-st231",
+ "delta-flash-promip";
+ clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
+ <&clk_s_c0_flexgen CLK_ST231_DMU>,
+ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
+ };
+
+ h264pp0: h264pp@8c00000 {
+ compatible = "st,h264pp";
+ reg = <0x8c00000 0x20000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
+ clock-names = "clk_h264pp_0";
+ clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
+ };
+
+ mali: mali@09f00000 {
+ compatible = "arm,mali-400";
+ reg = <0x09f00000 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
+ <GIC_SPI 50 IRQ_TYPE_NONE>,
+ <GIC_SPI 41 IRQ_TYPE_NONE>,
+ <GIC_SPI 45 IRQ_TYPE_NONE>,
+ <GIC_SPI 42 IRQ_TYPE_NONE>,
+ <GIC_SPI 46 IRQ_TYPE_NONE>,
+ <GIC_SPI 43 IRQ_TYPE_NONE>,
+ <GIC_SPI 47 IRQ_TYPE_NONE>,
+ <GIC_SPI 44 IRQ_TYPE_NONE>,
+ <GIC_SPI 48 IRQ_TYPE_NONE>;
+ interrupt-names = "IRQGP",
+ "IRQGPMMU",
+ "IRQPP0",
+ "IRQPPMMU0",
+ "IRQPP1",
+ "IRQPPMMU1",
+ "IRQPP2",
+ "IRQPPMMU2",
+ "IRQPP3",
+ "IRQPPMMU3";
+ clock-names = "gpu-clk";
+ clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
+ reset-names = "gpu";
+ resets = <&softreset STIH407_GPU_SOFTRESET>;
+ };
+
+ hva@8c85000{
+ compatible = "st,st-hva";
+ reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
+ reg-names = "hva_registers", "hva_esram";
+ interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
+ <GIC_SPI 59 IRQ_TYPE_NONE>;
+ clock-names = "clk_hva";
+ clocks = <&clk_s_c0_flexgen CLK_HVA>;
+ };
+ };
+};
model = "UniPhier LD11 Reference Board";
compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
aliases {
serial0 = &serial0;
serial1 = &serial1;
i2c5 = &i2c5;
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
};
ðsc {
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
-
-&pinctrl_system_bus {
- u-boot,dm-pre-reloc;
-};
<1 10 4>;
};
- soc {
+ soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
mioctrl@5b3e0000 {
- compatible = "socionext,uniphier-mioctrl",
+ compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
model = "UniPhier LD20 Reference Board";
compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
aliases {
serial0 = &serial0;
serial1 = &serial1;
i2c5 = &i2c5;
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
};
ðsc {
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
-
-&pinctrl_system_bus {
- u-boot,dm-pre-reloc;
-};
<1 10 4>;
};
- soc {
+ soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
model = "UniPhier LD4 Reference Board";
compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c2 = &i2c2;
i2c3 = &i2c3;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
};
ðsc {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
-
/ {
compatible = "socionext,uniphier-ld4";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
model = "UniPhier LD6b Reference Board";
compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c5 = &i2c5;
i2c6 = &i2c6;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
};
ðsc {
/*
* Device Tree Source for UniPhier SoCs default pinctrl settings
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
model = "UniPhier Pro4 Ace Board";
compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c5 = &i2c5;
i2c6 = &i2c6;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
};
&serial0 {
eeprom@54 {
compatible = "st,24c64", "i2c-eeprom";
reg = <0x54>;
+ pagesize = <32>;
u-boot,i2c-offset-len = <2>;
};
};
model = "UniPhier Pro4 Reference Board";
compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c6 = &i2c6;
usb0 = &usb0;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
};
ðsc {
model = "UniPhier Pro4 Sanji Board";
compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c5 = &i2c5;
i2c6 = &i2c6;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
};
&serial0 {
eeprom@54 {
compatible = "st,24c64", "i2c-eeprom";
reg = <0x54>;
+ pagesize = <32>;
u-boot,i2c-offset-len = <2>;
};
};
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
-
/ {
compatible = "socionext,uniphier-pro4";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
model = "UniPhier Pro5 4KBOX Board";
compatible = "socionext,uniphier-pro5-4kbox", "socionext,uniphier-pro5";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
chosen {
stdout-path = "serial1:115200n8";
};
i2c5 = &i2c5;
i2c6 = &i2c6;
};
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
};
&serial1 {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
-
/ {
compatible = "socionext,uniphier-pro5";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
compatible = "socionext,uniphier-pxs2-gentil",
"socionext,uniphier-pxs2";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c5 = &i2c5;
i2c6 = &i2c6;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
};
&serial2 {
eeprom@54 {
compatible = "st,24c64", "i2c-eeprom";
reg = <0x54>;
+ pagesize = <32>;
u-boot,i2c-offset-len = <2>;
};
};
model = "UniPhier PXs2 Vodka Board";
compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c5 = &i2c5;
i2c6 = &i2c6;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
};
&serial2 {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
-
/ {
compatible = "socionext,uniphier-pxs2";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
-
- i2c_clk: i2c_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
};
soc {
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
interrupts = <0 43 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 6>;
clock-frequency = <100000>;
};
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 8>;
clock-frequency = <400000>;
};
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
- clocks = <&i2c_clk>;
+ clocks = <&peri_clk 10>;
clock-frequency = <400000>;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-pxs2-sysctrl",
"simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
+ reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-pxs2-clock";
model = "UniPhier PXs3 Reference Board";
compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
aliases {
serial0 = &serial0;
serial1 = &serial1;
i2c6 = &i2c6;
};
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0xa0000000>;
};
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
};
ðsc {
<1 10 4>;
};
- soc {
+ soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/*
* Device Tree Source for UniPhier Reference Daughter Board
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
eeprom@50 {
compatible = "microchip,24lc128", "i2c-eeprom";
reg = <0x50>;
+ pagesize = <64>;
u-boot,i2c-offset-len = <2>;
};
};
model = "UniPhier sLD3 Reference Board";
compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000
- 0xc0000000 0x20000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c3 = &i2c3;
i2c4 = &i2c4;
};
+
+ memory@8000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000
+ 0xc0000000 0x20000000>;
+ };
};
ðsc {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
-
/ {
compatible = "socionext,uniphier-sld3";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&sys_clk 0>;
clock-frequency = <36864000>;
};
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&sys_clk 0>;
clock-frequency = <36864000>;
};
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&sys_clk 0>;
clock-frequency = <36864000>;
};
};
mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
+ compatible = "socionext,uniphier-sld3-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
sysctrl@f1840000 {
compatible = "socionext,uniphier-sld3-sysctrl",
"simple-mfd", "syscon";
- reg = <0xf1840000 0x4000>;
+ reg = <0xf1840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-sld3-clock";
model = "UniPhier sLD8 Reference Board";
compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
i2c2 = &i2c2;
i2c3 = &i2c3;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
};
ðsc {
* SPDX-License-Identifier: GPL-2.0+ X11
*/
-/include/ "skeleton.dtsi"
-
/ {
compatible = "socionext,uniphier-sld8";
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
/*
* Device Tree Source for UniPhier Support Card (Expansion Board)
*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
status = "okay";
ranges = <1 0x00000000 0x42000000 0x02000000>;
- support_card: support_card {
+ support_card: support_card@1,1f00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
config SECURE_BOOT
bool "Support i.MX HAB features"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+ select FSL_CAAM
help
This option enables the support for secure boot (HAB).
See doc/README.mxc_hab for more details.
void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base,
u32 size);
-void omap_nand_switch_ecc(uint32_t, uint32_t);
+int omap_nand_switch_ecc(uint32_t, uint32_t);
void set_uart_mux_conf(void);
void set_mux_conf_regs(void);
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
-#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ERRATUM_A008751
-/* ARM A57 CORE ERRATA */
-#define CONFIG_ARM_ERRATA_826974
-#define CONFIG_ARM_ERRATA_828024
-#define CONFIG_ARM_ERRATA_829520
-#define CONFIG_ARM_ERRATA_833471
-
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
},
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
},
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#elif defined(CONFIG_FSL_LSCH2)
},
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+ u32 gpporcr3;
+ u32 gpporcr4;
+ u8 res_030[0x60-0x30];
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
u32 dcfg_fusesr; /* Fuse status register */
- u32 gpporcr3;
- u32 gpporcr4;
- u8 res_034[0x70-0x34];
- u32 devdisr; /* Device disable control */
+ u8 res_064[0x70-0x64];
+ u32 devdisr; /* Device disable control 1 */
u32 devdisr2; /* Device disable control 2 */
u32 devdisr3; /* Device disable control 3 */
u32 devdisr4; /* Device disable control 4 */
u32 devdisr5; /* Device disable control 5 */
u32 devdisr6; /* Device disable control 6 */
- u32 devdisr7; /* Device disable control 7 */
+ u8 res_088[0x94-0x88];
+ u32 coredisr; /* Device disable control 7 */
#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
- u8 res_08c[0x90-0x8c];
- u32 coredisru; /* uppper portion for support of 64 cores */
- u32 coredisrl; /* lower portion for support of 64 cores */
u8 res_098[0xa0-0x98];
u32 pvr; /* Processor version */
u32 svr; /* System version */
- u32 mvr; /* Manufacturing version */
- u8 res_0ac[0x100-0xac];
- u32 rcwsr[32]; /* Reset control word status */
+ u8 res_0a8[0x100-0xa8];
+ u32 rcwsr[30]; /* Reset control word status */
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400
- u8 res_180[0x200-0x180];
- u32 scratchrw[32]; /* Scratch Read/Write */
- u8 res_280[0x300-0x280];
+ u8 res_178[0x200-0x178];
+ u32 scratchrw[16]; /* Scratch Read/Write */
+ u8 res_240[0x300-0x240];
u32 scratchw1r[4]; /* Scratch Read (Write once) */
u8 res_310[0x400-0x310];
u32 bootlocptrl; /* Boot location pointer low-order addr */
u32 bootlocptrh; /* Boot location pointer high-order addr */
- u8 res_408[0x500-0x408];
- u8 res_500[0x740-0x500]; /* add more registers when needed */
+ u8 res_408[0x520-0x408];
+ u32 usb1_amqr;
+ u32 usb2_amqr;
+ u8 res_528[0x530-0x528]; /* add more registers when needed */
+ u32 sdmm1_amqr;
+ u8 res_534[0x550-0x534]; /* add more registers when needed */
+ u32 sata1_amqr;
+ u32 sata2_amqr;
+ u8 res_558[0x570-0x558]; /* add more registers when needed */
+ u32 misc1_amqr;
+ u8 res_574[0x590-0x574]; /* add more registers when needed */
+ u32 spare1_amqr;
+ u32 spare2_amqr;
+ u8 res_598[0x620-0x598]; /* add more registers when needed */
+ u32 gencr[7]; /* General Control Registers */
+ u8 res_63c[0x640-0x63c]; /* add more registers when needed */
+ u32 cgensr1; /* Core General Status Register */
+ u8 res_644[0x660-0x644]; /* add more registers when needed */
+ u32 cgencr1; /* Core General Control Register */
+ u8 res_664[0x740-0x664]; /* add more registers when needed */
u32 tp_ityp[64]; /* Topology Initiator Type Register */
struct {
u32 upper;
u32 lower;
- } tp_cluster[3]; /* Core Cluster n Topology Register */
- u8 res_858[0x1000-0x858];
+ } tp_cluster[4]; /* Core cluster n Topology Register */
+ u8 res_864[0x920-0x864]; /* add more registers when needed */
+ u32 ioqoscr[8]; /*I/O Quality of Services Register */
+ u32 uccr;
+ u8 res_944[0x960-0x944]; /* add more registers when needed */
+ u32 ftmcr;
+ u8 res_964[0x990-0x964]; /* add more registers when needed */
+ u32 coredisablesr;
+ u8 res_994[0xa00-0x994]; /* add more registers when needed */
+ u32 sdbgcr; /*Secure Debug Confifuration Register */
+ u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
+ u32 ipbrr1;
+ u32 ipbrr2;
+ u8 res_858[0x1000-0xc00];
};
-
struct ccsr_clk_cluster_group {
struct {
u8 res_00[0x10];
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
-#include <asm/arch-armv8/mmu.h>
+void update_early_mmu_table(void);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
* ROM code API related flags
*/
#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
+#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2
#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
/*
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
-void omap_nand_switch_ecc(uint32_t, uint32_t);
+int omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_set_aux_cr_secure(u32 acr);
#if defined(CONFIG_DRA7XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
-#define NON_SECURE_SRAM_IMG_END 0x4037E000
+#define NON_SECURE_SRAM_IMG_END 0x4037C000
#else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
--- /dev/null
+/*
+ * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __STI_SDHCI_H__
+#define __STI_SDHCI_H__
+
+#define FLASHSS_MMC_CORE_CONFIG_1 0x400
+#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
+#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
+
+#define STI_FLASHSS_MMC_CORE_CONFIG_1 \
+ (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \
+ FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
+
+#define FLASHSS_MMC_CORE_CONFIG_2 0x404
+#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28)
+#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20)
+#define MAX_BLK_LENGTH_1024 BIT(16)
+#define BASE_CLK_FREQ_200 0xc8
+
+#define STI_FLASHSS_MMC_CORE_CONFIG2 \
+ (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
+ FLASHSS_MMC_CORECFG_8BIT_EMMC | \
+ MAX_BLK_LENGTH_1024 | \
+ BASE_CLK_FREQ_200 << 0)
+
+#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \
+ (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
+ MAX_BLK_LENGTH_1024 | \
+ BASE_CLK_FREQ_200)
+
+#define FLASHSS_MMC_CORE_CONFIG_3 0x408
+#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28)
+#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
+#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
+#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4)
+#define FLASHSS_MMC_CORECFG_SDMA BIT(0)
+
+#define STI_FLASHSS_MMC_CORE_CONFIG3 \
+ (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \
+ FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
+ FLASHSS_MMC_CORECFG_3P3_VOLT | \
+ FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
+ FLASHSS_MMC_CORECFG_SDMA)
+
+#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \
+ (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
+ FLASHSS_MMC_CORECFG_3P3_VOLT | \
+ FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
+ FLASHSS_MMC_CORECFG_SDMA)
+
+#define FLASHSS_MMC_CORE_CONFIG_4 0x40c
+#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20)
+#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16)
+#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12)
+
+#define STI_FLASHSS_MMC_CORE_CONFIG4 \
+ (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \
+ FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \
+ FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
+
+#define ST_MMC_CCONFIG_REG_5 0x210
+#define SYSCONF_MMC1_ENABLE_BIT 3
+
+#endif /* _STI_SDHCI_H_ */
#define PTE_TYPE_FAULT (0 << 0)
#define PTE_TYPE_TABLE (3 << 0)
#define PTE_TYPE_BLOCK (1 << 0)
+#define PTE_TYPE_VALID (1 << 0)
#define PTE_TABLE_PXN (1UL << 59)
#define PTE_TABLE_XN (1UL << 60)
*/
#define PMD_ATTRINDX(t) ((t) << 2)
#define PMD_ATTRINDX_MASK (7 << 2)
+#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
+ PTE_BLOCK_UXN | \
+ PMD_ATTRINDX_MASK | \
+ PTE_TYPE_VALID)
/*
* TCR flags.
.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
.macro ret\c, reg
-#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__)
+#if defined(__ARM_ARCH_5E__)
mov\c pc, \reg
#else
.ifeqs "\reg", "lr"
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_HW_ACCEL
#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA_FREESCALE_EXP
-
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_SPL_BUILD
/* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively.
*/
-#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800
-#define CONFIG_BS_ADDR_DEVICE 0x00000840
+#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
+#define CONFIG_BS_ADDR_DEVICE 0x00000940
#define CONFIG_BS_HDR_SIZE 0x00000010
#define CONFIG_BS_SIZE 0x00000008
#else
phys_addr_t secure_ram;
unsigned long tlb_allocated;
#endif
+#ifdef CONFIG_RESV_RAM
+ /*
+ * Reserved RAM for memory resident, eg. Management Complex (MC)
+ * driver which continues to run after U-Boot exits.
+ */
+ phys_addr_t resv_ram;
+#endif
#ifdef CONFIG_ARCH_OMAP2
u32 omap_boot_device;
-#ifndef CONFIG_ARCH_UNIPHIER
+#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>
void smp_kick_all_cpus(void);
void flush_l3_cache(void);
+void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
/*
*Issue a secure monitor call in accordance with ARM "SMC Calling convention",
*/
bl c_runtime_cpu_setup /* still call old routine */
#endif /* !CONFIG_SPL_BUILD */
-
-/* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */
+#if defined(CONFIG_SPL_BUILD)
+ bl spl_relocate_stack_gd /* may return NULL */
+ /*
+ * Perform 'sp = (x0 != NULL) ? x0 : sp' while working
+ * around the constraint that conditional moves can not
+ * have 'sp' as an operand
+ */
+ mov x1, sp
+ cmp x0, #0
+ csel x0, x0, x1, ne
+ mov sp, x0
+#endif
/*
* Clear BSS section
if (argc == 3 || argc == 4) {
ulong load_addr;
ulong end_addr = 0;
- ulong ret;
+ int ret;
char end_str[64];
load_addr = simple_strtoul(argv[2], NULL, 16);
ret = smh_load_file(argv[1], load_addr, &end_addr);
if (ret < 0)
- return 1;
+ return CMD_RET_FAILURE;
/* Optionally save returned end to the environment */
if (argc == 4) {
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select ARM_ERRATA_773022
+ select ARM_ERRATA_774769
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select DM_SERIAL
select DM_GPIO
select TI_I2C_BOARD_DETECT
+ imply SPL_ENV_SUPPORT
+ imply SPL_EXT_SUPPORT
+ imply SPL_FAT_SUPPORT
+ imply SPL_GPIO_SUPPORT
+ imply SPL_I2C_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_MMC_SUPPORT
+ imply SPL_NAND_SUPPORT
+ imply SPL_POWER_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply SPL_WATCHDOG_SUPPORT
+ imply SPL_YMODEM_SUPPORT
help
This option specifies support for the AM335x
GP and HS EVM development platforms. The AM335x
if AM43XX
-config SPL_EXT_SUPPORT
- default y
-
-config SPL_GPIO_SUPPORT
- default y
-
-config SPL_I2C_SUPPORT
- default y
-
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select BOARD_LATE_INIT
select TI_I2C_BOARD_DETECT
+ imply SPL_ENV_SUPPORT
+ imply SPL_EXT_SUPPORT
+ imply SPL_FAT_SUPPORT
+ imply SPL_GPIO_SUPPORT
+ imply SPL_I2C_SUPPORT
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBDISK_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_MMC_SUPPORT
+ imply SPL_NAND_SUPPORT
+ imply SPL_POWER_SUPPORT
+ imply SPL_SERIAL_SUPPORT
+ imply SPL_WATCHDOG_SUPPORT
+ imply SPL_YMODEM_SUPPORT
help
This option specifies support for the AM43xx
GP and HS EVM development platforms.The AM437x
ddr3_init(base, regs);
#endif
}
-#ifdef CONFIG_OMAP54X
+#ifdef CONFIG_OMAP54XX
if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
set_lpmode_selfrefresh(base);
if OMAP34XX
-config SPL_EXT_SUPPORT
- default y
-
-config SPL_FAT_SUPPORT
- default y
-
-config SPL_GPIO_SUPPORT
- default y
-
-config SPL_I2C_SUPPORT
- default y
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC_SUPPORT
- default y
-
-config SPL_NAND_SUPPORT
- default y
-
-config SPL_POWER_SUPPORT
- default y
-
-config SPL_SERIAL_SUPPORT
- default y
-
choice
prompt "OMAP3 board select"
optional
# SPDX-License-Identifier: GPL-2.0+
#
+# If clock.c is compiled for Thumb2, then it fails on OMAP3530
+CFLAGS_clock.o += -marm
+
obj-y := lowlevel_init.o
obj-y += board.o
*****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
+ int hw, strength = 1;
+
if (argc < 2 || argc > 3)
goto usage;
if (strncmp(argv[1], "hw", 2) == 0) {
- if (argc == 2) {
- omap_nand_switch_ecc(1, 1);
- } else {
- if (strncmp(argv[2], "hamming", 7) == 0)
- omap_nand_switch_ecc(1, 1);
- else if (strncmp(argv[2], "bch8", 4) == 0)
- omap_nand_switch_ecc(1, 8);
+ hw = 1;
+ if (argc == 3) {
+ if (strncmp(argv[2], "bch8", 4) == 0)
+ strength = 8;
else if (strncmp(argv[2], "bch16", 5) == 0)
- omap_nand_switch_ecc(1, 16);
- else
+ strength = 16;
+ else if (strncmp(argv[2], "hamming", 7) != 0)
goto usage;
}
} else if (strncmp(argv[1], "sw", 2) == 0) {
- if (argc == 2) {
- omap_nand_switch_ecc(0, 1);
- } else {
- if (strncmp(argv[2], "hamming", 7) == 0)
- omap_nand_switch_ecc(0, 1);
- else if (strncmp(argv[2], "bch8", 4) == 0)
- omap_nand_switch_ecc(0, 8);
- else
+ hw = 0;
+ if (argc == 3) {
+ if (strncmp(argv[2], "bch8", 4) == 0)
+ strength = 8;
+ else if (strncmp(argv[2], "hamming", 7) != 0)
goto usage;
}
} else {
goto usage;
}
- return 0;
+ return -omap_nand_switch_ecc(hw, strength);
usage:
printf ("Usage: nandecc %s\n", cmdtp->usage);
(u32 *)&emu_romcode_params);
}
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ if (get_device_type() == GP_DEVICE)
+ omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
+
+ /* L2 Cache Auxiliary Control Register is not banked */
+}
+
void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev)
{
if OMAP44XX
-config SPL_EXT_SUPPORT
- default y
-
-config SPL_FAT_SUPPORT
- default y
-
-config SPL_GPIO_SUPPORT
- default y
-
-config SPL_I2C_SUPPORT
- default y
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC_SUPPORT
- default y
-
-config SPL_NAND_SUPPORT
- default y
-
-config SPL_POWER_SUPPORT
- default y
-
-config SPL_SERIAL_SUPPORT
- default y
-
-config SPL_DISPLAY_PRINT
- default y
-
choice
prompt "OMAP4 board select"
optional
if OMAP54XX
-config SPL_EXT_SUPPORT
- default y
-
-config SPL_FAT_SUPPORT
- default y
-
-config SPL_GPIO_SUPPORT
- default y
-
-config SPL_I2C_SUPPORT
- default y
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC_SUPPORT
- default y
-
-config SPL_NAND_SUPPORT
- default y
-
-config SPL_POWER_SUPPORT
- default y
-
-config SPL_SERIAL_SUPPORT
- default y
-
-config SPL_DISPLAY_PRINT
- default y
-
choice
prompt "OMAP5 board select"
optional
u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
fdt64_t temp[2];
+ fdt32_t two;
/* If start address is zero, place at end of DRAM */
if (0 == sec_mem_start)
debug("Node %s not found\n", path);
path = "/";
subpath = "reserved-memory";
- fdt_path_offset(fdt, path);
+ offs = fdt_path_offset(fdt, path);
offs = fdt_add_subnode(fdt, offs, subpath);
if (offs < 0) {
printf("Could not create %s%s node.\n", path, subpath);
}
path = "/reserved-memory";
offs = fdt_path_offset(fdt, path);
+ two = cpu_to_fdt32(2);
+ fdt_setprop(fdt, offs, "#address-cells", &two, sizeof(two));
+ fdt_setprop(fdt, offs, "#size-cells", &two, sizeof(two));
+ fdt_setprop(fdt, offs, "ranges", NULL, 0);
}
subpath = "secure_reserved";
result = secure_rom_call(
API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0,
4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF);
+
+ /* Perform cache writeback on output buffer */
+ flush_dcache_range(
+ (u32)*image,
+ (u32)*image + roundup(*size, ARCH_DMA_MINALIGN));
+
auth_exit:
if (result != 0) {
printf("Authentication failed!\n");
config SPL_WATCHDOG_SUPPORT
default y
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ default y
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+ default 0xa2
+
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
--- /dev/null
+if ARCH_STI
+
+config SYS_SOC
+ default "stih410"
+
+choice
+ prompt "STiH410 board select"
+
+config TARGET_STIH410_B2260
+ bool "96Boards STiH410-B2260"
+ help
+ Support for 96Board STiH410-B2260 based on STMicrolectronics
+ STiH410 soc. This board complies with 96Board Open Platform
+ Specifications. Features:
+ - 1GB DDR
+ - On-Board USB combo WiFi/Bluetooth RTL8723BU
+ with PCB soldered antenna
+ - Ethernet 1000-BaseT
+ - Sata
+ - HDMI
+ - 2 x USB2 type A
+ - micro USB2 type AB
+ - SD card slot
+ - High speed connector (SD/I2C/USB interfaces)
+ - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
+
+endchoice
+
+source "board/st/stih410-b2260/Kconfig"
+
+endif
config TEGRA20
bool "Tegra20 family"
+ select ARM_ERRATA_716044
+ select ARM_ERRATA_742230
+ select ARM_ERRATA_751472
select TEGRA_ARMV7_COMMON
config TEGRA30
bool "Tegra30 family"
+ select ARM_ERRATA_743622
+ select ARM_ERRATA_751472
select TEGRA_ARMV7_COMMON
config TEGRA114
obj-y += spl_board_init.o
obj-y += memconf.o
obj-y += bcu/
+obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc-boot-mode.o
else
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o
obj-y += pinctrl-glue.o
+obj-$(CONFIG_MMC) += mmc-first-dev.o
endif
obj-y += soc-info.o
-obj-y += boot-mode/
+obj-y += boot-device/
obj-y += clk/
obj-y += dram/
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
- shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
+ shift = bd->dram_ch[0].size / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
- shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
+ shift = bd->dram_ch[0].size / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
.nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld20_pll_init,
+ .clk_init = uniphier_ld20_clk_init,
.misc_init = uniphier_ld20_misc_init,
},
#endif
#include <linux/io.h>
#include <../drivers/mtd/nand/denali.h>
-#include "boot-mode/boot-device.h"
+#include "init.h"
static void nand_denali_wp_disable(void)
{
{
puts("MODE: ");
- switch (spl_boot_device_raw()) {
+ switch (uniphier_boot_device_raw()) {
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
static const struct uniphier_board_data uniphier_sld3_data = {
.dram_freq = 1600,
- .dram_nr_ch = 3,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x20000000,
.width = 16,
},
.dram_ch[2] = {
- .base = 0xc0000000,
.size = 0x10000000,
.width = 16,
},
+ .flags = UNIPHIER_BD_DRAM_SPARSE,
};
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
static const struct uniphier_board_data uniphier_ld4_data = {
.dram_freq = 1600,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x10000000,
.width = 16,
},
.dram_ch[1] = {
- .base = 0x90000000,
.size = 0x10000000,
.width = 16,
},
/* 1GB RAM board */
static const struct uniphier_board_data uniphier_pro4_data = {
.dram_freq = 1600,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xa0000000,
.size = 0x20000000,
.width = 32,
},
/* 2GB RAM board */
static const struct uniphier_board_data uniphier_pro4_2g_data = {
.dram_freq = 1600,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
static const struct uniphier_board_data uniphier_sld8_data = {
.dram_freq = 1333,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x10000000,
.width = 16,
},
.dram_ch[1] = {
- .base = 0x90000000,
.size = 0x10000000,
.width = 16,
},
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
static const struct uniphier_board_data uniphier_pro5_data = {
.dram_freq = 1866,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xa0000000,
.size = 0x20000000,
.width = 32,
},
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
static const struct uniphier_board_data uniphier_pxs2_data = {
.dram_freq = 2133,
- .dram_nr_ch = 3,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[2] = {
- .base = 0xe0000000,
.size = 0x20000000,
.width = 16,
},
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
static const struct uniphier_board_data uniphier_ld6b_data = {
.dram_freq = 1866,
- .dram_nr_ch = 3,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[2] = {
- .base = 0xe0000000,
.size = 0x20000000,
.width = 16,
},
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
static const struct uniphier_board_data uniphier_ld11_data = {
.dram_freq = 1600,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x20000000,
.width = 16,
},
.dram_ch[1] = {
- .base = 0xa0000000,
.size = 0x20000000,
.width = 16,
},
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
static const struct uniphier_board_data uniphier_ld20_ref_data = {
.dram_freq = 1866,
- .dram_nr_ch = 3,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[2] = {
- .base = 0x100000000UL,
.size = 0x40000000,
.width = 32,
},
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
- .dram_nr_ch = 3,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[2] = {
- .base = 0x100000000UL,
.size = 0x40000000,
.width = 32,
},
static const struct uniphier_board_data uniphier_ld21_data = {
.dram_freq = 1866,
- .dram_nr_ch = 2,
.dram_ch[0] = {
- .base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
- .base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
- .flags = UNIPHIER_BD_BOARD_LD21_GLOBAL,
+ .flags = UNIPHIER_BD_DRAM_SPARSE | UNIPHIER_BD_BOARD_LD21_GLOBAL,
};
#endif
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += boot-device.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-device-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-device-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-device-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-device-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-device-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-device-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-device-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o
+endif
--- /dev/null
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "boot-device.h"
+
+const struct uniphier_boot_device uniphier_ld11_boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
+ {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_NOR, "NOR (XECS1)"},
+};
+
+const unsigned uniphier_ld11_boot_device_count =
+ ARRAY_SIZE(uniphier_ld11_boot_device_table);
+
+int uniphier_ld11_boot_device_is_usb(u32 pinmon)
+{
+ return !!(~pinmon & 0x00000080);
+}
+
+int uniphier_ld20_boot_device_is_usb(u32 pinmon)
+{
+ return !!(~pinmon & 0x00000780);
+}
+
+unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode)
+{
+ if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
+ mode = BOOT_DEVICE_BOARD;
+
+ return mode;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "boot-device.h"
+
+const struct uniphier_boot_device uniphier_ld4_boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V)"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NOR, "NOR (XECS0)"},
+};
+
+const unsigned uniphier_ld4_boot_device_count =
+ ARRAY_SIZE(uniphier_ld4_boot_device_table);
--- /dev/null
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "boot-device.h"
+
+const struct uniphier_boot_device uniphier_pro5_boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+};
+
+const unsigned uniphier_pro5_boot_device_count =
+ ARRAY_SIZE(uniphier_pro5_boot_device_table);
--- /dev/null
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "boot-device.h"
+
+const struct uniphier_boot_device uniphier_pxs2_boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
+ {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
+ {BOOT_DEVICE_SPI, "SPI (3Byte CS1)"},
+ {BOOT_DEVICE_SPI, "SPI (4Byte CS1)"},
+ {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
+ {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+const unsigned uniphier_pxs2_boot_device_count =
+ ARRAY_SIZE(uniphier_pxs2_boot_device_table);
+
+int uniphier_pxs2_boot_device_is_usb(u32 pinmon)
+{
+ return !!(pinmon & 0x00000040);
+}
+
+unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode)
+{
+ if (mode == BOOT_DEVICE_USB)
+ return BOOT_DEVICE_NOR;
+
+ return mode;
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "boot-device.h"
+
+const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = {
+ {BOOT_DEVICE_NOR, "NOR (XECS0)"},
+ {BOOT_DEVICE_NONE, "External Master"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+const unsigned uniphier_sld3_boot_device_count =
+ ARRAY_SIZE(uniphier_sld3_boot_device_table);
--- /dev/null
+/*
+ * Copyright (C) 2015-2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/log2.h>
+
+#include "../init.h"
+#include "../sbc/sbc-regs.h"
+#include "../sg-regs.h"
+#include "../soc-info.h"
+#include "boot-device.h"
+
+struct uniphier_boot_device_info {
+ unsigned int soc_id;
+ unsigned int boot_device_sel_shift;
+ const struct uniphier_boot_device *boot_device_table;
+ const unsigned int *boot_device_count;
+ int (*boot_device_is_usb)(u32 pinmon);
+ unsigned int (*boot_device_fixup)(unsigned int mode);
+};
+
+static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
+ {
+ .soc_id = UNIPHIER_SLD3_ID,
+ .boot_device_sel_shift = 0,
+ .boot_device_table = uniphier_sld3_boot_device_table,
+ .boot_device_count = &uniphier_sld3_boot_device_count,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
+ {
+ .soc_id = UNIPHIER_LD4_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_ld4_boot_device_table,
+ .boot_device_count = &uniphier_ld4_boot_device_count,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
+ {
+ .soc_id = UNIPHIER_PRO4_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_ld4_boot_device_table,
+ .boot_device_count = &uniphier_ld4_boot_device_count,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
+ {
+ .soc_id = UNIPHIER_SLD8_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_ld4_boot_device_table,
+ .boot_device_count = &uniphier_ld4_boot_device_count,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
+ {
+ .soc_id = UNIPHIER_PRO5_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_pro5_boot_device_table,
+ .boot_device_count = &uniphier_pro5_boot_device_count,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
+ {
+ .soc_id = UNIPHIER_PXS2_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_pxs2_boot_device_table,
+ .boot_device_count = &uniphier_pxs2_boot_device_count,
+ .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
+ .boot_device_fixup = uniphier_pxs2_boot_device_fixup,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
+ {
+ .soc_id = UNIPHIER_LD6B_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_pxs2_boot_device_table,
+ .boot_device_count = &uniphier_pxs2_boot_device_count,
+ .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb,
+ .boot_device_fixup = uniphier_pxs2_boot_device_fixup,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+ {
+ .soc_id = UNIPHIER_LD11_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_ld11_boot_device_table,
+ .boot_device_count = &uniphier_ld11_boot_device_count,
+ .boot_device_is_usb = uniphier_ld11_boot_device_is_usb,
+ .boot_device_fixup = uniphier_ld11_boot_device_fixup,
+ },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ {
+ .soc_id = UNIPHIER_LD20_ID,
+ .boot_device_sel_shift = 1,
+ .boot_device_table = uniphier_ld11_boot_device_table,
+ .boot_device_count = &uniphier_ld11_boot_device_count,
+ .boot_device_is_usb = uniphier_ld20_boot_device_is_usb,
+ .boot_device_fixup = uniphier_ld11_boot_device_fixup,
+ },
+#endif
+};
+UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info,
+ uniphier_boot_device_info)
+
+static unsigned int __uniphier_boot_device_raw(
+ const struct uniphier_boot_device_info *info)
+{
+ u32 pinmon;
+ unsigned int boot_sel;
+
+ if (boot_is_swapped())
+ return BOOT_DEVICE_NOR;
+
+ pinmon = readl(SG_PINMON0);
+
+ if (info->boot_device_is_usb && info->boot_device_is_usb(pinmon))
+ return BOOT_DEVICE_USB;
+
+ boot_sel = pinmon >> info->boot_device_sel_shift;
+
+ BUG_ON(!is_power_of_2(*info->boot_device_count));
+ boot_sel &= *info->boot_device_count - 1;
+
+ return info->boot_device_table[boot_sel].boot_device;
+}
+
+unsigned int uniphier_boot_device_raw(void)
+{
+ const struct uniphier_boot_device_info *info;
+
+ info = uniphier_get_boot_device_info();
+ if (!info) {
+ pr_err("unsupported SoC\n");
+ return BOOT_DEVICE_NONE;
+ }
+
+ return __uniphier_boot_device_raw(info);
+}
+
+u32 spl_boot_device(void)
+{
+ const struct uniphier_boot_device_info *info;
+ u32 raw_mode;
+
+ info = uniphier_get_boot_device_info();
+ if (!info) {
+ pr_err("unsupported SoC\n");
+ return BOOT_DEVICE_NONE;
+ }
+
+ raw_mode = __uniphier_boot_device_raw(info);
+
+ return info->boot_device_fixup ?
+ info->boot_device_fixup(raw_mode) : raw_mode;
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const struct uniphier_boot_device_info *info;
+ u32 pinmon;
+ unsigned int boot_device_count, boot_sel;
+ int i;
+
+ info = uniphier_get_boot_device_info();
+ if (!info) {
+ pr_err("unsupported SoC\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
+
+ pinmon = readl(SG_PINMON0);
+
+ if (info->boot_device_is_usb)
+ printf("USB Boot: %s\n\n",
+ info->boot_device_is_usb(pinmon) ? "ON" : "OFF");
+
+ boot_device_count = *info->boot_device_count;
+
+ boot_sel = pinmon >> info->boot_device_sel_shift;
+ boot_sel &= boot_device_count - 1;
+
+ printf("Boot Mode Sel:\n");
+ for (i = 0; i < boot_device_count; i++)
+ printf(" %c %02x %s\n", i == boot_sel ? '*' : ' ', i,
+ info->boot_device_table[i].desc);
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ pinmon, 1, 1, do_pinmon,
+ "pin monitor",
+ ""
+);
+
+#endif /* !CONFIG_SPL_BUILD */
--- /dev/null
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _UNIPHIER_BOOT_DEVICE_H_
+#define _UNIPHIER_BOOT_DEVICE_H_
+
+struct uniphier_boot_device {
+ unsigned int boot_device;
+ const char *desc;
+};
+
+extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
+extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
+
+extern const unsigned int uniphier_sld3_boot_device_count;
+extern const unsigned int uniphier_ld4_boot_device_count;
+extern const unsigned int uniphier_pro5_boot_device_count;
+extern const unsigned int uniphier_pxs2_boot_device_count;
+extern const unsigned int uniphier_ld11_boot_device_count;
+
+int uniphier_pxs2_boot_device_is_usb(u32 pinmon);
+int uniphier_ld11_boot_device_is_usb(u32 pinmon);
+int uniphier_ld20_boot_device_is_usb(u32 pinmon);
+
+unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode);
+unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode);
+
+#endif /* _UNIPHIER_BOOT_DEVICE_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <asm/processor.h>
+
+#include "../soc-info.h"
+
+#define MMC_CMD_SWITCH 6
+#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+
+#define EXT_CSD_PART_CONF 179 /* R/W */
+
+#define MMC_RSP_PRESENT BIT(0)
+#define MMC_RSP_136 BIT(1) /* 136 bit response */
+#define MMC_RSP_CRC BIT(2) /* expect valid crc */
+#define MMC_RSP_BUSY BIT(3) /* card may send busy */
+#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
+
+#define MMC_RSP_NONE (0)
+#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
+ MMC_RSP_BUSY)
+#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
+#define MMC_RSP_R3 (MMC_RSP_PRESENT)
+#define MMC_RSP_R4 (MMC_RSP_PRESENT)
+#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
+
+#define SDHCI_DMA_ADDRESS 0x00
+#define SDHCI_BLOCK_SIZE 0x04
+#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
+#define SDHCI_BLOCK_COUNT 0x06
+#define SDHCI_ARGUMENT 0x08
+#define SDHCI_TRANSFER_MODE 0x0C
+#define SDHCI_TRNS_DMA BIT(0)
+#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
+#define SDHCI_TRNS_ACMD12 BIT(2)
+#define SDHCI_TRNS_READ BIT(4)
+#define SDHCI_TRNS_MULTI BIT(5)
+#define SDHCI_COMMAND 0x0E
+#define SDHCI_CMD_RESP_MASK 0x03
+#define SDHCI_CMD_CRC 0x08
+#define SDHCI_CMD_INDEX 0x10
+#define SDHCI_CMD_DATA 0x20
+#define SDHCI_CMD_ABORTCMD 0xC0
+#define SDHCI_CMD_RESP_NONE 0x00
+#define SDHCI_CMD_RESP_LONG 0x01
+#define SDHCI_CMD_RESP_SHORT 0x02
+#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
+#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
+#define SDHCI_RESPONSE 0x10
+#define SDHCI_HOST_CONTROL 0x28
+#define SDHCI_CTRL_DMA_MASK 0x18
+#define SDHCI_CTRL_SDMA 0x00
+#define SDHCI_BLOCK_GAP_CONTROL 0x2A
+#define SDHCI_SOFTWARE_RESET 0x2F
+#define SDHCI_RESET_CMD 0x02
+#define SDHCI_RESET_DATA 0x04
+#define SDHCI_INT_STATUS 0x30
+#define SDHCI_INT_RESPONSE BIT(0)
+#define SDHCI_INT_DATA_END BIT(1)
+#define SDHCI_INT_ERROR BIT(15)
+#define SDHCI_SIGNAL_ENABLE 0x38
+
+/* RCA assigned by Boot ROM */
+#define UNIPHIER_EMMC_RCA 0x1000
+
+struct uniphier_mmc_cmd {
+ unsigned int cmdidx;
+ unsigned int resp_type;
+ unsigned int cmdarg;
+ unsigned int is_data;
+};
+
+static int uniphier_emmc_send_cmd(void __iomem *host_base,
+ struct uniphier_mmc_cmd *cmd)
+{
+ u32 mode = 0;
+ u32 mask = SDHCI_INT_RESPONSE;
+ u32 stat, flags;
+
+ writel(U32_MAX, host_base + SDHCI_INT_STATUS);
+ writel(0, host_base + SDHCI_SIGNAL_ENABLE);
+ writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT);
+
+ if (cmd->is_data)
+ mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
+ SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
+ SDHCI_TRNS_MULTI;
+
+ writew(mode, host_base + SDHCI_TRANSFER_MODE);
+
+ if (!(cmd->resp_type & MMC_RSP_PRESENT))
+ flags = SDHCI_CMD_RESP_NONE;
+ else if (cmd->resp_type & MMC_RSP_136)
+ flags = SDHCI_CMD_RESP_LONG;
+ else if (cmd->resp_type & MMC_RSP_BUSY)
+ flags = SDHCI_CMD_RESP_SHORT_BUSY;
+ else
+ flags = SDHCI_CMD_RESP_SHORT;
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ flags |= SDHCI_CMD_CRC;
+ if (cmd->resp_type & MMC_RSP_OPCODE)
+ flags |= SDHCI_CMD_INDEX;
+ if (cmd->is_data)
+ flags |= SDHCI_CMD_DATA;
+
+ if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
+ mask |= SDHCI_INT_DATA_END;
+
+ writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND);
+
+ do {
+ stat = readl(host_base + SDHCI_INT_STATUS);
+ if (stat & SDHCI_INT_ERROR)
+ return -EIO;
+
+ } while ((stat & mask) != mask);
+
+ return 0;
+}
+
+static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num)
+{
+ struct uniphier_mmc_cmd cmd = {};
+
+ cmd.cmdidx = MMC_CMD_SWITCH;
+ cmd.resp_type = MMC_RSP_R1b;
+ cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
+
+ return uniphier_emmc_send_cmd(host_base, &cmd);
+}
+
+static int uniphier_emmc_is_over_2gb(void __iomem *host_base)
+{
+ struct uniphier_mmc_cmd cmd = {};
+ u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */
+ int ret;
+
+ cmd.cmdidx = MMC_CMD_SEND_CSD;
+ cmd.resp_type = MMC_RSP_R2;
+ cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
+
+ ret = uniphier_emmc_send_cmd(host_base, &cmd);
+ if (ret)
+ return ret;
+
+ csd40 = readl(host_base + SDHCI_RESPONSE + 4);
+ csd72 = readl(host_base + SDHCI_RESPONSE + 8);
+
+ return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
+}
+
+static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr,
+ unsigned long load_addr, u32 block_cnt)
+{
+ struct uniphier_mmc_cmd cmd = {};
+ u8 tmp;
+
+ WARN_ON(load_addr >> 32);
+
+ writel(load_addr, host_base + SDHCI_DMA_ADDRESS);
+ writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE);
+ writew(block_cnt, host_base + SDHCI_BLOCK_COUNT);
+
+ tmp = readb(host_base + SDHCI_HOST_CONTROL);
+ tmp &= ~SDHCI_CTRL_DMA_MASK;
+ tmp |= SDHCI_CTRL_SDMA;
+ writeb(tmp, host_base + SDHCI_HOST_CONTROL);
+
+ tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL);
+ tmp &= ~1; /* clear Stop At Block Gap Request */
+ writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL);
+
+ cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = dev_addr;
+ cmd.is_data = 1;
+
+ return uniphier_emmc_send_cmd(host_base, &cmd);
+}
+
+static int spl_board_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+ void __iomem *host_base = (void __iomem *)0x5a000200;
+ struct uniphier_mmc_cmd cmd = {};
+ int ret;
+
+ /*
+ * deselect card before SEND_CSD command.
+ * Do not check the return code. It fails, but it is OK.
+ */
+ cmd.cmdidx = MMC_CMD_SELECT_CARD;
+ cmd.resp_type = MMC_RSP_R1;
+
+ uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
+
+ /* reset CMD Line */
+ writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA,
+ host_base + SDHCI_SOFTWARE_RESET);
+ while (readb(host_base + SDHCI_SOFTWARE_RESET))
+ cpu_relax();
+
+ ret = uniphier_emmc_is_over_2gb(host_base);
+ if (ret < 0)
+ return ret;
+ if (ret) {
+ debug("card is block addressing\n");
+ } else {
+ debug("card is byte addressing\n");
+ dev_addr *= 512;
+ }
+
+ cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
+
+ /* select card again */
+ ret = uniphier_emmc_send_cmd(host_base, &cmd);
+ if (ret)
+ printf("failed to select card\n");
+
+ /* Switch to Boot Partition 1 */
+ ret = uniphier_emmc_switch_part(host_base, 1);
+ if (ret)
+ printf("failed to switch partition\n");
+
+ ret = uniphier_emmc_load_image(host_base, dev_addr,
+ CONFIG_SYS_TEXT_BASE, 1);
+ if (ret) {
+ printf("failed to load image\n");
+ return ret;
+ }
+
+ ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
+ if (ret)
+ return ret;
+
+ ret = uniphier_emmc_load_image(host_base, dev_addr,
+ spl_image->load_addr,
+ spl_image->size / 512);
+ if (ret) {
+ printf("failed to load image\n");
+ return ret;
+ }
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += boot-mode.o
-
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += boot-mode-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += boot-mode-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += boot-mode-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-mode-ld20.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o
-else
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-endif
+++ /dev/null
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_BOOT_DEVICE_H_
-#define _ASM_BOOT_DEVICE_H_
-
-struct boot_device_info {
- u32 type;
- char *info;
-};
-
-u32 uniphier_sld3_boot_device(void);
-u32 uniphier_ld4_boot_device(void);
-u32 uniphier_pro5_boot_device(void);
-u32 uniphier_pxs2_boot_device(void);
-u32 uniphier_ld20_boot_device(void);
-
-void uniphier_sld3_boot_mode_show(void);
-void uniphier_ld4_boot_mode_show(void);
-void uniphier_pro5_boot_mode_show(void);
-void uniphier_pxs2_boot_mode_show(void);
-void uniphier_ld20_boot_mode_show(void);
-
-u32 spl_boot_device_raw(void);
-
-#endif /* _ASM_BOOT_DEVICE_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "../soc-info.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
- {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
- {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
- {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
- {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
- {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
- {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
- {BOOT_DEVICE_NOR, "NOR (XECS1)"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 uniphier_ld20_boot_device(void)
-{
- int boot_mode;
- u32 usb_boot_mask;
-
- switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_LD11)
- case UNIPHIER_LD11_ID:
- usb_boot_mask = 0x00000080;
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
- case UNIPHIER_LD20_ID:
- usb_boot_mask = 0x00000780;
- break;
-#endif
- default:
- BUG();
- }
-
- if (~readl(SG_PINMON0) & usb_boot_mask)
- return BOOT_DEVICE_USB;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void uniphier_ld20_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V)"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NOR, "NOR (XECS0)"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 uniphier_ld4_boot_device(void)
-{
- int boot_mode;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void uniphier_ld4_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- { /* sentinel */ }
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 uniphier_pro5_boot_device(void)
-{
- int boot_mode;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void uniphier_pro5_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
- {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
- {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
- {BOOT_DEVICE_SPI, "SPI (3Byte CS1)"},
- {BOOT_DEVICE_SPI, "SPI (4Byte CS1)"},
- {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
- {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
- {BOOT_DEVICE_NONE, "Reserved"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 uniphier_pxs2_boot_device(void)
-{
- int boot_mode;
-
- if (readl(SG_PINMON0) & BIT(6))
- return BOOT_DEVICE_USB;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void uniphier_pxs2_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../sg-regs.h"
-#include "boot-device.h"
-
-static struct boot_device_info boot_device_table[] = {
- {BOOT_DEVICE_NOR, "NOR (XECS0)"},
- {BOOT_DEVICE_NONE, "External Master"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
- {BOOT_DEVICE_NONE, "Reserved"},
-};
-
-static int get_boot_mode_sel(void)
-{
- return readl(SG_PINMON0) & 0x3f;
-}
-
-u32 uniphier_sld3_boot_device(void)
-{
- int boot_mode;
-
- boot_mode = get_boot_mode_sel();
-
- return boot_device_table[boot_mode].type;
-}
-
-void uniphier_sld3_boot_mode_show(void)
-{
- int mode_sel, i;
-
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <spl.h>
-#include <linux/errno.h>
-
-#include "../sbc/sbc-regs.h"
-#include "../soc-info.h"
-#include "boot-device.h"
-
-u32 spl_boot_device_raw(void)
-{
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
- switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- case UNIPHIER_SLD3_ID:
- return uniphier_sld3_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \
- defined(CONFIG_ARCH_UNIPHIER_SLD8)
- case UNIPHIER_LD4_ID:
- case UNIPHIER_PRO4_ID:
- case UNIPHIER_SLD8_ID:
- return uniphier_ld4_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- case UNIPHIER_PRO5_ID:
- return uniphier_pro5_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case UNIPHIER_PXS2_ID:
- case UNIPHIER_LD6B_ID:
- return uniphier_pxs2_boot_device();
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
- case UNIPHIER_LD11_ID:
- case UNIPHIER_LD20_ID:
- return uniphier_ld20_boot_device();
-#endif
- default:
- return BOOT_DEVICE_NONE;
- }
-}
-
-u32 spl_boot_device(void)
-{
- u32 mode;
-
- mode = spl_boot_device_raw();
-
- switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case UNIPHIER_PXS2_ID:
- case UNIPHIER_LD6B_ID:
- if (mode == BOOT_DEVICE_USB)
- mode = BOOT_DEVICE_NOR;
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
- case UNIPHIER_LD11_ID:
- case UNIPHIER_LD20_ID:
- if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
- mode = BOOT_DEVICE_BOARD;
- break;
-#endif
- default:
- break;
- }
-
- return mode;
-}
-
-u32 spl_boot_mode(const u32 boot_device)
-{
- struct mmc *mmc;
-
- /*
- * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8:
- *
- * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
- * Extended CSD register; when switching to the Boot Partition 1, the
- * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for
- * the Access Bits, but in fact it uses Write Byte for the Access Bits.
- * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG
- * is lost. This bug was fixed for PH1-Pro5 and later SoCs.
- *
- * Fixup mmc->part_config here because it is used to determine the
- * partition which the U-Boot image is read from.
- */
- mmc = find_mmc_device(0);
- mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
- mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
-
- return MMCSD_MODE_EMMCBOOT;
-}
-
-#if defined(CONFIG_DM_MMC) && !defined(CONFIG_SPL_BUILD)
-static int find_first_mmc_device(void)
-{
- struct mmc *mmc;
- int i;
-
- for (i = 0; (mmc = find_mmc_device(i)); i++) {
- if (!mmc_init(mmc) && IS_MMC(mmc))
- return i;
- }
-
- return -ENODEV;
-}
-
-int mmc_get_env_dev(void)
-{
- return find_first_mmc_device();
-}
-
-static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int dev;
-
- dev = find_first_mmc_device();
- if (dev < 0)
- return CMD_RET_FAILURE;
-
- setenv_ulong("mmc_first_dev", dev);
- return CMD_RET_SUCCESS;
-}
-
-U_BOOT_CMD(
- mmcsetn, 1, 1, do_mmcsetn,
- "Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
- ""
-);
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include "../sbc/sbc-regs.h"
-#include "../soc-info.h"
-#include "boot-device.h"
-
-static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
-
- switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
- case UNIPHIER_SLD3_ID:
- uniphier_sld3_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \
- defined(CONFIG_ARCH_UNIPHIER_SLD8)
- case UNIPHIER_LD4_ID:
- case UNIPHIER_PRO4_ID:
- case UNIPHIER_SLD8_ID:
- uniphier_ld4_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
- case UNIPHIER_PRO5_ID:
- uniphier_pro5_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
- case UNIPHIER_PXS2_ID:
- case UNIPHIER_LD6B_ID:
- uniphier_pxs2_boot_mode_show();
- break;
-#endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
- case UNIPHIER_LD11_ID:
- case UNIPHIER_LD20_ID:
- uniphier_ld20_boot_mode_show();
- break;
-#endif
- default:
- break;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- pinmon, 1, 1, do_pinmon,
- "pin monitor",
- ""
-);
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-#include <asm/processor.h>
-
-#include "../soc-info.h"
-
-struct uniphier_romfunc_table {
- void *mmc_send_cmd;
- void *mmc_card_blockaddr;
- void *mmc_switch_part;
- void *mmc_load_image;
-};
-
-static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = {
- .mmc_send_cmd = (void *)0x20d8,
- .mmc_card_blockaddr = (void *)0x1b68,
- .mmc_switch_part = (void *)0x1c38,
- .mmc_load_image = (void *)0x2e48,
-};
-
-static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = {
- .mmc_send_cmd = (void *)0x2130,
- .mmc_card_blockaddr = (void *)0x1ba0,
- .mmc_switch_part = (void *)0x1c70,
- .mmc_load_image = (void *)0x2ef0,
-};
-
-int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32),
- int (**card_blockaddr)(u32),
- int (**switch_part)(int),
- int (**load_image)(u32, uintptr_t, u32))
-{
- const struct uniphier_romfunc_table *table;
-
- switch (uniphier_get_soc_id()) {
- case UNIPHIER_LD11_ID:
- table = &uniphier_ld11_romfunc_table;
- break;
- case UNIPHIER_LD20_ID:
- table = &uniphier_ld20_romfunc_table;
- break;
- default:
- printf("unsupported SoC\n");
- return -EINVAL;
- }
-
- *send_cmd = table->mmc_send_cmd;
- *card_blockaddr = table->mmc_card_blockaddr;
- *switch_part = table->mmc_switch_part;
- *load_image = table->mmc_load_image;
-
- return 0;
-}
-
-static int spl_board_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
-{
- int (*send_cmd)(u32 cmd, u32 arg);
- int (*card_blockaddr)(u32 rca);
- int (*switch_part)(int part);
- int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt);
- u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
- const u32 rca = 0x1000; /* RCA assigned by Boot ROM */
- int ret;
-
- ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr,
- &switch_part, &load_image);
- if (ret)
- return ret;
-
- /*
- * deselect card before SEND_CSD command.
- * Do not check the return code. It fails, but it is OK.
- */
- (*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */
-
- /* reset CMD Line */
- writeb(0x6, 0x5a00022f);
- while (readb(0x5a00022f))
- cpu_relax();
-
- ret = (*card_blockaddr)(rca);
- if (ret) {
- debug("card is block addressing\n");
- } else {
- debug("card is byte addressing\n");
- dev_addr *= 512;
- }
-
- ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */
- if (ret)
- printf("failed to select card\n");
-
- ret = (*switch_part)(1); /* Switch to Boot Partition 1 */
- if (ret)
- printf("failed to switch partition\n");
-
- ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1);
- if (ret) {
- printf("failed to load image\n");
- return ret;
- }
-
- ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
- if (ret)
- return ret;
-
- ret = (*load_image)(dev_addr, spl_image->load_addr,
- spl_image->size / 512);
- if (ret) {
- printf("failed to load image\n");
- return ret;
- }
-
- return 0;
-}
-SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-pxs3.o
endif
#include <linux/bitops.h>
#include <linux/io.h>
-#include "../boot-mode/boot-device.h"
#include "../init.h"
#include "../sc64-regs.h"
#include "../sg-regs.h"
+#define SDCTRL_EMMC_HW_RESET 0x59810280
+
void uniphier_ld11_clk_init(void)
{
/* if booted from a device other than USB, without stand-by MPU */
if ((readl(SG_PINMON0) & BIT(27)) &&
- spl_boot_device_raw() != BOOT_DEVICE_USB) {
+ uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
writel(1, SG_ETPHYPSHUT);
writel(1, SG_ETPHYCNT);
writel(7, SG_ETPHYCNT);
}
+ /* TODO: use "mmc-pwrseq-emmc" */
+ writel(1, SDCTRL_EMMC_HW_RESET);
+
#ifdef CONFIG_USB_EHCI
{
/* FIXME: the current clk driver can not handle parents */
--- /dev/null
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+
+#define SDCTRL_EMMC_HW_RESET 0x59810280
+
+void uniphier_ld20_clk_init(void)
+{
+ /* TODO: use "mmc-pwrseq-emmc" */
+ writel(1, SDCTRL_EMMC_HW_RESET);
+}
#define SC_PLLCTRL_SSC_EN BIT(31)
#define SC_PLLCTRL2_NRSTDS BIT(28)
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
+#define SC_PLLCTRL3_REGI_SHIFT 16
+#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
/* PLL type: VPLL27 */
#define SC_VPLL27CTRL_WP BIT(0)
return 0;
}
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
+{
+ void __iomem *base;
+ u32 tmp;
+
+ base = ioremap(reg_base, SZ_16);
+ if (!base)
+ return -ENOMEM;
+
+ tmp = readl(base + 8); /* SSCPLLCTRL */
+ tmp &= ~SC_PLLCTRL3_REGI_MASK;
+ tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+ writel(tmp, base + 8);
+
+ iounmap(base);
+
+ return 0;
+}
+
int uniphier_ld20_vpll27_init(unsigned long reg_base)
{
void __iomem *base;
uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */
uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
+
mdelay(1);
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
unsigned int ssc_rate, unsigned int divn);
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
+int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
int uniphier_ld20_vpll27_init(unsigned long reg_base);
int uniphier_ld20_dspll_init(unsigned long reg_base);
ddrphy_init(phy_base, freq);
- for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
/*
* Copyright (C) 2016-2017 Socionext Inc.
*
- * based on commit e732175d0b0dbc2a3855cb8ac791c538666b6fd4 of Diag
+ * based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
phy_base + PHY_LANE_SEL);
}
+#define DDRPHY_EFUSEMON (void *)0x5f900118
+
static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
{
writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
cpu_relax();
- writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+
+ if (readl(DDRPHY_EFUSEMON) & BIT(ch))
+ writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+ else
+ writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
return -EINVAL;
}
- for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
- ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
- bd->dram_freq, size / (width / 16), ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
+ if (size) {
+ ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
+ bd->dram_freq, size / (width / 16),
+ ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
}
umc_ch_base += 0x00200000;
return -EINVAL;
}
- for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+ for (ch = 0; ch < DRAM_CH_NR; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
- ret = umc_ch_init(umc_ch_base, freq, size / (width / 16),
- width, ch);
- if (ret) {
- pr_err("failed to initialize UMC ch%d\n", ch);
- return ret;
+ if (size) {
+ ret = umc_ch_init(umc_ch_base, freq,
+ size / (width / 16), width, ch);
+ if (ret) {
+ pr_err("failed to initialize UMC ch%d\n", ch);
+ return ret;
+ }
}
umc_ch_base += 0x00200000;
#include <linux/errno.h>
#include <linux/sizes.h>
-#include "init.h"
#include "sg-regs.h"
#include "soc-info.h"
+#define pr_warn(fmt, args...) printf(fmt, ##args)
+#define pr_err(fmt, args...) printf(fmt, ##args)
+
DECLARE_GLOBAL_DATA_PTR;
struct uniphier_memif_data {
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
-static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
+struct uniphier_dram_map {
+ unsigned long base;
+ unsigned long size;
+};
+
+static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
{
const struct uniphier_memif_data *data;
unsigned long size;
val = readl(SG_MEMCONF);
/* set up ch0 */
- dram_ch[0].base = CONFIG_SYS_SDRAM_BASE;
+ dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
switch (val & SG_MEMCONF_CH0_SZ_MASK) {
case SG_MEMCONF_CH0_SZ_64M:
size = SZ_1G;
break;
default:
- pr_err("error: invald value is set to MEMCONF ch0 size\n");
+ pr_err("error: invalid value is set to MEMCONF ch0 size\n");
return -EINVAL;
}
if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
size *= 2;
- dram_ch[0].size = size;
+ dram_map[0].size = size;
/* set up ch1 */
- dram_ch[1].base = dram_ch[0].base + size;
+ dram_map[1].base = dram_map[0].base + size;
if (val & SG_MEMCONF_SPARSEMEM) {
- if (dram_ch[1].base > data->sparse_ch1_base) {
+ if (dram_map[1].base > data->sparse_ch1_base) {
pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
pr_warn("Only ch0 is available\n");
- dram_ch[1].base = 0;
+ dram_map[1].base = 0;
return 0;
}
- dram_ch[1].base = data->sparse_ch1_base;
+ dram_map[1].base = data->sparse_ch1_base;
}
switch (val & SG_MEMCONF_CH1_SZ_MASK) {
size = SZ_1G;
break;
default:
- pr_err("error: invald value is set to MEMCONF ch1 size\n");
+ pr_err("error: invalid value is set to MEMCONF ch1 size\n");
return -EINVAL;
}
if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
size *= 2;
- dram_ch[1].size = size;
+ dram_map[1].size = size;
- if (!data->have_ch2)
+ if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
return 0;
/* set up ch2 */
- dram_ch[2].base = dram_ch[1].base + size;
+ dram_map[2].base = dram_map[1].base + size;
switch (val & SG_MEMCONF_CH2_SZ_MASK) {
case SG_MEMCONF_CH2_SZ_64M:
size = SZ_1G;
break;
default:
- pr_err("error: invald value is set to MEMCONF ch2 size\n");
+ pr_err("error: invalid value is set to MEMCONF ch2 size\n");
return -EINVAL;
}
if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
size *= 2;
- dram_ch[2].size = size;
+ dram_map[2].size = size;
return 0;
}
int dram_init(void)
{
- struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
+ struct uniphier_dram_map dram_map[3] = {};
int ret, i;
gd->ram_size = 0;
- ret = uniphier_memconf_decode(dram_ch);
+ ret = uniphier_memconf_decode(dram_map);
if (ret)
return ret;
- for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
+ for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
- if (!dram_ch[i].size)
+ if (!dram_map[i].size)
break;
/*
* but it does not expect sparse memory. We use the first
* contiguous chunk here.
*/
- if (i > 0 &&
- dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base)
+ if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
+ dram_map[i].base)
break;
- gd->ram_size += dram_ch[i].size;
+ gd->ram_size += dram_map[i].size;
}
return 0;
void dram_init_banksize(void)
{
- struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
+ struct uniphier_dram_map dram_map[3] = {};
int i;
- uniphier_memconf_decode(dram_ch);
+ uniphier_memconf_decode(dram_map);
- for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
+ for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
if (i >= ARRAY_SIZE(gd->bd->bi_dram))
break;
- gd->bd->bi_dram[i].start = dram_ch[i].base;
- gd->bd->bi_dram[i].size = dram_ch[i].size;
+ gd->bd->bi_dram[i].start = dram_map[i].base;
+ gd->bd->bi_dram[i].size = dram_map[i].size;
}
}
return 0;
for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
+ if (!gd->bd->bi_dram[i].size)
+ continue;
+
rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
rsv_addr -= rsv_size;
#define UNIPHIER_MAX_NR_DRAM_CH 3
struct uniphier_dram_ch {
- unsigned long base;
unsigned long size;
unsigned int width;
};
struct uniphier_board_data {
unsigned int dram_freq;
- unsigned int dram_nr_ch;
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
-#define UNIPHIER_BD_DDR3PLUS BIT(2)
+#define UNIPHIER_BD_DRAM_SPARSE BIT(9)
+#define UNIPHIER_BD_DDR3PLUS BIT(8)
#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
void uniphier_pro5_clk_init(void);
void uniphier_pxs2_clk_init(void);
void uniphier_ld11_clk_init(void);
+void uniphier_ld20_clk_init(void);
+unsigned int uniphier_boot_device_raw(void);
int uniphier_pin_init(const char *pinconfig_name);
void uniphier_smp_kick_all_cpus(void);
void cci500_init(int nr_slaves);
+#undef pr_warn
#define pr_warn(fmt, args...) printf(fmt, ##args)
+#undef pr_err
#define pr_err(fmt, args...) printf(fmt, ##args)
#endif /* __MACH_INIT_H */
}
/* is sparse mem? */
- if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
+ if (bd->flags & UNIPHIER_BD_DRAM_SPARSE)
val |= SG_MEMCONF_SPARSEMEM;
if (!have_ch2)
revision &= 0xff;
/* revision 3.6.x card changed the revision format */
- printf("(CPLD version %s%d.%d)\n", revision >> 4 == 6 ? "3." : "",
+ printf("SC: Micro Support Card (CPLD version %s%d.%d)\n",
+ revision >> 4 == 6 ? "3." : "",
revision >> 4, revision & 0xf);
return 0;
}
-int checkboard(void)
-{
- printf("SC: Micro Support Card ");
- return support_card_show_revision();
-}
-
void support_card_init(void)
{
support_card_reset();
*/
udelay(200);
support_card_reset_deassert();
+
+ support_card_show_revision();
}
#if defined(CONFIG_SMC911X)
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <spl.h>
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ struct mmc *mmc;
+
+ /*
+ * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8:
+ *
+ * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
+ * Extended CSD register; when switching to the Boot Partition 1, the
+ * Boot ROM should issue the SWITCH command (CMD6) with Set Bits for
+ * the Access Bits, but in fact it uses Write Byte for the Access Bits.
+ * As a result, the BOOT_PARTITION_ENABLE field of the PARTITION_CONFIG
+ * is lost. This bug was fixed for PH1-Pro5 and later SoCs.
+ *
+ * Fixup mmc->part_config here because it is used to determine the
+ * partition which the U-Boot image is read from.
+ */
+ mmc = find_mmc_device(0);
+ mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK);
+ mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE;
+
+ return MMCSD_MODE_EMMCBOOT;
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <linux/errno.h>
+
+static int find_first_mmc_device(void)
+{
+ struct mmc *mmc;
+ int i;
+
+ for (i = 0; (mmc = find_mmc_device(i)); i++) {
+ if (!mmc_init(mmc) && IS_MMC(mmc))
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int mmc_get_env_dev(void)
+{
+ return find_first_mmc_device();
+}
+
+static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int dev;
+
+ dev = find_first_mmc_device();
+ if (dev < 0)
+ return CMD_RET_FAILURE;
+
+ setenv_ulong("mmc_first_dev", dev);
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ mmcsetn, 1, 1, do_mmcsetn,
+ "Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
+ ""
+);
pr_err("failed to init DRAM\n");
hang();
}
+
+#ifdef CONFIG_ARM64
+ dcache_disable();
+#endif
}
#define CONFIG_CMD_BLOB
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_RSA_FREESCALE_EXP
-
-#ifndef CONFIG_FSL_CAAM
-#define CONFIG_FSL_CAAM
-#endif
#ifndef CONFIG_SPL_BUILD
/*
endchoice
+# subarchitectures-specific options below
+config INTEL_MID
+ bool "Intel MID platform support"
+ help
+ Select to build a U-Boot capable of supporting Intel MID
+ (Mobile Internet Device) platform systems which do not have
+ the PCI legacy interfaces.
+
+ If you are building for a PC class system say N here.
+
+ Intel MID platforms are based on an Intel processor and
+ chipset which consume less power than most of the x86
+ derivatives.
+
# board-specific options below
source "board/advantech/Kconfig"
source "board/congatec/Kconfig"
".type irq_"#x", @function\n" \
"irq_"#x":\n" \
"pushl $"#x"\n" \
- "jmp irq_common_entry\n"
+ "jmp.d32 irq_common_entry\n"
static char *exceptions[] = {
"Divide Error",
if (!stack)
return -ENOMEM;
params->stack_top = (u32)(stack + size);
-#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
+ !defined(CONFIG_INTEL_MID)
params->microcode_ptr = ucode_base;
debug("Microcode at %x\n", params->microcode_ptr);
#endif
hdr->setup_move_size = 0x9100;
}
+#if defined(CONFIG_INTEL_MID)
+ hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
+#endif
+
/* build command line at COMMAND_LINE_OFFSET */
build_command_line(cmd_line, auto_boot);
}
U-Boot > tftp u-boot.ais
U-Boot > sf write c0700000 0 $filesize
+Flashing the images to MMC
+==========================
+If the boot pins are set to boot from mmc, the RBL will try to load the
+next boot stage form the first couple of sectors of an external mmc card.
+As sector 0 is usually used for storing the partition information, the
+AIS image should be written at least after the first sector, but before the
+first partition begins. (e.g: make sure to leave at least 500KB of unallocated
+space at the start of the mmc when creating the partitions)
+
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is used by SPL, and should
+point to the sector were the u-boot image is located. (eg. After SPL)
+
+There are 2 ways to copy the AIS image to the mmc card:
+
+ 1 - Using the TI tool "uflash"
+ $ uflash -d /dev/mmcblk0 -b ./u-boot.ais -p OMAPL138 -vv
+
+ 2 - using the "dd" command
+ $ dd if=u-boot.ais of=/dev/mmcblk0 seek=117 bs=512 conv=fsync
+
+uflash writes the AIS image at offset 117. For compatibility with uflash,
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this
+offset, and the dd command is adjusted accordingly.
Recovery
========
config CHAIN_OF_TRUST
depends on !FIT_SIGNATURE && SECURE_BOOT
+ select FSL_CAAM
bool
default y
return vdd_last;
}
+#ifdef CONFIG_FSL_LSCH3
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
-#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid, buf;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 10500,
+ 0, /* reserved */
+ 9750,
+ 0, /* reserved */
+ 9500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 0, /* reserved */
+ 10250,
+ 0, /* reserved */
+ 10500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* check IR chip work on Intel mode*/
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_le32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
+ /* Check vdd_target is in valid range */
+ printf("VID: Target VID %d mV is not in range.\n",
+ vdd_target);
+ ret = -1;
+ goto exit;
+ } else {
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+ return ret;
+}
+#else /* !CONFIG_FSL_LSCH3 */
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
}
/* get the voltage ID from fuse status register */
-#ifdef CONFIG_FSL_LSCH3
- fusesr = in_le32(&gur->dcfg_fusesr);
-#else
fusesr = in_be32(&gur->dcfg_fusesr);
-#endif
/*
* VID is used according to the table below
* ---------------------------------------
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
}
-#elif defined(CONFIG_FSL_LSCH3)
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
- }
#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
return ret;
}
+#endif
static int print_vdd(void)
{
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <environment.h>
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
return 0;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
return 0;
}
#endif
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
return 0;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* This will break-before-make MMU for DDR */
+ update_early_mmu_table();
+#endif
return 0;
}
return dram_size;
}
-
-void dram_init_banksize(void)
-{
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-}
return 0;
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return dram_size;
}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- if (soc_has_dp_ddr()) {
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
- }
-#endif
-}
#endif
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
fdt_fixup_memory_banks(blob, base, size, 2);
#ifdef CONFIG_FSL_MC_ENET
return dram_size;
}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- if (soc_has_dp_ddr()) {
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
- }
-#endif
-}
#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
+#include "../common/vid.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
return 0;
}
+int misc_init_r(void)
+{
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
+ return 0;
+}
+
void detail_board_ddr_info(void)
{
puts("\nDDR ");
#endif
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
fdt_fixup_memory_banks(blob, base, size, 2);
fsl_fdt_fixup_dr_usb(blob, bd);
return dram_size;
}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- /*
- * gd->arch.secure_ram tracks the location of secure memory.
- * It was set as if the memory starts from 0.
- * The address needs to add the offset of its bank.
- */
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[1].start +
- gd->arch.secure_ram -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- gd->arch.secure_ram = gd->bd->bi_dram[0].start +
- gd->arch.secure_ram;
- gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- if (soc_has_dp_ddr()) {
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
- }
-#endif
-}
#include <environment.h>
#include <efi_loader.h>
#include <i2c.h>
+#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <fsl_sec.h>
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
-#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
- if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
- efi_add_memory_map(gd->bd->bi_dram[2].start,
- gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
- EFI_RESERVED_MEMORY_TYPE, false);
- }
-#endif
-
return 0;
}
#endif
}
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
base[1] = gd->bd->bi_dram[1].start;
size[1] = gd->bd->bi_dram[1].size;
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+#endif
+
fdt_fixup_memory_banks(blob, base, size, 2);
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
+static int ft_enable_by_compatible(void *blob, char *compat, int enable)
+{
+ int off = fdt_node_offset_by_compatible(blob, -1, compat);
+ if (off < 0)
+ return off;
+
+ if (enable)
+ fdt_status_okay(blob, off);
+ else
+ fdt_status_disabled(blob, off);
+
+ return 0;
+}
+
int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
+ ft_enable_by_compatible(blob, "ti,omap2-nand",
+ gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
+ ft_enable_by_compatible(blob, "ti,omap2-onenand",
+ gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
+
return 0;
}
#endif
--- /dev/null
+if TARGET_STIH410_B2260
+
+config SYS_BOARD
+ string
+ default "stih410-b2260"
+
+config SYS_VENDOR
+ string
+ default "st"
+
+config SYS_SOC
+ string
+ default "stih410"
+
+config SYS_CONFIG_NAME
+ string
+ default "stih410-b2260"
+
+endif
--- /dev/null
+STIH410-B2260 BOARD
+M: Patrice Chotard <patrice.chotard@st.com>
+S: Maintained
+F: board/st/stih410-b2260/
+F: include/configs/stih410-b2260.h
+F: configs/stih410-b2260_defconfig
+F: arch/arm/dts/stih*
--- /dev/null
+#
+# (C) Copyright 2017
+# Patrice Chotard, <patrice.chotard@st.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = board.o
--- /dev/null
+/*
+ * Board init file for STiH410-B2260
+ *
+ * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+int board_init(void)
+{
+ return 0;
+}
if TARGET_AM335X_EVM
-config SPL_ENV_SUPPORT
- default y
-
-config SPL_WATCHDOG_SUPPORT
- default y
-
-config SPL_YMODEM_SUPPORT
- default y
-
config SYS_BOARD
default "am335x"
palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
val);
+ omap_die_id_serial();
+
return 0;
}
-config SPL_ENV_SUPPORT
- default y
-
config TI_I2C_BOARD_DETECT
bool "Support for Board detection for TI platforms"
help
Support for detection board information on Texas Instrument's
Evaluation Boards which have I2C based EEPROM detection
-
-config SPL_EXT_SUPPORT
- default y
-
-config SPL_FAT_SUPPORT
- default y
-
-config SPL_GPIO_SUPPORT
- default y
-
-config SPL_I2C_SUPPORT
- default y
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC_SUPPORT
- default y
-
-config SPL_NAND_SUPPORT
- default y
-
-config SPL_POWER_SUPPORT
- default y
-
-config SPL_SERIAL_SUPPORT
- default y
gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
}
#endif
+#ifdef CONFIG_RESV_RAM
+ if (gd->arch.resv_ram)
+ print_num("Reserved ram", gd->arch.resv_ram);
+#endif
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
print_eths();
#endif
#include <image.h>
#include <lmb.h>
#include <mapmem.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
uint32_t code1; /* Executable code */
uint64_t text_offset; /* Image load offset, LE */
uint64_t image_size; /* Effective Image size, LE */
- uint64_t res1; /* reserved */
+ uint64_t flags; /* Kernel flags, LE */
uint64_t res2; /* reserved */
uint64_t res3; /* reserved */
uint64_t res4; /* reserved */
{
struct Image_header *ih;
uint64_t dst;
- uint64_t image_size;
+ uint64_t image_size, text_offset;
ih = (struct Image_header *)map_sysmem(images->ep, 0);
puts("Bad Linux ARM64 Image magic!\n");
return 1;
}
-
+
+ /*
+ * Prior to Linux commit a2c1d73b94ed, the text_offset field
+ * is of unknown endianness. In these cases, the image_size
+ * field is zero, and we can assume a fixed value of 0x80000.
+ */
if (ih->image_size == 0) {
puts("Image lacks image_size field, assuming 16MiB\n");
image_size = 16 << 20;
+ text_offset = 0x80000;
} else {
image_size = le64_to_cpu(ih->image_size);
+ text_offset = le64_to_cpu(ih->text_offset);
}
/*
- * If we are not at the correct run-time location, set the new
- * correct location and then move the image there.
+ * If bit 3 of the flags field is set, the 2MB aligned base of the
+ * kernel image can be anywhere in physical memory, so respect
+ * images->ep. Otherwise, relocate the image to the base of RAM
+ * since memory below it is not accessible via the linear mapping.
*/
- dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
+ if (le64_to_cpu(ih->flags) & BIT(3))
+ dst = images->ep - text_offset;
+ else
+ dst = gd->bd->bi_dram[0].start;
+
+ dst = ALIGN(dst, SZ_2M) + text_offset;
unmap_sysmem(ih);
return gd->ram_top;
}
-__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size)
-{
-#ifdef CONFIG_SYS_MEM_TOP_HIDE
- return ram_size - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return ram_size;
-#endif
-}
-
static int setup_dest_addr(void)
{
debug("Monitor len: %08lX\n", gd->mon_len);
* Ram is setup, size stored in gd !!
*/
debug("Ram size: %08lX\n", (ulong)gd->ram_size);
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- /* Reserve memory for secure MMU tables, and/or security monitor */
- gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
- /*
- * Record secure memory location. Need recalcuate if memory splits
- * into banks, or the ram base is not zero.
- */
- gd->arch.secure_ram = gd->ram_size;
-#endif
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
/*
* Subtract specified amount of memory to hide so that it won't
* get "touched" at all by U-Boot. By fixing up gd->ram_size
* the Linux kernel should now get passed the now "corrected"
- * memory size and won't touch it either. This has been used
- * by arch/powerpc exclusively. Now ARMv8 takes advantage of
- * thie mechanism. If memory is split into banks, addresses
- * need to be calculated.
+ * memory size and won't touch it either. This should work
+ * for arch/ppc and arch/powerpc. Only Linux board ports in
+ * arch/powerpc with bootwrapper support, that recalculate the
+ * memory size from the SDRAM controller setup will have to
+ * get fixed.
*/
- gd->ram_size = board_reserve_ram_top(gd->ram_size);
-
+ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
+#endif
#ifdef CONFIG_SYS_SDRAM_BASE
gd->ram_top = CONFIG_SYS_SDRAM_BASE;
#endif
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ bool "MMC Raw mode: by partition"
+ depends on SPL
+ help
+ Use a partition for loading U-Boot when using MMC/SD in raw mode.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+ hex "Partition to use to load U-Boot from"
+ depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ default 1
+ help
+ Partition on the MMC to load U-Boot from when the MMC is being
+ used in raw mode
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ bool "MMC raw mode: by partition type"
+ depends on SPL && DOS_PARTITION && \
+ SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ help
+ Use partition type for specifying U-Boot partition on MMC/SD in
+ raw mode. U-Boot will be loaded from the first partition of this
+ type to be found.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
+ hex "Partition Type on the MMC to load U-Boot from"
+ depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ help
+ Partition Type on the MMC to load U-Boot from, when the MMC is being
+ used in raw mode.
+
config TPL
bool
depends on SPL && SUPPORT_TPL
return 0;
}
-#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
struct mmc *mmc, int partition)
{
disk_partition_t info;
int err;
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ int type_part;
+ /* Only support MBR so DOS_ENTRY_NUMBERS */
+ for (type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
+ err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+ if (err)
+ continue;
+ if (info.sys_ind ==
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) {
+ partition = type_part;
+ break;
+ }
+ }
+#endif
+
err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
if (err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
return mmc_load_image_raw_sector(spl_image, mmc, info.start);
#endif
}
-#else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -1
-static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
- struct mmc *mmc, int partition)
-{
- return -ENOSYS;
-}
#endif
#ifdef CONFIG_SPL_OS_BOOT
if (!err)
return err;
}
-
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
err = mmc_load_image_raw_partition(spl_image, mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
if (!err)
return err;
+#endif
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
err = mmc_load_image_raw_sector(spl_image, mmc,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
{
int res = 0;
loff_t bmp_size;
+ loff_t actread;
char *splash_file;
splash_file = getenv("splashfile");
}
splash_select_fs_dev(location);
- res = fs_read(splash_file, bmp_load_addr, 0, 0, NULL);
+ res = fs_read(splash_file, bmp_load_addr, 0, 0, &actread);
out:
if (location->ubivol != NULL)
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DFU_RAM=y
-CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPC(3)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_RTL8211X_PHY_FORCE_MASTER=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO3_VOLT=2800
CONFIG_AXP_ALDO4_VOLT=2800
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4420QDS=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_PCI is not set
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_PCI is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_PCI is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9131RDB=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_PCI is not set
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_FSL_ESPI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_DOS_PARTITION=y
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-# CONFIG_MMC is not set
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DFU_RAM=y
+# CONFIG_MMC is not set
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CPCI2DP=y
CONFIG_BOOTDELAY=3
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CPCI4052=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPH(12)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_EMR1=4
CONFIG_USB0_VBUS_PIN="PB09"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPB(8)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),SATAPWR=SUNXI_GPB(3)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,SATAPWR=SUNXI_GPH(2)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,SATAPWR=SUNXI_GPH(2)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5208EVBE=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M5208EVBE=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
-CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_TEXT_BASE=0x43E00000
+CONFIG_TARGET_M52277EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_TEXT_BASE=0xFFC00000
+CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5235EVB=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_M5235EVB=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_TARGET_M5249EVB=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_AUTOBOOT is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5253DEMO=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5253DEMO=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5253EVBE=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_M5253EVBE=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5272C3=y
CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_TARGET_M5272C3=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5275EVB=y
CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_TARGET_M5275EVB=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5282EVB=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_TARGET_M5282EVB=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M53017EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M53017EVB=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M5329EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M5373EVB=y
CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16"
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_M68K=y
-CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_M68K=y
-CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_M68K=y
-CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_M68K=y
-CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_M68K=y
-CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_M68K=y
-CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_M54418TWR=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_M68K=y
-CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_TEXT_BASE=0x47e00000
+CONFIG_TARGET_M54451EVB=y
CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
CONFIG_BOOTDELAY=1
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
-CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
-CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
-CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
-CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_TEXT_BASE=0x4FE00000
+CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
# CONFIG_CMD_LOADB is not set
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5475EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_M68K=y
-CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
CONFIG_PPC=y
CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10082-001 released"
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_MIP405T=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_PPC=y
CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10072-001 released"
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8313ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8315ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8323ERDB=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349ITX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8540ADS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8544DS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_PHYS_64BIT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8560ADS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8568MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_FSL_DDR2=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_FSL_DDR2=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8610HPCD=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=122
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_DRAM_ODT_EN=y
-# CONFIG_MMC is not set
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
+# CONFIG_MMC is not set
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_ELDO2_VOLT=1800
CONFIG_USB_MUSB_GADGET=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2D300=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2DNT2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2DNT2=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2D=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2I=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O2MNT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_O3DNT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PH26"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_PHYS_64BIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_PHYS_64BIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020UTM=y
CONFIG_PHYS_64BIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1020UTM=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_PHYS_64BIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_P1023RDB=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10084-001 released"
-# CONFIG_MMC is not set
CONFIG_5xx=y
CONFIG_TARGET_PATI=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_PPC=y
CONFIG_IDENT_STRING="\n(c) 2002 by MPL AG Switzerland, MEV-10066-001 released"
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_PIP405=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_PLU405=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_MAC_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_PMC405DE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_PMC440=y
CONFIG_OF_BOARD_SETUP=y
+CONFIG_API=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
-CONFIG_API=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
CONFIG_SPL=y
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB_PI=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_LCD=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TQM834X=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM850L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM850M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM855L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM855M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM860L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM860M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM862L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM862M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM866M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM885D=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_VOM405=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_VGA=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_A3M071=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_OS_BASE=0xfc200000
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_LIB_RAND=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_A4M072=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_A3M071=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_OS_BASE=0xfc200000
CONFIG_CMD_LINK_LOCAL=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_LIB_RAND=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_AC14XX=y
CONFIG_FIT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_ACADIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_PING=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_NDS32=y
-CONFIG_MMC=y
CONFIG_TARGET_ADP_AG101P=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_BALTOS=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_BALTOS=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_AM33XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_ARM=y
CONFIG_AM33XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_RSA=y
CONFIG_SPL_OF_LIBFDT=y
-CONFIG_PHY_MSCC=y
CONFIG_ARM=y
CONFIG_AM33XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ARM=y
CONFIG_AM33XX=y
CONFIG_TI_SECURE_DEVICE=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM335X_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_STACK_R_ADDR=0x82000000
-# CONFIG_SPL_YMODEM_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_SPL_YMODEM_SUPPORT is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm"
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_NAND=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_IGEP0033=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_IGEP0033=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_ICT=y
CONFIG_SERIES=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_NETBOOT=y
CONFIG_SERIES=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SERIES=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_AUTOBOOT_DELAY_STR="shc"
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SHC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SHC_SDBOOT=y
CONFIG_SERIES=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_AM335X_SL50=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_TARGET_AM335X_SL50=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_AM3517_CRANE=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AM3517_CRANE # "
# CONFIG_CMD_IMI is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_AM3517_EVM=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AM3517_EVM # "
CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_ARM=y
CONFIG_AM43XX=y
CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x40300350
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x403018e0
CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_FIT=y
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM57XX_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM57XX_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
CONFIG_TI_SECURE_DEVICE=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_M68K=y
+CONFIG_SYS_TEXT_BASE=0xffc00000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_TARGET_AMCORE=y
-CONFIG_SYS_TEXT_BASE=0xffc00000
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Apalis iMX6 # "
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
CONFIG_TARGET_APF27=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_IDENT_STRING=" apf27 patch 3.10"
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_ARCHES=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_ARIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_TARGET_ARMADILLO_800EVA=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_BDI is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
+# CONFIG_MMC is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_ASPENITE=y
CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91RM9200EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
CONFIG_BOOTDELAY=3
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9261EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_AT91SAM9260EK=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_AVR32=y
-CONFIG_MMC=y
CONFIG_TARGET_ATNGW100=y
CONFIG_BOOTDELAY=1
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_AVR32=y
-CONFIG_MMC=y
CONFIG_TARGET_ATNGW100MKII=y
CONFIG_BOOTDELAY=1
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MII=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_AVR32=y
-CONFIG_MMC=y
CONFIG_TARGET_ATSTK1002=y
CONFIG_BOOTDELAY=1
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
CONFIG_BOOTDELAY=3
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_ARC=y
CONFIG_SYS_DCACHE_OFF=y
-CONFIG_SYS_CLK_FREQ=750000000
-CONFIG_MMC=y
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=750000000
CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_SYS_I2C_DW=y
+CONFIG_MMC=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
-CONFIG_SYS_CLK_FREQ=100000000
-CONFIG_MMC=y
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=100000000
CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_SYS_I2C_DW=y
+CONFIG_MMC=y
CONFIG_MMC_DW=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_EMR1=4
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_BAMBOO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_BCMCYGNUS=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_BCMNSP=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_BF518F_EZBRD=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_BF527_AD7160_EVAL=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_BF537_STAMP=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_BF548_EZKIT=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_BF609_EZKIT=y
CONFIG_SILENT_CONSOLE=y
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_BAV335X=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_BAV335X=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_BAV335X=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_BAV335X=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_BOOTDELAY=-2
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_BOOTDELAY=-2
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
CONFIG_SPI_BOOT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=-2
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_BUBINGA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_CALIMAIN=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=0
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_CANMB=y
CONFIG_BOOTDELAY=5
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_CANYONLANDS=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_CGTQMX6EVAL=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > "
CONFIG_CMD_BOOTZ=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_CHARON=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_AM33XX=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_CHILIBOARD=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_CHILIBOARD=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ROCKCHIP_RK3288=y
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBIT_MICKEY=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ROCKCHIP_RK3288=y
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_JERRY=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI_SUPPORT=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_SPL_TIMER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_VIDEO=y
CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
-# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_VIDEO=y
CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_ROCKCHIP_RK3288=y
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_TARGET_CHROMEBOOK_MINNIE=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_CL_SOM_AM57X=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CLEARFOG=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_CM_BF537E=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_CM_BF537U=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_CM5200=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_CM_FX6=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-FX6 # "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_CM_T335=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_CM_T335=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T335 # "
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_CM_T35=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_CM_T43=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T43 # "
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_CM_T54=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_M68K=y
-CONFIG_TARGET_COBRA5272=y
CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_TARGET_COBRA5272=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="COBRA > "
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_COLIBRI_IMX6=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX6 # "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" D2 v2"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DA850EVM=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6720=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_MISC=y
+# CONFIG_MMC is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_DB_88F6820_AMC=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+# CONFIG_MMC is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_88F6820_GP=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_MV784MP_GP=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+# CONFIG_MMC is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" devconcenter 0.06"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_FIT=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_TARGET_DEVKIT3250=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_DIGSY_MTC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" dlvision-10g 0.06"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_DLVISION_10G=y
CONFIG_FIT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" dlvision 0.02"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_DLVISION=y
CONFIG_FIT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DNS325=y
CONFIG_IDENT_STRING="\nD-Link DNS-325"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DOCKSTAR=y
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="DockStar> "
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DRA7XX_EVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
CONFIG_OMAP54XX=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TI_SECURE_DEVICE=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_TI_SECURE_EMIF_REGION_START=0xbe000000
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI_MSM=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_MSM=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PM8916=y
CONFIG_MSM_SERIAL=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DS109=y
-# CONFIG_MMC is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_PING=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DS414=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SPL_OF_TRANSLATE=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_OMAP44XX=y
-# CONFIG_SPL_I2C_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_DUOVERO=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SYS_PROMPT="duovero # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_MMC_OMAP_HS=y
CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_M68K=y
+CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_VIDEO=y
CONFIG_TARGET_EB_CPU5282=y
-CONFIG_SYS_TEXT_BASE=0xFF000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
CONFIG_M68K=y
+CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_VIDEO=y
CONFIG_TARGET_EB_CPU5282=y
-CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
CONFIG_BOOTDELAY=5
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_ECO5PK=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_TARGET_EDB93XX=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+# CONFIG_DOS_PARTITION is not set
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=0
CONFIG_LED_STATUS_RED=1
CONFIG_LED_STATUS_GREEN_ENABLE=y
CONFIG_LED_STATUS_GREEN=0
-# CONFIG_DOS_PARTITION is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ORION5X=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_EDMINIV2=y
+CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_IDENT_STRING=" EDMiniV2"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARCH_EXYNOS7=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" for ESPRESSO7420"
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_ARCH_ASPEED=y
CONFIG_ASPEED_AST2500=y
CONFIG_TARGET_EVB_AST2500=y
-CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_DISPLAY_CPUINFO=n
-CONFIG_SYS_NS16550=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
+CONFIG_PRE_CON_BUF_ADDR=0x1e720000
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_IMLS is not set
+CONFIG_REGMAP=y
+CONFIG_CLK=y
+CONFIG_RAM=y
CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
-CONFIG_CLK=y
CONFIG_TIMER=y
-CONFIG_RAM=y
-CONFIG_REGMAP=y
-CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_PRE_CON_BUF_ADDR=0x1e720000
-CONFIG_PRE_CON_BUF_SZ=4096
-CONFIG_SYS_NO_FLASH=y
-CONFIG_CMD_IMLS=n
CONFIG_ROCKCHIP_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_ROCKCHIP_RK3399_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_ARM=y
CONFIG_TARGET_FLEA3=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_TQM5200=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_GDPPC440ETX=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_GLACIER=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_CANYONLANDS=y
CONFIG_GLACIER=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_TARGET_GPLUGD=y
CONFIG_IDENT_STRING="\nMarvell-gplugD"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPARC=y
-CONFIG_IDENT_STRING=" Gaisler LEON3 GR-CPCI-AX2000"
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_IDENT_STRING=" Gaisler LEON3 GR-CPCI-AX2000"
CONFIG_TARGET_GR_CPCI_AX2000=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_ELF is not set
CONFIG_SPARC=y
-CONFIG_IDENT_STRING=" Gaisler LEON3 EP2S60"
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_IDENT_STRING=" Gaisler LEON3 EP2S60"
CONFIG_TARGET_GR_EP2S60=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_ELF is not set
CONFIG_SPARC=y
-CONFIG_IDENT_STRING=" Gaisler LEON3 GR-XC3S-1500"
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_IDENT_STRING=" Gaisler LEON3 GR-XC3S-1500"
CONFIG_TARGET_GR_XC3S_1500=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_ELF is not set
CONFIG_SPARC=y
-CONFIG_IDENT_STRING=" Gaisler GRSIM"
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_IDENT_STRING=" Gaisler GRSIM"
CONFIG_TARGET_GRSIM=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_BOOTD is not set
CONFIG_SPARC=y
-CONFIG_IDENT_STRING=" Gaisler GRSIM LEON2"
CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_IDENT_STRING=" Gaisler GRSIM LEON2"
CONFIG_TARGET_GRSIM_LEON2=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_BOOTD is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_ARM=y
CONFIG_TARGET_H2200=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
+# CONFIG_MMC is not set
CONFIG_PXA_SERIAL=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_HIGHBANK=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=127
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_USB0_VBUS_PIN="PG12"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_ICON=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_CONSOLE_EXTRA_INFO=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_ICONNECT=y
CONFIG_IDENT_STRING=" Iomega iConnect"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="iconnect => "
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_IDS8313=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_ARM=y
CONFIG_TARGET_IMX31_PHYCORE=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="uboot> "
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
-CONFIG_CMD_UBI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE_RQS=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb"
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="icorem6qdl> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="icorem6qdl> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
-CONFIG_CMD_UBI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6Q_ICORE_RQS=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb"
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_GEAM=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="geam6ul> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_PROMPT="geam6ul> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
-CONFIG_CMD_UBI=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_I2C=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
# CONFIG_BLK is not set
+CONFIG_SYS_I2C_MXC=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_NAND_MXS=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
-CONFIG_SYS_I2C_MXC=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" IS v2"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_INKA4X0=y
CONFIG_BOOTDELAY=1
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM720T=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM920T=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM926EJ_S=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_CM946ES=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-AP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PCI=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM1136=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM920T=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM926EJ_S=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_CP=y
CONFIG_CM946ES=y
-# CONFIG_MMC is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Integrator-CP # "
CONFIG_CMD_ARMFLASH=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" intip 0.06"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_FIT=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" io64 0.02"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_IO64=y
CONFIG_FIT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" io 0.06"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_IO=y
CONFIG_FIT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" iocon 0.06"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_IOCON=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC5xxx=y
CONFIG_TARGET_IPEK01=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_USB0_VBUS_PIN="PB9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_JUPITER=y
CONFIG_BOOTDELAY=5
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2E_EVM=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="K2E EVM # "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2G_EVM=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2HK_EVM=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="K2HK EVM # "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_K2L_EVM=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="K2L EVM # "
CONFIG_CMD_BOOTZ=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_KATMAI=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_OMAP44XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_KC1=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="kc1 # "
CONFIG_CMD_BOOTZ=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_TARGET_KZM9G=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_PROMPT="KZM-A9-GT# "
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRDM=y
+CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
+CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
+CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_DOS_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_SYS_FSL_DDR3=y
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SECURE_BOOT=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
-CONFIG_OF_LIBFDT=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SECURE_BOOT=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_OF_CONTROL=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
-CONFIG_OF_LIBFDT=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_BOOTDELAY=0
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_CRYPTO_SUPPORT=y
CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
-CONFIG_OF_LIBFDT=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_CONTROL=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080A_EMU=y
CONFIG_IDENT_STRING=" LS2080A-EMU"
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-# CONFIG_PARTITION_UUIDS is not set
+CONFIG_FSL_CAAM=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
# CONFIG_CMD_MISC is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-# CONFIG_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_GPT=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_IDENT_STRING=" LS-CHLv2"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_LSXL=y
CONFIG_IDENT_STRING=" LS-XHL"
-# CONFIG_MMC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
+CONFIG_API=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_PARTITION_UUIDS is not set
CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
-CONFIG_API=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_LUAN=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" - v2.0"
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_4xx=y
CONFIG_TARGET_LWMON5=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_MAKALU=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MAXBCM=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_TRANSLATE=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_TARGET_MCCMON6=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_MCX=y
CONFIG_VIDEO=y
CONFIG_FIT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mcx # "
# CONFIG_CMD_IMI is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MECP5123=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MEESC=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_MEESC=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC8260=y
CONFIG_TARGET_KM82XX=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC8260=y
CONFIG_TARGET_KM82XX=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_MOTIONPRO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_LED_STATUS_FREQ1=10
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MPC5121ADS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC512X=y
CONFIG_TARGET_MPC5121ADS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_MT_VENTOUX=y
CONFIG_VIDEO=y
CONFIG_FIT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
# CONFIG_CMD_IMLS is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_MUNICES=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_MX31ADS=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_TARGET_MX31PDK=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_SPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6CUBOXI=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SABRESD=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SLEVK=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6SXSABRESD=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_MX6UL_9X9_EVK=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NAS220=y
CONFIG_IDENT_STRING="\nNAS 220"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" neo 0.02"
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_NEO=y
CONFIG_FIT=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_IDENT_STRING=" 2Big v2"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2 Lite"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS Max v2"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2 Mini"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_CMD_FAT=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_IDENT_STRING=" NS v2"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_CONSOLE_MUX=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SYS_NS16550=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KOSAGI_NOVENA=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_NSA310S=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARC=y
CONFIG_TARGET_NSIM=y
-CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
CONFIG_ARC=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_TARGET_NSIM=y
-CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
CONFIG_TARGET_NSIM=y
-CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
CONFIG_ISA_ARCV2=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_TARGET_NSIM=y
-CONFIG_SYS_CLK_FREQ=70000000
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="nsim# "
CONFIG_MESON_GXBB=y
CONFIG_TARGET_ODROID_C2=y
CONFIG_IDENT_STRING=" odroid-c2"
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_MMC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PINCTRL=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_OMAP3_EVM=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
# CONFIG_CMD_IMI is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_TAO3530=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_ARM=y
CONFIG_OMAP34XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_OMAP3_LOGIC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_ARM=y
CONFIG_OMAP44XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-# CONFIG_SPL_I2C_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP4_PANDA=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
+# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_OMAP44XX=y
-# CONFIG_SPL_I2C_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP4_SDP4430=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_ARM=y
CONFIG_OMAP54XX=y
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_OMAP5_UEVM=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_ARMV7_LPAE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_SYS_EXTRA_OPTIONS="MACPWR=SUNXI_GPD(6)"
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11),MACPWR=SUNXI_GPD(6)"
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_SPL_SPI_SUNXI=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_OT1200=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_PCM030=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_PCM051=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_TARGET_PCM051=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_PCM051=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_TARGET_PCM051=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PCM058=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC512X=y
CONFIG_TARGET_PDM360NG=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_LCD=y
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_LCD=y
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_PENGWYN=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_TARGET_PENGWYN=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_TARGET_PEPPER=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TARGET_PEPPER=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="pepper# "
CONFIG_CMD_BOOTZ=y
CONFIG_MIPS=y
CONFIG_SYS_MALLOC_F_LEN=0x600
-CONFIG_MMC=y
CONFIG_MACH_PIC32=y
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y
# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_DM_GPIO=y
+CONFIG_MMC=y
CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI_PIC32=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PIC32=y
CONFIG_DM_ETH=y
CONFIG_PIC32_ETH=y
CONFIG_PINCTRL=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARM=y
-CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PLATINUM_PICON=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="picon > "
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PLATINUM_TITANIUM=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="titanium > "
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9261=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9263=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_PM9G45=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_POGO_E02=y
CONFIG_IDENT_STRING="\nPogo E02"
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="PogoE02> "
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PG0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_MAX_CPUS=2
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_PCI_SUPPORT=y
CONFIG_SPL_PCH_SUPPORT=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_REDWOOD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_VIDEO=y
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SALVATOR_X=y
-# CONFIG_MMC is not set
CONFIG_BOOTSTAGE_USER_COUNT=0x20
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
CONFIG_BOOTDELAY=3
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
CONFIG_CMD_BOOTZ=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC86xx=y
CONFIG_TARGET_SBC8641D=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SH=y
-CONFIG_MMC=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7752EVB=y
CONFIG_BOOTDELAY=3
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
+CONFIG_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SH=y
-CONFIG_MMC=y
CONFIG_TARGET_SH7753EVB=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
+CONFIG_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SH=y
-CONFIG_MMC=y
CONFIG_SH_32BIT=y
CONFIG_TARGET_SH7757LCR=y
CONFIG_BOOTDELAY=3
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
+CONFIG_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_ARCH_S5PC1XX=y
CONFIG_TARGET_SMDKC100=y
CONFIG_IDENT_STRING=" for SMDKC100"
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_BOOTDELAY=3
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SNAPPER9260=y
-# CONFIG_MMC is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
CONFIG_BOOTDELAY=3
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_TARGET_SNIPER=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="sniper # "
CONFIG_CMD_BOOTZ=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
CONFIG_LCD=y
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
# CONFIG_SPL_SPI_SUPPORT is not set
CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
-CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
CONFIG_FIT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_IS1=y
-# CONFIG_MMC is not set
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
CONFIG_FIT=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
CONFIG_TARGET_SOCRATES=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,NAND"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR300=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,NAND"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,FLASH_PNOR"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR310=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,FLASH_PNOR"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,NAND"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,FLASH_PNOR"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR320=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,FLASH_PNOR"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,NAND"
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_TARGET_SPEAR600=y
CONFIG_IDENT_STRING="-SPEAr"
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY,NAND"
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_SYS_I2C_DW=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
+CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
CONFIG_LCD=y
-CONFIG_VIDCONSOLE_AS_LCD=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_STI=y
+CONFIG_IDENT_STRING="STMicroelectronics STiH410-B2260"
+CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="stih410-b2260 => "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_STI=y
+CONFIG_PINCTRL=y
+CONFIG_STI_ASC_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_TIMER=y
+CONFIG_SPL_OF_LIBFDT=y
CONFIG_STM32=y
CONFIG_STM32F4=y
CONFIG_TARGET_STM32F429_DISCOVERY=y
-# CONFIG_MMC is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIMER=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_STM32=y
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="stm32f746-disco"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
+# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="stv0991"
CONFIG_SYS_EXTRA_OPTIONS="STV0991"
CONFIG_BOOTDELAY=3
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_OF_CONTROL=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_T3CORP=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_TAO3530=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="TAO-3530 # "
# CONFIG_CMD_IMI is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
CONFIG_BOOTDELAY=3
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DFU_NAND=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_ARC=y
CONFIG_TARGET_TB100=y
-CONFIG_SYS_CLK_FREQ=500000000
CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_SYS_CLK_FREQ=500000000
CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="[tb100]:~# "
CONFIG_BLACKFIN=y
-CONFIG_MMC=y
CONFIG_TARGET_TCM_BF537=y
CONFIG_BOOTDELAY=5
CONFIG_SILENT_CONSOLE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_GPIO=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_THEADORABLE=y
-CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-# CONFIG_MMC is not set
CONFIG_VIDEO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_GPIO=y
+# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
CONFIG_ARM=y
CONFIG_TARGET_THUNDERX_88XX=y
CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core"
-# CONFIG_MMC is not set
CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM=y
+# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_PL011=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot/ti816x# "
# CONFIG_CMD_IMLS is not set
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_UBI=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_TARGET_TWISTER=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="twister => "
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_UDOO=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_UDOO_NEO=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD11_SINGLE=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD20_SINGLE=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_FAT=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_ARM=y
CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARCH_UNIPHIER_V8_MULTI=y
CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CONFIG=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_USB_A9263=y
-# CONFIG_MMC is not set
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC5xxx=y
CONFIG_TARGET_V38B=y
CONFIG_BOOTDELAY=3
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
-CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=16
CONFIG_LED_STATUS_STATE=1
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_USB=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VE8313=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
-# CONFIG_MMC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_MISC is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-# CONFIG_PARTITION_UUIDS is not set
CONFIG_DM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_VEXPRESS64_JUNO=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
-# CONFIG_MMC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_MISC is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-# CONFIG_PARTITION_UUIDS is not set
CONFIG_DM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_IDENT_STRING=" vexpress_aemv8a"
-# CONFIG_MMC is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_MISC is not set
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
-# CONFIG_PARTITION_UUIDS is not set
CONFIG_DM=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SERIAL=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_WANDBOARD=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_WORK_92105=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-# CONFIG_MMC is not set
+CONFIG_SPL_NAND_SUPPORT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
+# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_8xx=y
CONFIG_TARGET_TQM823L=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_EXT2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_LCD=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC405_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-# CONFIG_SPL_FAT_SUPPORT is not set
-# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_SPL_MMC_SUPPORT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm016 dc2"
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_XPEDITE1000=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC86xx=y
CONFIG_TARGET_XPEDITE517X=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE520X=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE537X=y
CONFIG_FIT=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_SYS_FSL_DDR2=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE550X=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_XPRESS=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_STDIO is not set
# CONFIG_DM_SEQ_ALIAS is not set
-CONFIG_DM_ETH=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
CONFIG_ETHOC=y
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI_PNP is not set
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
-# CONFIG_MMC is not set
CONFIG_4xx=y
CONFIG_TARGET_YUCCA=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_ZC5202=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_ZC5601=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
sprintf(info->uuid, "%08x-%02x", disksig, part_num);
#endif
+ info->sys_ind = pt->sys_ind;
return 0;
}
Write the following to the NAND device:
- spl/u-boot-spl.bin at the offset address 0x00000000
- - u-boot.bin at the offset address 0x00010000
+ - u-boot.bin at the offset address 0x00020000
or
Write the following to the Boot partition 1 of the eMMC device:
- spl/u-boot-spl.bin at the offset address 0x00000000
- - u-boot.bin at the offset address 0x00010000
+ - u-boot.bin at the offset address 0x00020000
or
--
Masahiro Yamada <yamada.masahiro@socionext.com>
-Oct. 2016
+Jan. 2017
/* I2C speed map for a DFSR value of 1 */
+#ifdef __M68K__
/*
* Map I2C frequency dividers to FDR and DFSR values
*
unsigned short divider;
u8 fdr;
} fsl_i2c_speed_map[] = {
-#ifdef __M68K__
{20, 32}, {22, 33}, {24, 34}, {26, 35},
{28, 0}, {28, 36}, {30, 1}, {32, 37},
{34, 2}, {36, 38}, {40, 3}, {40, 39},
{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
{-1, 31}
-#endif
};
+#endif
/**
* Set the I2C bus speed for a given I2C device
If unsure, say N.
+config MMC_SDHCI_STI
+ bool "SDHCI support for STMicroelectronics SoC"
+ depends on MMC_SDHCI && OF_CONTROL
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ on STMicroelectronics STiH410 SoC.
+
config MMC_SDHCI_XENON
bool "SDHCI support for the Xenon SDHCI controller"
depends on MMC_SDHCI && DM_MMC && OF_CONTROL
obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o
obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o
obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
--- /dev/null
+/*
+ * Copyright (c) 2017
+ * Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mmc.h>
+#include <sdhci.h>
+#include <asm/arch/sdhci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+/*
+ * used to get access to MMC1 reset,
+ * will be removed when STi reset driver will be available
+ */
+#define STIH410_SYSCONF5_BASE 0x092b0000
+
+/**
+ * sti_mmc_core_config: configure the Arasan HC
+ * @regbase: base address
+ * @mmc_instance: mmc instance id
+ * Description: this function is to configure the Arasan MMC HC.
+ * This should be called when the system starts in case of, on the SoC,
+ * it is needed to configure the host controller.
+ * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS
+ * needs to be configured as MMC 4.5 to have full capabilities.
+ * W/o these settings the SDHCI could configure and use the embedded controller
+ * with limited features.
+ */
+static void sti_mmc_core_config(const u32 regbase, int mmc_instance)
+{
+ unsigned long *sysconf;
+
+ /* only MMC1 has a reset line */
+ if (mmc_instance) {
+ sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE +
+ ST_MMC_CCONFIG_REG_5);
+ generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf);
+ }
+
+ writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
+ regbase + FLASHSS_MMC_CORE_CONFIG_1);
+
+ if (mmc_instance) {
+ writel(STI_FLASHSS_MMC_CORE_CONFIG2,
+ regbase + FLASHSS_MMC_CORE_CONFIG_2);
+ writel(STI_FLASHSS_MMC_CORE_CONFIG3,
+ regbase + FLASHSS_MMC_CORE_CONFIG_3);
+ } else {
+ writel(STI_FLASHSS_SDCARD_CORE_CONFIG2,
+ regbase + FLASHSS_MMC_CORE_CONFIG_2);
+ writel(STI_FLASHSS_SDCARD_CORE_CONFIG3,
+ regbase + FLASHSS_MMC_CORE_CONFIG_3);
+ }
+ writel(STI_FLASHSS_MMC_CORE_CONFIG4,
+ regbase + FLASHSS_MMC_CORE_CONFIG_4);
+}
+
+static int sti_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret, mmc_instance;
+
+ /*
+ * identify current mmc instance, mmc1 has a reset, not mmc0
+ * MMC0 is wired to the SD slot,
+ * MMC1 is wired on the high speed connector
+ */
+
+ if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL))
+ mmc_instance = 1;
+ else
+ mmc_instance = 0;
+
+ sti_mmc_core_config((const u32) host->ioaddr, mmc_instance);
+
+ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
+ SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_NO_HISPD_BIT;
+
+ host->host_caps = MMC_MODE_DDR_52MHz;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000);
+ if (ret)
+ return ret;
+
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ upriv->mmc = host->mmc;
+
+ return sdhci_probe(dev);
+}
+
+static int sti_sdhci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = strdup(dev->name);
+ host->ioaddr = (void *)dev_get_addr(dev);
+
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
+
+ return 0;
+}
+
+static int sti_sdhci_bind(struct udevice *dev)
+{
+ struct sti_sdhci_plat *plat = dev_get_platdata(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id sti_sdhci_ids[] = {
+ { .compatible = "st,sdhci" },
+ { }
+};
+
+U_BOOT_DRIVER(sti_mmc) = {
+ .name = "sti_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = sti_sdhci_ids,
+ .bind = sti_sdhci_bind,
+ .ops = &sdhci_ops,
+ .ofdata_to_platdata = sti_sdhci_ofdata_to_platdata,
+ .probe = sti_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat),
+};
config NAND_MXS
bool "MXS NAND support"
- depends on MX6
+ depends on MX6 || MX7
help
This enables NAND driver for the NAND flash controller on the
MXS processors.
help
This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC.
It can be found in H3/A64/A83T based SoCs and compatible with both
- External and Internal PHY's.
+ External and Internal PHYs.
config XILINX_AXIEMAC
depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
}
#endif
-/*
- * Calculates the values to be used to specify the address range
- * for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
- * It returns the highest 512MB-aligned address within the given
- * address range, in '*aligned_base_addr', and the number of 256 MiB
- * blocks in it, in 'num_256mb_blocks'.
- */
-static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
- size_t mc_ram_size,
- u64 *aligned_base_addr,
- u8 *num_256mb_blocks)
-{
- u64 addr;
- u16 num_blocks;
-
- if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
- printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
- mc_ram_size);
- return -EINVAL;
- }
-
- num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
- if (num_blocks < 1 || num_blocks > 0xff) {
- printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
- mc_ram_size);
- return -EINVAL;
- }
-
- addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
- MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
-
- if (addr < mc_private_ram_start_addr) {
- printf("fsl-mc: ERROR: bad start address %#llx\n",
- mc_private_ram_start_addr);
- return -EFAULT;
- }
-
- *aligned_base_addr = addr;
- *num_256mb_blocks = num_blocks;
- return 0;
-}
-
static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
struct eth_device *eth_dev)
{
size_t raw_image_size = 0;
#endif
struct mc_version mc_ver_info;
- u64 mc_ram_aligned_base_addr;
u8 mc_ram_num_256mb_blocks;
size_t mc_ram_size = mc_get_dram_block_size();
-
- error = calculate_mc_private_ram_params(mc_ram_addr,
- mc_ram_size,
- &mc_ram_aligned_base_addr,
- &mc_ram_num_256mb_blocks);
- if (error != 0)
+ mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
+ if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
+ error = -EINVAL;
+ printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
+ mc_ram_size);
goto out;
+ }
/*
* Management Complex cores should be held at reset out of POR.
/*
* Tell MC what is the address range of the DRAM block assigned to it:
*/
- reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
+ reg_mcfbalr = (u32)mc_ram_addr |
(mc_ram_num_256mb_blocks - 1);
out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(&mc_ccsr_regs->reg_mcfbahr,
- (u32)(mc_ram_aligned_base_addr >> 32));
+ (u32)(mc_ram_addr >> 32));
out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
/*
*/
u64 mc_get_dram_addr(void)
{
- u64 mc_ram_addr;
-
- /*
- * The MC private DRAM block was already carved at the end of DRAM
- * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
- */
- if (gd->bd->bi_dram[1].start) {
- mc_ram_addr =
- gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
- } else {
- mc_ram_addr =
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
- }
-
- return mc_ram_addr;
+ return gd->arch.resv_ram;
}
/**
struct mii_dev *bus;
#ifdef CONFIG_DM_ETH
+#ifdef CONFIG_CLK
unsigned long pclk_rate;
+#endif
phy_interface_t phy_interface;
#endif
};
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
-#ifdef CONFIG_DM_ETH
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
{
u32 config;
-#ifdef CONFIG_DM_ETH
+#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
.write_hwaddr = macb_write_hwaddr,
};
+#ifdef CONFIG_CLK
static int macb_enable_clk(struct udevice *dev)
{
struct macb_device *macb = dev_get_priv(dev);
return 0;
}
+#endif
static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
- int ret;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
macb->regs = (void *)pdata->iobase;
- ret = macb_enable_clk(dev);
+#ifdef CONFIG_CLK
+ int ret = macb_enable_clk(dev);
if (ret)
return ret;
+#endif
_macb_eth_initialize(macb);
if (!priv->phydev)
return -ENODEV;
- priv->phydev->supported = supported | ADVERTISED_Pause |
+ priv->phydev->supported &= supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
priv->phydev->advertising = priv->phydev->supported;
by a device tree node which contains both GPIO defintion and pin control
functions.
+config PINCTRL_STI
+ bool "STMicroelectronics STi pin-control and pin-mux driver"
+ depends on DM && ARCH_STI
+ default y
+ help
+ Support pin multiplexing control on STMicrolectronics STi SoCs.
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available multiplex
+ function.
+
endif
source "drivers/pinctrl/meson/Kconfig"
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
+obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
--- /dev/null
+/*
+ * Pinctrl driver for STMicroelectronics STi SoCs
+ *
+ * Copyright (c) 2017
+ * Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_STI_PINCONF_ENTRIES 7
+/* Output enable */
+#define OE (1 << 27)
+/* Pull Up */
+#define PU (1 << 26)
+/* Open Drain */
+#define OD (1 << 25)
+
+/* User-frendly defines for Pin Direction */
+ /* oe = 0, pu = 0, od = 0 */
+#define IN (0)
+ /* oe = 0, pu = 1, od = 0 */
+#define IN_PU (PU)
+ /* oe = 1, pu = 0, od = 0 */
+#define OUT (OE)
+ /* oe = 1, pu = 1, od = 0 */
+#define OUT_PU (OE | PU)
+ /* oe = 1, pu = 0, od = 1 */
+#define BIDIR (OE | OD)
+ /* oe = 1, pu = 1, od = 1 */
+#define BIDIR_PU (OE | PU | OD)
+
+struct sti_pinctrl_platdata {
+ struct regmap *regmap;
+};
+
+struct sti_pin_desc {
+ unsigned char bank;
+ unsigned char pin;
+ unsigned char alt;
+ int dir;
+};
+
+/*
+ * PIO alternative Function selector
+ */
+void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
+{
+ struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
+ unsigned long sysconf, *sysconfreg;
+ int alt = pin_desc->alt;
+ int bank = pin_desc->bank;
+ int pin = pin_desc->pin;
+
+ sysconfreg = (unsigned long *)plat->regmap->base;
+
+ switch (bank) {
+ case 0 ... 5: /* in "SBC Bank" */
+ sysconfreg += bank;
+ break;
+ case 10 ... 20: /* in "FRONT Bank" */
+ sysconfreg += bank - 10;
+ break;
+ case 30 ... 35: /* in "REAR Bank" */
+ sysconfreg += bank - 30;
+ break;
+ case 40 ... 42: /* in "FLASH Bank" */
+ sysconfreg += bank - 40;
+ break;
+ default:
+ BUG();
+ return;
+ }
+
+ sysconf = readl(sysconfreg);
+ sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
+ writel(sysconf, sysconfreg);
+}
+
+/* pin configuration */
+void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
+{
+ struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
+ int bit;
+ int oe = 0, pu = 0, od = 0;
+ unsigned long *sysconfreg;
+ int bank = pin_desc->bank;
+
+ sysconfreg = (unsigned long *)plat->regmap->base + 40;
+
+ /*
+ * NOTE: The PIO configuration for the PIO pins in the
+ * "FLASH Bank" are different from all the other banks!
+ * Specifically, the output-enable pin control register
+ * (SYS_CFG_3040) and the pull-up pin control register
+ * (SYS_CFG_3050), are both classed as being "reserved".
+ * Hence, we do not write to these registers to configure
+ * the OE and PU features for PIOs in this bank. However,
+ * the open-drain pin control register (SYS_CFG_3060)
+ * follows the style of the other banks, and so we can
+ * treat that register normally.
+ *
+ * Being pedantic, we should configure the PU and PD features
+ * in the "FLASH Bank" explicitly instead using the four
+ * SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
+ * would necessitate passing in the alternate function number
+ * to this function, and adding some horrible complexity here.
+ * Alternatively, we could just perform 4 32-bit "pokes" to
+ * these four SYS_CFG registers early in the initialization.
+ * In practice, these four SYS_CFG registers are correct
+ * after a reset, and U-Boot does not need to change them, so
+ * we (cheat and) rely on these registers being correct.
+ * WARNING: Please be aware of this (pragmatic) behaviour!
+ */
+ int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
+
+ switch (pin_desc->dir) {
+ case IN:
+ oe = 0; pu = 0; od = 0;
+ break;
+ case IN_PU:
+ oe = 0; pu = 1; od = 0;
+ break;
+ case OUT:
+ oe = 1; pu = 0; od = 0;
+ break;
+ case BIDIR:
+ oe = 1; pu = 0; od = 1;
+ break;
+ case BIDIR_PU:
+ oe = 1; pu = 1; od = 1;
+ break;
+
+ default:
+ error("%s invalid direction value: 0x%x\n",
+ __func__, pin_desc->dir);
+ BUG();
+ break;
+ }
+
+ switch (bank) {
+ case 0 ... 5: /* in "SBC Bank" */
+ sysconfreg += bank / 4;
+ break;
+ case 10 ... 20: /* in "FRONT Bank" */
+ bank -= 10;
+ sysconfreg += bank / 4;
+ break;
+ case 30 ... 35: /* in "REAR Bank" */
+ bank -= 30;
+ sysconfreg += bank / 4;
+ break;
+ case 40 ... 42: /* in "FLASH Bank" */
+ bank -= 40;
+ sysconfreg += bank / 4;
+ flashss = 1; /* pin is in the Flash Sub-System */
+ break;
+ default:
+ BUG();
+ return;
+ }
+
+ bit = ((bank * 8) + pin_desc->pin) % 32;
+
+ /*
+ * set the "Output Enable" pin control
+ * but, do nothing if in the flashSS
+ */
+ if (!flashss) {
+ if (oe)
+ generic_set_bit(bit, sysconfreg);
+ else
+ generic_clear_bit(bit, sysconfreg);
+ }
+
+ sysconfreg += 10; /* skip to next set of syscfg registers */
+
+ /*
+ * set the "Pull Up" pin control
+ * but, do nothing if in the FlashSS
+ */
+
+ if (!flashss) {
+ if (pu)
+ generic_set_bit(bit, sysconfreg);
+ else
+ generic_clear_bit(bit, sysconfreg);
+ }
+
+ sysconfreg += 10; /* skip to next set of syscfg registers */
+
+ /* set the "Open Drain Enable" pin control */
+ if (od)
+ generic_set_bit(bit, sysconfreg);
+ else
+ generic_clear_bit(bit, sysconfreg);
+}
+
+
+static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct fdtdec_phandle_args args;
+ const void *blob = gd->fdt_blob;
+ const char *prop_name;
+ int node = dev_of_offset(config);
+ int property_offset, prop_len;
+ int pinconf_node, ret, count;
+ const char *bank_name;
+ u32 cells[MAX_STI_PINCONF_ENTRIES];
+
+ struct sti_pin_desc pin_desc;
+
+ /* go to next node "st,pins" which contains the pins configuration */
+ pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
+
+ /*
+ * parse each pins configuration which looks like :
+ * pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
+ */
+
+ fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
+ fdt_getprop_by_offset(blob, property_offset, &prop_name,
+ &prop_len);
+
+ /* extract the bank of the pin description */
+ ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
+ prop_name, "#gpio-cells",
+ 0, 0, &args);
+ if (ret < 0) {
+ error("Can't get the gpio bank phandle: %d\n", ret);
+ return ret;
+ }
+
+ bank_name = fdt_getprop(blob, args.node, "st,bank-name",
+ &count);
+ if (count < 0) {
+ error("Can't find bank-name property %d\n", count);
+ return -EINVAL;
+ }
+
+ pin_desc.bank = trailing_strtoln(bank_name, NULL);
+
+ count = fdtdec_get_int_array_count(blob, pinconf_node,
+ prop_name, cells,
+ ARRAY_SIZE(cells));
+ if (count < 0) {
+ error("Bad pin configuration array %d\n", count);
+ return -EINVAL;
+ }
+
+ if (count > MAX_STI_PINCONF_ENTRIES) {
+ error("Unsupported pinconf array count %d\n", count);
+ return -EINVAL;
+ }
+
+ pin_desc.pin = cells[1];
+ pin_desc.alt = cells[2];
+ pin_desc.dir = cells[3];
+
+ sti_alternate_select(dev, &pin_desc);
+ sti_pin_configure(dev, &pin_desc);
+ };
+
+ return 0;
+}
+
+static int sti_pinctrl_probe(struct udevice *dev)
+{
+ struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
+ struct udevice *syscon;
+ int err;
+
+ /* get corresponding syscon phandle */
+ err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "st,syscfg", &syscon);
+ if (err) {
+ error("unable to find syscon device\n");
+ return err;
+ }
+
+ plat->regmap = syscon_get_regmap(syscon);
+ if (!plat->regmap) {
+ error("unable to find regmap\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id sti_pinctrl_ids[] = {
+ { .compatible = "st,stih407-sbc-pinctrl" },
+ { .compatible = "st,stih407-front-pinctrl" },
+ { .compatible = "st,stih407-rear-pinctrl" },
+ { .compatible = "st,stih407-flash-pinctrl" },
+ { }
+};
+
+const struct pinctrl_ops sti_pinctrl_ops = {
+ .set_state = sti_pinctrl_set_state,
+};
+
+U_BOOT_DRIVER(pinctrl_sti) = {
+ .name = "pinctrl_sti",
+ .id = UCLASS_PINCTRL,
+ .of_match = sti_pinctrl_ids,
+ .ops = &sti_pinctrl_ops,
+ .probe = sti_pinctrl_probe,
+ .platdata_auto_alloc_size = sizeof(struct sti_pinctrl_platdata),
+ .ops = &sti_pinctrl_ops,
+};
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/sizes.h>
#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
+#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
#define UNIPHIER_PINCTRL_IECTRL 0x1d00
static const char *uniphier_pinctrl_dummy_name = "_dummy";
return priv->socdata->functions[selector];
}
-static void uniphier_pinconf_input_enable_perpin(struct udevice *dev,
- unsigned pin)
+static int uniphier_pinconf_input_enable_perpin(struct udevice *dev,
+ unsigned int pin, int enable)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
unsigned reg;
mask = BIT(pin % 32);
tmp = readl(priv->base + reg);
- tmp |= mask;
+ if (enable)
+ tmp |= mask;
+ else
+ tmp &= ~mask;
writel(tmp, priv->base + reg);
+
+ return 0;
}
-static void uniphier_pinconf_input_enable_legacy(struct udevice *dev,
- unsigned pin)
+static int uniphier_pinconf_input_enable_legacy(struct udevice *dev,
+ unsigned int pin, int enable)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
int pins_count = priv->socdata->pins_count;
const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
int i;
+ /*
+ * Multiple pins share one input enable, per-pin disabling is
+ * impossible.
+ */
+ if (!enable)
+ return -EINVAL;
+
for (i = 0; i < pins_count; i++) {
if (pins[i].number == pin) {
unsigned int iectrl;
writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL);
}
}
+
+ return 0;
}
-static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin)
+static int uniphier_pinconf_input_enable(struct udevice *dev,
+ unsigned int pin, int enable)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
- uniphier_pinconf_input_enable_perpin(dev, pin);
+ return uniphier_pinconf_input_enable_perpin(dev, pin, enable);
+ else
+ return uniphier_pinconf_input_enable_legacy(dev, pin, enable);
+}
+
+#if CONFIG_IS_ENABLED(PINCONF)
+
+static const struct pinconf_param uniphier_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
+ { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+ { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
+};
+
+static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin,
+ unsigned int param, unsigned int arg)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned int enable = 1;
+ unsigned int reg;
+ u32 mask, tmp;
+
+ if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE))
+ return -ENOTSUPP;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ enable = 0;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (arg == 0) /* total bias is not supported */
+ return -EINVAL;
+ break;
+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+ if (arg == 0) /* configuration ignored */
+ return 0;
+ default:
+ BUG();
+ }
+
+ reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pin / 32 * 4;
+ mask = BIT(pin % 32);
+
+ tmp = readl(priv->base + reg);
+ if (enable)
+ tmp |= mask;
else
- uniphier_pinconf_input_enable_legacy(dev, pin);
+ tmp &= ~mask;
+ writel(tmp, priv->base + reg);
+
+ return 0;
+}
+
+static int uniphier_pinconf_set_one(struct udevice *dev, unsigned int pin,
+ unsigned int param, unsigned int arg)
+{
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+ ret = uniphier_pinconf_bias_set(dev, pin, param, arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ ret = uniphier_pinconf_input_enable(dev, pin, arg);
+ break;
+ default:
+ printf("unsupported configuration parameter %u\n", param);
+ return -EINVAL;
+ }
+
+ return ret;
}
+static int uniphier_pinconf_group_set(struct udevice *dev,
+ unsigned int group_selector,
+ unsigned int param, unsigned int arg)
+{
+ struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct uniphier_pinctrl_group *grp =
+ &priv->socdata->groups[group_selector];
+ int i, ret;
+
+ for (i = 0; i < grp->num_pins; i++) {
+ ret = uniphier_pinconf_set_one(dev, grp->pins[i], param, arg);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_IS_ENABLED(PINCONF) */
+
static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
int muxval)
{
u32 tmp;
/* some pins need input-enabling */
- uniphier_pinconf_input_enable(dev, pin);
+ uniphier_pinconf_input_enable(dev, pin, 1);
if (muxval < 0)
return; /* dedicated pin; nothing to do for pin-mux */
.get_functions_count = uniphier_pinmux_get_functions_count,
.get_function_name = uniphier_pinmux_get_function_name,
.pinmux_group_set = uniphier_pinmux_group_set,
+#if CONFIG_IS_ENABLED(PINCONF)
+ .pinconf_num_params = ARRAY_SIZE(uniphier_pinconf_params),
+ .pinconf_params = uniphier_pinconf_params,
+ .pinconf_group_set = uniphier_pinconf_group_set,
+#endif
.set_state = pinctrl_generic_set_state,
};
.groups_count = ARRAY_SIZE(uniphier_ld11_groups),
.functions = uniphier_ld11_functions,
.functions_count = ARRAY_SIZE(uniphier_ld11_functions),
- .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+ .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+ UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
};
static int uniphier_ld11_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(uniphier_ld20_groups),
.functions = uniphier_ld20_functions,
.functions_count = ARRAY_SIZE(uniphier_ld20_functions),
- .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+ .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+ UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
};
static int uniphier_ld20_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(uniphier_ld6b_groups),
.functions = uniphier_ld6b_functions,
.functions_count = ARRAY_SIZE(uniphier_ld6b_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE,
};
static int uniphier_ld6b_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(uniphier_pro5_groups),
.functions = uniphier_pro5_functions,
.functions_count = ARRAY_SIZE(uniphier_pro5_functions),
- .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
+ .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+ UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
static int uniphier_pro5_pinctrl_probe(struct udevice *dev)
.groups_count = ARRAY_SIZE(uniphier_pxs2_groups),
.functions = uniphier_pxs2_functions,
.functions_count = ARRAY_SIZE(uniphier_pxs2_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE,
};
static int uniphier_pxs2_pinctrl_probe(struct udevice *dev)
const char * const *functions;
int functions_count;
unsigned caps;
+#define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE BIT(3)
#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
if (aldo_num == 3)
return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
AXP809_OUTPUT_CTRL2_ALDO3_EN);
- return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+ return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
}
If you have a machine based on a Marvell XScale PXA2xx CPU you
can enable its onboard serial ports by enabling this option.
+config STI_ASC_SERIAL
+ bool "STMicroelectronics on-chip UART"
+ depends on DM_SERIAL && ARCH_STI
+ help
+ Select this to enable Asynchronous Serial Controller available
+ on STiH410 SoC. This is a basic implementation, it supports
+ following baudrate 9600, 19200, 38400, 57600 and 115200.
+
endmenu
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
+obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
--- /dev/null
+/*
+ * Support for Serial I/O using STMicroelectronics' on-chip ASC.
+ *
+ * Copyright (c) 2017
+ * Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BAUDMODE 0x00001000
+#define RXENABLE 0x00000100
+#define RUN 0x00000080
+#define MODE 0x00000001
+#define MODE_8BIT 0x0001
+#define STOP_1BIT 0x0008
+#define PARITYODD 0x0020
+
+#define STA_TF BIT(9)
+#define STA_RBF BIT(0)
+
+struct sti_asc_uart {
+ u32 baudrate;
+ u32 txbuf;
+ u32 rxbuf;
+ u32 control;
+ u32 inten;
+ u32 status;
+ u32 guardtime;
+ u32 timeout;
+ u32 txreset;
+ u32 rxreset;
+};
+
+struct sti_asc_serial {
+ /* address of registers in physical memory */
+ struct sti_asc_uart *regs;
+};
+
+/* Values for the BAUDRATE Register */
+#define PCLK (200ul * 1000000ul)
+#define BAUDRATE_VAL_M0(bps) (PCLK / (16 * (bps)))
+#define BAUDRATE_VAL_M1(bps) ((bps * (1 << 14)) + (1<<13)) / (PCLK/(1 << 6))
+
+/*
+ * MODE 0
+ * ICCLK
+ * ASCBaudRate = ----------------
+ * baudrate * 16
+ *
+ * MODE 1
+ * baudrate * 16 * 2^16
+ * ASCBaudRate = ------------------------
+ * ICCLK
+ *
+ * NOTE:
+ * Mode 1 should be used for baudrates of 19200, and above, as it
+ * has a lower deviation error than Mode 0 for higher frequencies.
+ * Mode 0 should be used for all baudrates below 19200.
+ */
+
+static int sti_asc_pending(struct udevice *dev, bool input)
+{
+ struct sti_asc_serial *priv = dev_get_priv(dev);
+ struct sti_asc_uart *const uart = priv->regs;
+ unsigned long status;
+
+ status = readl(&uart->status);
+ if (input)
+ return status & STA_RBF;
+ else
+ return status & STA_TF;
+}
+
+static int _sti_asc_serial_setbrg(struct sti_asc_uart *uart, int baudrate)
+{
+ unsigned long val;
+ int t, mode = 1;
+
+ switch (baudrate) {
+ case 9600:
+ t = BAUDRATE_VAL_M0(9600);
+ mode = 0;
+ break;
+ case 19200:
+ t = BAUDRATE_VAL_M1(19200);
+ break;
+ case 38400:
+ t = BAUDRATE_VAL_M1(38400);
+ break;
+ case 57600:
+ t = BAUDRATE_VAL_M1(57600);
+ break;
+ default:
+ debug("ASC: unsupported baud rate: %d, using 115200 instead.\n",
+ baudrate);
+ case 115200:
+ t = BAUDRATE_VAL_M1(115200);
+ break;
+ }
+
+ /* disable the baudrate generator */
+ val = readl(&uart->control);
+ writel(val & ~RUN, &uart->control);
+
+ /* set baud generator reload value */
+ writel(t, &uart->baudrate);
+ /* reset the RX & TX buffers */
+ writel(1, &uart->txreset);
+ writel(1, &uart->rxreset);
+
+ /* set baud generator mode */
+ if (mode)
+ val |= BAUDMODE;
+
+ /* finally, write value and enable ASC */
+ writel(val, &uart->control);
+
+ return 0;
+}
+
+/* called to adjust baud-rate */
+static int sti_asc_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct sti_asc_serial *priv = dev_get_priv(dev);
+ struct sti_asc_uart *const uart = priv->regs;
+
+ return _sti_asc_serial_setbrg(uart, baudrate);
+}
+
+/* blocking function, that returns next char */
+static int sti_asc_serial_getc(struct udevice *dev)
+{
+ struct sti_asc_serial *priv = dev_get_priv(dev);
+ struct sti_asc_uart *const uart = priv->regs;
+
+ /* polling wait: for a char to be read */
+ if (!sti_asc_pending(dev, true))
+ return -EAGAIN;
+
+ return readl(&uart->rxbuf);
+}
+
+/* write write out a single char */
+static int sti_asc_serial_putc(struct udevice *dev, const char c)
+{
+ struct sti_asc_serial *priv = dev_get_priv(dev);
+ struct sti_asc_uart *const uart = priv->regs;
+
+ /* wait till safe to write next char */
+ if (sti_asc_pending(dev, false))
+ return -EAGAIN;
+
+ /* finally, write next char */
+ writel(c, &uart->txbuf);
+
+ return 0;
+}
+
+/* initialize the ASC */
+static int sti_asc_serial_probe(struct udevice *dev)
+{
+ struct sti_asc_serial *priv = dev_get_priv(dev);
+ unsigned long val;
+ fdt_addr_t base;
+
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = (struct sti_asc_uart *)base;
+ sti_asc_serial_setbrg(dev, gd->baudrate);
+
+ /*
+ * build up the value to be written to CONTROL
+ * set character length, bit stop number, odd parity
+ */
+ val = RXENABLE | RUN | MODE_8BIT | STOP_1BIT | PARITYODD;
+ writel(val, &priv->regs->control);
+
+ return 0;
+}
+
+static const struct dm_serial_ops sti_asc_serial_ops = {
+ .putc = sti_asc_serial_putc,
+ .pending = sti_asc_pending,
+ .getc = sti_asc_serial_getc,
+ .setbrg = sti_asc_serial_setbrg,
+};
+
+static const struct udevice_id sti_serial_of_match[] = {
+ { .compatible = "st,asc" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_sti_asc) = {
+ .name = "serial_sti_asc",
+ .id = UCLASS_SERIAL,
+ .of_match = sti_serial_of_match,
+ .ops = &sti_asc_serial_ops,
+ .probe = sti_asc_serial_probe,
+ .priv_auto_alloc_size = sizeof(struct sti_asc_serial),
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
+obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
--- /dev/null
+/*
+ * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <sysreset.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_sysreset_priv {
+ phys_addr_t base;
+};
+
+static int sti_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct sti_sysreset_priv *priv = dev_get_priv(dev);
+
+ generic_clear_bit(0, (void __iomem *)priv->base);
+
+ return -EINPROGRESS;
+}
+
+static int sti_sysreset_probe(struct udevice *dev)
+{
+ struct sti_sysreset_priv *priv = dev_get_priv(dev);
+ struct udevice *syscon;
+ struct regmap *regmap;
+ struct fdtdec_phandle_args syscfg_phandle;
+ int ret;
+
+ /* get corresponding syscon phandle */
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
+ "st,syscfg", NULL, 0, 0,
+ &syscfg_phandle);
+ if (ret < 0) {
+ error("Can't get syscfg phandle: %d\n", ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SYSCON,
+ syscfg_phandle.node,
+ &syscon);
+ if (ret) {
+ error("%s: uclass_get_device_by_of_offset failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ regmap = syscon_get_regmap(syscon);
+ if (!regmap) {
+ error("unable to get regmap for %s\n", syscon->name);
+ return -ENODEV;
+ }
+
+ priv->base = regmap->base;
+
+ return 0;
+}
+
+static struct sysreset_ops sti_sysreset = {
+ .request = sti_sysreset_request,
+};
+
+static const struct udevice_id sti_sysreset_ids[] = {
+ { .compatible = "st,stih407-restart" },
+ { }
+};
+
+U_BOOT_DRIVER(sysreset_sti) = {
+ .name = "sysreset_sti",
+ .id = UCLASS_SYSRESET,
+ .ops = &sti_sysreset,
+ .probe = sti_sysreset_probe,
+ .of_match = sti_sysreset_ids,
+ .priv_auto_alloc_size = sizeof(struct sti_sysreset_priv),
+};
This is mostly because they all share several registers which
makes it difficult to completely separate them.
+config STI_TIMER
+ bool "STi timer support"
+ depends on TIMER
+ default y if ARCH_STI
+ help
+ Select this to enable a timer for STi devices.
+
endmenu
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
+obj-$(CONFIG_STI_TIMER) += sti-timer.o
--- /dev/null
+/*
+ * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <timer.h>
+
+#include <asm/io.h>
+#include <asm/arch-armv7/globaltimer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_timer_priv {
+ struct globaltimer *global_timer;
+};
+
+static int sti_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct globaltimer *global_timer = priv->global_timer;
+ u32 low, high;
+ u64 timer;
+ u32 old = readl(&global_timer->cnt_h);
+
+ while (1) {
+ low = readl(&global_timer->cnt_l);
+ high = readl(&global_timer->cnt_h);
+ if (old == high)
+ break;
+ else
+ old = high;
+ }
+ timer = high;
+ *count = (u64)((timer << 32) | low);
+
+ return 0;
+}
+
+static int sti_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct sti_timer_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+
+ /* get arm global timer base address */
+ addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
+ priv->global_timer = (struct globaltimer *)addr;
+
+ /* init timer */
+ writel(0x01, &priv->global_timer->ctl);
+
+ return 0;
+}
+
+static const struct timer_ops sti_timer_ops = {
+ .get_count = sti_timer_get_count,
+};
+
+static const struct udevice_id sti_timer_ids[] = {
+ { .compatible = "arm,cortex-a9-global-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(sti_timer) = {
+ .name = "sti_timer",
+ .id = UCLASS_TIMER,
+ .of_match = sti_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct sti_timer_priv),
+ .probe = sti_timer_probe,
+ .ops = &sti_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-#include <asm/arch/sys_proto.h>
#include "core.h"
#include "gadget.h"
int ret;
ret = dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf,
- req->length, f_dfu->blk_seq_num);
+ req->actual, f_dfu->blk_seq_num);
if (ret) {
f_dfu->dfu_status = DFU_STATUS_errUNKNOWN;
f_dfu->dfu_state = DFU_STATE_dfuERROR;
DFU_MANIFEST_POLL_TIMEOUT;
}
-static void handle_getstatus(struct usb_request *req)
+static int handle_getstatus(struct usb_request *req)
{
struct dfu_status *dstat = (struct dfu_status *)req->buf;
struct f_dfu *f_dfu = req->context;
dstat->bStatus = f_dfu->dfu_status;
dstat->bState = f_dfu->dfu_state;
dstat->iString = 0;
+
+ return sizeof(struct dfu_status);
}
-static void handle_getstate(struct usb_request *req)
+static int handle_getstate(struct usb_request *req)
{
struct f_dfu *f_dfu = req->context;
((u8 *)req->buf)[0] = f_dfu->dfu_state;
- req->actual = sizeof(u8);
+ return sizeof(u8);
}
static inline void to_dfu_mode(struct f_dfu *f_dfu)
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
case USB_REQ_DFU_DETACH:
f_dfu->dfu_state = DFU_STATE_appDETACH;
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_appIDLE;
value = RET_ZLP;
break;
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
case USB_REQ_DFU_DETACH:
/*
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
value = RET_ZLP;
break;
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
case USB_REQ_DFU_GETSTATUS:
/* We're MainfestationTolerant */
f_dfu->dfu_state = DFU_STATE_dfuMANIFEST;
- handle_getstatus(req);
+ value = handle_getstatus(req);
f_dfu->blk_seq_num = 0;
- value = RET_STAT_LEN;
req->complete = dnload_request_flush;
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
case USB_REQ_DFU_GETSTATUS:
/* We're MainfestationTolerant */
f_dfu->dfu_state = DFU_STATE_dfuIDLE;
- handle_getstatus(req);
+ value = handle_getstatus(req);
f_dfu->blk_seq_num = 0;
- value = RET_STAT_LEN;
puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n");
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
value = RET_ZLP;
break;
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
default:
f_dfu->dfu_state = DFU_STATE_dfuERROR;
switch (ctrl->bRequest) {
case USB_REQ_DFU_GETSTATUS:
- handle_getstatus(req);
- value = RET_STAT_LEN;
+ value = handle_getstatus(req);
break;
case USB_REQ_DFU_GETSTATE:
- handle_getstate(req);
+ value = handle_getstate(req);
break;
case USB_REQ_DFU_CLRSTATUS:
f_dfu->dfu_state = DFU_STATE_dfuIDLE;
struct usb_interface_descriptor *d;
int i = 0;
- f_dfu->function = calloc(sizeof(struct usb_descriptor_header *), n + 1);
+ f_dfu->function = calloc(sizeof(struct usb_descriptor_header *), n + 2);
if (!f_dfu->function)
goto enomem;
f_dfu->function[i] = (struct usb_descriptor_header *)d;
}
+
+ /* add DFU Functional Descriptor */
+ f_dfu->function[i] = calloc(sizeof(dfu_func), 1);
+ if (!f_dfu->function[i])
+ goto enomem;
+ memcpy(f_dfu->function[i], &dfu_func, sizeof(dfu_func));
+
+ i++;
f_dfu->function[i] = NULL;
return 0;
{
struct usb_composite_dev *cdev = c->cdev;
struct f_dfu *f_dfu = func_to_dfu(f);
+ const char *s;
int alt_num = dfu_get_alt_number();
int rv, id, i;
cdev->req->context = f_dfu;
+ s = getenv("serial#");
+ if (s)
+ g_dnl_set_serialnumber((char *)s);
+
error:
return rv;
}
#define RET_STALL -1
#define RET_ZLP 0
-#define RET_STAT_LEN 6
enum dfu_state {
DFU_STATE_appIDLE = 0,
void g_dnl_set_serialnumber(char *s)
{
memset(g_dnl_serial, 0, MAX_STRING_SERIAL);
- if (strlen(s) < MAX_STRING_SERIAL)
- strncpy(g_dnl_serial, s, strlen(s));
+ strncpy(g_dnl_serial, s, MAX_STRING_SERIAL - 1);
}
static struct usb_device_descriptor device_desc = {
}
#define FILL_32BIT_X888RGB(r,g,b) { \
- *(unsigned long *)fb = \
- SWAP32((unsigned long)(((r<<16) | \
+ *(u32 *)fb = \
+ SWAP32((unsigned int)(((r<<16) | \
(g<<8) | \
b))); \
fb += 4; \
break;
case GDF_32BIT_X888RGB:
for (i = 0; i < cnt; i++) {
- *(unsigned long *) addr = p[bm[*off]].ce.dw;
+ *(u32 *) addr = p[bm[*off]].ce.dw;
addr += 4;
}
break;
(b >> 3)));
break;
case GDF_32BIT_X888RGB:
- *(unsigned long *) dest =
- SWAP32((unsigned long) (
+ *(u32 *) dest =
+ SWAP32((u32) (
(r << 16) |
(g << 8) |
b));
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
int timeout = 1000000;
+ if (!panel.frameAdrs)
+ return;
+
writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg);
writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg);
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
.mpixelclock = 66000000,
.cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
}, {
- .mpixelclock = 835000000,
+ .mpixelclock = 83500000,
.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
}, {
.mpixelclock = 146250000,
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#endif
/* High Level Configuration Options */
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE
#endif
/* High Level Configuration Options */
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#if defined(CONFIG_PCI)
#endif
/* High Level Configuration Options */
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#ifdef CONFIG_PCI
#endif
/* High Level Configuration Options */
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
#if defined(CONFIG_PCI)
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_DEEP_SLEEP
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-
/* support deep sleep */
#ifdef CONFIG_ARCH_T1024
#define CONFIG_DEEP_SLEEP
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
/*
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
-/* CPU Errata */
-#define CONFIG_ARM_ERRATA_773022
-#define CONFIG_ARM_ERRATA_774769
-
/* Power */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
# define CONFIG_LZO
-# ifdef CONFIG_ENABLE_VBOOT
-# endif
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_CM_T3517 /* working with CM-T3517 */
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
-
/*
* Console
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_FSL_CAAM /* Enable CAAM */
-
/*
* Serial Port
*/
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#define CONFIG_FSL_CAAM /* Enable CAAM */
-
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
+#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
-#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_FSL_CAAM /* Enable CAAM */
-
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
#endif
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-
/* FMan ucode */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
+#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_FSL_DDR_BIST
+#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#endif
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
/* FMan ucode */
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
+#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#endif
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
/* We need architecture specific misc initializations */
-#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
-
/* Link Definitions */
#ifndef CONFIG_QSPI_BOOT
#ifdef CONFIG_SPL
#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
/* MC firmware */
-#define CONFIG_FSL_MC_ENET
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
*/
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
-#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
#endif
/* Command line configuration */
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP3_MCX /* working with mcx */
#define CONFIG_OMAP_GPIO
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define __MX6_COMMON_H
#ifndef CONFIG_MX6UL
-#define CONFIG_ARM_ERRATA_743622
-#define CONFIG_ARM_ERRATA_751472
-#define CONFIG_ARM_ERRATA_794072
-#define CONFIG_ARM_ERRATA_761320
-
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000
-#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000
-#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
#endif
#define CONFIG_OMAP3430 /* which is in a 3430 */
#define CONFIG_OMAP3_RX51 /* working with RX51 */
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
*/
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
/* environment organization */
-#define CONFIG_ENV_IS_IN_UBI 1
+#define CONFIG_ENV_IS_NOWHERE 1
#define CONFIG_ENV_UBI_PART "UBI"
#define CONFIG_ENV_UBI_VOLUME "config"
#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
*/
#define CONFIG_ARM_ARCH_CP15_ERRATA
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
/*
* Platform
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 2
-
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
-#else
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
#endif
#endif
--- /dev/null
+/*
+ * (C) Copyright 2017
+ * Patrice Chotard, <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config.h>
+
+/* ram memory-related information */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x40000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define PHYS_SDRAM_1_SIZE 0x3FE00000
+#define CONFIG_SYS_TEXT_BASE 0x7D600000
+#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */
+
+/* Libraries */
+#define CONFIG_MD5
+
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+
+/* Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "board= B2260" \
+ "load_addr= #CONFIG_SYS_LOAD_ADDR \0"
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x4000
+
+/* Extra Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN 0x1800000
+#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#endif /* __CONFIG_H */
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* Has an SDRC controller */
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
-/*
- * Errata configuration
- */
-#define CONFIG_ARM_ERRATA_716044
-#define CONFIG_ARM_ERRATA_742230
-#define CONFIG_ARM_ERRATA_751472
-
/*
* NS16550 Configuration
*/
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
-/*
- * Errata configuration
- */
-#define CONFIG_ARM_ERRATA_743622
-#define CONFIG_ARM_ERRATA_751472
-
/*
* NS16550 Configuration
*/
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
/* The chip has SDRC controller */
#define CONFIG_SDRC
#ifndef __CONFIG_TI_OMAP5_COMMON_H
#define __CONFIG_TI_OMAP5_COMMON_H
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_798870
-
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_MII
#define CONFIG_ARP_TIMEOUT 200UL
-/* Network config - Allow larger/faster download for TFTP/NFS */
-#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE 4096
-#define CONFIG_NFS_READ_SIZE 4096
/* Command definition */
#define CONFIG_CMD_BMODE
"update_uboot=if tftp ${uboot}; then " \
"if itest ${filesize} > 0; then " \
"mmc dev ${mmcdev}; mmc rescan; " \
- "setexpr blkc ${filesize} / 0x200; " \
- "setexpr blkc ${blkc} + 1; " \
+ "setexpr blkc ${filesize} + 0x1ff; " \
+ "setexpr blkc ${blkc} / 0x200; " \
"if itest ${blkc} <= ${uboot_size}; then " \
"mmc write ${loadaddr} ${uboot_start} " \
"${blkc}; " \
"if tftp ${kernel}; then " \
"if itest ${filesize} > 0; then " \
"mmc dev ${mmcdev}; mmc rescan; " \
- "setexpr blkc ${filesize} / 0x200; " \
- "setexpr blkc ${blkc} + 1; " \
+ "setexpr blkc ${filesize} + 0x1ff; " \
+ "setexpr blkc ${blkc} / 0x200; " \
"if itest ${blkc} <= ${kernel_size}; then " \
"mmc write ${loadaddr} " \
"${kernel_start} ${blkc}; " \
"update_fdt=if tftp ${fdt_file}; then " \
"if itest ${filesize} > 0; then " \
"mmc dev ${mmcdev}; mmc rescan; " \
- "setexpr blkc ${filesize} / 0x200; " \
- "setexpr blkc ${blkc} + 1; " \
+ "setexpr blkc ${filesize} + 0x1ff; " \
+ "setexpr blkc ${blkc} / 0x200; " \
"if itest ${blkc} <= ${fdt_size}; then " \
"mmc write ${loadaddr} ${fdt_start} ${blkc}; " \
"fi; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${fdt_start} * " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
- "sf read ${${fdt_addr}} ${offset} ${size}; " \
+ "sf read ${fdt_addr} ${offset} ${size}; " \
"setenv size ; setenv offset\0" \
#define CONFIG_BOOTCOMMAND \
/* 128 MiB offset as in ARM related docu for linux suggested */
#define TQMA6_FDT_ADDRESS 0x18000000
+/* set to a resonable value, changeable by user */
+#define TQMA6_CMA_SIZE 160M
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"board=tqma6\0" \
"uimage=uImage\0" \
"uboot=u-boot.imx\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \
- "console=" CONSOLE_DEV "\0" \
+ "console=" CONSOLE_DEV "\0" \
+ "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
+ "rootfsmode=ro\0" \
+ "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \
"addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
"addfb=setenv bootargs ${bootargs} " \
"imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \
"mmcpart=2\0" \
"mmcblkdev=0\0" \
- "mmcargs=run addmmc addtty addfb\0" \
+ "mmcargs=run addmmc addtty addfb addcma\0" \
"addmmc=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk${mmcblkdev}p${mmcpart} rw rootwait\0" \
+ "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \
+ "rootwait\0" \
"mmcboot=echo Booting from mmc ...; " \
"setenv bootargs; " \
"run mmcargs; " \
"netdev=eth0\0" \
"rootpath=/srv/nfs/tqma6\0" \
"ipmode=static\0" \
- "netargs=run addnfs addip addtty addfb\0" \
+ "netargs=run addnfs addip addtty addfb addcma\0" \
"addnfs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath},v3,tcp;\0" \
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
/* Linux only */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc0,115200\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdtfile=undefined\0" \
"echo WARNING: Could not determine dtb to use; fi\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "ramdisk_addr_r=0x83000000\0" \
+ "ramdisk_addr_r=0x84000000\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
BOOTENV
#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
/* ARM Trusted Firmware */
#define BOOT_IMAGES \
- "second_image=bl1.bin\0" \
+ "second_image=unph_bl.bin\0" \
"third_image=fip.bin\0"
#else
#define BOOT_IMAGES \
--- /dev/null
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN A0 */
+#define CLK_IC_LMI0 0
+#define CLK_IC_LMI1 1
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU 0
+#define CLK_FDMA 1
+#define CLK_NAND 2
+#define CLK_HVA 3
+#define CLK_PROC_STFE 4
+#define CLK_PROC_TP 5
+#define CLK_RX_ICN_DMU 6
+#define CLK_RX_ICN_DISP_0 6
+#define CLK_RX_ICN_DISP_1 6
+#define CLK_RX_ICN_HVA 7
+#define CLK_RX_ICN_TS 7
+#define CLK_ICN_CPU 8
+#define CLK_TX_ICN_DMU 9
+#define CLK_TX_ICN_HVA 9
+#define CLK_TX_ICN_TS 9
+#define CLK_ICN_COMPO 9
+#define CLK_MMC_0 10
+#define CLK_MMC_1 11
+#define CLK_JPEGDEC 12
+#define CLK_ICN_REG 13
+#define CLK_TRACE_A9 13
+#define CLK_PTI_STM 13
+#define CLK_EXT2F_A9 13
+#define CLK_IC_BDISP_0 14
+#define CLK_IC_BDISP_1 15
+#define CLK_PP_DMU 16
+#define CLK_VID_DMU 17
+#define CLK_DSS_LPC 18
+#define CLK_ST231_AUD_0 19
+#define CLK_ST231_GP_0 19
+#define CLK_ST231_GP_1 20
+#define CLK_ST231_DMU 21
+#define CLK_ICN_LMI 22
+#define CLK_TX_ICN_DISP_0 23
+#define CLK_TX_ICN_DISP_1 23
+#define CLK_ICN_SBC 24
+#define CLK_STFE_FRC2 25
+#define CLK_ETH_PHY 26
+#define CLK_ETH_REF_PHYCLK 27
+#define CLK_FLASH_PROMIP 28
+#define CLK_MAIN_DISP 29
+#define CLK_AUX_DISP 30
+#define CLK_COMPO_DVP 31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0 0
+#define CLK_PCM_1 1
+#define CLK_PCM_2 2
+#define CLK_SPDIFF 3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP 0
+#define CLK_PIX_PIP 1
+#define CLK_PIX_GDP1 2
+#define CLK_PIX_GDP2 3
+#define CLK_PIX_GDP3 4
+#define CLK_PIX_GDP4 5
+#define CLK_PIX_AUX_DISP 6
+#define CLK_DENC 7
+#define CLK_PIX_HDDAC 8
+#define CLK_HDDAC 9
+#define CLK_SDDAC 10
+#define CLK_PIX_DVO 11
+#define CLK_DVO 12
+#define CLK_PIX_HDMI 13
+#define CLK_TMDS_HDMI 14
+#define CLK_REF_HDMIPHY 15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1 0
+#define CLK_TSOUT_0 1
+#define CLK_TSOUT_1 2
+#define CLK_MCHI 3
+#define CLK_VSENS_COMPO 4
+#define CLK_FRC1_REMOTE 5
+#define CLK_LPC_0 6
+#define CLK_LPC_1 7
+#endif
--- /dev/null
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES 32
+#define CLK_RX_ICN_HADES 33
+#define CLK_ICN_REG_16 34
+#define CLK_PP_HADES 35
+#define CLK_CLUST_HADES 36
+#define CLK_HWPE_HADES 37
+#define CLK_FC_HADES 38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER 4
+#define CLK_USB2_PHY 5
+
+#endif
--- /dev/null
+/*
+ * include/linux/irqchip/irq-st.h
+ *
+ * Copyright (C) 2014 STMicroelectronics All Rights Reserved
+ *
+ * Author: Lee Jones <lee.jones@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
+
+#define ST_IRQ_SYSCFG_EXT_0 0
+#define ST_IRQ_SYSCFG_EXT_1 1
+#define ST_IRQ_SYSCFG_EXT_2 2
+#define ST_IRQ_SYSCFG_CTI_0 3
+#define ST_IRQ_SYSCFG_CTI_1 4
+#define ST_IRQ_SYSCFG_PMU_0 5
+#define ST_IRQ_SYSCFG_PMU_1 6
+#define ST_IRQ_SYSCFG_pl310_L2 7
+#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF
+
+#define ST_IRQ_SYSCFG_EXT_1_INV 0x1
+#define ST_IRQ_SYSCFG_EXT_2_INV 0x2
+#define ST_IRQ_SYSCFG_EXT_3_INV 0x4
+
+#endif
--- /dev/null
+/*
+ * This header provides shared DT/Driver defines for ST's LPC device
+ *
+ * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
+ *
+ * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics
+ */
+
+#ifndef __DT_BINDINGS_ST_LPC_H__
+#define __DT_BINDINGS_ST_LPC_H__
+
+#define ST_LPC_MODE_RTC 0
+#define ST_LPC_MODE_WDT 1
+#define ST_LPC_MODE_CLKSRC 2
+
+#endif /* __DT_BINDINGS_ST_LPC_H__ */
--- /dev/null
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
+
+/* Powerdown requests control 0 */
+#define STIH407_EMISS_POWERDOWN 0
+#define STIH407_NAND_POWERDOWN 1
+
+/* Synp GMAC PowerDown */
+#define STIH407_ETH1_POWERDOWN 2
+
+/* Powerdown requests control 1 */
+#define STIH407_USB3_POWERDOWN 3
+#define STIH407_USB2_PORT1_POWERDOWN 4
+#define STIH407_USB2_PORT0_POWERDOWN 5
+#define STIH407_PCIE1_POWERDOWN 6
+#define STIH407_PCIE0_POWERDOWN 7
+#define STIH407_SATA1_POWERDOWN 8
+#define STIH407_SATA0_POWERDOWN 9
+
+/* Reset defines */
+#define STIH407_ETH1_SOFTRESET 0
+#define STIH407_MMC1_SOFTRESET 1
+#define STIH407_PICOPHY_SOFTRESET 2
+#define STIH407_IRB_SOFTRESET 3
+#define STIH407_PCIE0_SOFTRESET 4
+#define STIH407_PCIE1_SOFTRESET 5
+#define STIH407_SATA0_SOFTRESET 6
+#define STIH407_SATA1_SOFTRESET 7
+#define STIH407_MIPHY0_SOFTRESET 8
+#define STIH407_MIPHY1_SOFTRESET 9
+#define STIH407_MIPHY2_SOFTRESET 10
+#define STIH407_SATA0_PWR_SOFTRESET 11
+#define STIH407_SATA1_PWR_SOFTRESET 12
+#define STIH407_DELTA_SOFTRESET 13
+#define STIH407_BLITTER_SOFTRESET 14
+#define STIH407_HDTVOUT_SOFTRESET 15
+#define STIH407_HDQVDP_SOFTRESET 16
+#define STIH407_VDP_AUX_SOFTRESET 17
+#define STIH407_COMPO_SOFTRESET 18
+#define STIH407_HDMI_TX_PHY_SOFTRESET 19
+#define STIH407_JPEG_DEC_SOFTRESET 20
+#define STIH407_VP8_DEC_SOFTRESET 21
+#define STIH407_GPU_SOFTRESET 22
+#define STIH407_HVA_SOFTRESET 23
+#define STIH407_ERAM_HVA_SOFTRESET 24
+#define STIH407_LPM_SOFTRESET 25
+#define STIH407_KEYSCAN_SOFTRESET 26
+#define STIH407_USB2_PORT0_SOFTRESET 27
+#define STIH407_USB2_PORT1_SOFTRESET 28
+#define STIH407_ST231_AUD_SOFTRESET 29
+#define STIH407_ST231_DMU_SOFTRESET 30
+#define STIH407_ST231_GP0_SOFTRESET 31
+#define STIH407_ST231_GP1_SOFTRESET 32
+
+/* Picophy reset defines */
+#define STIH407_PICOPHY0_RESET 0
+#define STIH407_PICOPHY1_RESET 1
+#define STIH407_PICOPHY2_RESET 2
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
#ifdef CONFIG_PARTITION_TYPE_GUID
char type_guid[37]; /* type GUID as string, if exists */
#endif
+#ifdef CONFIG_DOS_PARTITION
+ uchar sys_ind; /* partition type */
+#endif
} disk_partition_t;
/* Misc _get_dev functions */
return EFI_SUCCESS;
}
-int efi_memory_init(void)
+__weak void efi_add_known_memory(void)
{
- unsigned long runtime_start, runtime_end, runtime_pages;
- unsigned long uboot_start, uboot_pages;
- unsigned long uboot_stack_size = 16 * 1024 * 1024;
int i;
/* Add RAM */
efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
false);
}
+}
+
+int efi_memory_init(void)
+{
+ unsigned long runtime_start, runtime_end, runtime_pages;
+ unsigned long uboot_start, uboot_pages;
+ unsigned long uboot_stack_size = 16 * 1024 * 1024;
+
+ efi_add_known_memory();
/* Add U-Boot */
uboot_start = (gd->start_addr_sp - uboot_stack_size) & ~EFI_PAGE_MASK;
void (*putc)(struct printf_info *info, char ch);
};
-void putc_normal(struct printf_info *info, char ch)
+static void putc_normal(struct printf_info *info, char ch)
{
putc(ch);
}
out_dgt(info, dgt);
}
-int _vprintf(struct printf_info *info, const char *fmt, va_list va)
+static int _vprintf(struct printf_info *info, const char *fmt, va_list va)
{
char ch;
char *p;
# Usage: $(call ld-ifversion, -ge, 22252, y)
ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4))
+# dtc-option
+# Usage: DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+dtc-option = $(call try-run,\
+ echo '/dts-v1/; / {};' | $(DTC) $(1),$(1),$(2))
+
######
###
endif
KBUILD_CFLAGS += $(warning)
+
+else
+
+# Disable noisy checks by default
+DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg)
+
endif
CONFIG_ARM_ARCH_CP15_ERRATA
CONFIG_ARM_ASM_UNIFIED
CONFIG_ARM_DCC
-CONFIG_ARM_ERRATA_430973
-CONFIG_ARM_ERRATA_454179
-CONFIG_ARM_ERRATA_621766
-CONFIG_ARM_ERRATA_716044
-CONFIG_ARM_ERRATA_742230
-CONFIG_ARM_ERRATA_743622
-CONFIG_ARM_ERRATA_751472
-CONFIG_ARM_ERRATA_761320
-CONFIG_ARM_ERRATA_773022
-CONFIG_ARM_ERRATA_774769
-CONFIG_ARM_ERRATA_794072
-CONFIG_ARM_ERRATA_798870
-CONFIG_ARM_ERRATA_801819
-CONFIG_ARM_ERRATA_826974
-CONFIG_ARM_ERRATA_828024
-CONFIG_ARM_ERRATA_829520
-CONFIG_ARM_ERRATA_833069
-CONFIG_ARM_ERRATA_833471
CONFIG_ARM_FREQ
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_ARM_PL180_MMCI
CONFIG_BFIN_TRUE_IDE
CONFIG_BFIN_WATCHDOG
CONFIG_BIOSEMU
-CONFIG_BITBANGMII
CONFIG_BITBANGMII_MULTI
CONFIG_BKUP_FLASH
CONFIG_BL1_OFFSET
CONFIG_BOARD_AXM
CONFIG_BOARD_BOOTCMD
CONFIG_BOARD_COMMON
-CONFIG_BOARD_EARLY_INIT_F
CONFIG_BOARD_EARLY_INIT_R
CONFIG_BOARD_ECC_SUPPORT
CONFIG_BOARD_EMAC_COUNT
CONFIG_BOARD_IS_OPENRD_BASE
CONFIG_BOARD_IS_OPENRD_CLIENT
CONFIG_BOARD_IS_OPENRD_ULTIMATE
-CONFIG_BOARD_LATE_INIT
CONFIG_BOARD_MEM_LIMIT
CONFIG_BOARD_NAME
CONFIG_BOARD_POSTCLK_INIT
CONFIG_CGU_CTL_VAL
CONFIG_CGU_DIV_VAL
CONFIG_CHAIN_BOOT_CMD
-CONFIG_CHAIN_OF_TRUST
CONFIG_CHARON
CONFIG_CHIP_SELECTS_PER_CTRL
CONFIG_CHIP_SELECT_QUAD_CAPABLE
CONFIG_CMD_FPGA_LOADP
CONFIG_CMD_FUSE
CONFIG_CMD_GETTIME
-CONFIG_CMD_GPT
CONFIG_CMD_GSC
CONFIG_CMD_HASH
CONFIG_CMD_HD44760
CONFIG_CMD_NAND_TRIMFFS
CONFIG_CMD_ONENAND
CONFIG_CMD_OTP
-CONFIG_CMD_PART
CONFIG_CMD_PCA953X
CONFIG_CMD_PCA953X_INFO
CONFIG_CMD_PCI
CONFIG_CMD_TSI148
CONFIG_CMD_UBIFS
CONFIG_CMD_UNIVERSE
-CONFIG_CMD_UNZIP
CONFIG_CMD_USB_STORAGE
CONFIG_CMD_UUID
CONFIG_CMD_ZBOOT
CONFIG_DA8XX_GPIO
CONFIG_DASA_SIM
CONFIG_DATA
-CONFIG_DAVINCI_MMC
-CONFIG_DAVINCI_MMC_SD1
CONFIG_DAVINCI_SPI
CONFIG_DBAU1000
CONFIG_DBAU1X00
CONFIG_DWC_AHSATA
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID
-CONFIG_DWMMC
CONFIG_DW_ALTDESCRIPTOR
CONFIG_DW_AXI_BURST_LEN
CONFIG_DW_GMAC_DEFAULT_DMA_PBL
CONFIG_ENABLE_36BIT_PHYS
CONFIG_ENABLE_MMU
CONFIG_ENABLE_MUST_CHECK
-CONFIG_ENABLE_VBOOT
CONFIG_ENABLE_WARN_DEPRECATED
CONFIG_ENC_SILENTLINK
CONFIG_ENV_ACCESS_IGNORE_FORCE
CONFIG_EXYNOS7420
CONFIG_EXYNOS_ACE_SHA
CONFIG_EXYNOS_DP
-CONFIG_EXYNOS_DWMMC
CONFIG_EXYNOS_FB
CONFIG_EXYNOS_MIPI_DSIM
CONFIG_EXYNOS_RELOCATE_CODE_BASE
CONFIG_FSL_DIU_FB
CONFIG_FSL_DMA
CONFIG_FSL_DSPI1
-CONFIG_FSL_ELBC
CONFIG_FSL_ESDHC
CONFIG_FSL_ESDHC_ADAPTER_IDENT
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
CONFIG_FSL_I2C_CUSTOM_DFSR
CONFIG_FSL_I2C_CUSTOM_FDR
-CONFIG_FSL_IFC
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_LAYERSCAPE
CONFIG_FSL_LBC
CONFIG_FSL_LINFLEXUART
CONFIG_FSL_MC9SDZ60
-CONFIG_FSL_MC_ENET
CONFIG_FSL_MEMAC
CONFIG_FSL_NFC_CHIPS
CONFIG_FSL_NFC_SPARE_SIZE
CONFIG_FTSDC010_BASE_LIST
CONFIG_FTSDC010_NUMBER
CONFIG_FTSDC010_SDIO
-CONFIG_FTSDC021_CLOCK
CONFIG_FTSDMC021
CONFIG_FTSDMC021_BASE
CONFIG_FTSMC020
CONFIG_HETROGENOUS_CLUSTERS
CONFIG_HIDE_LOGO_VERSION
CONFIG_HIGH_BATS
-CONFIG_HIKEY_DWMMC
CONFIG_HIKEY_GPIO
CONFIG_HIS_DRIVER
CONFIG_HITACHI_SP19X001_Z1A
CONFIG_IMA
CONFIG_IMAGE_FORMAT_LEGACY
CONFIG_IMX
-CONFIG_IMX31_PHYCORE_EET
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
CONFIG_IMX_NAND
CONFIG_M88E1111_PHY
CONFIG_M88E1112_PHY
CONFIG_M88E1141_PHY
-CONFIG_MACB
CONFIG_MACB0_PHY
CONFIG_MACB1_PHY
CONFIG_MACB2_PHY
CONFIG_MMC_SPI_BUS
CONFIG_MMC_SPI_CRC_ON
CONFIG_MMC_SPI_CS
-CONFIG_MMC_SPI_CS_EPGIO
CONFIG_MMC_SPI_MODE
CONFIG_MMC_SPI_SPEED
-CONFIG_MMC_SUNXI
CONFIG_MMC_SUNXI_SLOT
CONFIG_MMC_TRACE
CONFIG_MMU
CONFIG_MUSB_HOST
CONFIG_MV88E61XX_CPU_PORT
CONFIG_MV88E61XX_PHY_PORTS
-CONFIG_MV88E61XX_SWITCH
-CONFIG_MV88E6352_SWITCH
CONFIG_MVEBU_MMC
CONFIG_MVGBE
CONFIG_MVGBE_PORTS
CONFIG_MXC_GPIO
CONFIG_MXC_GPT_HCLK
CONFIG_MXC_MCI_REGS_BASE
-CONFIG_MXC_MMC
CONFIG_MXC_NAND_HWECC
CONFIG_MXC_NAND_IP_REGS_BASE
CONFIG_MXC_NAND_REGS_BASE
CONFIG_MXS_AUART
CONFIG_MXS_AUART_BASE
CONFIG_MXS_GPIO
-CONFIG_MXS_MMC
CONFIG_MXS_OCOTP
CONFIG_MXS_SPI
CONFIG_MX_CYCLIC
CONFIG_OMAP3_SPI_D0_D1_SWAPPED
CONFIG_OMAP3_ZOOM1
CONFIG_OMAP4430
-CONFIG_OMAP54X
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
CONFIG_OMAP_GPIO
-CONFIG_OMAP_HSMMC
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
CONFIG_OMAP_USB2PHY2_HOST
CONFIG_OMAP_USB3PHY1_HOST
CONFIG_PCIE_IMX
CONFIG_PCIE_IMX_PERST_GPIO
CONFIG_PCIE_IMX_POWER_GPIO
-CONFIG_PCIE_LAYERSCAPE
CONFIG_PCISLAVE
CONFIG_PCIX_CHECK
CONFIG_PCI_33M
CONFIG_PHY2_ADDR
CONFIG_PHY3_ADDR
CONFIG_PHYCORE_MPC5200B_TINY
-CONFIG_PHYLIB_10G
CONFIG_PHYSMEM
CONFIG_PHY_ADDR
-CONFIG_PHY_AQUANTIA
-CONFIG_PHY_ATHEROS
CONFIG_PHY_BASE_ADR
CONFIG_PHY_BCM5421S
-CONFIG_PHY_BROADCOM
CONFIG_PHY_CLK_FREQ
CONFIG_PHY_CLOCK_FREQ
CONFIG_PHY_CMD_DELAY
-CONFIG_PHY_CORTINA
-CONFIG_PHY_DAVICOM
CONFIG_PHY_DYNAMIC_ANEG
-CONFIG_PHY_ET1011C
CONFIG_PHY_ET1011C_TX_CLK_FIX
CONFIG_PHY_GIGE
CONFIG_PHY_ID
CONFIG_PHY_INTERFACE_MODE
CONFIG_PHY_IRAM_BASE
CONFIG_PHY_KSZ9031
-CONFIG_PHY_LXT
CONFIG_PHY_M88E1111
-CONFIG_PHY_MARVELL
CONFIG_PHY_MAX_ADDR
-CONFIG_PHY_MICREL
CONFIG_PHY_MICREL_KSZ9021
CONFIG_PHY_MICREL_KSZ9031
CONFIG_PHY_MODE_NEED_CHANGE
-CONFIG_PHY_NATSEMI
-CONFIG_PHY_REALTEK
CONFIG_PHY_RESET
CONFIG_PHY_RESET_DELAY
-CONFIG_PHY_SMSC
-CONFIG_PHY_TERANETICS
-CONFIG_PHY_TI
CONFIG_PHY_TYPE
-CONFIG_PHY_VITESSE
-CONFIG_PHY_XILINX
CONFIG_PHYx_ADDR
CONFIG_PICOSAM
CONFIG_PIGGY_MAC_ADRESS_OFFSET
CONFIG_SMSTP7_ENA
CONFIG_SMSTP8_ENA
CONFIG_SMSTP9_ENA
-CONFIG_SOCFPGA_DWMMC
-CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH
CONFIG_SOCFPGA_VIRTUAL_TARGET
CONFIG_SOCRATES
CONFIG_SOC_AU1000
CONFIG_SPL_PANIC_ON_RAW_IMAGE
CONFIG_SPL_PBL_PAD
CONFIG_SPL_PPAACT_ADDR
-CONFIG_SPL_RAM_DEVICE
CONFIG_SPL_RELOC_MALLOC_ADDR
CONFIG_SPL_RELOC_MALLOC_SIZE
CONFIG_SPL_RELOC_STACK
CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
-CONFIG_SYS_FSL_CLK
CONFIG_SYS_FSL_CLK_ADDR
CONFIG_SYS_FSL_CLUSTER_1_L2
CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
CONFIG_SYS_I2C_QIXIS_ADDR
CONFIG_SYS_I2C_RCAR
CONFIG_SYS_I2C_RTC_ADDR
-CONFIG_SYS_I2C_S3C24X0
CONFIG_SYS_I2C_S3C24X0_SLAVE
CONFIG_SYS_I2C_S3C24X0_SPEED
CONFIG_SYS_I2C_SH
CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
CONFIG_SYS_LS_MC_FW_IN_DDR
-CONFIG_SYS_LS_PPA_FW_ADDR
-CONFIG_SYS_LS_PPA_FW_IN_XIP
CONFIG_SYS_LS_PPA_FW_IN_xxx
CONFIG_SYS_M41T11_BASE_YEAR
CONFIG_SYS_M41T11_EXT_CENTURY_DATA
CONFIG_SYS_MCLINK_MAX
CONFIG_SYS_MCMEM0_VAL
CONFIG_SYS_MCMEM1_VAL
-CONFIG_SYS_MC_RSV_MEM_ALIGN
CONFIG_SYS_MDC1_PIN
CONFIG_SYS_MDCNFG_VAL
CONFIG_SYS_MDC_PIN
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
CONFIG_SYS_MMC_BASE
CONFIG_SYS_MMC_CD_PIN
CONFIG_SYS_MMC_CLK_OD
CONFIG_SYS_PCIE4_PHYS_SIZE
CONFIG_SYS_PCIE_ADDR_HIGH
CONFIG_SYS_PCIE_BASE
-CONFIG_SYS_PCIE_CFG0_PHYS_OFF
-CONFIG_SYS_PCIE_CFG0_SIZE
-CONFIG_SYS_PCIE_CFG1_PHYS_OFF
-CONFIG_SYS_PCIE_CFG1_SIZE
CONFIG_SYS_PCIE_INBOUND_BASE
-CONFIG_SYS_PCIE_IO_BUS
-CONFIG_SYS_PCIE_IO_PHYS_OFF
-CONFIG_SYS_PCIE_IO_SIZE
CONFIG_SYS_PCIE_MEMBASE
CONFIG_SYS_PCIE_MEMSIZE
-CONFIG_SYS_PCIE_MEM_BUS
-CONFIG_SYS_PCIE_MEM_PHYS_OFF
-CONFIG_SYS_PCIE_MEM_SIZE
CONFIG_SYS_PCIE_MMAP_SIZE
CONFIG_SYS_PCIE_NR_PORTS
CONFIG_SYS_PCIE_PHYS
CONFIG_TEGRA_GPU
CONFIG_TEGRA_KEYBOARD
CONFIG_TEGRA_LP0
-CONFIG_TEGRA_MMC
CONFIG_TEGRA_NAND
CONFIG_TEGRA_PMU
CONFIG_TEGRA_SLINK_CTRLS
CONFIG_X600
CONFIG_X86EMU_DEBUG
CONFIG_X86EMU_RAW_IO
-CONFIG_X86_64
-CONFIG_X86_BSWAP
CONFIG_X86_MRC_ADDR
CONFIG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
$(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \
-I$(srctree)/lib/libfdt \
-I$(srctree)/tools \
- -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
-DUSE_HOSTCC \
-D__KERNEL_STRICT_NAMES \
-D_GNU_SOURCE
subdir- += env
ifneq ($(CROSS_BUILD_TOOLS),)
-HOSTCC = $(CC)
+override HOSTCC = $(CC)
quiet_cmd_crosstools_strip = STRIP $^
cmd_crosstools_strip = $(STRIP) $^; touch $@
-#!/usr/bin/env python
+#!/usr/bin/env python2
# Copyright (c) 2016 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
line_feeder.unget()
- elif t0 == T_SELECT:
+ elif t0 == T_SELECT or t0 == T_IMPLY:
target = tokens.get_next()
stmt.referenced_syms.add(target)
T_OPTIONAL, T_PROMPT, T_DEFAULT,
T_BOOL, T_TRISTATE, T_HEX, T_INT, T_STRING,
T_DEF_BOOL, T_DEF_TRISTATE,
- T_SELECT, T_RANGE, T_OPTION, T_ALLNOCONFIG_Y, T_ENV,
- T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(39)
+ T_SELECT, T_IMPLY, T_RANGE, T_OPTION, T_ALLNOCONFIG_Y, T_ENV,
+ T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(40)
# The leading underscore before the function assignments below prevent pydoc
# from listing them. The constants could be hidden too, but they're fairly
"prompt": T_PROMPT, "default": T_DEFAULT, "bool": T_BOOL, "boolean": T_BOOL,
"tristate": T_TRISTATE, "int": T_INT, "hex": T_HEX, "def_bool": T_DEF_BOOL,
"def_tristate": T_DEF_TRISTATE, "string": T_STRING, "select": T_SELECT,
- "range": T_RANGE, "option": T_OPTION, "allnoconfig_y": T_ALLNOCONFIG_Y,
- "env": T_ENV, "defconfig_list": T_DEFCONFIG_LIST, "modules": T_MODULES,
+ "imply": T_IMPLY, "range": T_RANGE, "option": T_OPTION,
+ "allnoconfig_y": T_ALLNOCONFIG_Y, "env": T_ENV,
+ "defconfig_list": T_DEFCONFIG_LIST, "modules": T_MODULES,
"visible": T_VISIBLE}.get
# Strings to use for True and False
# fw_printenv is supposed to run on the target system, which means it should be
# built with cross tools. Although it may look weird, we only replace "HOSTCC"
# with "CC" here for the maximum code reuse of scripts/Makefile.host.
-HOSTCC = $(CC)
+override HOSTCC = $(CC)
# Compile for a hosted environment on the target
HOST_EXTRACFLAGS = $(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \
return -1;
}
- fstat(fileno(bin), &s);
+ if (fstat(fileno(bin), &s)) {
+ fprintf(stderr, "Cannot stat binary file %s\n",
+ binarye->binary.file);
+ goto err_close;
+ }
binhdrsz = sizeof(struct opt_hdr_v1) +
(binarye->binary.nargs + 2) * sizeof(uint32_t) +
fprintf(stderr,
"Could not read binary image %s\n",
binarye->binary.file);
- return -1;
+ goto err_close;
}
fclose(bin);
cur += sizeof(uint32_t);
return 0;
+
+err_close:
+ fclose(bin);
+
+ return -1;
}
#if defined(CONFIG_KWB_SECURE)
hdr_v0->srcaddr = hdr_v0->ext
? sizeof(struct kwb_header)
: sizeof(*hdr_v0);
- } else {
- /*
- * Subtract mkimage header size from destination address
- * as this header is not expected by the Marvell BootROM.
- * This way, the execution address is identical to the
- * one the image is compiled for (TEXT_BASE).
- */
- hdr->destaddr = hdr->destaddr - sizeof(struct image_header);
}
hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum;
toc++;
memset(toc, 0xff, sizeof(*toc));
- gph_set_header(gph, sbuf->st_size - OMAP_FILE_HDR_SIZE,
+ gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE,
params->addr, 0);
if (strncmp(params->imagename, "byteswap", 8) == 0) {
projects / u-boot / commitdiff