]> git.sur5r.net Git - u-boot/commitdiff
ipu_common: Let the MX6 IPU clock be calculated in run-time
authorFabio Estevam <fabio.estevam@nxp.com>
Wed, 6 Sep 2017 16:49:31 +0000 (13:49 -0300)
committerAnatolij Gustschin <agust@denx.de>
Mon, 11 Sep 2017 10:46:51 +0000 (12:46 +0200)
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz.

When running a SPL target, which supports multiple MX6 variants we cannot
properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as
such decision is done in build-time currently.

Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be
configured in run-time on mx6.

Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
[agust: fixed #endif in cgtqmx6eval.h]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
22 files changed:
drivers/video/ipu_common.c
include/configs/advantech_dms-ba16.h
include/configs/apalis_imx6.h
include/configs/aristainetos-common.h
include/configs/cgtqmx6eval.h
include/configs/cm_fx6.h
include/configs/colibri_imx6.h
include/configs/embestmx6boards.h
include/configs/ge_bx50v3.h
include/configs/gw_ventana.h
include/configs/imx6-engicam.h
include/configs/m53evk.h
include/configs/mx51evk.h
include/configs/mx53cx9020.h
include/configs/mx53loco.h
include/configs/mx6cuboxi.h
include/configs/mx6sabre_common.h
include/configs/nitrogen6x.h
include/configs/novena.h
include/configs/tbs2910.h
include/configs/wandboard.h
scripts/config_whitelist.txt

index f259fb9633212ba42b39d1efe5015fbcc5ac984d..96229da502bc13998721ccef733e4d93021b8302 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
 #include <div64.h>
 #include "ipu.h"
 #include "ipu_regs.h"
@@ -81,6 +82,11 @@ struct ipu_ch_param {
 
 #define IPU_SW_RST_TOUT_USEC   (10000)
 
+#define IPUV3_CLK_MX51         133000000
+#define IPUV3_CLK_MX53         200000000
+#define IPUV3_CLK_MX6Q         264000000
+#define IPUV3_CLK_MX6DL                198000000
+
 void clk_enable(struct clk *clk)
 {
        if (clk) {
@@ -196,7 +202,6 @@ static void clk_ipu_disable(struct clk *clk)
 
 static struct clk ipu_clk = {
        .name = "ipu_clk",
-       .rate = CONFIG_IPUV3_CLK,
 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        .enable_reg = (u32 *)(CCM_BASE_ADDR +
                offsetof(struct mxc_ccm_reg, CCGR5)),
@@ -476,6 +481,13 @@ int ipu_probe(void)
        g_pixel_clk[1] = &pixel_clk[1];
 
        g_ipu_clk = &ipu_clk;
+#if defined(CONFIG_MX51)
+       g_ipu_clk->rate = IPUV3_CLK_MX51;
+#elif defined(CONFIG_MX53)
+       g_ipu_clk->rate = IPUV3_CLK_MX53;
+#else
+       g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;
+#endif
        debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
        g_ldb_clk = &ldb_clk;
        debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
index 86302cf55f6886c5e6e15daff2ead04bb49b7ab3..09f470c6b56f4466eb97e32fb36630822a063a1e 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK                260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index a15f19dce23cdfcfbcabd9f7e0a7c4bfbaa6c52e..9022a9d7bb12c4b439340f0408dd7b2016765adf 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index d24d564d480a44e7fd63934b856a8e90b226c224..397afbb4089063c742bce64706b250036de54a28 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 198000000
 #define CONFIG_IMX_VIDEO_SKIP
 
 #define CONFIG_PWM_IMX
index 8f7f26b9edbba3aeae86d57f97dd86ab982d0a55..2e8993d7d4c6a0f743d1426165757ade909e301a 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#ifdef CONFIG_MX6DL
-#define CONFIG_IPUV3_CLK 198000000
-#else
-#define CONFIG_IPUV3_CLK 264000000
-#endif
 #define CONFIG_IMX_HDMI
 
 /* SATA */
index 2d6132df9b51e7efbac0cdd5ef36602a566578a2..e278961177b8ae1fe7327e0d01fcadffb9ac048f 100644 (file)
 
 /* Display */
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK          260000000
 #define CONFIG_IMX_HDMI
 
 #define CONFIG_SPLASH_SCREEN
index db71369706cb2ae61034ee3af2f904307d8e54f8..5fd9aab03cc6ba7d96f8101790d4603673faca4a 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index 245623049b4263deab293afc7200ae389b4af58d..3f128e67cd8e799a8187259a50bb0c346ee1849c 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
index 45f845b3788950481bea5cc3746c7e3ddbcfe80b..a0468d204b63c89487739b83d4d37a91c2621475 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index 9c26059a068eff1ae6fc0f812bc5578c49d8f05b..128a6e5aec6eddaae93200f41ec2486e5be483b5 100644 (file)
 /* Framebuffer and LCD */
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK          260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #define CONFIG_VIDEO_BMP_LOGO
index a1b70361560f2b5b174b7d98d28291c24631a7eb..c34dc30127a5906bdee47e9874313e6e6c70e6a2 100644 (file)
 
 /* Framebuffer */
 #ifdef CONFIG_VIDEO_IPUV3
-# define CONFIG_IPUV3_CLK              260000000
 # define CONFIG_IMX_VIDEO_SKIP
 
 # define CONFIG_SPLASH_SCREEN
index 74b627c31ef7181b0dee639a644a56006e3cb9d9..dcc12dd604548fe6697df9b5b1a8e37fdff00456 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-#define CONFIG_IPUV3_CLK               200000000
 #endif
 
 /*
index c89cb0f43b0f01a9105e2918081621625db5eb4e..3ecb92c27da83072027da3c083729eca0aa95fa2 100644 (file)
@@ -84,7 +84,6 @@
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       133000000
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
index d78a877d8ec7ea954a93cddce00fa835fda83a32..ccb1a4a60973d6c812aa7f5649ba3cd668474327 100644 (file)
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       200000000
 
 #endif /* __CONFIG_H */
index 45b9bbf403fc832ed2459773982246ee5194b36e..e973b3569850c279af36e287df26af1c9f89f8c9 100644 (file)
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       200000000
 
 #endif                         /* __CONFIG_H */
index a168577ee728670fdb5490d160fbe0ccfe65f9b4..4e12de1212249adfe24aa8cf73505925aaa2ae1b 100644 (file)
@@ -41,7 +41,6 @@
 
 /* Framebuffer */
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
index 036c76d950a4a3eec27babfb444b1602f972b4e8..f083dc8a93ff8352510c940582362ece4a849b4c 100644 (file)
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#ifdef CONFIG_MX6DL
-#define CONFIG_IPUV3_CLK 198000000
-#else
-#define CONFIG_IPUV3_CLK 264000000
-#endif
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
index d32d8f871a99d79e49f10b1a380b7ba3e1c32e25..520a52cbc6cf03a1dee38f1079c2b359cb02b904 100644 (file)
@@ -80,7 +80,6 @@
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
 #define CONFIG_BMP_16BPP
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
index be8c6911e63a175a66a84dd4f1780253dacdf0c6..4480aaffa0e317ef72e3904536d89d01b6528011 100644 (file)
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index f98bf9562b80986c301667120f6ad673fde9763a..849d4a6aecccce3ecae5d41e185039fced60bce1 100644 (file)
@@ -64,7 +64,6 @@
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
-#define CONFIG_IPUV3_CLK               260000000
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
index d9237d7b81b03138cc500ca1424c476c54d9de61..3ba4c29f6745cf74d70d97f8bd49d1b3f816e406 100644 (file)
@@ -71,7 +71,6 @@
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
index 9ce0c3f039ffa26e16b6e31897813ac42f13b590..4a0eae3633ee0ab6170fa91bd2af917748ae6613 100644 (file)
@@ -1119,7 +1119,6 @@ CONFIG_IPAM390_GPIO_BOOTMODE
 CONFIG_IPAM390_GPIO_LED_GREEN
 CONFIG_IPAM390_GPIO_LED_RED
 CONFIG_IPROC
-CONFIG_IPUV3_CLK
 CONFIG_IP_DEFRAG
 CONFIG_IRAM_BASE
 CONFIG_IRAM_END