]> git.sur5r.net Git - u-boot/commitdiff
ARM: uniphier: parse device tree to determine DRAM base and size
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Fri, 11 Sep 2015 11:17:49 +0000 (20:17 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 24 Sep 2015 15:27:53 +0000 (00:27 +0900)
Device tree specifies the available memory ranges in its "/memory"
node.  Use it to simplify the CONFIG defines.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/mach-uniphier/board_common.c
arch/arm/mach-uniphier/dram_init.c
include/configs/uniphier.h

index 5f2d5f6f5b9cdb2b3dc3e76ce55e2ecc69c0704f..967fa6c0865d47664dfb42cf24b12fbfc1a208af 100644 (file)
@@ -18,15 +18,3 @@ int board_init(void)
 
        return 0;
 }
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
-       DECLARE_GLOBAL_DATA_PTR;
-
-       gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
-       gd->bd->bi_dram[0].size  = CONFIG_SDRAM0_SIZE;
-       gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
-       gd->bd->bi_dram[1].size  = CONFIG_SDRAM1_SIZE;
-}
-#endif
index 4b8c938b5ead10b2362b2a7b956315e6cff6f42a..32cc448aeb5b3b71b2f40c696dbaa0b84ed1db7c 100644 (file)
@@ -1,16 +1,59 @@
 /*
- * Copyright (C) 2012-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+       int offset;
+
+       offset = fdt_path_offset(fdt, "/memory");
+       if (offset < 0)
+               return NULL;
+
+       return fdt_getprop(fdt, offset, "reg", lenp);
+}
 
 int dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+       const fdt32_t *val;
+       int len;
+
+       val = get_memory_reg_prop(gd->fdt_blob, &len);
+       if (len < sizeof(*val))
+               return -EINVAL;
+
+       gd->ram_size = fdt32_to_cpu(*(val + 1));
+
+       debug("DRAM size = %08lx\n", gd->ram_size);
 
        return 0;
 }
+
+void dram_init_banksize(void)
+{
+       const fdt32_t *val;
+       int len, i;
+
+       val = get_memory_reg_prop(gd->fdt_blob, &len);
+       if (len < 0)
+               return;
+
+       len /= sizeof(*val);
+       len /= 2;
+
+       for (i = 0; i < len; i++) {
+               gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
+               gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
+
+               debug("DRAM bank %d: start = %08lx, size = %08lx\n",
+                     i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+       }
+}
index 45b39c075e577a7ce5850680d7ea18b885ccce1a..a15838b172534c59d6b69ca07305c2de3393dc1e 100644 (file)
 /* Open Firmware flat tree */
 #define CONFIG_OF_LIBFDT
 
-/* Memory Size & Mapping */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SDRAM0_BASE
-
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
-/* Thre is no memory hole */
-#define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_SYS_SDRAM_SIZE  (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
-#else
+#define CONFIG_SYS_SDRAM_BASE          0x80000000
 #define CONFIG_NR_DRAM_BANKS           2
-#define CONFIG_SYS_SDRAM_SIZE  (CONFIG_SDRAM0_SIZE)
-#endif
 
 #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
        defined(CONFIG_MACH_PH1_SLD8)