]> git.sur5r.net Git - u-boot/commitdiff
am335x: Initial support for Silica Pengwyn board
authorLothar Felten <lothar.felten@gmail.com>
Fri, 31 Jan 2014 16:34:14 +0000 (17:34 +0100)
committerTom Rini <trini@ti.com>
Fri, 21 Feb 2014 18:54:57 +0000 (13:54 -0500)
This patch add support for the Silica Pengwyn board [1]
The board is based on a TI AM3354 CPU [2]
All jumpers removed it will boot from the SDcard, the console is on
UART1 accessible via the FDTI -> USB. The on board NAND flash is
supported and can act as boot medium, depending on jumper settings.
USB Host, USB Device and Ethernet are also provided but untested.

[1]
http://www.silica.com/product/silica-pengwyn-board.html
[2]
http://www.ti.com/product/am3354

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
[trini: Move CONFIG_BOARD_LATE_INIT into am335x_evm.h, drop unused
spi0_pin_mux from Pengwyn support]
Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/include/asm/arch-am33xx/ddr_defs.h
board/silica/pengwyn/Makefile [new file with mode: 0644]
board/silica/pengwyn/board.c [new file with mode: 0644]
board/silica/pengwyn/board.h [new file with mode: 0644]
board/silica/pengwyn/mux.c [new file with mode: 0644]
boards.cfg
include/configs/am335x_evm.h
include/configs/pengwyn.h [new file with mode: 0644]
include/configs/ti_am335x_common.h

index fbe599d1ab36444cc62ab38609a26dca2149a7e4..4d899528f5bc157fc0affd398670c4e33dce969b 100644 (file)
 #define MT41J128MJT125_PHY_FIFO_WE             0x100
 #define MT41J128MJT125_IOCTRL_VALUE            0x18B
 
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY      0x06
+#define MT41K128MJT187E_EMIF_TIM1              0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2              0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3              0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG             0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF             0x0000093B
+#define MT41K128MJT187E_ZQ_CFG                 0x50074BE4
+#define MT41K128MJT187E_RATIO                  0x40
+#define MT41K128MJT187E_INVERT_CLKOUT          0x1
+#define MT41K128MJT187E_RD_DQS                 0x3B
+#define MT41K128MJT187E_WR_DQS                 0x85
+#define MT41K128MJT187E_PHY_WR_DATA            0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE            0x100
+#define MT41K128MJT187E_IOCTRL_VALUE           0x18B
+
 /* Micron MT41J64M16JT-125 */
 #define MT41J64MJT125_EMIF_SDCFG               0x61C04A32
 
diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
new file mode 100644 (file)
index 0000000..c8b4f9a
--- /dev/null
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
+obj-y  := mux.o
+endif
+
+obj-y  += board.o
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
new file mode 100644 (file)
index 0000000..a553129
--- /dev/null
@@ -0,0 +1,207 @@
+/*
+ * board.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD)
+
+/* DDR3 RAM timings */
+static const struct ddr_data ddr3_data = {
+       .datardsratio0 = MT41K128MJT187E_RD_DQS,
+       .datawdsratio0 = MT41K128MJT187E_WR_DQS,
+       .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
+       .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+       .cmd0csratio = MT41K128MJT187E_RATIO,
+       .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+       .cmd1csratio = MT41K128MJT187E_RATIO,
+       .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+       .cmd2csratio = MT41K128MJT187E_RATIO,
+       .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+       .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
+       .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
+       .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
+       .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
+       .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
+       .zq_config = MT41K128MJT187E_ZQ_CFG,
+       .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
+                               PHY_EN_DYN_PWRDN,
+};
+
+const struct ctrl_ioregs ddr3_ioregs = {
+       .cm0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+       /* break into full u-boot on 'c' */
+       return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr_266 = {
+               266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_303 = {
+               303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_400 = {
+               400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+       /*
+        * The pengwyn board uses the TPS650250 PMIC  without I2C
+        * interface and will output the following fixed voltages:
+        * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
+        * VLDO1=1V8 (IO) VLDO2=1V8(IO)
+        * Vcore=1V1 is fixed, generated by TPS62231
+        */
+
+       /* Get the frequency */
+       dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+       /* Set CORE Frequencies to OPP100 */
+       do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+       /* 720MHz cpu, this might change on newer board revisions */
+       dpll_mpu_opp100.m = MPUPLL_M_720;
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+       /* future configs can return other clock settings */
+       return &dpll_ddr_303;
+}
+
+void set_uart_mux_conf(void)
+{
+       enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+       enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+       config_ddr(303, &ddr3_ioregs, &ddr3_data,
+                  &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif /* if CONFIG_SPL_BUILD */
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+       gpmc_init();
+       return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+       /* VTP can be added here */
+       return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+       {
+               .slave_reg_ofs  = 0x208,
+               .sliver_reg_ofs = 0xd80,
+               .phy_id         = 0,
+               .phy_if         = PHY_INTERFACE_MODE_MII,
+       },
+       {
+               .slave_reg_ofs  = 0x308,
+               .sliver_reg_ofs = 0xdc0,
+               .phy_id         = 1,
+               .phy_if         = PHY_INTERFACE_MODE_MII,
+       },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
+       .mdio_div               = 0xff,
+       .channels               = 8,
+       .cpdma_reg_ofs          = 0x800,
+       .slaves                 = 1,
+       .slave_data             = cpsw_slaves,
+       .ale_reg_ofs            = 0xd00,
+       .ale_entries            = 1024,
+       .host_port_reg_ofs      = 0x108,
+       .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
+       .mac_control            = (1 << 5),
+       .control                = cpsw_control,
+       .host_port_num          = 0,
+       .version                = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+       int rv, n = 0;
+       uint8_t mac_addr[6];
+       uint32_t mac_hi, mac_lo;
+
+       if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+               printf("<ethaddr> not set. Reading from E-fuse\n");
+               /* try reading mac address from efuse */
+               mac_lo = readl(&cdev->macid0l);
+               mac_hi = readl(&cdev->macid0h);
+               mac_addr[0] = mac_hi & 0xFF;
+               mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+               mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+               mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+               mac_addr[4] = mac_lo & 0xFF;
+               mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+               if (is_valid_ether_addr(mac_addr))
+                       eth_setenv_enetaddr("ethaddr", mac_addr);
+               else
+                       return n;
+       }
+
+       writel(MII_MODE_ENABLE, &cdev->miisel);
+
+       rv = cpsw_register(&cpsw_data);
+       if (rv < 0)
+               printf("Error %d registering CPSW switch\n", rv);
+       else
+               n += rv;
+       return n;
+}
+#endif /* if CONFIG_DRIVER_TI_CPSW */
diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h
new file mode 100644 (file)
index 0000000..05addf6
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * board.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#endif
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
new file mode 100644 (file)
index 0000000..c8be440
--- /dev/null
@@ -0,0 +1,98 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
+static struct module_pin_mux uart0_pin_mux[] = {
+       {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART0_RXD */
+       {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},              /* UART0_TXD */
+       {-1},
+};
+
+/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
+
+/* I2C pins C16(scl)/C17(sda) */
+static struct module_pin_mux i2c0_pin_mux[] = {
+       {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+                                       PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
+       {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+                                       PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
+       {-1},
+};
+
+/* MMC0 pins */
+static struct module_pin_mux mmc0_pin_mux[] = {
+       {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+       {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+       {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+       {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+       {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CLK */
+       {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_CMD */
+       {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},  /* MMC0_CD */
+       {-1},
+};
+
+/* MII pins */
+static struct module_pin_mux mii1_pin_mux[] = {
+       {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},       /* MII1_RXERR */
+       {OFFSET(mii1_txen), MODE(0)},                   /* MII1_TXEN */
+       {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},        /* MII1_RXDV */
+       {OFFSET(mii1_txd3), MODE(0)},                   /* MII1_TXD3 */
+       {OFFSET(mii1_txd2), MODE(0)},                   /* MII1_TXD2 */
+       {OFFSET(mii1_txd1), MODE(0)},                   /* MII1_TXD1 */
+       {OFFSET(mii1_txd0), MODE(0)},                   /* MII1_TXD0 */
+       {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},       /* MII1_TXCLK */
+       {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},       /* MII1_RXCLK */
+       {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},        /* MII1_RXD3 */
+       {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},        /* MII1_RXD2 */
+       {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},        /* MII1_RXD1 */
+       {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},        /* MII1_RXD0 */
+       {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+       {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
+       {-1},
+};
+
+/* NAND pins */
+static struct module_pin_mux nand_pin_mux[] = {
+       {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD0 */
+       {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD1 */
+       {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD2 */
+       {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD3 */
+       {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD4 */
+       {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD5 */
+       {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD6 */
+       {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD7 */
+       {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+       {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},   /* NAND_WPN */
+       {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},      /* NAND_CS0 */
+       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+       {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},   /* NAND_OE */
+       {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},       /* NAND_WEN */
+       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},  /* NAND_BE_CLE */
+       {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+       configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+       configure_module_pin_mux(i2c0_pin_mux);
+       configure_module_pin_mux(uart0_pin_mux);
+       configure_module_pin_mux(mii1_pin_mux);
+       configure_module_pin_mux(mmc0_pin_mux);
+       configure_module_pin_mux(nand_pin_mux);
+}
index 0e663d93a25d44b93d1e664959567096b878cb61..e917753259f0036e63558049f8f6a776b8ada748 100644 (file)
@@ -256,6 +256,7 @@ Active  arm         armv7          am33xx      phytec          pcm051
 Active  arm         armv7          am33xx      siemens         dxr2                dxr2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         pxm2                pxm2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         rut                 rut                                  -                                                                                                                                 Roger Meier <r.meier@siemens.com>
+Active  arm         armv7          am33xx      silica          pengwyn             pengwyn                              -                                                                                                                                 Lothar Felten <lothar.felten@gmail.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_boneblack                     am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT                                                                                         Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm                           am335x_evm:SERIAL1,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_nor                       am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR                                                                                          Tom Rini <trini@ti.com>
index 73a9adb293ec4f6853eb1ae815f722d1620740bb..96ae369c6aca3f7e97ab1c5d0738ebd4e8236b15 100644 (file)
@@ -20,6 +20,7 @@
 
 #define MACH_TYPE_TIAM335EVM           3589    /* Until the next sync */
 #define CONFIG_MACH_TYPE               MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
 
 /* Clock Defines */
 #define V_OSCK                         24000000  /* Clock output from T2 */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
new file mode 100644 (file)
index 0000000..5a55556
--- /dev/null
@@ -0,0 +1,208 @@
+/*
+ * pengwyn.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_PENGWYN_H
+#define __CONFIG_PENGWYN_H
+
+#define CONFIG_NAND
+#define CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX              1
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock Defines */
+#define V_OSCK                         24000000
+#define V_SCLK                         V_OSCK
+
+/* set env size */
+#define CONFIG_ENV_SIZE                        0x4000
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "loadaddr=0x80200000\0" \
+       "fdtaddr=0x80F80000\0" \
+       "bootpart=0:2\0" \
+       "bootdir=/boot\0" \
+       "bootfile=zImage\0" \
+       "fdtfile=am335x-pengwyn.dtb\0" \
+       "console=ttyO0,115200n8\0" \
+       "optargs=\0" \
+       "mmcdev=0\0" \
+       "mmcroot=/dev/mmcblk0p2 ro\0" \
+       "mmcrootfstype=ext4 rootwait\0" \
+       "rootpath=/export/rootfs\0" \
+       "nfsopts=nolock\0" \
+       "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+               "::off\0" \
+       "mmcargs=setenv bootargs console=${console} " \
+               "${optargs} " \
+               "root=${mmcroot} " \
+               "rootfstype=${mmcrootfstype}\0" \
+       "netargs=setenv bootargs console=${console} " \
+               "${optargs} " \
+               "root=/dev/nfs " \
+               "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+               "ip=dhcp\0" \
+       "bootenv=uEnv.txt\0" \
+       "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+       "importbootenv=echo Importing environment from mmc ...; " \
+               "env import -t $loadaddr $filesize\0" \
+       "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+       "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+       "mmcloados=run mmcargs; " \
+               "bootz ${loadaddr} - ${fdtaddr};\0" \
+       "mmcboot=mmc dev ${mmcdev}; " \
+               "if mmc rescan; then " \
+                       "echo SD/MMC found on device ${mmcdev};" \
+                       "if run loadbootenv; then " \
+                               "echo Loaded environment from ${bootenv};" \
+                               "run importbootenv;" \
+                       "fi;" \
+                       "if test -n $uenvcmd; then " \
+                               "echo Running uenvcmd ...;" \
+                               "run uenvcmd;" \
+                       "fi;" \
+                       "if run loadimage; then " \
+                               "run loadfdt;" \
+                               "run mmcloados;" \
+                       "fi;" \
+               "fi;\0" \
+       "netboot=echo Booting from network ...; " \
+               "setenv autoload no; " \
+               "dhcp; " \
+               "tftp ${loadaddr} ${bootfile}; " \
+               "tftp ${fdtaddr} ${fdtfile}; " \
+               "run netargs; " \
+               "bootz ${loadaddr} - ${fdtaddr}\0" \
+       "mtdids=" MTDIDS_DEFAULT "\0" \
+       "mtdparts=" MTDPARTS_DEFAULT "\0" \
+       "nandargs=setenv bootargs console=${console} " \
+               "${optargs} " \
+               "root=${nandroot} " \
+               "rootfstype=${nandrootfstype}\0" \
+       "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+       "nandrootfstype=ubifs rootwait=1\0" \
+       "nandboot=echo Booting from nand ...; " \
+               "run nandargs; " \
+               "nand read ${fdtaddr} u-boot-spl-os; " \
+               "nand read ${loadaddr} kernel; " \
+               "bootz ${loadaddr} - ${fdtaddr}\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+       "run mmcboot;" \
+       "run nandboot;"
+
+/* NS16550 Configuration: primary UART via FDTI */
+#define CONFIG_SYS_NS16550_COM1                0x44e09000
+#define CONFIG_BAUDRATE                        115200
+
+/* I2C Configuration */
+#define        CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING      "AM335x U-Boot SPL"
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT     (CONFIG_SYS_NAND_BLOCK_SIZE / \
+                                        CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS         { 2, 3, 4, 5, 6, 7, 8, 9, \
+                                        10, 11, 12, 13, 14, 15, 16, 17, \
+                                        18, 19, 20, 21, 22, 23, 24, 25, \
+                                        26, 27, 28, 29, 30, 31, 32, 33, \
+                                        34, 35, 36, 37, 38, 39, 40, 41, \
+                                        42, 43, 44, 45, 46, 47, 48, 49, \
+                                        50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE                512
+#define CONFIG_SYS_NAND_ECCBYTES       14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
+
+#define GPMC_NAND_ECC_LP_x8_LAYOUT     1
+#define MTDIDS_DEFAULT                 "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT               "mtdparts=omap2-nand.0:128k(SPL)," \
+                                       "128k(SPL.backup1)," \
+                                       "128k(SPL.backup2)," \
+                                       "128k(SPL.backup3),1792k(u-boot)," \
+                                       "128k(u-boot-spl-os)," \
+                                       "128k(u-boot-env),5m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW    2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE        MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#if defined(CONFIG_MUSB_HOST)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* Disable CPSW SPL support so we fit within the 101KiB limit. */
+#undef CONFIG_SPL_ETH_SUPPORT
+#endif
+
+/* Network */
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR                1
+#define CONFIG_PHY_RESET       1
+#define CONFIG_PHY_NATSEMI
+
+/* CPSW support */
+#define CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif /* ! __CONFIG_PENGWYN_H */
index 91f97dd0610f1d492c22685fcb110fe7b19d3698..7e9ca01cd5a4d766dafe786110f85ffdc1e55d09 100644 (file)
@@ -13,7 +13,6 @@
 #define __CONFIG_TI_AM335X_COMMON_H__
 
 #define CONFIG_AM33XX
-#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */