phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
};
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&avb {
groups = "scif_clk_a";
function = "scif_clk";
};
+
+ sdhi3_pins: sd2 {
+ groups = "sdhi3_data8", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins_uhs: sd2_uhs {
+ groups = "sdhi3_data8", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
};
&sdhi0 {
};
&sdhi3 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
bus-width = <8>;
+ mmc-hs200-1_8v;
non-removable;
status = "okay";
};
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0x58280000
+CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77970=y
eth->phydev = phydev;
- /* 10BASE is not supported for Ethernet AVB MAC */
- phydev->supported &= ~(SUPPORTED_10baseT_Full
- | SUPPORTED_10baseT_Half);
+ phydev->supported &= SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
+ SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause;
+
if (pdata->max_speed != 1000) {
- phydev->supported &= ~(SUPPORTED_1000baseT_Half
- | SUPPORTED_1000baseT_Full);
+ phydev->supported &= ~SUPPORTED_1000baseT_Full;
reg = phy_read(phydev, -1, MII_CTRL1000);
reg &= ~(BIT(9) | BIT(8));
phy_write(phydev, -1, MII_CTRL1000, reg);
ret = ravb_reset(dev);
if (ret)
- goto err;
+ return ret;
ravb_base_desc_init(eth);
ravb_tx_desc_init(eth);
ret = ravb_config(dev);
if (ret)
- goto err;
+ return ret;
/* Setting the control will start the AVB-DMAC process. */
writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
return 0;
-
-err:
- clk_disable(ð->clk);
- return ret;
}
static void ravb_stop(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct ravb_priv *eth = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
struct mii_dev *mdiodev;
void __iomem *iobase;
int ret;
if (ret < 0)
goto err_mdio_alloc;
- gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
- GPIOD_IS_OUT);
+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
+ if (!ret) {
+ gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
+ ð->reset_gpio, GPIOD_IS_OUT);
+ }
+
+ if (!dm_gpio_is_valid(ð->reset_gpio)) {
+ gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
+ GPIOD_IS_OUT);
+ }
mdiodev = mdio_alloc();
if (!mdiodev) {
struct eth_pdata *pdata = dev_get_platdata(udev);
struct sh_ether_priv *priv = dev_get_priv(udev);
struct sh_eth_dev *eth = &priv->shdev;
+ struct ofnode_phandle_args phandle_args;
struct mii_dev *mdiodev;
int ret;
if (ret < 0)
return ret;
- gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
- GPIOD_IS_OUT);
+ ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
+ if (!ret) {
+ gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
+ &priv->reset_gpio, GPIOD_IS_OUT);
+ }
+
+ if (!dm_gpio_is_valid(&priv->reset_gpio)) {
+ gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
+ GPIOD_IS_OUT);
+ }
mdiodev = mdio_alloc();
if (!mdiodev) {
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
{
- return sh_pfc_read_raw_reg(pfc->regs + reg, 32);
+ return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
}
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
if (pfc->info->unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
- sh_pfc_write_raw_reg(pfc->regs + reg, 32, data);
+ sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
}
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,